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Hi, in your SimpleO3 llc.cpp, each cache miss will issue a single read. So I assume each read is a 64 bytes read. However, I find that in many DDR configuration DQ = 16 and BL =16. So the read length should be 16 * 16 / 8 = 32 bytes. So I want to ask how does it guarantee each read is 64 bytes.
The text was updated successfully, but these errors were encountered:
Hi, in your SimpleO3 llc.cpp, each cache miss will issue a single read. So I assume each read is a 64 bytes read. However, I find that in many DDR configuration DQ = 16 and BL =16. So the read length should be 16 * 16 / 8 = 32 bytes. So I want to ask how does it guarantee each read is 64 bytes.
The text was updated successfully, but these errors were encountered: