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Hello. Does the prefetch address generated by Pythia sequentially access L1D, L2, LLC, and DRAM? I mean, does the prefetch address generated by Pythia access the cache and main memory in a traditional manner? #15

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szuhzw asked this question in Q&A
Hello. Does the prefetch address generated by Pythia sequentially access L1D, L2, LLC, and DRAM? I mean, does the prefetch address generated by Pythia access the cache and main memory in a traditional manner? #15
@szuhzw szuhzw
Dec 2, 2024 · 1 comment
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szuhzw
Dec 2, 2024

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rahulbera
Dec 6, 2024
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@szuhzw @rahulbera
Converted from issue

This discussion was converted from issue #14 on December 06, 2024 14:26.