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README.md
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This project aims to provide a learning platform for RISC-V and Rust.
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+```mermaid
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+flowchart LR
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+
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+hart[HART] --> ram(RAM)
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+hart --> csr(CSR)
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+hart -->|SBI| see[SEE]
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+see -..-> hart
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+```
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+### Glossary
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+| | Definition |
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+|------|----------------------------------|
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+| HART | Hardware Thread |
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+| CSR | Control and Status Registers |
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+| SBI | Supervisor Binary Interface |
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+| SEE | Supervisor Execution Environment |
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+| ISA | Instruction Set Architecture |
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+| M | Machine Mode |
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+| XLEN | RISC-V 32 or 64 flavour |
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## Development
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```
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