Skip to content

Commit f97bab6

Browse files
committed
Add a glossary
1 parent aef6b9d commit f97bab6

File tree

1 file changed

+22
-0
lines changed

1 file changed

+22
-0
lines changed

README.md

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,28 @@
22

33
This project aims to provide a learning platform for RISC-V and Rust.
44

5+
```mermaid
6+
flowchart LR
7+
8+
9+
hart[HART] --> ram(RAM)
10+
hart --> csr(CSR)
11+
hart -->|SBI| see[SEE]
12+
see -..-> hart
13+
```
14+
15+
### Glossary
16+
17+
| | Definition |
18+
|------|----------------------------------|
19+
| HART | Hardware Thread |
20+
| CSR | Control and Status Registers |
21+
| SBI | Supervisor Binary Interface |
22+
| SEE | Supervisor Execution Environment |
23+
| ISA | Instruction Set Architecture |
24+
| M | Machine Mode |
25+
| XLEN | RISC-V 32 or 64 flavour |
26+
527
## Development
628

729
```

0 commit comments

Comments
 (0)