Skip to content

Commit

Permalink
Revise formatting
Browse files Browse the repository at this point in the history
  • Loading branch information
BuJo committed Oct 3, 2023
1 parent 4beef54 commit 675a921
Show file tree
Hide file tree
Showing 2 changed files with 5 additions and 4 deletions.
1 change: 1 addition & 0 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ flowchart LR
* `SEE` is global
* `CSR`s are per `hart` (or per core)
* The `SEE` can control all `hart`s
* The device tree (`DTB`) is accessible via `RAM`

### Glossary

Expand Down
8 changes: 4 additions & 4 deletions src/ram.rs
Original file line number Diff line number Diff line change
Expand Up @@ -25,10 +25,10 @@ impl Ram {
pub fn write_word(&self, addr: usize, word: u32) -> Option<()> {
let mut shared = self.ram.write().unwrap();

*(shared.get_mut(addr)?)= (word & 0xFF) as u8;
*(shared.get_mut(addr+1)?) = ((word >> 8) & 0xFF) as u8;
*(shared.get_mut(addr+2)?) = ((word >> 16) & 0xFF) as u8;
*(shared.get_mut(addr+3)?) = ((word >> 24) & 0xFF) as u8;
*(shared.get_mut(addr)?) = (word & 0xFF) as u8;
*(shared.get_mut(addr + 1)?) = ((word >> 8) & 0xFF) as u8;
*(shared.get_mut(addr + 2)?) = ((word >> 16) & 0xFF) as u8;
*(shared.get_mut(addr + 3)?) = ((word >> 24) & 0xFF) as u8;

Some(())
}
Expand Down

0 comments on commit 675a921

Please sign in to comment.