diff --git a/src/bin/archtest.rs b/src/bin/archtest.rs
index c36fe6c..0b1a766 100644
--- a/src/bin/archtest.rs
+++ b/src/bin/archtest.rs
@@ -1,8 +1,8 @@
-use std::{env, fs};
 use std::fs::File;
 use std::io::Write;
 use std::ops::Range;
 use std::sync::Arc;
+use std::{env, fs};
 
 use object::{Object, ObjectSection, ObjectSymbol};
 
diff --git a/src/csr.rs b/src/csr.rs
index 0ffd97a..47f5728 100644
--- a/src/csr.rs
+++ b/src/csr.rs
@@ -69,12 +69,7 @@ impl IndexMut<usize> for Csr {
     }
 }
 
-
-const NAME_MAP: [(usize, &str); 2] = [
-    (MSCRATCH, "mscratch"),
-    (MTVEC, "mtvec"),
-];
-
+const NAME_MAP: [(usize, &str); 2] = [(MSCRATCH, "mscratch"), (MTVEC, "mtvec")];
 
 impl Csr {
     pub fn name(id: u32) -> &'static str {
diff --git a/src/dynbus.rs b/src/dynbus.rs
index 40866df..c97b5d4 100644
--- a/src/dynbus.rs
+++ b/src/dynbus.rs
@@ -20,7 +20,9 @@ unsafe impl Sync for DynBus {}
 
 impl DynBus {
     pub fn new() -> DynBus {
-        Self { devices: RwLock::new(vec![]) }
+        Self {
+            devices: RwLock::new(vec![]),
+        }
     }
 
     pub fn map(&mut self, device: impl Device + 'static, range: Range<usize>) {
@@ -36,7 +38,6 @@ impl Default for DynBus {
     }
 }
 
-
 impl Device for DynBus {
     fn write_word(&self, addr: usize, val: u32) -> Result<(), Fault> {
         let devices = self.devices.read().unwrap();
@@ -129,7 +130,6 @@ mod test {
         assert_eq!(err.is_ok(), true, "ram should write");
     }
 
-
     #[test]
     fn htif() {
         let htif = Htif::new();
diff --git a/src/hart.rs b/src/hart.rs
index 87fe70e..709e89a 100644
--- a/src/hart.rs
+++ b/src/hart.rs
@@ -270,7 +270,9 @@ impl<BT: Device> Hart<BT> {
                 rs2,
                 funct7: 0x00,
             } => {
-                let (val, _) = self.get_register(rs1).overflowing_shl(self.get_register(rs2));
+                let (val, _) = self
+                    .get_register(rs1)
+                    .overflowing_shl(self.get_register(rs2));
                 self.set_register(rd, val);
 
                 self.dbgins(ins, format!("sll\t{},{},{}", reg(rd), reg(rs1), reg(rs2)))
@@ -284,7 +286,9 @@ impl<BT: Device> Hart<BT> {
                 rs2,
                 funct7: 0x00,
             } => {
-                let (val, _) = self.get_register(rs1).overflowing_shr(self.get_register(rs2));
+                let (val, _) = self
+                    .get_register(rs1)
+                    .overflowing_shr(self.get_register(rs2));
                 self.set_register(rd, val);
 
                 self.dbgins(ins, format!("srl\t{},{},{}", reg(rd), reg(rs1), reg(rs2)))
@@ -298,7 +302,8 @@ impl<BT: Device> Hart<BT> {
                 rs2,
                 funct7: 0x20,
             } => {
-                let (val, _) = (self.get_register(rs1) as i32).overflowing_shr(self.get_register(rs2));
+                let (val, _) =
+                    (self.get_register(rs1) as i32).overflowing_shr(self.get_register(rs2));
                 self.set_register(rd, val as u32);
 
                 self.dbgins(ins, format!("sra\t{},{},{}", reg(rd), reg(rs1), reg(rs2)))
@@ -314,7 +319,9 @@ impl<BT: Device> Hart<BT> {
             } => {
                 let val = if (self.get_register(rs1) as i32) < (self.get_register(rs2) as i32) {
                     1
-                } else { 0 };
+                } else {
+                    0
+                };
                 self.set_register(rd, val as u32);
 
                 self.dbgins(ins, format!("slt\t{},{},{}", reg(rd), reg(rs1), reg(rs2)))
@@ -330,7 +337,9 @@ impl<BT: Device> Hart<BT> {
             } => {
                 let val = if self.get_register(rs1) < self.get_register(rs2) {
                     1
-                } else { 0 };
+                } else {
+                    0
+                };
                 self.set_register(rd, val as u32);
 
                 self.dbgins(ins, format!("sltu\t{},{},{}", reg(rd), reg(rs1), reg(rs2)))
@@ -408,7 +417,9 @@ impl<BT: Device> Hart<BT> {
                 rs1,
                 imm,
             } if ((imm as u16) >> 5) == 0x00 => {
-                let (val, _) = self.get_register(rs1).overflowing_shl((imm & 0b11111) as u32);
+                let (val, _) = self
+                    .get_register(rs1)
+                    .overflowing_shl((imm & 0b11111) as u32);
                 self.set_register(rd, val);
 
                 self.dbgins(
@@ -424,7 +435,10 @@ impl<BT: Device> Hart<BT> {
                 rs1,
                 imm,
             } if ((imm as u16) >> 5) == 0x00 => {
-                let val = self.get_register(rs1).overflowing_shr((imm & 0b11111) as u32).0;
+                let val = self
+                    .get_register(rs1)
+                    .overflowing_shr((imm & 0b11111) as u32)
+                    .0;
                 self.set_register(rd, val);
 
                 self.dbgins(
@@ -440,7 +454,9 @@ impl<BT: Device> Hart<BT> {
                 rs1,
                 imm,
             } if ((imm as u16) >> 5) == 0x20 => {
-                let val = (self.get_register(rs1) as i32).overflowing_shr((imm & 0b11111) as u32).0 as u32;
+                let val = (self.get_register(rs1) as i32)
+                    .overflowing_shr((imm & 0b11111) as u32)
+                    .0 as u32;
                 self.set_register(rd, val);
 
                 self.dbgins(
@@ -458,7 +474,9 @@ impl<BT: Device> Hart<BT> {
             } => {
                 let val = if (self.get_register(rs1) as i32) < (imm as i32) {
                     1
-                } else { 0 };
+                } else {
+                    0
+                };
                 self.set_register(rd, val);
 
                 self.dbgins(
@@ -476,7 +494,9 @@ impl<BT: Device> Hart<BT> {
             } => {
                 let val = if self.get_register(rs1) < (imm as u32) {
                     1
-                } else { 0 };
+                } else {
+                    0
+                };
                 self.set_register(rd, val);
 
                 self.dbgins(
@@ -667,7 +687,10 @@ impl<BT: Device> Hart<BT> {
                 imm,
             } => {
                 let target = self.pc.wrapping_add(imm as u32).wrapping_sub(4);
-                self.dbgins(ins, format!("bgltu\t{},{},{:x}", reg(rs1), reg(rs2), target));
+                self.dbgins(
+                    ins,
+                    format!("bgltu\t{},{},{:x}", reg(rs1), reg(rs2), target),
+                );
 
                 if self.get_register(rs1) < self.get_register(rs2) {
                     self.pc = target;
@@ -803,17 +826,29 @@ impl<BT: Device> Hart<BT> {
                 rd,
                 funct3: 0x1,
                 rs1,
-                imm
+                imm,
             } => {
                 if rd != 0 {
-                    eprintln!("CSR {} to {} = {:x}", Csr::name(imm as u32), reg(rd),self.get_register(rs1));
+                    eprintln!(
+                        "CSR {} to {} = {:x}",
+                        Csr::name(imm as u32),
+                        reg(rd),
+                        self.get_register(rs1)
+                    );
                     self.set_register(rd, self.csr[imm as usize]);
                 } else {
-                    eprintln!("CSR {} = {:x}", Csr::name(imm as u32), self.get_register(rs1));
+                    eprintln!(
+                        "CSR {} = {:x}",
+                        Csr::name(imm as u32),
+                        self.get_register(rs1)
+                    );
                 }
                 self.csr[imm as usize] = self.get_register(rs1);
 
-                self.dbgins(ins, format!("csrrw\t{},{},{}", reg(rd), Csr::name(imm as u32), reg(rs1)))
+                self.dbgins(
+                    ins,
+                    format!("csrrw\t{},{},{}", reg(rd), Csr::name(imm as u32), reg(rs1)),
+                )
             }
             // csrrs Atomic Read and Set Bits in CSR
             I {
@@ -821,21 +856,33 @@ impl<BT: Device> Hart<BT> {
                 rd,
                 funct3: 0x2,
                 rs1,
-                imm
+                imm,
             } => {
                 self.set_register(rd, self.csr[imm as usize]);
 
-
                 if rs1 != 0 {
-                    eprintln!("CSR {} to {} = {:x}->{:x}", Csr::name(imm as u32), reg(rd), self.csr[imm as usize],
-                              (self.csr[imm as usize] | self.get_register(rs1)));
+                    eprintln!(
+                        "CSR {} to {} = {:x}->{:x}",
+                        Csr::name(imm as u32),
+                        reg(rd),
+                        self.csr[imm as usize],
+                        (self.csr[imm as usize] | self.get_register(rs1))
+                    );
                     self.csr[imm as usize] |= self.get_register(rs1);
                 }
                 {
-                    eprintln!("CSR {} to {} = {:x}", Csr::name(imm as u32), reg(rd), self.csr[imm as usize]);
+                    eprintln!(
+                        "CSR {} to {} = {:x}",
+                        Csr::name(imm as u32),
+                        reg(rd),
+                        self.csr[imm as usize]
+                    );
                 }
 
-                self.dbgins(ins, format!("csrrs\t{},{},{}", reg(rd), Csr::name(imm as u32), reg(rs1)))
+                self.dbgins(
+                    ins,
+                    format!("csrrs\t{},{},{}", reg(rd), Csr::name(imm as u32), reg(rs1)),
+                )
             }
             // csrrc Atomic Read and Clear Bits in CSR
             I {
@@ -843,7 +890,7 @@ impl<BT: Device> Hart<BT> {
                 rd,
                 funct3: 0x3,
                 rs1,
-                imm
+                imm,
             } => {
                 if rd != 0 {
                     self.set_register(rd, self.csr[imm as usize]);
@@ -853,7 +900,10 @@ impl<BT: Device> Hart<BT> {
                     self.csr[imm as usize] &= !self.get_register(rs1);
                 }
 
-                self.dbgins(ins, format!("csrrc\t{},{},{}", reg(rd), Csr::name(imm as u32), reg(rs1)))
+                self.dbgins(
+                    ins,
+                    format!("csrrc\t{},{},{}", reg(rd), Csr::name(imm as u32), reg(rs1)),
+                )
             }
 
             _ => {
@@ -1298,11 +1348,7 @@ mod tests {
         let decoded = m.decode_instruction(ins).expect("decode").1;
         println!("{:032b} {}", ins, decoded);
         match decoded {
-            InstructionFormat::J {
-                opcode,
-                rd,
-                imm,
-            } => {
+            InstructionFormat::J { opcode, rd, imm } => {
                 assert_eq!(opcode, 0b1101111, "opcode wrong");
                 assert_eq!(rd, treg("zero"), "rd wrong");
                 assert_eq!(imm, 2052, "imm wrong");
diff --git a/src/lib.rs b/src/lib.rs
index 1cb1165..bd27847 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -1,12 +1,12 @@
 pub mod bus;
 pub mod csr;
+pub mod device;
 pub mod dt;
 pub mod dynbus;
 pub mod hart;
 pub mod htif;
+pub mod plic;
 pub mod ram;
 pub mod rom;
 pub mod rtc;
 pub mod see;
-pub mod device;
-pub mod plic;
diff --git a/src/main.rs b/src/main.rs
index 673322b..98cdaa9 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -1,6 +1,6 @@
-use std::{env, fs};
 use std::sync::Arc;
 use std::thread;
+use std::{env, fs};
 
 use rriscv::bus::Bus;
 use rriscv::hart::Hart;