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Format via cargo
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@BuJo
BuJo committed Oct 8, 2023
1 parent 7253892 commit 32f2942
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Showing 6 changed files with 82 additions and 41 deletions.
2 changes: 1 addition & 1 deletion src/bin/archtest.rs
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
use std::{env, fs};
use std::fs::File;
use std::io::Write;
use std::ops::Range;
use std::sync::Arc;
use std::{env, fs};

use object::{Object, ObjectSection, ObjectSymbol};

Expand Down
7 changes: 1 addition & 6 deletions src/csr.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -69,12 +69,7 @@ impl IndexMut<usize> for Csr {
}
}


const NAME_MAP: [(usize, &str); 2] = [
(MSCRATCH, "mscratch"),
(MTVEC, "mtvec"),
];

const NAME_MAP: [(usize, &str); 2] = [(MSCRATCH, "mscratch"), (MTVEC, "mtvec")];

impl Csr {
pub fn name(id: u32) -> &'static str {
Expand Down
6 changes: 3 additions & 3 deletions src/dynbus.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,9 @@ unsafe impl Sync for DynBus {}

impl DynBus {
pub fn new() -> DynBus {
Self { devices: RwLock::new(vec![]) }
Self {
devices: RwLock::new(vec![]),
}
}

pub fn map(&mut self, device: impl Device + 'static, range: Range<usize>) {
Expand All @@ -36,7 +38,6 @@ impl Default for DynBus {
}
}


impl Device for DynBus {
fn write_word(&self, addr: usize, val: u32) -> Result<(), Fault> {
let devices = self.devices.read().unwrap();
Expand Down Expand Up @@ -129,7 +130,6 @@ mod test {
assert_eq!(err.is_ok(), true, "ram should write");
}


#[test]
fn htif() {
let htif = Htif::new();
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102 changes: 74 additions & 28 deletions src/hart.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -270,7 +270,9 @@ impl<BT: Device> Hart<BT> {
rs2,
funct7: 0x00,
} => {
let (val, _) = self.get_register(rs1).overflowing_shl(self.get_register(rs2));
let (val, _) = self
.get_register(rs1)
.overflowing_shl(self.get_register(rs2));
self.set_register(rd, val);

self.dbgins(ins, format!("sll\t{},{},{}", reg(rd), reg(rs1), reg(rs2)))
Expand All @@ -284,7 +286,9 @@ impl<BT: Device> Hart<BT> {
rs2,
funct7: 0x00,
} => {
let (val, _) = self.get_register(rs1).overflowing_shr(self.get_register(rs2));
let (val, _) = self
.get_register(rs1)
.overflowing_shr(self.get_register(rs2));
self.set_register(rd, val);

self.dbgins(ins, format!("srl\t{},{},{}", reg(rd), reg(rs1), reg(rs2)))
Expand All @@ -298,7 +302,8 @@ impl<BT: Device> Hart<BT> {
rs2,
funct7: 0x20,
} => {
let (val, _) = (self.get_register(rs1) as i32).overflowing_shr(self.get_register(rs2));
let (val, _) =
(self.get_register(rs1) as i32).overflowing_shr(self.get_register(rs2));
self.set_register(rd, val as u32);

self.dbgins(ins, format!("sra\t{},{},{}", reg(rd), reg(rs1), reg(rs2)))
Expand All @@ -314,7 +319,9 @@ impl<BT: Device> Hart<BT> {
} => {
let val = if (self.get_register(rs1) as i32) < (self.get_register(rs2) as i32) {
1
} else { 0 };
} else {
0
};
self.set_register(rd, val as u32);

self.dbgins(ins, format!("slt\t{},{},{}", reg(rd), reg(rs1), reg(rs2)))
Expand All @@ -330,7 +337,9 @@ impl<BT: Device> Hart<BT> {
} => {
let val = if self.get_register(rs1) < self.get_register(rs2) {
1
} else { 0 };
} else {
0
};
self.set_register(rd, val as u32);

self.dbgins(ins, format!("sltu\t{},{},{}", reg(rd), reg(rs1), reg(rs2)))
Expand Down Expand Up @@ -408,7 +417,9 @@ impl<BT: Device> Hart<BT> {
rs1,
imm,
} if ((imm as u16) >> 5) == 0x00 => {
let (val, _) = self.get_register(rs1).overflowing_shl((imm & 0b11111) as u32);
let (val, _) = self
.get_register(rs1)
.overflowing_shl((imm & 0b11111) as u32);
self.set_register(rd, val);

self.dbgins(
Expand All @@ -424,7 +435,10 @@ impl<BT: Device> Hart<BT> {
rs1,
imm,
} if ((imm as u16) >> 5) == 0x00 => {
let val = self.get_register(rs1).overflowing_shr((imm & 0b11111) as u32).0;
let val = self
.get_register(rs1)
.overflowing_shr((imm & 0b11111) as u32)
.0;
self.set_register(rd, val);

self.dbgins(
Expand All @@ -440,7 +454,9 @@ impl<BT: Device> Hart<BT> {
rs1,
imm,
} if ((imm as u16) >> 5) == 0x20 => {
let val = (self.get_register(rs1) as i32).overflowing_shr((imm & 0b11111) as u32).0 as u32;
let val = (self.get_register(rs1) as i32)
.overflowing_shr((imm & 0b11111) as u32)
.0 as u32;
self.set_register(rd, val);

self.dbgins(
Expand All @@ -458,7 +474,9 @@ impl<BT: Device> Hart<BT> {
} => {
let val = if (self.get_register(rs1) as i32) < (imm as i32) {
1
} else { 0 };
} else {
0
};
self.set_register(rd, val);

self.dbgins(
Expand All @@ -476,7 +494,9 @@ impl<BT: Device> Hart<BT> {
} => {
let val = if self.get_register(rs1) < (imm as u32) {
1
} else { 0 };
} else {
0
};
self.set_register(rd, val);

self.dbgins(
Expand Down Expand Up @@ -667,7 +687,10 @@ impl<BT: Device> Hart<BT> {
imm,
} => {
let target = self.pc.wrapping_add(imm as u32).wrapping_sub(4);
self.dbgins(ins, format!("bgltu\t{},{},{:x}", reg(rs1), reg(rs2), target));
self.dbgins(
ins,
format!("bgltu\t{},{},{:x}", reg(rs1), reg(rs2), target),
);

if self.get_register(rs1) < self.get_register(rs2) {
self.pc = target;
Expand Down Expand Up @@ -803,47 +826,71 @@ impl<BT: Device> Hart<BT> {
rd,
funct3: 0x1,
rs1,
imm
imm,
} => {
if rd != 0 {
eprintln!("CSR {} to {} = {:x}", Csr::name(imm as u32), reg(rd),self.get_register(rs1));
eprintln!(
"CSR {} to {} = {:x}",
Csr::name(imm as u32),
reg(rd),
self.get_register(rs1)
);
self.set_register(rd, self.csr[imm as usize]);
} else {
eprintln!("CSR {} = {:x}", Csr::name(imm as u32), self.get_register(rs1));
eprintln!(
"CSR {} = {:x}",
Csr::name(imm as u32),
self.get_register(rs1)
);
}
self.csr[imm as usize] = self.get_register(rs1);

self.dbgins(ins, format!("csrrw\t{},{},{}", reg(rd), Csr::name(imm as u32), reg(rs1)))
self.dbgins(
ins,
format!("csrrw\t{},{},{}", reg(rd), Csr::name(imm as u32), reg(rs1)),
)
}
// csrrs Atomic Read and Set Bits in CSR
I {
opcode: 0b1110011,
rd,
funct3: 0x2,
rs1,
imm
imm,
} => {
self.set_register(rd, self.csr[imm as usize]);


if rs1 != 0 {
eprintln!("CSR {} to {} = {:x}->{:x}", Csr::name(imm as u32), reg(rd), self.csr[imm as usize],
(self.csr[imm as usize] | self.get_register(rs1)));
eprintln!(
"CSR {} to {} = {:x}->{:x}",
Csr::name(imm as u32),
reg(rd),
self.csr[imm as usize],
(self.csr[imm as usize] | self.get_register(rs1))
);
self.csr[imm as usize] |= self.get_register(rs1);
}
{
eprintln!("CSR {} to {} = {:x}", Csr::name(imm as u32), reg(rd), self.csr[imm as usize]);
eprintln!(
"CSR {} to {} = {:x}",
Csr::name(imm as u32),
reg(rd),
self.csr[imm as usize]
);
}

self.dbgins(ins, format!("csrrs\t{},{},{}", reg(rd), Csr::name(imm as u32), reg(rs1)))
self.dbgins(
ins,
format!("csrrs\t{},{},{}", reg(rd), Csr::name(imm as u32), reg(rs1)),
)
}
// csrrc Atomic Read and Clear Bits in CSR
I {
opcode: 0b1110011,
rd,
funct3: 0x3,
rs1,
imm
imm,
} => {
if rd != 0 {
self.set_register(rd, self.csr[imm as usize]);
Expand All @@ -853,7 +900,10 @@ impl<BT: Device> Hart<BT> {
self.csr[imm as usize] &= !self.get_register(rs1);
}

self.dbgins(ins, format!("csrrc\t{},{},{}", reg(rd), Csr::name(imm as u32), reg(rs1)))
self.dbgins(
ins,
format!("csrrc\t{},{},{}", reg(rd), Csr::name(imm as u32), reg(rs1)),
)
}

_ => {
Expand Down Expand Up @@ -1298,11 +1348,7 @@ mod tests {
let decoded = m.decode_instruction(ins).expect("decode").1;
println!("{:032b} {}", ins, decoded);
match decoded {
InstructionFormat::J {
opcode,
rd,
imm,
} => {
InstructionFormat::J { opcode, rd, imm } => {
assert_eq!(opcode, 0b1101111, "opcode wrong");
assert_eq!(rd, treg("zero"), "rd wrong");
assert_eq!(imm, 2052, "imm wrong");
Expand Down
4 changes: 2 additions & 2 deletions src/lib.rs
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Original file line number Diff line number Diff line change
@@ -1,12 +1,12 @@
pub mod bus;
pub mod csr;
pub mod device;
pub mod dt;
pub mod dynbus;
pub mod hart;
pub mod htif;
pub mod plic;
pub mod ram;
pub mod rom;
pub mod rtc;
pub mod see;
pub mod device;
pub mod plic;
2 changes: 1 addition & 1 deletion src/main.rs
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
use std::{env, fs};
use std::sync::Arc;
use std::thread;
use std::{env, fs};

use rriscv::bus::Bus;
use rriscv::hart::Hart;
Expand Down

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