From aaad4da8c3f0578f93fa85cefa6c433d07c1199e Mon Sep 17 00:00:00 2001 From: Austin Seipp Date: Tue, 24 Aug 2021 04:06:14 -0500 Subject: [PATCH 1/4] chore(comp): remove -v95 flag Remove all support code for Verilog 95 compatibility. Not only is V95 ancient, it also doesn't support necessary features like vendor-agnostic attributes, which will now see use. This also deletes the relevant tests, and simplifies a little of the pretty-printing code, too. Signed-off-by: Austin Seipp --- doc/user_guide/user_guide.tex | 10 ------ src/comp/AVerilogUtil.hs | 29 ++++------------- src/comp/Flags.hs | 1 - src/comp/FlagsDecode.hs | 6 ---- src/comp/GenABin.hs | 8 ++--- src/comp/Verilog.hs | 11 ++----- testsuite/bsc.options/bsc.help.out.expected | 1 - .../bsc.print-flags-raw.out.expected | 1 - testsuite/bsc.verilog/v95/Makefile | 7 ---- testsuite/bsc.verilog/v95/Param.v | 29 ----------------- testsuite/bsc.verilog/v95/ParamOrder.bsv | 32 ------------------- testsuite/bsc.verilog/v95/Signed.bsv | 14 -------- .../v95/sysParamOrder.out.expected | 3 -- .../bsc.verilog/v95/sysSigned.out.expected | 14 -------- .../v95/sysSigned.v95.out.expected | 14 -------- testsuite/bsc.verilog/v95/v95.exp | 20 ------------ 16 files changed, 14 insertions(+), 186 deletions(-) delete mode 100644 testsuite/bsc.verilog/v95/Makefile delete mode 100644 testsuite/bsc.verilog/v95/Param.v delete mode 100644 testsuite/bsc.verilog/v95/ParamOrder.bsv delete mode 100644 testsuite/bsc.verilog/v95/Signed.bsv delete mode 100644 testsuite/bsc.verilog/v95/sysParamOrder.out.expected delete mode 100644 testsuite/bsc.verilog/v95/sysSigned.out.expected delete mode 100644 testsuite/bsc.verilog/v95/sysSigned.v95.out.expected delete mode 100644 testsuite/bsc.verilog/v95/v95.exp diff --git a/doc/user_guide/user_guide.tex b/doc/user_guide/user_guide.tex index 10ff60c59..808c5dcc9 100644 --- a/doc/user_guide/user_guide.tex +++ b/doc/user_guide/user_guide.tex @@ -1627,14 +1627,12 @@ \subsection{Verilog back-end} back end. \index{-remove-unused-modules@\te{-remove-unused-modules} (compiler flag)} -\index{-v95@\te{-v95} (compiler flag)} \index{-remove-dollar@\te{-remove-dollar} (compiler flag)} \index{-unspecified-to@\te{-unspecified-to} (compiler flag)} \index{-Xv@\te{-Xv} (compiler flag)} \index{-verilog-filter@\te{-verilog-filter} (compiler flag)} \begin{centerboxverbatim} -remove-unused-modules remove unconnected modules from the Verilog --v95 generate strict Verilog 95 code -unspecified-to val remaining unspecified values are set to: 'X', '0', '1', 'Z', or 'A' -remove-dollar remove dollar signs from Verilog identifiers @@ -1649,14 +1647,6 @@ \subsection{Verilog back-end} should be used on modules undergoing synthesis, and not be used for testbench modules. -The {\bf\tt -v95} flag restricts the Verilog output to pure Verilog-95. -By default, the Verilog output uses features which are not in the -Verilog-95 standard. These features include passing module -parameters by name and use of the {\tt \$signed} system task for formatting -{\tt \$display} output. When the {\tt -v95} flag is turned on, uses -of these features are removed, but comments are left in the Verilog -indicating the parameter names or system tasks which were removed. - The {\bf\tt -unspecified-to val} flag defines the value which any remaining unspecified values should be tied to. The valid set of values are: {\tt X}, {\tt 0}, {\tt 1}, {\tt Z}, or {\tt A}, diff --git a/src/comp/AVerilogUtil.hs b/src/comp/AVerilogUtil.hs index 68cc9edaf..dc46372af 100644 --- a/src/comp/AVerilogUtil.hs +++ b/src/comp/AVerilogUtil.hs @@ -36,7 +36,7 @@ import Data.Maybe import FStringCompat(FString, getFString) import ErrorUtil -import Flags(Flags, readableMux, unSpecTo, v95, systemVerilogTasks) +import Flags(Flags, readableMux, unSpecTo, systemVerilogTasks) import PPrint import IntLit import Id @@ -56,7 +56,6 @@ import ForeignFunctions(ForeignFunction(..), ForeignFuncMap, isPoly, isMappedAVI import Util import IntegerUtil -import ListUtil(mapSnd, mapFst) import qualified Data.Map as M import qualified Data.Set as S @@ -70,8 +69,6 @@ import SCC(tsort) -- Define a structure which controls Verilog conversions data VConvtOpts = VConvtOpts { vco_unspec :: String, - vco_v95 :: Bool, - vco_v95_tasks :: [String], vco_readableMux :: Bool, vco_sv_tasks :: Bool } @@ -80,8 +77,6 @@ data VConvtOpts = VConvtOpts { flagsToVco :: Flags -> VConvtOpts flagsToVco flags = VConvtOpts { vco_unspec = unSpecTo flags, - vco_v95 = v95 flags, - vco_v95_tasks = ["$signed", "$unsigned"], vco_readableMux = readableMux flags, vco_sv_tasks = systemVerilogTasks flags } @@ -209,7 +204,7 @@ vForeignCall vco f@(AForeignCall aid taskid (c:es) ids resets) ffmap = if aid==idSVA then fcall es else foldr (Vif . mkNotEqualsReset . vExpr vco) fcall_body resets where - vtaskid = VId (vCommentTaskName vco taskid) aid Nothing + vtaskid = VId taskid aid Nothing (ids',es') = let lv = headOrErr "vForeignCall: missing return value" ids in case polyReturnType ffmap f of (Just ty) -> ([], (ASDef ty lv) : es) @@ -532,7 +527,7 @@ vDefMpd vco (ADef i t vi_module_name = mkVId n, vi_inst_name = VId inst_name i Nothing, -- these are size params, so default width of 32 is fine - vi_inst_params = Left (map (\x -> (Nothing,VEConst x)) is), + vi_inst_params = Left (map (\x -> VEConst x) is), vi_inst_ports = (zip (map (mkVId . fst) ips') (map (Just . (vExpr vco)) es') @@ -573,7 +568,7 @@ vDefMpd vco (ADef i_t t_t@(ATBit _) fn@(AFunCall {}) _) ffmap [ VMDecl $ VVDecl VDReg (vSize t_t) [VVar (vId i_t)] , VMStmt { vi_translate_off = True, vi_body = body } ] - where name = vCommentTaskName vco (vNameToTask (ae_funname fn)) + where name = vNameToTask (ae_funname fn) vtaskid = VId name (ae_objid fn) Nothing sensitivityList = nub (concatMap aIds (ae_args fn)) ev = foldr1 VEEOr (map (VEE . VEVar) sensitivityList) @@ -676,7 +671,7 @@ vExpr vco (APrim aid t p es) = VEOp (idToVId aid) (vExpr vco (APrim aid t p (ini -- vExpr vco (AMethCall t i m _) = internalError "AVerilog.vExpr: AMethCall with args" -- vExpr vco (AMethValue t i m) = VEVar (vMethId i m 1 MethodResult M.Empty) vExpr vco (AFunCall _ _ n isC es) = - let name = vCommentTaskName vco (if isC then vNameToTask n else n) + let name = if isC then vNameToTask n else n in VEFctCall (mkVId name) (map (vExpr vco) es) vExpr vco (ASInt idt (ATBit w) (IntLit _ b i)) = VEWConst (idToVId idt) w b i vExpr vco (ASReal _ _ r) = VEReal r @@ -759,9 +754,7 @@ muxInst vco pri s i es = ++ "Mux_" ++ itos (length es `div` 2)), vi_inst_name = i, - vi_inst_params = if ( vco_v95 vco ) - then Left [(Just $ getVIdString viWidth ,VEConst s)] - else Right [(viWidth, Just (VEConst s))], + vi_inst_params = Right [(viWidth, VEConst s)], vi_inst_ports = zip muxInputs (map Just es) } @@ -977,9 +970,7 @@ vState flags rewire_map avinst = vminst = VMInst { vi_module_name = vIdV (vName vi), vi_inst_name = vInstId v_inst_name, - vi_inst_params = if ( vco_v95 vco ) - then Left (mapFst (Just . getVIdString) paramExprs) - else Right (mapSnd Just paramExprs), + vi_inst_params = Right paramExprs, vi_inst_ports = map (updateArgPosition ifc_position . tildeHack) args } @@ -1084,14 +1075,8 @@ aIds _ = internalError("Unexpected pattern in AVerilog::aIds" -- ============================== --- replace non v95 task with their name enclosed in a comment -vCommentTaskName :: VConvtOpts -> String -> String -vCommentTaskName vco s | vco_v95 vco && elem s (vco_v95_tasks vco) = " /*" ++ s ++ "*/ " - | otherwise = s - -- create a Verilog task name from a foreign function name vNameToTask :: String -> String vNameToTask s = "$imported_" ++ s - -- ============================== diff --git a/src/comp/Flags.hs b/src/comp/Flags.hs index f0d3701b7..0abe20c70 100644 --- a/src/comp/Flags.hs +++ b/src/comp/Flags.hs @@ -140,7 +140,6 @@ data Flags = Flags { usePrelude :: Bool, useProvisoSAT :: Bool, stdlibNames :: Bool, - v95 :: Bool, vFlags :: [String], vdir :: Maybe String, vPathRaw :: [String], diff --git a/src/comp/FlagsDecode.hs b/src/comp/FlagsDecode.hs index fb85a35aa..5fad6f788 100644 --- a/src/comp/FlagsDecode.hs +++ b/src/comp/FlagsDecode.hs @@ -627,7 +627,6 @@ defaultFlags bluespecdir = Flags { usePrelude = True, useProvisoSAT = True, stdlibNames = False, - v95 = False, vFlags = [], vdir = Nothing, -- The vPath value will be produced from the raw value, @@ -1637,10 +1636,6 @@ externalFlags = [ (Toggle (\f x -> f {stdlibNames=x}) (showIfTrue stdlibNames), "the source file is from the standard library", Hidden)), - ("v95", - (Toggle (\f x -> f {v95=x}) (showIfTrue v95), - "generate strict Verilog 95 code", Visible)), - ("vdir", (Arg "dir" (\f s -> Left (f {vdir = Just s})) (Just (FRTMaybeString vdir)), "output directory for .v files", Visible)), @@ -1922,7 +1917,6 @@ showFlagsRaw flags = ("useNegate", show (useNegate flags)), ("usePrelude", show (usePrelude flags)), ("useProvisoSAT", show (useProvisoSAT flags)), - ("v95", show (v95 flags)), ("vFlags", show (vFlags flags)), ("vPath", show (vPath flags)), ("vPathRaw", show (vPathRaw flags)), diff --git a/src/comp/GenABin.hs b/src/comp/GenABin.hs index 3769b1f13..fe2473d8c 100644 --- a/src/comp/GenABin.hs +++ b/src/comp/GenABin.hs @@ -554,7 +554,7 @@ instance Bin Flags where a_100 a_101 a_102 a_103 a_104 a_105 a_106 a_107 a_108 a_109 a_110 a_111 a_112 a_113 a_114 a_115 a_116 a_117 a_118 a_119 a_120 a_121 a_122 a_123 a_124 a_125 a_126 a_127 a_128 a_129 - a_130 a_131 a_132) = + a_130 a_131) = do toBin a_000; toBin a_001; toBin a_002; toBin a_003; toBin a_004; toBin a_005; toBin a_006; toBin a_007; toBin a_008; toBin a_009; toBin a_010; toBin a_011; toBin a_012; toBin a_013; toBin a_014; @@ -581,7 +581,7 @@ instance Bin Flags where toBin a_115; toBin a_116; toBin a_117; toBin a_118; toBin a_119; toBin a_120; toBin a_121; toBin a_122; toBin a_123; toBin a_124; toBin a_125; toBin a_126; toBin a_127; toBin a_128; toBin a_129; - toBin a_130; toBin a_131; toBin a_132; + toBin a_130; toBin a_131; readBytes = do a_000 <- fromBin; a_001 <- fromBin; a_002 <- fromBin; a_003 <- fromBin; a_004 <- fromBin; a_005 <- fromBin; a_006 <- fromBin; a_007 <- fromBin; a_008 <- fromBin; a_009 <- fromBin; @@ -609,7 +609,7 @@ instance Bin Flags where a_115 <- fromBin; a_116 <- fromBin; a_117 <- fromBin; a_118 <- fromBin; a_119 <- fromBin; a_120 <- fromBin; a_121 <- fromBin; a_122 <- fromBin; a_123 <- fromBin; a_124 <- fromBin; a_125 <- fromBin; a_126 <- fromBin; a_127 <- fromBin; a_128 <- fromBin; a_129 <- fromBin; - a_130 <- fromBin; a_131 <- fromBin; a_132 <- fromBin + a_130 <- fromBin; a_131 <- fromBin return (Flags a_000 a_001 a_002 a_003 a_004 a_005 a_006 a_007 a_008 a_009 a_010 a_011 a_012 a_013 a_014 a_015 a_016 a_017 a_018 a_019 @@ -624,7 +624,7 @@ instance Bin Flags where a_100 a_101 a_102 a_103 a_104 a_105 a_106 a_107 a_108 a_109 a_110 a_111 a_112 a_113 a_114 a_115 a_116 a_117 a_118 a_119 a_120 a_121 a_122 a_123 a_124 a_125 a_126 a_127 a_128 a_129 - a_130 a_131 a_132) + a_130 a_131) -- ---------- diff --git a/src/comp/Verilog.hs b/src/comp/Verilog.hs index f6d79c6b1..c380d47d6 100644 --- a/src/comp/Verilog.hs +++ b/src/comp/Verilog.hs @@ -241,7 +241,7 @@ data VMItem | VMInst { vi_module_name :: VId, vi_inst_name :: VId, -- The string is for comments - vi_inst_params :: Either [(Maybe String,VExpr)] [(VId, Maybe VExpr)], + vi_inst_params :: Either [VExpr] [(VId, VExpr)], vi_inst_ports :: [(VId, Maybe VExpr)] } | VMAssign VLValue VExpr | VMStmt { vi_translate_off :: Bool, vi_body :: VStmt } @@ -306,11 +306,11 @@ instance PPrint VMItem where pPrint d p (VMInst mid iid pvs cs) = pPrint d 0 mid <> (case pvs of Left ps -> (if null ps then text "" - else text " #" <> pparen True (sepList (map (pv95params d) ps) comma )) + else text " #" <> pparen True (sepList (map (pPrint d 0) ps) comma)) Right ps -> (if null ps then text "" else text " #" <> pparen True (sepList (map (\ (i, me) -> text "." <> pPrint d 0 i <> - pparen True (case me of Just e -> pPrint d 0 e; Nothing -> text "")) ps) (text ",")))) <> + pparen True (pPrint d 0 me)) ps) (text ",")))) <> text "" <+> pPrint d 0 iid <> pparen True (sepList (map (\ (i, me) -> text "." <> pPrint d 0 i <> pparen True (case me of @@ -331,11 +331,6 @@ instance PPrint VMItem where ppComment cs $+$ pPrint d p stmt -pv95params :: PDetail -> (Maybe String, VExpr) -> Doc -pv95params d (Nothing,x) = pPrint d 0 x -pv95params d (Just "", x) = pPrint d 0 x -pv95params d (Just s,x) = text (" /*" ++ s ++ "*/ ") <> pPrint d 0 x - -- Decide where to place blank spaces between VMItems, by grouping -- them into a list of lists between which there should be a space. -- A space is added around instantiations and statements (initial and diff --git a/testsuite/bsc.options/bsc.help.out.expected b/testsuite/bsc.options/bsc.help.out.expected index 895b8aed7..88912fbf0 100644 --- a/testsuite/bsc.options/bsc.help.out.expected +++ b/testsuite/bsc.options/bsc.help.out.expected @@ -77,7 +77,6 @@ Compiler flags: -u check and recompile packages that are not up to date -unspecified-to val remaining unspecified values are set to: 'X', '0', '1', 'Z', or 'A' -v same as -verbose --v95 generate strict Verilog 95 code -vdir dir output directory for .v files -verbose be more talkative -verilog compile BSV generating Verilog file diff --git a/testsuite/bsc.options/bsc.print-flags-raw.out.expected b/testsuite/bsc.options/bsc.print-flags-raw.out.expected index 850c4a4f7..e00d69df0 100644 --- a/testsuite/bsc.options/bsc.print-flags-raw.out.expected +++ b/testsuite/bsc.options/bsc.print-flags-raw.out.expected @@ -119,7 +119,6 @@ Flags { useNegate = True, usePrelude = True, useProvisoSAT = True, - v95 = False, vFlags = [], vPath = [".","BLUESPECDIR/Libraries","BLUESPECDIR/Verilog"], vPathRaw = ["$DEFAULT_PATH"], diff --git a/testsuite/bsc.verilog/v95/Makefile b/testsuite/bsc.verilog/v95/Makefile deleted file mode 100644 index 48626d887..000000000 --- a/testsuite/bsc.verilog/v95/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# for "make clean" to work everywhere - -CONFDIR = $(realpath ../..) - -KEEPFILES = Param.v - -include $(CONFDIR)/clean.mk diff --git a/testsuite/bsc.verilog/v95/Param.v b/testsuite/bsc.verilog/v95/Param.v deleted file mode 100644 index ce14d0227..000000000 --- a/testsuite/bsc.verilog/v95/Param.v +++ /dev/null @@ -1,29 +0,0 @@ - -module Param ( CLK, - GO, - RDY_GO - ) ; - - // parameters are not in alphabetical or reverse order. - parameter C = 0 ; - parameter A = 0 ; - parameter B = 0 ; - - input CLK; - input GO; - output RDY_GO ; - - assign RDY_GO = 1'b1 ; - - always @ (posedge CLK ) - begin - if ( GO ) - begin - $display( "Parameter A is %d", A) ; - $display( "Parameter B is %d", B) ; - $display( "Parameter C is %d", C) ; - $finish(0); - end - end // always @ (posedge CLK ) - -endmodule // Param diff --git a/testsuite/bsc.verilog/v95/ParamOrder.bsv b/testsuite/bsc.verilog/v95/ParamOrder.bsv deleted file mode 100644 index b42938bc3..000000000 --- a/testsuite/bsc.verilog/v95/ParamOrder.bsv +++ /dev/null @@ -1,32 +0,0 @@ -package ParamOrder ; - -interface Ptest_Ifc; - method Action go() ; -endinterface - -import "BVI" Param = -module mkParam#(Integer a, Integer b, Integer c)( Ptest_Ifc) ; - - default_clock (CLK) ; - default_reset () ; - - // Parameter must be in same order as Verilog - parameter C = c; - parameter A = a; - parameter B = b; - - method go() enable(GO) ready(RDY_GO); - -endmodule - - -(* synthesize *) -module sysParamOrder() ; - Ptest_Ifc dut <- mkParam(1, 10 , 1000); - - rule fire ; - dut.go ; - endrule -endmodule - -endpackage diff --git a/testsuite/bsc.verilog/v95/Signed.bsv b/testsuite/bsc.verilog/v95/Signed.bsv deleted file mode 100644 index eada1ba65..000000000 --- a/testsuite/bsc.verilog/v95/Signed.bsv +++ /dev/null @@ -1,14 +0,0 @@ -// Test that the $signed functions are out of the generated code - -(* synthesize *) -module sysSigned() ; - - // Use signed data - Reg#(int) d <- mkReg(-4) ; - - rule check (True ) ; - d <= d + 1 ; - $display( "Showing signed data %0d", d ); - if ( d > 8 ) $finish(0) ; - endrule -endmodule diff --git a/testsuite/bsc.verilog/v95/sysParamOrder.out.expected b/testsuite/bsc.verilog/v95/sysParamOrder.out.expected deleted file mode 100644 index b06c09c0a..000000000 --- a/testsuite/bsc.verilog/v95/sysParamOrder.out.expected +++ /dev/null @@ -1,3 +0,0 @@ -Parameter A is 1 -Parameter B is 10 -Parameter C is 1000 diff --git a/testsuite/bsc.verilog/v95/sysSigned.out.expected b/testsuite/bsc.verilog/v95/sysSigned.out.expected deleted file mode 100644 index ee9aedf80..000000000 --- a/testsuite/bsc.verilog/v95/sysSigned.out.expected +++ /dev/null @@ -1,14 +0,0 @@ -Showing signed data -4 -Showing signed data -3 -Showing signed data -2 -Showing signed data -1 -Showing signed data 0 -Showing signed data 1 -Showing signed data 2 -Showing signed data 3 -Showing signed data 4 -Showing signed data 5 -Showing signed data 6 -Showing signed data 7 -Showing signed data 8 -Showing signed data 9 diff --git a/testsuite/bsc.verilog/v95/sysSigned.v95.out.expected b/testsuite/bsc.verilog/v95/sysSigned.v95.out.expected deleted file mode 100644 index a8a080685..000000000 --- a/testsuite/bsc.verilog/v95/sysSigned.v95.out.expected +++ /dev/null @@ -1,14 +0,0 @@ -Showing signed data 4294967292 -Showing signed data 4294967293 -Showing signed data 4294967294 -Showing signed data 4294967295 -Showing signed data 0 -Showing signed data 1 -Showing signed data 2 -Showing signed data 3 -Showing signed data 4 -Showing signed data 5 -Showing signed data 6 -Showing signed data 7 -Showing signed data 8 -Showing signed data 9 diff --git a/testsuite/bsc.verilog/v95/v95.exp b/testsuite/bsc.verilog/v95/v95.exp deleted file mode 100644 index b1270bdd1..000000000 --- a/testsuite/bsc.verilog/v95/v95.exp +++ /dev/null @@ -1,20 +0,0 @@ - -## Output should be the same regardless of v95 switch -test_veri_only_bsv_modules_options ParamOrder "" "" "" - -erase ParamOrder.bo -erase ParamOrder.bi -test_veri_only_bsv_modules_options ParamOrder "" "-v95" - -erase ParamOrder.bo -erase ParamOrder.bi -test_veri_only_bsv_modules_options ParamOrder "" "-no-v95" - - -test_veri_only_bsv_modules_options Signed "" "" -erase Signed.bo -erase Signed.bi -test_veri_only_bsv_modules_options Signed "" "-v95" "sysSigned.v95.out.expected" - - - From 5ee910fdb64e9e2a2dcc5836eb7fb6cf3b8b95fd Mon Sep 17 00:00:00 2001 From: Austin Seipp Date: Wed, 11 Mar 2020 19:12:06 -0500 Subject: [PATCH 2/4] fix(comp): use verilog attributes for {parallel, full}_case modifiers Verilog 2001 attributes are supported by Vivado, Quartus, and other tools (like Yosys) in order to parallel/full case semantics. Usage of synopsys-specific synthesis comments can be done better this way, and it suppresses a real warning with Yosys. This takes us *out* of v95 territory, because Verilog attributes were added in Verilog 2001. Currently, no fallback is supported, though this could be fixed. It's unclear to me how much this harms "portability" of the output Verilog code, but such features can always be added back later on demand... Signed-off-by: Austin Seipp --- doc/user_guide/user_guide.tex | 2 +- src/comp/Verilog.hs | 15 +++++++-------- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/doc/user_guide/user_guide.tex b/doc/user_guide/user_guide.tex index 808c5dcc9..c3a79c293 100644 --- a/doc/user_guide/user_guide.tex +++ b/doc/user_guide/user_guide.tex @@ -3642,7 +3642,7 @@ \subsubsection{Other signals} WILL_FIRE_RL_flip or reg_1 or WILL_FIRE_RL_sub or MUX_reg_2$write_1__VAL_3) begin - case (1'b1) // synopsys parallel_case + (* parallel_case *) case (1'b1) EN_start: reg_2$D_IN = start_num2; WILL_FIRE_RL_flip: reg_2$D_IN = reg_1; WILL_FIRE_RL_sub: reg_2$D_IN = MUX_reg_2$write_1__VAL_3; diff --git a/src/comp/Verilog.hs b/src/comp/Verilog.hs index c380d47d6..86ce98d96 100644 --- a/src/comp/Verilog.hs +++ b/src/comp/Verilog.hs @@ -430,13 +430,13 @@ instance PPrint VStmt where text "`endif // BSV_NO_INITIAL_BLOCKS" pPrint d p (VSeq ss) = text "begin" $+$ (text " " <> ppLines d ss) $+$ text "end" pPrint d p s@(Vcasex {}) = - (text "casex" <+> pparen True (pPrint d 0 (vs_case_expr s))) <+> - pprintCaseAttributes (vs_parallel s) (vs_full s) $+$ + pprintCaseAttributes (vs_parallel s) (vs_full s) <+> + (text "casex" <+> pparen True (pPrint d 0 (vs_case_expr s))) $+$ (text " " <> ppLines d (vs_case_arms s)) $+$ (text "endcase") pPrint d p s@(Vcase {}) = - (text "case" <+> pparen True (pPrint d 0 (vs_case_expr s))) <+> - pprintCaseAttributes (vs_parallel s) (vs_full s) $+$ + pprintCaseAttributes (vs_parallel s) (vs_full s) <+> + (text "case" <+> pparen True (pPrint d 0 (vs_case_expr s))) $+$ (text " " <> ppLines d (vs_case_arms s)) $+$ (text "endcase") pPrint d p (VAssign v e) = @@ -495,10 +495,9 @@ ppAs1 d i cs xs = text c1 <> ppAs1 d i c2 xs where pprintCaseAttributes :: Bool -> Bool -> Doc pprintCaseAttributes False False = empty -pprintCaseAttributes True False = mkSynthPragma "parallel_case" -pprintCaseAttributes False True = mkSynthPragma "full_case" -pprintCaseAttributes True True = mkSynthPragma "parallel_case full_case" - +pprintCaseAttributes True False = text "(* parallel_case *)" +pprintCaseAttributes False True = text "(* full_case *)" +pprintCaseAttributes True True = text "(* parallel_case, full_case *)" -- hack to check if expressions are known to be true or false isOne :: VExpr -> Bool From dea4ebbd7e7e311cc364e4c753a36affd40678b2 Mon Sep 17 00:00:00 2001 From: Austin Seipp Date: Tue, 24 Aug 2021 04:30:49 -0500 Subject: [PATCH 3/4] fix(comp): remove use of synopsys pragmas Modern tools such as Yosys hate ancient proprietary synopsys pragmas of the following, but handle them anyway: // synopsys translate_off .... // synopsys translate_on For translate pragmas, almost all reasonable synthesis tools support the following standardized alternative: `ifndef SYNTHESIS .... `endif // SYNTHESIS This moves all the compiler code to now emit the latter code, instead of the former. The former style currently still exists in the standard library's Verilog primitives. Signed-off-by: Austin Seipp --- doc/user_guide/user_guide.tex | 8 ++++---- src/comp/AVerilog.hs | 2 +- src/comp/AVerilogUtil.hs | 12 ++++++------ src/comp/InlineReg.hs | 6 +++--- src/comp/VPrims.hs | 2 +- src/comp/Verilog.hs | 28 ++++++++-------------------- 6 files changed, 23 insertions(+), 35 deletions(-) diff --git a/doc/user_guide/user_guide.tex b/doc/user_guide/user_guide.tex index c3a79c293..e95a4b2e9 100644 --- a/doc/user_guide/user_guide.tex +++ b/doc/user_guide/user_guide.tex @@ -3432,14 +3432,14 @@ \subsubsection{State elements} `ifdef BSV_NO_INITIAL_BLOCKS `else // no BSV_NO_INITIAL_BLOCKS -// synopsys translate_off +`ifndef SYNTHESIS initial begin reg_1 = 51'h2AAAAAAAAAAAA; reg_2 = 51'h2AAAAAAAAAAAA; reg_3 = 51'h2AAAAAAAAAAAA; end -// synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS \end{centerboxverbatim} % \caption{\label{reg-ver-fig}Generated Verilog for Register @@ -3662,7 +3662,7 @@ \subsubsection{Other signals} if (reg_2$EN) reg_2 <= `BSV_ASSIGNMENT_DELAY reg_2$D_IN; end - // synopsys translate_off + `ifndef SYNTHESIS `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS initial @@ -3671,7 +3671,7 @@ \subsubsection{Other signals} reg_2 = 51'h2AAAAAAAAAAAA; end `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on + `endif // SYNTHESIS endmodule // mkGCD \end{libverbatim} diff --git a/src/comp/AVerilog.hs b/src/comp/AVerilog.hs index c89efa05b..a38d45a08 100644 --- a/src/comp/AVerilog.hs +++ b/src/comp/AVerilog.hs @@ -711,7 +711,7 @@ groupForeignBlockDefs vDef foreign_block_ids ds = let (foreign_defs, other_defs) = findADefs foreign_block_ids ds (foreign_vdecls, foreign_vdefs) = mkVDeclsAndDefs vDef foreign_defs comment = ["declarations used by system tasks"] - foreign_vgroup = VMGroup { vg_translate_off = True + foreign_vgroup = VMGroup { vg_simulation_only = True , vg_body = [foreign_vdecls] } in case foreign_vdefs of diff --git a/src/comp/AVerilogUtil.hs b/src/comp/AVerilogUtil.hs index dc46372af..e298269d0 100644 --- a/src/comp/AVerilogUtil.hs +++ b/src/comp/AVerilogUtil.hs @@ -185,13 +185,13 @@ vForeignBlock vco ffmap ds (clks, fcalls) = foldr1 VEEOr (map (VEEposedge . (vExpr vco)) clks) mkVAssert :: VStmt -> VMItem mkVAssert (VTask _ es) = - VMStmt { vi_translate_off = True, + VMStmt { vi_simulation_only = True, vi_body = VAssert ass_sensitivity_list es } mkVAssert x = internalError("mkVAssert: " ++ (show x)) ass_stmts = map mkVAssert asses in -- put it together, with translate_off, since it is for sim only Just ((if null fcall_stmts then [] else - [VMStmt { vi_translate_off = True, + [VMStmt { vi_simulation_only = True, vi_body = always_stmt }])++ (if null asses then [] else ass_stmts), @@ -454,7 +454,7 @@ vDefMpd vco def@(ADef i t (APrim _ _ PrimPriMux es) _) _ = muxInst vco True (aSize t) (vPrimInstId "priorityMux_" i) (VEVar (vId i) : map (vExpr vco) es) ] else [ VMDecl $ VVDecl VDReg (vSize t) [VVar vi], - VMStmt { vi_translate_off = False, + VMStmt { vi_simulation_only = False, vi_body = Valways $ VAt ev $ Vcase { vs_case_expr = one, @@ -481,7 +481,7 @@ vDefMpd vco def@(ADef i t (APrim _ _ PrimMux es) _) _ = muxInst vco False (aSize t) (vPrimInstId "mux_" i) (VEVar (vId i) : map (vExpr vco) es) ] else [ VMDecl $ VVDecl VDReg (vSize t) [VVar vi], - VMStmt { vi_translate_off = False, + VMStmt { vi_simulation_only = False, vi_body = Valways $ VAt ev $ VSeq [ -- VAssign (VLId vi) (VEConst 0), -- no need to put default assignment @@ -537,7 +537,7 @@ vDefMpd vco (ADef i t vDefMpd vco defin@(ADef i t (APrim _ _ PrimCase es@(x:defarm:ces_t)) _) _ = [ VMDecl $ VVDecl VDReg (vSize t) [VVar vi], - VMStmt { vi_translate_off = False, + VMStmt { vi_simulation_only = False, vi_body = Valways $ VAt ev $ VSeq [Vcase { vs_case_expr = vExpr vco x, @@ -566,7 +566,7 @@ vDefMpd vco (ADef i_t t_t@(ATBit _) (ATaskValue {}) _) _ = vDefMpd vco (ADef i_t t_t@(ATBit _) fn@(AFunCall {}) _) ffmap | isImportedPolyReturn ffmap fn = [ VMDecl $ VVDecl VDReg (vSize t_t) [VVar (vId i_t)] - , VMStmt { vi_translate_off = True, vi_body = body } + , VMStmt { vi_simulation_only = True, vi_body = body } ] where name = vNameToTask (ae_funname fn) vtaskid = VId name (ae_objid fn) Nothing diff --git a/src/comp/InlineReg.hs b/src/comp/InlineReg.hs index f3e3891d5..77694fb67 100644 --- a/src/comp/InlineReg.hs +++ b/src/comp/InlineReg.hs @@ -122,7 +122,7 @@ vInlineN errh vco (clk, avis) = -- begin/end, even when there is only one item inside it stmt = Valways $ VAt ev $ VSeq body_items in - VMStmt { vi_translate_off = False, vi_body = stmt } + VMStmt { vi_simulation_only = False, vi_body = stmt } -- generate an always block for all RegA on the same clock and reset @@ -147,7 +147,7 @@ vInlineA vco ((clk, rstn), avis) = -- this body has no begin/end because it is an if-stmt; stmt = Valways $ VAt ev $ body_item in - VMStmt { vi_translate_off = False, vi_body = stmt } + VMStmt { vi_simulation_only = False, vi_body = stmt } -- Assign an initial (debug) value to all RegUN @@ -176,7 +176,7 @@ mkInitialAssignments flags avis = -- begin/end, even when there is only one item inside it stmt = Vinitial $ VSeq $ map mkInit avis in - [VMStmt { vi_translate_off = True, vi_body = stmt }] + [VMStmt { vi_simulation_only = True, vi_body = stmt }] -- make the conditional enable assignment to a register diff --git a/src/comp/VPrims.hs b/src/comp/VPrims.hs index 82f5da4ad..f57b7b349 100644 --- a/src/comp/VPrims.hs +++ b/src/comp/VPrims.hs @@ -36,7 +36,7 @@ vMuxP parallel n = VModule { vm_name = (mkVId ("Mux_" ++ itos n)), s n = mkVId ("s_" ++ itos n) outassign = VMAssign (VLId viOut) (VEVar viOutReg) regdecl = VMDecl (VVDecl VDReg rng [(VVar viOutReg)]) - body = VMStmt{ vi_translate_off = False, + body = VMStmt{ vi_simulation_only = False, vi_body = Valways $ VAt (slist (ins ++ (init sels))) $ Vcase { vs_case_expr = onetickbone, vs_case_arms = arms (VLId viOutReg) (zip (map VEVar sels) (map VEVar ins)), diff --git a/src/comp/Verilog.hs b/src/comp/Verilog.hs index 86ce98d96..f0bf2796a 100644 --- a/src/comp/Verilog.hs +++ b/src/comp/Verilog.hs @@ -62,18 +62,6 @@ import qualified Data.Generics as Generic --import Debug.Trace - --- string to start synthesis attributes with -synthesis_str :: String -synthesis_str = "synopsys" --- other possibilities ---synthesis_str = "synthesis" ---synthesis_str = "pragma" - -mkSynthPragma :: String -> Doc -mkSynthPragma s = text ("// " ++ synthesis_str ++ " " ++ s) - - -- VProgram -- * a list of modules -- * a comment for the entire file, not for any one module @@ -244,7 +232,7 @@ data VMItem vi_inst_params :: Either [VExpr] [(VId, VExpr)], vi_inst_ports :: [(VId, Maybe VExpr)] } | VMAssign VLValue VExpr - | VMStmt { vi_translate_off :: Bool, vi_body :: VStmt } + | VMStmt { vi_simulation_only :: Bool, vi_body :: VStmt } | VMComment VComment VMItem -- like VMComment but specific to inlined registers, -- to carry info for xref generation. @@ -252,7 +240,7 @@ data VMItem | VMRegGroup VId String VComment VMItem -- VMGroup: the lists of VMItem will be separated by empty lines; -- if no spaces needed, use a list of one list. - | VMGroup { vg_translate_off :: Bool, vg_body :: [[VMItem]]} + | VMGroup { vg_simulation_only :: Bool, vg_body :: [[VMItem]]} | VMFunction VFunction deriving (Eq, Show, Generic.Data, Generic.Typeable) @@ -296,9 +284,9 @@ instance Ord VMItem where instance PPrint VMItem where pPrint d p (VMDecl dcl) = pPrint d p dcl pPrint d p s@(VMStmt {}) - | vi_translate_off s = mkSynthPragma "translate_off" $$ - pPrint d p (vi_body s) $$ - mkSynthPragma "translate_on" + | vi_simulation_only s = text "`ifndef SYNTHESIS" $$ + pPrint d p (vi_body s) $$ + text "`endif // SYNTHESIS" | otherwise = pPrint d p (vi_body s) pPrint d p (VMAssign v e) = -- trace("Assignment :" ++ (ppReadable v) ++ " = " ++ (ppReadable e) ++ "\n") $ sep [text "assign" <+> pPrint d 45 v <+> text "=", @@ -319,9 +307,9 @@ instance PPrint VMItem where <> text ";" pPrint d p (VMComment cs stmt) = ppComment cs $+$ pPrint d p stmt pPrint d p g@(VMGroup _ stmtss) - | vg_translate_off g = mkSynthPragma "translate_off" $$ - vsepEmptyLine (map (ppLines d) stmtss) $$ - mkSynthPragma "translate_on" + | vg_simulation_only g = text "`ifndef SYNTHESIS" $$ + vsepEmptyLine (map (ppLines d) stmtss) $$ + text "`endif // SYNTHESIS" | otherwise = vsepEmptyLine (map (ppLines d) stmtss) pPrint d p (VMFunction f) = pPrint d p f From 39fddce9b08f94c1ebc8a766e88e72bd8ea1f23c Mon Sep 17 00:00:00 2001 From: Austin Seipp Date: Tue, 24 Aug 2021 04:53:22 -0500 Subject: [PATCH 4/4] chore(verilog): remove use of synopsys translate pragmas To align with previous changes in the compiler, this migrates all Verilog primitives to use `ifndef SYNOPSYS` instead of `translate_off` pragmas. Signed-off-by: Austin Seipp --- src/Verilog.Vivado/BRAM1.v | 4 ++-- src/Verilog.Vivado/BRAM1BE.v | 4 ++-- src/Verilog.Vivado/BRAM1BELoad.v | 4 ++-- src/Verilog.Vivado/BRAM1Load.v | 4 ++-- src/Verilog.Vivado/BRAM2.v | 4 ++-- src/Verilog.Vivado/BRAM2BE.v | 4 ++-- src/Verilog.Vivado/BRAM2BELoad.v | 4 ++-- src/Verilog.Vivado/BRAM2Load.v | 4 ++-- src/Verilog.Vivado/GatedClock.v | 4 ++-- src/Verilog.Vivado/MakeClock.v | 4 ++-- src/Verilog.Vivado/RegFile.v | 8 ++++---- src/Verilog.Vivado/SizedFIFO.v | 12 ++++++------ src/Verilog/BRAM1.v | 4 ++-- src/Verilog/BRAM1BE.v | 4 ++-- src/Verilog/BRAM1BELoad.v | 4 ++-- src/Verilog/BRAM1Load.v | 4 ++-- src/Verilog/BRAM2.v | 4 ++-- src/Verilog/BRAM2BE.v | 4 ++-- src/Verilog/BRAM2BELoad.v | 4 ++-- src/Verilog/BRAM2Load.v | 4 ++-- src/Verilog/CRegA5.v | 4 ++-- src/Verilog/CRegN5.v | 4 ++-- src/Verilog/CRegUN5.v | 4 ++-- src/Verilog/ClockDiv.v | 4 ++-- src/Verilog/ClockGen.v | 4 ++-- src/Verilog/ClockMux.v | 4 ++-- src/Verilog/ClockSelect.v | 4 ++-- src/Verilog/ConstrainedRandom.v | 4 ++-- src/Verilog/Counter.v | 4 ++-- src/Verilog/CrossingRegA.v | 4 ++-- src/Verilog/CrossingRegN.v | 4 ++-- src/Verilog/CrossingRegUN.v | 4 ++-- src/Verilog/DualPortRam.v | 4 ++-- src/Verilog/FIFO1.v | 8 ++++---- src/Verilog/FIFO10.v | 8 ++++---- src/Verilog/FIFO2.v | 8 ++++---- src/Verilog/FIFO20.v | 8 ++++---- src/Verilog/FIFOL1.v | 8 ++++---- src/Verilog/FIFOL10.v | 8 ++++---- src/Verilog/FIFOL2.v | 8 ++++---- src/Verilog/FIFOL20.v | 8 ++++---- src/Verilog/GatedClock.v | 4 ++-- src/Verilog/GatedClockDiv.v | 4 ++-- src/Verilog/GatedClockInverter.v | 4 ++-- src/Verilog/InitialReset.v | 4 ++-- src/Verilog/LatchCrossingReg.v | 4 ++-- src/Verilog/MakeClock.v | 4 ++-- src/Verilog/MakeReset.v | 4 ++-- src/Verilog/MakeReset0.v | 4 ++-- src/Verilog/MakeResetA.v | 4 ++-- src/Verilog/McpRegUN.v | 4 ++-- src/Verilog/ProbeCapture.v | 4 ++-- src/Verilog/ProbeMux.v | 4 ++-- src/Verilog/ProbeTrigger.v | 8 ++++---- src/Verilog/ProbeValue.v | 8 ++++---- src/Verilog/RegA.v | 4 ++-- src/Verilog/RegFile.v | 8 ++++---- src/Verilog/RegFileLoad.v | 4 ++-- src/Verilog/RegN.v | 4 ++-- src/Verilog/RegTwoA.v | 4 ++-- src/Verilog/RegTwoN.v | 4 ++-- src/Verilog/RegTwoUN.v | 4 ++-- src/Verilog/RegUN.v | 4 ++-- src/Verilog/ResetMux.v | 4 ++-- src/Verilog/SizedFIFO.v | 12 ++++++------ src/Verilog/SizedFIFO0.v | 8 ++++---- src/Verilog/SizedFIFOL.v | 12 ++++++------ src/Verilog/SizedFIFOL0.v | 8 ++++---- src/Verilog/SyncBit.v | 4 ++-- src/Verilog/SyncBit05.v | 4 ++-- src/Verilog/SyncBit1.v | 4 ++-- src/Verilog/SyncBit15.v | 4 ++-- src/Verilog/SyncFIFO.v | 8 ++++---- src/Verilog/SyncFIFO0.v | 8 ++++---- src/Verilog/SyncFIFO1.v | 8 ++++---- src/Verilog/SyncFIFO10.v | 8 ++++---- src/Verilog/SyncFIFOLevel.v | 12 ++++++------ src/Verilog/SyncFIFOLevel0.v | 12 ++++++------ src/Verilog/SyncHandshake.v | 4 ++-- src/Verilog/SyncPulse.v | 4 ++-- src/Verilog/SyncRegister.v | 4 ++-- src/Verilog/SyncReset.v | 4 ++-- src/Verilog/SyncResetA.v | 4 ++-- src/Verilog/UngatedClockMux.v | 4 ++-- src/Verilog/UngatedClockSelect.v | 4 ++-- 85 files changed, 226 insertions(+), 226 deletions(-) diff --git a/src/Verilog.Vivado/BRAM1.v b/src/Verilog.Vivado/BRAM1.v index 439192774..2cc3fe369 100644 --- a/src/Verilog.Vivado/BRAM1.v +++ b/src/Verilog.Vivado/BRAM1.v @@ -32,7 +32,7 @@ module BRAM1(CLK, `ifdef BSV_NO_INITIAL_BLOCKS `else - // synopsys translate_off +`ifndef SYNTHESIS integer i; initial begin : init_block @@ -42,7 +42,7 @@ module BRAM1(CLK, DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; end - // synopsys translate_on +`endif // SYNTHESIS `endif // !`ifdef BSV_NO_INITIAL_BLOCKS always @(posedge CLK) begin diff --git a/src/Verilog.Vivado/BRAM1BE.v b/src/Verilog.Vivado/BRAM1BE.v index 6303d445c..c543855b0 100644 --- a/src/Verilog.Vivado/BRAM1BE.v +++ b/src/Verilog.Vivado/BRAM1BE.v @@ -35,7 +35,7 @@ module BRAM1BE(CLK, `ifdef BSV_NO_INITIAL_BLOCKS `else - // synopsys translate_off +`ifndef SYNTHESIS initial begin : init_block integer i; @@ -45,7 +45,7 @@ module BRAM1BE(CLK, DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; end - // synopsys translate_on +`endif // SYNTHESIS `endif // !`ifdef BSV_NO_INITIAL_BLOCKS generate diff --git a/src/Verilog.Vivado/BRAM1BELoad.v b/src/Verilog.Vivado/BRAM1BELoad.v index e25b9f067..f15d2aa23 100644 --- a/src/Verilog.Vivado/BRAM1BELoad.v +++ b/src/Verilog.Vivado/BRAM1BELoad.v @@ -34,7 +34,7 @@ module BRAM1BELoad(CLK, reg [DATA_WIDTH-1:0] DO_R; reg [DATA_WIDTH-1:0] DO_R2; - // synopsys translate_off +`ifndef SYNTHESIS initial begin : init_block `ifdef BSV_NO_INITIAL_BLOCKS @@ -43,7 +43,7 @@ module BRAM1BELoad(CLK, DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; `endif // !`ifdef BSV_NO_INITIAL_BLOCKS end - // synopsys translate_on +`endif // SYNTHESIS initial begin : init_rom_block diff --git a/src/Verilog.Vivado/BRAM1Load.v b/src/Verilog.Vivado/BRAM1Load.v index d099daaa5..3fd805999 100644 --- a/src/Verilog.Vivado/BRAM1Load.v +++ b/src/Verilog.Vivado/BRAM1Load.v @@ -32,7 +32,7 @@ module BRAM1Load(CLK, reg [DATA_WIDTH-1:0] DO_R; reg [DATA_WIDTH-1:0] DO_R2; - // synopsys translate_off +`ifndef SYNTHESIS initial begin : init_block `ifdef BSV_NO_INITIAL_BLOCKS @@ -41,7 +41,7 @@ module BRAM1Load(CLK, DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; `endif // !`ifdef BSV_NO_INITIAL_BLOCKS end - // synopsys translate_on +`endif // SYNTHESIS initial begin : init_rom_block diff --git a/src/Verilog.Vivado/BRAM2.v b/src/Verilog.Vivado/BRAM2.v index 98d73891c..144ba6b3d 100644 --- a/src/Verilog.Vivado/BRAM2.v +++ b/src/Verilog.Vivado/BRAM2.v @@ -47,7 +47,7 @@ module BRAM2(CLKA, `ifdef BSV_NO_INITIAL_BLOCKS `else - // synopsys translate_off +`ifndef SYNTHESIS integer i; initial begin : init_block @@ -59,7 +59,7 @@ module BRAM2(CLKA, DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; end - // synopsys translate_on +`endif // SYNTHESIS `endif // !`ifdef BSV_NO_INITIAL_BLOCKS always @(posedge CLKA) begin diff --git a/src/Verilog.Vivado/BRAM2BE.v b/src/Verilog.Vivado/BRAM2BE.v index e612f45f9..bf13303f1 100644 --- a/src/Verilog.Vivado/BRAM2BE.v +++ b/src/Verilog.Vivado/BRAM2BE.v @@ -49,7 +49,7 @@ module BRAM2BE(CLKA, `ifdef BSV_NO_INITIAL_BLOCKS `else - // synopsys translate_off +`ifndef SYNTHESIS integer i; initial begin : init_block @@ -61,7 +61,7 @@ module BRAM2BE(CLKA, DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; end - // synopsys translate_on +`endif // SYNTHESIS `endif // !`ifdef BSV_NO_INITIAL_BLOCKS // PORT A diff --git a/src/Verilog.Vivado/BRAM2BELoad.v b/src/Verilog.Vivado/BRAM2BELoad.v index 40947fb31..6d3a99320 100644 --- a/src/Verilog.Vivado/BRAM2BELoad.v +++ b/src/Verilog.Vivado/BRAM2BELoad.v @@ -49,7 +49,7 @@ module BRAM2BELoad(CLKA, reg [DATA_WIDTH-1:0] DOB_R; reg [DATA_WIDTH-1:0] DOB_R2; - // synopsys translate_off +`ifndef SYNTHESIS initial begin : init_block `ifdef BSV_NO_INITIAL_BLOCKS @@ -60,7 +60,7 @@ module BRAM2BELoad(CLKA, DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; `endif // !`ifdef BSV_NO_INITIAL_BLOCKS end - // synopsys translate_on +`endif // SYNTHESIS initial begin : init_rom_block diff --git a/src/Verilog.Vivado/BRAM2Load.v b/src/Verilog.Vivado/BRAM2Load.v index c061d3486..70818e76e 100644 --- a/src/Verilog.Vivado/BRAM2Load.v +++ b/src/Verilog.Vivado/BRAM2Load.v @@ -47,7 +47,7 @@ module BRAM2Load(CLKA, reg [DATA_WIDTH-1:0] DOA_R2; reg [DATA_WIDTH-1:0] DOB_R2; - // synopsys translate_off +`ifndef SYNTHESIS initial begin : init_block `ifdef BSV_NO_INITIAL_BLOCKS @@ -58,7 +58,7 @@ module BRAM2Load(CLKA, DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; `endif // !`ifdef BSV_NO_INITIAL_BLOCKS end - // synopsys translate_on +`endif // SYNTHESIS initial begin : init_rom_block diff --git a/src/Verilog.Vivado/GatedClock.v b/src/Verilog.Vivado/GatedClock.v index e2ab40d8e..fad0d7866 100644 --- a/src/Verilog.Vivado/GatedClock.v +++ b/src/Verilog.Vivado/GatedClock.v @@ -79,14 +79,14 @@ module GatedClock( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin #0 ; new_gate = 1'b0 ; COND_reg = 1'b0 ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule // GatedClock diff --git a/src/Verilog.Vivado/MakeClock.v b/src/Verilog.Vivado/MakeClock.v index 331291b80..9d5688511 100644 --- a/src/Verilog.Vivado/MakeClock.v +++ b/src/Verilog.Vivado/MakeClock.v @@ -111,7 +111,7 @@ module MakeClock ( CLK, RST, `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin #0 ; current_clk = 1'b0 ; @@ -119,7 +119,7 @@ module MakeClock ( CLK, RST, new_gate = 1'b1 ; CLK_VAL_OUT = 1'b0; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog.Vivado/RegFile.v b/src/Verilog.Vivado/RegFile.v index f89e9e1b4..414d18e27 100644 --- a/src/Verilog.Vivado/RegFile.v +++ b/src/Verilog.Vivado/RegFile.v @@ -51,7 +51,7 @@ module RegFile(CLK, `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin : init_block integer i; // temporary for generate reset value @@ -59,7 +59,7 @@ module RegFile(CLK, arr[i] = {((data_width + 1)/2){2'b10}} ; end end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS @@ -75,7 +75,7 @@ module RegFile(CLK, assign D_OUT_4 = arr[ADDR_4]; assign D_OUT_5 = arr[ADDR_5]; - // synopsys translate_off +`ifndef SYNTHESIS always@(posedge CLK) begin : runtime_check reg enable_check; @@ -96,6 +96,6 @@ module RegFile(CLK, $display( "Warning: RegFile: %m -- Write Address port is out of bounds: %h", ADDR_IN ) ; end end - // synopsys translate_on +`endif // SYNTHESIS endmodule diff --git a/src/Verilog.Vivado/SizedFIFO.v b/src/Verilog.Vivado/SizedFIFO.v index a2a89444d..495eb8600 100644 --- a/src/Verilog.Vivado/SizedFIFO.v +++ b/src/Verilog.Vivado/SizedFIFO.v @@ -84,7 +84,7 @@ module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin : initial_block integer i; @@ -101,7 +101,7 @@ module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); arr[i] = D_OUT ; end end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS @@ -209,7 +209,7 @@ module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); end // else: !if(RST == `BSV_RESET_VALUE) end // always @ (posedge CLK) - // synopsys translate_off +`ifndef SYNTHESIS always@(posedge CLK) begin: error_checks reg deqerror, enqerror ; @@ -230,9 +230,9 @@ module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); end end end // block: error_checks - // synopsys translate_on +`endif // SYNTHESIS - // synopsys translate_off +`ifndef SYNTHESIS // Some assertions about parameter values initial begin : parameter_assertions @@ -254,6 +254,6 @@ module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); if ( ok == 0 ) $finish ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS endmodule diff --git a/src/Verilog/BRAM1.v b/src/Verilog/BRAM1.v index a6a5cda4f..a8253fd27 100644 --- a/src/Verilog/BRAM1.v +++ b/src/Verilog/BRAM1.v @@ -31,7 +31,7 @@ module BRAM1(CLK, `ifdef BSV_NO_INITIAL_BLOCKS `else - // synopsys translate_off +`ifndef SYNTHESIS integer i; initial begin : init_block @@ -41,7 +41,7 @@ module BRAM1(CLK, DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; end - // synopsys translate_on +`endif // SYNTHESIS `endif // !`ifdef BSV_NO_INITIAL_BLOCKS always @(posedge CLK) begin diff --git a/src/Verilog/BRAM1BE.v b/src/Verilog/BRAM1BE.v index 83ba84bad..909c9293c 100644 --- a/src/Verilog/BRAM1BE.v +++ b/src/Verilog/BRAM1BE.v @@ -34,7 +34,7 @@ module BRAM1BE(CLK, `ifdef BSV_NO_INITIAL_BLOCKS `else - // synopsys translate_off +`ifndef SYNTHESIS initial begin : init_block integer i; @@ -44,7 +44,7 @@ module BRAM1BE(CLK, DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; end - // synopsys translate_on +`endif // SYNTHESIS `endif // !`ifdef BSV_NO_INITIAL_BLOCKS generate diff --git a/src/Verilog/BRAM1BELoad.v b/src/Verilog/BRAM1BELoad.v index 0e3f1befa..40a50735a 100644 --- a/src/Verilog/BRAM1BELoad.v +++ b/src/Verilog/BRAM1BELoad.v @@ -33,7 +33,7 @@ module BRAM1BELoad(CLK, reg [DATA_WIDTH-1:0] DO_R; reg [DATA_WIDTH-1:0] DO_R2; - // synopsys translate_off +`ifndef SYNTHESIS initial begin : init_block `ifdef BSV_NO_INITIAL_BLOCKS @@ -42,7 +42,7 @@ module BRAM1BELoad(CLK, DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; `endif // !`ifdef BSV_NO_INITIAL_BLOCKS end - // synopsys translate_on +`endif // SYNTHESIS initial begin : init_rom_block diff --git a/src/Verilog/BRAM1Load.v b/src/Verilog/BRAM1Load.v index c514fe4f3..d08486bf3 100644 --- a/src/Verilog/BRAM1Load.v +++ b/src/Verilog/BRAM1Load.v @@ -31,7 +31,7 @@ module BRAM1Load(CLK, reg [DATA_WIDTH-1:0] DO_R; reg [DATA_WIDTH-1:0] DO_R2; - // synopsys translate_off +`ifndef SYNTHESIS initial begin : init_block `ifdef BSV_NO_INITIAL_BLOCKS @@ -40,7 +40,7 @@ module BRAM1Load(CLK, DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; `endif // !`ifdef BSV_NO_INITIAL_BLOCKS end - // synopsys translate_on +`endif // SYNTHESIS initial begin : init_rom_block diff --git a/src/Verilog/BRAM2.v b/src/Verilog/BRAM2.v index 417ee3148..e3a7cce40 100644 --- a/src/Verilog/BRAM2.v +++ b/src/Verilog/BRAM2.v @@ -46,7 +46,7 @@ module BRAM2(CLKA, `ifdef BSV_NO_INITIAL_BLOCKS `else - // synopsys translate_off +`ifndef SYNTHESIS integer i; initial begin : init_block @@ -58,7 +58,7 @@ module BRAM2(CLKA, DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; end - // synopsys translate_on +`endif // SYNTHESIS `endif // !`ifdef BSV_NO_INITIAL_BLOCKS always @(posedge CLKA) begin diff --git a/src/Verilog/BRAM2BE.v b/src/Verilog/BRAM2BE.v index 5452975cb..129b1347b 100644 --- a/src/Verilog/BRAM2BE.v +++ b/src/Verilog/BRAM2BE.v @@ -48,7 +48,7 @@ module BRAM2BE(CLKA, `ifdef BSV_NO_INITIAL_BLOCKS `else - // synopsys translate_off +`ifndef SYNTHESIS integer i; initial begin : init_block @@ -60,7 +60,7 @@ module BRAM2BE(CLKA, DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; end - // synopsys translate_on +`endif // SYNTHESIS `endif // !`ifdef BSV_NO_INITIAL_BLOCKS // PORT A diff --git a/src/Verilog/BRAM2BELoad.v b/src/Verilog/BRAM2BELoad.v index 0a1b6a622..9a4046dfe 100644 --- a/src/Verilog/BRAM2BELoad.v +++ b/src/Verilog/BRAM2BELoad.v @@ -48,7 +48,7 @@ module BRAM2BELoad(CLKA, reg [DATA_WIDTH-1:0] DOB_R; reg [DATA_WIDTH-1:0] DOB_R2; - // synopsys translate_off +`ifndef SYNTHESIS initial begin : init_block `ifdef BSV_NO_INITIAL_BLOCKS @@ -59,7 +59,7 @@ module BRAM2BELoad(CLKA, DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; `endif // !`ifdef BSV_NO_INITIAL_BLOCKS end - // synopsys translate_on +`endif // SYNTHESIS initial begin : init_rom_block diff --git a/src/Verilog/BRAM2Load.v b/src/Verilog/BRAM2Load.v index da1b20415..68a5c21cd 100644 --- a/src/Verilog/BRAM2Load.v +++ b/src/Verilog/BRAM2Load.v @@ -46,7 +46,7 @@ module BRAM2Load(CLKA, reg [DATA_WIDTH-1:0] DOA_R2; reg [DATA_WIDTH-1:0] DOB_R2; - // synopsys translate_off +`ifndef SYNTHESIS initial begin : init_block `ifdef BSV_NO_INITIAL_BLOCKS @@ -57,7 +57,7 @@ module BRAM2Load(CLKA, DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; `endif // !`ifdef BSV_NO_INITIAL_BLOCKS end - // synopsys translate_on +`endif // SYNTHESIS initial begin : init_rom_block diff --git a/src/Verilog/CRegA5.v b/src/Verilog/CRegA5.v index 12332a901..8b24eb1dc 100644 --- a/src/Verilog/CRegA5.v +++ b/src/Verilog/CRegA5.v @@ -92,11 +92,11 @@ module CRegA5 `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin Q_OUT_0 = {((width + 1)/2){2'b10}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog/CRegN5.v b/src/Verilog/CRegN5.v index 9ab2d713f..9118b14a4 100644 --- a/src/Verilog/CRegN5.v +++ b/src/Verilog/CRegN5.v @@ -92,11 +92,11 @@ module CRegN5 `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin Q_OUT_0 = {((width + 1)/2){2'b10}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog/CRegUN5.v b/src/Verilog/CRegUN5.v index 6b31f3312..6c8b48011 100644 --- a/src/Verilog/CRegUN5.v +++ b/src/Verilog/CRegUN5.v @@ -81,11 +81,11 @@ module CRegUN5 `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin Q_OUT_0 = {((width + 1)/2){2'b10}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog/ClockDiv.v b/src/Verilog/ClockDiv.v index 59b6cce86..37d1999d8 100644 --- a/src/Verilog/ClockDiv.v +++ b/src/Verilog/ClockDiv.v @@ -88,14 +88,14 @@ module ClockDiv(CLK_IN, RST, PREEDGE, CLK_OUT); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin #0 ; cntr = (upper - offset) ; PREEDGE = 0 ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS diff --git a/src/Verilog/ClockGen.v b/src/Verilog/ClockGen.v index 2c65c7713..0f9a481a8 100644 --- a/src/Verilog/ClockGen.v +++ b/src/Verilog/ClockGen.v @@ -17,7 +17,7 @@ module ClockGen(CLK_OUT); output CLK_OUT ; reg CLK_OUT ; - // synopsys translate_off +`ifndef SYNTHESIS // Clock is set to initValue for initDelay, and // then repeats set to value1 for value1Width @@ -58,7 +58,7 @@ module ClockGen(CLK_OUT); if ( ok == 0 ) $finish ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS endmodule // ClockGen diff --git a/src/Verilog/ClockMux.v b/src/Verilog/ClockMux.v index a369093dd..a67c19337 100644 --- a/src/Verilog/ClockMux.v +++ b/src/Verilog/ClockMux.v @@ -47,13 +47,13 @@ module ClockMux( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin #0 ; sel_reg = 1'b0 ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog/ClockSelect.v b/src/Verilog/ClockSelect.v index ede88a28f..da0a45185 100644 --- a/src/Verilog/ClockSelect.v +++ b/src/Verilog/ClockSelect.v @@ -106,7 +106,7 @@ module ClockSelect( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin #0 ; @@ -115,7 +115,7 @@ module ClockSelect( // initialize out of reset forcing the designer to call reset reset_hold = {(RSTDELAY + 1) {~ `BSV_RESET_VALUE}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog/ConstrainedRandom.v b/src/Verilog/ConstrainedRandom.v index 504ef0d60..c72947fdf 100644 --- a/src/Verilog/ConstrainedRandom.v +++ b/src/Verilog/ConstrainedRandom.v @@ -47,11 +47,11 @@ module ConstrainedRandom(CLK, RST, OUT, EN); end - // synopsys translate_off +`ifndef SYNTHESIS initial begin OUT = {((width + 1)/2){2'b10}} ; end - // synopsys translate_on +`endif // SYNTHESIS endmodule // ConstrainedRandom diff --git a/src/Verilog/Counter.v b/src/Verilog/Counter.v index fc51e0cfa..94df7a5e0 100644 --- a/src/Verilog/Counter.v +++ b/src/Verilog/Counter.v @@ -65,11 +65,11 @@ module Counter(CLK, `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin q_state = {((width + 1)/2){2'b10}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog/CrossingRegA.v b/src/Verilog/CrossingRegA.v index 45e1bb4f9..e39a1dd3e 100644 --- a/src/Verilog/CrossingRegA.v +++ b/src/Verilog/CrossingRegA.v @@ -40,11 +40,11 @@ module CrossingRegA(CLK, RST, Q_OUT, D_IN, EN); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin Q_OUT = {((width + 1)/2){2'b10}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog/CrossingRegN.v b/src/Verilog/CrossingRegN.v index 4ec51fe65..48c954358 100644 --- a/src/Verilog/CrossingRegN.v +++ b/src/Verilog/CrossingRegN.v @@ -39,11 +39,11 @@ module CrossingRegN(CLK, RST, Q_OUT, D_IN, EN); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin Q_OUT = {((width + 1)/2){2'b10}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog/CrossingRegUN.v b/src/Verilog/CrossingRegUN.v index 176f4be34..cb661b464 100644 --- a/src/Verilog/CrossingRegUN.v +++ b/src/Verilog/CrossingRegUN.v @@ -18,11 +18,11 @@ module CrossingRegUN(CLK, EN, D_IN, Q_OUT); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin Q_OUT = {((width + 1)/2){2'b10}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS diff --git a/src/Verilog/DualPortRam.v b/src/Verilog/DualPortRam.v index 77dd74dfd..45d25e080 100644 --- a/src/Verilog/DualPortRam.v +++ b/src/Verilog/DualPortRam.v @@ -49,7 +49,7 @@ module DualPortRam( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin : init_block integer i; // temporary for generate reset value @@ -58,7 +58,7 @@ module DualPortRam( memArray[i] = {((dataWidth + 1)/2){2'b10}} ; end end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog/FIFO1.v b/src/Verilog/FIFO1.v index 4d74b0c36..ccac94982 100644 --- a/src/Verilog/FIFO1.v +++ b/src/Verilog/FIFO1.v @@ -58,13 +58,13 @@ module FIFO1(CLK, `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin D_OUT = {((width + 1)/2) {2'b10}} ; empty_reg = 1'b0 ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS @@ -108,7 +108,7 @@ module FIFO1(CLK, end // else: !if(RST == `BSV_RESET_VALUE) end // always@ (posedge CLK or `BSV_RESET_EDGE RST) - // synopsys translate_off +`ifndef SYNTHESIS always@(posedge CLK) begin: error_checks reg deqerror, enqerror ; @@ -129,7 +129,7 @@ module FIFO1(CLK, end end // if (RST == ! `BSV_RESET_VALUE) end - // synopsys translate_on +`endif // SYNTHESIS endmodule diff --git a/src/Verilog/FIFO10.v b/src/Verilog/FIFO10.v index a5302cb29..b12c891a7 100644 --- a/src/Verilog/FIFO10.v +++ b/src/Verilog/FIFO10.v @@ -47,12 +47,12 @@ module FIFO10(CLK, `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin empty_reg = 1'b0; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS @@ -81,7 +81,7 @@ module FIFO10(CLK, end // else: !if(RST == `BSV_RESET_VALUE) end // always@ (posedge CLK or `BSV_RESET_EDGE RST) - // synopsys translate_off +`ifndef SYNTHESIS always@(posedge CLK) begin: error_checks reg deqerror, enqerror ; @@ -102,7 +102,7 @@ module FIFO10(CLK, end end // if (RST == ! `BSV_RESET_VALUE) end - // synopsys translate_on +`endif // SYNTHESIS endmodule diff --git a/src/Verilog/FIFO2.v b/src/Verilog/FIFO2.v index 070b51886..fe0fbd853 100644 --- a/src/Verilog/FIFO2.v +++ b/src/Verilog/FIFO2.v @@ -67,7 +67,7 @@ module FIFO2(CLK, `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin data0_reg = {((width + 1)/2) {2'b10}} ; @@ -75,7 +75,7 @@ module FIFO2(CLK, empty_reg = 1'b0; full_reg = 1'b1; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS always@(posedge CLK `BSV_ARESET_EDGE_META) @@ -127,7 +127,7 @@ module FIFO2(CLK, - // synopsys translate_off +`ifndef SYNTHESIS always@(posedge CLK) begin: error_checks reg deqerror, enqerror ; @@ -148,6 +148,6 @@ module FIFO2(CLK, end end end // always@ (posedge CLK) - // synopsys translate_on +`endif // SYNTHESIS endmodule diff --git a/src/Verilog/FIFO20.v b/src/Verilog/FIFO20.v index e06e42854..e334df4d1 100644 --- a/src/Verilog/FIFO20.v +++ b/src/Verilog/FIFO20.v @@ -48,13 +48,13 @@ module FIFO20(CLK, `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin empty_reg = 1'b0 ; full_reg = 1'b1 ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS always@(posedge CLK `BSV_ARESET_EDGE_META) @@ -84,7 +84,7 @@ module FIFO20(CLK, end // else: !if(RST == `BSV_RESET_VALUE) end // always@ (posedge CLK or `BSV_RESET_EDGE RST) - // synopsys translate_off +`ifndef SYNTHESIS always@(posedge CLK) begin: error_checks reg deqerror, enqerror ; @@ -105,6 +105,6 @@ module FIFO20(CLK, end end // if (RST == ! `BSV_RESET_VALUE) end - // synopsys translate_on +`endif // SYNTHESIS endmodule diff --git a/src/Verilog/FIFOL1.v b/src/Verilog/FIFOL1.v index 0d90cfb3d..1f7e65a66 100644 --- a/src/Verilog/FIFOL1.v +++ b/src/Verilog/FIFOL1.v @@ -58,13 +58,13 @@ module FIFOL1(CLK, `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin D_OUT <= `BSV_ASSIGNMENT_DELAY {((width + 1)/2) {2'b10}} ; empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS @@ -109,7 +109,7 @@ module FIFOL1(CLK, end // else: !if(RST == `BSV_RESET_VALUE) end // always@ (posedge CLK or `BSV_RESET_EDGE RST) - // synopsys translate_off +`ifndef SYNTHESIS always@(posedge CLK) begin: error_checks reg deqerror, enqerror ; @@ -127,6 +127,6 @@ module FIFOL1(CLK, $display( "Warning: FIFOL1: %m -- Enqueuing to a full fifo" ) ; end end - // synopsys translate_on +`endif // SYNTHESIS endmodule diff --git a/src/Verilog/FIFOL10.v b/src/Verilog/FIFOL10.v index c9752408e..5fe3db681 100644 --- a/src/Verilog/FIFOL10.v +++ b/src/Verilog/FIFOL10.v @@ -39,12 +39,12 @@ module FIFOL10(CLK, RST, ENQ, FULL_N, DEQ, EMPTY_N, CLR); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin empty_reg = 1'b0 ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS @@ -71,7 +71,7 @@ module FIFOL10(CLK, RST, ENQ, FULL_N, DEQ, EMPTY_N, CLR); end // else: !if(RST == `BSV_RESET_VALUE) end // always@ (posedge CLK or `BSV_RESET_EDGE RST) - // synopsys translate_off +`ifndef SYNTHESIS always@(posedge CLK) begin: error_checks reg deqerror, enqerror ; @@ -89,7 +89,7 @@ module FIFOL10(CLK, RST, ENQ, FULL_N, DEQ, EMPTY_N, CLR); $display( "Warning: FIFOL10: %m -- Enqueuing to a full fifo" ) ; end end - // synopsys translate_on +`endif // SYNTHESIS endmodule diff --git a/src/Verilog/FIFOL2.v b/src/Verilog/FIFOL2.v index c6b5e62db..fc84b8ea5 100644 --- a/src/Verilog/FIFOL2.v +++ b/src/Verilog/FIFOL2.v @@ -67,7 +67,7 @@ module FIFOL2(CLK, `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin data0_reg = {((width + 1)/2) {2'b10}} ; @@ -75,7 +75,7 @@ module FIFOL2(CLK, empty_reg = 1'b0; full_reg = 1'b1; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS always@(posedge CLK `BSV_ARESET_EDGE_HEAD) @@ -123,7 +123,7 @@ module FIFOL2(CLK, end // else: !if(RST == `BSV_RESET_VALUE) end // always@ (posedge CLK or `BSV_RESET_EDGE RST) - // synopsys translate_off +`ifndef SYNTHESIS always@(posedge CLK) begin: error_checks reg deqerror, enqerror ; @@ -144,6 +144,6 @@ module FIFOL2(CLK, end end end // always@ (posedge CLK) - // synopsys translate_on +`endif // SYNTHESIS endmodule diff --git a/src/Verilog/FIFOL20.v b/src/Verilog/FIFOL20.v index d08b4c3f5..f26cb2daf 100644 --- a/src/Verilog/FIFOL20.v +++ b/src/Verilog/FIFOL20.v @@ -46,13 +46,13 @@ module FIFOL20(CLK, `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin empty_reg = 1'b0 ; full_reg = 1'b1 ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS always@(posedge CLK `BSV_ARESET_EDGE_META) @@ -82,7 +82,7 @@ module FIFOL20(CLK, end // else: !if(RST == `BSV_RESET_VALUE) end // always@ (posedge CLK or `BSV_RESET_EDGE RST) - // synopsys translate_off +`ifndef SYNTHESIS always@(posedge CLK) begin: error_checks reg deqerror, enqerror ; @@ -103,6 +103,6 @@ module FIFOL20(CLK, end end // if (RST == ! `BSV_RESET_VALUE) end - // synopsys translate_on +`endif // SYNTHESIS endmodule diff --git a/src/Verilog/GatedClock.v b/src/Verilog/GatedClock.v index c48c9c459..4292615e0 100644 --- a/src/Verilog/GatedClock.v +++ b/src/Verilog/GatedClock.v @@ -79,14 +79,14 @@ module GatedClock( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin #0 ; new_gate = 1'b0 ; COND_reg = 1'b0 ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule // GatedClock diff --git a/src/Verilog/GatedClockDiv.v b/src/Verilog/GatedClockDiv.v index 3c446f888..8db5dca31 100644 --- a/src/Verilog/GatedClockDiv.v +++ b/src/Verilog/GatedClockDiv.v @@ -104,7 +104,7 @@ module GatedClockDiv(CLK_IN, `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin #0 ; @@ -112,7 +112,7 @@ module GatedClockDiv(CLK_IN, PREEDGE = 0 ; new_gate = 0 ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS diff --git a/src/Verilog/GatedClockInverter.v b/src/Verilog/GatedClockInverter.v index 75e0aff8c..c6c1cc45c 100644 --- a/src/Verilog/GatedClockInverter.v +++ b/src/Verilog/GatedClockInverter.v @@ -32,13 +32,13 @@ module GatedClockInverter(CLK_IN, CLK_GATE_IN, PREEDGE, CLK_OUT, CLK_GATE_OUT); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin #0 ; new_gate = 1 ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule // GatedClockInverter diff --git a/src/Verilog/InitialReset.v b/src/Verilog/InitialReset.v index 2bfd094aa..0bfa02f1b 100644 --- a/src/Verilog/InitialReset.v +++ b/src/Verilog/InitialReset.v @@ -28,7 +28,7 @@ module InitialReset ( input CLK ; output OUT_RST ; - // synopsys translate_off +`ifndef SYNTHESIS reg [RSTHOLD-1:0] reset_hold ; wire [RSTHOLD:0] next_reset = {reset_hold, ~ `BSV_RESET_VALUE} ; @@ -47,7 +47,7 @@ module InitialReset ( end - // synopsys translate_on +`endif // SYNTHESIS endmodule // InitialReset diff --git a/src/Verilog/LatchCrossingReg.v b/src/Verilog/LatchCrossingReg.v index 316b9bd3f..1542f2384 100644 --- a/src/Verilog/LatchCrossingReg.v +++ b/src/Verilog/LatchCrossingReg.v @@ -51,11 +51,11 @@ module LatchCrossingReg(SCLK, SRST, EN, D_IN, Q_OUT, DCLK, L_OUT); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin Q_OUT = {((width + 1)/2){2'b10}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog/MakeClock.v b/src/Verilog/MakeClock.v index a60a6e5aa..c4841b001 100644 --- a/src/Verilog/MakeClock.v +++ b/src/Verilog/MakeClock.v @@ -108,7 +108,7 @@ module MakeClock ( CLK, RST, `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin #0 ; current_clk = 1'b0 ; @@ -116,7 +116,7 @@ module MakeClock ( CLK, RST, new_gate = 1'b1 ; CLK_VAL_OUT = 1'b0; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog/MakeReset.v b/src/Verilog/MakeReset.v index 6c5483fb1..f329d9842 100644 --- a/src/Verilog/MakeReset.v +++ b/src/Verilog/MakeReset.v @@ -58,12 +58,12 @@ module MakeReset ( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin #0 ; rst = ~ `BSV_RESET_VALUE ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule // MakeReset diff --git a/src/Verilog/MakeReset0.v b/src/Verilog/MakeReset0.v index cb888fea2..9052221f4 100644 --- a/src/Verilog/MakeReset0.v +++ b/src/Verilog/MakeReset0.v @@ -53,12 +53,12 @@ module MakeReset0 ( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin #0 ; rst = ~ `BSV_RESET_VALUE ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule // MakeReset0 diff --git a/src/Verilog/MakeResetA.v b/src/Verilog/MakeResetA.v index 63719aefc..8baa7a9b8 100644 --- a/src/Verilog/MakeResetA.v +++ b/src/Verilog/MakeResetA.v @@ -58,12 +58,12 @@ module MakeResetA ( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin #0 ; rst = ~ `BSV_RESET_VALUE ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule // MakeResetA diff --git a/src/Verilog/McpRegUN.v b/src/Verilog/McpRegUN.v index c798aec7e..630eecf88 100644 --- a/src/Verilog/McpRegUN.v +++ b/src/Verilog/McpRegUN.v @@ -53,11 +53,11 @@ module McpRegUN(CLK, RST, SET, val, get); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin get = {((width + 1)/2){2'b10}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog/ProbeCapture.v b/src/Verilog/ProbeCapture.v index e7f3c7d7e..a58191fd5 100644 --- a/src/Verilog/ProbeCapture.v +++ b/src/Verilog/ProbeCapture.v @@ -276,7 +276,7 @@ module ProbeCapture ( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin enabled <= 1'b0 ; capstate <= 2'b0 ; @@ -292,7 +292,7 @@ module ProbeCapture ( probeData <= { ProbeWidth {1'b0 } }; probeChanged <= 1'b0; end - // synopsys translate_on +`endif // SYNTHESIS `endif endmodule diff --git a/src/Verilog/ProbeMux.v b/src/Verilog/ProbeMux.v index d91f5b459..fb4090d06 100644 --- a/src/Verilog/ProbeMux.v +++ b/src/Verilog/ProbeMux.v @@ -103,13 +103,13 @@ module ProbeMux ( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin sending <= 1'b0; DATAUP <= { 16 {2'b10} }; AorB <= 1'b0; end - // synopsys translate_on +`endif // SYNTHESIS `endif endmodule diff --git a/src/Verilog/ProbeTrigger.v b/src/Verilog/ProbeTrigger.v index b601da790..d4a47804f 100644 --- a/src/Verilog/ProbeTrigger.v +++ b/src/Verilog/ProbeTrigger.v @@ -156,16 +156,16 @@ module ProbeTrigger ( if (TRIGGER) begin triggerToggle <= `BSV_ASSIGNMENT_DELAY ! triggerToggle; end - // synopsys translate_off +`ifndef SYNTHESIS if (enabled && triggered && TRIGGER) begin $display ("Error: %m ProbeTrigger has been double triggered!"); end - // synopsys translate_on +`endif // SYNTHESIS end `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin DATAUP <= { 16 {2'b10}}; triggerToggle <= 1'b0; @@ -176,7 +176,7 @@ module ProbeTrigger ( enabled <= 1'b0; reportIds <= {NumWords * 8 {2'b10}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif endmodule diff --git a/src/Verilog/ProbeValue.v b/src/Verilog/ProbeValue.v index c147f1d0b..fbb73c186 100644 --- a/src/Verilog/ProbeValue.v +++ b/src/Verilog/ProbeValue.v @@ -130,17 +130,17 @@ module ProbeValue ( probeData <= `BSV_ASSIGNMENT_DELAY PROBEIN; probeChanged <= `BSV_ASSIGNMENT_DELAY ! probeChanged; end - // synopsys translate_off +`ifndef SYNTHESIS if (enabled && newProbeData && newData) begin $display ("Error: %m Probevalue has been overrun with data!"); end - // synopsys translate_on +`endif // SYNTHESIS end `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin probeData <= { ProbeWidth {1'b0 } }; probeChanged <= 1'b0; @@ -153,7 +153,7 @@ module ProbeValue ( captureChanged <= 1'b0; DATAUP <= {16 {2'b10}}; end - // synopsys translate_on +`endif // SYNTHESIS `endif endmodule diff --git a/src/Verilog/RegA.v b/src/Verilog/RegA.v index cf43e3799..401465c7b 100644 --- a/src/Verilog/RegA.v +++ b/src/Verilog/RegA.v @@ -40,11 +40,11 @@ module RegA(CLK, RST, Q_OUT, D_IN, EN); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin Q_OUT = {((width + 1)/2){2'b10}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog/RegFile.v b/src/Verilog/RegFile.v index 72ec88409..f72c3ac4c 100644 --- a/src/Verilog/RegFile.v +++ b/src/Verilog/RegFile.v @@ -50,7 +50,7 @@ module RegFile(CLK, `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin : init_block integer i; // temporary for generate reset value @@ -58,7 +58,7 @@ module RegFile(CLK, arr[i] = {((data_width + 1)/2){2'b10}} ; end end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS @@ -74,7 +74,7 @@ module RegFile(CLK, assign D_OUT_4 = arr[ADDR_4]; assign D_OUT_5 = arr[ADDR_5]; - // synopsys translate_off +`ifndef SYNTHESIS always@(posedge CLK) begin : runtime_check reg enable_check; @@ -95,6 +95,6 @@ module RegFile(CLK, $display( "Warning: RegFile: %m -- Write Address port is out of bounds: %h", ADDR_IN ) ; end end - // synopsys translate_on +`endif // SYNTHESIS endmodule diff --git a/src/Verilog/RegFileLoad.v b/src/Verilog/RegFileLoad.v index 4481262bb..64cd66ba4 100644 --- a/src/Verilog/RegFileLoad.v +++ b/src/Verilog/RegFileLoad.v @@ -70,7 +70,7 @@ module RegFileLoad(CLK, assign D_OUT_4 = arr[ADDR_4]; assign D_OUT_5 = arr[ADDR_5]; - // synopsys translate_off +`ifndef SYNTHESIS always@(posedge CLK) begin : runtime_check reg enable_check; @@ -91,6 +91,6 @@ module RegFileLoad(CLK, $display( "Warning: RegFile: %m -- Write Address port is out of bounds: %h", ADDR_IN ) ; end end - // synopsys translate_on +`endif // SYNTHESIS endmodule diff --git a/src/Verilog/RegN.v b/src/Verilog/RegN.v index 979861782..d0e691dfb 100644 --- a/src/Verilog/RegN.v +++ b/src/Verilog/RegN.v @@ -39,11 +39,11 @@ module RegN(CLK, RST, Q_OUT, D_IN, EN); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin Q_OUT = {((width + 1)/2){2'b10}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog/RegTwoA.v b/src/Verilog/RegTwoA.v index 61ab1c25b..b25147376 100644 --- a/src/Verilog/RegTwoA.v +++ b/src/Verilog/RegTwoA.v @@ -44,12 +44,12 @@ module RegTwoA(CLK, RST, Q_OUT, D_INA, ENA, D_INB, ENB); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin Q_OUT = {((width + 1)/2){2'b10}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog/RegTwoN.v b/src/Verilog/RegTwoN.v index a554277ed..cb1f2e00c 100644 --- a/src/Verilog/RegTwoN.v +++ b/src/Verilog/RegTwoN.v @@ -43,11 +43,11 @@ module RegTwoN(CLK, RST, Q_OUT, D_INA, ENA, D_INB, ENB); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin Q_OUT = {((width + 1)/2){2'b10}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog/RegTwoUN.v b/src/Verilog/RegTwoUN.v index 829135a2b..772dd2676 100644 --- a/src/Verilog/RegTwoUN.v +++ b/src/Verilog/RegTwoUN.v @@ -21,11 +21,11 @@ module RegTwoUN(CLK, ENA, D_INA, ENB, D_INB, Q_OUT); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin Q_OUT = {((width + 1)/2){2'b10}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS diff --git a/src/Verilog/RegUN.v b/src/Verilog/RegUN.v index c35b1c34b..bf4caf3d1 100644 --- a/src/Verilog/RegUN.v +++ b/src/Verilog/RegUN.v @@ -18,11 +18,11 @@ module RegUN(CLK, EN, D_IN, Q_OUT); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin Q_OUT = {((width + 1)/2){2'b10}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS diff --git a/src/Verilog/ResetMux.v b/src/Verilog/ResetMux.v index fd55a891b..65de6c2af 100644 --- a/src/Verilog/ResetMux.v +++ b/src/Verilog/ResetMux.v @@ -37,13 +37,13 @@ module ResetMux( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin #0 ; sel_reg = 1'b0 ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog/SizedFIFO.v b/src/Verilog/SizedFIFO.v index 18714ac6a..caab0ba07 100644 --- a/src/Verilog/SizedFIFO.v +++ b/src/Verilog/SizedFIFO.v @@ -83,7 +83,7 @@ module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin : initial_block integer i; @@ -100,7 +100,7 @@ module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); arr[i] = D_OUT ; end end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS @@ -208,7 +208,7 @@ module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); end // else: !if(RST == `BSV_RESET_VALUE) end // always @ (posedge CLK) - // synopsys translate_off +`ifndef SYNTHESIS always@(posedge CLK) begin: error_checks reg deqerror, enqerror ; @@ -229,9 +229,9 @@ module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); end end end // block: error_checks - // synopsys translate_on +`endif // SYNTHESIS - // synopsys translate_off +`ifndef SYNTHESIS // Some assertions about parameter values initial begin : parameter_assertions @@ -253,6 +253,6 @@ module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); if ( ok == 0 ) $finish ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS endmodule diff --git a/src/Verilog/SizedFIFO0.v b/src/Verilog/SizedFIFO0.v index 563292748..268af287c 100644 --- a/src/Verilog/SizedFIFO0.v +++ b/src/Verilog/SizedFIFO0.v @@ -44,14 +44,14 @@ module SizedFIFO0(CLK, RST, ENQ, FULL_N, DEQ, EMPTY_N, CLR); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin count = 0 ; not_empty = 1'b0; not_full = 1'b1; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS @@ -88,7 +88,7 @@ module SizedFIFO0(CLK, RST, ENQ, FULL_N, DEQ, EMPTY_N, CLR); end // else: !if(RST == `BSV_RESET_VALUE) end // always @ (posedge CLK or `BSV_RESET_EDGE RST) - // synopsys translate_off +`ifndef SYNTHESIS always@(posedge CLK) begin: error_checks reg deqerror, enqerror ; @@ -109,6 +109,6 @@ module SizedFIFO0(CLK, RST, ENQ, FULL_N, DEQ, EMPTY_N, CLR); end end // if (RST == ! `BSV_RESET_VALUE) end // block: error_checks - // synopsys translate_on +`endif // SYNTHESIS endmodule // SizedFIFO0 diff --git a/src/Verilog/SizedFIFOL.v b/src/Verilog/SizedFIFOL.v index 0011c0a44..16d26b773 100644 --- a/src/Verilog/SizedFIFOL.v +++ b/src/Verilog/SizedFIFOL.v @@ -84,7 +84,7 @@ module SizedFIFOL(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin : initial_block integer i; @@ -101,7 +101,7 @@ module SizedFIFOL(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); arr[i] = D_OUT ; end end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS @@ -209,7 +209,7 @@ module SizedFIFOL(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); end // else: !if(RST == `BSV_RESET_VALUE) end // always @ (posedge CLK) - // synopsys translate_off +`ifndef SYNTHESIS always@(posedge CLK) begin: error_checks reg deqerror, enqerror ; @@ -230,9 +230,9 @@ module SizedFIFOL(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); end end end // block: error_checks - // synopsys translate_on +`endif // SYNTHESIS - // synopsys translate_off +`ifndef SYNTHESIS // Some assertions about parameter values initial begin : parameter_assertions @@ -254,6 +254,6 @@ module SizedFIFOL(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); if ( ok == 0 ) $finish ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS endmodule diff --git a/src/Verilog/SizedFIFOL0.v b/src/Verilog/SizedFIFOL0.v index 802040599..006af4817 100644 --- a/src/Verilog/SizedFIFOL0.v +++ b/src/Verilog/SizedFIFOL0.v @@ -44,14 +44,14 @@ module SizedFIFOL0(CLK, RST, ENQ, FULL_N, DEQ, EMPTY_N, CLR); `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin count = 0 ; not_empty = 1'b0; not_full = 1'b1; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS @@ -88,7 +88,7 @@ module SizedFIFOL0(CLK, RST, ENQ, FULL_N, DEQ, EMPTY_N, CLR); end // else: !if(RST == `BSV_RESET_VALUE) end // always @ (posedge CLK or `BSV_RESET_EDGE RST) - // synopsys translate_off +`ifndef SYNTHESIS always@(posedge CLK) begin: error_checks reg deqerror, enqerror ; @@ -109,6 +109,6 @@ module SizedFIFOL0(CLK, RST, ENQ, FULL_N, DEQ, EMPTY_N, CLR); end end // if (RST == ! `BSV_RESET_VALUE) end // block: error_checks - // synopsys translate_on +`endif // SYNTHESIS endmodule // SizedFIFOL0 diff --git a/src/Verilog/SyncBit.v b/src/Verilog/SyncBit.v index 9cf4d3700..d48eb5d5b 100644 --- a/src/Verilog/SyncBit.v +++ b/src/Verilog/SyncBit.v @@ -73,14 +73,14 @@ module SyncBit ( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin sSyncReg = init ; dSyncReg1 = init ; dSyncReg2 = init ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule // BitSync diff --git a/src/Verilog/SyncBit05.v b/src/Verilog/SyncBit05.v index 9f23bdc75..b1b68c1aa 100644 --- a/src/Verilog/SyncBit05.v +++ b/src/Verilog/SyncBit05.v @@ -72,13 +72,13 @@ module SyncBit05 ( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin sSyncReg = init ; dSyncReg1 = init ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule // BitSync diff --git a/src/Verilog/SyncBit1.v b/src/Verilog/SyncBit1.v index b5a9cacf1..0750394e0 100644 --- a/src/Verilog/SyncBit1.v +++ b/src/Verilog/SyncBit1.v @@ -71,13 +71,13 @@ module SyncBit1 ( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin sSyncReg = init ; dSyncReg1 = init ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule // BitSync diff --git a/src/Verilog/SyncBit15.v b/src/Verilog/SyncBit15.v index 35753d35c..c3c99a45d 100644 --- a/src/Verilog/SyncBit15.v +++ b/src/Verilog/SyncBit15.v @@ -85,14 +85,14 @@ module SyncBit15 ( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin sSyncReg = init ; dSyncReg1 = init ; dSyncReg2 = init ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule // BitSync diff --git a/src/Verilog/SyncFIFO.v b/src/Verilog/SyncFIFO.v index a5b229ab0..25f7d8b97 100644 --- a/src/Verilog/SyncFIFO.v +++ b/src/Verilog/SyncFIFO.v @@ -210,7 +210,7 @@ module SyncFIFO( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin : initBlock integer i ; @@ -238,11 +238,11 @@ module SyncFIFO( dSyncReg1 = sGEnqPtr ; dEnqPtr = sGEnqPtr ; end // block: initBlock - // synopsys translate_on +`endif // SYNTHESIS - // synopsys translate_off +`ifndef SYNTHESIS initial begin : parameter_assertions integer ok ; @@ -268,7 +268,7 @@ module SyncFIFO( if ( ok == 0 ) $finish ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS function [indxWidth+1:0] incrGrayP ; diff --git a/src/Verilog/SyncFIFO0.v b/src/Verilog/SyncFIFO0.v index 3ba6c1eb2..0a82e9abd 100644 --- a/src/Verilog/SyncFIFO0.v +++ b/src/Verilog/SyncFIFO0.v @@ -179,7 +179,7 @@ module SyncFIFO0( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin : initBlock integer i ; @@ -200,11 +200,11 @@ module SyncFIFO0( dSyncReg1 = sGEnqPtr ; dEnqPtr = sGEnqPtr ; end // block: initBlock - // synopsys translate_on +`endif // SYNTHESIS - // synopsys translate_off +`ifndef SYNTHESIS initial begin : parameter_assertions integer ok ; @@ -230,7 +230,7 @@ module SyncFIFO0( if ( ok == 0 ) $finish ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS function [indxWidth+1:0] incrGrayP ; diff --git a/src/Verilog/SyncFIFO1.v b/src/Verilog/SyncFIFO1.v index d11acc283..13736715d 100644 --- a/src/Verilog/SyncFIFO1.v +++ b/src/Verilog/SyncFIFO1.v @@ -98,7 +98,7 @@ module SyncFIFO1( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin : initBlock syncFIFO1Data = {((dataWidth + 1)/2){2'b10}} ; sEnqToggle = 1'b0; @@ -109,10 +109,10 @@ module SyncFIFO1( dDeqToggle = 1'b0; dSyncReg1 = 1'b0; end - // synopsys translate_on +`endif // SYNTHESIS `endif // !`ifdef BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS always@(posedge sCLK) begin: error_checks1 reg enqerror ; @@ -138,6 +138,6 @@ module SyncFIFO1( end end end // block: error_checks - // synopsys translate_on +`endif // SYNTHESIS endmodule diff --git a/src/Verilog/SyncFIFO10.v b/src/Verilog/SyncFIFO10.v index 81d254717..daf27e060 100644 --- a/src/Verilog/SyncFIFO10.v +++ b/src/Verilog/SyncFIFO10.v @@ -88,7 +88,7 @@ module SyncFIFO10( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin : initBlock sEnqToggle = 1'b0; sDeqToggle = 1'b0; @@ -98,10 +98,10 @@ module SyncFIFO10( dDeqToggle = 1'b0; dSyncReg1 = 1'b0; end - // synopsys translate_on +`endif // SYNTHESIS `endif // !`ifdef BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS always@(posedge sCLK) begin: error_checks1 reg enqerror ; @@ -127,6 +127,6 @@ module SyncFIFO10( end end end // block: error_checks - // synopsys translate_on +`endif // SYNTHESIS endmodule diff --git a/src/Verilog/SyncFIFOLevel.v b/src/Verilog/SyncFIFOLevel.v index 58215d6a7..0d1dad224 100644 --- a/src/Verilog/SyncFIFOLevel.v +++ b/src/Verilog/SyncFIFOLevel.v @@ -310,7 +310,7 @@ module SyncFIFOLevel( end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST) //////////////////////////////////////////////////////////////////////// - // synopsys translate_off +`ifndef SYNTHESIS // Run time assertion check always @(posedge sCLK) begin @@ -320,11 +320,11 @@ module SyncFIFOLevel( begin if ( dDEQ && ! dNotEmptyReg ) $display ("Warning: SyncFIFOLevel: %m -- Dequeuing from empty fifo"); end - // synopsys translate_on +`endif // SYNTHESIS `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin : initBlock integer i ; @@ -352,9 +352,9 @@ module SyncFIFOLevel( dSyncReg1 = sGEnqPtr ; dEnqPtr = sGEnqPtr ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS - // synopsys translate_off +`ifndef SYNTHESIS initial begin : parameter_assertions integer ok ; @@ -379,7 +379,7 @@ module SyncFIFOLevel( if ( ok == 0 ) $finish ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS function [indxWidth:0] grayToBinary ; diff --git a/src/Verilog/SyncFIFOLevel0.v b/src/Verilog/SyncFIFOLevel0.v index 7284ad39e..0fcce2391 100644 --- a/src/Verilog/SyncFIFOLevel0.v +++ b/src/Verilog/SyncFIFOLevel0.v @@ -279,7 +279,7 @@ module SyncFIFOLevel0( end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST) //////////////////////////////////////////////////////////////////////// - // synopsys translate_off +`ifndef SYNTHESIS // Run time assertion check always @(posedge sCLK) begin @@ -289,11 +289,11 @@ module SyncFIFOLevel0( begin if ( dDEQ && ! dNotEmptyReg ) $display ("Warning: SyncFIFOLevel: %m -- Dequeuing from empty fifo"); end - // synopsys translate_on +`endif // SYNTHESIS `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin : initBlock integer i ; @@ -314,9 +314,9 @@ module SyncFIFOLevel0( dSyncReg1 = sGEnqPtr ; dEnqPtr = sGEnqPtr ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS - // synopsys translate_off +`ifndef SYNTHESIS initial begin : parameter_assertions integer ok ; @@ -341,7 +341,7 @@ module SyncFIFOLevel0( if ( ok == 0 ) $finish ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS function [indxWidth:0] grayToBinary ; diff --git a/src/Verilog/SyncHandshake.v b/src/Verilog/SyncHandshake.v index e226e1f4d..3920ef443 100644 --- a/src/Verilog/SyncHandshake.v +++ b/src/Verilog/SyncHandshake.v @@ -90,7 +90,7 @@ module SyncHandshake( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin dSyncReg1 = init ; @@ -102,7 +102,7 @@ module SyncHandshake( sSyncReg2 = ! init ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule // HandshakeSync diff --git a/src/Verilog/SyncPulse.v b/src/Verilog/SyncPulse.v index 4067ea467..07e93c95c 100644 --- a/src/Verilog/SyncPulse.v +++ b/src/Verilog/SyncPulse.v @@ -77,7 +77,7 @@ module SyncPulse( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin sSyncReg = 1'b0 ; @@ -85,7 +85,7 @@ module SyncPulse( dSyncReg2 = 1'b0 ; dSyncPulse = 1'b0 ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule // PulseSync diff --git a/src/Verilog/SyncRegister.v b/src/Verilog/SyncRegister.v index a5386d420..fafb89772 100644 --- a/src/Verilog/SyncRegister.v +++ b/src/Verilog/SyncRegister.v @@ -89,13 +89,13 @@ module SyncRegister( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin sDataSyncIn = {((width + 1)/2){2'b10}} ; dD_OUT = {((width + 1)/2){2'b10}} ; end // initial begin - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS diff --git a/src/Verilog/SyncReset.v b/src/Verilog/SyncReset.v index 8fca79390..173f59a28 100644 --- a/src/Verilog/SyncReset.v +++ b/src/Verilog/SyncReset.v @@ -45,14 +45,14 @@ module SyncReset ( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin #0 ; // initialize out of reset forcing the designer to do one reset_hold = {(RSTDELAY + 1) {~ `BSV_RESET_VALUE }} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule // SyncReset diff --git a/src/Verilog/SyncResetA.v b/src/Verilog/SyncResetA.v index 1ae604abb..b13cfe4ee 100644 --- a/src/Verilog/SyncResetA.v +++ b/src/Verilog/SyncResetA.v @@ -48,14 +48,14 @@ module SyncResetA ( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin #0 ; // initialize out of reset forcing the designer to do one reset_hold = {(RSTDELAY + 1) {~ `BSV_RESET_VALUE}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule // SyncResetA diff --git a/src/Verilog/UngatedClockMux.v b/src/Verilog/UngatedClockMux.v index 96c90849e..a4e96b262 100644 --- a/src/Verilog/UngatedClockMux.v +++ b/src/Verilog/UngatedClockMux.v @@ -39,13 +39,13 @@ module UngatedClockMux( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin #0 ; sel_reg = 1'b0 ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule diff --git a/src/Verilog/UngatedClockSelect.v b/src/Verilog/UngatedClockSelect.v index e4f8f51b0..e91883c29 100644 --- a/src/Verilog/UngatedClockSelect.v +++ b/src/Verilog/UngatedClockSelect.v @@ -98,7 +98,7 @@ module UngatedClockSelect( `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off +`ifndef SYNTHESIS initial begin #0 ; @@ -107,7 +107,7 @@ module UngatedClockSelect( // initialize out of reset forcin the designer to do one. reset_hold = {(RSTDELAY + 1) {~ `BSV_RESET_VALUE}} ; end - // synopsys translate_on +`endif // SYNTHESIS `endif // BSV_NO_INITIAL_BLOCKS endmodule