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driver-avalon4.c
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driver-avalon4.c
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/*
* Copyright 2014-2015 Mikeqin <[email protected]>
* Copyright 2013-2015 Con Kolivas <[email protected]>
* Copyright 2012-2015 Xiangfu <[email protected]>
* Copyright 2012 Luke Dashjr
* Copyright 2012 Andrew Smith
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 3 of the License, or (at your option)
* any later version. See COPYING for more details.
*/
#include <math.h>
#include "config.h"
#include "miner.h"
#include "driver-avalon4.h"
#include "crc.h"
#include "sha2.h"
#include "hexdump.c"
#define get_fan_pwm(v) (AVA4_PWM_MAX - (v) * AVA4_PWM_MAX / 100)
int opt_avalon4_temp_target = AVA4_DEFAULT_TEMP_TARGET;
int opt_avalon4_overheat = AVA4_DEFAULT_TEMP_OVERHEAT;
int opt_avalon4_fan_min = AVA4_DEFAULT_FAN_MIN;
int opt_avalon4_fan_max = AVA4_DEFAULT_FAN_MAX;
bool opt_avalon4_autov;
bool opt_avalon4_freezesafe;
int opt_avalon4_voltage_min = AVA4_DEFAULT_VOLTAGE;
int opt_avalon4_voltage_max = AVA4_DEFAULT_VOLTAGE;
unsigned int opt_avalon4_freq[3] = {AVA4_DEFAULT_FREQUENCY,
AVA4_DEFAULT_FREQUENCY,
AVA4_DEFAULT_FREQUENCY};
int opt_avalon4_polling_delay = AVA4_DEFAULT_POLLING_DELAY;
int opt_avalon4_aucspeed = AVA4_AUC_SPEED;
int opt_avalon4_aucxdelay = AVA4_AUC_XDELAY;
int opt_avalon4_ntime_offset = AVA4_DEFAULT_ASIC_MAX;
int opt_avalon4_miningmode = AVA4_MOD_CUSTOM;
int opt_avalon4_ntcb = AVA4_DEFAULT_NTCB;
int opt_avalon4_freq_min = AVA4_DEFAULT_FREQUENCY_MIN;
int opt_avalon4_freq_max = AVA4_DEFAULT_FREQUENCY_MAX;
bool opt_avalon4_noncecheck = AVA4_DEFAULT_NCHECK;
int opt_avalon4_smart_speed = AVA4_DEFAULT_SMART_SPEED;
/*
* smart speed have 3 modes
* 1. auto speed by A3218 chips
* 2. option 1 + adjust by least pll count
* option 1 + adjust by most pll count
* 3. option 1 + adjust by average frequency
*/
int opt_avalon4_least_pll_check = AVA4_DEFAULT_LEAST_PLL;
int opt_avalon4_most_pll_check = AVA4_DEFAULT_MOST_PLL;
int opt_avalon4_speed_bingo = AVA4_DEFAULT_SPEED_BINGO;
int opt_avalon4_speed_error = AVA4_DEFAULT_SPEED_ERROR;
bool opt_avalon4_iic_detect = AVA4_DEFAULT_IIC_DETECT;
int opt_avalon4_freqadj_time = AVA4_DEFAULT_FREQADJ_TIME;
int opt_avalon4_delta_temp = AVA4_DEFAULT_DELTA_T;
int opt_avalon4_delta_freq = AVA4_DEFAULT_DELTA_FREQ;
int opt_avalon4_freqadj_temp = AVA4_MM60_TEMP_FREQADJ;
static uint8_t avalon4_freezsafemode = 0;
/* Only for Avalon4 */
static uint32_t g_freq_array[][2] = {
{100, 0x1e678447},
{113, 0x22688447},
{125, 0x1c470447},
{138, 0x2a6a8447},
{150, 0x22488447},
{163, 0x326c8447},
{175, 0x1a268447},
{188, 0x1c270447},
{200, 0x1e278447},
{213, 0x20280447},
{225, 0x22288447},
{238, 0x24290447},
{250, 0x26298447},
{263, 0x282a0447},
{275, 0x2a2a8447},
{288, 0x2c2b0447},
{300, 0x2e2b8447},
{313, 0x302c0447},
{325, 0x322c8447},
{338, 0x342d0447},
{350, 0x1a068447},
{363, 0x382e0447},
{375, 0x1c070447},
{388, 0x3c2f0447},
{400, 0x1e078447},
{413, 0x40300447},
{425, 0x20080447},
{438, 0x44310447},
{450, 0x22088447},
{463, 0x48320447},
{475, 0x24090447},
{488, 0x4c330447},
{500, 0x26098447},
{513, 0x50340447},
{525, 0x280a0447},
{538, 0x54350447},
{550, 0x2a0a8447},
{563, 0x58360447},
{575, 0x2c0b0447},
{588, 0x5c370447},
{600, 0x2e0b8447},
{613, 0x60380447},
{625, 0x300c0447},
{638, 0x64390447},
{650, 0x320c8447},
{663, 0x683a0447},
{675, 0x340d0447},
{688, 0x6c3b0447},
{700, 0x360d8447},
{713, 0x703c0447},
{725, 0x380e0447},
{738, 0x743d0447},
{750, 0x3a0e8447},
{763, 0x783e0447},
{775, 0x3c0f0447},
{788, 0x7c3f0447},
{800, 0x3e0f8447},
{813, 0x3e0f8447},
{825, 0x40100447},
{838, 0x40100447},
{850, 0x42108447},
{863, 0x42108447},
{875, 0x44110447},
{888, 0x44110447},
{900, 0x46118447},
{913, 0x46118447},
{925, 0x48120447},
{938, 0x48120447},
{950, 0x4a128447},
{963, 0x4a128447},
{975, 0x4c130447},
{988, 0x4c130447},
{1000, 0x4e138447}
};
#define UNPACK32(x, str) \
{ \
*((str) + 3) = (uint8_t) ((x) ); \
*((str) + 2) = (uint8_t) ((x) >> 8); \
*((str) + 1) = (uint8_t) ((x) >> 16); \
*((str) + 0) = (uint8_t) ((x) >> 24); \
}
static inline void sha256_prehash(const unsigned char *message, unsigned int len, unsigned char *digest)
{
sha256_ctx ctx;
int i;
sha256_init(&ctx);
sha256_update(&ctx, message, len);
for (i = 0; i < 8; i++) {
UNPACK32(ctx.h[i], &digest[i << 2]);
}
}
static inline uint8_t rev8(uint8_t d)
{
int i;
uint8_t out = 0;
/* (from left to right) */
for (i = 0; i < 8; i++)
if (d & (1 << i))
out |= (1 << (7 - i));
return out;
}
#define R_REF 10000
#define R0 10000
#define T0 25
static float convert_temp(uint16_t adc)
{
float ret, resistance;
if (!adc || adc >= AVA4_ADC_MAX)
return -273.15;
resistance = (AVA4_ADC_MAX * 1.0 / adc) - 1;
resistance = R_REF / resistance;
ret = resistance / R0;
ret = logf(ret);
ret /= opt_avalon4_ntcb;
ret += 1.0 / (T0 + 273.15);
ret = 1.0 / ret;
ret -= 273.15;
return ret;
}
#define V_REF 3.3
static float convert_voltage(uint16_t adc, float percent)
{
float voltage;
voltage = adc * V_REF * 1.0 / AVA4_ADC_MAX / percent;
return voltage + 0.4;
}
char *set_avalon4_fan(char *arg)
{
int val1, val2, ret;
ret = sscanf(arg, "%d-%d", &val1, &val2);
if (ret < 1)
return "No values passed to avalon4-fan";
if (ret == 1)
val2 = val1;
if (val1 < 0 || val1 > 100 || val2 < 0 || val2 > 100 || val2 < val1)
return "Invalid value passed to avalon4-fan";
opt_avalon4_fan_min = val1;
opt_avalon4_fan_max = val2;
return NULL;
}
char *set_avalon4_freq(char *arg)
{
char *colon1, *colon2;
int val1 = 0, val2 = 0, val3 = 0;
if (!(*arg))
return NULL;
colon1 = strchr(arg, ':');
if (colon1)
*(colon1++) = '\0';
if (*arg) {
val1 = atoi(arg);
if (val1 < AVA4_DEFAULT_FREQUENCY_MIN || val1 > AVA4_DEFAULT_FREQUENCY_MAX)
return "Invalid value1 passed to avalon4-freq";
}
if (colon1 && *colon1) {
colon2 = strchr(colon1, ':');
if (colon2)
*(colon2++) = '\0';
if (*colon1) {
val2 = atoi(colon1);
if (val2 < AVA4_DEFAULT_FREQUENCY_MIN || val2 > AVA4_DEFAULT_FREQUENCY_MAX)
return "Invalid value2 passed to avalon4-freq";
}
if (colon2 && *colon2) {
val3 = atoi(colon2);
if (val3 < AVA4_DEFAULT_FREQUENCY_MIN || val3 > AVA4_DEFAULT_FREQUENCY_MAX)
return "Invalid value3 passed to avalon4-freq";
}
}
if (!val1)
val3 = val2 = val1 = AVA4_DEFAULT_FREQUENCY;
if (!val2)
val3 = val2 = val1;
if (!val3)
val3 = val2;
opt_avalon4_freq[0] = val1;
opt_avalon4_freq[1] = val2;
opt_avalon4_freq[2] = val3;
return NULL;
}
char *set_avalon4_voltage(char *arg)
{
int val1, val2, ret;
ret = sscanf(arg, "%d-%d", &val1, &val2);
if (ret < 1)
return "No values passed to avalon4-voltage";
if (ret == 1)
val2 = val1;
if (val1 < AVA4_DEFAULT_VOLTAGE_MIN || val1 > AVA4_DEFAULT_VOLTAGE_MAX ||
val2 < AVA4_DEFAULT_VOLTAGE_MIN || val2 > AVA4_DEFAULT_VOLTAGE_MAX ||
val2 < val1)
return "Invalid value passed to avalon4-voltage";
opt_avalon4_voltage_min = val1;
opt_avalon4_voltage_max = val2;
return NULL;
}
static int avalon4_init_pkg(struct avalon4_pkg *pkg, uint8_t type, uint8_t idx, uint8_t cnt)
{
unsigned short crc;
pkg->head[0] = AVA4_H1;
pkg->head[1] = AVA4_H2;
pkg->type = type;
pkg->opt = 0;
pkg->idx = idx;
pkg->cnt = cnt;
crc = crc16(pkg->data, AVA4_P_DATA_LEN);
pkg->crc[0] = (crc & 0xff00) >> 8;
pkg->crc[1] = crc & 0x00ff;
return 0;
}
static int job_idcmp(uint8_t *job_id, char *pool_job_id)
{
int job_id_len;
unsigned short crc, crc_expect;
if (!pool_job_id)
return 1;
job_id_len = strlen(pool_job_id);
crc_expect = crc16((unsigned char *)pool_job_id, job_id_len);
crc = job_id[0] << 8 | job_id[1];
if (crc_expect == crc)
return 0;
applog(LOG_DEBUG, "Avalon4: job_id doesn't match! [%04x:%04x (%s)]",
crc, crc_expect, pool_job_id);
return 1;
}
static inline int get_current_temp_max(struct avalon4_info *info)
{
int i;
int t = info->temp[0];
for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
if (info->enable[i] && info->temp[i] > t)
t = info->temp[i];
}
return t;
}
static inline int get_temp_max(struct avalon4_info *info, int addr)
{
int i;
int t = -273, t1 = -273;
if (info->enable[addr]) {
t = info->temp[addr];
for (i = 0; i < 2; i++) {
t1 = convert_temp(info->adc[addr][i]);
if (t1 > t)
t = t1;
}
}
return t;
}
/* http://www.onsemi.com/pub_link/Collateral/ADP3208D.PDF */
static uint32_t encode_voltage_adp3208d(uint32_t v)
{
return rev8((0x78 - v / 125) << 1 | 1) << 8;
}
static uint32_t decode_voltage_adp3208d(uint32_t v)
{
return (0x78 - (rev8(v >> 8) >> 1)) * 125;
}
/* http://www.onsemi.com/pub/Collateral/NCP5392P-D.PDF */
static uint32_t encode_voltage_ncp5392p(uint32_t v)
{
if (v == 0)
return 0xff00;
return rev8(((0x59 - (v - 5000) / 125) & 0xff) << 1 | 1) << 8;
}
static uint32_t decode_voltage_ncp5392p(uint32_t v)
{
if (v == 0xff00)
return 0;
return (0x59 - (rev8(v >> 8) >> 1)) * 125 + 5000;
}
static inline uint32_t adjust_fan(struct avalon4_info *info, int id)
{
uint32_t pwm;
int t = info->temp[id], diff, fandiff = opt_avalon4_fan_max - opt_avalon4_fan_min;;
if (info->mod_type[id] == AVA4_TYPE_MM60) {
int t1, t2;
t1 = (int)convert_temp(info->adc[id][0]),
t2 = (int)convert_temp(info->adc[id][1]),
t = t > t1 ? t : t1;
t = t > t2 ? t : t2;
}
if (avalon4_freezsafemode) {
pwm = get_fan_pwm(AVA4_FREEZESAFE_FAN);
return pwm;
}
/* Scale fan% non linearly relatively to target temperature. It will
* not try to keep the temperature at temp_target that accurately but
* avoids temperature overshoot in both directions. */
diff = t - opt_avalon4_temp_target + 30;
if (diff > 32)
diff = 32;
else if (diff < 0)
diff = 0;
diff *= diff;
fandiff = fandiff * diff / 1024;
info->fan_pct[id] = opt_avalon4_fan_min + fandiff;
pwm = get_fan_pwm(info->fan_pct[id]);
if ((info->mod_type[id] == AVA4_TYPE_MM60) &&
(info->freq_mode[id] == AVA4_FREQ_TEMPADJ_MODE))
pwm = get_fan_pwm(opt_avalon4_fan_max);
if (info->cutoff[id])
pwm = get_fan_pwm(opt_avalon4_fan_max);
applog(LOG_DEBUG, "[%d], Adjust_fan: %dC-%d%%(%03x)", id, t, info->fan_pct[id], pwm);
return pwm;
}
static int decode_pkg(struct thr_info *thr, struct avalon4_ret *ar, int modular_id)
{
struct cgpu_info *avalon4 = thr->cgpu;
struct avalon4_info *info = avalon4->device_data;
struct pool *pool, *real_pool;
struct pool *pool_stratum0 = &info->pool0;
struct pool *pool_stratum1 = &info->pool1;
struct pool *pool_stratum2 = &info->pool2;
unsigned int expected_crc;
unsigned int actual_crc;
uint32_t nonce, nonce2, ntime, miner, chip_id, volt, tmp;
uint8_t job_id[4];
int pool_no, i;
uint32_t val[AVA4_DEFAULT_MINER_MAX];
if (ar->head[0] != AVA4_H1 && ar->head[1] != AVA4_H2) {
applog(LOG_DEBUG, "%s-%d-%d: H1 %02x, H2 %02x",
avalon4->drv->name, avalon4->device_id, modular_id,
ar->head[0], ar->head[1]);
hexdump(ar->data, 32);
return 1;
}
expected_crc = crc16(ar->data, AVA4_P_DATA_LEN);
actual_crc = (ar->crc[0] & 0xff) | ((ar->crc[1] & 0xff) << 8);
if (expected_crc != actual_crc) {
applog(LOG_DEBUG, "%s-%d-%d: %02x: expected crc(%04x), actual_crc(%04x)",
avalon4->drv->name, avalon4->device_id, modular_id,
ar->type, expected_crc, actual_crc);
return 1;
}
switch(ar->type) {
case AVA4_P_NONCE:
applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_NONCE", avalon4->drv->name, avalon4->device_id, modular_id);
memcpy(&miner, ar->data + 0, 4);
memcpy(&pool_no, ar->data + 4, 4);
memcpy(&nonce2, ar->data + 8, 4);
memcpy(&ntime, ar->data + 12, 4);
memcpy(&nonce, ar->data + 16, 4);
memcpy(job_id, ar->data + 20, 4);
miner = be32toh(miner);
chip_id = (miner >> 16) & 0xffff;
miner &= 0xffff;
pool_no = be32toh(pool_no);
ntime = be32toh(ntime);
if (miner >= info->miner_count[modular_id] ||
pool_no >= total_pools || pool_no < 0) {
applog(LOG_DEBUG, "%s-%d-%d: Wrong miner/pool_no %d/%d",
avalon4->drv->name, avalon4->device_id, modular_id,
miner, pool_no);
break;
}
nonce2 = be32toh(nonce2);
nonce = be32toh(nonce);
if ((info->mod_type[modular_id] == AVA4_TYPE_MM40) ||
(info->mod_type[modular_id] == AVA4_TYPE_MM41) ||
(info->mod_type[modular_id] == AVA4_TYPE_MM50))
nonce -= 0x4000;
applog(LOG_DEBUG, "%s-%d-%d: Found! P:%d - N2:%08x N:%08x NR:%d [M:%d - MW: %d(%d,%d,%d,%d)]",
avalon4->drv->name, avalon4->device_id, modular_id,
pool_no, nonce2, nonce, ntime,
miner, info->matching_work[modular_id][miner],
info->chipmatching_work[modular_id][miner][0],
info->chipmatching_work[modular_id][miner][1],
info->chipmatching_work[modular_id][miner][2],
info->chipmatching_work[modular_id][miner][3]);
real_pool = pool = pools[pool_no];
if (job_idcmp(job_id, pool->swork.job_id)) {
if (!job_idcmp(job_id, pool_stratum0->swork.job_id)) {
applog(LOG_DEBUG, "%s-%d-%d: Match to previous stratum0! (%s)",
avalon4->drv->name, avalon4->device_id, modular_id,
pool_stratum0->swork.job_id);
pool = pool_stratum0;
} else if (!job_idcmp(job_id, pool_stratum1->swork.job_id)) {
applog(LOG_DEBUG, "%s-%d-%d: Match to previous stratum1! (%s)",
avalon4->drv->name, avalon4->device_id, modular_id,
pool_stratum1->swork.job_id);
pool = pool_stratum1;
} else if (!job_idcmp(job_id, pool_stratum2->swork.job_id)) {
applog(LOG_DEBUG, "%s-%d-%d: Match to previous stratum2! (%s)",
avalon4->drv->name, avalon4->device_id, modular_id,
pool_stratum2->swork.job_id);
pool = pool_stratum2;
} else {
applog(LOG_ERR, "%s-%d-%d: Cannot match to any stratum! (%s)",
avalon4->drv->name, avalon4->device_id, modular_id,
pool->swork.job_id);
inc_hw_errors(thr);
if (info->mod_type[modular_id] == AVA4_TYPE_MM60) {
info->hw_works_i[modular_id][miner]++;
info->hw5_i[modular_id][miner][info->i_5s]++;
}
break;
}
}
if (!submit_nonce2_nonce(thr, pool, real_pool, nonce2, nonce, ntime)) {
if (info->mod_type[modular_id] == AVA4_TYPE_MM60) {
info->hw_works_i[modular_id][miner]++;
info->hw5_i[modular_id][miner][info->i_5s]++;
}
} else {
info->matching_work[modular_id][miner]++;
info->chipmatching_work[modular_id][miner][chip_id]++;
}
break;
case AVA4_P_STATUS:
applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS", avalon4->drv->name, avalon4->device_id, modular_id);
hexdump(ar->data, 32);
memcpy(&tmp, ar->data, 4);
tmp = be32toh(tmp);
info->temp[modular_id] = tmp;
memcpy(&tmp, ar->data + 4, 4);
tmp = be32toh(tmp);
info->fan[modular_id] = tmp;
memcpy(&(info->get_frequency[modular_id]), ar->data + 8, 4);
memcpy(&(info->get_voltage[modular_id]), ar->data + 12, 4);
memcpy(&(info->local_work[modular_id]), ar->data + 16, 4);
memcpy(&(info->hw_work[modular_id]), ar->data + 20, 4);
memcpy(&(info->power_good[modular_id]), ar->data + 24, 4);
memcpy(&(info->error_code[modular_id]), ar->data + 28, 4);
if (info->mod_type[modular_id] == AVA4_TYPE_MM60) {
if (info->total_asics[modular_id])
info->get_frequency[modular_id] = be32toh(info->get_frequency[modular_id]) / info->total_asics[modular_id];
} else
info->get_frequency[modular_id] = be32toh(info->get_frequency[modular_id]) * 3968 / 65;
info->get_voltage[modular_id] = be32toh(info->get_voltage[modular_id]);
info->local_work[modular_id] = be32toh(info->local_work[modular_id]);
info->hw_work[modular_id] = be32toh(info->hw_work[modular_id]);
info->power_good[modular_id] = be32toh(info->power_good[modular_id]);
info->error_code[modular_id] = be32toh(info->error_code[modular_id]);
volt = info->get_voltage[modular_id];
if (info->mod_type[modular_id] == AVA4_TYPE_MM40)
tmp = decode_voltage_adp3208d(volt);
if (info->mod_type[modular_id] == AVA4_TYPE_MM41)
tmp = decode_voltage_ncp5392p(volt);
if (info->mod_type[modular_id] == AVA4_TYPE_MM50)
tmp = decode_voltage_ncp5392p(volt);
/* TODO: fix it with the actual board */
if (info->mod_type[modular_id] == AVA4_TYPE_MM60)
tmp = decode_voltage_ncp5392p(volt);
info->get_voltage[modular_id] = tmp;
info->local_works[modular_id] += info->local_work[modular_id];
info->hw_works[modular_id] += info->hw_work[modular_id];
info->lw5[modular_id][info->i_5s] += info->local_work[modular_id];
info->hw5[modular_id][info->i_5s] += info->hw_work[modular_id];
avalon4->temp = get_current_temp_max(info);
break;
case AVA4_P_STATUS_LW:
applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS_LW", avalon4->drv->name, avalon4->device_id, modular_id);
for (i = 0; i < info->miner_count[modular_id]; i++) {
info->local_works_i[modular_id][i] += ((ar->data[i * 3] << 16) |
(ar->data[i * 3 + 1] << 8) |
(ar->data[i * 3 + 2]));
info->lw5_i[modular_id][i][info->i_5s] += ((ar->data[i * 3] << 16) |
(ar->data[i * 3 + 1] << 8) |
(ar->data[i * 3 + 2]));
}
break;
case AVA4_P_STATUS_HW:
applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS_HW", avalon4->drv->name, avalon4->device_id, modular_id);
if (info->mod_type[modular_id] == AVA4_TYPE_MM60) {
applog(LOG_NOTICE, "%s-%d-%d: AVA4_P_STATUS_HW found on Avalon6!", avalon4->drv->name, avalon4->device_id, modular_id);
break;
}
for (i = 0; i < info->miner_count[modular_id]; i++) {
info->hw_works_i[modular_id][i] += ((ar->data[i * 3] << 16) |
(ar->data[i * 3 + 1] << 8) |
(ar->data[i * 3 + 2]));
info->hw5_i[modular_id][i][info->i_5s] += ((ar->data[i * 3] << 16) |
(ar->data[i * 3 + 1] << 8) |
(ar->data[i * 3 + 2]));
}
break;
case AVA4_P_ACKDETECT:
applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_ACKDETECT", avalon4->drv->name, avalon4->device_id, modular_id);
break;
case AVA4_P_STATUS_VOLT:
applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS_VOLT", avalon4->drv->name, avalon4->device_id, modular_id);
hexdump(ar->data, 32);
for(i = 0; i < info->miner_count[modular_id]; i++) {
tmp = (ar->data[i * 2] << 8) + ar->data[i * 2 + 1];
if (info->mod_type[modular_id] == AVA4_TYPE_MM40)
tmp = decode_voltage_adp3208d(tmp);
if (info->mod_type[modular_id] == AVA4_TYPE_MM41)
tmp = decode_voltage_ncp5392p(tmp);
if (info->mod_type[modular_id] == AVA4_TYPE_MM50)
tmp = decode_voltage_ncp5392p(tmp);
/* TODO: fix it with the actual board */
if (info->mod_type[modular_id] == AVA4_TYPE_MM60)
tmp = decode_voltage_ncp5392p(tmp);
if (tmp < AVA4_DEFAULT_VOLTAGE_MIN || tmp > AVA4_DEFAULT_VOLTAGE_MAX) {
applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS_VOLT invalid voltage %d", avalon4->drv->name, avalon4->device_id, modular_id, tmp);
return 1;
}
val[((4 + i / 5 * 5) - i + (i / 5 * 5))] = tmp;
}
if (i == info->miner_count[modular_id]) {
for (i = 0; i < info->miner_count[modular_id]; i++) {
info->get_voltage_i[modular_id][i] = val[i];
}
}
break;
case AVA4_P_STATUS_MA:
applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS_MA", avalon4->drv->name, avalon4->device_id, modular_id);
for (i = 0; i < info->asic_count[modular_id]; i++)
info->ma_sum[modular_id][ar->opt][i] = ar->data[i];
break;
case AVA4_P_STATUS_M:
applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS_M", avalon4->drv->name, avalon4->device_id, modular_id);
for (i = 0; i < AVA4_DEFAULT_ADC_MAX; i++)
info->adc[modular_id][i] = (ar->data[2 * i] << 8) | ar->data[(2 * i) + 1];
/* MCU LED status --> data[2 * AVA4_DEFAULT_ADC : 2 * AVA4_DEFAULT_ADC_MAX + 3] */
for (i = 0; i < AVA4_DEFAULT_PLL_MAX; i++)
info->pll_sel[modular_id][i] = (ar->data[2 * (AVA4_DEFAULT_ADC_MAX + 2 + i)] << 8) |
ar->data[(2 * (AVA4_DEFAULT_ADC_MAX + 2 + i)) + 1];
break;
default:
applog(LOG_DEBUG, "%s-%d-%d: Unknown response", avalon4->drv->name, avalon4->device_id, modular_id);
break;
}
return 0;
}
/*
# IIC packet format: length[1]+transId[1]+sesId[1]+req[1]+data[60]
# length: 4+len(data)
# transId: 0
# sesId: 0
# req: checkout the header file
# data:
# INIT: clock_rate[4] + reserved[4] + payload[52]
# XFER: txSz[1]+rxSz[1]+options[1]+slaveAddr[1] + payload[56]
*/
static int avalon4_auc_init_pkg(uint8_t *iic_pkg, struct avalon4_iic_info *iic_info, uint8_t *buf, int wlen, int rlen)
{
memset(iic_pkg, 0, AVA4_AUC_P_SIZE);
switch (iic_info->iic_op) {
case AVA4_IIC_INIT:
iic_pkg[0] = 12; /* 4 bytes IIC header + 4 bytes speed + 4 bytes xfer delay */
iic_pkg[3] = AVA4_IIC_INIT;
iic_pkg[4] = iic_info->iic_param.aucParam[0] & 0xff;
iic_pkg[5] = (iic_info->iic_param.aucParam[0] >> 8) & 0xff;
iic_pkg[6] = (iic_info->iic_param.aucParam[0] >> 16) & 0xff;
iic_pkg[7] = iic_info->iic_param.aucParam[0] >> 24;
iic_pkg[8] = iic_info->iic_param.aucParam[1] & 0xff;
iic_pkg[9] = (iic_info->iic_param.aucParam[1] >> 8) & 0xff;
iic_pkg[10] = (iic_info->iic_param.aucParam[1] >> 16) & 0xff;
iic_pkg[11] = iic_info->iic_param.aucParam[1] >> 24;
break;
case AVA4_IIC_XFER:
iic_pkg[0] = 8 + wlen;
iic_pkg[3] = AVA4_IIC_XFER;
iic_pkg[4] = wlen;
iic_pkg[5] = rlen;
iic_pkg[7] = iic_info->iic_param.slave_addr;
if (buf && wlen)
memcpy(iic_pkg + 8, buf, wlen);
break;
case AVA4_IIC_RESET:
case AVA4_IIC_DEINIT:
case AVA4_IIC_INFO:
iic_pkg[0] = 4;
iic_pkg[3] = iic_info->iic_op;
break;
default:
break;
}
return 0;
}
static int avalon4_iic_xfer(struct cgpu_info *avalon4, uint8_t slave_addr,
uint8_t *wbuf, int wlen,
uint8_t *rbuf, int rlen)
{
struct avalon4_info *info = avalon4->device_data;
struct i2c_ctx *pctx = NULL;
int err = 1;
bool ret = false;
pctx = info->i2c_slaves[slave_addr];
if (!pctx) {
applog(LOG_ERR, "%s-%d: IIC xfer i2c slaves null!", avalon4->drv->name, avalon4->device_id);
goto out;
}
if (wbuf) {
ret = pctx->write_raw(pctx, wbuf, wlen);
if (!ret) {
applog(LOG_DEBUG, "%s-%d: IIC xfer write raw failed!", avalon4->drv->name, avalon4->device_id);
goto out;
}
}
cgsleep_ms(5);
if (rbuf) {
ret = pctx->read_raw(pctx, rbuf, rlen);
if (!ret) {
applog(LOG_DEBUG, "%s-%d: IIC xfer read raw failed!", avalon4->drv->name, avalon4->device_id);
hexdump(rbuf, rlen);
goto out;
}
}
return 0;
out:
return err;
}
static int avalon4_auc_xfer(struct cgpu_info *avalon4,
uint8_t *wbuf, int wlen, int *write,
uint8_t *rbuf, int rlen, int *read)
{
int err = -1;
if (unlikely(avalon4->usbinfo.nodev))
goto out;
usb_buffer_clear(avalon4);
err = usb_write(avalon4, (char *)wbuf, wlen, write, C_AVA4_WRITE);
if (err || *write != wlen) {
applog(LOG_DEBUG, "%s-%d: AUC xfer %d, w(%d-%d)!", avalon4->drv->name, avalon4->device_id, err, wlen, *write);
usb_nodev(avalon4);
goto out;
}
cgsleep_ms(opt_avalon4_aucxdelay / 4800 + 1);
rlen += 4; /* Add 4 bytes IIC header */
err = usb_read(avalon4, (char *)rbuf, rlen, read, C_AVA4_READ);
if (err || *read != rlen || *read != rbuf[0]) {
applog(LOG_DEBUG, "%s-%d: AUC xfer %d, r(%d-%d-%d)!", avalon4->drv->name, avalon4->device_id, err, rlen - 4, *read, rbuf[0]);
hexdump(rbuf, rlen);
return -1;
}
*read = rbuf[0] - 4; /* Remove 4 bytes IIC header */
out:
return err;
}
static int avalon4_auc_init(struct cgpu_info *avalon4, char *ver)
{
struct avalon4_iic_info iic_info;
int err, wlen, rlen;
uint8_t wbuf[AVA4_AUC_P_SIZE];
uint8_t rbuf[AVA4_AUC_P_SIZE];
if (unlikely(avalon4->usbinfo.nodev))
return 1;
/* Try to clean the AUC buffer */
usb_buffer_clear(avalon4);
err = usb_read(avalon4, (char *)rbuf, AVA4_AUC_P_SIZE, &rlen, C_AVA4_READ);
applog(LOG_DEBUG, "%s-%d: AUC usb_read %d, %d!", avalon4->drv->name, avalon4->device_id, err, rlen);
hexdump(rbuf, AVA4_AUC_P_SIZE);
/* Reset */
iic_info.iic_op = AVA4_IIC_RESET;
rlen = 0;
avalon4_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen);
memset(rbuf, 0, AVA4_AUC_P_SIZE);
err = avalon4_auc_xfer(avalon4, wbuf, AVA4_AUC_P_SIZE, &wlen, rbuf, rlen, &rlen);
if (err) {
applog(LOG_ERR, "%s-%d: Failed to reset Avalon USB2IIC Converter", avalon4->drv->name, avalon4->device_id);
return 1;
}
/* Deinit */
iic_info.iic_op = AVA4_IIC_DEINIT;
rlen = 0;
avalon4_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen);
memset(rbuf, 0, AVA4_AUC_P_SIZE);
err = avalon4_auc_xfer(avalon4, wbuf, AVA4_AUC_P_SIZE, &wlen, rbuf, rlen, &rlen);
if (err) {
applog(LOG_ERR, "%s-%d: Failed to deinit Avalon USB2IIC Converter", avalon4->drv->name, avalon4->device_id);
return 1;
}
/* Init */
iic_info.iic_op = AVA4_IIC_INIT;
iic_info.iic_param.aucParam[0] = opt_avalon4_aucspeed;
iic_info.iic_param.aucParam[1] = opt_avalon4_aucxdelay;
rlen = AVA4_AUC_VER_LEN;
avalon4_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen);
memset(rbuf, 0, AVA4_AUC_P_SIZE);
err = avalon4_auc_xfer(avalon4, wbuf, AVA4_AUC_P_SIZE, &wlen, rbuf, rlen, &rlen);
if (err) {
applog(LOG_ERR, "%s-%d: Failed to init Avalon USB2IIC Converter", avalon4->drv->name, avalon4->device_id);
return 1;
}
hexdump(rbuf, AVA4_AUC_P_SIZE);
memcpy(ver, rbuf + 4, AVA4_AUC_VER_LEN);
ver[AVA4_AUC_VER_LEN] = '\0';
applog(LOG_DEBUG, "%s-%d: USB2IIC Converter version: %s!", avalon4->drv->name, avalon4->device_id, ver);
return 0;
}
static int avalon4_auc_getinfo(struct cgpu_info *avalon4)
{
struct avalon4_iic_info iic_info;
int err, wlen, rlen;
uint8_t wbuf[AVA4_AUC_P_SIZE];
uint8_t rbuf[AVA4_AUC_P_SIZE];
uint8_t *pdata = rbuf + 4;
uint16_t adc_val;
struct avalon4_info *info = avalon4->device_data;
iic_info.iic_op = AVA4_IIC_INFO;
/* Device info: (9 bytes)
* tempadc(2), reqRdIndex, reqWrIndex,
* respRdIndex, respWrIndex, tx_flags, state
* */
rlen = 7;
avalon4_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen);
memset(rbuf, 0, AVA4_AUC_P_SIZE);
err = avalon4_auc_xfer(avalon4, wbuf, AVA4_AUC_P_SIZE, &wlen, rbuf, rlen, &rlen);
if (err) {
applog(LOG_ERR, "%s-%d: AUC Failed to get info ", avalon4->drv->name, avalon4->device_id);
return 1;
}
applog(LOG_DEBUG, "%s-%d: AUC tempADC(%03d), reqcnt(%d), respcnt(%d), txflag(%d), state(%d)",
avalon4->drv->name, avalon4->device_id,
pdata[1] << 8 | pdata[0],
pdata[2],
pdata[3],
pdata[5] << 8 | pdata[4],
pdata[6]);
adc_val = pdata[1] << 8 | pdata[0];
info->auc_temp = 3.3 * adc_val * 10000 / 1023;
return 0;
}
static int avalon4_iic_xfer_pkg(struct cgpu_info *avalon4, uint8_t slave_addr,
const struct avalon4_pkg *pkg, struct avalon4_ret *ret)
{
struct avalon4_iic_info iic_info;
int err, wcnt, rcnt, rlen = 0;
uint8_t wbuf[AVA4_AUC_P_SIZE];
uint8_t rbuf[AVA4_AUC_P_SIZE];
struct avalon4_info *info = avalon4->device_data;
if (ret)
rlen = AVA4_READ_SIZE;
if (info->connecter == AVA4_CONNECTER_AUC) {
if (unlikely(avalon4->usbinfo.nodev))
return AVA4_SEND_ERROR;
iic_info.iic_op = AVA4_IIC_XFER;
iic_info.iic_param.slave_addr = slave_addr;
avalon4_auc_init_pkg(wbuf, &iic_info, (uint8_t *)pkg, AVA4_WRITE_SIZE, rlen);
err = avalon4_auc_xfer(avalon4, wbuf, wbuf[0], &wcnt, rbuf, rlen, &rcnt);
if ((pkg->type != AVA4_P_DETECT) && err == -7 && !rcnt && rlen) {
avalon4_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen);
err = avalon4_auc_xfer(avalon4, wbuf, wbuf[0], &wcnt, rbuf, rlen, &rcnt);
applog(LOG_DEBUG, "%s-%d-%d: AUC read again!(type:0x%x, err:%d)", avalon4->drv->name, avalon4->device_id, slave_addr, pkg->type, err);
}
if (err || rcnt != rlen) {
if (info->xfer_err_cnt++ == 100) {
applog(LOG_DEBUG, "%s-%d-%d: AUC xfer_err_cnt reach err = %d, rcnt = %d, rlen = %d",
avalon4->drv->name, avalon4->device_id, slave_addr,
err, rcnt, rlen);
cgsleep_ms(5 * 1000); /* Wait MM reset */
avalon4_auc_init(avalon4, info->auc_version);
}
return AVA4_SEND_ERROR;
}
if (ret)
memcpy((char *)ret, rbuf + 4, AVA4_READ_SIZE);
info->xfer_err_cnt = 0;
}
if (info->connecter == AVA4_CONNECTER_IIC) {
err = avalon4_iic_xfer(avalon4, slave_addr, (uint8_t *)pkg, AVA4_WRITE_SIZE, (uint8_t *)ret, AVA4_READ_SIZE);
if ((pkg->type != AVA4_P_DETECT) && err) {
err = avalon4_iic_xfer(avalon4, slave_addr, (uint8_t *)pkg, AVA4_WRITE_SIZE, (uint8_t *)ret, AVA4_READ_SIZE);
applog(LOG_DEBUG, "%s-%d-%d: IIC read again!(type:0x%x, err:%d)", avalon4->drv->name, avalon4->device_id, slave_addr, pkg->type, err);
}
if (err) {
/* FIXME: Don't care broadcast message with no reply, or it will block other thread when called by avalon4_send_bc_pkgs */
if ((pkg->type != AVA4_P_DETECT) && (slave_addr == AVA4_MODULE_BROADCAST))
return AVA4_SEND_OK;
if (info->xfer_err_cnt++ == 100) {
info->xfer_err_cnt = 0;
applog(LOG_DEBUG, "%s-%d-%d: IIC xfer_err_cnt reach err = %d, rcnt = %d, rlen = %d",
avalon4->drv->name, avalon4->device_id, slave_addr,
err, rcnt, rlen);
cgsleep_ms(5 * 1000); /* Wait MM reset */
}
return AVA4_SEND_ERROR;
}
info->xfer_err_cnt = 0;
}
return AVA4_SEND_OK;
}
static int avalon4_send_bc_pkgs(struct cgpu_info *avalon4, const struct avalon4_pkg *pkg)
{
int ret;
do {
ret = avalon4_iic_xfer_pkg(avalon4, AVA4_MODULE_BROADCAST, pkg, NULL);
} while (ret != AVA4_SEND_OK);
return 0;
}
static void avalon4_stratum_pkgs(struct cgpu_info *avalon4, struct pool *pool)
{
struct avalon4_info *info = avalon4->device_data;
const int merkle_offset = 36;
struct avalon4_pkg pkg;
int i, a, b, tmp;
unsigned char target[32];
int job_id_len, n2size;