-
Notifications
You must be signed in to change notification settings - Fork 1
/
Copy pathvivado_16564.backup.log
935 lines (919 loc) · 64.3 KB
/
vivado_16564.backup.log
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
#-----------------------------------------------------------
# Vivado v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Sun Jun 11 20:05:47 2023
# Process ID: 16564
# Current directory: E:/Xilinx/Projects/Nano Processor Final
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent17412 E:\Xilinx\Projects\Nano Processor Final\Nano Processor Final.xpr
# Log file: E:/Xilinx/Projects/Nano Processor Final/vivado.log
# Journal file: E:/Xilinx/Projects/Nano Processor Final\vivado.jou
#-----------------------------------------------------------
start_gui
open_project {E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.xpr}
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2018.2/data/ip'.
open_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 840.477 ; gain = 102.605
update_compile_order -fileset sources_1
reset_run synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/synth_1
launch_runs impl_1 -jobs 4
[Sun Jun 11 21:10:50 2023] Launched synth_1...
Run output will be captured here: E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/synth_1/runme.log
[Sun Jun 11 21:10:50 2023] Launched impl_1...
Run output will be captured here: E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/impl_1/runme.log
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'System_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj System_TB_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sources_1/new/LUT_16_7.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity LUT_16_7
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sources_1/new/Nano_Processor.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Nano_Processor
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sources_1/new/Slow_Clock.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Slow_Clock
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sources_1/new/System.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity System
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 872.977 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '7' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: E:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 67a5dd7157414ed9814149af3173682b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot System_TB_behav xil_defaultlib.System_TB -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.LUT_16_7 [lut_16_7_default]
Compiling architecture behavioral of entity xil_defaultlib.Slow_Clock [slow_clock_default]
Compiling architecture behavioral of entity xil_defaultlib.Reg_3bit [reg_3bit_default]
Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default]
Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default]
Compiling architecture behavioral of entity xil_defaultlib.Adder_3bit [adder_3bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Mux_2_to_1_3bit [mux_2_to_1_3bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Program_ROM [program_rom_default]
Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default]
Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default]
Compiling architecture behavioral of entity xil_defaultlib.Mux_2_to_1_4bit [mux_2_to_1_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Reg_4bit [reg_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default]
Compiling architecture behavioral of entity xil_defaultlib.Register_Bank [register_bank_default]
Compiling architecture behavioral of entity xil_defaultlib.Mux_8_to_1_4bit [mux_8_to_1_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.ASU_4bit [asu_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Nano_Processor [nano_processor_default]
Compiling architecture behavioral of entity xil_defaultlib.System [system_default]
Compiling architecture behavioral of entity xil_defaultlib.system_tb
Built simulation snapshot System_TB_behav
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:08 . Memory (MB): peak = 872.977 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '8' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "System_TB_behav -key {Behavioral:sim_1:Functional:System_TB} -tclbatch {System_TB.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source System_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
xsim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 883.680 ; gain = 10.703
INFO: [USF-XSim-96] XSim completed. Design snapshot 'System_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:24 . Memory (MB): peak = 883.680 ; gain = 10.703
reset_run synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/synth_1
launch_runs impl_1 -jobs 4
[Sun Jun 11 21:37:05 2023] Launched synth_1...
Run output will be captured here: E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/synth_1/runme.log
[Sun Jun 11 21:37:05 2023] Launched impl_1...
Run output will be captured here: E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/impl_1/runme.log
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'System_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj System_TB_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sources_1/new/Nano_Processor.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Nano_Processor
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sources_1/new/Program_ROM.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Program_ROM
INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: E:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 67a5dd7157414ed9814149af3173682b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot System_TB_behav xil_defaultlib.System_TB -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.LUT_16_7 [lut_16_7_default]
Compiling architecture behavioral of entity xil_defaultlib.Slow_Clock [slow_clock_default]
Compiling architecture behavioral of entity xil_defaultlib.Reg_3bit [reg_3bit_default]
Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default]
Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default]
Compiling architecture behavioral of entity xil_defaultlib.Adder_3bit [adder_3bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Mux_2_to_1_3bit [mux_2_to_1_3bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Program_ROM [program_rom_default]
Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default]
Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default]
Compiling architecture behavioral of entity xil_defaultlib.Mux_2_to_1_4bit [mux_2_to_1_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Reg_4bit [reg_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default]
Compiling architecture behavioral of entity xil_defaultlib.Register_Bank [register_bank_default]
Compiling architecture behavioral of entity xil_defaultlib.Mux_8_to_1_4bit [mux_8_to_1_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.ASU_4bit [asu_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Nano_Processor [nano_processor_default]
Compiling architecture behavioral of entity xil_defaultlib.System [system_default]
Compiling architecture behavioral of entity xil_defaultlib.system_tb
Built simulation snapshot System_TB_behav
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 891.695 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "System_TB_behav -key {Behavioral:sim_1:Functional:System_TB} -tclbatch {System_TB.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source System_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'System_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:15 . Memory (MB): peak = 892.238 ; gain = 0.543
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'System_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj System_TB_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: E:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 67a5dd7157414ed9814149af3173682b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot System_TB_behav xil_defaultlib.System_TB -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "System_TB_behav -key {Behavioral:sim_1:Functional:System_TB} -tclbatch {System_TB.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source System_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'System_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 893.402 ; gain = 0.000
reset_run synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/synth_1
launch_runs impl_1 -jobs 4
[Sun Jun 11 22:07:14 2023] Launched synth_1...
Run output will be captured here: E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/synth_1/runme.log
[Sun Jun 11 22:07:14 2023] Launched impl_1...
Run output will be captured here: E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/impl_1/runme.log
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'System_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj System_TB_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sources_1/new/Nano_Processor.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Nano_Processor
INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: E:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 67a5dd7157414ed9814149af3173682b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot System_TB_behav xil_defaultlib.System_TB -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.LUT_16_7 [lut_16_7_default]
Compiling architecture behavioral of entity xil_defaultlib.Slow_Clock [slow_clock_default]
Compiling architecture behavioral of entity xil_defaultlib.Reg_3bit [reg_3bit_default]
Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default]
Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default]
Compiling architecture behavioral of entity xil_defaultlib.Adder_3bit [adder_3bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Mux_2_to_1_3bit [mux_2_to_1_3bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Program_ROM [program_rom_default]
Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default]
Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default]
Compiling architecture behavioral of entity xil_defaultlib.Mux_2_to_1_4bit [mux_2_to_1_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Reg_4bit [reg_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default]
Compiling architecture behavioral of entity xil_defaultlib.Register_Bank [register_bank_default]
Compiling architecture behavioral of entity xil_defaultlib.Mux_8_to_1_4bit [mux_8_to_1_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.ASU_4bit [asu_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Nano_Processor [nano_processor_default]
Compiling architecture behavioral of entity xil_defaultlib.System [system_default]
Compiling architecture behavioral of entity xil_defaultlib.system_tb
Built simulation snapshot System_TB_behav
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 896.953 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "System_TB_behav -key {Behavioral:sim_1:Functional:System_TB} -tclbatch {System_TB.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source System_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'System_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:14 . Memory (MB): peak = 896.953 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
reset_run synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/synth_1
launch_runs impl_1 -jobs 4
[Sun Jun 11 22:30:50 2023] Launched synth_1...
Run output will be captured here: E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/synth_1/runme.log
[Sun Jun 11 22:30:50 2023] Launched impl_1...
Run output will be captured here: E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/impl_1/runme.log
reset_run synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/synth_1
launch_runs synth_1 -jobs 4
[Sun Jun 11 22:32:30 2023] Launched synth_1...
Run output will be captured here: E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/synth_1/runme.log
launch_runs impl_1 -jobs 4
[Sun Jun 11 22:33:22 2023] Launched impl_1...
Run output will be captured here: E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/impl_1/runme.log
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'System_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj System_TB_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sources_1/new/Nano_Processor.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Nano_Processor
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sources_1/new/Slow_Clock.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Slow_Clock
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sources_1/new/System.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity System
INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: E:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 67a5dd7157414ed9814149af3173682b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot System_TB_behav xil_defaultlib.System_TB -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-718] formal port <ResetPush> does not exist in entity <System>. Please compare the definition of block <System> to its component declaration and its instantion to detect the mismatch. [E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/System_TB.vhd:12]
ERROR: [VRFC 10-718] formal port <Seg7> does not exist in entity <System>. Please compare the definition of block <System> to its component declaration and its instantion to detect the mismatch. [E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/System_TB.vhd:13]
ERROR: [VRFC 10-718] formal port <Reg7> does not exist in entity <System>. Please compare the definition of block <System> to its component declaration and its instantion to detect the mismatch. [E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/System_TB.vhd:15]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit system_tb in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-99] Step results log file:'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:09 . Memory (MB): peak = 903.648 ; gain = 4.715
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'System_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj System_TB_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: E:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 67a5dd7157414ed9814149af3173682b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot System_TB_behav xil_defaultlib.System_TB -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-718] formal port <ResetPush> does not exist in entity <System>. Please compare the definition of block <System> to its component declaration and its instantion to detect the mismatch. [E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/System_TB.vhd:12]
ERROR: [VRFC 10-718] formal port <Seg7> does not exist in entity <System>. Please compare the definition of block <System> to its component declaration and its instantion to detect the mismatch. [E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/System_TB.vhd:13]
ERROR: [VRFC 10-718] formal port <Reg7> does not exist in entity <System>. Please compare the definition of block <System> to its component declaration and its instantion to detect the mismatch. [E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/System_TB.vhd:15]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit system_tb in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'System_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj System_TB_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: E:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 67a5dd7157414ed9814149af3173682b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot System_TB_behav xil_defaultlib.System_TB -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-718] formal port <ResetPush> does not exist in entity <System>. Please compare the definition of block <System> to its component declaration and its instantion to detect the mismatch. [E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/System_TB.vhd:12]
ERROR: [VRFC 10-718] formal port <Seg7> does not exist in entity <System>. Please compare the definition of block <System> to its component declaration and its instantion to detect the mismatch. [E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/System_TB.vhd:13]
ERROR: [VRFC 10-718] formal port <Reg7> does not exist in entity <System>. Please compare the definition of block <System> to its component declaration and its instantion to detect the mismatch. [E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/System_TB.vhd:15]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit system_tb in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-99] Step results log file:'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 906.785 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
reset_run synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/synth_1
launch_runs impl_1 -jobs 4
[Sun Jun 11 22:41:13 2023] Launched synth_1...
Run output will be captured here: E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/synth_1/runme.log
[Sun Jun 11 22:41:13 2023] Launched impl_1...
Run output will be captured here: E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/impl_1/runme.log
reset_run synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/synth_1
launch_runs synth_1 -jobs 4
[Sun Jun 11 22:44:18 2023] Launched synth_1...
Run output will be captured here: E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/synth_1/runme.log
launch_runs impl_1 -jobs 4
[Sun Jun 11 22:48:32 2023] Launched impl_1...
Run output will be captured here: E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/impl_1/runme.log
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'System_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj System_TB_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/System_TB.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity System_TB
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 912.555 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '5' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: E:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 67a5dd7157414ed9814149af3173682b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot System_TB_behav xil_defaultlib.System_TB -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.LUT_16_7 [lut_16_7_default]
Compiling architecture behavioral of entity xil_defaultlib.Slow_Clock [slow_clock_default]
Compiling architecture behavioral of entity xil_defaultlib.Reg_3bit [reg_3bit_default]
Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default]
Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default]
Compiling architecture behavioral of entity xil_defaultlib.Adder_3bit [adder_3bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Mux_2_to_1_3bit [mux_2_to_1_3bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Program_ROM [program_rom_default]
Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default]
Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default]
Compiling architecture behavioral of entity xil_defaultlib.Mux_2_to_1_4bit [mux_2_to_1_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Reg_4bit [reg_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default]
Compiling architecture behavioral of entity xil_defaultlib.Register_Bank [register_bank_default]
Compiling architecture behavioral of entity xil_defaultlib.Mux_8_to_1_4bit [mux_8_to_1_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.ASU_4bit [asu_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Nano_Processor [nano_processor_default]
Compiling architecture behavioral of entity xil_defaultlib.System [system_default]
Compiling architecture behavioral of entity xil_defaultlib.system_tb
Built simulation snapshot System_TB_behav
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 912.555 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '7' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "System_TB_behav -key {Behavioral:sim_1:Functional:System_TB} -tclbatch {System_TB.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source System_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'System_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:18 . Memory (MB): peak = 917.219 ; gain = 4.664
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open {E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Nano_Processor_TB.vhd} w ]
add_files -fileset sim_1 {{E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Nano_Processor_TB.vhd}}
update_compile_order -fileset sim_1
set_property top Nano_Processor_TB [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
set_property top Nano_Processor [current_fileset]
update_compile_order -fileset sim_1
update_compile_order -fileset sources_1
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Nano_Processor_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Nano_Processor_TB_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Nano_Processor_TB.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Nano_Processor_TB
INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: E:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 67a5dd7157414ed9814149af3173682b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Nano_Processor_TB_behav xil_defaultlib.Nano_Processor_TB -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-122] nanoprocessor remains a black-box since it has no binding entity [E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Nano_Processor_TB.vhd:29]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling architecture behavioral of entity xil_defaultlib.nano_processor_tb
Built simulation snapshot Nano_Processor_TB_behav
****** Webtalk v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source E:/Xilinx/Projects/Nano -notrace
couldn't read file "E:/Xilinx/Projects/Nano": permission denied
INFO: [Common 17-206] Exiting Webtalk at Sun Jun 11 23:10:03 2023...
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:08 . Memory (MB): peak = 923.973 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '8' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "Nano_Processor_TB_behav -key {Behavioral:sim_1:Functional:Nano_Processor_TB} -tclbatch {Nano_Processor_TB.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source Nano_Processor_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Nano_Processor_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:16 . Memory (MB): peak = 930.168 ; gain = 6.195
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Nano_Processor_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Nano_Processor_TB_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Nano_Processor_TB.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Nano_Processor_TB
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: E:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 67a5dd7157414ed9814149af3173682b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Nano_Processor_TB_behav xil_defaultlib.Nano_Processor_TB -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-122] nanoprocessor remains a black-box since it has no binding entity [E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Nano_Processor_TB.vhd:26]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling architecture behavioral of entity xil_defaultlib.nano_processor_tb
Built simulation snapshot Nano_Processor_TB_behav
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 933.984 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '8' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "Nano_Processor_TB_behav -key {Behavioral:sim_1:Functional:Nano_Processor_TB} -tclbatch {Nano_Processor_TB.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source Nano_Processor_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Nano_Processor_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:13 . Memory (MB): peak = 933.984 ; gain = 0.000
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open {E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Instruction_Decoder_TB.vhd} w ]
add_files -fileset sim_1 {{E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Instruction_Decoder_TB.vhd}}
close_sim
INFO: [Simtcl 6-16] Simulation closed
update_compile_order -fileset sim_1
set_property top Instruction_Decoder [current_fileset]
set_property top InstructionDecoderNew_sim [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
set_property top Instruction_Decoder_TB [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
update_compile_order -fileset sim_1
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Instruction_Decoder_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Instruction_Decoder_TB_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sources_1/new/Instruction_Decoder.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Instruction_Decoder
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Instruction_Decoder_TB.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Instruction_Decoder_TB
INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: E:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 67a5dd7157414ed9814149af3173682b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Instruction_Decoder_TB_behav xil_defaultlib.Instruction_Decoder_TB -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default]
Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default]
Compiling architecture behavioral of entity xil_defaultlib.instruction_decoder_tb
Built simulation snapshot Instruction_Decoder_TB_behav
****** Webtalk v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source E:/Xilinx/Projects/Nano -notrace
couldn't read file "E:/Xilinx/Projects/Nano": permission denied
INFO: [Common 17-206] Exiting Webtalk at Sun Jun 11 23:22:27 2023...
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:10 . Memory (MB): peak = 933.984 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "Instruction_Decoder_TB_behav -key {Behavioral:sim_1:Functional:Instruction_Decoder_TB} -tclbatch {Instruction_Decoder_TB.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source Instruction_Decoder_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Instruction_Decoder_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:17 . Memory (MB): peak = 933.984 ; gain = 0.000
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open {E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Program_ROM_TB.vhd} w ]
add_files -fileset sim_1 {{E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Program_ROM_TB.vhd}}
update_compile_order -fileset sim_1
current_sim simulation_5
close_sim
INFO: [Simtcl 6-16] Simulation closed
export_ip_user_files -of_objects [get_files {{E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Program_ROM_TB.vhd}}] -no_script -reset -force -quiet
remove_files -fileset sim_1 {{E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Program_ROM_TB.vhd}}
file delete -force {E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Program_ROM_TB.vhd}
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open {E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Register_Bank_TB.vhd} w ]
add_files -fileset sim_1 {{E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Register_Bank_TB.vhd}}
update_compile_order -fileset sim_1
set_property top Register_Bank_TB [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
set_property top Register_Bank [current_fileset]
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Register_Bank_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Register_Bank_TB_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Register_Bank_TB.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Register_Bank_TB
INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: E:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 67a5dd7157414ed9814149af3173682b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Register_Bank_TB_behav xil_defaultlib.Register_Bank_TB -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-718] formal port <Output> does not exist in entity <Register_Bank>. Please compare the definition of block <Register_Bank> to its component declaration and its instantion to detect the mismatch. [E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Register_Bank_TB.vhd:14]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit register_bank_tb in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-99] Step results log file:'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 935.578 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Register_Bank_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Register_Bank_TB_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Register_Bank_TB.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Register_Bank_TB
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: E:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 67a5dd7157414ed9814149af3173682b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Register_Bank_TB_behav xil_defaultlib.Register_Bank_TB -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling architecture behavioral of entity xil_defaultlib.Reg_4bit [reg_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default]
Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default]
Compiling architecture behavioral of entity xil_defaultlib.Register_Bank [register_bank_default]
Compiling architecture behavioral of entity xil_defaultlib.register_bank_tb
Built simulation snapshot Register_Bank_TB_behav
****** Webtalk v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source E:/Xilinx/Projects/Nano -notrace
couldn't read file "E:/Xilinx/Projects/Nano": permission denied
INFO: [Common 17-206] Exiting Webtalk at Sun Jun 11 23:36:05 2023...
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 935.578 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "Register_Bank_TB_behav -key {Behavioral:sim_1:Functional:Register_Bank_TB} -tclbatch {Register_Bank_TB.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source Register_Bank_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Register_Bank_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:12 . Memory (MB): peak = 939.852 ; gain = 4.273
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open {E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Slow_Clock_TB.vhd} w ]
add_files -fileset sim_1 {{E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Slow_Clock_TB.vhd}}
update_compile_order -fileset sim_1
set_property top Slow_Clock_TB [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
set_property top Slow_Clock [current_fileset]
update_compile_order -fileset sim_1
update_compile_order -fileset sources_1
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Slow_Clock_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Slow_Clock_TB_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Slow_Clock_TB.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Slow_Clock_TB
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: E:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 67a5dd7157414ed9814149af3173682b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Slow_Clock_TB_behav xil_defaultlib.Slow_Clock_TB -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling architecture behavioral of entity xil_defaultlib.Slow_Clock [slow_clock_default]
Compiling architecture behavioral of entity xil_defaultlib.slow_clock_tb
Built simulation snapshot Slow_Clock_TB_behav
****** Webtalk v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source E:/Xilinx/Projects/Nano -notrace
couldn't read file "E:/Xilinx/Projects/Nano": permission denied
INFO: [Common 17-206] Exiting Webtalk at Sun Jun 11 23:40:25 2023...
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 941.789 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "Slow_Clock_TB_behav -key {Behavioral:sim_1:Functional:Slow_Clock_TB} -tclbatch {Slow_Clock_TB.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source Slow_Clock_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Slow_Clock_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 950.477 ; gain = 8.719
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open {E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Adder_3bit_TB.vhd} w ]
add_files -fileset sim_1 {{E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/Adder_3bit_TB.vhd}}
update_compile_order -fileset sim_1
set_property top System_TB [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
update_compile_order -fileset sim_1
set_property top System [current_fileset]
update_compile_order -fileset sources_1
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open {E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/AS_4bit_TB.vhd} w ]
add_files -fileset sim_1 {{E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/AS_4bit_TB.vhd}}
update_compile_order -fileset sim_1
reset_run synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/synth_1
launch_runs synth_1 -jobs 4
[Sun Jun 11 23:58:00 2023] Launched synth_1...
Run output will be captured here: E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/synth_1/runme.log
launch_runs impl_1 -jobs 4
[Mon Jun 12 00:00:30 2023] Launched impl_1...
Run output will be captured here: E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/impl_1/runme.log
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Mon Jun 12 00:03:15 2023] Launched impl_1...
Run output will be captured here: E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.runs/impl_1/runme.log
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'System_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj System_TB_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sources_1/new/Nano_Processor.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Nano_Processor
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.srcs/sim_1/new/System_TB.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity System_TB
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 959.359 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '5' seconds
INFO: [USF-XSim-3] XSim::Elaborate design