diff --git a/projects.yaml b/projects.yaml index 411362396b..31f0c2609f 100644 --- a/projects.yaml +++ b/projects.yaml @@ -53,6 +53,9 @@ module: hic_lpc4322: &module_hic_lpc4322 - records/rtos/rtos-cm3.yaml - records/hic_hal/lpc4322.yaml + hic_psoc5lp: &module_hic_psoc5lp + - records/rtos/rtos-cm3.yaml + - records/hic_hal/psoc5lp.yaml hic_sam3u2c: &module_hic_sam3u2c - records/rtos/rtos-cm3.yaml - records/hic_hal/sam3u2c.yaml @@ -595,3 +598,11 @@ projects: - *module_if - *module_hic_max32625 - records/board/max32630fthr.yaml + psoc5lp_bl: + - *module_bl + - *module_hic_psoc5lp + - records/board/psoc5lp_bl.yaml + psoc5lp_cy8ckit_if: + - *module_if + - *module_hic_psoc5lp + - records/board/cy8ckit.yaml diff --git a/records/board/cy8ckit.yaml b/records/board/cy8ckit.yaml new file mode 100644 index 0000000000..c6ca866df2 --- /dev/null +++ b/records/board/cy8ckit.yaml @@ -0,0 +1,14 @@ +common: + macros: + - TARGET_MCU_PSOC6 + includes: + - source/family/cypress/PSoC6xxx + sources: + board: + - source/board/cy8ckit.c + target: + - source/family/cypress/target.c + - source/family/cypress/target_reset.c + - source/family/cypress/PSoC6xxx/PSOC6xxx.c + + diff --git a/records/board/psoc5lp_bl.yaml b/records/board/psoc5lp_bl.yaml new file mode 100644 index 0000000000..6390515b23 --- /dev/null +++ b/records/board/psoc5lp_bl.yaml @@ -0,0 +1,4 @@ +common: + sources: + board: + - source/board/psoc5lp_bl.c diff --git a/records/hic_hal/psoc5lp.yaml b/records/hic_hal/psoc5lp.yaml new file mode 100644 index 0000000000..38310aa5c8 --- /dev/null +++ b/records/hic_hal/psoc5lp.yaml @@ -0,0 +1,27 @@ +common: + target: + - CY8C5868LTI-LP039 + core: + - Cortex-M3 + macros: + - OS_CLOCK=64000000 + - DAPLINK_HIC_ID=0x2E127069 # DAPLINK_HIC_ID_PSOC5LP + includes: + - source/hic_hal/cypress/psoc5lp + - source/hic_hal/cypress/psoc5lp/PSoC5 + - projectfiles/uvision/psoc5lp_bl/build + sources: + hic_hal: + - source/hic_hal/cypress/psoc5lp + - source/hic_hal/cypress/psoc5lp/PSoC5 + - source/hic_hal/cypress/psoc5lp/armcc + +tool_specific: + uvision: + misc: + ld_flags: + - --predefine="-I..\..\..\source\hic_hal\cypress\psoc5lp" + make_armcc: + misc: + ld_flags: + - --predefine="-Isource\hic_hal\cypress\psoc5lp" diff --git a/source/board/cy8ckit.c b/source/board/cy8ckit.c new file mode 100644 index 0000000000..766acf45fd --- /dev/null +++ b/source/board/cy8ckit.c @@ -0,0 +1,352 @@ +/******************************************************************************* +* @file cy8ckit.c +* @brief Board ID definitions for all Cypress povided kits. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "target_family.h" +#include "target_board.h" + +#include "CyLib.h" +#include "Pin_VoltageEn.h" +#include "target_reset.h" +#include "EEPROM_ModeStorage.h" +#include "PSOC6xxx.h" + +// Minimum flashboot version with sflash restriction +#define MIN_FB_SR_VER (0x24000000u) + +// Maximum count of supported HW ids +#define MAX_SUPPORTED_HWID (13u) + +// Silicon ids (To add new clear revion bits) +#define CY8CPROTO_062_4343W_SIID (0xE4020002u) +#define CY8CKIT_062_BLE_SIID (0xE2070000u) +#define CY8CKIT_062_WIFI_BT_SIID (0xE2060000u) +#define CYW943012P6EVB_01_SIID (0xE2060000u) +#define CY8CKIT_062_4343W_SIID (0xE4020002u) +#define CY8CPROTO_062_43012_SIID (0xE4020102u) // Added revision number to avoid twins +#define CY8CPROTO_063_BLE_SIID (0xE2F00000u) +#define CY8CPROTO_062S2_43012_SIID (0xE4020002u) +#define CY8CPROTO_064_SB_SIID (0xE2620000u) // CYB06447BZI-D54 + +// Unique ID record header +#define UID_PSOC5_HEADER (0x6970122Eu) + +#define P5LP_EEPROM_ROW_SIZE (16u) +#define CRC8_2S_COMP_BASE (0x0100u) + +// Unique ID record struct +typedef struct __attribute__((packed)) unique_id_struct +{ + uint32_t signature; // Unique id header (PSoC5 silicon ID) - 4 bytes + char mbed_board_id[4]; // mbed ID - 4 bytes + uint16_t uid; // Unique kit ID - 2 bytes + uint64_t feature_list; // Kit feature list - 8 bytes + char name[32]; // Full kit name - 32 bytes + uint8_t hw_id; // Kit HW id - 1 byte + uint32_t target_siid; // Target silicon id - 4 bytes + uint16_t ver; // Record version(1 byte for major part, 1 byte for minor part) - 2 bytes + uint8_t resrved[6]; // Reserved for future use - 6 bytes + uint8_t checksum; // Record checksum - 1 byte +} unique_id_struct_t; + +// Board properties struct definition +typedef struct +{ + bool kitHasThreeLeds; /**< Kit has three lEDs, assuming in false case kit has single LED */ + bool kitHasTwoButtons; /**< Kit has two buttons, assuming in false case kit has single button */ +} board_properties_t; + +const board_properties_t board_config[MAX_SUPPORTED_HWID + 1u] = +{ + [0] = { .kitHasThreeLeds = false, .kitHasTwoButtons = false }, /* HWID = 0 */ + [1] = { .kitHasThreeLeds = true, . kitHasTwoButtons = false }, /* HWID = 1 */ + [2] = { .kitHasThreeLeds = true, . kitHasTwoButtons = true }, /* HWID = 2 */ + [3] = { .kitHasThreeLeds = false, .kitHasTwoButtons = false }, /* HWID = 3 */ + [4] = { .kitHasThreeLeds = false, .kitHasTwoButtons = false }, /* HWID = 4 */ + [5] = { .kitHasThreeLeds = true, . kitHasTwoButtons = true }, /* HWID = 5 */ + [6] = { .kitHasThreeLeds = false, .kitHasTwoButtons = false }, /* HWID = 6 */ + [7] = { .kitHasThreeLeds = true, . kitHasTwoButtons = true }, /* HWID = 7 */ + [8] = { .kitHasThreeLeds = false, .kitHasTwoButtons = false }, /* HWID = 8 */ + [9] = { .kitHasThreeLeds = false, .kitHasTwoButtons = false }, /* HWID = 9 */ + [10] = { .kitHasThreeLeds = true, . kitHasTwoButtons = true }, /* HWID = 10(0x0A) */ + [11] = { .kitHasThreeLeds = false, .kitHasTwoButtons = false }, /* HWID = 11(0x0B) */ + [12] = { .kitHasThreeLeds = true, . kitHasTwoButtons = true }, /* HWID = 12(0x0C) */ + [13] = { .kitHasThreeLeds = false, .kitHasTwoButtons = false } /* HWID = 13(0x0D) */ +}; + +unique_id_struct_t id; + +// Kits unique ID enums +typedef enum names +{ + CY8CKIT_062_BLE = 0x0005u, + CY8CKIT_062_WIFI_BT = 0x0006u, + CY8CPROTO_063_BLE = 0x000Bu, + CY8CPROTO_062_4343W = 0x0010u, + CY8CPROTO_062_43012 = 0x0011u, + CY8CPROTO_064_SB = 0x0012u, + CYW943012P6EVB_01 = 0x0015u, + CY8CKIT_062_4343W = 0x0016u, + CY8CPROTO_062S2_43012 = 0x0017u, + UNSPECIFIED +} CyKits; + +static CyKits cy_kit = UNSPECIFIED; +static bool sflash_restriction = true; + +void prerun_board_config(void); + +// Default Daplink board_info +const board_info_t g_board_info = +{ + .infoVersion = 0x0, + .board_id = "19FF", + .family_id = kCypress_psoc6_FamilyID, + .target_cfg = &target_device, + .prerun_board_config = prerun_board_config, + .flags = kEnablePageErase +}; + +const char *const board_ids[] = { + [CY8CKIT_062_BLE ] = "1902", + [CY8CKIT_062_WIFI_BT ] = "1900", + [CY8CPROTO_063_BLE ] = "1904", + [CY8CPROTO_062_4343W ] = "1901", + [CY8CPROTO_062_43012 ] = "1903", + [CYW943012P6EVB_01 ] = "1906", + [CY8CKIT_062_4343W ] = "1905", + [CY8CPROTO_062S2_43012] = "1909", + [CY8CPROTO_064_SB ] = "1907", + [UNSPECIFIED ] = "19FF" +}; + +extern uint8_t get_hw_id(void); +extern uint8_t get_silcon_id(void); +extern void init_flash_algo(uint32_t si_id); +extern uint32_t get_fb_version(void); + +// Read uiniqe id record and calculate crc +uint8_t get_uniq_id(unique_id_struct_t *uid_record) +{ + reg8* modeAddress = (reg8 *) CYDEV_EE_BASE; + uint8_t eeprom_array[sizeof(unique_id_struct_t)]; + uint8_t crc = 0; + + EEPROM_ModeStorage_Start(); + + for (uint8_t i = 0; i < sizeof(unique_id_struct_t); i++) + { + eeprom_array[i] = modeAddress[P5LP_EEPROM_ROW_SIZE + i]; + + if (i < (sizeof(unique_id_struct_t) - 1u)) + { + crc += eeprom_array[i]; + } + } + + EEPROM_ModeStorage_Stop(); + memcpy(uid_record, eeprom_array, sizeof(unique_id_struct_t)); + + return (CRC8_2S_COMP_BASE - crc); +} + +// Define board id based on HW id and silicon ID +void define_board_id(void) +{ + uint8_t crc_tmp = 0u; + + // Read unique id record + crc_tmp = get_uniq_id(&id); + + if ((UID_PSOC5_HEADER == id.signature) && (crc_tmp == id.checksum)) + { + switch (id.uid) + { + // CY8CPROTO_064_SB + case CY8CPROTO_064_SB: + cy_kit = CY8CPROTO_064_SB; + id.target_siid = CY8CPROTO_064_SB_SIID; + sflash_restriction = true; + break; + // CYW943012P6EVB_01 + case CYW943012P6EVB_01: + cy_kit = CYW943012P6EVB_01; + id.target_siid = CYW943012P6EVB_01_SIID; + sflash_restriction = false; + break; + // CY8CPROTO_062S2_43012 + case CY8CPROTO_062S2_43012: + cy_kit = CY8CPROTO_062S2_43012; + id.target_siid = CY8CPROTO_062S2_43012_SIID; + sflash_restriction = false; + break; + + default: + break; + } + } + + // Analyze HW ID and Silicon ID in case + // when unique id record is empty or corrupted + if (cy_kit == UNSPECIFIED) + { + // Read kit hw id + id.hw_id = get_hw_id(); + + // Read silicon IDe + id.target_siid = get_silcon_id(); + + // Read flashboot version + uint32_t fb_ver = get_fb_version(); + if (fb_ver >= MIN_FB_SR_VER) + { + sflash_restriction = true; + } + else + { + sflash_restriction = false; + } + + // Decode HW_ID/Silicon_ID + switch (id.hw_id) + { + // Kits with HW_ID 0x02 + case 0x02: + switch (id.target_siid) + { + // CY8CKIT-062-BLE + case CY8CKIT_062_BLE_SIID: + cy_kit = CY8CKIT_062_BLE; + break; + + // CY8CKIT-062-WiFi-BT + case CY8CKIT_062_WIFI_BT_SIID: + cy_kit = CY8CKIT_062_WIFI_BT; + break; + + // CY8CKIT-062-4343W + case CY8CKIT_062_4343W_SIID: + cy_kit = CY8CKIT_062_4343W; + break; + + default: + break; + } + break; + + // Kits with HW_ID 0x03 + case 0x03: + switch (id.target_siid) + { + // CY8CPROTO-063-BLE + case CY8CPROTO_063_BLE_SIID: + cy_kit = CY8CPROTO_063_BLE; + break; + + // CY8CPROTO-064-SB + case CY8CPROTO_064_SB_SIID: + cy_kit = CY8CPROTO_064_SB; + break; + + default: + break; + } + break; + + // Kits with HW_ID 0x0B + case 0x0B: + switch (id.target_siid) + { + // CY8CPROTO-062-4343W + case CY8CPROTO_062_4343W_SIID: + cy_kit = CY8CPROTO_062_4343W; + break; + + // CY8CPROTO-062-43012 + case CY8CPROTO_062_43012_SIID: + cy_kit = CY8CPROTO_062_43012; + break; + + default: + break; + } + break; + + // Kits with HW_ID 0x0D + case 0x0D: + if (id.target_siid == CY8CPROTO_062S2_43012_SIID) + { + cy_kit = CY8CPROTO_062S2_43012; + } + break; + + default: + break; + } + } + + if (cy_kit != UNSPECIFIED) + { + g_board_info.target_cfg->rt_board_id = board_ids[cy_kit]; + } +} + +// Called in main_task() to init before USB and files are configured +void prerun_board_config(void) +{ + // Powering up target + Pin_VoltageEn_Write(1u); + + //Wait for target initialization + CyDelay(100u); + + // Define board ID + define_board_id(); + + //Reset target + target_set_state(RESET_RUN); +} + +// Called in main_task() to init before USB and files are configured +void prerun_target_config(void) +{ + // Initialize main flash,WFlash, SFlash and SMIF programming algorithms + // and set proper flash geometry based on family type/silicon ID + init_flash_algo(id.target_siid); +} + +// Get .kitHasThreeLeds board property +bool kit_has_three_led(void) +{ + return board_config[id.hw_id].kitHasThreeLeds; +} + +// Get .kitHasTwoButtons board property +bool kit_has_two_buttons(void) +{ + return board_config[id.hw_id].kitHasTwoButtons; +} + +// Get Kit unique ID +bool kit_has_sflash_restriction(void) +{ + return sflash_restriction; +} + diff --git a/source/board/psoc5lp_bl.c b/source/board/psoc5lp_bl.c new file mode 100644 index 0000000000..1017ede11e --- /dev/null +++ b/source/board/psoc5lp_bl.c @@ -0,0 +1,56 @@ +/******************************************************************************* +* @file psoc5lp_bl.c +* @brief board ID and meta-data for the hardware interface circuit (HIC) based on the CYPRESS PSoC5LP +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "target_config.h" +#include "daplink_addr.h" +#include "compiler.h" +#include "target_board.h" +#include "target_family.h" + +// Warning - changing the interface start will break backwards compatibility +COMPILER_ASSERT(DAPLINK_ROM_IF_START == 0x00021800); +COMPILER_ASSERT(DAPLINK_ROM_IF_SIZE == 0x0001E500); + +// PSoCLP target information +target_cfg_t target_device = { + .sector_size = 0x4000u, + // Assume memory is regions are same size. Flash algo should ignore requests + // when variable sized sectors exist + // .sector_cnt = ((.flash_end - .flash_start) / .sector_size); + .sector_cnt = (DAPLINK_ROM_IF_SIZE / 0x4000u), + .flash_start = DAPLINK_ROM_IF_START, + .flash_end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE, + .ram_start = DAPLINK_RAM_START, + .ram_end = DAPLINK_RAM_START + DAPLINK_RAM_SIZE, + /* .flash_algo not needed for bootloader */ +}; + +//bootloader has no family +const target_family_descriptor_t *g_target_family = NULL; + +const board_info_t g_board_info = { + .infoVersion = 0x0, + .board_id = "0000", + .daplink_url_name = "HELP_FAQHTM", + .daplink_drive_name = "MAINTENANCE", + .daplink_target_url = "https://mbed.com/daplink", + .target_cfg = &target_device, +}; diff --git a/source/daplink/daplink.h b/source/daplink/daplink.h index dcd3655045..e70ecc7244 100644 --- a/source/daplink/daplink.h +++ b/source/daplink/daplink.h @@ -67,7 +67,7 @@ COMPILER_ASSERT(DAPLINK_RAM_SHARED_START + DAPLINK_RAM_SHARED_SIZE == DAPLINK_RA #define DAPLINK_HIC_ID_LPC54606 0x9796990C // reserving for future use #define DAPLINK_HIC_ID_STM32F723IE 0x9796990D // reserving for future use #define DAPLINK_HIC_ID_LPC55S69 0x97969920 // reserving for future use -#define DAPLINK_HIC_ID_PSOC5 0x2E127069 +#define DAPLINK_HIC_ID_PSOC5LP 0x2E127069 //@} #define DAPLINK_INFO_OFFSET 0x20 diff --git a/source/daplink/interface/swd_host.c b/source/daplink/interface/swd_host.c index 26228051c0..7801ce6227 100644 --- a/source/daplink/interface/swd_host.c +++ b/source/daplink/interface/swd_host.c @@ -18,6 +18,11 @@ * See the License for the specific language governing permissions and * limitations under the License. */ +/******************************************************************************* +* Copyright 2019, Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +*****************************************************************************/ #ifndef TARGET_MCU_CORTEX_A #include "cmsis_os2.h" @@ -48,6 +53,18 @@ #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ +#define DELAY_AFTER_RESET (2) // in OS tick units + +#ifdef TARGET_MCU_PSOC6 +#define SYS_AP (0u << 24u) +#define CM0_AP (1u << 24u) +#define CM4_AP (2u << 24u) + +uint32_t DAP_AP = SYS_AP; +#else +#define DAP_AP (0x0u) +#endif + typedef struct { uint32_t select; uint32_t csw; @@ -170,7 +187,7 @@ uint8_t swd_read_ap(uint32_t adr, uint32_t *val) uint8_t tmp_in, ack; uint8_t tmp_out[4]; uint32_t tmp; - uint32_t apsel = adr & 0xff000000; + uint32_t apsel = adr & APSEL; uint32_t bank_sel = adr & APBANKSEL; if (!swd_write_dp(DP_SELECT, apsel | bank_sel)) { @@ -198,7 +215,7 @@ uint8_t swd_write_ap(uint32_t adr, uint32_t val) { uint8_t data[4]; uint8_t req, ack; - uint32_t apsel = adr & 0xff000000; + uint32_t apsel = adr & APSEL; uint32_t bank_sel = adr & APBANKSEL; if (!swd_write_dp(DP_SELECT, apsel | bank_sel)) { @@ -246,7 +263,7 @@ static uint8_t swd_write_block(uint32_t address, uint8_t *data, uint32_t size) size_in_words = size / 4; // CSW register - if (!swd_write_ap(AP_CSW, CSW_VALUE | CSW_SIZE32)) { + if (!swd_write_ap(AP_CSW | DAP_AP, CSW_VALUE | CSW_SIZE32)) { return 0; } @@ -289,7 +306,7 @@ static uint8_t swd_read_block(uint32_t address, uint8_t *data, uint32_t size) size_in_words = size / 4; - if (!swd_write_ap(AP_CSW, CSW_VALUE | CSW_SIZE32)) { + if (!swd_write_ap(AP_CSW | DAP_AP, CSW_VALUE | CSW_SIZE32)) { return 0; } @@ -390,7 +407,7 @@ static uint8_t swd_write_data(uint32_t address, uint32_t data) // Read 32-bit word from target memory. uint8_t swd_read_word(uint32_t addr, uint32_t *val) { - if (!swd_write_ap(AP_CSW, CSW_VALUE | CSW_SIZE32)) { + if (!swd_write_ap(AP_CSW | DAP_AP, CSW_VALUE | CSW_SIZE32)) { return 0; } @@ -404,7 +421,7 @@ uint8_t swd_read_word(uint32_t addr, uint32_t *val) // Write 32-bit word to target memory. uint8_t swd_write_word(uint32_t addr, uint32_t val) { - if (!swd_write_ap(AP_CSW, CSW_VALUE | CSW_SIZE32)) { + if (!swd_write_ap(AP_CSW | DAP_AP, CSW_VALUE | CSW_SIZE32)) { return 0; } @@ -420,7 +437,7 @@ uint8_t swd_read_byte(uint32_t addr, uint8_t *val) { uint32_t tmp; - if (!swd_write_ap(AP_CSW, CSW_VALUE | CSW_SIZE8)) { + if (!swd_write_ap(AP_CSW | DAP_AP, CSW_VALUE | CSW_SIZE8)) { return 0; } @@ -437,7 +454,7 @@ uint8_t swd_write_byte(uint32_t addr, uint8_t val) { uint32_t tmp; - if (!swd_write_ap(AP_CSW, CSW_VALUE | CSW_SIZE8)) { + if (!swd_write_ap(AP_CSW | DAP_AP, CSW_VALUE | CSW_SIZE8)) { return 0; } @@ -553,7 +570,7 @@ static uint8_t swd_write_debug_state(DEBUG_STATE *state) { uint32_t i, status; - if (!swd_write_dp(DP_SELECT, 0)) { + if (!swd_write_dp(DP_SELECT, DAP_AP)) { return 0; } @@ -675,7 +692,7 @@ static uint8_t swd_wait_until_halted(void) return 0; } -uint8_t swd_flash_syscall_exec(const program_syscall_t *sysCallParam, uint32_t entry, uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t arg4) +uint8_t swd_flash_syscall_exec(const program_syscall_t *sysCallParam, uint32_t entry, uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t arg4, flash_algo_return_t return_type) { DEBUG_STATE state = {{0}, 0}; // Call flash algorithm function on target and wait for result. @@ -706,9 +723,19 @@ uint8_t swd_flash_syscall_exec(const program_syscall_t *sysCallParam, uint32_t e return 0; } - // Flash functions return 0 if successful. - if (state.r[0] != 0) { - return 0; + if ( return_type == FLASHALGO_RETURN_POINTER ) + { + // Flash verify functions return pointer to byte following the buffer if successful. + if (state.r[0] != (arg1 + arg2)) { + return 0; + } + } + else + { + // Flash functions return 0 if successful. + if (state.r[0] != 0) { + return 0; + } } return 1; @@ -794,9 +821,9 @@ uint8_t swd_init_debug(void) //do an abort on stale target, then reset the device swd_write_dp(DP_ABORT, DAPABORT); swd_set_target_reset(1); - osDelay(2); + osDelay(DELAY_AFTER_RESET); swd_set_target_reset(0); - osDelay(2); + osDelay(DELAY_AFTER_RESET); do_abort = 0; } swd_init(); @@ -817,7 +844,7 @@ uint8_t swd_init_debug(void) continue; } - if (!swd_write_dp(DP_SELECT, 0)) { + if (!swd_write_dp(DP_SELECT, DAP_AP)) { do_abort = 1; continue; @@ -857,7 +884,7 @@ uint8_t swd_init_debug(void) g_target_family->target_unlock_sequence(); } - if (!swd_write_dp(DP_SELECT, 0)) { + if (!swd_write_dp(DP_SELECT, DAP_AP)) { do_abort = 1; continue; } @@ -885,9 +912,9 @@ uint8_t swd_set_target_state_hw(TARGET_RESET_STATE state) case RESET_RUN: swd_set_target_reset(1); - osDelay(2); + osDelay(DELAY_AFTER_RESET); swd_set_target_reset(0); - osDelay(2); + osDelay(DELAY_AFTER_RESET); swd_off(); break; @@ -899,7 +926,7 @@ uint8_t swd_set_target_state_hw(TARGET_RESET_STATE state) if (reset_connect == CONNECT_UNDER_RESET) { // Assert reset swd_set_target_reset(1); - osDelay(2); + osDelay(DELAY_AFTER_RESET); } // Enable debug @@ -908,9 +935,9 @@ uint8_t swd_set_target_state_hw(TARGET_RESET_STATE state) return 0; // Target is in invalid state? swd_set_target_reset(1); - osDelay(2); + osDelay(DELAY_AFTER_RESET); swd_set_target_reset(0); - osDelay(2); + osDelay(DELAY_AFTER_RESET); } // Enable halt on reset @@ -921,12 +948,12 @@ uint8_t swd_set_target_state_hw(TARGET_RESET_STATE state) if (reset_connect == CONNECT_NORMAL) { // Assert reset swd_set_target_reset(1); - osDelay(2); + osDelay(DELAY_AFTER_RESET); } // Deassert reset swd_set_target_reset(0); - osDelay(2); + osDelay(DELAY_AFTER_RESET); do { if (!swd_read_word(DBG_HCSR, &val)) { @@ -958,7 +985,7 @@ uint8_t swd_set_target_state_hw(TARGET_RESET_STATE state) } // Ensure CTRL/STAT register selected in DPBANKSEL - if (!swd_write_dp(DP_SELECT, 0)) { + if (!swd_write_dp(DP_SELECT, DAP_AP)) { return 0; } @@ -1026,9 +1053,9 @@ uint8_t swd_set_target_state_sw(TARGET_RESET_STATE state) case RESET_RUN: swd_set_target_reset(1); - osDelay(2); + osDelay(DELAY_AFTER_RESET); swd_set_target_reset(0); - osDelay(2); + osDelay(DELAY_AFTER_RESET); swd_off(); break; @@ -1044,9 +1071,9 @@ uint8_t swd_set_target_state_sw(TARGET_RESET_STATE state) } // Target is in invalid state? swd_set_target_reset(1); - osDelay(2); + osDelay(DELAY_AFTER_RESET); swd_set_target_reset(0); - osDelay(2); + osDelay(DELAY_AFTER_RESET); } // Wait until core is halted @@ -1070,7 +1097,7 @@ uint8_t swd_set_target_state_sw(TARGET_RESET_STATE state) return 0; } - osDelay(2); + osDelay(DELAY_AFTER_RESET); do { if (!swd_read_word(DBG_HCSR, &val)) { @@ -1102,7 +1129,7 @@ uint8_t swd_set_target_state_sw(TARGET_RESET_STATE state) } // Ensure CTRL/STAT register selected in DPBANKSEL - if (!swd_write_dp(DP_SELECT, 0)) { + if (!swd_write_dp(DP_SELECT, DAP_AP)) { return 0; } diff --git a/source/daplink/interface/swd_host.h b/source/daplink/interface/swd_host.h index 04e75fa247..d5a37f81ff 100644 --- a/source/daplink/interface/swd_host.h +++ b/source/daplink/interface/swd_host.h @@ -39,6 +39,11 @@ typedef enum { CONNECT_UNDER_RESET, } SWD_CONNECT_TYPE; +typedef enum { + FLASHALGO_RETURN_BOOL, + FLASHALGO_RETURN_POINTER +} flash_algo_return_t; + uint8_t swd_init(void); uint8_t swd_off(void); uint8_t swd_init_debug(void); @@ -55,7 +60,7 @@ uint8_t swd_read_memory(uint32_t address, uint8_t *data, uint32_t size); uint8_t swd_write_memory(uint32_t address, uint8_t *data, uint32_t size); uint8_t swd_read_core_register(uint32_t n, uint32_t *val); uint8_t swd_write_core_register(uint32_t n, uint32_t val); -uint8_t swd_flash_syscall_exec(const program_syscall_t *sysCallParam, uint32_t entry, uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t arg4); +uint8_t swd_flash_syscall_exec(const program_syscall_t *sysCallParam, uint32_t entry, uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t arg4, flash_algo_return_t return_type); uint8_t swd_set_target_state_hw(TARGET_RESET_STATE state); uint8_t swd_set_target_state_sw(TARGET_RESET_STATE state); uint8_t swd_transfer_retry(uint32_t req, uint32_t *data); diff --git a/source/daplink/interface/target_flash.c b/source/daplink/interface/target_flash.c index cc4bfb105a..4076dff32f 100644 --- a/source/daplink/interface/target_flash.c +++ b/source/daplink/interface/target_flash.c @@ -18,6 +18,12 @@ * See the License for the specific language governing permissions and * limitations under the License. */ +/******************************************************************************* +* Copyright 2019, Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +*****************************************************************************/ + #ifdef DRAG_N_DROP_SUPPORT #include "string.h" @@ -33,6 +39,8 @@ #include "target_family.h" #include "target_board.h" +#define DEFAULT_PROGRAM_PAGE_MIN_SIZE (256u) + typedef enum { STATE_CLOSED, STATE_OPEN, @@ -101,13 +109,15 @@ static error_t flash_func_start(flash_func_t func) { // Finish the currently active function. if (FLASH_FUNC_NOP != last_flash_func && - 0 == swd_flash_syscall_exec(&flash->sys_call_s, flash->uninit, last_flash_func, 0, 0, 0)) { + ((flash->algo_flags & kAlgoSingleInitType) == 0 || FLASH_FUNC_NOP == func ) && + 0 == swd_flash_syscall_exec(&flash->sys_call_s, flash->uninit, last_flash_func, 0, 0, 0, FLASHALGO_RETURN_BOOL)) { return ERROR_UNINIT; } // Start a new function. if (FLASH_FUNC_NOP != func && - 0 == swd_flash_syscall_exec(&flash->sys_call_s, flash->init, flash_start, 0, func, 0)) { + ((flash->algo_flags & kAlgoSingleInitType) == 0 || FLASH_FUNC_NOP == last_flash_func ) && + 0 == swd_flash_syscall_exec(&flash->sys_call_s, flash->init, flash_start, 0, func, 0, FLASHALGO_RETURN_BOOL)) { return ERROR_INIT; } @@ -222,7 +232,8 @@ static error_t target_flash_program_page(uint32_t addr, const uint8_t *buf, uint addr, write_size, flash->program_buffer, - 0)) { + 0, + FLASHALGO_RETURN_BOOL)) { return ERROR_WRITE; } @@ -233,12 +244,19 @@ static error_t target_flash_program_page(uint32_t addr, const uint8_t *buf, uint if (status != ERROR_SUCCESS) { return status; } + flash_algo_return_t return_type; + if ((flash->algo_flags & kAlgoVerifyReturnsAddress) != 0) { + return_type = FLASHALGO_RETURN_POINTER; + } else { + return_type = FLASHALGO_RETURN_BOOL; + } if (!swd_flash_syscall_exec(&flash->sys_call_s, flash->verify, addr, write_size, flash->program_buffer, - 0)) { + 0, + return_type)) { return ERROR_WRITE_VERIFY; } } else { @@ -293,7 +311,7 @@ static error_t target_flash_erase_sector(uint32_t addr) return status; } - if (0 == swd_flash_syscall_exec(&flash->sys_call_s, flash->erase_sector, addr, 0, 0, 0)) { + if (0 == swd_flash_syscall_exec(&flash->sys_call_s, flash->erase_sector, addr, 0, 0, 0, FLASHALGO_RETURN_BOOL)) { return ERROR_ERASE_SECTOR; } @@ -324,7 +342,7 @@ static error_t target_flash_erase_chip(void) if (status != ERROR_SUCCESS) { return status; } - if (0 == swd_flash_syscall_exec(&flash->sys_call_s, flash->erase_chip, 0, 0, 0, 0)) { + if (0 == swd_flash_syscall_exec(&flash->sys_call_s, flash->erase_chip, 0, 0, 0, 0, FLASHALGO_RETURN_BOOL)) { return ERROR_ERASE_ALL; } @@ -355,7 +373,7 @@ static error_t target_flash_erase_chip(void) static uint32_t target_flash_program_page_min_size(uint32_t addr) { if (g_board_info.target_cfg){ - uint32_t size = 256; + uint32_t size = DEFAULT_PROGRAM_PAGE_MIN_SIZE; if (size > target_flash_erase_sector_size(addr)) { size = target_flash_erase_sector_size(addr); } diff --git a/source/family/cypress/PSoC6xxx/PSOC6xxx.c b/source/family/cypress/PSoC6xxx/PSOC6xxx.c new file mode 100644 index 0000000000..ee4a104578 --- /dev/null +++ b/source/family/cypress/PSoC6xxx/PSOC6xxx.c @@ -0,0 +1,1460 @@ +/******************************************************************************* +* @file PSOC6xxx.c +* @brief PSOC6xxx family core API for acquiring and target detecting +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "PSOC6xxx.h" +#include "DAP_config.h" +#include "CyLib.h" +#include "Timer_CSTick.h" +#include "Pin_HWVersion.h" + +#define FB_VERSION_ADDR (0x16002004u) +#define FB_VERSION_UNKNOWN (0xFFFFFFFFu) +#define MAX_SWD_WRITE_RTRY (10u) + +#define DP_POWER_UP_VALUE (0x50000000u) +#define SYS_AP (0u << 24u) +#define TRANSFER_MODE_32BIT (0x00000002u) +#define TEST_MODE_REGISTER (0x40260100u) +#define TEST_MODE_VALUE (0x80000000u) +#define DPACC_DP_ABORT_MASK (0x0000001Eu) + +// 8-bit header +static uint8_t gbHeader; + +// 32-bit data +static uint8_t gbData[SWD_XFER_SIZE]; + +// 8-bit status +static uint8_t gbStatsReg; + +// 3-bit ACK response +static uint8_t gbAck; +static uint8_t ack0 = 0u; +static uint8_t ack1 = 0u; +static uint8_t ack2 = 0u; + +/****************************************************************************** +* SWDResetBus +***************************************************************************//** +* Reset the SWD bus by clocking 60 times. +* +******************************************************************************/ +static void SWDResetBus(void) +{ + uint8_t enableInterrupts; + + SWD_SET_SCK_OUT; + + /* Disable all the interrupts */ + enableInterrupts = CyEnterCriticalSection(); + + /* see 001-11605 4.2.1.2. Clocks more than 52 times to reset the SWD bus */ + SWD_SET_SDA_HI; + SWD_SET_SDA_OUT; + SWD_CLOCK_BIT; /* 1 */ + SWD_CLOCK_BIT; /* 2 */ + SWD_CLOCK_BIT; /* 3 */ + SWD_CLOCK_BIT; /* 4 */ + SWD_CLOCK_BIT; /* 5 */ + SWD_CLOCK_BIT; /* 6 */ + SWD_CLOCK_BIT; /* 7 */ + SWD_CLOCK_BIT; /* 8 */ + SWD_CLOCK_BIT; /* 9 */ + SWD_CLOCK_BIT; /* 10 */ + SWD_CLOCK_BIT; /* 11 */ + SWD_CLOCK_BIT; /* 12 */ + SWD_CLOCK_BIT; /* 13 */ + SWD_CLOCK_BIT; /* 14 */ + SWD_CLOCK_BIT; /* 15 */ + SWD_CLOCK_BIT; /* 16 */ + SWD_CLOCK_BIT; /* 17 */ + SWD_CLOCK_BIT; /* 18 */ + SWD_CLOCK_BIT; /* 19 */ + SWD_CLOCK_BIT; /* 20 */ + SWD_CLOCK_BIT; /* 21 */ + SWD_CLOCK_BIT; /* 22 */ + SWD_CLOCK_BIT; /* 23 */ + SWD_CLOCK_BIT; /* 24 */ + SWD_CLOCK_BIT; /* 25 */ + SWD_CLOCK_BIT; /* 26 */ + SWD_CLOCK_BIT; /* 27 */ + SWD_CLOCK_BIT; /* 28 */ + SWD_CLOCK_BIT; /* 29 */ + SWD_CLOCK_BIT; /* 30 */ + SWD_CLOCK_BIT; /* 31 */ + SWD_CLOCK_BIT; /* 32 */ + SWD_CLOCK_BIT; /* 33 */ + SWD_CLOCK_BIT; /* 34 */ + SWD_CLOCK_BIT; /* 35 */ + SWD_CLOCK_BIT; /* 36 */ + SWD_CLOCK_BIT; /* 37 */ + SWD_CLOCK_BIT; /* 38 */ + SWD_CLOCK_BIT; /* 39 */ + SWD_CLOCK_BIT; /* 40 */ + SWD_CLOCK_BIT; /* 41 */ + SWD_CLOCK_BIT; /* 42 */ + SWD_CLOCK_BIT; /* 43 */ + SWD_CLOCK_BIT; /* 44 */ + SWD_CLOCK_BIT; /* 45 */ + SWD_CLOCK_BIT; /* 46 */ + SWD_CLOCK_BIT; /* 47 */ + SWD_CLOCK_BIT; /* 48 */ + SWD_CLOCK_BIT; /* 49 */ + SWD_CLOCK_BIT; /* 50 */ + SWD_CLOCK_BIT; /* 51 */ + SWD_CLOCK_BIT; /* 52 */ + SWD_CLOCK_BIT; /* 53 */ + SWD_CLOCK_BIT; /* 54 */ + SWD_CLOCK_BIT; /* 55 */ + SWD_CLOCK_BIT; /* 56 */ + SWD_CLOCK_BIT; /* 57 */ + SWD_CLOCK_BIT; /* 58 */ + SWD_CLOCK_BIT; /* 59 */ + SWD_CLOCK_BIT; /* 60 */ + + /* Enable all the interrupts */ + CyExitCriticalSection(enableInterrupts); + SWD_SET_SDA_LO; + SWD_SET_SDA_IN; +} + +/****************************************************************************** +* SWDPutByte +***************************************************************************//** +* Writes a byte on to the SWD lines. +* +* @param[in] bPutData Byte to be written on to the SWD lines. +* +******************************************************************************/ +static void SWDPutByte(uint8_t bPutData) +{ + SWD_BYTE = bPutData; + + SWD_SET_SCK_LO; SWD_SDA = SWD_DATA_BIT_B0; SWD_SET_SCK_HI; + SWD_SET_SCK_LO; SWD_SDA = SWD_DATA_BIT_B1; SWD_SET_SCK_HI; + SWD_SET_SCK_LO; SWD_SDA = SWD_DATA_BIT_B2; SWD_SET_SCK_HI; + SWD_SET_SCK_LO; SWD_SDA = SWD_DATA_BIT_B3; SWD_SET_SCK_HI; + SWD_SET_SCK_LO; SWD_SDA = SWD_DATA_BIT_B4; SWD_SET_SCK_HI; + SWD_SET_SCK_LO; SWD_SDA = SWD_DATA_BIT_B5; SWD_SET_SCK_HI; + SWD_SET_SCK_LO; SWD_SDA = SWD_DATA_BIT_B6; SWD_SET_SCK_HI; + SWD_SET_SCK_LO; SWD_SDA = SWD_DATA_BIT_B7; SWD_SET_SCK_HI; +} + + +/****************************************************************************** +* SWDSwitchJTAGToSWD +***************************************************************************//** +* Generates JTAG to SWD sequence: +* - 60-cycles Line Reset +* - 2-byte 0x9EE7 sequence +* - 60-cycle Line Reset +* +*******************************************************************************/ +static void SWDSwitchJTAGToSWD(void) +{ + uint8_t enableInterrupts; + + SWDResetBus(); + /* Clock J2S 16-bit header */ + SWD_SET_SDA_OUT; + enableInterrupts = CyEnterCriticalSection(); + SWDPutByte(0x9Eu); /* see 001-11605 4.5.1.5 JTAG to SWD */ + SWDPutByte(0xE7u); + CyExitCriticalSection(enableInterrupts); + SWD_SET_SDA_IN; + SWDResetBus(); +} + +/****************************************************************************** +* SWDPutHeaderSegment +***************************************************************************//** +* Puts the Header segment on to the SWD lines. +* +******************************************************************************/ +static void SWDPutHeaderSegment(void) +{ + SWD_SET_SDA_LO; + SWD_SET_SDA_OUT; + CY_NOP; + CY_NOP; + + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + SWD_CLOCK_BIT; + + SWDPutByte(gbHeader); + + SWD_SET_SDA_IN; +} + +/****************************************************************************** +* SWDClockTrn +***************************************************************************//** +* Puts the PSoC 5LP in the turn around mode of SWD programming. +* +******************************************************************************/ +static void SWDClockTrn (void) +{ + SWD_SET_SDA_IN; + SWD_CLOCK_BIT; +} + +/****************************************************************************** +* SWDGetAckSegment +***************************************************************************//** +* Retrieves the Ack bits from the SWD lines. Fill result in ack0, ack1 and ack2 +* variables. Ack = 0:fail, 1:ACK, 2:WAIT, 4:FAULT +* +******************************************************************************/ +static void SWDGetAckSegment(void) +{ + /* get ACK */ + SWD_SET_SDA_IN; + + SWD_SET_SCK_LO; + ack0 = SWD_GET_SDA; + SWD_SET_SCK_HI; + + SWD_SET_SCK_LO; + ack1 = SWD_GET_SDA; + SWD_SET_SCK_HI; + + SWD_SET_SCK_LO; + ack2 = SWD_GET_SDA; + SWD_SET_SCK_HI; +} + +/****************************************************************************** +* SWDGetByte +***************************************************************************//** +* Reads a byte from the SWD lines. +* +* @return Byte read from the SWD lines. +* +******************************************************************************/ +static uint8_t SWDGetByte(void) +{ + SWD_SET_SCK_LO; SWD_DATA_BIT_B0 = SWD_GET_SDA; SWD_SET_SCK_HI; + SWD_SET_SCK_LO; SWD_DATA_BIT_B1 = SWD_GET_SDA; SWD_SET_SCK_HI; + SWD_SET_SCK_LO; SWD_DATA_BIT_B2 = SWD_GET_SDA; SWD_SET_SCK_HI; + SWD_SET_SCK_LO; SWD_DATA_BIT_B3 = SWD_GET_SDA; SWD_SET_SCK_HI; + SWD_SET_SCK_LO; SWD_DATA_BIT_B4 = SWD_GET_SDA; SWD_SET_SCK_HI; + SWD_SET_SCK_LO; SWD_DATA_BIT_B5 = SWD_GET_SDA; SWD_SET_SCK_HI; + SWD_SET_SCK_LO; SWD_DATA_BIT_B6 = SWD_GET_SDA; SWD_SET_SCK_HI; + SWD_SET_SCK_LO; SWD_DATA_BIT_B7 = SWD_GET_SDA; SWD_SET_SCK_HI; + + return SWD_BYTE; +} + + +/****************************************************************************** +* SWDGetDataSegment +***************************************************************************//** +* Reads the data segment from the SWD lines. +* +* @param[out] pbData Pointer to the address where data to be written to +* the SWD lines is stored. +* +******************************************************************************/ +static void SWDGetDataSegment(uint8_t *pbData) +{ + SWD_SET_SDA_IN; + + *pbData++ = SWDGetByte(); + *pbData++ = SWDGetByte(); + *pbData++ = SWDGetByte(); + *pbData = SWDGetByte(); +} + +/****************************************************************************** +* SWDCountBits +***************************************************************************//** +* Counts the number of '1's in the byte passed. +* +* @param[in] data Byte for which number of ones is to be calculated +* +* @return Number of ones in the byte. +* +******************************************************************************/ +static uint8_t SWDCountBits(uint8_t data) +{ + uint8_t c; + + for (c = 0; data != 0; data >>= 1) + { + c += data & 1u; + } + + return c; +} + +/****************************************************************************** +* SWDComputeDataParity +***************************************************************************//** +* Calculates the parity for the data segment. +* +* @param[in] pbData Pointer to the address location of data whose parity has +* to be calculated. +* +* @return Parity of the data segment. +* +******************************************************************************/ +static uint8_t SWDComputeDataParity(const uint8_t *pbData) +{ + uint8_t bCount = 0u; + + bCount += SWDCountBits(*pbData++); + bCount += SWDCountBits(*pbData++); + bCount += SWDCountBits(*pbData++); + bCount += SWDCountBits(*pbData++); + + return (bCount & 1u); +} + + +/****************************************************************************** +* SWDGetData +***************************************************************************//** +* Invokes the functions to read a data segment from the SWD lines and checks the +* acknowledgement to decide whether the read operation was successful or not. +* +* @param[out] pbData Pointer to the address location where data read from the +* SWD lines has to be stored. +* +******************************************************************************/ +static void SWDGetData(uint8_t *pbData) +{ + uint8_t enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + gbStatsReg = 0u; + SWDPutHeaderSegment(); + SWDClockTrn(); + SWDGetAckSegment(); + gbAck = ack0 | (ack1 << 1u) | (ack2 << 2u); + + switch (gbAck) + { + /* This handles error in pre-ES10 silicon for reads */ + case SWD_ACK+SWD_WAIT: + + /* This handles normal expected response for ACK=OK */ + case SWD_ACK: + { + uint8_t parity; + + SWDGetDataSegment(pbData); + SWD_SET_SCK_LO; + parity = SWD_GET_SDA; + SWD_SET_SCK_HI; + SWDClockTrn(); + + if (SWDComputeDataParity(pbData) != parity) + { + gbStatsReg |= SWD_PERR; + } + + SWD_SET_SDA_IN; + SWD_SET_SDA_HI; + SWD_SET_SCK_HI; + gbStatsReg |= gbAck; + break; + } + + case SWD_WAIT: + case SWD_FAULT: + { + SWDClockTrn(); + + for (uint32_t i = 0u; i < SWD_XFER_SIZE; i++) + { + *pbData++ = 0u; + } + + SWD_SET_SDA_IN; + SWD_SET_SDA_HI; + SWD_SET_SCK_HI; + gbStatsReg |= gbAck; + break; + } + + default: + { + SWDClockTrn(); + SWD_SET_SDA_IN; + SWD_SET_SDA_HI; + SWD_SET_SCK_HI; + + /* Protocol Error - no response from target */ + gbStatsReg |= SWD_ERROR; + break; + } + } + CyExitCriticalSection(enableInterrupts); + return; +} + +/****************************************************************************** +* SWDPutDataSegment +***************************************************************************//** +* Puts the complete data segment received on to the SWD lines. +* +* @param[in] Pointer to the address with data to write. +* +******************************************************************************/ +static void SWDPutDataSegment(const uint8_t *pbData) +{ + SWD_SET_SDA_OUT; + + SWDPutByte(*pbData++); + SWDPutByte(*pbData++); + SWDPutByte(*pbData++); + SWDPutByte(*pbData); +} + +/****************************************************************************** +* SWDPutData +***************************************************************************//** +* Calls the functions to write data segment on to the SWD lines and checks the +* acknowledgement to decide whether the write was successful or not. +* +* @param[in] pbData Pointer to the address location where data to be written +* to the SWD lines is stored. +* +******************************************************************************/ +static void SWDPutData(uint8_t *pbData) +{ + uint8_t bParity; + uint8_t enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + gbStatsReg = 0u; + bParity = SWDComputeDataParity(pbData); + SWDPutHeaderSegment(); + + SWDClockTrn(); + SWDGetAckSegment(); + gbAck = ack0 | (ack1 << 1u) | (ack2 << 2u); + SWDClockTrn(); + + switch (gbAck) + { + case SWD_ACK: + { + SWDPutDataSegment(pbData); + + if (bParity != 0u) + { + SWD_SET_SDA_HI; + } + else + { + SWD_SDA = 0u; + } + + /* 46th clock ends SWD transaction */ + SWD_CLOCK_BIT; + + /* keep Data low to not start next SWD transaction on 47th clock */ + SWD_SDA = 0u; + SWD_CLOCK_BIT; /* 47th clock is required to move Addr/Data from DAP to AHB bus. */ + + SWD_CLOCK_BIT; /* 48th clock CDT 127910 */ + SWD_CLOCK_BIT; /* 49th clock */ + SWD_CLOCK_BIT; /* 50th clock */ + SWD_CLOCK_BIT; /* 51th clock */ + SWD_CLOCK_BIT; /* 52th clock */ + SWD_CLOCK_BIT; /* 53th clock */ + SWD_CLOCK_BIT; /* 54th clock CDT 127910 */ + + SWD_SET_SDA_IN; + SWD_SET_SDA_HI; + SWD_SET_SCK_HI; + + gbStatsReg |= gbAck; + break; + } + + case SWD_WAIT: + case SWD_FAULT: + { + SWD_SET_SDA_IN; + SWD_SET_SDA_HI; + SWD_SET_SCK_HI; + gbStatsReg |= gbAck; + break; + } + + default: + { + SWD_SET_SDA_IN; + SWD_SET_SDA_HI; + SWD_SET_SCK_HI; + + /* Protocol Error - no response from target */ + gbStatsReg |= SWD_ERROR; + break; + } + } + CyExitCriticalSection(enableInterrupts); + return; +} + +/****************************************************************************** +* SWDWrite +***************************************************************************//** +* Executes SWD-write command on the bus. Command located at bufOut, +* result (ACK) is returned to buf_ACK buffer. +* +* @param[in] bufOut pointer to buffer +* @param[out] buf_ACK buffer for return (ACK). +* +******************************************************************************/ +static void SWDWrite(uint8_t *bufOut, uint8_t *buf_ACK) +{ + /* bRetry - should only take 2 at most */ + register uint8_t bRetry = MAX_SWD_WRITE_RTRY; + + gbHeader = bufOut[0u]; + + do + { + SWDPutData(&bufOut[1u]); + }while (--bRetry && ((gbStatsReg & SWD_ACK_BITS) == SWD_ACK_BITS)); + + buf_ACK[0u] = gbStatsReg | SWD_DONE; + return; +} + + +/****************************************************************************** +* SWDAcquirePSoC6BLE +***************************************************************************//** +* Acquires PSoC 6 BLE. +* +* @param[in] acquireMode Reset or Power cycle acquire. +* @param[in] attempts Number of retries before declaring acquire failed. +* +* @return Flag whether the PSoC 6 BLE is acquired or not (ACQUIRE_PASS / +* ACQUIRE_FAIL). +* +******************************************************************************/ +uint32_t SWDAcquirePSoC6BLE(uint8_t acquireMode, uint8_t attempts) +{ + uint8_t count; + bool ret = false; + uint8_t bData[SWD_DATA_SIZE]; + uint8_t bAck; + uint8_t enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + /* Acquire algorithm for PSoC6 */ + for (count = 0u; count < attempts; count++) + { + bool swdAcquired = false; + uint16_t tmrVal = 0u; + uint16_t tmrDiff = 0u; + +// just only reset mode implemented +// +// if (acquireMode == 0u) +// { +// (void)RESET_TARGET(); +// } +// else +// { +// /* PowerCycle mode acquire. */ +// if (KitIsMiniProg()) +// { +// Pin_VoltageEn_Write(0u); +// CyDelayUs(100u); +// Pin_VoltageEn_Write(1u); +// CyDelayUs(100u); +// } +// } + (void)RESET_TARGET(); + + /* #1 Try to acquire SWD port */ + tmrVal = Timer_CSTick_ReadCounter(); + + do + { + /* Send JTAG to SWD sequence with LineReset before and after */ + SWDSwitchJTAGToSWD(); + + /* Read SWD ID code */ + gbData[0u] = 0u; + gbHeader = DPACC_DP_IDCODE_READ; + + /* gbData contains actual ID */ + SWDGetData(gbData); + swdAcquired = (gbStatsReg & (SWD_ACK_BITS | SWD_PERR)) == SWD_ACK; + + /* Timer_CSTick is running at 8Hz rate */ + /* It is used as a time source here instead of loop counter */ + /* This ensures we will get `real` timeout value */ + tmrDiff = tmrVal - Timer_CSTick_ReadCounter(); + } + while ((tmrDiff < PSOC6_TVII_AQUIRE_TIMEOUT_TICKS) && (!swdAcquired)); + + if(!swdAcquired) + { + /* NACK, try to acquire again */ + continue; + } + + /* #2 Reset SWD bus */ + SWDResetBus(); + + /* #3 Send Target Select request*/ + /* Not needed for CMR PSVP bitfile */ + /* bData[0u] = 0x99u; + bData[1u] = 0x00u; + bData[2u] = 0x00u; + bData[3u] = 0x00u; + bData[4u] = 0x00u; + SWDWrite(bData, &bAck); */ + + /* #4 Read SWD ID code */ + gbData[0u] = 0u; + gbHeader = DPACC_DP_IDCODE_READ; + SWDGetData(gbData); + + /* Check status for the Read SWD ID code request */ + if ((gbStatsReg & (SWD_ACK_BITS | SWD_PERR)) != SWD_ACK ) + { + /* NACK, try to acquire again */ + continue; + } + + /* #5 Power up debug port */ + bData[0u] = DPACC_DP_CTRLSTAT_WRITE; + bData[1u] = (uint8) DP_POWER_UP_VALUE; + bData[2u] = (uint8)(DP_POWER_UP_VALUE >> SHIFT_8); + bData[3u] = (uint8)(DP_POWER_UP_VALUE >> SHIFT_16); + bData[4u] = (uint8)(DP_POWER_UP_VALUE >> SHIFT_24); + SWDWrite(bData, &bAck); + + /* Check status for the Power up debug port request*/ + if ((bAck & SWD_ACK_BITS) != SWD_ACK ) + { + /* NACK, try to acquire again */ + continue; + } + + /* #6 Select SYS AP*/ + bData[0u] = DPACC_DP_SELECT_WRITE; + bData[1u] = (uint8) SYS_AP; + bData[2u] = (uint8)(SYS_AP >> SHIFT_8); + bData[3u] = (uint8)(SYS_AP >> SHIFT_16); + bData[4u] = (uint8)(SYS_AP >> SHIFT_24); + SWDWrite(bData, &bAck); + + /* Check status for the Select SYS AP request */ + if ((bAck & SWD_ACK_BITS) != SWD_ACK ) + { + /* NACK, try to acquire again */ + continue; + } + + /* #7 Set 32-bit transfer mode*/ + bData[0u] = DPACC_AP_CSW_WRITE; + bData[1u] = (uint8) TRANSFER_MODE_32BIT; + bData[2u] = (uint8)(TRANSFER_MODE_32BIT >> SHIFT_8); + bData[3u] = (uint8)(TRANSFER_MODE_32BIT >> SHIFT_16); + bData[4u] = (uint8)(TRANSFER_MODE_32BIT >> SHIFT_24); + SWDWrite(bData, &bAck); + + /* Check status for the Set 32-bit transfer mode request*/ + if ((bAck & SWD_ACK_BITS) != SWD_ACK ) + { + /* NACK, try to acquire again */ + continue; + } + + /* #8 Set Test Mode*/ + /* #8.1 Set Test Mode register as destination */ + bData[0u] = DPACC_AP_TAR_WRITE; + bData[1u] = (uint8) TEST_MODE_REGISTER; + bData[2u] = (uint8)(TEST_MODE_REGISTER >> SHIFT_8); + bData[3u] = (uint8)(TEST_MODE_REGISTER >> SHIFT_16); + bData[4u] = (uint8)(TEST_MODE_REGISTER >> SHIFT_24); + SWDWrite(bData, &bAck); + + /* Check status for the set Test mode register as destination request */ + if ((bAck & SWD_ACK_BITS) != SWD_ACK ) + { + /* NACK, try to acquire again */ + continue; + } + + /* #8.2 Write data into Test Mode register*/ + bData[0u] = DPACC_AP_DRW_WRITE; + bData[1u] = (uint8) TEST_MODE_VALUE; + bData[2u] = (uint8)(TEST_MODE_VALUE >> SHIFT_8); + bData[3u] = (uint8)(TEST_MODE_VALUE >> SHIFT_16); + bData[4u] = (uint8)(TEST_MODE_VALUE >> SHIFT_24); + SWDWrite(bData, &bAck); + + /* Check status for the data write into Test Mode register request */ + if ((bAck & SWD_ACK_BITS) != SWD_ACK) + { + /* NACK, try to acquire again */ + continue; + } + + /* #9 Read SWD ID code */ + gbData[0u] = 0u; + gbHeader = DPACC_DP_IDCODE_READ; + SWDGetData(gbData); + + /* Check status for the Read SWD ID code request*/ + if ((gbStatsReg & (SWD_ACK_BITS | SWD_PERR)) != SWD_ACK ) + { + /* NACK, try to acquire again */ + continue; + } + + ret = true; + break; + } + + CyExitCriticalSection(enableInterrupts); + + return (ret ? ACQUIRE_PASS : ACQUIRE_FAIL); +} + +/******************************************************************************* +* Function Name: CheckHWVerPerPin() +******************************************************************************** +* Summary: +* Checks whether the pins are floating or grounded. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +uint8_t CheckHWVerPerPin(uint8_t bValuePullup, uint8_t bValuePullDwn) +{ + uint8_t bHwVer = NOT_CONNECTED; + + if(bValuePullup != 0 && bValuePullDwn == 0) + { + /* Follows pull up/down, so it is floating */ + bHwVer = NOT_CONNECTED; + } + else if(bValuePullup == 0 && bValuePullDwn == 0) + { + /* Always LOW, so it is GND */ + bHwVer = GROUND; + } + else + { + /* Shall not be here because these lines are never pulled up in the hardware */ + } + + return bHwVer; +} + +/******************************************************************************* +* Function Name: GetHWVersion() +******************************************************************************** +* Summary: +* Calculates the hardware version of the KitProg board. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +uint8_t get_hw_id(void) +{ + uint8_t kitProgHwId; + kitProgHwId = (~Pin_HWVersion_Read()) & Pin_HWVersion_MASK; + + /* These pins no longer used, set them to HiZ analogue to save power */ + Pin_HWVersion_SetDriveMode(Pin_HWVersion_DM_ALG_HIZ); + + return kitProgHwId; + +} +/******************************************************************************* +* Function Name: WriteSWD() +******************************************************************************** +* Summary: +* Executes SWD-write command on the bus. Command located at (bufOut + *bufOutOffset), +* result (ACK) is returned to buf_ACK buffer. +* +* Parameters: +* pointers to the buffer addresses +* +* Return: +* void +* +*******************************************************************************/ +static void WriteSWD(uint8_t *bufOut, uint8_t *buf_ACK) +{ + // bRetry - should only take 2 at most + register uint8_t bRetry = MAX_SWD_WRITE_RTRY; + + gbHeader = bufOut[0u]; + + do + { + SWDPutData(&bufOut[1u]); + }while (--bRetry && ((gbStatsReg & SWD_ACK_BITS) == SWD_ACK_BITS)); + + buf_ACK[0] = gbStatsReg | SWD_DONE; + return; +} + +/******************************************************************************* +* Function Name: SWD_Send() +******************************************************************************** +* Summary: +* Writes 32-bit data into specified address of CPU address space. +* Returns “true” if all SWD transactions succeeded (ACKed). +* +* Parameters: +* addr_32 - Address at which the data has to be written in CPU address space +* data_32 - 32-bit variable containing the value to be written +* +* Return: +* bAck - Acknowledge packet for the last SWD transaction +* +*******************************************************************************/ +uint8_t SWD_Send(uint32_t addr_32, uint32_t data_32) +{ + uint8_t bData[SWD_DATA_SIZE]; + uint8_t bAck; + uint8_t status; + + // Prepare SWD packet header for DPACC_AP_TAR_WRITE + bData[0u] = DPACC_AP_TAR_WRITE; + + // Prepare SWD data + bData[1u] = (uint8) addr_32; + bData[2u] = (uint8)(addr_32 >> SHIFT_8); + bData[3u] = (uint8)(addr_32 >> SHIFT_16); + bData[4u] = (uint8)(addr_32 >> SHIFT_24); + + // Send SWD data for addres + WriteSWD(bData, &bAck); + + if ((bAck & SWD_ACK_BITS) != SWD_ACK ) + { + status = (bAck & SWD_ACK_BITS); + } + else + { + // Prepare SWD packet header for DPACC_AP_DRW_WRITE + bData[0u] = DPACC_AP_DRW_WRITE; + + // Prepare SWD data + bData[1u] = (uint8) data_32; + bData[2u] = (uint8)(data_32 >> SHIFT_8); + bData[3u] = (uint8)(data_32 >> SHIFT_16); + bData[4u] = (uint8)(data_32 >> SHIFT_24); + + // Send SWD data for data + WriteSWD(bData, &bAck); + + status = (bAck & SWD_ACK_BITS); + } + + return status; +} + +/****************************************************************************** +* Function Name: SWD_Receive() +******************************************************************************* +* +* Summary: +* Reads 32-bit date from specified address of CPU address space. +* Returns OK ACK if all SWD transactions succeeds (ACKed). +* +* Parameters: +* addr_32 - Address from which the data has to be read from CPU address space +* data_32 - 32-bit variable containing the read value +* +* Return: +* Swd_PacketAck - Acknowledge packet for the last SWD transaction +* +*******************************************************************************/ +uint8_t SWD_Receive(uint32_t adr_32, uint32_t *data_32) +{ + uint8_t bData[SWD_DATA_SIZE]; + uint8_t bAck; + + /* Prepare SWD packet header for DPACC_AP_TAR_WRITE */ + bData[0u] = DPACC_AP_TAR_WRITE; + + /* Prepare SWD data */ + bData[1u] = (uint8) adr_32; + bData[2u] = (uint8)(adr_32 >> SHIFT_8); + bData[3u] = (uint8)(adr_32 >> SHIFT_16); + bData[4u] = (uint8)(adr_32 >> SHIFT_24); + + /* Send SWD data for addres */ + WriteSWD(bData, &bAck); + + if ((bAck & SWD_ACK_BITS) != SWD_ACK ) + { + return (bAck & SWD_ACK_BITS); + } + + /* Get IPC_STRUCT acquire status */ + gbData[0u] = 0u; + gbHeader = DPACC_AP_DRW_READ; + SWDGetData(gbData); + + /* Check status for the read IPC_STRUCT acquire status request*/ + if ((gbStatsReg & (SWD_ACK_BITS | SWD_PERR)) != SWD_ACK ) + { + return (gbStatsReg & (SWD_ACK_BITS | SWD_PERR)); + } + + /* Get IPC_STRUCT acquire status */ + gbData[0u] = 0u; + gbHeader = DPACC_AP_DRW_READ; + SWDGetData(gbData); + + /* Check status for the read IPC_STRUCT acquire status request*/ + if ((gbStatsReg & (SWD_ACK_BITS | SWD_PERR)) != SWD_ACK ) + { + return (gbStatsReg & (SWD_ACK_BITS | SWD_PERR)); + } + + *data_32 = (uint32) gbData[0u]+\ + (((uint32)gbData[1u]) << SHIFT_8)+\ + (((uint32)gbData[2u]) << SHIFT_16)+\ + (((uint32)gbData[3u]) << SHIFT_24); + + return (gbStatsReg & (SWD_ACK_BITS | SWD_PERR)); +} + +/****************************************************************************** +* Function Name: PSoC6_Ipc_PollLockStatus() +******************************************************************************* +* Summary: +* Lock defined IPC_STRUCT status +* +* Parameters: +* ipcID : IPC_STRUCT ID number 0- IPC_STRUCT_0, 1- IPC_STRUCT_1, +* 2- IPC_STRUCT_2 +* lockExpected : expected status value +* timeout : IPC_STRUCTX acquring timeout +* dev_family : device family ID 0 - CY8C6XX6,CY8C6XX7, 1 - CY8C6XX8,CY8C6XXA +* +* Return: +* SWD_ACK - IPC_STRUCT_X status was sucsesfully locked +* !SWD_ACK - IPC_STRUCT_X status was not locked +* +******************************************************************************/ +static uint8_t PSoC6_Ipc_PollLockStatus(uint8_t ipcId, uint8_t lockExpected, uint32_t timeout, uint8_t dev_family) +{ + uint32_t timeElapsed = 0u; + uint32_t readData = 0; + uint32_t ipcAddr; + uint8_t status; + uint8_t isExpectedStatus; + + /* Calculate IPC_STRUCT lock status address based on device family */ + if (dev_family == PSOC6_67) + { + ipcAddr = IPC_STRUCT0_1M + IPC_STRUCT_SIZE * ipcId + IPC_STRUCT_LOCK_STATUS_OFFSET_1M; + } + else + { + ipcAddr = IPC_STRUCT0_2M + IPC_STRUCT_SIZE * ipcId + IPC_STRUCT_LOCK_STATUS_OFFSET_2M; + } + + do + { + /* Check Lock Status */ + status = SWD_Receive(ipcAddr, &readData); + isExpectedStatus = (lockExpected && (readData & IPC_STRUCT_LOCK_STATUS_ACQUIRED_MSK) ) || (!lockExpected && !(readData & IPC_STRUCT_LOCK_STATUS_ACQUIRED_MSK)); + + if (status != SWD_ACK) + { + timeElapsed = timeout; + } + + timeElapsed ++; + } + while((isExpectedStatus == 0) && (timeElapsed < timeout)); + + return (status); +} + +/****************************************************************************** +* Function Name: PSoC6_Ipc_Acquire() +******************************************************************************* +* Summary: +* Acquire defined IPC structure before executing SROM API +* +* Parameters: +* ipcID : IPC_STRUCT ID number 0- IPC_STRUCT_0, 1- IPC_STRUCT_1, +* 2- IPC_STRUCT_2 +* timeout : IPC_STRUCTX acquring timeout +* dev_family : device family ID 0 - CY8C6XX6,CY8C6XX7, 1 - CY8C6XX8,CY8C6XXA +* +* Return: +* SWD_ACK - IPC_STRUCT_X was sucsesfully acquired +* !SWD_ACK - IPC_STRUCT_X acquiring was not performed +* +******************************************************************************/ +static uint8_t PSoC6_Ipc_Acquire(uint8_t ipcId, uint32_t timeout, uint8_t dev_family) +{ + uint32_t timeElapsed = 0u; + uint32_t readData = 0; + uint32_t ipcAddr; + uint8_t status; + + /* Calculate IPC_STRUCT address based on device family */ + if (dev_family == PSOC6_67) + { + ipcAddr = IPC_STRUCT0_1M + IPC_STRUCT_SIZE * ipcId + IPC_STRUCT_ACQUIRE_OFFSET; + } + else + { + ipcAddr = IPC_STRUCT0_2M + IPC_STRUCT_SIZE * ipcId + IPC_STRUCT_ACQUIRE_OFFSET; + } + + do + { + /* Acquire the lock in DAP IPC struct (IPC_STRUCT.ACQUIRE).*/ + status = SWD_Send(ipcAddr, IPC_STRUCT_ACQUIRE_SUCCESS_MSK); + + if ( status != SWD_ACK) + { + timeElapsed = timeout; + } + else + { + /* Read written value back. */ + status = SWD_Receive(ipcAddr, &readData); + + if ( status != SWD_ACK) + { + timeElapsed = timeout; + } + } + + timeElapsed++; + } + while(((readData & IPC_STRUCT_ACQUIRE_SUCCESS_MSK) == 0) && (timeElapsed < timeout)); + + if (status == SWD_ACK) + { + /* Check PSoC6_Ipc_PollLockStatus */ + status = PSoC6_Ipc_PollLockStatus(ipcId ,1u ,timeout - timeElapsed, dev_family); + } + + return (status); +} + +/****************************************************************************** +* Function Name: PSoC6_PollSromApiStatus +******************************************************************************* +* Summary: +* Polls the IPC_STRUCT status/data till previous API call is completed or +* a timeout condition occurred, whichever is earlier. +* +* Parameters: +* addr_32: SROM API status polling address +* timeout: Polling timeout +* dataOut: Pinter to API executing data +* +* Return: +* SWD_ACK - SROM executed the task successfully +* !SWD_ACK - SROM task is not executed successfully and a timeout error occured. +* The failure code is stored in the statusCode global variable. +* +* Note: +* This function is called after non volatile memory operations like Read, +* Write of Flash, to check if SROM task has been executed which is indicated +* by SWD_ACK. +* +******************************************************************************/ +static uint8_t PSoC6_PollSromApiStatus(uint32_t addr_32, uint32_t timeout, uint32_t *dataOut) +{ + uint32_t timeElapsed = 0u; + uint8_t status; + + do + { + /* Poll data */ + status = SWD_Receive(addr_32, dataOut); + + if (status != SWD_ACK) + { + timeElapsed = timeout; + } + + timeElapsed++; + } + while ((( *dataOut & SROM_STATUS_SUCCESS_MASK) != MXS40_SROMAPI_STAT_SUCCESS)\ + && (timeElapsed < timeout)); + + return (status); +} + +/****************************************************************************** +* Function Name: PSoC6_CallSromApi() +******************************************************************************* +* Summary: +* Call PSoC6 SROM API. Depending on parameters_32 value s API's arguments can +* be located in IPC data structure or in SRAM memory. Besides API's arguments +* params_32 include API opcode. After API compeletion resulting data is pulled +* out form IPC data struct or from SRAM +* +* Parameters: +* params_32 : 4-byte value that combines API opcode and API arguments location +* data_32 : pionter for 4-byte API return data +* dev_family : device family ID 0 - CY8C6XX6,CY8C6XX7, 1 - CY8C6XX8,CY8C6XXA +* +* Return: +* SUCCESS - SROM executed the task successfully +* FAILURE - SROM task is not executed successfully and a timeout error occured. +* The failure code is stored in the statusCode global variable. +* +* Note: +* This function is called to perform volatile memory operations like Read, +* Write of Flash. +* +******************************************************************************/ +static uint8_t PSoC6_CallSromApi(uint32_t params_32, uint32_t *data_32, uint8_t dev_family) +{ + uint8_t status; + uint8_t apiStatus = 0; + + // Acquire IPC_STRUCT[2] for DAP + status = PSoC6_Ipc_Acquire(IPC_2, IPC_STRUCT_ACQUIRE_TIMEOUT, dev_family); + + if (status == SWD_ACK) + { + // Make System Call + // Write to IPC_STRUCT2.DATA - Sys call ID and Parameters OR address in SRAM, where they are located + if ((params_32 & MXS40_SROMAPI_DATA_LOCATION_MSK) == 0) + { + if (dev_family == PSOC6_67) + { + status = SWD_Send(IPC_STRUCT_DATA_1M, SRAM_SCRATCH_ADDR); + } + else + { + status = SWD_Send(IPC_STRUCT_DATA_2M, SRAM_SCRATCH_ADDR); + } + } + else + { + if (dev_family == PSOC6_67) + { + status = SWD_Send(IPC_STRUCT_DATA_1M, params_32); + } + else + { + status = SWD_Send(IPC_STRUCT_DATA_2M, params_32); + } + } + + if (status == SWD_ACK) + { + // Enable notification interrupt of IPC_INTR_STRUCT0(CM0+) for IPC_STRUCT2 + if (dev_family == PSOC6_67) + { + status = SWD_Send(IPC_INTR_STRUCT_DATA_1M, IPC_INTR_STRUCT_DATA_VALUE); + } + else + { + status = SWD_Send(IPC_INTR_STRUCT_DATA_2M, IPC_INTR_STRUCT_DATA_VALUE); + } + + if (status == SWD_ACK) + { + // Notify to IPC_INTR_STRUCT0. IPC_STRUCT2.MASK <- Notify + if (dev_family == PSOC6_67) + { + status = SWD_Send(IPC_STRUCT2_NOTIFY_DATA_1M, 0x00000001u); + } + else + { + status = SWD_Send(IPC_STRUCT2_NOTIFY_DATA_2M, 0x00000001u); + } + + if (status == SWD_ACK) + { + // Poll lock status + status = PSoC6_Ipc_PollLockStatus(2u, 0u, IPC_STRUCT_ACQUIRE_TIMEOUT, dev_family); + + if (status == SWD_ACK) + { + // Poll Data byte + if ((params_32 & MXS40_SROMAPI_DATA_LOCATION_MSK) == 0) + { + status = PSoC6_PollSromApiStatus(SRAM_SCRATCH_ADDR, IPC_STRUCT_DATA_TIMEOUT, data_32); + } + else + { + if (dev_family == PSOC6_67) + { + status = PSoC6_PollSromApiStatus(IPC_STRUCT2_1M + IPC_STRUCT_DATA_OFFSET, + IPC_STRUCT_DATA_TIMEOUT, data_32); + } + else + { + status = PSoC6_PollSromApiStatus(IPC_STRUCT2_2M + IPC_STRUCT_DATA_OFFSET, + IPC_STRUCT_DATA_TIMEOUT, data_32); + } + } + + if (status == SWD_ACK) + { + apiStatus = 0x01; + } + } + } + } + } + } + + return apiStatus; +} + +/****************************************************************************** +* Function Name: GetSiliconId +******************************************************************************* +* +* Summary: +* This function obtains Silicon Device ID using SROM commands. +* +* Parameters: +* None +* +* Return: +* Device ID - Returns Silicon Device ID read from chip. +* or +* FAILURE - Returns Failure (0x00000000), if any of the intermediate step +* returns a fail message. +* +* Note: +* +******************************************************************************/ +uint32_t get_silcon_id(void) +{ + // read psoc6 silicon id + uint32_t target_siid = 0; + uint32_t parameter1 = 0; + uint32_t siliconIdData1 = 0; + uint32_t siliconIdData2 = 0; + uint8_t enableInterrupts; + uint8_t dev_family = PSOC6_67; + uint8_t i = 0; + + // get family id and revision id + parameter1 = MXS40_SROMAPI_SILID_CODE + PSOC6_SROM_SILID_CODE_LO; + + // Acquire PSoC6 device before reading silicon ID + if (SWDAcquirePSoC6BLE(0u, NUMBER_OF_ATTEMPTS)) + { + enableInterrupts = CyEnterCriticalSection(); + + do + { + if (PSoC6_CallSromApi(parameter1, &siliconIdData1, dev_family)) + { + /* get Silicon ID and protection state */ + parameter1 = MXS40_SROMAPI_SILID_CODE + PSOC6_SROM_SILID_CODE_HI; + + if (PSoC6_CallSromApi(parameter1, &siliconIdData2, dev_family)) + { + target_siid = (siliconIdData1 & PSOC6_FAMILY_ID_LO_MSK) + | ((siliconIdData1 & PSOC6_REV_ID_MAJ_MSK) >> SHIFT_8) + | ((siliconIdData1 & PSOC6_REV_ID_MIN_MSK) >> SHIFT_8) + | ((siliconIdData2 & PSOC6_SILICON_ID_LO_MSK) << SHIFT_16) + | ((siliconIdData2 & PSOC6_SILICON_ID_HI_MSK) << SHIFT_16); + } + } + if (target_siid) + { + i = i + 2; + } + else + { + dev_family = PSOC6_8A; + i++; + } + } while (i < GET_SIID_ATTEMTS); + + CyExitCriticalSection(enableInterrupts); + + } + + return (target_siid & PSOC6_SILICON_ID_MASK); +} + +/****************************************************************************** +* Function Name: SWD_SelectAP +******************************************************************************* +* +* Summary: +* Select debug acces point by writing to AP Select Register. +* Returns OK ACK if all SWD transactions succeeds (ACKed). +* +* Parameters: +* ap - Acsess point number +* +* Return: +* Swd_PacketAck - Acknowledge packet for the last SWD transaction +* +*******************************************************************************/ +uint8_t SWD_SelectAP(uint32_t ap) +{ + uint8_t bData[SWD_DATA_SIZE]; + uint8_t bAck; + + /* Prepare SWD packet header for DPACC_DP_SELECT_WRITE */ + bData[0u] = DPACC_DP_SELECT_WRITE; + + /* Prepare SWD data */ + bData[1u] = (uint8) ap; + bData[2u] = (uint8) (ap >> SHIFT_8); + bData[3u] = (uint8) (ap >> SHIFT_16); + bData[4u] = (uint8) (ap >> SHIFT_24); + + /* Send SWD data for addres */ + WriteSWD(bData, &bAck); + + return (bAck & SWD_ACK_BITS); +} + +/****************************************************************************** +* Function Name: SWD_Abort +******************************************************************************* +* +* Summary: +* Clear error and sticky flag conditions. +* Returns OK ACK if all SWD transactions succeeds (ACKed). +** +* Return: +* Swd_PacketAck - Acknowledge packet for the last SWD transaction +* +*******************************************************************************/ +uint8_t SWD_Abort(void) +{ + uint8_t bData[SWD_DATA_SIZE]; + uint8_t bAck; + + /* Prepare SWD packet header for DPACC_DP_ABORT */ + bData[0u] = DPACC_DP_ABORT_WRITE; + + /* Prepare SWD data */ + bData[1u] = (uint8) DPACC_DP_ABORT_MASK; + bData[2u] = (uint8)(DPACC_DP_ABORT_MASK >> SHIFT_8); + bData[3u] = (uint8)(DPACC_DP_ABORT_MASK >> SHIFT_16); + bData[4u] = (uint8)(DPACC_DP_ABORT_MASK >> SHIFT_24); + + /* Send SWD data for addres */ + WriteSWD(bData, &bAck); + + return (bAck & SWD_ACK_BITS); +} + +/****************************************************************************** +* Function Name: SWD_WriteCSW +******************************************************************************* +* +* Summary: +* Write given value to CSW Register. +* Returns OK ACK if all SWD transactions succeeds (ACKed). +** +* Parameters: +* csw_val - Value to write +* +* Return: +* Swd_PacketAck - Acknowledge packet for the last SWD transaction +* +*******************************************************************************/ +uint8_t SWD_WriteCSW(uint32_t csw_val) +{ + uint8_t bData[SWD_DATA_SIZE]; + uint8_t bAck; + + /* Prepare SWD packet header for CSW write */ + bData[0u] = DPACC_AP_CSW_WRITE; + + /* Prepare SWD data */ + bData[1u] = (uint8) csw_val; + bData[2u] = (uint8) (csw_val >> SHIFT_8); + bData[3u] = (uint8) (csw_val >> SHIFT_16); + bData[4u] = (uint8) (csw_val >> SHIFT_24); + + /* Send SWD data for addres */ + WriteSWD(bData, &bAck); + + return (bAck & SWD_ACK_BITS); +} + +/****************************************************************************** +* Function Name: get_fb_version +******************************************************************************* +* +* Summary: +* Read version of flash boot. +** +* Return: +* version word or 0xFFFFFFFF on error +* +*******************************************************************************/ +uint32_t get_fb_version(void) +{ + uint32_t version; + if (SWD_Receive(FB_VERSION_ADDR, &version) != SWD_ACK) + { + SWD_Abort(); + version = FB_VERSION_UNKNOWN; + } + return version; +} diff --git a/source/family/cypress/PSoC6xxx/PSOC6xxx.h b/source/family/cypress/PSoC6xxx/PSOC6xxx.h new file mode 100644 index 0000000000..cff833e1d3 --- /dev/null +++ b/source/family/cypress/PSoC6xxx/PSOC6xxx.h @@ -0,0 +1,119 @@ +/******************************************************************************* +* @file PSOC6xxx.h +* +* @brief +* This file provides constants and function declaration for PSoC6xxx family +* device acquiring, silicon id reading. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "CyLib.h" + +#if !defined(PSOC6XXX_H) +#define PSOC6XXX_H + +// Acquire result macros +#define ACQUIRE_PASS (0x01u) +#define ACQUIRE_FAIL (0x00u) + +// SWD data macros +#define SWD_DATA_SIZE (5u) + +// Acquire timeout in Timer_CSTick ticks (8Hz rate, 8 ticks == 1000ms) +#define PSOC6_TVII_AQUIRE_TIMEOUT_TICKS (8u) + +// Data shift +#define SHIFT_24 (24u) +#define SHIFT_16 (16u) +#define SHIFT_12 (12u) +#define SHIFT_8 (8u) +#define SHIFT_4 (4u) +#define SHIFT_2 (2u) + +// Device family ID definitions +#define PSOC6_67 (0x01u) +#define PSOC6_8A (0x02u) + +// CY8C6xx6, CY8C6XX7 devices +#define MEM_BASE_IPC_1M (0x40230000u) +#define IPC_STRUCT0_1M MEM_BASE_IPC_1M +#define IPC_STRUCT1_1M (IPC_STRUCT0_1M + IPC_STRUCT_SIZE) +#define IPC_STRUCT2_1M (IPC_STRUCT1_1M + IPC_STRUCT_SIZE) +#define IPC_INTR_STRUCT_1M (0x40231000u) +#define IPC_STRUCT_LOCK_STATUS_OFFSET_1M (0x10u) +#define IPC_STRUCT_DATA_1M (IPC_STRUCT2_1M + IPC_STRUCT_DATA_OFFSET) +#define IPC_STRUCT2_NOTIFY_DATA_1M (IPC_STRUCT2_1M + IPC_STRUCT_NOTIFY_OFFSET) +#define IPC_INTR_STRUCT_DATA_1M (IPC_INTR_STRUCT_1M + IPC_INTR_STRUCT_INTR_IPC_MASK_OFFSET) +#define IPC_CONST_1M (0x000104000u) + +// CY8C6xx8, CY8C6XXA devices +#define MEM_BASE_IPC_2M (0x40220000u) +#define IPC_STRUCT0_2M MEM_BASE_IPC_2M +#define IPC_STRUCT1_2M (IPC_STRUCT0_2M + IPC_STRUCT_SIZE) +#define IPC_STRUCT2_2M (IPC_STRUCT1_2M + IPC_STRUCT_SIZE) +#define IPC_INTR_STRUCT_2M (0x40221000u) +#define IPC_STRUCT_LOCK_STATUS_OFFSET_2M (0x1Cu) +#define IPC_STRUCT_DATA_2M (IPC_STRUCT2_2M + IPC_STRUCT_DATA_OFFSET) +#define IPC_STRUCT2_NOTIFY_DATA_2M (IPC_STRUCT2_2M + IPC_STRUCT_NOTIFY_OFFSET) +#define IPC_INTR_STRUCT_DATA_2M (IPC_INTR_STRUCT_2M + IPC_INTR_STRUCT_INTR_IPC_MASK_OFFSET) +#define IPC_CONST_2M (0x00000000u) + +// IPC strustures definitions fro PSoC6 SROM API usage +#define MXS40_SROMAPI_SILID_CODE (0x00000001u) +#define PSOC6_SROM_SILID_CODE_LO (0x0000FF00u & (0u << SHIFT_8)) +#define PSOC6_SROM_SILID_CODE_HI (0x0000FF00u & (1u << SHIFT_8)) +#define IPC_2 (2u) +#define IPC_STRUCT_SIZE (0x20u) +#define IPC_STRUCT_ACQUIRE_TIMEOUT (5000u) +#define MXS40_SROMAPI_DATA_LOCATION_MSK (0x00000001u) +#define SRAM_SCRATCH_ADDR (0x08000400u) +#define IPC_INTR_STRUCT_INTR_IPC_MASK_OFFSET (0x08u) +#define IPC_INTR_STRUCT_DATA_VALUE (1u << (SHIFT_16 + 2u)) +#define IPC_STRUCT_DATA_OFFSET (0x0Cu) +#define IPC_STRUCT_NOTIFY_OFFSET (0x08u) +#define IPC_STRUCT_DATA_TIMEOUT (9000u) +#define IPC_STRUCT_ACQUIRE_OFFSET (0x00u) +#define IPC_STRUCT_ACQUIRE_SUCCESS_MSK (0x80000000u) +#define IPC_STRUCT_LOCK_STATUS_ACQUIRED_MSK (0x80000000u) +#define SROM_STATUS_SUCCESS_MASK (0xF0000000u) +#define MXS40_SROMAPI_STAT_SUCCESS (0xA0000000u) + +// Number of PSoC6 acquiring attempts +#define NUMBER_OF_ATTEMPTS (0x10u) + +// Number of PSoC6 silicon ID reading attemts +#define GET_SIID_ATTEMTS (2u) + +// Masks for Silicond ID parts for PSoC6 +#define PSOC6_FAMILY_ID_HI_MSK (0x0000FF00u) +#define PSOC6_FAMILY_ID_LO_MSK (0x000000FFu) +#define PSOC6_REV_ID_MAJ_MSK (0x00F00000u) +#define PSOC6_REV_ID_MIN_MSK (0x000F0000u) +#define PSOC6_SILICON_ID_LO_MSK (0x000000FFu) +#define PSOC6_SILICON_ID_HI_MSK (0x0000FF00u) +#define PSOC6_SILICON_ID_MASK (0xFFFF00FFu) + +// Family ID for PSoC6xxx targets +#define PSOC6_BLE_FAMILY_ID_LO (0x00u) +#define PSOC6_2M_FAMILY_ID_LO (0x02u) + +// Possible HW Version Pin States +#define NOT_CONNECTED (0x00u) +#define GROUND (0x01u) + +#endif /* PSOC6XXX_H */ diff --git a/source/family/cypress/PSoC6xxx/p6_2m_flash_blob.c b/source/family/cypress/PSoC6xxx/p6_2m_flash_blob.c new file mode 100644 index 0000000000..c2f7b7742f --- /dev/null +++ b/source/family/cypress/PSoC6xxx/p6_2m_flash_blob.c @@ -0,0 +1,680 @@ +/******************************************************************************* +* @file p6_2m_flash_blob.c +* @brief Flash algorithm for the PSoC6 2M target MCU +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "flash_blob.h" + +// Main Flash algo + +static const uint32_t CY8C6xxA_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x20004603, 0x46014770, 0x47702000, 0xf000b510, 0xbd10f972, 0x4604b510, 0xf0004620, 0xbd10f915, + 0x4606b570, 0x4615460c, 0x46294622, 0xf0004630, 0xbd70f969, 0x4604b570, 0x4616460d, 0x46294632, + 0xf0004620, 0xbd70f81f, 0x47706001, 0x600a6802, 0x21004770, 0x1c49e000, 0x43424ad6, 0xd8fa428a, + 0xb5084770, 0x48d44669, 0xfff0f7ff, 0x0209210f, 0x40089800, 0xd1012800, 0xe0002001, 0x46032000, + 0xbd084618, 0x4603b570, 0x461d460c, 0xe0052100, 0x5c6e5c50, 0xd00042b0, 0x1c49e002, 0xd3f742a1, + 0x1858bf00, 0xb5febd70, 0x460b4605, 0x20004616, 0x24009002, 0x01682700, 0x184049c0, 0xbf009000, + 0x9800a901, 0xf7ff301c, 0x9801ffc1, 0x2b000fc7, 0x2f00d001, 0x2b00d103, 0x2f00d103, 0x2001d101, + 0x2000e000, 0x2c004604, 0x9802d109, 0xd90042b0, 0x2001e007, 0xffadf7ff, 0x1c409802, 0x2c009002, + 0xbf00d0de, 0x21014620, 0xbdfe4048, 0x4604b5f8, 0x2600460d, 0x01602300, 0x184749a8, 0x4669bf00, + 0xf7ff4638, 0x9800ff93, 0x2b000fc3, 0x42aed106, 0xe005d900, 0xf7ff2001, 0x1c76ff8c, 0xd0ee2b00, + 0x4618bf00, 0x40482101, 0xb5f0bdf8, 0x460d4607, 0x26004613, 0xbf002400, 0x46384619, 0xff76f7ff, + 0x0f006818, 0x21050700, 0x42880749, 0x2001d101, 0x2000e000, 0x2c004604, 0x42aed106, 0xe005d900, + 0xf7ff2001, 0x1c76ff66, 0xd0e52c00, 0x4620bf00, 0x40482101, 0xb5f3bdf0, 0x4606b082, 0x48882700, + 0x90014478, 0x0fc007f0, 0x40482101, 0x25009000, 0xff57f7ff, 0xd0022800, 0x4d802400, 0x2401e002, + 0x35204d7e, 0x31f521ff, 0xf7ff4620, 0x4607ff9f, 0xd1362f00, 0x28009800, 0x4628d005, 0x9901300c, + 0xff32f7ff, 0x4631e004, 0x300c4628, 0xff2cf7ff, 0x30104620, 0x40822201, 0x48724611, 0xff24f7ff, + 0x46282101, 0xf7ff3008, 0x22ffff1f, 0x210032f5, 0xf7ff4620, 0x4607ff48, 0xd1122f00, 0x28009800, + 0x21ffd007, 0x9a0331f5, 0xf7ff9801, 0x4607ff8e, 0x21ffe007, 0x462831f5, 0x9a03300c, 0xff85f7ff, + 0x46384607, 0xbdf0b004, 0x4604b538, 0x447d4d5c, 0x495d3dae, 0xf7ff4628, 0x4621fef7, 0xf7ff1d28, + 0x4669fef3, 0xf7ff4858, 0xbd38ff96, 0x4604b538, 0x447d4d53, 0x49553dd2, 0xf7ff4628, 0x4621fee5, + 0xf7ff1d28, 0x4669fee1, 0xf7ff4850, 0xbd38ff84, 0x4604b538, 0x447d4d4a, 0x494c3df6, 0xf7ff4628, + 0x4621fed3, 0xf7ff1d28, 0x4669fecf, 0xf7ff4847, 0xbd38ff72, 0x4c46b518, 0x4946447c, 0xf7ff4620, + 0x4669fec3, 0xf7ff4843, 0xbd18ff66, 0x4606b570, 0x2500460c, 0x4630e00a, 0xffb6f7ff, 0x2d004605, + 0xe005d000, 0x36ff36ff, 0x1e643602, 0xd1f22c00, 0x4628bf00, 0xb510bd70, 0xf7ff2400, 0x4604ffdb, + 0xbd104620, 0x4605b5f8, 0x4617460e, 0x447c4c30, 0x49313c56, 0xf7ff4620, 0x21fffe97, 0x1d203107, + 0xfe92f7ff, 0x46204629, 0xf7ff3008, 0x4631fe8d, 0x300c4620, 0xfe88f7ff, 0x48274669, 0xff2bf7ff, + 0xb5f8bdf8, 0x460e4605, 0x4c214617, 0x3c94447c, 0x46204922, 0xfe78f7ff, 0x310721ff, 0xf7ff1d20, + 0x4629fe73, 0x30084620, 0xfe6ef7ff, 0x46204631, 0xf7ff300c, 0x4669fe69, 0xf7ff4818, 0xbdf8ff0c, + 0xb0ffb570, 0x4605b081, 0x24002600, 0x2000e003, 0x55084669, 0x20011c64, 0x42840240, 0x4602dbf7, + 0x46284669, 0xffcdf7ff, 0x46304606, 0xb001b07f, 0x0000bd70, 0x00000d05, 0x40200000, 0x40220000, + 0x0000023c, 0x40221008, 0x1c000100, 0x14000100, 0x00000124, 0x0a000100, 0x06000100, 0x05000100, + 0x00000000 +}; + +// Start address of flash +// static const uint32_t flash_start = 0x10000000; +// Size of flash +// static const uint32_t flash_size = 0x00100000; + +/** +* List of start and size for each size of flash sector - even indexes are start, odd are size +* The size will apply to all sectors between the listed address and the next address +* in the list. +* The last pair in the list will have sectors starting at that address and ending +* at address flash_start + flash_size. +*/ + +// WFLASH (Work) algo +static const uint32_t CY8C6xxA_WFLASH_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x20004603, 0x46014770, 0x47702000, 0xf000b510, 0xbd10f972, 0x4604b510, 0xf0004620, 0xbd10f915, + 0x4606b570, 0x4615460c, 0x46294622, 0xf0004630, 0xbd70f96c, 0x4604b570, 0x4616460d, 0x46294632, + 0xf0004620, 0xbd70f81f, 0x47706001, 0x600a6802, 0x21004770, 0x1c49e000, 0x43424ad7, 0xd8fa428a, + 0xb5084770, 0x48d54669, 0xfff0f7ff, 0x0209210f, 0x40089800, 0xd1012800, 0xe0002001, 0x46032000, + 0xbd084618, 0x4603b570, 0x461d460c, 0xe0052100, 0x5c6e5c50, 0xd00042b0, 0x1c49e002, 0xd3f742a1, + 0x1858bf00, 0xb5febd70, 0x460b4605, 0x20004616, 0x24009002, 0x01682700, 0x184049c1, 0xbf009000, + 0x9800a901, 0xf7ff301c, 0x9801ffc1, 0x2b000fc7, 0x2f00d001, 0x2b00d103, 0x2f00d103, 0x2001d101, + 0x2000e000, 0x2c004604, 0x9802d109, 0xd90042b0, 0x2001e007, 0xffadf7ff, 0x1c409802, 0x2c009002, + 0xbf00d0de, 0x21014620, 0xbdfe4048, 0x4604b5f8, 0x2600460d, 0x01602300, 0x184749a9, 0x4669bf00, + 0xf7ff4638, 0x9800ff93, 0x2b000fc3, 0x42aed106, 0xe005d900, 0xf7ff2001, 0x1c76ff8c, 0xd0ee2b00, + 0x4618bf00, 0x40482101, 0xb5f0bdf8, 0x460d4607, 0x26004613, 0xbf002400, 0x46384619, 0xff76f7ff, + 0x0f006818, 0x21050700, 0x42880749, 0x2001d101, 0x2000e000, 0x2c004604, 0x42aed106, 0xe005d900, + 0xf7ff2001, 0x1c76ff66, 0xd0e52c00, 0x4620bf00, 0x40482101, 0xb5f3bdf0, 0x4606b082, 0x48892700, + 0x90014478, 0x0fc007f0, 0x40482101, 0x25009000, 0xff57f7ff, 0xd0022800, 0x4d812400, 0x2401e002, + 0x35204d7f, 0x31f521ff, 0xf7ff4620, 0x4607ff9f, 0xd1362f00, 0x28009800, 0x4628d005, 0x9901300c, + 0xff32f7ff, 0x4631e004, 0x300c4628, 0xff2cf7ff, 0x30104620, 0x40822201, 0x48734611, 0xff24f7ff, + 0x46282101, 0xf7ff3008, 0x22ffff1f, 0x210032f5, 0xf7ff4620, 0x4607ff48, 0xd1122f00, 0x28009800, + 0x21ffd007, 0x9a0331f5, 0xf7ff9801, 0x4607ff8e, 0x21ffe007, 0x462831f5, 0x9a03300c, 0xff85f7ff, + 0x46384607, 0xbdf0b004, 0x4604b538, 0x447d4d5d, 0x495e3dae, 0xf7ff4628, 0x4621fef7, 0xf7ff1d28, + 0x4669fef3, 0xf7ff4859, 0xbd38ff96, 0x4604b538, 0x447d4d54, 0x49563dd2, 0xf7ff4628, 0x4621fee5, + 0xf7ff1d28, 0x4669fee1, 0xf7ff4851, 0xbd38ff84, 0x4604b538, 0x447d4d4b, 0x494d3df6, 0xf7ff4628, + 0x4621fed3, 0xf7ff1d28, 0x4669fecf, 0xf7ff4848, 0xbd38ff72, 0x4c47b518, 0x4947447c, 0xf7ff4620, + 0x4669fec3, 0xf7ff4844, 0xbd18ff66, 0x4606b570, 0x2500460c, 0x4630e00a, 0xffb6f7ff, 0x2d004605, + 0xe005d000, 0x36ff36ff, 0x1e643602, 0xd1f22c00, 0x4628bf00, 0xb510bd70, 0x21402400, 0x06802005, + 0xffe4f7ff, 0x46204604, 0xb5f8bd10, 0x460e4605, 0x4c304617, 0x3c5c447c, 0x46204930, 0xfe94f7ff, + 0x310721ff, 0xf7ff1d20, 0x4629fe8f, 0x30084620, 0xfe8af7ff, 0x46204631, 0xf7ff300c, 0x4669fe85, + 0xf7ff4826, 0xbdf8ff28, 0x4605b5f8, 0x4617460e, 0x447c4c20, 0x49223c9a, 0xf7ff4620, 0x21fffe75, + 0x1d203107, 0xfe70f7ff, 0x46204629, 0xf7ff3008, 0x4631fe6b, 0x300c4620, 0xfe66f7ff, 0x48184669, + 0xff09f7ff, 0xb570bdf8, 0xb081b0ff, 0x26004605, 0xe0032400, 0x46692000, 0x1c645508, 0x02402001, + 0xdbf74284, 0x46694602, 0xf7ff4628, 0x4606ffcd, 0xb07f4630, 0xbd70b001, 0x00000d05, 0x40200000, + 0x40220000, 0x00000240, 0x40221008, 0x1c000100, 0x14000100, 0x00000128, 0x0a000100, 0x06000100, + 0x05000100, 0x00000000 +}; + +// SFLASH: User Data algo +static const uint32_t CY8C6xxA_SFLASH_USER_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x20004603, 0x46014770, 0x47702000, 0xf000b510, 0xbd10f9aa, 0x4604b510, 0xf0004620, 0xbd10f976, + 0x4606b570, 0x4615460c, 0x46294622, 0xf0004630, 0xbd70f94d, 0x4604b570, 0x4616460d, 0x46294632, + 0xf0004620, 0xbd70f81f, 0x47706001, 0x600a6802, 0x21004770, 0x1c49e000, 0x43424ad7, 0xd8fa428a, + 0xb5084770, 0x48d54669, 0xfff0f7ff, 0x0209210f, 0x40089800, 0xd1012800, 0xe0002001, 0x46032000, + 0xbd084618, 0x4603b570, 0x461d460c, 0xe0052100, 0x5c6e5c50, 0xd00042b0, 0x1c49e002, 0xd3f742a1, + 0x1858bf00, 0xb5febd70, 0x460b4605, 0x20004616, 0x24009002, 0x01682700, 0x184049c1, 0xbf009000, + 0x9800a901, 0xf7ff301c, 0x9801ffc1, 0x2b000fc7, 0x2f00d001, 0x2b00d103, 0x2f00d103, 0x2001d101, + 0x2000e000, 0x2c004604, 0x9802d109, 0xd90042b0, 0x2001e007, 0xffadf7ff, 0x1c409802, 0x2c009002, + 0xbf00d0de, 0x21014620, 0xbdfe4048, 0x4604b5f8, 0x2600460d, 0x01602300, 0x184749a9, 0x4669bf00, + 0xf7ff4638, 0x9800ff93, 0x2b000fc3, 0x42aed106, 0xe005d900, 0xf7ff2001, 0x1c76ff8c, 0xd0ee2b00, + 0x4618bf00, 0x40482101, 0xb5f0bdf8, 0x460d4607, 0x26004613, 0xbf002400, 0x46384619, 0xff76f7ff, + 0x0f006818, 0x21050700, 0x42880749, 0x2001d101, 0x2000e000, 0x2c004604, 0x42aed106, 0xe005d900, + 0xf7ff2001, 0x1c76ff66, 0xd0e52c00, 0x4620bf00, 0x40482101, 0xb5f3bdf0, 0x4606b082, 0x48892700, + 0x90014478, 0x0fc007f0, 0x40482101, 0x25009000, 0xff57f7ff, 0xd0022800, 0x4d812400, 0x2401e002, + 0x35204d7f, 0x31f521ff, 0xf7ff4620, 0x4607ff9f, 0xd1362f00, 0x28009800, 0x4628d005, 0x9901300c, + 0xff32f7ff, 0x4631e004, 0x300c4628, 0xff2cf7ff, 0x30104620, 0x40822201, 0x48734611, 0xff24f7ff, + 0x46282101, 0xf7ff3008, 0x22ffff1f, 0x210032f5, 0xf7ff4620, 0x4607ff48, 0xd1122f00, 0x28009800, + 0x21ffd007, 0x9a0331f5, 0xf7ff9801, 0x4607ff8e, 0x21ffe007, 0x462831f5, 0x9a03300c, 0xff85f7ff, + 0x46384607, 0xbdf0b004, 0x4604b538, 0x447d4d5d, 0x495e3dae, 0xf7ff4628, 0x4621fef7, 0xf7ff1d28, + 0x4669fef3, 0xf7ff4859, 0xbd38ff96, 0x4604b538, 0x447d4d54, 0x49563dd2, 0xf7ff4628, 0x4621fee5, + 0xf7ff1d28, 0x4669fee1, 0xf7ff4851, 0xbd38ff84, 0x4604b538, 0x447d4d4b, 0x494d3df6, 0xf7ff4628, + 0x4621fed3, 0xf7ff1d28, 0x4669fecf, 0xf7ff4848, 0xbd38ff72, 0x4c47b518, 0x4947447c, 0xf7ff4620, + 0x4669fec3, 0xf7ff4844, 0xbd18ff66, 0x4605b5f8, 0x4617460e, 0x447c4c3f, 0x49403c1e, 0xf7ff4620, + 0x21fffeb3, 0x1d203107, 0xfeaef7ff, 0x46204629, 0xf7ff3008, 0x4631fea9, 0x300c4620, 0xfea4f7ff, + 0x48364669, 0xff47f7ff, 0xb570bdf8, 0xb081b0ff, 0x26004605, 0xe0032400, 0x46692000, 0x1c645508, + 0x02402001, 0xdbf74284, 0x46694602, 0xf7ff4628, 0x4606ffcd, 0xb07f4630, 0xbd70b001, 0x4606b570, + 0x2500460c, 0x4630e00a, 0xffdff7ff, 0x2d004605, 0xe005d000, 0x36ff36ff, 0x1e643602, 0xd1f22c00, + 0x4628bf00, 0xb510bd70, 0x21042400, 0xf7ff481c, 0x4604ffe5, 0xbd104620, 0x4605b5f8, 0x4617460e, + 0x447c4c14, 0x49173cca, 0xf7ff4620, 0x21fffe5d, 0x1d203107, 0xfe58f7ff, 0x46204629, 0xf7ff3008, + 0x4631fe53, 0x300c4620, 0xfe4ef7ff, 0x480d4669, 0xfef1f7ff, 0x0000bdf8, 0x00000d05, 0x40200000, + 0x40220000, 0x00000244, 0x40221008, 0x1c000100, 0x14000100, 0x0000012c, 0x0a000100, 0x05000100, + 0x16000800, 0x06000100, 0x00000000 +}; + +// SFLASH: NAR algo +static const uint32_t CY8C6xxA_SFLASH_NAR_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x20004603, 0x46014770, 0x47702000, 0xf000b510, 0xbd10f9aa, 0x4604b510, 0xf0004620, 0xbd10f976, + 0x4606b570, 0x4615460c, 0x46294622, 0xf0004630, 0xbd70f94d, 0x4604b570, 0x4616460d, 0x46294632, + 0xf0004620, 0xbd70f81f, 0x47706001, 0x600a6802, 0x21004770, 0x1c49e000, 0x43424ad7, 0xd8fa428a, + 0xb5084770, 0x48d54669, 0xfff0f7ff, 0x0209210f, 0x40089800, 0xd1012800, 0xe0002001, 0x46032000, + 0xbd084618, 0x4603b570, 0x461d460c, 0xe0052100, 0x5c6e5c50, 0xd00042b0, 0x1c49e002, 0xd3f742a1, + 0x1858bf00, 0xb5febd70, 0x460b4605, 0x20004616, 0x24009002, 0x01682700, 0x184049c1, 0xbf009000, + 0x9800a901, 0xf7ff301c, 0x9801ffc1, 0x2b000fc7, 0x2f00d001, 0x2b00d103, 0x2f00d103, 0x2001d101, + 0x2000e000, 0x2c004604, 0x9802d109, 0xd90042b0, 0x2001e007, 0xffadf7ff, 0x1c409802, 0x2c009002, + 0xbf00d0de, 0x21014620, 0xbdfe4048, 0x4604b5f8, 0x2600460d, 0x01602300, 0x184749a9, 0x4669bf00, + 0xf7ff4638, 0x9800ff93, 0x2b000fc3, 0x42aed106, 0xe005d900, 0xf7ff2001, 0x1c76ff8c, 0xd0ee2b00, + 0x4618bf00, 0x40482101, 0xb5f0bdf8, 0x460d4607, 0x26004613, 0xbf002400, 0x46384619, 0xff76f7ff, + 0x0f006818, 0x21050700, 0x42880749, 0x2001d101, 0x2000e000, 0x2c004604, 0x42aed106, 0xe005d900, + 0xf7ff2001, 0x1c76ff66, 0xd0e52c00, 0x4620bf00, 0x40482101, 0xb5f3bdf0, 0x4606b082, 0x48892700, + 0x90014478, 0x0fc007f0, 0x40482101, 0x25009000, 0xff57f7ff, 0xd0022800, 0x4d812400, 0x2401e002, + 0x35204d7f, 0x31f521ff, 0xf7ff4620, 0x4607ff9f, 0xd1362f00, 0x28009800, 0x4628d005, 0x9901300c, + 0xff32f7ff, 0x4631e004, 0x300c4628, 0xff2cf7ff, 0x30104620, 0x40822201, 0x48734611, 0xff24f7ff, + 0x46282101, 0xf7ff3008, 0x22ffff1f, 0x210032f5, 0xf7ff4620, 0x4607ff48, 0xd1122f00, 0x28009800, + 0x21ffd007, 0x9a0331f5, 0xf7ff9801, 0x4607ff8e, 0x21ffe007, 0x462831f5, 0x9a03300c, 0xff85f7ff, + 0x46384607, 0xbdf0b004, 0x4604b538, 0x447d4d5d, 0x495e3dae, 0xf7ff4628, 0x4621fef7, 0xf7ff1d28, + 0x4669fef3, 0xf7ff4859, 0xbd38ff96, 0x4604b538, 0x447d4d54, 0x49563dd2, 0xf7ff4628, 0x4621fee5, + 0xf7ff1d28, 0x4669fee1, 0xf7ff4851, 0xbd38ff84, 0x4604b538, 0x447d4d4b, 0x494d3df6, 0xf7ff4628, + 0x4621fed3, 0xf7ff1d28, 0x4669fecf, 0xf7ff4848, 0xbd38ff72, 0x4c47b518, 0x4947447c, 0xf7ff4620, + 0x4669fec3, 0xf7ff4844, 0xbd18ff66, 0x4605b5f8, 0x4617460e, 0x447c4c3f, 0x49403c1e, 0xf7ff4620, + 0x21fffeb3, 0x1d203107, 0xfeaef7ff, 0x46204629, 0xf7ff3008, 0x4631fea9, 0x300c4620, 0xfea4f7ff, + 0x48364669, 0xff47f7ff, 0xb570bdf8, 0xb081b0ff, 0x26004605, 0xe0032400, 0x46692000, 0x1c645508, + 0x02402001, 0xdbf74284, 0x46694602, 0xf7ff4628, 0x4606ffcd, 0xb07f4630, 0xbd70b001, 0x4606b570, + 0x2500460c, 0x4630e00a, 0xffdff7ff, 0x2d004605, 0xe005d000, 0x36ff36ff, 0x1e643602, 0xd1f22c00, + 0x4628bf00, 0xb510bd70, 0x21012400, 0xf7ff481c, 0x4604ffe5, 0xbd104620, 0x4605b5f8, 0x4617460e, + 0x447c4c14, 0x49173cca, 0xf7ff4620, 0x21fffe5d, 0x1d203107, 0xfe58f7ff, 0x46204629, 0xf7ff3008, + 0x4631fe53, 0x300c4620, 0xfe4ef7ff, 0x480d4669, 0xfef1f7ff, 0x0000bdf8, 0x00000d05, 0x40200000, + 0x40220000, 0x00000244, 0x40221008, 0x1c000100, 0x14000100, 0x0000012c, 0x0a000100, 0x05000100, + 0x16001a00, 0x06000100, 0x00000000 +}; + +// SFLASH: Public Key algo +static const uint32_t CY8C6xxA_SFLASH_PKEY_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x20004603, 0x46014770, 0x47702000, 0xf000b510, 0xbd10f9aa, 0x4604b510, 0xf0004620, 0xbd10f976, + 0x4606b570, 0x4615460c, 0x46294622, 0xf0004630, 0xbd70f94d, 0x4604b570, 0x4616460d, 0x46294632, + 0xf0004620, 0xbd70f81f, 0x47706001, 0x600a6802, 0x21004770, 0x1c49e000, 0x43424ad7, 0xd8fa428a, + 0xb5084770, 0x48d54669, 0xfff0f7ff, 0x0209210f, 0x40089800, 0xd1012800, 0xe0002001, 0x46032000, + 0xbd084618, 0x4603b570, 0x461d460c, 0xe0052100, 0x5c6e5c50, 0xd00042b0, 0x1c49e002, 0xd3f742a1, + 0x1858bf00, 0xb5febd70, 0x460b4605, 0x20004616, 0x24009002, 0x01682700, 0x184049c1, 0xbf009000, + 0x9800a901, 0xf7ff301c, 0x9801ffc1, 0x2b000fc7, 0x2f00d001, 0x2b00d103, 0x2f00d103, 0x2001d101, + 0x2000e000, 0x2c004604, 0x9802d109, 0xd90042b0, 0x2001e007, 0xffadf7ff, 0x1c409802, 0x2c009002, + 0xbf00d0de, 0x21014620, 0xbdfe4048, 0x4604b5f8, 0x2600460d, 0x01602300, 0x184749a9, 0x4669bf00, + 0xf7ff4638, 0x9800ff93, 0x2b000fc3, 0x42aed106, 0xe005d900, 0xf7ff2001, 0x1c76ff8c, 0xd0ee2b00, + 0x4618bf00, 0x40482101, 0xb5f0bdf8, 0x460d4607, 0x26004613, 0xbf002400, 0x46384619, 0xff76f7ff, + 0x0f006818, 0x21050700, 0x42880749, 0x2001d101, 0x2000e000, 0x2c004604, 0x42aed106, 0xe005d900, + 0xf7ff2001, 0x1c76ff66, 0xd0e52c00, 0x4620bf00, 0x40482101, 0xb5f3bdf0, 0x4606b082, 0x48892700, + 0x90014478, 0x0fc007f0, 0x40482101, 0x25009000, 0xff57f7ff, 0xd0022800, 0x4d812400, 0x2401e002, + 0x35204d7f, 0x31f521ff, 0xf7ff4620, 0x4607ff9f, 0xd1362f00, 0x28009800, 0x4628d005, 0x9901300c, + 0xff32f7ff, 0x4631e004, 0x300c4628, 0xff2cf7ff, 0x30104620, 0x40822201, 0x48734611, 0xff24f7ff, + 0x46282101, 0xf7ff3008, 0x22ffff1f, 0x210032f5, 0xf7ff4620, 0x4607ff48, 0xd1122f00, 0x28009800, + 0x21ffd007, 0x9a0331f5, 0xf7ff9801, 0x4607ff8e, 0x21ffe007, 0x462831f5, 0x9a03300c, 0xff85f7ff, + 0x46384607, 0xbdf0b004, 0x4604b538, 0x447d4d5d, 0x495e3dae, 0xf7ff4628, 0x4621fef7, 0xf7ff1d28, + 0x4669fef3, 0xf7ff4859, 0xbd38ff96, 0x4604b538, 0x447d4d54, 0x49563dd2, 0xf7ff4628, 0x4621fee5, + 0xf7ff1d28, 0x4669fee1, 0xf7ff4851, 0xbd38ff84, 0x4604b538, 0x447d4d4b, 0x494d3df6, 0xf7ff4628, + 0x4621fed3, 0xf7ff1d28, 0x4669fecf, 0xf7ff4848, 0xbd38ff72, 0x4c47b518, 0x4947447c, 0xf7ff4620, + 0x4669fec3, 0xf7ff4844, 0xbd18ff66, 0x4605b5f8, 0x4617460e, 0x447c4c3f, 0x49403c1e, 0xf7ff4620, + 0x21fffeb3, 0x1d203107, 0xfeaef7ff, 0x46204629, 0xf7ff3008, 0x4631fea9, 0x300c4620, 0xfea4f7ff, + 0x48364669, 0xff47f7ff, 0xb570bdf8, 0xb081b0ff, 0x26004605, 0xe0032400, 0x46692000, 0x1c645508, + 0x02402001, 0xdbf74284, 0x46694602, 0xf7ff4628, 0x4606ffcd, 0xb07f4630, 0xbd70b001, 0x4606b570, + 0x2500460c, 0x4630e00a, 0xffdff7ff, 0x2d004605, 0xe005d000, 0x36ff36ff, 0x1e643602, 0xd1f22c00, + 0x4628bf00, 0xb510bd70, 0x21062400, 0xf7ff481c, 0x4604ffe5, 0xbd104620, 0x4605b5f8, 0x4617460e, + 0x447c4c14, 0x49173cca, 0xf7ff4620, 0x21fffe5d, 0x1d203107, 0xfe58f7ff, 0x46204629, 0xf7ff3008, + 0x4631fe53, 0x300c4620, 0xfe4ef7ff, 0x480d4669, 0xfef1f7ff, 0x0000bdf8, 0x00000d05, 0x40200000, + 0x40220000, 0x00000244, 0x40221008, 0x1c000100, 0x14000100, 0x0000012c, 0x0a000100, 0x05000100, + 0x16005a00, 0x06000100, 0x00000000 +}; + +// SFLASH: TOC2 algo +static const uint32_t CY8C6xxA_SFLASH_TOC2_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x20004603, 0x46014770, 0x47702000, 0xf000b510, 0xbd10f9aa, 0x4604b510, 0xf0004620, 0xbd10f976, + 0x4606b570, 0x4615460c, 0x46294622, 0xf0004630, 0xbd70f94d, 0x4604b570, 0x4616460d, 0x46294632, + 0xf0004620, 0xbd70f81f, 0x47706001, 0x600a6802, 0x21004770, 0x1c49e000, 0x43424ad7, 0xd8fa428a, + 0xb5084770, 0x48d54669, 0xfff0f7ff, 0x0209210f, 0x40089800, 0xd1012800, 0xe0002001, 0x46032000, + 0xbd084618, 0x4603b570, 0x461d460c, 0xe0052100, 0x5c6e5c50, 0xd00042b0, 0x1c49e002, 0xd3f742a1, + 0x1858bf00, 0xb5febd70, 0x460b4605, 0x20004616, 0x24009002, 0x01682700, 0x184049c1, 0xbf009000, + 0x9800a901, 0xf7ff301c, 0x9801ffc1, 0x2b000fc7, 0x2f00d001, 0x2b00d103, 0x2f00d103, 0x2001d101, + 0x2000e000, 0x2c004604, 0x9802d109, 0xd90042b0, 0x2001e007, 0xffadf7ff, 0x1c409802, 0x2c009002, + 0xbf00d0de, 0x21014620, 0xbdfe4048, 0x4604b5f8, 0x2600460d, 0x01602300, 0x184749a9, 0x4669bf00, + 0xf7ff4638, 0x9800ff93, 0x2b000fc3, 0x42aed106, 0xe005d900, 0xf7ff2001, 0x1c76ff8c, 0xd0ee2b00, + 0x4618bf00, 0x40482101, 0xb5f0bdf8, 0x460d4607, 0x26004613, 0xbf002400, 0x46384619, 0xff76f7ff, + 0x0f006818, 0x21050700, 0x42880749, 0x2001d101, 0x2000e000, 0x2c004604, 0x42aed106, 0xe005d900, + 0xf7ff2001, 0x1c76ff66, 0xd0e52c00, 0x4620bf00, 0x40482101, 0xb5f3bdf0, 0x4606b082, 0x48892700, + 0x90014478, 0x0fc007f0, 0x40482101, 0x25009000, 0xff57f7ff, 0xd0022800, 0x4d812400, 0x2401e002, + 0x35204d7f, 0x31f521ff, 0xf7ff4620, 0x4607ff9f, 0xd1362f00, 0x28009800, 0x4628d005, 0x9901300c, + 0xff32f7ff, 0x4631e004, 0x300c4628, 0xff2cf7ff, 0x30104620, 0x40822201, 0x48734611, 0xff24f7ff, + 0x46282101, 0xf7ff3008, 0x22ffff1f, 0x210032f5, 0xf7ff4620, 0x4607ff48, 0xd1122f00, 0x28009800, + 0x21ffd007, 0x9a0331f5, 0xf7ff9801, 0x4607ff8e, 0x21ffe007, 0x462831f5, 0x9a03300c, 0xff85f7ff, + 0x46384607, 0xbdf0b004, 0x4604b538, 0x447d4d5d, 0x495e3dae, 0xf7ff4628, 0x4621fef7, 0xf7ff1d28, + 0x4669fef3, 0xf7ff4859, 0xbd38ff96, 0x4604b538, 0x447d4d54, 0x49563dd2, 0xf7ff4628, 0x4621fee5, + 0xf7ff1d28, 0x4669fee1, 0xf7ff4851, 0xbd38ff84, 0x4604b538, 0x447d4d4b, 0x494d3df6, 0xf7ff4628, + 0x4621fed3, 0xf7ff1d28, 0x4669fecf, 0xf7ff4848, 0xbd38ff72, 0x4c47b518, 0x4947447c, 0xf7ff4620, + 0x4669fec3, 0xf7ff4844, 0xbd18ff66, 0x4605b5f8, 0x4617460e, 0x447c4c3f, 0x49403c1e, 0xf7ff4620, + 0x21fffeb3, 0x1d203107, 0xfeaef7ff, 0x46204629, 0xf7ff3008, 0x4631fea9, 0x300c4620, 0xfea4f7ff, + 0x48364669, 0xff47f7ff, 0xb570bdf8, 0xb081b0ff, 0x26004605, 0xe0032400, 0x46692000, 0x1c645508, + 0x02402001, 0xdbf74284, 0x46694602, 0xf7ff4628, 0x4606ffcd, 0xb07f4630, 0xbd70b001, 0x4606b570, + 0x2500460c, 0x4630e00a, 0xffdff7ff, 0x2d004605, 0xe005d000, 0x36ff36ff, 0x1e643602, 0xd1f22c00, + 0x4628bf00, 0xb510bd70, 0x21022400, 0xf7ff481c, 0x4604ffe5, 0xbd104620, 0x4605b5f8, 0x4617460e, + 0x447c4c14, 0x49173cca, 0xf7ff4620, 0x21fffe5d, 0x1d203107, 0xfe58f7ff, 0x46204629, 0xf7ff3008, + 0x4631fe53, 0x300c4620, 0xfe4ef7ff, 0x480d4669, 0xfef1f7ff, 0x0000bdf8, 0x00000d05, 0x40200000, + 0x40220000, 0x00000244, 0x40221008, 0x1c000100, 0x14000100, 0x0000012c, 0x0a000100, 0x05000100, + 0x16007c00, 0x06000100, 0x00000000 +}; + +// SMIF algo +static const uint32_t CY8C6xxA_SMIF_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x08801c80, 0x1c40d003, 0xd1fc1e80, 0x4770bf00, 0x4605b570, 0x4616460c, 0xcc0fe002, 0x3e10c50f, + 0xd2fa2e10, 0xd3022e08, 0xc503cc03, 0x2e043e08, 0xcc01d307, 0x1f36c501, 0x7821e003, 0x1c647029, + 0x1e761c6d, 0xbd70d2f9, 0x4604b510, 0xf0002000, 0xf000f892, 0x4620f847, 0xf989f000, 0xbd102000, + 0xf000b510, 0x2000f992, 0xb510bd10, 0xf93bf000, 0xb510bd10, 0x04092101, 0xf939f000, 0xb510bd10, + 0xf935f000, 0xb510bd10, 0x2100460b, 0xf93ff000, 0xb508bd10, 0xf000466b, 0x9800f94a, 0xb508bd08, + 0xf000466a, 0x9800f97b, 0x0000bd08, 0xb5104a7d, 0x09d21882, 0x23004c7c, 0x19120112, 0x6004680c, + 0x644468cc, 0x6484690c, 0x64c4694c, 0x6404688c, 0x6184684c, 0x6504698c, 0x601069c8, 0x60506a08, + 0xbd104618, 0x4871b500, 0x6881b089, 0x01090909, 0x4a6e6081, 0x3a402100, 0x68026091, 0x430a0601, + 0x68426002, 0x6042430a, 0x430a6882, 0x49686082, 0x44792224, 0xf7ff4668, 0x4669ff7b, 0xf7ff4865, + 0x4963ffc5, 0x44792224, 0x46683110, 0xff70f7ff, 0x48614669, 0xffbaf7ff, 0x2224495d, 0x311e4479, + 0xf7ff4668, 0x485cff65, 0x30804669, 0xffaef7ff, 0x22244957, 0x312a4479, 0xf7ff4668, 0x4669ff59, + 0xf7ff4856, 0xb009ffa3, 0xb510bd00, 0x18400081, 0xff46f7ff, 0xb5f0bd10, 0x4b504a51, 0x4d4e4c4d, + 0x2800444a, 0x4849d021, 0x60816811, 0x60016851, 0x60416891, 0x608168d1, 0x31104611, 0xf7ff4618, + 0x4947ff85, 0x44494620, 0xf7ff3134, 0x4944ff7f, 0x44494628, 0xf7ff3158, 0x4941ff79, 0x4449483e, + 0x3080317c, 0xff72f7ff, 0x4837bdf0, 0x3010681e, 0x4449493b, 0x600e3110, 0x31404938, 0x4f38684e, + 0x3710444f, 0x688e60fe, 0x68ce613e, 0x680e617e, 0x699e60be, 0x690e607e, 0x680661be, 0x684061fe, + 0x6230463e, 0x46386826, 0x60063024, 0x36404e29, 0x60c76877, 0x610768b7, 0x614768f7, 0x60876837, + 0x604469a4, 0x61846934, 0x34804c1f, 0x61c46824, 0x34804c1d, 0x4e1c6864, 0x682c6204, 0x302436b0, + 0x4c1d6004, 0x68673440, 0x68a760c7, 0x68e76107, 0x68276147, 0x69ad6087, 0x69246045, 0x68346184, + 0x687461c4, 0x4c106204, 0x34c0681d, 0x60053024, 0x60c5684d, 0x6105688d, 0x614568cd, 0x6085680d, + 0x6043699b, 0x61816909, 0x61c16821, 0x62016861, 0x68814806, 0x68016011, 0x68416051, 0x68806091, + 0xbdf060d0, 0xbfcf0000, 0x40300000, 0x40260380, 0x00001b46, 0x40310400, 0x40310580, 0x40310080, + 0x00000004, 0x06c92103, 0xd2014288, 0x47702000, 0x06c9211d, 0x21011840, 0x428806c9, 0x2001d201, + 0x20024770, 0xb5104770, 0xfab1f000, 0xb510bd10, 0x4603460a, 0xffe6f7ff, 0xd0012800, 0xd0012801, + 0xbd102001, 0x46184611, 0xf9a3f000, 0xb570bd10, 0x4605460c, 0xffd6f7ff, 0xd0012800, 0xd0012801, + 0xbd702001, 0x46284621, 0xfac4f000, 0xb570bd70, 0x4605460c, 0xffc6f7ff, 0xd0012800, 0xd0012801, + 0xbd702001, 0x46284621, 0xfbb9f000, 0xb510bd70, 0x4604460b, 0xffb6f7ff, 0xd0012800, 0xd0012801, + 0xbd102001, 0x46204619, 0xfbc8f000, 0xb510bd10, 0xf7ff4602, 0x2800ffa7, 0x2801d001, 0x2001d001, + 0x4610bd10, 0xfbd3f000, 0xb510bd10, 0xfbe2f000, 0x20014604, 0xfeeff7ff, 0xbd104620, 0x4614b570, + 0x4605460e, 0xf7ff2200, 0x2800ff8d, 0x2801d009, 0x2201d001, 0x4628e00f, 0xfbb9f000, 0x28014602, + 0x2000d009, 0x60204603, 0x5ce9e003, 0x1c5b1840, 0x42b36020, 0x4610d3f9, 0x0000bd70, 0xb51048fe, + 0x444849fd, 0x44496840, 0x3110220f, 0x188401d2, 0x07d36ce2, 0xf000d003, 0x2001fc1d, 0x0793e004, + 0xf000d505, 0x2002fbb4, 0x6c206420, 0x0750bd10, 0x2005d503, 0x20046188, 0x0710e7f6, 0x2006d503, + 0x20086188, 0x06d0e7f0, 0x2007d503, 0x20106188, 0x0690e7ea, 0x2008d5ea, 0x20206188, 0x4ae6e7e4, + 0x7811444a, 0xd0014381, 0x47702000, 0x70102000, 0x680148e2, 0x68092000, 0xd0052900, 0xd0031c4b, + 0x071b2301, 0xd2014299, 0x47702001, 0x210160d1, 0x47707011, 0x4604b5f0, 0x46942500, 0x4628460e, + 0xffddf7ff, 0xd1202800, 0x23004ad3, 0x68d0444a, 0xb2878800, 0x68d0e017, 0x68400099, 0x28005840, + 0x6030d010, 0x07897901, 0x68c1d50c, 0xd80942a1, 0x18086900, 0xd90542a0, 0x25016830, 0x46606981, + 0xe0026001, 0x42bb1c5b, 0x4628dbe5, 0x40482101, 0xb5ffbdf0, 0x4ec0b081, 0x2500990a, 0x2900444e, + 0x68b0d105, 0xd0022800, 0x4290aa01, 0x2000d058, 0x460860b0, 0xffa3f7ff, 0x28014604, 0x2c02d00e, + 0x4bb5d04e, 0x444b227d, 0x00d23310, 0x6870a901, 0xfbf6f000, 0xd0070005, 0xd0002c02, 0x2d002401, + 0x2c02d00f, 0xe03cd03c, 0xd0f72c01, 0xd0372c02, 0x68f14aa9, 0x3210444a, 0xf0016870, 0x4605f975, + 0x2c01e7ed, 0x2c02d02d, 0x49a3d02a, 0x44496870, 0xf0003110, 0x68f0fd49, 0x88002400, 0xe01bb287, + 0x00a568f0, 0x59416840, 0xd0142900, 0x6bc06988, 0xd0102800, 0x68704a98, 0x3210444a, 0xf9e2f001, + 0xd1082800, 0x4a9468f0, 0x444a6840, 0x32105941, 0xf0016870, 0x1c64fa53, 0xdbe142bc, 0x60b0a801, + 0x46202400, 0xbdf0b005, 0x2400b5f0, 0x460d4607, 0x46204626, 0xff43f7ff, 0xd11b2800, 0x49862204, + 0x44490083, 0x684968c9, 0x290058c9, 0x6039d00f, 0x079b790b, 0x6949d50b, 0xd10542a9, 0xd0032c00, + 0x26016838, 0xe0056038, 0xd10042a9, 0x1c402401, 0xdbe44290, 0x21014630, 0xbdf04048, 0x2400b5f3, + 0xb0814d75, 0x46264607, 0x9400444d, 0x46394a72, 0x3210444a, 0xf0016868, 0x6979f9d8, 0xd00b2900, + 0xd10b2800, 0xf7ff4668, 0x4a6bffbf, 0x444a9900, 0x68683210, 0xf9c9f001, 0xd0032800, 0x42849802, + 0x2601dd02, 0xbdfe4630, 0xf7ff2064, 0x1c64fd8e, 0xb5f0e7dc, 0x2700b089, 0x4604460d, 0x97079706, + 0xa906aa08, 0xf7ff9708, 0x2800ff05, 0x9806d111, 0x29006941, 0x460fd005, 0xf7ffa807, 0x2800ff95, + 0x2000d107, 0x48549000, 0x30384448, 0xf7ffc80f, 0x9908ff20, 0x698e9a06, 0x1a6468d1, 0xd1052800, + 0x4610494f, 0xffaaf7ff, 0xd07d2800, 0xbdf0b009, 0x99062000, 0x69889005, 0x28016800, 0x2802d006, + 0x2803d007, 0x2804d009, 0xe014d00d, 0x75044668, 0x466ae011, 0x0a207554, 0x466ae00c, 0x0a207594, + 0x0c207550, 0x466ae006, 0x0a2075d4, 0x0c207590, 0x0e207550, 0x4a387510, 0x444a4837, 0x32104448, + 0xf0016840, 0x2800f91f, 0x2001d001, 0x2f00e7ce, 0x4a31d00a, 0x444a4830, 0x32104448, 0x68409907, + 0xf910f001, 0xd1f02800, 0xd20042b5, 0x4b2a462e, 0x444b4829, 0x33104448, 0x9906aa05, 0xf0016840, + 0x2800f9ee, 0x2f00d1e1, 0x4b23d00b, 0x444b4822, 0x33104448, 0x9907aa05, 0xf0016840, 0x2800f9e0, + 0x481dd1d3, 0x68404448, 0x68404684, 0xd1f80fc0, 0x4b199906, 0x22007808, 0x3310444b, 0x92039201, + 0x92009304, 0x69889002, 0x6a804613, 0x46607801, 0xfb27f000, 0x21014810, 0x68404448, 0x650104c9, + 0x6c413080, 0xe0002900, 0xd0fae04d, 0xb2c06d00, 0x20649000, 0xfcd9f7ff, 0x69809806, 0x98006b81, + 0xd1ce4201, 0xd0352f00, 0x44484803, 0x46846840, 0x0fc06840, 0xe005d1f8, 0x000000a4, 0x16007c0c, + 0x0000c350, 0x4bf79907, 0x22007808, 0x9201444b, 0x93049203, 0x90029200, 0x46136988, 0x78016a80, + 0xf0004660, 0x48effaee, 0x04c92101, 0x38104448, 0x65016840, 0x6c413080, 0xd0fc2900, 0xb2c06d00, + 0x20649000, 0xfca1f7ff, 0x69809807, 0x98006b81, 0xd1c94201, 0x980649e4, 0xfee0f7ff, 0xd0002800, + 0x1bade734, 0x2d0019a4, 0xe731d000, 0xb5f8e72e, 0x20004cdc, 0x3428444c, 0xcc0f9000, 0xfe39f7ff, + 0xd0262801, 0x39484621, 0x260068c9, 0xb2898809, 0xe01b9100, 0x00b249d3, 0x39104449, 0x684968c9, + 0x2d00588d, 0x7929d011, 0xd50e0789, 0x69af2400, 0x68e8e008, 0x190069b9, 0xfedbf7ff, 0xd0082801, + 0x190c69b9, 0x42a16929, 0x1c76d8f3, 0x428e9900, 0xbdf8dbe0, 0xb08bb5ff, 0x980c4604, 0x1823461e, + 0x90092000, 0x90079006, 0xaa089008, 0x4618a909, 0xfdd0f7ff, 0xd1080005, 0x69419809, 0xd0062900, + 0x9106a807, 0xfe60f7ff, 0x2d014605, 0x2001d008, 0x48b49000, 0x30284448, 0xf7ffc80f, 0x4605fdea, + 0x6a479808, 0x68c19809, 0x990c1a62, 0x21001854, 0x2d01910a, 0x49acd005, 0xfe70f7ff, 0x28014605, + 0xe0c9d178, 0x99092000, 0x69889005, 0x28016800, 0x2802d006, 0x2803d007, 0x2804d009, 0xe014d00d, + 0x75044668, 0x466ae011, 0x0a207554, 0x466ae00c, 0x0a207594, 0x0c207550, 0x466ae006, 0x0a2075d4, + 0x0c207590, 0x0e207550, 0x4a967510, 0x4610444a, 0x68403810, 0xffe6f000, 0xd1492800, 0x28009806, + 0x4a90d009, 0x444a9907, 0x38104610, 0xf0006840, 0x2800ffd9, 0x488bd13c, 0x38104448, 0x46846840, + 0x68404660, 0xd1fb0fc0, 0xd20042be, 0x98094637, 0x78014b84, 0x90009808, 0x444b6a00, 0x79404686, + 0x22009001, 0xc00ea802, 0xab059800, 0x90006800, 0x79024670, 0x46607801, 0xfa03f000, 0xd1172800, + 0x44484878, 0x68403810, 0x31804601, 0x0712684a, 0xd1fb0f12, 0x21004a73, 0x444a9100, 0x92019908, + 0x7d136a0a, 0x21006a4a, 0xfa29f000, 0xd0022800, 0xe0512501, 0x496be04d, 0x44499a08, 0x68493910, + 0x46942000, 0xe00a3180, 0x18139a0a, 0x5cd29a0d, 0x684a610a, 0x0f120712, 0xd8fa2a04, 0x46621c40, + 0x42826a52, 0x485fd8f0, 0x38104448, 0x46846840, 0x0fc06840, 0x9809d1f7, 0x78034a5a, 0x444a2100, + 0x91039101, 0x92049302, 0x69809100, 0x6a802300, 0x7801461a, 0xf0004660, 0x4852f9b4, 0x04c92101, + 0x38104448, 0x65016840, 0x6c413080, 0xd0fc2900, 0xb2c06d00, 0x20649000, 0xfb67f7ff, 0x69809809, + 0x98006b81, 0xd1ce4201, 0x1bf6980a, 0x19e419c0, 0x2e00900a, 0xe735d000, 0xb00f4628, 0xb5ffbdf0, + 0xb0814604, 0x90002000, 0x4615483e, 0x460e4448, 0xc80f3038, 0xfcfdf7ff, 0xd10e2800, 0x23004621, + 0x5ceae006, 0x42ba5ccf, 0x2001d001, 0x1c5be002, 0xd3f642b3, 0x990418ca, 0xe553600a, 0x4606b5f8, + 0x90002000, 0x4614482f, 0x460d4448, 0xc80f3038, 0xfcdff7ff, 0xd1052800, 0xe0052300, 0x42a15cf1, + 0x2001d001, 0x1c5bbdf8, 0xd3f742ab, 0xb50ebdf8, 0x91012100, 0xaa029102, 0xf7ffa901, 0x2800fc9b, + 0x2001d107, 0x481f9000, 0x30384448, 0xf7ffc80f, 0xbd0efcc0, 0xb510491b, 0x39104449, 0x2401688a, + 0xd0022a00, 0xf0006848, 0x4620f8ef, 0xb570bd10, 0x460d694c, 0x460368ca, 0x6c593380, 0x0f090709, + 0xd90042a1, 0x29004621, 0x2908d03f, 0x2901d015, 0x2902d01c, 0x2903d01d, 0x2904d01e, 0x2905d021, + 0x2906d022, 0x2907d025, 0x6d99d028, 0x6d996011, 0x21086051, 0x1a641852, 0x6d9ee7df, 0x6d9e6016, + 0xe7f76056, 0x000000b4, 0x0000c350, 0x70166d1e, 0x6d5ee7f0, 0xe7ed8016, 0x80166d5e, 0x70966d1e, + 0x6d9ee7e8, 0xe7e56016, 0x60166d9e, 0x71166d1e, 0x6d9ee7e0, 0x6d5e6016, 0xe7db8096, 0x60166d9e, + 0x80966d5e, 0x71966d1e, 0x60eae7d4, 0x2c00616c, 0x210fd10e, 0x184001c9, 0x22026c81, 0x64814391, + 0x61a82003, 0x28006a28, 0x6a29d002, 0x47882003, 0xbd70616c, 0x688db4f0, 0x4603680a, 0x685c3380, + 0x0f240724, 0x1b342608, 0xd90042ac, 0x2c00462c, 0x2c08d039, 0x2c01d018, 0x2c02d01a, 0x2c03d01a, + 0x2c04d01a, 0x2c05d01c, 0x2c06d01d, 0x2c07d01f, 0x6814d022, 0x6854619c, 0x2408619c, 0x1b2d1912, + 0x0724685c, 0xe7de0f24, 0x619f6817, 0xe0086857, 0xe0167817, 0xe00d8817, 0x615f8817, 0xe0107897, + 0x619f6817, 0x6817e7ea, 0x7917619f, 0x6817e009, 0x8897619f, 0xe7e1615f, 0x619f6817, 0x615f8897, + 0x611f7997, 0x60cae7da, 0x2d00614d, 0x220fd10f, 0x188001d2, 0x08526c82, 0x64820052, 0x61882001, + 0x280069c8, 0x69c9d003, 0x2001bcf0, 0xbcf04708, 0x60014770, 0x47702000, 0x60086800, 0x47702000, + 0x4cf7b510, 0xd01d2800, 0xd01b2900, 0xd0192b00, 0x220f625a, 0x188201d2, 0x089b6c93, 0x6493009b, + 0x7a0b780a, 0x079b07d2, 0x0c9b0fd2, 0x790b431a, 0x075b7b09, 0x07c90b5b, 0x09c9431a, 0x6002430a, + 0x24006800, 0xbd104620, 0x2103b510, 0x60010209, 0x46012400, 0x600c3180, 0x210f640c, 0x184101c9, + 0x2301648c, 0x02db4621, 0x181201ca, 0x601418d2, 0x1c496812, 0xd3f72904, 0x2900bd10, 0xd0046801, + 0x43112201, 0x68006001, 0x08494770, 0xe7f90049, 0x68094601, 0x07c92000, 0x2001d000, 0x29014770, + 0x2902d012, 0x2904d013, 0x2908d014, 0x2000d015, 0xd0082800, 0x23036801, 0x0792041b, 0x0b924399, + 0x60014311, 0x47706800, 0x02c92101, 0x2111e007, 0xe00401c9, 0x02092109, 0x2113e001, 0x184001c9, + 0xb5ffe7e6, 0x9f0eb083, 0x073f0792, 0x0d3f4605, 0x0b929b10, 0x9e0c2000, 0x6a5b433a, 0x4604430a, + 0x2e009300, 0x2100d009, 0x0c0907c9, 0x652a430a, 0x0789990d, 0x91010b89, 0x990fe019, 0x6c68e7f4, + 0x0f400740, 0xd20f2804, 0x9a011c61, 0xd20142b1, 0xe0002000, 0x07c0980f, 0x43020c00, 0x5d009806, + 0x43024338, 0xb2cc652a, 0xf0004668, 0x42b4fad3, 0x49a3d203, 0x42881e89, 0xb007d1e1, 0xb5f0bdf0, + 0x489f4605, 0x9c069e05, 0xd01e2a00, 0x1ec06c6f, 0x0f7f077f, 0xd2182f04, 0x23010798, 0x049b0b80, + 0x1e5318c0, 0x4318b29b, 0x29006528, 0x6021d00c, 0x60a26062, 0x200261e6, 0x200f61a0, 0x182801c0, + 0x22016c81, 0x64814311, 0xbdf02000, 0xb08cb570, 0x488b4604, 0x2a009e10, 0x6c65d028, 0x076d1ec0, + 0x2d040f6d, 0x0798d222, 0x0b802301, 0x18c0049b, 0xb29b1e53, 0x65204318, 0x29002000, 0x6a73d016, + 0x91019300, 0x21009203, 0x21029108, 0x4d7c9107, 0xe0061ead, 0x4620a901, 0xf9b4f000, 0xf0004668, + 0x9907fa79, 0xd1012902, 0xd1f342a8, 0xbd70b00c, 0x4605b5f0, 0x9e054872, 0x2a009c06, 0x6c6fd01f, + 0x077f1ec0, 0x2f040f7f, 0x0798d219, 0x0b802301, 0x18c004db, 0x039b1e53, 0x43180b9b, 0x29006528, + 0x60e1d00c, 0x61626122, 0x20046226, 0x200f61a0, 0x182801c0, 0x22026c81, 0x64814311, 0xbdf02000, + 0xb08cb570, 0x485e4604, 0x2a009e10, 0x6c65d0ce, 0x076d1ec0, 0x2d040f6d, 0x0798d2c8, 0x0b802301, + 0x18c004db, 0x039b1e53, 0x43180b9b, 0x20006520, 0xd0bb2900, 0x930a6a73, 0x92059103, 0x91082100, + 0x91062104, 0x1ead4d4e, 0x4669e006, 0xf0004620, 0xa80af9b8, 0xfa1ef000, 0x29049906, 0x42a8d1a6, + 0xe7a3d1f3, 0x48464602, 0x1ec06c53, 0x0f5b075b, 0xd2062b04, 0xb2881e49, 0x04892103, 0x65101840, + 0x47702000, 0x47706988, 0x600a2200, 0x608a604a, 0x610a60ca, 0x618a614a, 0x22016801, 0x431107d2, + 0x68006001, 0xb5ff4770, 0x4604b087, 0x4d349810, 0x00176a40, 0xd0489004, 0x07009808, 0x2500d145, + 0x34ff0918, 0x462e34ff, 0x90063402, 0x0130e03b, 0x90059908, 0x62201840, 0x08406820, 0x60200040, + 0x60202001, 0xa804e003, 0xf9d4f000, 0x68204605, 0xd00307c0, 0x1e804822, 0xd1f44285, 0x1e804820, + 0xd0224285, 0x22016e20, 0xf0004669, 0x6e60f9b9, 0xa9012201, 0xf9b4f000, 0x22016ea0, 0xf000a902, + 0x6ee0f9af, 0xa9032201, 0xf9aaf000, 0x99052000, 0x1809466b, 0x5c1b5c7a, 0x405a1c40, 0x2810547a, + 0x9806d3f5, 0x42b01c76, 0x4628d8c1, 0xbdf0b00b, 0x1dc22301, 0x32f907db, 0xd00c2901, 0x308130ff, + 0xd0042902, 0xd1052903, 0x43196811, 0x68016011, 0x60014319, 0x68104770, 0x60104318, 0x00004770, + 0x00b20004, 0x32f91dc2, 0xd00e2901, 0x308130ff, 0xd0052902, 0xd1f12903, 0x00496811, 0x60110849, + 0x00496801, 0x60010849, 0x6810e7e8, 0x08400040, 0xe7e36010, 0x1dc22301, 0x32f9079b, 0xd00c2901, + 0x308130ff, 0xd0042902, 0xd1d72903, 0x43196811, 0x68016011, 0x60014319, 0x6810e7d0, 0x60104318, + 0x2301e7cc, 0x079b1dc2, 0x290132f9, 0x30ffd00c, 0x29023081, 0x2903d004, 0x6811d1c0, 0x60114399, + 0x43996801, 0xe7b96001, 0x43986810, 0xe7b56010, 0x23011dc2, 0x290132f9, 0x30ffd00c, 0x29023081, + 0x2903d004, 0x6891d1aa, 0x60914319, 0x43196881, 0xe7a36081, 0x43186890, 0xe79f6090, 0x6842b530, + 0x78006881, 0x4c9c2300, 0xd0062801, 0xd0222802, 0xd0232804, 0xd1162808, 0x6988e01d, 0x2804b2c0, + 0x2000d00c, 0x0fcd6851, 0x46104305, 0xfde0f7ff, 0xd0012801, 0xd0032d00, 0xe0022001, 0xe7f12001, + 0x28002000, 0x4623d001, 0x6810e008, 0x08400040, 0x68106010, 0x4610e002, 0xfef6f7ff, 0xbd304618, + 0x6842b530, 0x78006881, 0x4c832300, 0xd0062801, 0xd0222802, 0xd0232804, 0xd1162808, 0x6988e01d, + 0x2804b2c0, 0x2000d00c, 0x0fcd6851, 0x46104305, 0xfdaef7ff, 0xd0012801, 0xd0032d00, 0xe0022001, + 0xe7f12001, 0x28002000, 0x4623d001, 0x6810e008, 0x08400040, 0x68106010, 0x4610e002, 0xfec4f7ff, + 0xbd304618, 0x688db4f0, 0x4603680a, 0x685c3380, 0x0f240724, 0x1b342608, 0xd90042ac, 0x2c00462c, + 0x2c08d039, 0x2c01d018, 0x2c02d01a, 0x2c03d01a, 0x2c04d01a, 0x2c05d01c, 0x2c06d01d, 0x2c07d01f, + 0x6814d022, 0x6854619c, 0x2408619c, 0x1b2d1912, 0x0724685c, 0xe7de0f24, 0x619f6817, 0xe0086857, + 0xe0167817, 0xe00d8817, 0x615f8817, 0xe0107897, 0x619f6817, 0x6817e7ea, 0x7917619f, 0x6817e009, + 0x8897619f, 0xe7e1615f, 0x619f6817, 0x615f8897, 0x611f7997, 0x60cae7da, 0x2d00614d, 0x220fd10f, + 0x188001d2, 0x08526c82, 0x64820052, 0x61882001, 0x280069c8, 0x69c9d003, 0x2001bcf0, 0xbcf04708, + 0xb5704770, 0x460d694c, 0x460368ca, 0x6c593380, 0x0f090709, 0xd90042a1, 0x29004621, 0x2908d03b, + 0x2901d015, 0x2902d018, 0x2903d019, 0x2904d01a, 0x2905d01d, 0x2906d01e, 0x2907d021, 0x6d99d024, + 0x6d996011, 0x21086051, 0x1a641852, 0x6d9ee7df, 0x6d9e6016, 0xe7f76056, 0x70166d1e, 0x6d5ee7f4, + 0xe7f18016, 0x80166d5e, 0x70966d1e, 0x6d9ee7ec, 0xe7e96016, 0x60166d9e, 0x71166d1e, 0x6d9ee7e4, + 0x6d5e6016, 0xe7df8096, 0x60166d9e, 0x80966d5e, 0x71966d1e, 0x60eae7d8, 0x2c00616c, 0x210fd10e, + 0x184001c9, 0x22026c81, 0x64814391, 0x61a82003, 0x28006a28, 0x6a29d002, 0x47882003, 0xbd70616c, + 0x70080a03, 0x2a00704b, 0x0c02d003, 0x0e00708a, 0xe67370c8, 0x4604b510, 0x20006821, 0xd0072900, + 0xf7fe2001, 0x6820feb2, 0x60201e40, 0x2000d001, 0x4802bd10, 0x0000bd10, 0x004200ff, 0x00b20002, + 0x698cb530, 0x68a368cd, 0x6a220a2d, 0x6085022d, 0x43ed690d, 0x0a2d1c6d, 0x60c5022d, 0x69497824, + 0x07a41e64, 0x29000fa4, 0x21ffd001, 0x430c3101, 0x681c6204, 0x1c6549fc, 0x791dd006, 0x07adb2e4, + 0x432c0bad, 0xe0001864, 0x64042400, 0x07a4795c, 0x64440ba4, 0x1c65689c, 0x7b1dd006, 0x07adb2e4, + 0x432c0bad, 0xe0001864, 0x64842400, 0x2c00691c, 0x1e64d003, 0x0ee406e4, 0x64c41864, 0x079b7d1b, + 0x65030b9b, 0x1c5c6813, 0x7914d006, 0x07a4b2db, 0x43230ba4, 0xe000185b, 0x66032300, 0x079b7953, + 0x66430b9b, 0x1c5c6893, 0x7b14d006, 0x07a4b2db, 0x43230ba4, 0xe000185b, 0x66832300, 0x2b006913, + 0x1e5bd004, 0x0edb06db, 0xe0001859, 0x66c12100, 0x07897d11, 0x67010b89, 0xb5ffbd30, 0x2600b0c7, + 0x460c9645, 0x9f506b4d, 0x99499a4a, 0xf7ff9847, 0x7969fc46, 0xaa029849, 0xc2c19101, 0x90002003, + 0x7829792a, 0x9847ab45, 0xfc5bf7ff, 0xd13f2800, 0x98476929, 0xfd46f7ff, 0xd1392800, 0x96009701, + 0x22ff7d2b, 0x9847a905, 0xfce2f7ff, 0xd12f2800, 0xe0086a7d, 0x2d002000, 0x2001d005, 0xfe05f7fe, + 0xd00d1e6d, 0x69b92000, 0xd0022903, 0x428849b7, 0x2800d1f0, 0x4669d11c, 0x29537d09, 0xe015d002, + 0xe7f048b2, 0x7d494669, 0xd10f2946, 0x7d894669, 0xd10b2944, 0x7dc94669, 0xd1072950, 0x7e094669, + 0xd3032906, 0x7e494669, 0xd0032901, 0x1cc048a7, 0xbdf0b04b, 0x780aa908, 0x4694ab05, 0x46961c92, + 0x68a15c9a, 0x0f920752, 0x2a01d004, 0x2a02d002, 0xe001d104, 0xe0002203, 0x60222204, 0x08924662, + 0x18d20092, 0x8c929200, 0x05d50553, 0x0f9b0717, 0x0f3f0eed, 0x2b002200, 0x2b01d006, 0x2b02d006, + 0x2b03d006, 0xe005d108, 0xe0052201, 0xe0032210, 0xe0012280, 0x00d2227d, 0x1c9b007b, 0x461f1c6d, + 0x436b4355, 0x9a006423, 0x005a6a93, 0x00da0f95, 0x92000ed2, 0x2d002200, 0x2d01d006, 0x2d02d006, + 0x2d03d007, 0xe007d10a, 0xe0072210, 0x320122ff, 0x227de004, 0xe0010152, 0x0252227d, 0x1c6d9d00, + 0x436f4355, 0x6467049a, 0x04da0fd7, 0x0ed2071d, 0x2f000f2d, 0x2340d017, 0x006d1c52, 0x1cad435a, + 0xaa054355, 0x64a54462, 0x79177955, 0x433d022d, 0x799379d7, 0x041b063f, 0x432f431f, 0x1c7fd405, + 0x606308fb, 0x2308e005, 0x4b67e7e6, 0x431f1eff, 0x46136067, 0x469c3320, 0x091f7a1b, 0x461d2301, + 0x626540bd, 0x40ab7f15, 0xab0561a3, 0x5d5b4675, 0x069f4d5f, 0x9f4ad512, 0xd00f2f01, 0xd00d2f03, + 0x600b7a53, 0x2302710e, 0x7a17714b, 0xd003097f, 0x608f275a, 0xe0137a17, 0xe7fb608d, 0xd515065f, + 0x2f019f4a, 0x2f03d012, 0x7ad3d010, 0x710e600b, 0x714b2302, 0x097f7a97, 0x275ad006, 0x7a97608f, + 0x0eff06ff, 0xe021610f, 0xe7f8608d, 0xd50d06df, 0x600b7bd3, 0x2301710e, 0x7b97714b, 0xd003097f, + 0x608f275a, 0xe7eb7b97, 0xe7fb608d, 0xd01107db, 0x600b7b53, 0x714e710e, 0x095b7b13, 0x235ad008, + 0x7b13608b, 0x0edb06db, 0x2301610b, 0xe008750b, 0xe7f6608d, 0x600b2303, 0x714e710e, 0x608d610e, + 0x68e3750e, 0x60192106, 0x270268e1, 0x6923710e, 0x60192104, 0x710e6921, 0x216069e3, 0x69e16019, + 0x7f51710e, 0x60116962, 0x22056961, 0x6961710e, 0x6a21714e, 0x6a21600f, 0x6a21710e, 0x6a21714e, + 0x6a21608d, 0x6a21610e, 0x2101750e, 0x6aa363a1, 0x6aa3601a, 0x6b23711e, 0x4663711e, 0x065b7e9b, + 0x00330f5e, 0xfa2cf000, 0x100b0506, 0x040b0b17, 0x63e5e6de, 0x600d6b21, 0x600d6ae1, 0x63e7e6d8, + 0x60116b22, 0xe00c2135, 0x63e32340, 0x60196b23, 0x600a6ae1, 0x2180e6cc, 0x6b2263e1, 0x6011213e, + 0x6ae2213f, 0xe6c36011, 0x4808b5f7, 0x1c80b084, 0x90012700, 0xd0642900, 0x90036808, 0x90026848, + 0x46062000, 0xe0539001, 0x80000000, 0x00b20002, 0xffffffff, 0x00b19802, 0x2c005844, 0x7821d047, + 0x29019804, 0x2902d022, 0x2904d023, 0x2908d024, 0x2500d025, 0xd0472d00, 0x21036828, 0x43880409, + 0x07897a21, 0x43080b89, 0x79206028, 0xd51a0740, 0x90009806, 0x78227a23, 0x980469a1, 0xfe2df7ff, + 0xd0102800, 0x40b02008, 0xe01f4307, 0x02c92101, 0x2111e007, 0xe00401c9, 0x02092109, 0x2113e001, + 0x184501c9, 0x7920e7d6, 0xd50f0780, 0x46284621, 0xfda6f7ff, 0x686021ff, 0x40083102, 0x07897a21, + 0x43080b89, 0x07c92101, 0x60281840, 0x1c766828, 0x42869803, 0x2f00d3ae, 0x2059d003, 0x43070440, + 0x98019701, 0xbdf0b007, 0x900148cc, 0xb510e7f3, 0x24012300, 0x02e4461a, 0x180901d9, 0x600a1909, + 0x60ca608a, 0x640a620a, 0x648a644a, 0x650a64ca, 0x664a660a, 0x66ca668a, 0x6809670a, 0x2b041c5b, + 0xbd10d3ea, 0x698bb530, 0xb085780d, 0x210068db, 0x91012401, 0x94039502, 0x91009204, 0x7819791a, + 0xf7ff2300, 0xb005fa3e, 0xb530bd30, 0x780d698b, 0x691bb085, 0x24012100, 0x95029101, 0x92049403, + 0x791a9100, 0x23007819, 0xfa2bf7ff, 0xb5f0e7eb, 0x4606b085, 0x20007809, 0x9c0a461f, 0x90014615, + 0x46039003, 0x91024602, 0x94049000, 0x46304639, 0xfa17f7ff, 0xd1062800, 0x22012300, 0x46304629, + 0xf7ff9400, 0xb005facd, 0xb51cbdf0, 0x466c2301, 0x698c7123, 0x6aa29200, 0xaa017813, 0xffd7f7ff, + 0xd1052800, 0x8f204669, 0x40087909, 0x71084669, 0x79004668, 0xd0002800, 0xbd1c2001, 0xb085b5ff, + 0x46179d0e, 0x460c461e, 0x9805462a, 0xff9af7ff, 0xd1112800, 0x6bc069a0, 0xd0002802, 0x78212001, + 0xac022201, 0x2300c426, 0x90009301, 0x2200463b, 0x98054631, 0xf9d5f7ff, 0xbdf0b009, 0xb084b5f7, + 0x90012000, 0x46149805, 0x6ae86985, 0x6b287807, 0x7800463b, 0x6aa89002, 0x92007806, 0x9905aa01, + 0xf7ff9804, 0x2800ff94, 0x6be8d109, 0x2802ad01, 0x2840d010, 0x2880d004, 0x4870d028, 0xe7411e40, + 0x79084669, 0x43082140, 0x71084669, 0x462a9400, 0xe02d9b02, 0x46339400, 0x9905462a, 0xf7ff9804, + 0x2800ff76, 0x9400d1eb, 0x1c6a463b, 0x98049905, 0xff6df7ff, 0xd1e22800, 0x79484669, 0x43082102, + 0x71484669, 0xaa019400, 0xe0119b02, 0x463b9400, 0x99051c6a, 0xf7ff9804, 0x2800ff5a, 0x4669d1cf, + 0x21807948, 0x46694308, 0x9b027148, 0x1c6a9400, 0x98049905, 0xff82f7ff, 0xb530e704, 0x780d698b, + 0x69dbb085, 0x24012100, 0x95029101, 0x92049403, 0x791a9100, 0x23007819, 0xf963f7ff, 0xb5f0e723, + 0xb0854c46, 0xd0102a00, 0x7809698d, 0x2701696c, 0x93047926, 0x96019703, 0x68299102, 0x46139100, + 0x46327821, 0xf94df7ff, 0x46204604, 0xb5ffe73b, 0x698db085, 0x9f0e4839, 0x6a2c9e10, 0xd0282a00, + 0x42bb6a6b, 0x6948d325, 0xd0232800, 0x7961b2c0, 0x93032300, 0x91019604, 0x68289002, 0x79209000, + 0x46024613, 0x98057821, 0xf92bf7ff, 0xd1102800, 0x29006921, 0x9805d004, 0xfa14f7ff, 0xd1082800, + 0x9000980f, 0x7d239601, 0x9908463a, 0xf7ff9805, 0xe741f956, 0xe7da7808, 0x698fb5ff, 0x481fb085, + 0x68bc9e10, 0xd0362a00, 0x28006948, 0xb2c5d034, 0x20007961, 0x95029604, 0x90039101, 0x90006838, + 0x46137920, 0x78214602, 0xf7ff9805, 0x2800f8fa, 0x6921d121, 0xd0042900, 0xf7ff9805, 0x2800f9e3, + 0x68a0d119, 0xd00d1c41, 0x91012100, 0x91009103, 0x95029604, 0x7d22b2c1, 0x98052300, 0xf8e1f7ff, + 0xd1082800, 0x9000980f, 0x7d239601, 0x99089a0e, 0xf7ff9805, 0xe6fff96d, 0xe7c9780d, 0x00b20004, + 0x4674b430, 0x78251e64, 0x42ab1c64, 0x461dd200, 0x005b5d63, 0xbc3018e3, 0x00004718, 0x00000003, + 0x00000000, 0x00000000, 0x00000068, 0x00000000, 0x00000000, 0x00000000, 0x00001212, 0x00000000, + 0x000000ff, 0x00000000, 0x00000000, 0x6eeee666, 0x00000000, 0x00000000, 0x00000000, 0x11111111, + 0x11111111, 0x0000001f, 0x00000000, 0x00000000, 0x0006eeee, 0x00000000, 0x00000000, 0x00000000, + 0x11111111, 0x00000011, 0x00000001, 0x00000000, 0x00000000, 0x0000000b, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000001, 0x00000001, 0x00000001, + 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, + 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, + 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, + 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, + 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000000, 0x40420000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000007, 0x00000001, 0x00000000, 0x00000001, 0x00000007, + 0x00000001, 0x00000000 +}; + +static const program_target_t CY8C6xxA_flash_prog = + // Main Flash + { + .init = 0x08000021, // Init + .uninit = 0x08000027, // UnInit + .erase_chip = 0x0800002d, // EraseChip + .erase_sector = 0x08000035, // EraseSector + .program_page = 0x08000041, // ProgramPage + .verify = 0x08000055, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08000a14, + 0x08000d00 + }, + .program_buffer = 0x08000000 + 0x00000D00, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxA_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxA_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00000200, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; +static const program_target_t CY8C6xxA_WFLASH_flash_prog = + // WFLASH (Work) + { + .init = 0x08000021, // Init + .uninit = 0x08000027, // UnInit + .erase_chip = 0x0800002d, // EraseChip + .erase_sector = 0x08000035, // EraseSector + .program_page = 0x08000041, // ProgramPage + .verify = 0x08000055, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08000a18, + 0x08000d00 + }, + .program_buffer = 0x08000000 + 0x00000D00, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxA_WFLASH_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxA_WFLASH_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00000200, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; +static const program_target_t CY8C6xxA_SFLASH_USER_flash_prog = + // SFLASH: User Data + { + .init = 0x08000021, // Init + .uninit = 0x08000027, // UnInit + .erase_chip = 0x0800002d, // EraseChip + .erase_sector = 0x08000035, // EraseSector + .program_page = 0x08000041, // ProgramPage + .verify = 0x08000055, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08000a1c, + 0x08000d00 + }, + .program_buffer = 0x08000000 + 0x00000D00, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxA_SFLASH_USER_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxA_SFLASH_USER_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00000200, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; +static const program_target_t CY8C6xxA_SFLASH_NAR_flash_prog = + // SFLASH: NAR + { + .init = 0x08000021, // Init + .uninit = 0x08000027, // UnInit + .erase_chip = 0x0800002d, // EraseChip + .erase_sector = 0x08000035, // EraseSector + .program_page = 0x08000041, // ProgramPage + .verify = 0x08000055, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08000a1c, + 0x08000d00 + }, + .program_buffer = 0x08000000 + 0x00000D00, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxA_SFLASH_NAR_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxA_SFLASH_NAR_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00000200, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; +static const program_target_t CY8C6xxA_SFLASH_PKEY_flash_prog = + // SFLASH: Public Key + { + .init = 0x08000021, // Init + .uninit = 0x08000027, // UnInit + .erase_chip = 0x0800002d, // EraseChip + .erase_sector = 0x08000035, // EraseSector + .program_page = 0x08000041, // ProgramPage + .verify = 0x08000055, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08000a1c, + 0x08000d00 + }, + .program_buffer = 0x08000000 + 0x00000D00, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxA_SFLASH_PKEY_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxA_SFLASH_PKEY_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00000200, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; +static const program_target_t CY8C6xxA_SFLASH_TOC2_flash_prog = + // SFLASH: TOC2 + { + .init = 0x08000021, // Init + .uninit = 0x08000027, // UnInit + .erase_chip = 0x0800002d, // EraseChip + .erase_sector = 0x08000035, // EraseSector + .program_page = 0x08000041, // ProgramPage + .verify = 0x08000055, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08000a1c, + 0x08000d00 + }, + .program_buffer = 0x08000000 + 0x00000D00, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxA_SFLASH_TOC2_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxA_SFLASH_TOC2_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00000200, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; +static const program_target_t CY8C6xxA_SMIF_flash_prog = + // SMIF + { + .init = 0x08000069, // Init + .uninit = 0x08000081, // UnInit + .erase_chip = 0x0800008b, // EraseChip + .erase_sector = 0x08000093, // EraseSector + .program_page = 0x080000a7, // ProgramPage + .verify = 0x080000b3, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08001d0c, + 0x08004000 + }, + .program_buffer = 0x08000000 + 0x00004000, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxA_SMIF_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxA_SMIF_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00001000, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; + diff --git a/source/family/cypress/PSoC6xxx/p6_ble_flash_blob.c b/source/family/cypress/PSoC6xxx/p6_ble_flash_blob.c new file mode 100644 index 0000000000..2d1a4e8eb4 --- /dev/null +++ b/source/family/cypress/PSoC6xxx/p6_ble_flash_blob.c @@ -0,0 +1,686 @@ +/******************************************************************************* +* @file p6_ble_flash_blob.c +* @brief Flash algorithm for the PSoC6 BLE target MCU +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "flash_blob.h" + +// Main Flash algo + +static const uint32_t CY8C6xx7_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x20004603, 0x46014770, 0x47702000, 0xf000b510, 0xbd10f972, 0x4604b510, 0xf0004620, 0xbd10f915, + 0x4606b570, 0x4615460c, 0x46294622, 0xf0004630, 0xbd70f969, 0x4604b570, 0x4616460d, 0x46294632, + 0xf0004620, 0xbd70f81f, 0x47706001, 0x600a6802, 0x21004770, 0x1c49e000, 0x43424ad6, 0xd8fa428a, + 0xb5084770, 0x48d44669, 0xfff0f7ff, 0x0209210f, 0x40089800, 0xd1012800, 0xe0002001, 0x46032000, + 0xbd084618, 0x4603b570, 0x461d460c, 0xe0052100, 0x5c6e5c50, 0xd00042b0, 0x1c49e002, 0xd3f742a1, + 0x1858bf00, 0xb5febd70, 0x460b4605, 0x20004616, 0x24009002, 0x01682700, 0x184049c0, 0xbf009000, + 0x9800a901, 0xf7ff3010, 0x9801ffc1, 0x2b000fc7, 0x2f00d001, 0x2b00d103, 0x2f00d103, 0x2001d101, + 0x2000e000, 0x2c004604, 0x9802d109, 0xd90042b0, 0x2001e007, 0xffadf7ff, 0x1c409802, 0x2c009002, + 0xbf00d0de, 0x21014620, 0xbdfe4048, 0x4604b5f8, 0x2600460d, 0x01602300, 0x184749a8, 0x4669bf00, + 0xf7ff4638, 0x9800ff93, 0x2b000fc3, 0x42aed106, 0xe005d900, 0xf7ff2001, 0x1c76ff8c, 0xd0ee2b00, + 0x4618bf00, 0x40482101, 0xb5f0bdf8, 0x460d4607, 0x26004613, 0xbf002400, 0x46384619, 0xff76f7ff, + 0x0f006818, 0x21050700, 0x42880749, 0x2001d101, 0x2000e000, 0x2c004604, 0x42aed106, 0xe005d900, + 0xf7ff2001, 0x1c76ff66, 0xd0e52c00, 0x4620bf00, 0x40482101, 0xb5f3bdf0, 0x4606b082, 0x48882700, + 0x90014478, 0x0fc007f0, 0x40482101, 0x25009000, 0xff57f7ff, 0xd0022800, 0x4d802400, 0x2401e002, + 0x35204d7e, 0x31f521ff, 0xf7ff4620, 0x4607ff9f, 0xd1362f00, 0x28009800, 0x4628d005, 0x9901300c, + 0xff32f7ff, 0x4631e004, 0x300c4628, 0xff2cf7ff, 0x30104620, 0x40822201, 0x48724611, 0xff24f7ff, + 0x46282101, 0xf7ff3008, 0x22ffff1f, 0x210032f5, 0xf7ff4620, 0x4607ff48, 0xd1122f00, 0x28009800, + 0x21ffd007, 0x9a0331f5, 0xf7ff9801, 0x4607ff8e, 0x21ffe007, 0x462831f5, 0x9a03300c, 0xff85f7ff, + 0x46384607, 0xbdf0b004, 0x4604b538, 0x447d4d5c, 0x495d3dae, 0xf7ff4628, 0x4621fef7, 0xf7ff1d28, + 0x4669fef3, 0xf7ff4858, 0xbd38ff96, 0x4604b538, 0x447d4d53, 0x49553dd2, 0xf7ff4628, 0x4621fee5, + 0xf7ff1d28, 0x4669fee1, 0xf7ff4850, 0xbd38ff84, 0x4604b538, 0x447d4d4a, 0x494c3df6, 0xf7ff4628, + 0x4621fed3, 0xf7ff1d28, 0x4669fecf, 0xf7ff4847, 0xbd38ff72, 0x4c46b518, 0x4946447c, 0xf7ff4620, + 0x4669fec3, 0xf7ff4843, 0xbd18ff66, 0x4606b570, 0x2500460c, 0x4630e00a, 0xffb6f7ff, 0x2d004605, + 0xe005d000, 0x36ff36ff, 0x1e643602, 0xd1f22c00, 0x4628bf00, 0xb510bd70, 0xf7ff2400, 0x4604ffdb, + 0xbd104620, 0x4605b5f8, 0x4617460e, 0x447c4c30, 0x49313c56, 0xf7ff4620, 0x21fffe97, 0x1d203107, + 0xfe92f7ff, 0x46204629, 0xf7ff3008, 0x4631fe8d, 0x300c4620, 0xfe88f7ff, 0x48274669, 0xff2bf7ff, + 0xb5f8bdf8, 0x460e4605, 0x4c214617, 0x3c94447c, 0x46204922, 0xfe78f7ff, 0x310721ff, 0xf7ff1d20, + 0x4629fe73, 0x30084620, 0xfe6ef7ff, 0x46204631, 0xf7ff300c, 0x4669fe69, 0xf7ff4818, 0xbdf8ff0c, + 0xb0ffb570, 0x4605b081, 0x24002600, 0x2000e003, 0x55084669, 0x20011c64, 0x42840240, 0x4602dbf7, + 0x46284669, 0xffcdf7ff, 0x46304606, 0xb001b07f, 0x0000bd70, 0x00000d05, 0x40210400, 0x40230000, + 0x0000023c, 0x40231008, 0x1c000100, 0x14000100, 0x00000124, 0x0a000100, 0x06000100, 0x05000100, + 0x00000000 +}; + +// Start address of flash +// static const uint32_t flash_start = 0x10000000; +// Size of flash +// static const uint32_t flash_size = 0x00100000; + +/** +* List of start and size for each size of flash sector - even indexes are start, odd are size +* The size will apply to all sectors between the listed address and the next address +* in the list. +* The last pair in the list will have sectors starting at that address and ending +* at address flash_start + flash_size. +*/ + +// WFLASH (Work) algo +static const uint32_t CY8C6xxx_WFLASH_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x20004603, 0x46014770, 0x47702000, 0xf000b510, 0xbd10f972, 0x4604b510, 0xf0004620, 0xbd10f915, + 0x4606b570, 0x4615460c, 0x46294622, 0xf0004630, 0xbd70f96c, 0x4604b570, 0x4616460d, 0x46294632, + 0xf0004620, 0xbd70f81f, 0x47706001, 0x600a6802, 0x21004770, 0x1c49e000, 0x43424ad7, 0xd8fa428a, + 0xb5084770, 0x48d54669, 0xfff0f7ff, 0x0209210f, 0x40089800, 0xd1012800, 0xe0002001, 0x46032000, + 0xbd084618, 0x4603b570, 0x461d460c, 0xe0052100, 0x5c6e5c50, 0xd00042b0, 0x1c49e002, 0xd3f742a1, + 0x1858bf00, 0xb5febd70, 0x460b4605, 0x20004616, 0x24009002, 0x01682700, 0x184049c1, 0xbf009000, + 0x9800a901, 0xf7ff3010, 0x9801ffc1, 0x2b000fc7, 0x2f00d001, 0x2b00d103, 0x2f00d103, 0x2001d101, + 0x2000e000, 0x2c004604, 0x9802d109, 0xd90042b0, 0x2001e007, 0xffadf7ff, 0x1c409802, 0x2c009002, + 0xbf00d0de, 0x21014620, 0xbdfe4048, 0x4604b5f8, 0x2600460d, 0x01602300, 0x184749a9, 0x4669bf00, + 0xf7ff4638, 0x9800ff93, 0x2b000fc3, 0x42aed106, 0xe005d900, 0xf7ff2001, 0x1c76ff8c, 0xd0ee2b00, + 0x4618bf00, 0x40482101, 0xb5f0bdf8, 0x460d4607, 0x26004613, 0xbf002400, 0x46384619, 0xff76f7ff, + 0x0f006818, 0x21050700, 0x42880749, 0x2001d101, 0x2000e000, 0x2c004604, 0x42aed106, 0xe005d900, + 0xf7ff2001, 0x1c76ff66, 0xd0e52c00, 0x4620bf00, 0x40482101, 0xb5f3bdf0, 0x4606b082, 0x48892700, + 0x90014478, 0x0fc007f0, 0x40482101, 0x25009000, 0xff57f7ff, 0xd0022800, 0x4d812400, 0x2401e002, + 0x35204d7f, 0x31f521ff, 0xf7ff4620, 0x4607ff9f, 0xd1362f00, 0x28009800, 0x4628d005, 0x9901300c, + 0xff32f7ff, 0x4631e004, 0x300c4628, 0xff2cf7ff, 0x30104620, 0x40822201, 0x48734611, 0xff24f7ff, + 0x46282101, 0xf7ff3008, 0x22ffff1f, 0x210032f5, 0xf7ff4620, 0x4607ff48, 0xd1122f00, 0x28009800, + 0x21ffd007, 0x9a0331f5, 0xf7ff9801, 0x4607ff8e, 0x21ffe007, 0x462831f5, 0x9a03300c, 0xff85f7ff, + 0x46384607, 0xbdf0b004, 0x4604b538, 0x447d4d5d, 0x495e3dae, 0xf7ff4628, 0x4621fef7, 0xf7ff1d28, + 0x4669fef3, 0xf7ff4859, 0xbd38ff96, 0x4604b538, 0x447d4d54, 0x49563dd2, 0xf7ff4628, 0x4621fee5, + 0xf7ff1d28, 0x4669fee1, 0xf7ff4851, 0xbd38ff84, 0x4604b538, 0x447d4d4b, 0x494d3df6, 0xf7ff4628, + 0x4621fed3, 0xf7ff1d28, 0x4669fecf, 0xf7ff4848, 0xbd38ff72, 0x4c47b518, 0x4947447c, 0xf7ff4620, + 0x4669fec3, 0xf7ff4844, 0xbd18ff66, 0x4606b570, 0x2500460c, 0x4630e00a, 0xffb6f7ff, 0x2d004605, + 0xe005d000, 0x36ff36ff, 0x1e643602, 0xd1f22c00, 0x4628bf00, 0xb510bd70, 0x21402400, 0x06802005, + 0xffe4f7ff, 0x46204604, 0xb5f8bd10, 0x460e4605, 0x4c304617, 0x3c5c447c, 0x46204930, 0xfe94f7ff, + 0x310721ff, 0xf7ff1d20, 0x4629fe8f, 0x30084620, 0xfe8af7ff, 0x46204631, 0xf7ff300c, 0x4669fe85, + 0xf7ff4826, 0xbdf8ff28, 0x4605b5f8, 0x4617460e, 0x447c4c20, 0x49223c9a, 0xf7ff4620, 0x21fffe75, + 0x1d203107, 0xfe70f7ff, 0x46204629, 0xf7ff3008, 0x4631fe6b, 0x300c4620, 0xfe66f7ff, 0x48184669, + 0xff09f7ff, 0xb570bdf8, 0xb081b0ff, 0x26004605, 0xe0032400, 0x46692000, 0x1c645508, 0x02402001, + 0xdbf74284, 0x46694602, 0xf7ff4628, 0x4606ffcd, 0xb07f4630, 0xbd70b001, 0x00000d05, 0x40210400, + 0x40230000, 0x00000240, 0x40231008, 0x1c000100, 0x14000100, 0x00000128, 0x0a000100, 0x06000100, + 0x05000100, 0x00000000 +}; + +// SFLASH: User Data algo +static const uint32_t CY8C6xxx_SFLASH_USER_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x20004603, 0x46014770, 0x47702000, 0xf000b510, 0xbd10f9aa, 0x4604b510, 0xf0004620, 0xbd10f976, + 0x4606b570, 0x4615460c, 0x46294622, 0xf0004630, 0xbd70f94d, 0x4604b570, 0x4616460d, 0x46294632, + 0xf0004620, 0xbd70f81f, 0x47706001, 0x600a6802, 0x21004770, 0x1c49e000, 0x43424ad7, 0xd8fa428a, + 0xb5084770, 0x48d54669, 0xfff0f7ff, 0x0209210f, 0x40089800, 0xd1012800, 0xe0002001, 0x46032000, + 0xbd084618, 0x4603b570, 0x461d460c, 0xe0052100, 0x5c6e5c50, 0xd00042b0, 0x1c49e002, 0xd3f742a1, + 0x1858bf00, 0xb5febd70, 0x460b4605, 0x20004616, 0x24009002, 0x01682700, 0x184049c1, 0xbf009000, + 0x9800a901, 0xf7ff3010, 0x9801ffc1, 0x2b000fc7, 0x2f00d001, 0x2b00d103, 0x2f00d103, 0x2001d101, + 0x2000e000, 0x2c004604, 0x9802d109, 0xd90042b0, 0x2001e007, 0xffadf7ff, 0x1c409802, 0x2c009002, + 0xbf00d0de, 0x21014620, 0xbdfe4048, 0x4604b5f8, 0x2600460d, 0x01602300, 0x184749a9, 0x4669bf00, + 0xf7ff4638, 0x9800ff93, 0x2b000fc3, 0x42aed106, 0xe005d900, 0xf7ff2001, 0x1c76ff8c, 0xd0ee2b00, + 0x4618bf00, 0x40482101, 0xb5f0bdf8, 0x460d4607, 0x26004613, 0xbf002400, 0x46384619, 0xff76f7ff, + 0x0f006818, 0x21050700, 0x42880749, 0x2001d101, 0x2000e000, 0x2c004604, 0x42aed106, 0xe005d900, + 0xf7ff2001, 0x1c76ff66, 0xd0e52c00, 0x4620bf00, 0x40482101, 0xb5f3bdf0, 0x4606b082, 0x48892700, + 0x90014478, 0x0fc007f0, 0x40482101, 0x25009000, 0xff57f7ff, 0xd0022800, 0x4d812400, 0x2401e002, + 0x35204d7f, 0x31f521ff, 0xf7ff4620, 0x4607ff9f, 0xd1362f00, 0x28009800, 0x4628d005, 0x9901300c, + 0xff32f7ff, 0x4631e004, 0x300c4628, 0xff2cf7ff, 0x30104620, 0x40822201, 0x48734611, 0xff24f7ff, + 0x46282101, 0xf7ff3008, 0x22ffff1f, 0x210032f5, 0xf7ff4620, 0x4607ff48, 0xd1122f00, 0x28009800, + 0x21ffd007, 0x9a0331f5, 0xf7ff9801, 0x4607ff8e, 0x21ffe007, 0x462831f5, 0x9a03300c, 0xff85f7ff, + 0x46384607, 0xbdf0b004, 0x4604b538, 0x447d4d5d, 0x495e3dae, 0xf7ff4628, 0x4621fef7, 0xf7ff1d28, + 0x4669fef3, 0xf7ff4859, 0xbd38ff96, 0x4604b538, 0x447d4d54, 0x49563dd2, 0xf7ff4628, 0x4621fee5, + 0xf7ff1d28, 0x4669fee1, 0xf7ff4851, 0xbd38ff84, 0x4604b538, 0x447d4d4b, 0x494d3df6, 0xf7ff4628, + 0x4621fed3, 0xf7ff1d28, 0x4669fecf, 0xf7ff4848, 0xbd38ff72, 0x4c47b518, 0x4947447c, 0xf7ff4620, + 0x4669fec3, 0xf7ff4844, 0xbd18ff66, 0x4605b5f8, 0x4617460e, 0x447c4c3f, 0x49403c1e, 0xf7ff4620, + 0x21fffeb3, 0x1d203107, 0xfeaef7ff, 0x46204629, 0xf7ff3008, 0x4631fea9, 0x300c4620, 0xfea4f7ff, + 0x48364669, 0xff47f7ff, 0xb570bdf8, 0xb081b0ff, 0x26004605, 0xe0032400, 0x46692000, 0x1c645508, + 0x02402001, 0xdbf74284, 0x46694602, 0xf7ff4628, 0x4606ffcd, 0xb07f4630, 0xbd70b001, 0x4606b570, + 0x2500460c, 0x4630e00a, 0xffdff7ff, 0x2d004605, 0xe005d000, 0x36ff36ff, 0x1e643602, 0xd1f22c00, + 0x4628bf00, 0xb510bd70, 0x21042400, 0xf7ff481c, 0x4604ffe5, 0xbd104620, 0x4605b5f8, 0x4617460e, + 0x447c4c14, 0x49173cca, 0xf7ff4620, 0x21fffe5d, 0x1d203107, 0xfe58f7ff, 0x46204629, 0xf7ff3008, + 0x4631fe53, 0x300c4620, 0xfe4ef7ff, 0x480d4669, 0xfef1f7ff, 0x0000bdf8, 0x00000d05, 0x40210400, + 0x40230000, 0x00000244, 0x40231008, 0x1c000100, 0x14000100, 0x0000012c, 0x0a000100, 0x05000100, + 0x16000800, 0x06000100, 0x00000000 +}; + +// SFLASH: NAR algo +static const uint32_t CY8C6xxx_SFLASH_NAR_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x20004603, 0x46014770, 0x47702000, 0xf000b510, 0xbd10f9aa, 0x4604b510, 0xf0004620, 0xbd10f976, + 0x4606b570, 0x4615460c, 0x46294622, 0xf0004630, 0xbd70f94d, 0x4604b570, 0x4616460d, 0x46294632, + 0xf0004620, 0xbd70f81f, 0x47706001, 0x600a6802, 0x21004770, 0x1c49e000, 0x43424ad7, 0xd8fa428a, + 0xb5084770, 0x48d54669, 0xfff0f7ff, 0x0209210f, 0x40089800, 0xd1012800, 0xe0002001, 0x46032000, + 0xbd084618, 0x4603b570, 0x461d460c, 0xe0052100, 0x5c6e5c50, 0xd00042b0, 0x1c49e002, 0xd3f742a1, + 0x1858bf00, 0xb5febd70, 0x460b4605, 0x20004616, 0x24009002, 0x01682700, 0x184049c1, 0xbf009000, + 0x9800a901, 0xf7ff3010, 0x9801ffc1, 0x2b000fc7, 0x2f00d001, 0x2b00d103, 0x2f00d103, 0x2001d101, + 0x2000e000, 0x2c004604, 0x9802d109, 0xd90042b0, 0x2001e007, 0xffadf7ff, 0x1c409802, 0x2c009002, + 0xbf00d0de, 0x21014620, 0xbdfe4048, 0x4604b5f8, 0x2600460d, 0x01602300, 0x184749a9, 0x4669bf00, + 0xf7ff4638, 0x9800ff93, 0x2b000fc3, 0x42aed106, 0xe005d900, 0xf7ff2001, 0x1c76ff8c, 0xd0ee2b00, + 0x4618bf00, 0x40482101, 0xb5f0bdf8, 0x460d4607, 0x26004613, 0xbf002400, 0x46384619, 0xff76f7ff, + 0x0f006818, 0x21050700, 0x42880749, 0x2001d101, 0x2000e000, 0x2c004604, 0x42aed106, 0xe005d900, + 0xf7ff2001, 0x1c76ff66, 0xd0e52c00, 0x4620bf00, 0x40482101, 0xb5f3bdf0, 0x4606b082, 0x48892700, + 0x90014478, 0x0fc007f0, 0x40482101, 0x25009000, 0xff57f7ff, 0xd0022800, 0x4d812400, 0x2401e002, + 0x35204d7f, 0x31f521ff, 0xf7ff4620, 0x4607ff9f, 0xd1362f00, 0x28009800, 0x4628d005, 0x9901300c, + 0xff32f7ff, 0x4631e004, 0x300c4628, 0xff2cf7ff, 0x30104620, 0x40822201, 0x48734611, 0xff24f7ff, + 0x46282101, 0xf7ff3008, 0x22ffff1f, 0x210032f5, 0xf7ff4620, 0x4607ff48, 0xd1122f00, 0x28009800, + 0x21ffd007, 0x9a0331f5, 0xf7ff9801, 0x4607ff8e, 0x21ffe007, 0x462831f5, 0x9a03300c, 0xff85f7ff, + 0x46384607, 0xbdf0b004, 0x4604b538, 0x447d4d5d, 0x495e3dae, 0xf7ff4628, 0x4621fef7, 0xf7ff1d28, + 0x4669fef3, 0xf7ff4859, 0xbd38ff96, 0x4604b538, 0x447d4d54, 0x49563dd2, 0xf7ff4628, 0x4621fee5, + 0xf7ff1d28, 0x4669fee1, 0xf7ff4851, 0xbd38ff84, 0x4604b538, 0x447d4d4b, 0x494d3df6, 0xf7ff4628, + 0x4621fed3, 0xf7ff1d28, 0x4669fecf, 0xf7ff4848, 0xbd38ff72, 0x4c47b518, 0x4947447c, 0xf7ff4620, + 0x4669fec3, 0xf7ff4844, 0xbd18ff66, 0x4605b5f8, 0x4617460e, 0x447c4c3f, 0x49403c1e, 0xf7ff4620, + 0x21fffeb3, 0x1d203107, 0xfeaef7ff, 0x46204629, 0xf7ff3008, 0x4631fea9, 0x300c4620, 0xfea4f7ff, + 0x48364669, 0xff47f7ff, 0xb570bdf8, 0xb081b0ff, 0x26004605, 0xe0032400, 0x46692000, 0x1c645508, + 0x02402001, 0xdbf74284, 0x46694602, 0xf7ff4628, 0x4606ffcd, 0xb07f4630, 0xbd70b001, 0x4606b570, + 0x2500460c, 0x4630e00a, 0xffdff7ff, 0x2d004605, 0xe005d000, 0x36ff36ff, 0x1e643602, 0xd1f22c00, + 0x4628bf00, 0xb510bd70, 0x21012400, 0xf7ff481c, 0x4604ffe5, 0xbd104620, 0x4605b5f8, 0x4617460e, + 0x447c4c14, 0x49173cca, 0xf7ff4620, 0x21fffe5d, 0x1d203107, 0xfe58f7ff, 0x46204629, 0xf7ff3008, + 0x4631fe53, 0x300c4620, 0xfe4ef7ff, 0x480d4669, 0xfef1f7ff, 0x0000bdf8, 0x00000d05, 0x40210400, + 0x40230000, 0x00000244, 0x40231008, 0x1c000100, 0x14000100, 0x0000012c, 0x0a000100, 0x05000100, + 0x16001a00, 0x06000100, 0x00000000 +}; + +// SFLASH: Public Key algo +static const uint32_t CY8C6xxx_SFLASH_PKEY_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x20004603, 0x46014770, 0x47702000, 0xf000b510, 0xbd10f9aa, 0x4604b510, 0xf0004620, 0xbd10f976, + 0x4606b570, 0x4615460c, 0x46294622, 0xf0004630, 0xbd70f94d, 0x4604b570, 0x4616460d, 0x46294632, + 0xf0004620, 0xbd70f81f, 0x47706001, 0x600a6802, 0x21004770, 0x1c49e000, 0x43424ad7, 0xd8fa428a, + 0xb5084770, 0x48d54669, 0xfff0f7ff, 0x0209210f, 0x40089800, 0xd1012800, 0xe0002001, 0x46032000, + 0xbd084618, 0x4603b570, 0x461d460c, 0xe0052100, 0x5c6e5c50, 0xd00042b0, 0x1c49e002, 0xd3f742a1, + 0x1858bf00, 0xb5febd70, 0x460b4605, 0x20004616, 0x24009002, 0x01682700, 0x184049c1, 0xbf009000, + 0x9800a901, 0xf7ff3010, 0x9801ffc1, 0x2b000fc7, 0x2f00d001, 0x2b00d103, 0x2f00d103, 0x2001d101, + 0x2000e000, 0x2c004604, 0x9802d109, 0xd90042b0, 0x2001e007, 0xffadf7ff, 0x1c409802, 0x2c009002, + 0xbf00d0de, 0x21014620, 0xbdfe4048, 0x4604b5f8, 0x2600460d, 0x01602300, 0x184749a9, 0x4669bf00, + 0xf7ff4638, 0x9800ff93, 0x2b000fc3, 0x42aed106, 0xe005d900, 0xf7ff2001, 0x1c76ff8c, 0xd0ee2b00, + 0x4618bf00, 0x40482101, 0xb5f0bdf8, 0x460d4607, 0x26004613, 0xbf002400, 0x46384619, 0xff76f7ff, + 0x0f006818, 0x21050700, 0x42880749, 0x2001d101, 0x2000e000, 0x2c004604, 0x42aed106, 0xe005d900, + 0xf7ff2001, 0x1c76ff66, 0xd0e52c00, 0x4620bf00, 0x40482101, 0xb5f3bdf0, 0x4606b082, 0x48892700, + 0x90014478, 0x0fc007f0, 0x40482101, 0x25009000, 0xff57f7ff, 0xd0022800, 0x4d812400, 0x2401e002, + 0x35204d7f, 0x31f521ff, 0xf7ff4620, 0x4607ff9f, 0xd1362f00, 0x28009800, 0x4628d005, 0x9901300c, + 0xff32f7ff, 0x4631e004, 0x300c4628, 0xff2cf7ff, 0x30104620, 0x40822201, 0x48734611, 0xff24f7ff, + 0x46282101, 0xf7ff3008, 0x22ffff1f, 0x210032f5, 0xf7ff4620, 0x4607ff48, 0xd1122f00, 0x28009800, + 0x21ffd007, 0x9a0331f5, 0xf7ff9801, 0x4607ff8e, 0x21ffe007, 0x462831f5, 0x9a03300c, 0xff85f7ff, + 0x46384607, 0xbdf0b004, 0x4604b538, 0x447d4d5d, 0x495e3dae, 0xf7ff4628, 0x4621fef7, 0xf7ff1d28, + 0x4669fef3, 0xf7ff4859, 0xbd38ff96, 0x4604b538, 0x447d4d54, 0x49563dd2, 0xf7ff4628, 0x4621fee5, + 0xf7ff1d28, 0x4669fee1, 0xf7ff4851, 0xbd38ff84, 0x4604b538, 0x447d4d4b, 0x494d3df6, 0xf7ff4628, + 0x4621fed3, 0xf7ff1d28, 0x4669fecf, 0xf7ff4848, 0xbd38ff72, 0x4c47b518, 0x4947447c, 0xf7ff4620, + 0x4669fec3, 0xf7ff4844, 0xbd18ff66, 0x4605b5f8, 0x4617460e, 0x447c4c3f, 0x49403c1e, 0xf7ff4620, + 0x21fffeb3, 0x1d203107, 0xfeaef7ff, 0x46204629, 0xf7ff3008, 0x4631fea9, 0x300c4620, 0xfea4f7ff, + 0x48364669, 0xff47f7ff, 0xb570bdf8, 0xb081b0ff, 0x26004605, 0xe0032400, 0x46692000, 0x1c645508, + 0x02402001, 0xdbf74284, 0x46694602, 0xf7ff4628, 0x4606ffcd, 0xb07f4630, 0xbd70b001, 0x4606b570, + 0x2500460c, 0x4630e00a, 0xffdff7ff, 0x2d004605, 0xe005d000, 0x36ff36ff, 0x1e643602, 0xd1f22c00, + 0x4628bf00, 0xb510bd70, 0x21062400, 0xf7ff481c, 0x4604ffe5, 0xbd104620, 0x4605b5f8, 0x4617460e, + 0x447c4c14, 0x49173cca, 0xf7ff4620, 0x21fffe5d, 0x1d203107, 0xfe58f7ff, 0x46204629, 0xf7ff3008, + 0x4631fe53, 0x300c4620, 0xfe4ef7ff, 0x480d4669, 0xfef1f7ff, 0x0000bdf8, 0x00000d05, 0x40210400, + 0x40230000, 0x00000244, 0x40231008, 0x1c000100, 0x14000100, 0x0000012c, 0x0a000100, 0x05000100, + 0x16005a00, 0x06000100, 0x00000000 +}; + +// SFLASH: TOC2 algo +static const uint32_t CY8C6xxx_SFLASH_TOC2_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x20004603, 0x46014770, 0x47702000, 0xf000b510, 0xbd10f9aa, 0x4604b510, 0xf0004620, 0xbd10f976, + 0x4606b570, 0x4615460c, 0x46294622, 0xf0004630, 0xbd70f94d, 0x4604b570, 0x4616460d, 0x46294632, + 0xf0004620, 0xbd70f81f, 0x47706001, 0x600a6802, 0x21004770, 0x1c49e000, 0x43424ad7, 0xd8fa428a, + 0xb5084770, 0x48d54669, 0xfff0f7ff, 0x0209210f, 0x40089800, 0xd1012800, 0xe0002001, 0x46032000, + 0xbd084618, 0x4603b570, 0x461d460c, 0xe0052100, 0x5c6e5c50, 0xd00042b0, 0x1c49e002, 0xd3f742a1, + 0x1858bf00, 0xb5febd70, 0x460b4605, 0x20004616, 0x24009002, 0x01682700, 0x184049c1, 0xbf009000, + 0x9800a901, 0xf7ff3010, 0x9801ffc1, 0x2b000fc7, 0x2f00d001, 0x2b00d103, 0x2f00d103, 0x2001d101, + 0x2000e000, 0x2c004604, 0x9802d109, 0xd90042b0, 0x2001e007, 0xffadf7ff, 0x1c409802, 0x2c009002, + 0xbf00d0de, 0x21014620, 0xbdfe4048, 0x4604b5f8, 0x2600460d, 0x01602300, 0x184749a9, 0x4669bf00, + 0xf7ff4638, 0x9800ff93, 0x2b000fc3, 0x42aed106, 0xe005d900, 0xf7ff2001, 0x1c76ff8c, 0xd0ee2b00, + 0x4618bf00, 0x40482101, 0xb5f0bdf8, 0x460d4607, 0x26004613, 0xbf002400, 0x46384619, 0xff76f7ff, + 0x0f006818, 0x21050700, 0x42880749, 0x2001d101, 0x2000e000, 0x2c004604, 0x42aed106, 0xe005d900, + 0xf7ff2001, 0x1c76ff66, 0xd0e52c00, 0x4620bf00, 0x40482101, 0xb5f3bdf0, 0x4606b082, 0x48892700, + 0x90014478, 0x0fc007f0, 0x40482101, 0x25009000, 0xff57f7ff, 0xd0022800, 0x4d812400, 0x2401e002, + 0x35204d7f, 0x31f521ff, 0xf7ff4620, 0x4607ff9f, 0xd1362f00, 0x28009800, 0x4628d005, 0x9901300c, + 0xff32f7ff, 0x4631e004, 0x300c4628, 0xff2cf7ff, 0x30104620, 0x40822201, 0x48734611, 0xff24f7ff, + 0x46282101, 0xf7ff3008, 0x22ffff1f, 0x210032f5, 0xf7ff4620, 0x4607ff48, 0xd1122f00, 0x28009800, + 0x21ffd007, 0x9a0331f5, 0xf7ff9801, 0x4607ff8e, 0x21ffe007, 0x462831f5, 0x9a03300c, 0xff85f7ff, + 0x46384607, 0xbdf0b004, 0x4604b538, 0x447d4d5d, 0x495e3dae, 0xf7ff4628, 0x4621fef7, 0xf7ff1d28, + 0x4669fef3, 0xf7ff4859, 0xbd38ff96, 0x4604b538, 0x447d4d54, 0x49563dd2, 0xf7ff4628, 0x4621fee5, + 0xf7ff1d28, 0x4669fee1, 0xf7ff4851, 0xbd38ff84, 0x4604b538, 0x447d4d4b, 0x494d3df6, 0xf7ff4628, + 0x4621fed3, 0xf7ff1d28, 0x4669fecf, 0xf7ff4848, 0xbd38ff72, 0x4c47b518, 0x4947447c, 0xf7ff4620, + 0x4669fec3, 0xf7ff4844, 0xbd18ff66, 0x4605b5f8, 0x4617460e, 0x447c4c3f, 0x49403c1e, 0xf7ff4620, + 0x21fffeb3, 0x1d203107, 0xfeaef7ff, 0x46204629, 0xf7ff3008, 0x4631fea9, 0x300c4620, 0xfea4f7ff, + 0x48364669, 0xff47f7ff, 0xb570bdf8, 0xb081b0ff, 0x26004605, 0xe0032400, 0x46692000, 0x1c645508, + 0x02402001, 0xdbf74284, 0x46694602, 0xf7ff4628, 0x4606ffcd, 0xb07f4630, 0xbd70b001, 0x4606b570, + 0x2500460c, 0x4630e00a, 0xffdff7ff, 0x2d004605, 0xe005d000, 0x36ff36ff, 0x1e643602, 0xd1f22c00, + 0x4628bf00, 0xb510bd70, 0x21022400, 0xf7ff481c, 0x4604ffe5, 0xbd104620, 0x4605b5f8, 0x4617460e, + 0x447c4c14, 0x49173cca, 0xf7ff4620, 0x21fffe5d, 0x1d203107, 0xfe58f7ff, 0x46204629, 0xf7ff3008, + 0x4631fe53, 0x300c4620, 0xfe4ef7ff, 0x480d4669, 0xfef1f7ff, 0x0000bdf8, 0x00000d05, 0x40210400, + 0x40230000, 0x00000244, 0x40231008, 0x1c000100, 0x14000100, 0x0000012c, 0x0a000100, 0x05000100, + 0x16007c00, 0x06000100, 0x00000000 +}; + + //SMIF algo +static const uint32_t CY8C6xxx_SMIF_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x08801c80, 0x1c40d003, 0xd1fc1e80, 0x4770bf00, 0x4605b570, 0x4616460c, 0xcc0fe002, 0x3e10c50f, + 0xd2fa2e10, 0xd3022e08, 0xc503cc03, 0x2e043e08, 0xcc01d307, 0x1f36c501, 0x7821e003, 0x1c647029, + 0x1e761c6d, 0xbd70d2f9, 0x4604b510, 0xf0002000, 0xf000f892, 0x4620f847, 0xf97bf000, 0xbd102000, + 0xf000b510, 0x2000f984, 0xb510bd10, 0xf92df000, 0xb510bd10, 0x04092101, 0xf92bf000, 0xb510bd10, + 0xf927f000, 0xb510bd10, 0x2100460b, 0xf931f000, 0xb508bd10, 0xf000466b, 0x9800f93c, 0xb508bd08, + 0xf000466a, 0x9800f96d, 0x0000bd08, 0xb5104a76, 0x09d21882, 0x23004c75, 0x19120112, 0x6004680c, + 0x628468cc, 0x62c4690c, 0x6304694c, 0x6244688c, 0x6184684c, 0x6344698c, 0x601069c8, 0x60506a08, + 0xbd104618, 0x486ab500, 0x6881b089, 0x01090909, 0x4a676081, 0x3a402100, 0x68026091, 0x430a0601, + 0x68426002, 0x6042430a, 0x430a6882, 0x49616082, 0x44792224, 0xf7ff4668, 0x4669ff7b, 0xf7ff485e, + 0x495cffc5, 0x44792224, 0x46683110, 0xff70f7ff, 0x485a4669, 0xffbaf7ff, 0x22244956, 0x311e4479, + 0xf7ff4668, 0x4855ff65, 0x30804669, 0xffaef7ff, 0x22244950, 0x312a4479, 0xf7ff4668, 0x4669ff59, + 0xf7ff484f, 0xb009ffa3, 0xb510bd00, 0x18400081, 0xff46f7ff, 0xb5f0bd10, 0x494a0003, 0x48484a44, + 0x4d464c45, 0xd0204449, 0x6093680b, 0x6013684b, 0x6053688b, 0x609168c9, 0x44494942, 0xf7ff3110, + 0x4940ff85, 0x44494620, 0xf7ff3134, 0x493dff7f, 0x44494628, 0xf7ff3158, 0x493aff79, 0x44494837, + 0x3080317c, 0xff72f7ff, 0x4e30bdf0, 0x36106807, 0x444b4b34, 0x601f3310, 0x60df6a87, 0x611f6ac7, + 0x615f6b07, 0x609f6a47, 0x605f6987, 0x619f6b47, 0x61df6837, 0x621e6876, 0x68274e24, 0x33243680, + 0x6aa7601f, 0x6ae760df, 0x6b27611f, 0x6a67615f, 0x69a7609f, 0x6b64605f, 0x6834619c, 0x687461dc, + 0x4c1a621c, 0x34b0682e, 0x601e3324, 0x60de6aae, 0x611e6aee, 0x615e6b2e, 0x609e6a6e, 0x605e69ae, + 0x619d6b6d, 0x61dd6825, 0x621c6864, 0x68054c0f, 0x332434c0, 0x6a85601d, 0x6ac560dd, 0x6b05611d, + 0x6a45615d, 0x6985609d, 0x6b40605d, 0x68206198, 0x686061d8, 0x68906218, 0x68106008, 0x68506048, + 0x68906088, 0xbdf060c8, 0xbfce0000, 0x40310000, 0x40260380, 0x00001b2a, 0x40320400, 0x40320580, + 0x40320080, 0x00000004, 0x06c92103, 0xd2014288, 0x47702000, 0x06c9211d, 0x21011840, 0x428806c9, + 0x2001d201, 0x20024770, 0xb5104770, 0xfab1f000, 0xb510bd10, 0x4603460a, 0xffe6f7ff, 0xd0012800, + 0xd0012801, 0xbd102001, 0x46184611, 0xf9a3f000, 0xb570bd10, 0x4605460c, 0xffd6f7ff, 0xd0012800, + 0xd0012801, 0xbd702001, 0x46284621, 0xfac4f000, 0xb570bd70, 0x4605460c, 0xffc6f7ff, 0xd0012800, + 0xd0012801, 0xbd702001, 0x46284621, 0xfbb9f000, 0xb510bd70, 0x4604460b, 0xffb6f7ff, 0xd0012800, + 0xd0012801, 0xbd102001, 0x46204619, 0xfbc8f000, 0xb510bd10, 0xf7ff4602, 0x2800ffa7, 0x2801d001, + 0x2001d001, 0x4610bd10, 0xfbd3f000, 0xb510bd10, 0xfbe2f000, 0x20014604, 0xfefdf7ff, 0xbd104620, + 0x4614b570, 0x4605460e, 0xf7ff2200, 0x2800ff8d, 0x2801d009, 0x2201d001, 0x4628e00f, 0xfbb9f000, + 0x28014602, 0x2000d009, 0x60204603, 0x5ce9e003, 0x1c5b1840, 0x42b36020, 0x4610d3f9, 0x0000bd70, + 0xb51048fe, 0x444849fd, 0x44496840, 0x3110220f, 0x188401d2, 0x07d36ce2, 0xf000d003, 0x2001fc1d, + 0x0793e004, 0xf000d505, 0x2002fbb4, 0x6c206420, 0x0750bd10, 0x2005d503, 0x20046188, 0x0710e7f6, + 0x2006d503, 0x20086188, 0x06d0e7f0, 0x2007d503, 0x20106188, 0x0690e7ea, 0x2008d5ea, 0x20206188, + 0x4ae6e7e4, 0x7811444a, 0xd0014381, 0x47702000, 0x70102000, 0x680148e2, 0x68092000, 0xd0052900, + 0xd0031c4b, 0x071b2301, 0xd2014299, 0x47702001, 0x210160d1, 0x47707011, 0x4604b5f0, 0x46942500, + 0x4628460e, 0xffddf7ff, 0xd1202800, 0x23004ad3, 0x68d0444a, 0xb2878800, 0x68d0e017, 0x68400099, + 0x28005840, 0x6030d010, 0x07897901, 0x68c1d50c, 0xd80942a1, 0x18086900, 0xd90542a0, 0x25016830, + 0x46606981, 0xe0026001, 0x42bb1c5b, 0x4628dbe5, 0x40482101, 0xb5ffbdf0, 0x4ec0b081, 0x2500990a, + 0x2900444e, 0x68b0d105, 0xd0022800, 0x4290aa01, 0x2000d058, 0x460860b0, 0xffa3f7ff, 0x28014604, + 0x2c02d00e, 0x4bb5d04e, 0x444b227d, 0x00d23310, 0x6870a901, 0xfbf6f000, 0xd0070005, 0xd0002c02, + 0x2d002401, 0x2c02d00f, 0xe03cd03c, 0xd0f72c01, 0xd0372c02, 0x68f14aa9, 0x3210444a, 0xf0016870, + 0x4605f975, 0x2c01e7ed, 0x2c02d02d, 0x49a3d02a, 0x44496870, 0xf0003110, 0x68f0fd49, 0x88002400, + 0xe01bb287, 0x00a568f0, 0x59416840, 0xd0142900, 0x6bc06988, 0xd0102800, 0x68704a98, 0x3210444a, + 0xf9e2f001, 0xd1082800, 0x4a9468f0, 0x444a6840, 0x32105941, 0xf0016870, 0x1c64fa53, 0xdbe142bc, + 0x60b0a801, 0x46202400, 0xbdf0b005, 0x2400b5f0, 0x460d4607, 0x46204626, 0xff43f7ff, 0xd11b2800, + 0x49862204, 0x44490083, 0x684968c9, 0x290058c9, 0x6039d00f, 0x079b790b, 0x6949d50b, 0xd10542a9, + 0xd0032c00, 0x26016838, 0xe0056038, 0xd10042a9, 0x1c402401, 0xdbe44290, 0x21014630, 0xbdf04048, + 0x2400b5f3, 0xb0814d75, 0x46264607, 0x9400444d, 0x46394a72, 0x3210444a, 0xf0016868, 0x6979f9d8, + 0xd00b2900, 0xd10b2800, 0xf7ff4668, 0x4a6bffbf, 0x444a9900, 0x68683210, 0xf9c9f001, 0xd0032800, + 0x42849802, 0x2601dd02, 0xbdfe4630, 0xf7ff2064, 0x1c64fd9c, 0xb5f0e7dc, 0x2700b089, 0x4604460d, + 0x97079706, 0xa906aa08, 0xf7ff9708, 0x2800ff05, 0x9806d111, 0x29006941, 0x460fd005, 0xf7ffa807, + 0x2800ff95, 0x2000d107, 0x48549000, 0x30384448, 0xf7ffc80f, 0x9908ff20, 0x698e9a06, 0x1a6468d1, + 0xd1052800, 0x4610494f, 0xffaaf7ff, 0xd07d2800, 0xbdf0b009, 0x99062000, 0x69889005, 0x28016800, + 0x2802d006, 0x2803d007, 0x2804d009, 0xe014d00d, 0x75044668, 0x466ae011, 0x0a207554, 0x466ae00c, + 0x0a207594, 0x0c207550, 0x466ae006, 0x0a2075d4, 0x0c207590, 0x0e207550, 0x4a387510, 0x444a4837, + 0x32104448, 0xf0016840, 0x2800f91f, 0x2001d001, 0x2f00e7ce, 0x4a31d00a, 0x444a4830, 0x32104448, + 0x68409907, 0xf910f001, 0xd1f02800, 0xd20042b5, 0x4b2a462e, 0x444b4829, 0x33104448, 0x9906aa05, + 0xf0016840, 0x2800f9ee, 0x2f00d1e1, 0x4b23d00b, 0x444b4822, 0x33104448, 0x9907aa05, 0xf0016840, + 0x2800f9e0, 0x481dd1d3, 0x68404448, 0x68404684, 0xd1f80fc0, 0x4b199906, 0x22007808, 0x3310444b, + 0x92039201, 0x92009304, 0x69889002, 0x6a804613, 0x46607801, 0xfb27f000, 0x21014810, 0x68404448, + 0x650104c9, 0x6c413080, 0xe0002900, 0xd0fae04d, 0xb2c06d00, 0x20649000, 0xfce7f7ff, 0x69809806, + 0x98006b81, 0xd1ce4201, 0xd0352f00, 0x44484803, 0x46846840, 0x0fc06840, 0xe005d1f8, 0x000000a4, + 0x16007c0c, 0x0000c350, 0x4bf79907, 0x22007808, 0x9201444b, 0x93049203, 0x90029200, 0x46136988, + 0x78016a80, 0xf0004660, 0x48effaee, 0x04c92101, 0x38104448, 0x65016840, 0x6c413080, 0xd0fc2900, + 0xb2c06d00, 0x20649000, 0xfcaff7ff, 0x69809807, 0x98006b81, 0xd1c94201, 0x980649e4, 0xfee0f7ff, + 0xd0002800, 0x1bade734, 0x2d0019a4, 0xe731d000, 0xb5f8e72e, 0x20004cdc, 0x3428444c, 0xcc0f9000, + 0xfe39f7ff, 0xd0262801, 0x39484621, 0x260068c9, 0xb2898809, 0xe01b9100, 0x00b249d3, 0x39104449, + 0x684968c9, 0x2d00588d, 0x7929d011, 0xd50e0789, 0x69af2400, 0x68e8e008, 0x190069b9, 0xfedbf7ff, + 0xd0082801, 0x190c69b9, 0x42a16929, 0x1c76d8f3, 0x428e9900, 0xbdf8dbe0, 0xb08bb5ff, 0x980c4604, + 0x1823461e, 0x90092000, 0x90079006, 0xaa089008, 0x4618a909, 0xfdd0f7ff, 0xd1080005, 0x69419809, + 0xd0062900, 0x9106a807, 0xfe60f7ff, 0x2d014605, 0x2001d008, 0x48b49000, 0x30284448, 0xf7ffc80f, + 0x4605fdea, 0x6a479808, 0x68c19809, 0x990c1a62, 0x21001854, 0x2d01910a, 0x49acd005, 0xfe70f7ff, + 0x28014605, 0xe0c9d178, 0x99092000, 0x69889005, 0x28016800, 0x2802d006, 0x2803d007, 0x2804d009, + 0xe014d00d, 0x75044668, 0x466ae011, 0x0a207554, 0x466ae00c, 0x0a207594, 0x0c207550, 0x466ae006, + 0x0a2075d4, 0x0c207590, 0x0e207550, 0x4a967510, 0x4610444a, 0x68403810, 0xffe6f000, 0xd1492800, + 0x28009806, 0x4a90d009, 0x444a9907, 0x38104610, 0xf0006840, 0x2800ffd9, 0x488bd13c, 0x38104448, + 0x46846840, 0x68404660, 0xd1fb0fc0, 0xd20042be, 0x98094637, 0x78014b84, 0x90009808, 0x444b6a00, + 0x79404686, 0x22009001, 0xc00ea802, 0xab059800, 0x90006800, 0x79024670, 0x46607801, 0xfa03f000, + 0xd1172800, 0x44484878, 0x68403810, 0x31804601, 0x0712684a, 0xd1fb0f12, 0x21004a73, 0x444a9100, + 0x92019908, 0x7d136a0a, 0x21006a4a, 0xfa29f000, 0xd0022800, 0xe0512501, 0x496be04d, 0x44499a08, + 0x68493910, 0x46942000, 0xe00a3180, 0x18139a0a, 0x5cd29a0d, 0x684a610a, 0x0f120712, 0xd8fa2a04, + 0x46621c40, 0x42826a52, 0x485fd8f0, 0x38104448, 0x46846840, 0x0fc06840, 0x9809d1f7, 0x78034a5a, + 0x444a2100, 0x91039101, 0x92049302, 0x69809100, 0x6a802300, 0x7801461a, 0xf0004660, 0x4852f9b4, + 0x04c92101, 0x38104448, 0x65016840, 0x6c413080, 0xd0fc2900, 0xb2c06d00, 0x20649000, 0xfb75f7ff, + 0x69809809, 0x98006b81, 0xd1ce4201, 0x1bf6980a, 0x19e419c0, 0x2e00900a, 0xe735d000, 0xb00f4628, + 0xb5ffbdf0, 0xb0814604, 0x90002000, 0x4615483e, 0x460e4448, 0xc80f3038, 0xfcfdf7ff, 0xd10e2800, + 0x23004621, 0x5ceae006, 0x42ba5ccf, 0x2001d001, 0x1c5be002, 0xd3f642b3, 0x990418ca, 0xe553600a, + 0x4606b5f8, 0x90002000, 0x4614482f, 0x460d4448, 0xc80f3038, 0xfcdff7ff, 0xd1052800, 0xe0052300, + 0x42a15cf1, 0x2001d001, 0x1c5bbdf8, 0xd3f742ab, 0xb50ebdf8, 0x91012100, 0xaa029102, 0xf7ffa901, + 0x2800fc9b, 0x2001d107, 0x481f9000, 0x30384448, 0xf7ffc80f, 0xbd0efcc0, 0xb510491b, 0x39104449, + 0x2401688a, 0xd0022a00, 0xf0006848, 0x4620f8ef, 0xb570bd10, 0x460d694c, 0x460368ca, 0x6c593380, + 0x0f090709, 0xd90042a1, 0x29004621, 0x2908d03f, 0x2901d015, 0x2902d01c, 0x2903d01d, 0x2904d01e, + 0x2905d021, 0x2906d022, 0x2907d025, 0x6d99d028, 0x6d996011, 0x21086051, 0x1a641852, 0x6d9ee7df, + 0x6d9e6016, 0xe7f76056, 0x000000b4, 0x0000c350, 0x70166d1e, 0x6d5ee7f0, 0xe7ed8016, 0x80166d5e, + 0x70966d1e, 0x6d9ee7e8, 0xe7e56016, 0x60166d9e, 0x71166d1e, 0x6d9ee7e0, 0x6d5e6016, 0xe7db8096, + 0x60166d9e, 0x80966d5e, 0x71966d1e, 0x60eae7d4, 0x2c00616c, 0x210fd10e, 0x184001c9, 0x22026c81, + 0x64814391, 0x61a82003, 0x28006a28, 0x6a29d002, 0x47882003, 0xbd70616c, 0x688db4f0, 0x4603680a, + 0x685c3380, 0x0f240724, 0x1b342608, 0xd90042ac, 0x2c00462c, 0x2c08d039, 0x2c01d018, 0x2c02d01a, + 0x2c03d01a, 0x2c04d01a, 0x2c05d01c, 0x2c06d01d, 0x2c07d01f, 0x6814d022, 0x6854619c, 0x2408619c, + 0x1b2d1912, 0x0724685c, 0xe7de0f24, 0x619f6817, 0xe0086857, 0xe0167817, 0xe00d8817, 0x615f8817, + 0xe0107897, 0x619f6817, 0x6817e7ea, 0x7917619f, 0x6817e009, 0x8897619f, 0xe7e1615f, 0x619f6817, + 0x615f8897, 0x611f7997, 0x60cae7da, 0x2d00614d, 0x220fd10f, 0x188001d2, 0x08526c82, 0x64820052, + 0x61882001, 0x280069c8, 0x69c9d003, 0x2001bcf0, 0xbcf04708, 0x60014770, 0x47702000, 0x60086800, + 0x47702000, 0x4cf7b510, 0xd01d2800, 0xd01b2900, 0xd0192b00, 0x220f625a, 0x188201d2, 0x089b6c93, + 0x6493009b, 0x7a0b780a, 0x079b07d2, 0x0c9b0fd2, 0x790b431a, 0x075b7b09, 0x07c90b5b, 0x09c9431a, + 0x6002430a, 0x24006800, 0xbd104620, 0x2103b510, 0x60010209, 0x46012400, 0x600c3180, 0x210f640c, + 0x184101c9, 0x2301648c, 0x02db4621, 0x181201ca, 0x601418d2, 0x1c496812, 0xd3f72904, 0x2900bd10, + 0xd0046801, 0x43112201, 0x68006001, 0x08494770, 0xe7f90049, 0x68094601, 0x07c92000, 0x2001d000, + 0x29014770, 0x2902d012, 0x2904d013, 0x2908d014, 0x2000d015, 0xd0082800, 0x23036801, 0x0792041b, + 0x0b924399, 0x60014311, 0x47706800, 0x02c92101, 0x2111e007, 0xe00401c9, 0x02092109, 0x2113e001, + 0x184001c9, 0xb5ffe7e6, 0x9f0eb083, 0x073f0792, 0x0d3f4605, 0x0b929b10, 0x9e0c2000, 0x6a5b433a, + 0x4604430a, 0x2e009300, 0x2100d009, 0x0c0907c9, 0x652a430a, 0x0789990d, 0x91010b89, 0x990fe019, + 0x6c68e7f4, 0x0f400740, 0xd20f2804, 0x9a011c61, 0xd20142b1, 0xe0002000, 0x07c0980f, 0x43020c00, + 0x5d009806, 0x43024338, 0xb2cc652a, 0xf0004668, 0x42b4fad3, 0x49a3d203, 0x42881e89, 0xb007d1e1, + 0xb5f0bdf0, 0x489f4605, 0x9c069e05, 0xd01e2a00, 0x1ec06c6f, 0x0f7f077f, 0xd2182f04, 0x23010798, + 0x049b0b80, 0x1e5318c0, 0x4318b29b, 0x29006528, 0x6021d00c, 0x60a26062, 0x200261e6, 0x200f61a0, + 0x182801c0, 0x22016c81, 0x64814311, 0xbdf02000, 0xb08cb570, 0x488b4604, 0x2a009e10, 0x6c65d028, + 0x076d1ec0, 0x2d040f6d, 0x0798d222, 0x0b802301, 0x18c0049b, 0xb29b1e53, 0x65204318, 0x29002000, + 0x6a73d016, 0x91019300, 0x21009203, 0x21029108, 0x4d7c9107, 0xe0061ead, 0x4620a901, 0xf9b4f000, + 0xf0004668, 0x9907fa79, 0xd1012902, 0xd1f342a8, 0xbd70b00c, 0x4605b5f0, 0x9e054872, 0x2a009c06, + 0x6c6fd01f, 0x077f1ec0, 0x2f040f7f, 0x0798d219, 0x0b802301, 0x18c004db, 0x039b1e53, 0x43180b9b, + 0x29006528, 0x60e1d00c, 0x61626122, 0x20046226, 0x200f61a0, 0x182801c0, 0x22026c81, 0x64814311, + 0xbdf02000, 0xb08cb570, 0x485e4604, 0x2a009e10, 0x6c65d0ce, 0x076d1ec0, 0x2d040f6d, 0x0798d2c8, + 0x0b802301, 0x18c004db, 0x039b1e53, 0x43180b9b, 0x20006520, 0xd0bb2900, 0x930a6a73, 0x92059103, + 0x91082100, 0x91062104, 0x1ead4d4e, 0x4669e006, 0xf0004620, 0xa80af9b8, 0xfa1ef000, 0x29049906, + 0x42a8d1a6, 0xe7a3d1f3, 0x48464602, 0x1ec06c53, 0x0f5b075b, 0xd2062b04, 0xb2881e49, 0x04892103, + 0x65101840, 0x47702000, 0x47706988, 0x600a2200, 0x608a604a, 0x610a60ca, 0x618a614a, 0x22016801, + 0x431107d2, 0x68006001, 0xb5ff4770, 0x4604b087, 0x4d349810, 0x00176a40, 0xd0489004, 0x07009808, + 0x2500d145, 0x34ff0918, 0x462e34ff, 0x90063402, 0x0130e03b, 0x90059908, 0x62201840, 0x08406820, + 0x60200040, 0x60202001, 0xa804e003, 0xf9d4f000, 0x68204605, 0xd00307c0, 0x1e804822, 0xd1f44285, + 0x1e804820, 0xd0224285, 0x22016e20, 0xf0004669, 0x6e60f9b9, 0xa9012201, 0xf9b4f000, 0x22016ea0, + 0xf000a902, 0x6ee0f9af, 0xa9032201, 0xf9aaf000, 0x99052000, 0x1809466b, 0x5c1b5c7a, 0x405a1c40, + 0x2810547a, 0x9806d3f5, 0x42b01c76, 0x4628d8c1, 0xbdf0b00b, 0x1dc22301, 0x32f907db, 0xd00c2901, + 0x308130ff, 0xd0042902, 0xd1052903, 0x43196811, 0x68016011, 0x60014319, 0x68104770, 0x60104318, + 0x00004770, 0x00b20004, 0x32f91dc2, 0xd00e2901, 0x308130ff, 0xd0052902, 0xd1f12903, 0x00496811, + 0x60110849, 0x00496801, 0x60010849, 0x6810e7e8, 0x08400040, 0xe7e36010, 0x1dc22301, 0x32f9079b, + 0xd00c2901, 0x308130ff, 0xd0042902, 0xd1d72903, 0x43196811, 0x68016011, 0x60014319, 0x6810e7d0, + 0x60104318, 0x2301e7cc, 0x079b1dc2, 0x290132f9, 0x30ffd00c, 0x29023081, 0x2903d004, 0x6811d1c0, + 0x60114399, 0x43996801, 0xe7b96001, 0x43986810, 0xe7b56010, 0x23011dc2, 0x290132f9, 0x30ffd00c, + 0x29023081, 0x2903d004, 0x6891d1aa, 0x60914319, 0x43196881, 0xe7a36081, 0x43186890, 0xe79f6090, + 0x6842b530, 0x78006881, 0x4c9c2300, 0xd0062801, 0xd0222802, 0xd0232804, 0xd1162808, 0x6988e01d, + 0x2804b2c0, 0x2000d00c, 0x0fcd6851, 0x46104305, 0xfde0f7ff, 0xd0012801, 0xd0032d00, 0xe0022001, + 0xe7f12001, 0x28002000, 0x4623d001, 0x6810e008, 0x08400040, 0x68106010, 0x4610e002, 0xfef6f7ff, + 0xbd304618, 0x6842b530, 0x78006881, 0x4c832300, 0xd0062801, 0xd0222802, 0xd0232804, 0xd1162808, + 0x6988e01d, 0x2804b2c0, 0x2000d00c, 0x0fcd6851, 0x46104305, 0xfdaef7ff, 0xd0012801, 0xd0032d00, + 0xe0022001, 0xe7f12001, 0x28002000, 0x4623d001, 0x6810e008, 0x08400040, 0x68106010, 0x4610e002, + 0xfec4f7ff, 0xbd304618, 0x688db4f0, 0x4603680a, 0x685c3380, 0x0f240724, 0x1b342608, 0xd90042ac, + 0x2c00462c, 0x2c08d039, 0x2c01d018, 0x2c02d01a, 0x2c03d01a, 0x2c04d01a, 0x2c05d01c, 0x2c06d01d, + 0x2c07d01f, 0x6814d022, 0x6854619c, 0x2408619c, 0x1b2d1912, 0x0724685c, 0xe7de0f24, 0x619f6817, + 0xe0086857, 0xe0167817, 0xe00d8817, 0x615f8817, 0xe0107897, 0x619f6817, 0x6817e7ea, 0x7917619f, + 0x6817e009, 0x8897619f, 0xe7e1615f, 0x619f6817, 0x615f8897, 0x611f7997, 0x60cae7da, 0x2d00614d, + 0x220fd10f, 0x188001d2, 0x08526c82, 0x64820052, 0x61882001, 0x280069c8, 0x69c9d003, 0x2001bcf0, + 0xbcf04708, 0xb5704770, 0x460d694c, 0x460368ca, 0x6c593380, 0x0f090709, 0xd90042a1, 0x29004621, + 0x2908d03b, 0x2901d015, 0x2902d018, 0x2903d019, 0x2904d01a, 0x2905d01d, 0x2906d01e, 0x2907d021, + 0x6d99d024, 0x6d996011, 0x21086051, 0x1a641852, 0x6d9ee7df, 0x6d9e6016, 0xe7f76056, 0x70166d1e, + 0x6d5ee7f4, 0xe7f18016, 0x80166d5e, 0x70966d1e, 0x6d9ee7ec, 0xe7e96016, 0x60166d9e, 0x71166d1e, + 0x6d9ee7e4, 0x6d5e6016, 0xe7df8096, 0x60166d9e, 0x80966d5e, 0x71966d1e, 0x60eae7d8, 0x2c00616c, + 0x210fd10e, 0x184001c9, 0x22026c81, 0x64814391, 0x61a82003, 0x28006a28, 0x6a29d002, 0x47882003, + 0xbd70616c, 0x70080a03, 0x2a00704b, 0x0c02d003, 0x0e00708a, 0xe67370c8, 0x4604b510, 0x20006821, + 0xd0072900, 0xf7fe2001, 0x6820fec0, 0x60201e40, 0x2000d001, 0x4802bd10, 0x0000bd10, 0x004200ff, + 0x00b20002, 0x698cb530, 0x68a368cd, 0x6a220a2d, 0x6085022d, 0x43ed690d, 0x0a2d1c6d, 0x60c5022d, + 0x69497824, 0x07a41e64, 0x29000fa4, 0x21ffd001, 0x430c3101, 0x681c6204, 0x1c6549fc, 0x791dd006, + 0x07adb2e4, 0x432c0bad, 0xe0001864, 0x64042400, 0x07a4795c, 0x64440ba4, 0x1c65689c, 0x7b1dd006, + 0x07adb2e4, 0x432c0bad, 0xe0001864, 0x64842400, 0x2c00691c, 0x1e64d003, 0x0ee406e4, 0x64c41864, + 0x079b7d1b, 0x65030b9b, 0x1c5c6813, 0x7914d006, 0x07a4b2db, 0x43230ba4, 0xe000185b, 0x66032300, + 0x079b7953, 0x66430b9b, 0x1c5c6893, 0x7b14d006, 0x07a4b2db, 0x43230ba4, 0xe000185b, 0x66832300, + 0x2b006913, 0x1e5bd004, 0x0edb06db, 0xe0001859, 0x66c12100, 0x07897d11, 0x67010b89, 0xb5ffbd30, + 0x2600b0c7, 0x460c9645, 0x9f506b4d, 0x99499a4a, 0xf7ff9847, 0x7969fc46, 0xaa029849, 0xc2c19101, + 0x90002003, 0x7829792a, 0x9847ab45, 0xfc5bf7ff, 0xd13f2800, 0x98476929, 0xfd46f7ff, 0xd1392800, + 0x96009701, 0x22ff7d2b, 0x9847a905, 0xfce2f7ff, 0xd12f2800, 0xe0086a7d, 0x2d002000, 0x2001d005, + 0xfe13f7fe, 0xd00d1e6d, 0x69b92000, 0xd0022903, 0x428849b7, 0x2800d1f0, 0x4669d11c, 0x29537d09, + 0xe015d002, 0xe7f048b2, 0x7d494669, 0xd10f2946, 0x7d894669, 0xd10b2944, 0x7dc94669, 0xd1072950, + 0x7e094669, 0xd3032906, 0x7e494669, 0xd0032901, 0x1cc048a7, 0xbdf0b04b, 0x780aa908, 0x4694ab05, + 0x46961c92, 0x68a15c9a, 0x0f920752, 0x2a01d004, 0x2a02d002, 0xe001d104, 0xe0002203, 0x60222204, + 0x08924662, 0x18d20092, 0x8c929200, 0x05d50553, 0x0f9b0717, 0x0f3f0eed, 0x2b002200, 0x2b01d006, + 0x2b02d006, 0x2b03d006, 0xe005d108, 0xe0052201, 0xe0032210, 0xe0012280, 0x00d2227d, 0x1c9b007b, + 0x461f1c6d, 0x436b4355, 0x9a006423, 0x005a6a93, 0x00da0f95, 0x92000ed2, 0x2d002200, 0x2d01d006, + 0x2d02d006, 0x2d03d007, 0xe007d10a, 0xe0072210, 0x320122ff, 0x227de004, 0xe0010152, 0x0252227d, + 0x1c6d9d00, 0x436f4355, 0x6467049a, 0x04da0fd7, 0x0ed2071d, 0x2f000f2d, 0x2340d017, 0x006d1c52, + 0x1cad435a, 0xaa054355, 0x64a54462, 0x79177955, 0x433d022d, 0x799379d7, 0x041b063f, 0x432f431f, + 0x1c7fd405, 0x606308fb, 0x2308e005, 0x4b67e7e6, 0x431f1eff, 0x46136067, 0x469c3320, 0x091f7a1b, + 0x461d2301, 0x626540bd, 0x40ab7f15, 0xab0561a3, 0x5d5b4675, 0x069f4d5f, 0x9f4ad512, 0xd00f2f01, + 0xd00d2f03, 0x600b7a53, 0x2302710e, 0x7a17714b, 0xd003097f, 0x608f275a, 0xe0137a17, 0xe7fb608d, + 0xd515065f, 0x2f019f4a, 0x2f03d012, 0x7ad3d010, 0x710e600b, 0x714b2302, 0x097f7a97, 0x275ad006, + 0x7a97608f, 0x0eff06ff, 0xe021610f, 0xe7f8608d, 0xd50d06df, 0x600b7bd3, 0x2301710e, 0x7b97714b, + 0xd003097f, 0x608f275a, 0xe7eb7b97, 0xe7fb608d, 0xd01107db, 0x600b7b53, 0x714e710e, 0x095b7b13, + 0x235ad008, 0x7b13608b, 0x0edb06db, 0x2301610b, 0xe008750b, 0xe7f6608d, 0x600b2303, 0x714e710e, + 0x608d610e, 0x68e3750e, 0x60192106, 0x270268e1, 0x6923710e, 0x60192104, 0x710e6921, 0x216069e3, + 0x69e16019, 0x7f51710e, 0x60116962, 0x22056961, 0x6961710e, 0x6a21714e, 0x6a21600f, 0x6a21710e, + 0x6a21714e, 0x6a21608d, 0x6a21610e, 0x2101750e, 0x6aa363a1, 0x6aa3601a, 0x6b23711e, 0x4663711e, + 0x065b7e9b, 0x00330f5e, 0xfa2cf000, 0x100b0506, 0x040b0b17, 0x63e5e6de, 0x600d6b21, 0x600d6ae1, + 0x63e7e6d8, 0x60116b22, 0xe00c2135, 0x63e32340, 0x60196b23, 0x600a6ae1, 0x2180e6cc, 0x6b2263e1, + 0x6011213e, 0x6ae2213f, 0xe6c36011, 0x4808b5f7, 0x1c80b084, 0x90012700, 0xd0642900, 0x90036808, + 0x90026848, 0x46062000, 0xe0539001, 0x80000000, 0x00b20002, 0xffffffff, 0x00b19802, 0x2c005844, + 0x7821d047, 0x29019804, 0x2902d022, 0x2904d023, 0x2908d024, 0x2500d025, 0xd0472d00, 0x21036828, + 0x43880409, 0x07897a21, 0x43080b89, 0x79206028, 0xd51a0740, 0x90009806, 0x78227a23, 0x980469a1, + 0xfe2df7ff, 0xd0102800, 0x40b02008, 0xe01f4307, 0x02c92101, 0x2111e007, 0xe00401c9, 0x02092109, + 0x2113e001, 0x184501c9, 0x7920e7d6, 0xd50f0780, 0x46284621, 0xfda6f7ff, 0x686021ff, 0x40083102, + 0x07897a21, 0x43080b89, 0x07c92101, 0x60281840, 0x1c766828, 0x42869803, 0x2f00d3ae, 0x2059d003, + 0x43070440, 0x98019701, 0xbdf0b007, 0x900148cc, 0xb510e7f3, 0x24012300, 0x02e4461a, 0x180901d9, + 0x600a1909, 0x60ca608a, 0x640a620a, 0x648a644a, 0x650a64ca, 0x664a660a, 0x66ca668a, 0x6809670a, + 0x2b041c5b, 0xbd10d3ea, 0x698bb530, 0xb085780d, 0x210068db, 0x91012401, 0x94039502, 0x91009204, + 0x7819791a, 0xf7ff2300, 0xb005fa3e, 0xb530bd30, 0x780d698b, 0x691bb085, 0x24012100, 0x95029101, + 0x92049403, 0x791a9100, 0x23007819, 0xfa2bf7ff, 0xb5f0e7eb, 0x4606b085, 0x20007809, 0x9c0a461f, + 0x90014615, 0x46039003, 0x91024602, 0x94049000, 0x46304639, 0xfa17f7ff, 0xd1062800, 0x22012300, + 0x46304629, 0xf7ff9400, 0xb005facd, 0xb51cbdf0, 0x466c2301, 0x698c7123, 0x6aa29200, 0xaa017813, + 0xffd7f7ff, 0xd1052800, 0x8f204669, 0x40087909, 0x71084669, 0x79004668, 0xd0002800, 0xbd1c2001, + 0xb085b5ff, 0x46179d0e, 0x460c461e, 0x9805462a, 0xff9af7ff, 0xd1112800, 0x6bc069a0, 0xd0002802, + 0x78212001, 0xac022201, 0x2300c426, 0x90009301, 0x2200463b, 0x98054631, 0xf9d5f7ff, 0xbdf0b009, + 0xb084b5f7, 0x90012000, 0x46149805, 0x6ae86985, 0x6b287807, 0x7800463b, 0x6aa89002, 0x92007806, + 0x9905aa01, 0xf7ff9804, 0x2800ff94, 0x6be8d109, 0x2802ad01, 0x2840d010, 0x2880d004, 0x4870d028, + 0xe7411e40, 0x79084669, 0x43082140, 0x71084669, 0x462a9400, 0xe02d9b02, 0x46339400, 0x9905462a, + 0xf7ff9804, 0x2800ff76, 0x9400d1eb, 0x1c6a463b, 0x98049905, 0xff6df7ff, 0xd1e22800, 0x79484669, + 0x43082102, 0x71484669, 0xaa019400, 0xe0119b02, 0x463b9400, 0x99051c6a, 0xf7ff9804, 0x2800ff5a, + 0x4669d1cf, 0x21807948, 0x46694308, 0x9b027148, 0x1c6a9400, 0x98049905, 0xff82f7ff, 0xb530e704, + 0x780d698b, 0x69dbb085, 0x24012100, 0x95029101, 0x92049403, 0x791a9100, 0x23007819, 0xf963f7ff, + 0xb5f0e723, 0xb0854c46, 0xd0102a00, 0x7809698d, 0x2701696c, 0x93047926, 0x96019703, 0x68299102, + 0x46139100, 0x46327821, 0xf94df7ff, 0x46204604, 0xb5ffe73b, 0x698db085, 0x9f0e4839, 0x6a2c9e10, + 0xd0282a00, 0x42bb6a6b, 0x6948d325, 0xd0232800, 0x7961b2c0, 0x93032300, 0x91019604, 0x68289002, + 0x79209000, 0x46024613, 0x98057821, 0xf92bf7ff, 0xd1102800, 0x29006921, 0x9805d004, 0xfa14f7ff, + 0xd1082800, 0x9000980f, 0x7d239601, 0x9908463a, 0xf7ff9805, 0xe741f956, 0xe7da7808, 0x698fb5ff, + 0x481fb085, 0x68bc9e10, 0xd0362a00, 0x28006948, 0xb2c5d034, 0x20007961, 0x95029604, 0x90039101, + 0x90006838, 0x46137920, 0x78214602, 0xf7ff9805, 0x2800f8fa, 0x6921d121, 0xd0042900, 0xf7ff9805, + 0x2800f9e3, 0x68a0d119, 0xd00d1c41, 0x91012100, 0x91009103, 0x95029604, 0x7d22b2c1, 0x98052300, + 0xf8e1f7ff, 0xd1082800, 0x9000980f, 0x7d239601, 0x99089a0e, 0xf7ff9805, 0xe6fff96d, 0xe7c9780d, + 0x00b20004, 0x4674b430, 0x78251e64, 0x42ab1c64, 0x461dd200, 0x005b5d63, 0xbc3018e3, 0x00004718, + 0x00000003, 0x00000000, 0x00000000, 0x00000068, 0x00000000, 0x00000000, 0x00000000, 0x00001212, + 0x00000000, 0x000000ff, 0x00000000, 0x00000000, 0x6eeee666, 0x00000000, 0x00000000, 0x00000000, + 0x11111111, 0x11111111, 0x0000001f, 0x00000000, 0x00000000, 0x0006eeee, 0x00000000, 0x00000000, + 0x00000000, 0x11111111, 0x00000011, 0x00000001, 0x00000000, 0x00000000, 0x0000000b, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000001, 0x00000001, + 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, + 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, + 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, + 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, + 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000000, 0x40420000, 0x00000000, + 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000007, 0x00000001, 0x00000000, 0x00000001, + 0x00000007, 0x00000001, 0x00000000 +}; + +static const program_target_t CY8C6xx7_flash_prog = + // Main Flash + { + .init = 0x08000021, // Init + .uninit = 0x08000027, // UnInit + .erase_chip = 0x0800002d, // EraseChip + .erase_sector = 0x08000035, // EraseSector + .program_page = 0x08000041, // ProgramPage + .verify = 0x08000055, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08000a14, + 0x08000d00 + }, + .program_buffer = 0x08000000 + 0x00000D00, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xx7_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xx7_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00000200, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; + +static const program_target_t CY8C6xxx_WFLASH_flash_prog = + // WFLASH (Work) + { + .init = 0x08000021, // Init + .uninit = 0x08000027, // UnInit + .erase_chip = 0x0800002d, // EraseChip + .erase_sector = 0x08000035, // EraseSector + .program_page = 0x08000041, // ProgramPage + .verify = 0x08000055, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08000a18, + 0x08000d00 + }, + .program_buffer = 0x08000000 + 0x00000D00, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxx_WFLASH_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxx_WFLASH_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00000200, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; + +static const program_target_t CY8C6xxx_SFLASH_USER_flash_prog = + // SFLASH: User Data + { + .init = 0x08000021, // Init + .uninit = 0x08000027, // UnInit + .erase_chip = 0x0800002d, // EraseChip + .erase_sector = 0x08000035, // EraseSector + .program_page = 0x08000041, // ProgramPage + .verify = 0x08000055, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08000a1c, + 0x08000d00 + }, + .program_buffer = 0x08000000 + 0x00000D00, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxx_SFLASH_USER_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxx_SFLASH_USER_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00000200, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; + +static const program_target_t CY8C6xxx_SFLASH_NAR_flash_prog = + // SFLASH: NAR + { + .init = 0x08000021, // Init + .uninit = 0x08000027, // UnInit + .erase_chip = 0x0800002d, // EraseChip + .erase_sector = 0x08000035, // EraseSector + .program_page = 0x08000041, // ProgramPage + .verify = 0x08000055, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08000a1c, + 0x08000d00 + }, + .program_buffer = 0x08000000 + 0x00000D00, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxx_SFLASH_NAR_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxx_SFLASH_NAR_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00000200, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; + +static const program_target_t CY8C6xxx_SFLASH_PKEY_flash_prog = + // SFLASH: Public Key + { + .init = 0x08000021, // Init + .uninit = 0x08000027, // UnInit + .erase_chip = 0x0800002d, // EraseChip + .erase_sector = 0x08000035, // EraseSector + .program_page = 0x08000041, // ProgramPage + .verify = 0x08000055, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08000a1c, + 0x08000d00 + }, + .program_buffer = 0x08000000 + 0x00000D00, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxx_SFLASH_PKEY_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxx_SFLASH_PKEY_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00000200, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; + +static const program_target_t CY8C6xxx_SFLASH_TOC2_flash_prog = + // SFLASH: TOC2 + { + .init = 0x08000021, // Init + .uninit = 0x08000027, // UnInit + .erase_chip = 0x0800002d, // EraseChip + .erase_sector = 0x08000035, // EraseSector + .program_page = 0x08000041, // ProgramPage + .verify = 0x08000055, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08000a1c, + 0x08000d00 + }, + .program_buffer = 0x08000000 + 0x00000D00, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxx_SFLASH_TOC2_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxx_SFLASH_TOC2_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00000200, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; + +static const program_target_t CY8C6xxx_SMIF_flash_prog = + // SMIF + { + .init = 0x08000069, // Init + .uninit = 0x08000081, // UnInit + .erase_chip = 0x0800008b, // EraseChip + .erase_sector = 0x08000093, // EraseSector + .program_page = 0x080000a7, // ProgramPage + .verify = 0x080000b3, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08001cf0, + 0x08004000 + }, + .program_buffer = 0x08000000 + 0x00004000, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxx_SMIF_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxx_SMIF_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00001000, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; + + diff --git a/source/family/cypress/PSoC6xxx/p6_sb_flash_blob.c b/source/family/cypress/PSoC6xxx/p6_sb_flash_blob.c new file mode 100644 index 0000000000..c4aae50ede --- /dev/null +++ b/source/family/cypress/PSoC6xxx/p6_sb_flash_blob.c @@ -0,0 +1,765 @@ +/******************************************************************************* +* @file p6_sb_flash_blob.c +* @brief Flash algorithm for the PSoC64 target MCU +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "flash_blob.h" + +// Main Flash algo + +static const uint32_t CY8C6xx7_sb_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x20004603, 0x46014770, 0x47702000, 0xf000b510, 0xbd10f972, 0x4604b510, 0xf0004620, 0xbd10f915, + 0x4606b570, 0x4615460c, 0x46294622, 0xf0004630, 0xbd70f969, 0x4604b570, 0x4616460d, 0x46294632, + 0xf0004620, 0xbd70f81f, 0x47706001, 0x600a6802, 0x21004770, 0x1c49e000, 0x43424ad6, 0xd8fa428a, + 0xb5084770, 0x48d44669, 0xfff0f7ff, 0x0209210f, 0x40089800, 0xd1012800, 0xe0002001, 0x46032000, + 0xbd084618, 0x4603b570, 0x461d460c, 0xe0052100, 0x5c6e5c50, 0xd00042b0, 0x1c49e002, 0xd3f742a1, + 0x1858bf00, 0xb5febd70, 0x460b4605, 0x20004616, 0x24009002, 0x01682700, 0x184049c0, 0xbf009000, + 0x9800a901, 0xf7ff3010, 0x9801ffc1, 0x2b000fc7, 0x2f00d001, 0x2b00d103, 0x2f00d103, 0x2001d101, + 0x2000e000, 0x2c004604, 0x9802d109, 0xd90042b0, 0x2001e007, 0xffadf7ff, 0x1c409802, 0x2c009002, + 0xbf00d0de, 0x21014620, 0xbdfe4048, 0x4604b5f8, 0x2600460d, 0x01602300, 0x184749a8, 0x4669bf00, + 0xf7ff4638, 0x9800ff93, 0x2b000fc3, 0x42aed106, 0xe005d900, 0xf7ff2001, 0x1c76ff8c, 0xd0ee2b00, + 0x4618bf00, 0x40482101, 0xb5f0bdf8, 0x460d4607, 0x26004613, 0xbf002400, 0x46384619, 0xff76f7ff, + 0x0f006818, 0x21050700, 0x42880749, 0x2001d101, 0x2000e000, 0x2c004604, 0x42aed106, 0xe005d900, + 0xf7ff2001, 0x1c76ff66, 0xd0e52c00, 0x4620bf00, 0x40482101, 0xb5f3bdf0, 0x4606b082, 0x48882700, + 0x90014478, 0x0fc007f0, 0x40482101, 0x25009000, 0xff57f7ff, 0xd0022800, 0x4d802400, 0x2401e002, + 0x35204d7e, 0x31f521ff, 0xf7ff4620, 0x4607ff9f, 0xd1362f00, 0x28009800, 0x4628d005, 0x9901300c, + 0xff32f7ff, 0x4631e004, 0x300c4628, 0xff2cf7ff, 0x30104620, 0x40822201, 0x48724611, 0xff24f7ff, + 0x46282101, 0xf7ff3008, 0x22ffff1f, 0x210032f5, 0xf7ff4620, 0x4607ff48, 0xd1122f00, 0x28009800, + 0x21ffd007, 0x9a0331f5, 0xf7ff9801, 0x4607ff8e, 0x21ffe007, 0x462831f5, 0x9a03300c, 0xff85f7ff, + 0x46384607, 0xbdf0b004, 0x4604b538, 0x447d4d5c, 0x495d3dae, 0xf7ff4628, 0x4621fef7, 0xf7ff1d28, + 0x4669fef3, 0xf7ff4858, 0xbd38ff96, 0x4604b538, 0x447d4d53, 0x49553dd2, 0xf7ff4628, 0x4621fee5, + 0xf7ff1d28, 0x4669fee1, 0xf7ff4850, 0xbd38ff84, 0x4604b538, 0x447d4d4a, 0x494c3df6, 0xf7ff4628, + 0x4621fed3, 0xf7ff1d28, 0x4669fecf, 0xf7ff4847, 0xbd38ff72, 0x4c46b518, 0x4946447c, 0xf7ff4620, + 0x4669fec3, 0xf7ff4843, 0xbd18ff66, 0x4606b570, 0x2500460c, 0x4630e00a, 0xffb6f7ff, 0x2d004605, + 0xe005d000, 0x36ff36ff, 0x1e643602, 0xd1f22c00, 0x4628bf00, 0xb510bd70, 0xf7ff2400, 0x4604ffdb, + 0xbd104620, 0x4605b5f8, 0x4617460e, 0x447c4c30, 0x49313c56, 0xf7ff4620, 0x21fffe97, 0x1d203107, + 0xfe92f7ff, 0x46204629, 0xf7ff3008, 0x4631fe8d, 0x300c4620, 0xfe88f7ff, 0x48274669, 0xff2bf7ff, + 0xb5f8bdf8, 0x460e4605, 0x4c214617, 0x3c94447c, 0x46204922, 0xfe78f7ff, 0x310721ff, 0xf7ff1d20, + 0x4629fe73, 0x30084620, 0xfe6ef7ff, 0x46204631, 0xf7ff300c, 0x4669fe69, 0xf7ff4818, 0xbdf8ff0c, + 0xb0ffb570, 0x4605b081, 0x24002600, 0x2000e003, 0x55084669, 0x20011c64, 0x42840240, 0x4602dbf7, + 0x46284669, 0xffcdf7ff, 0x46304606, 0xb001b07f, 0x0000bd70, 0x00000d05, 0x40210400, 0x40230000, + 0x0000023c, 0x40231008, 0x1c000100, 0x14000100, 0x00000124, 0x0a000100, 0x06000100, 0x05000100, + 0x00000000 +}; + +// WFLASH (Work) algo +static const uint32_t CY8C6xxx_sb_WFLASH_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x20004603, 0x46014770, 0x47702000, 0xf000b510, 0xbd10f972, 0x4604b510, 0xf0004620, 0xbd10f915, + 0x4606b570, 0x4615460c, 0x46294622, 0xf0004630, 0xbd70f96c, 0x4604b570, 0x4616460d, 0x46294632, + 0xf0004620, 0xbd70f81f, 0x47706001, 0x600a6802, 0x21004770, 0x1c49e000, 0x43424ad7, 0xd8fa428a, + 0xb5084770, 0x48d54669, 0xfff0f7ff, 0x0209210f, 0x40089800, 0xd1012800, 0xe0002001, 0x46032000, + 0xbd084618, 0x4603b570, 0x461d460c, 0xe0052100, 0x5c6e5c50, 0xd00042b0, 0x1c49e002, 0xd3f742a1, + 0x1858bf00, 0xb5febd70, 0x460b4605, 0x20004616, 0x24009002, 0x01682700, 0x184049c1, 0xbf009000, + 0x9800a901, 0xf7ff3010, 0x9801ffc1, 0x2b000fc7, 0x2f00d001, 0x2b00d103, 0x2f00d103, 0x2001d101, + 0x2000e000, 0x2c004604, 0x9802d109, 0xd90042b0, 0x2001e007, 0xffadf7ff, 0x1c409802, 0x2c009002, + 0xbf00d0de, 0x21014620, 0xbdfe4048, 0x4604b5f8, 0x2600460d, 0x01602300, 0x184749a9, 0x4669bf00, + 0xf7ff4638, 0x9800ff93, 0x2b000fc3, 0x42aed106, 0xe005d900, 0xf7ff2001, 0x1c76ff8c, 0xd0ee2b00, + 0x4618bf00, 0x40482101, 0xb5f0bdf8, 0x460d4607, 0x26004613, 0xbf002400, 0x46384619, 0xff76f7ff, + 0x0f006818, 0x21050700, 0x42880749, 0x2001d101, 0x2000e000, 0x2c004604, 0x42aed106, 0xe005d900, + 0xf7ff2001, 0x1c76ff66, 0xd0e52c00, 0x4620bf00, 0x40482101, 0xb5f3bdf0, 0x4606b082, 0x48892700, + 0x90014478, 0x0fc007f0, 0x40482101, 0x25009000, 0xff57f7ff, 0xd0022800, 0x4d812400, 0x2401e002, + 0x35204d7f, 0x31f521ff, 0xf7ff4620, 0x4607ff9f, 0xd1362f00, 0x28009800, 0x4628d005, 0x9901300c, + 0xff32f7ff, 0x4631e004, 0x300c4628, 0xff2cf7ff, 0x30104620, 0x40822201, 0x48734611, 0xff24f7ff, + 0x46282101, 0xf7ff3008, 0x22ffff1f, 0x210032f5, 0xf7ff4620, 0x4607ff48, 0xd1122f00, 0x28009800, + 0x21ffd007, 0x9a0331f5, 0xf7ff9801, 0x4607ff8e, 0x21ffe007, 0x462831f5, 0x9a03300c, 0xff85f7ff, + 0x46384607, 0xbdf0b004, 0x4604b538, 0x447d4d5d, 0x495e3dae, 0xf7ff4628, 0x4621fef7, 0xf7ff1d28, + 0x4669fef3, 0xf7ff4859, 0xbd38ff96, 0x4604b538, 0x447d4d54, 0x49563dd2, 0xf7ff4628, 0x4621fee5, + 0xf7ff1d28, 0x4669fee1, 0xf7ff4851, 0xbd38ff84, 0x4604b538, 0x447d4d4b, 0x494d3df6, 0xf7ff4628, + 0x4621fed3, 0xf7ff1d28, 0x4669fecf, 0xf7ff4848, 0xbd38ff72, 0x4c47b518, 0x4947447c, 0xf7ff4620, + 0x4669fec3, 0xf7ff4844, 0xbd18ff66, 0x4606b570, 0x2500460c, 0x4630e00a, 0xffb6f7ff, 0x2d004605, + 0xe005d000, 0x36ff36ff, 0x1e643602, 0xd1f22c00, 0x4628bf00, 0xb510bd70, 0x21402400, 0x06802005, + 0xffe4f7ff, 0x46204604, 0xb5f8bd10, 0x460e4605, 0x4c304617, 0x3c5c447c, 0x46204930, 0xfe94f7ff, + 0x310721ff, 0xf7ff1d20, 0x4629fe8f, 0x30084620, 0xfe8af7ff, 0x46204631, 0xf7ff300c, 0x4669fe85, + 0xf7ff4826, 0xbdf8ff28, 0x4605b5f8, 0x4617460e, 0x447c4c20, 0x49223c9a, 0xf7ff4620, 0x21fffe75, + 0x1d203107, 0xfe70f7ff, 0x46204629, 0xf7ff3008, 0x4631fe6b, 0x300c4620, 0xfe66f7ff, 0x48184669, + 0xff09f7ff, 0xb570bdf8, 0xb081b0ff, 0x26004605, 0xe0032400, 0x46692000, 0x1c645508, 0x02402001, + 0xdbf74284, 0x46694602, 0xf7ff4628, 0x4606ffcd, 0xb07f4630, 0xbd70b001, 0x00000d05, 0x40210400, + 0x40230000, 0x00000240, 0x40231008, 0x1c000100, 0x14000100, 0x00000128, 0x0a000100, 0x06000100, + 0x05000100, 0x00000000 +}; + +// SFLASH: User Data algo +static const uint32_t CY8C6xxx_sb_SFLASH_USER_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x20004603, 0x46014770, 0x47702000, 0xf000b510, 0xbd10f9aa, 0x4604b510, 0xf0004620, 0xbd10f976, + 0x4606b570, 0x4615460c, 0x46294622, 0xf0004630, 0xbd70f94d, 0x4604b570, 0x4616460d, 0x46294632, + 0xf0004620, 0xbd70f81f, 0x47706001, 0x600a6802, 0x21004770, 0x1c49e000, 0x43424ad7, 0xd8fa428a, + 0xb5084770, 0x48d54669, 0xfff0f7ff, 0x0209210f, 0x40089800, 0xd1012800, 0xe0002001, 0x46032000, + 0xbd084618, 0x4603b570, 0x461d460c, 0xe0052100, 0x5c6e5c50, 0xd00042b0, 0x1c49e002, 0xd3f742a1, + 0x1858bf00, 0xb5febd70, 0x460b4605, 0x20004616, 0x24009002, 0x01682700, 0x184049c1, 0xbf009000, + 0x9800a901, 0xf7ff3010, 0x9801ffc1, 0x2b000fc7, 0x2f00d001, 0x2b00d103, 0x2f00d103, 0x2001d101, + 0x2000e000, 0x2c004604, 0x9802d109, 0xd90042b0, 0x2001e007, 0xffadf7ff, 0x1c409802, 0x2c009002, + 0xbf00d0de, 0x21014620, 0xbdfe4048, 0x4604b5f8, 0x2600460d, 0x01602300, 0x184749a9, 0x4669bf00, + 0xf7ff4638, 0x9800ff93, 0x2b000fc3, 0x42aed106, 0xe005d900, 0xf7ff2001, 0x1c76ff8c, 0xd0ee2b00, + 0x4618bf00, 0x40482101, 0xb5f0bdf8, 0x460d4607, 0x26004613, 0xbf002400, 0x46384619, 0xff76f7ff, + 0x0f006818, 0x21050700, 0x42880749, 0x2001d101, 0x2000e000, 0x2c004604, 0x42aed106, 0xe005d900, + 0xf7ff2001, 0x1c76ff66, 0xd0e52c00, 0x4620bf00, 0x40482101, 0xb5f3bdf0, 0x4606b082, 0x48892700, + 0x90014478, 0x0fc007f0, 0x40482101, 0x25009000, 0xff57f7ff, 0xd0022800, 0x4d812400, 0x2401e002, + 0x35204d7f, 0x31f521ff, 0xf7ff4620, 0x4607ff9f, 0xd1362f00, 0x28009800, 0x4628d005, 0x9901300c, + 0xff32f7ff, 0x4631e004, 0x300c4628, 0xff2cf7ff, 0x30104620, 0x40822201, 0x48734611, 0xff24f7ff, + 0x46282101, 0xf7ff3008, 0x22ffff1f, 0x210032f5, 0xf7ff4620, 0x4607ff48, 0xd1122f00, 0x28009800, + 0x21ffd007, 0x9a0331f5, 0xf7ff9801, 0x4607ff8e, 0x21ffe007, 0x462831f5, 0x9a03300c, 0xff85f7ff, + 0x46384607, 0xbdf0b004, 0x4604b538, 0x447d4d5d, 0x495e3dae, 0xf7ff4628, 0x4621fef7, 0xf7ff1d28, + 0x4669fef3, 0xf7ff4859, 0xbd38ff96, 0x4604b538, 0x447d4d54, 0x49563dd2, 0xf7ff4628, 0x4621fee5, + 0xf7ff1d28, 0x4669fee1, 0xf7ff4851, 0xbd38ff84, 0x4604b538, 0x447d4d4b, 0x494d3df6, 0xf7ff4628, + 0x4621fed3, 0xf7ff1d28, 0x4669fecf, 0xf7ff4848, 0xbd38ff72, 0x4c47b518, 0x4947447c, 0xf7ff4620, + 0x4669fec3, 0xf7ff4844, 0xbd18ff66, 0x4605b5f8, 0x4617460e, 0x447c4c3f, 0x49403c1e, 0xf7ff4620, + 0x21fffeb3, 0x1d203107, 0xfeaef7ff, 0x46204629, 0xf7ff3008, 0x4631fea9, 0x300c4620, 0xfea4f7ff, + 0x48364669, 0xff47f7ff, 0xb570bdf8, 0xb081b0ff, 0x26004605, 0xe0032400, 0x46692000, 0x1c645508, + 0x02402001, 0xdbf74284, 0x46694602, 0xf7ff4628, 0x4606ffcd, 0xb07f4630, 0xbd70b001, 0x4606b570, + 0x2500460c, 0x4630e00a, 0xffdff7ff, 0x2d004605, 0xe005d000, 0x36ff36ff, 0x1e643602, 0xd1f22c00, + 0x4628bf00, 0xb510bd70, 0x21042400, 0xf7ff481c, 0x4604ffe5, 0xbd104620, 0x4605b5f8, 0x4617460e, + 0x447c4c14, 0x49173cca, 0xf7ff4620, 0x21fffe5d, 0x1d203107, 0xfe58f7ff, 0x46204629, 0xf7ff3008, + 0x4631fe53, 0x300c4620, 0xfe4ef7ff, 0x480d4669, 0xfef1f7ff, 0x0000bdf8, 0x00000d05, 0x40210400, + 0x40230000, 0x00000244, 0x40231008, 0x1c000100, 0x14000100, 0x0000012c, 0x0a000100, 0x05000100, + 0x16000800, 0x06000100, 0x00000000 +}; + +// SFLASH: NAR algo +static const uint32_t CY8C6xxx_sb_SFLASH_NAR_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x20004603, 0x46014770, 0x47702000, 0xf000b510, 0xbd10f9aa, 0x4604b510, 0xf0004620, 0xbd10f976, + 0x4606b570, 0x4615460c, 0x46294622, 0xf0004630, 0xbd70f94d, 0x4604b570, 0x4616460d, 0x46294632, + 0xf0004620, 0xbd70f81f, 0x47706001, 0x600a6802, 0x21004770, 0x1c49e000, 0x43424ad7, 0xd8fa428a, + 0xb5084770, 0x48d54669, 0xfff0f7ff, 0x0209210f, 0x40089800, 0xd1012800, 0xe0002001, 0x46032000, + 0xbd084618, 0x4603b570, 0x461d460c, 0xe0052100, 0x5c6e5c50, 0xd00042b0, 0x1c49e002, 0xd3f742a1, + 0x1858bf00, 0xb5febd70, 0x460b4605, 0x20004616, 0x24009002, 0x01682700, 0x184049c1, 0xbf009000, + 0x9800a901, 0xf7ff3010, 0x9801ffc1, 0x2b000fc7, 0x2f00d001, 0x2b00d103, 0x2f00d103, 0x2001d101, + 0x2000e000, 0x2c004604, 0x9802d109, 0xd90042b0, 0x2001e007, 0xffadf7ff, 0x1c409802, 0x2c009002, + 0xbf00d0de, 0x21014620, 0xbdfe4048, 0x4604b5f8, 0x2600460d, 0x01602300, 0x184749a9, 0x4669bf00, + 0xf7ff4638, 0x9800ff93, 0x2b000fc3, 0x42aed106, 0xe005d900, 0xf7ff2001, 0x1c76ff8c, 0xd0ee2b00, + 0x4618bf00, 0x40482101, 0xb5f0bdf8, 0x460d4607, 0x26004613, 0xbf002400, 0x46384619, 0xff76f7ff, + 0x0f006818, 0x21050700, 0x42880749, 0x2001d101, 0x2000e000, 0x2c004604, 0x42aed106, 0xe005d900, + 0xf7ff2001, 0x1c76ff66, 0xd0e52c00, 0x4620bf00, 0x40482101, 0xb5f3bdf0, 0x4606b082, 0x48892700, + 0x90014478, 0x0fc007f0, 0x40482101, 0x25009000, 0xff57f7ff, 0xd0022800, 0x4d812400, 0x2401e002, + 0x35204d7f, 0x31f521ff, 0xf7ff4620, 0x4607ff9f, 0xd1362f00, 0x28009800, 0x4628d005, 0x9901300c, + 0xff32f7ff, 0x4631e004, 0x300c4628, 0xff2cf7ff, 0x30104620, 0x40822201, 0x48734611, 0xff24f7ff, + 0x46282101, 0xf7ff3008, 0x22ffff1f, 0x210032f5, 0xf7ff4620, 0x4607ff48, 0xd1122f00, 0x28009800, + 0x21ffd007, 0x9a0331f5, 0xf7ff9801, 0x4607ff8e, 0x21ffe007, 0x462831f5, 0x9a03300c, 0xff85f7ff, + 0x46384607, 0xbdf0b004, 0x4604b538, 0x447d4d5d, 0x495e3dae, 0xf7ff4628, 0x4621fef7, 0xf7ff1d28, + 0x4669fef3, 0xf7ff4859, 0xbd38ff96, 0x4604b538, 0x447d4d54, 0x49563dd2, 0xf7ff4628, 0x4621fee5, + 0xf7ff1d28, 0x4669fee1, 0xf7ff4851, 0xbd38ff84, 0x4604b538, 0x447d4d4b, 0x494d3df6, 0xf7ff4628, + 0x4621fed3, 0xf7ff1d28, 0x4669fecf, 0xf7ff4848, 0xbd38ff72, 0x4c47b518, 0x4947447c, 0xf7ff4620, + 0x4669fec3, 0xf7ff4844, 0xbd18ff66, 0x4605b5f8, 0x4617460e, 0x447c4c3f, 0x49403c1e, 0xf7ff4620, + 0x21fffeb3, 0x1d203107, 0xfeaef7ff, 0x46204629, 0xf7ff3008, 0x4631fea9, 0x300c4620, 0xfea4f7ff, + 0x48364669, 0xff47f7ff, 0xb570bdf8, 0xb081b0ff, 0x26004605, 0xe0032400, 0x46692000, 0x1c645508, + 0x02402001, 0xdbf74284, 0x46694602, 0xf7ff4628, 0x4606ffcd, 0xb07f4630, 0xbd70b001, 0x4606b570, + 0x2500460c, 0x4630e00a, 0xffdff7ff, 0x2d004605, 0xe005d000, 0x36ff36ff, 0x1e643602, 0xd1f22c00, + 0x4628bf00, 0xb510bd70, 0x21012400, 0xf7ff481c, 0x4604ffe5, 0xbd104620, 0x4605b5f8, 0x4617460e, + 0x447c4c14, 0x49173cca, 0xf7ff4620, 0x21fffe5d, 0x1d203107, 0xfe58f7ff, 0x46204629, 0xf7ff3008, + 0x4631fe53, 0x300c4620, 0xfe4ef7ff, 0x480d4669, 0xfef1f7ff, 0x0000bdf8, 0x00000d05, 0x40210400, + 0x40230000, 0x00000244, 0x40231008, 0x1c000100, 0x14000100, 0x0000012c, 0x0a000100, 0x05000100, + 0x16001a00, 0x06000100, 0x00000000 +}; + +// SFLASH: Public Key algo +static const uint32_t CY8C6xxx_sb_SFLASH_PKEY_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x20004603, 0x46014770, 0x47702000, 0xf000b510, 0xbd10f9aa, 0x4604b510, 0xf0004620, 0xbd10f976, + 0x4606b570, 0x4615460c, 0x46294622, 0xf0004630, 0xbd70f94d, 0x4604b570, 0x4616460d, 0x46294632, + 0xf0004620, 0xbd70f81f, 0x47706001, 0x600a6802, 0x21004770, 0x1c49e000, 0x43424ad7, 0xd8fa428a, + 0xb5084770, 0x48d54669, 0xfff0f7ff, 0x0209210f, 0x40089800, 0xd1012800, 0xe0002001, 0x46032000, + 0xbd084618, 0x4603b570, 0x461d460c, 0xe0052100, 0x5c6e5c50, 0xd00042b0, 0x1c49e002, 0xd3f742a1, + 0x1858bf00, 0xb5febd70, 0x460b4605, 0x20004616, 0x24009002, 0x01682700, 0x184049c1, 0xbf009000, + 0x9800a901, 0xf7ff3010, 0x9801ffc1, 0x2b000fc7, 0x2f00d001, 0x2b00d103, 0x2f00d103, 0x2001d101, + 0x2000e000, 0x2c004604, 0x9802d109, 0xd90042b0, 0x2001e007, 0xffadf7ff, 0x1c409802, 0x2c009002, + 0xbf00d0de, 0x21014620, 0xbdfe4048, 0x4604b5f8, 0x2600460d, 0x01602300, 0x184749a9, 0x4669bf00, + 0xf7ff4638, 0x9800ff93, 0x2b000fc3, 0x42aed106, 0xe005d900, 0xf7ff2001, 0x1c76ff8c, 0xd0ee2b00, + 0x4618bf00, 0x40482101, 0xb5f0bdf8, 0x460d4607, 0x26004613, 0xbf002400, 0x46384619, 0xff76f7ff, + 0x0f006818, 0x21050700, 0x42880749, 0x2001d101, 0x2000e000, 0x2c004604, 0x42aed106, 0xe005d900, + 0xf7ff2001, 0x1c76ff66, 0xd0e52c00, 0x4620bf00, 0x40482101, 0xb5f3bdf0, 0x4606b082, 0x48892700, + 0x90014478, 0x0fc007f0, 0x40482101, 0x25009000, 0xff57f7ff, 0xd0022800, 0x4d812400, 0x2401e002, + 0x35204d7f, 0x31f521ff, 0xf7ff4620, 0x4607ff9f, 0xd1362f00, 0x28009800, 0x4628d005, 0x9901300c, + 0xff32f7ff, 0x4631e004, 0x300c4628, 0xff2cf7ff, 0x30104620, 0x40822201, 0x48734611, 0xff24f7ff, + 0x46282101, 0xf7ff3008, 0x22ffff1f, 0x210032f5, 0xf7ff4620, 0x4607ff48, 0xd1122f00, 0x28009800, + 0x21ffd007, 0x9a0331f5, 0xf7ff9801, 0x4607ff8e, 0x21ffe007, 0x462831f5, 0x9a03300c, 0xff85f7ff, + 0x46384607, 0xbdf0b004, 0x4604b538, 0x447d4d5d, 0x495e3dae, 0xf7ff4628, 0x4621fef7, 0xf7ff1d28, + 0x4669fef3, 0xf7ff4859, 0xbd38ff96, 0x4604b538, 0x447d4d54, 0x49563dd2, 0xf7ff4628, 0x4621fee5, + 0xf7ff1d28, 0x4669fee1, 0xf7ff4851, 0xbd38ff84, 0x4604b538, 0x447d4d4b, 0x494d3df6, 0xf7ff4628, + 0x4621fed3, 0xf7ff1d28, 0x4669fecf, 0xf7ff4848, 0xbd38ff72, 0x4c47b518, 0x4947447c, 0xf7ff4620, + 0x4669fec3, 0xf7ff4844, 0xbd18ff66, 0x4605b5f8, 0x4617460e, 0x447c4c3f, 0x49403c1e, 0xf7ff4620, + 0x21fffeb3, 0x1d203107, 0xfeaef7ff, 0x46204629, 0xf7ff3008, 0x4631fea9, 0x300c4620, 0xfea4f7ff, + 0x48364669, 0xff47f7ff, 0xb570bdf8, 0xb081b0ff, 0x26004605, 0xe0032400, 0x46692000, 0x1c645508, + 0x02402001, 0xdbf74284, 0x46694602, 0xf7ff4628, 0x4606ffcd, 0xb07f4630, 0xbd70b001, 0x4606b570, + 0x2500460c, 0x4630e00a, 0xffdff7ff, 0x2d004605, 0xe005d000, 0x36ff36ff, 0x1e643602, 0xd1f22c00, + 0x4628bf00, 0xb510bd70, 0x21062400, 0xf7ff481c, 0x4604ffe5, 0xbd104620, 0x4605b5f8, 0x4617460e, + 0x447c4c14, 0x49173cca, 0xf7ff4620, 0x21fffe5d, 0x1d203107, 0xfe58f7ff, 0x46204629, 0xf7ff3008, + 0x4631fe53, 0x300c4620, 0xfe4ef7ff, 0x480d4669, 0xfef1f7ff, 0x0000bdf8, 0x00000d05, 0x40210400, + 0x40230000, 0x00000244, 0x40231008, 0x1c000100, 0x14000100, 0x0000012c, 0x0a000100, 0x05000100, + 0x16005a00, 0x06000100, 0x00000000 +}; + +// SFLASH: TOC2 algo +static const uint32_t CY8C6xxx_sb_SFLASH_TOC2_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x20004603, 0x46014770, 0x47702000, 0xf000b510, 0xbd10f9aa, 0x4604b510, 0xf0004620, 0xbd10f976, + 0x4606b570, 0x4615460c, 0x46294622, 0xf0004630, 0xbd70f94d, 0x4604b570, 0x4616460d, 0x46294632, + 0xf0004620, 0xbd70f81f, 0x47706001, 0x600a6802, 0x21004770, 0x1c49e000, 0x43424ad7, 0xd8fa428a, + 0xb5084770, 0x48d54669, 0xfff0f7ff, 0x0209210f, 0x40089800, 0xd1012800, 0xe0002001, 0x46032000, + 0xbd084618, 0x4603b570, 0x461d460c, 0xe0052100, 0x5c6e5c50, 0xd00042b0, 0x1c49e002, 0xd3f742a1, + 0x1858bf00, 0xb5febd70, 0x460b4605, 0x20004616, 0x24009002, 0x01682700, 0x184049c1, 0xbf009000, + 0x9800a901, 0xf7ff3010, 0x9801ffc1, 0x2b000fc7, 0x2f00d001, 0x2b00d103, 0x2f00d103, 0x2001d101, + 0x2000e000, 0x2c004604, 0x9802d109, 0xd90042b0, 0x2001e007, 0xffadf7ff, 0x1c409802, 0x2c009002, + 0xbf00d0de, 0x21014620, 0xbdfe4048, 0x4604b5f8, 0x2600460d, 0x01602300, 0x184749a9, 0x4669bf00, + 0xf7ff4638, 0x9800ff93, 0x2b000fc3, 0x42aed106, 0xe005d900, 0xf7ff2001, 0x1c76ff8c, 0xd0ee2b00, + 0x4618bf00, 0x40482101, 0xb5f0bdf8, 0x460d4607, 0x26004613, 0xbf002400, 0x46384619, 0xff76f7ff, + 0x0f006818, 0x21050700, 0x42880749, 0x2001d101, 0x2000e000, 0x2c004604, 0x42aed106, 0xe005d900, + 0xf7ff2001, 0x1c76ff66, 0xd0e52c00, 0x4620bf00, 0x40482101, 0xb5f3bdf0, 0x4606b082, 0x48892700, + 0x90014478, 0x0fc007f0, 0x40482101, 0x25009000, 0xff57f7ff, 0xd0022800, 0x4d812400, 0x2401e002, + 0x35204d7f, 0x31f521ff, 0xf7ff4620, 0x4607ff9f, 0xd1362f00, 0x28009800, 0x4628d005, 0x9901300c, + 0xff32f7ff, 0x4631e004, 0x300c4628, 0xff2cf7ff, 0x30104620, 0x40822201, 0x48734611, 0xff24f7ff, + 0x46282101, 0xf7ff3008, 0x22ffff1f, 0x210032f5, 0xf7ff4620, 0x4607ff48, 0xd1122f00, 0x28009800, + 0x21ffd007, 0x9a0331f5, 0xf7ff9801, 0x4607ff8e, 0x21ffe007, 0x462831f5, 0x9a03300c, 0xff85f7ff, + 0x46384607, 0xbdf0b004, 0x4604b538, 0x447d4d5d, 0x495e3dae, 0xf7ff4628, 0x4621fef7, 0xf7ff1d28, + 0x4669fef3, 0xf7ff4859, 0xbd38ff96, 0x4604b538, 0x447d4d54, 0x49563dd2, 0xf7ff4628, 0x4621fee5, + 0xf7ff1d28, 0x4669fee1, 0xf7ff4851, 0xbd38ff84, 0x4604b538, 0x447d4d4b, 0x494d3df6, 0xf7ff4628, + 0x4621fed3, 0xf7ff1d28, 0x4669fecf, 0xf7ff4848, 0xbd38ff72, 0x4c47b518, 0x4947447c, 0xf7ff4620, + 0x4669fec3, 0xf7ff4844, 0xbd18ff66, 0x4605b5f8, 0x4617460e, 0x447c4c3f, 0x49403c1e, 0xf7ff4620, + 0x21fffeb3, 0x1d203107, 0xfeaef7ff, 0x46204629, 0xf7ff3008, 0x4631fea9, 0x300c4620, 0xfea4f7ff, + 0x48364669, 0xff47f7ff, 0xb570bdf8, 0xb081b0ff, 0x26004605, 0xe0032400, 0x46692000, 0x1c645508, + 0x02402001, 0xdbf74284, 0x46694602, 0xf7ff4628, 0x4606ffcd, 0xb07f4630, 0xbd70b001, 0x4606b570, + 0x2500460c, 0x4630e00a, 0xffdff7ff, 0x2d004605, 0xe005d000, 0x36ff36ff, 0x1e643602, 0xd1f22c00, + 0x4628bf00, 0xb510bd70, 0x21022400, 0xf7ff481c, 0x4604ffe5, 0xbd104620, 0x4605b5f8, 0x4617460e, + 0x447c4c14, 0x49173cca, 0xf7ff4620, 0x21fffe5d, 0x1d203107, 0xfe58f7ff, 0x46204629, 0xf7ff3008, + 0x4631fe53, 0x300c4620, 0xfe4ef7ff, 0x480d4669, 0xfef1f7ff, 0x0000bdf8, 0x00000d05, 0x40210400, + 0x40230000, 0x00000244, 0x40231008, 0x1c000100, 0x14000100, 0x0000012c, 0x0a000100, 0x05000100, + 0x16007c00, 0x06000100, 0x00000000 +}; + + //SMIF algo +static const uint32_t CY8C6xxx_sb_SMIF_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x08801c80, 0x1c40d003, 0xd1fc1e80, 0x4770bf00, 0x4605b570, 0x4616460c, 0xcc0fe002, 0x3e10c50f, + 0xd2fa2e10, 0xd3022e08, 0xc503cc03, 0x2e043e08, 0xcc01d307, 0x1f36c501, 0x7821e003, 0x1c647029, + 0x1e761c6d, 0xbd70d2f9, 0x4604b5f8, 0x4617460e, 0x46202500, 0xff8cf000, 0x46284605, 0xb570bdf8, + 0x24004605, 0xffa2f000, 0x46204604, 0xb510bd70, 0xf0002400, 0x4604fd5b, 0xbd104620, 0x4604b570, + 0x21012500, 0x46200409, 0xfbf6f000, 0x46284605, 0xb570bd70, 0x460d4604, 0x46204629, 0xfbecf000, + 0x46304606, 0xb5f8bd70, 0x460c4605, 0x27004616, 0x46324623, 0x46282100, 0xfd7df000, 0x46384607, + 0xb5f8bdf8, 0x460e4604, 0x46254617, 0x463a466b, 0x46204631, 0xfecdf000, 0x2d004605, 0x9d00d100, + 0xbdf84628, 0x4604b5f8, 0x4616460d, 0x46322700, 0x46204629, 0xff30f000, 0x46384607, 0xb530bdf8, + 0x460b4602, 0x46142000, 0xe0022100, 0x18285c65, 0x42991c49, 0xbd30d3fa, 0x47706001, 0x600a6802, + 0x21004770, 0x1c49e000, 0x43424a02, 0xd8fa428a, 0x00004770, 0x00000d05, 0x4669b538, 0xf7ff4807, + 0x210fffed, 0x98000209, 0x28004008, 0x2001d101, 0x2000e000, 0x46204604, 0x0000bd38, 0x40210400, + 0xb085b5f0, 0x460c4606, 0x20004617, 0x25009003, 0x49670170, 0x90011840, 0x2000bf00, 0xa9029000, + 0x30109801, 0xffcaf7ff, 0x0fc09802, 0x2c009000, 0x9800d002, 0xd1042800, 0xd1042c00, 0x28009800, + 0x2001d101, 0x2000e000, 0x2d004605, 0x9803d109, 0xd90042b8, 0x2001e007, 0xffb3f7ff, 0x1c409803, + 0x2d009003, 0xbf00d0d9, 0x21014628, 0xb0054048, 0xb5febdf0, 0x460e4605, 0x24002700, 0x494c0168, + 0x90011840, 0x4669bf00, 0xf7ff9801, 0x9800ff97, 0x2c000fc4, 0x42b7d106, 0xe005d900, 0xf7ff2001, + 0x1c7fff90, 0xd0ee2c00, 0x4620bf00, 0x40482101, 0xb5f7bdfe, 0x4614460e, 0x25002700, 0x4621bf00, + 0xf7ff9800, 0x6820ff7b, 0x07000f00, 0x07492105, 0xd1014288, 0xe0002001, 0x46052000, 0xd1062d00, + 0xd90042b7, 0x2001e005, 0xff6bf7ff, 0x2d001c7f, 0xbf00d0e5, 0x21014628, 0xbdfe4048, 0xb083b5f3, + 0x27004606, 0x4478482b, 0x07f09002, 0x21010fc0, 0x90014048, 0xf7ff2500, 0x2800ff5f, 0x2400d002, + 0xe0024d23, 0x4d222401, 0x21ff3520, 0x462031f5, 0xff9ff7ff, 0x2f004607, 0x9801d136, 0xd0052800, + 0x300c4628, 0xf7ff9902, 0xe004ff37, 0x46284631, 0xf7ff300c, 0x4620ff31, 0x22013010, 0x46114082, + 0xf7ff4815, 0x2101ff29, 0x30084628, 0xff24f7ff, 0x32f522ff, 0x46202100, 0xff42f7ff, 0x2f004607, + 0x9801d112, 0xd0072800, 0x31f521ff, 0x98029a04, 0xff8ff7ff, 0xe0074607, 0x31f521ff, 0x300c4628, + 0xf7ff9a04, 0x4607ff86, 0xb0054638, 0x0000bdf0, 0x40230000, 0x000026fa, 0x40231008, 0x4604b5fe, + 0x6978460f, 0x68fd9001, 0x20c4bf00, 0x07005900, 0x90020f00, 0x98029901, 0xd9014288, 0xe0009801, + 0x46069802, 0x2e08e05a, 0x20d8d106, 0x60285900, 0x590020d8, 0xe03f6068, 0xd1032e01, 0x590020d0, + 0xe0397028, 0xd1032e02, 0x590020d4, 0xe0338028, 0xd1062e03, 0x590020d4, 0x20d08028, 0x70a85900, + 0x2e04e02a, 0x20d8d103, 0x60285900, 0x2e05e024, 0x20d8d106, 0x60285900, 0x590020d0, 0xe01b7128, + 0xd1062e06, 0x590020d8, 0x20d46028, 0x80a85900, 0x2e07e012, 0x20d8d109, 0x60285900, 0x590020d4, + 0x20d080a8, 0x71a85900, 0x20d8e006, 0x60285900, 0x590020d8, 0x26086068, 0x980119ad, 0x90011b80, + 0x20c4bf00, 0x07005900, 0x90020f00, 0x98029901, 0xd9014288, 0xe0009801, 0x46069802, 0xd1a22e00, + 0x980160fd, 0x98016178, 0xd1132800, 0x200fbf00, 0x182001c0, 0x21026c80, 0x46014388, 0x46209000, + 0xfdd4f000, 0x61b82003, 0x28006a38, 0x6a39d002, 0x47882003, 0x61789801, 0xb5febdfe, 0x460f4604, + 0x900168b8, 0x4620683d, 0xfdc5f000, 0x1a082108, 0x99019002, 0x42889802, 0x9801d901, 0x9802e000, + 0xe0584606, 0xd1052e08, 0x68292098, 0x68695101, 0xe03e5101, 0xd1032e01, 0x20907829, 0xe0385101, + 0xd1032e02, 0x20948829, 0xe0325101, 0xd1062e03, 0x20948829, 0x78a95101, 0x51012090, 0x2e04e029, + 0x2098d103, 0x51016829, 0x2e05e023, 0x2098d106, 0x51016829, 0x20907929, 0xe01a5101, 0xd1062e06, + 0x68292098, 0x88a95101, 0x51012094, 0x2e07e011, 0x2098d109, 0x51016829, 0x209488a9, 0x79a95101, + 0x51012090, 0x2098e005, 0x51016829, 0x51016869, 0x19ad2608, 0x1b809801, 0x46209001, 0xfd6bf000, + 0x1a082108, 0x99019002, 0x42889802, 0x9801d901, 0x9802e000, 0x2e004606, 0x60fdd1a4, 0x61789801, + 0x28009801, 0xbf00d113, 0x01c0200f, 0x6c801820, 0x00400840, 0x90004601, 0xf0004620, 0x2001fd47, + 0x69f861b8, 0xd0022800, 0x200169f9, 0xbdfe4788, 0x49fbb510, 0x48fb4449, 0x68004448, 0xfd48f000, + 0xb570bd10, 0x25014606, 0x48f72400, 0x78004448, 0xd0022800, 0xd1002e00, 0x2d022502, 0x2000d017, + 0x444949f1, 0x4cf17008, 0x25006824, 0xd00b2c00, 0x28006820, 0x6820d008, 0x28001c40, 0x2101d004, + 0x68200709, 0xd2024288, 0xffe8f001, 0x2d014604, 0x2d02d009, 0x49e6d007, 0x68204449, 0x20016008, + 0x444949e1, 0x2d027008, 0x2500d100, 0xbd704628, 0x4605b5f8, 0x4617460c, 0x90002000, 0xffc1f7ff, + 0x2e004606, 0x2601d000, 0xd0322e01, 0x48d82601, 0x68004448, 0xb2818800, 0xe0262000, 0x444a4ad4, + 0x68526812, 0x58d20083, 0xd01d2a00, 0x444a4ad0, 0x68526812, 0x58d20083, 0x68226022, 0x23026852, + 0x2a00401a, 0x6822d010, 0x42aa68d2, 0x6822d80c, 0x682368d2, 0x18d2691b, 0xd90542aa, 0x69926822, + 0x2201603a, 0xe0029200, 0x42881c40, 0xbf00dbd6, 0x2101bf00, 0x40489800, 0x46304606, 0xb5ffbdf8, + 0x9f0ab081, 0x26002400, 0xd10b2f00, 0x444848b9, 0x28006800, 0x48b7d006, 0x68004448, 0x4288a901, + 0x2402d100, 0xd0092c01, 0xd0072c02, 0x49b12000, 0x60084449, 0xf7ff4638, 0x4604ff64, 0xd00c2c01, + 0xd00a2c02, 0x444b4ba6, 0x00d2227d, 0x48a5a901, 0x68004448, 0xfd9ef000, 0x2e004606, 0x2c01d10f, + 0x2c02d00d, 0x4a9ed00b, 0x48a1444a, 0x68014448, 0x4448489c, 0xf0016800, 0x4606fa67, 0x2c02e002, + 0x2401d000, 0xd14b2e00, 0xd0492c01, 0xd0472c02, 0x44494993, 0x44484893, 0xf0006800, 0x4894ff22, + 0x68004448, 0xb2808800, 0x25009000, 0x4890e02f, 0x68004448, 0x00a96840, 0x28005840, 0x488cd026, + 0x68004448, 0x00a96840, 0x69805840, 0x28006bc0, 0x4887d01c, 0x68004448, 0x00aa6840, 0x4a805881, + 0x4880444a, 0x68004448, 0xfb2bf001, 0x2e004606, 0x487fd10c, 0x68004448, 0x00aa6840, 0x4a785881, + 0x4878444a, 0x68004448, 0xfbb3f001, 0x98001c6d, 0xdbcc4285, 0x4877a901, 0x60014448, 0xbf002400, + 0xd1002c02, 0x46202400, 0xbdf0b005, 0x4604b57c, 0x2000460d, 0xf7ff9001, 0x4606fee4, 0xd0002e00, + 0x2e012601, 0x2100d02f, 0x90002004, 0xe0252000, 0x444a4a67, 0x68526812, 0x58d20083, 0xd01c2a00, + 0x444a4a63, 0x68526812, 0x58d20083, 0x6822603a, 0x23026852, 0x2a00401a, 0x6822d00f, 0x42aa6952, + 0x2901d106, 0x683ad104, 0x22016022, 0xe0089201, 0x69526822, 0xd10042aa, 0x1c402101, 0x42909a00, + 0xbf00dbd6, 0x2101bf00, 0x40489801, 0x46304606, 0xb5febd7c, 0x460e4604, 0x20002700, 0x90009001, + 0x4a47bf00, 0x4621444a, 0x44484846, 0xf0016800, 0x4605fb06, 0x28006960, 0x2d00d00e, 0xa801d10c, + 0xf7ff6961, 0x4a3effa3, 0x483e444a, 0x99014448, 0xf0016800, 0x4605faf4, 0xd0082d00, 0xdd0242b7, + 0x90002001, 0x2064e005, 0xfd03f001, 0x2d001c7f, 0xbf00d1d7, 0xbdfe9800, 0xb08fb5f3, 0x980f2500, + 0x2000900e, 0x900c900d, 0x900a900b, 0xa90caa0a, 0xf7ff980e, 0x4605fe9d, 0xd10c2d00, 0x6940980c, + 0xd0082800, 0x6940980c, 0x980c900d, 0xa80b6941, 0xff6cf7ff, 0x2d004605, 0x2000d107, 0x48269000, + 0xc80f4448, 0xfecbf7ff, 0x9f104605, 0x6980980a, 0x980c9009, 0x980f68c1, 0x94081a44, 0x2d009c08, + 0x491ed104, 0xf7ff980c, 0x4605ff94, 0xd1782d00, 0x2000e115, 0x980c9007, 0x68006980, 0xd1022801, + 0x770c4669, 0x980ce03e, 0x68006980, 0xd1062802, 0x77444668, 0x0e010420, 0x77014668, 0x980ce032, + 0x68006980, 0xd11b2803, 0x77844668, 0x0e010420, 0x77414668, 0x0e010220, 0x77014668, 0x0000e022, + 0x00000010, 0x00000004, 0x00000038, 0x16007c0c, 0x0000000c, 0x00000008, 0x0000003c, 0x0000c350, + 0x6980980c, 0x28046800, 0x4668d10c, 0x042077c4, 0x46680e01, 0x02207781, 0x46680e01, 0x0e207741, + 0x77084669, 0x444a4afe, 0x444848fe, 0x6800990c, 0xfa07f001, 0x2e004606, 0x2501d001, 0x980de0c2, + 0xd00c2800, 0x444a4af6, 0x444848f6, 0x6800990b, 0xf9f7f001, 0x2e004606, 0x2501d001, 0x9809e0b2, + 0xd2004287, 0x4bee9709, 0xaa07444b, 0x444848ed, 0x6800990c, 0xfb0ff001, 0x2e004606, 0x2501d002, + 0xe0a0e0a0, 0x2800980d, 0x4be5d00d, 0xaa07444b, 0x444848e4, 0x6800990b, 0xfafdf001, 0x2e004606, + 0x2501d001, 0x2000e08e, 0xbf009006, 0x48ddbf00, 0x68004448, 0xfae5f000, 0xd1f82800, 0x444949d8, + 0x980c2200, 0x92017800, 0x92009203, 0x90029104, 0x6980980c, 0x78016a80, 0x48d24613, 0x68004448, + 0xfc6df000, 0x20014606, 0x49ce04c0, 0x68094449, 0xbf006508, 0x444848cb, 0x30806800, 0x28006c40, + 0x48c8d0f8, 0x68004448, 0x6d003080, 0x9006b2c0, 0xf0012064, 0x980cfbfe, 0x6b806980, 0x40089906, + 0xd1c32800, 0x2800980d, 0xbf00d03c, 0x48bdbf00, 0x68004448, 0xfaa5f000, 0xd1f82800, 0x444949b8, + 0x980b2200, 0x92017800, 0x92009203, 0x90029104, 0x6980980b, 0x78016a80, 0x48b24613, 0x68004448, + 0xfc2df000, 0x20014606, 0x49ae04c0, 0x68094449, 0xbf006508, 0x444848ab, 0x30806800, 0x28006c40, + 0x48a8d0f8, 0x68004448, 0x6d003080, 0x9006b2c0, 0xf0012064, 0x980bfbbe, 0x6b806980, 0x40089906, + 0xd1c32800, 0x980c49a0, 0xfe83f7ff, 0x2d004605, 0xe007d000, 0x1a3f9809, 0x18249809, 0x2f00bf00, + 0xe6e6d000, 0x4628bf00, 0xbdf0b011, 0x2600b5fe, 0x90002000, 0x44484895, 0xf7ffc80f, 0x4606fd90, + 0xd0362e01, 0x44484892, 0x88006800, 0x9001b280, 0xe02a2400, 0x4448488e, 0x68406800, 0x584000a1, + 0xd0212800, 0x4448488a, 0x68406800, 0x584500a1, 0x68682102, 0x28004008, 0x69a8d015, 0x27009000, + 0x9a00e00d, 0x68ea6991, 0xf7ff19d0, 0x4606fe75, 0xd1012e01, 0xbdfe4630, 0x69809800, 0x692819c7, + 0xd8ee42b8, 0xbf00bf00, 0x98011c64, 0xdbd14284, 0x4630bf00, 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0x93092300, + 0x2b009b0b, 0x2b01d006, 0x2b02d007, 0x2b03d009, 0xe00ad10f, 0x93092310, 0x23ffe00c, 0x93093301, + 0x237de008, 0x9309015b, 0x237de004, 0x9309025b, 0xbf00e000, 0x9b0abf00, 0x9f091c5b, 0x9f0d437b, + 0x007f1c7f, 0x6463437b, 0x035b2301, 0x0b5b4013, 0x231f9308, 0x4013021b, 0x93070a1b, 0x0f1b0713, + 0x9b089306, 0xd1022b00, 0x93052308, 0x2340e001, 0x9b079305, 0x9f051c5b, 0x9f06437b, 0x007f1c7f, + 0x64a3437b, 0xaf151d0b, 0x930219db, 0x93032301, 0x93012300, 0x785b9b02, 0x9b02021f, 0x431f781b, + 0x9b039701, 0xd0092b00, 0x78db9b02, 0x9f02061b, 0x043f78bf, 0x9f01433b, 0x9301433b, 0x93049b01, + 0x0fdb9b04, 0x2b0007db, 0x9b04d104, 0x08db1c5b, 0xe0056063, 0x1edb9b04, 0x07ff2701, 0x6063433b, + 0x3328460b, 0x5cfbaf15, 0x403b27f0, 0x2301091f, 0x626340bb, 0x331c460b, 0x5cffaf15, 0x40bb2301, + 0xaf1561a3, 0x5cfb9b12, 0x403b2720, 0x2b00095b, 0x2d01d023, 0x2d03d021, 0x460bd01f, 0xaf153309, + 0x60035cfb, 0x71032300, 0x71432302, 0x3308460b, 0x27e05cfb, 0x095b403b, 0xd1022b00, 0x60831e5b, + 0x235ae001, 0x460b6083, 0xaf153308, 0x06db5cfb, 0x61030edb, 0x75032302, 0xaf15e082, 0x5cfb9b12, + 0x403b2740, 0x2b00099b, 0x2d01d023, 0x2d03d021, 0x460bd01f, 0xaf15330b, 0x60035cfb, 0x71032300, + 0x71432302, 0x330a460b, 0x27e05cfb, 0x095b403b, 0xd1022b00, 0x60831e5b, 0x235ae001, 0x460b6083, + 0xaf15330a, 0x06db5cfb, 0x61030edb, 0x75032302, 0xaf15e056, 0x5cfb9b12, 0x403b2710, 0x2b00091b, + 0x460bd01f, 0xaf15330f, 0x60035cfb, 0x71032300, 0x71432301, 0x330e460b, 0x27e05cfb, 0x095b403b, + 0xd1022b00, 0x60831e5b, 0x235ae001, 0x460b6083, 0xaf15330e, 0x06db5cfb, 0x61030edb, 0x75032301, + 0xaf15e02e, 0x5cfb9b12, 0x0fdb07db, 0xd01d2b00, 0x330d460b, 0x60035cfb, 0x71032300, 0x460b7143, + 0x5cfb330c, 0x403b27e0, 0x2b00095b, 0x1e5bd102, 0xe0016083, 0x6083235a, 0x330c460b, 0x5cfbaf15, + 0x0edb06db, 0x23016103, 0xe0097503, 0x60032303, 0x71032300, 0x1e5b7143, 0x23006083, 0x75036103, + 0x68e72306, 0x2300603b, 0x713b68e7, 0x69272304, 0x2300603b, 0x713b6927, 0x69e72360, 0x2300603b, + 0x713b69e7, 0x331d460b, 0x5cfbaf15, 0x603b6967, 0x69672300, 0x6967713b, 0x2302717b, 0x603b6a27, + 0x6a272300, 0x6a27713b, 0x1e5b717b, 0x60bb6a27, 0x6a272300, 0x6a27613b, 0x2301753b, 0x230563a3, + 0x603b6aa7, 0x6aa72300, 0x6b27713b, 0xe001713b, 0x00b20002, 0x333a460b, 0x5cfbaf15, 0x403b2770, + 0x003b091f, 0xfd6af000, 0x170c0406, 0x290e0d20, 0x43db2300, 0x6b2763e3, 0x6ae7603b, 0xe01d603b, + 0xbf00bf00, 0x63e32302, 0x6b272301, 0x2335603b, 0x603b6ae7, 0x2340e012, 0x230163e3, 0x603b6b27, + 0x6ae72305, 0xe009603b, 0x63e32380, 0x6b27233e, 0x233f603b, 0x603b6ae7, 0xbf00e000, 0xe000bf00, + 0x46304efe, 0xbdf0b059, 0xb086b5f7, 0x48fb460e, 0x90051e40, 0x90042000, 0xd0772e00, 0x90036830, + 0x90026870, 0x90052000, 0xe0772700, 0x980200b9, 0x2c005844, 0x7822d071, 0x2a019906, 0x2a02d006, + 0x2a04d008, 0x2a08d00c, 0xe00fd117, 0x02db2301, 0xe01418c8, 0x02db2301, 0x461818cb, 0xe00e3080, + 0x02db2301, 0x1dd818cb, 0xe00830f9, 0x02db2301, 0x461818cb, 0x308130ff, 0x2000e001, 0xbf00bf00, + 0x4605bf00, 0xd0432d00, 0x21036828, 0x43880409, 0x04097a21, 0x04122203, 0x43084011, 0x20006028, + 0x21049001, 0x40086860, 0xd0102800, 0x90009808, 0x78227a23, 0x980669a1, 0xfd27f7ff, 0x98019001, + 0xd0042800, 0x40b82008, 0x43089904, 0x98019004, 0xd1192800, 0x68602102, 0x28004008, 0x4621d014, + 0xf7ff4628, 0x7920fc7f, 0x0fc007c0, 0x320122ff, 0x40116861, 0x7a214308, 0x22030409, 0x40110412, + 0x03d14308, 0x60281840, 0xe0056828, 0xe004e00b, 0x1e4048ba, 0xe0049005, 0x1c7fbf00, 0x42879803, + 0xbf00d384, 0x9804bf00, 0xd0042800, 0x04492159, 0x43089804, 0x98059005, 0xbdf0b009, 0x4601b510, + 0xe05b2000, 0x01c32200, 0x02e42401, 0x50e2190c, 0x240101c3, 0x190c02e4, 0x609a191b, 0x240101c3, + 0x190c02e4, 0x60da191b, 0x240101c3, 0x190c02e4, 0x621a191b, 0x240101c3, 0x190c02e4, 0x641a191b, + 0x240101c3, 0x190c02e4, 0x645a191b, 0x01c22300, 0x02e42401, 0x1912190c, 0x22006493, 0x240101c3, + 0x190c02e4, 0x64da191b, 0x240101c3, 0x190c02e4, 0x651a191b, 0x240101c3, 0x190c02e4, 0x661a191b, + 0x240101c3, 0x190c02e4, 0x665a191b, 0x240101c3, 0x190c02e4, 0x669a191b, 0x240101c3, 0x190c02e4, + 0x66da191b, 0x240101c3, 0x190c02e4, 0x671a191b, 0x230101c2, 0x18cb02db, 0x1c40589a, 0xd3a12804, + 0xb5f0bd10, 0x4607b085, 0x4615460c, 0x68c669a0, 0x78202101, 0x92012200, 0xc323ab02, 0x79329200, + 0x23007831, 0xf7ff4638, 0xb005faaa, 0xb5f0bdf0, 0x4607b085, 0x4615460c, 0x690669a0, 0x78202101, + 0x92012200, 0xc323ab02, 0x79329200, 0x23007831, 0xf7ff4638, 0xb005fa94, 0xb5ffbdf0, 0x460cb087, + 0x461e4615, 0x21009f10, 0x91017820, 0x460b9103, 0x9704460a, 0x90029100, 0x98074631, 0xfa7ff7ff, + 0x98069006, 0xd1072800, 0x22012300, 0x97004629, 0xf7ff9807, 0x9006fb31, 0xb00b9806, 0xb5f7bdf0, + 0x460cb082, 0x20014615, 0x69a69001, 0x6ab09500, 0xaa017803, 0x98024621, 0xffcff7ff, 0x2f004607, + 0x4669d104, 0x6bb07909, 0x90014008, 0x79004668, 0xd0022800, 0xb0052001, 0x2000bdf0, 0xb5ffe7fb, + 0x460cb089, 0x461e4615, 0x463a9f12, 0x98094621, 0xff87f7ff, 0x98089008, 0xd1172800, 0x6bc069a0, + 0x98069006, 0xd1002802, 0x2001e000, 0x21019007, 0x22007820, 0xc383ab02, 0x98079201, 0x4631462b, + 0x98099000, 0xfa2bf7ff, 0xbf009008, 0xb00d9808, 0xb5f7bdf0, 0x4614b086, 0x90052000, 0x69869807, + 0x78006af0, 0x6b309004, 0x90037800, 0x78006ab0, 0x94009002, 0x9b04aa05, 0x98069907, 0xff7df7ff, + 0x2d004605, 0x6bf7d15c, 0xd0132f02, 0xd0022f40, 0xd1512f80, 0x4669e032, 0xb2f97d08, 0x46694308, + 0x94007508, 0x9b03aa05, 0x98069907, 0xffa7f7ff, 0xe0434605, 0xaa059400, 0x99079b02, 0xf7ff9806, + 0x4605ff5c, 0xd1182d00, 0xaa059400, 0x9b043201, 0x98069907, 0xff51f7ff, 0x2d004605, 0x4669d10d, + 0xb2f97d48, 0x46694308, 0x94007548, 0x9b03aa05, 0x98069907, 0xff83f7ff, 0xe01f4605, 0xaa059400, + 0x9b043201, 0x98069907, 0xff37f7ff, 0x2d004605, 0x4669d111, 0xb2f97d48, 0xe0014308, 0x00b20005, + 0x75484669, 0xaa059400, 0x9b033201, 0x98069907, 0xff65f7ff, 0xe0014605, 0xbf004d6a, 0xbf00bf00, + 0xb0094628, 0xb5f0bdf0, 0x4607b087, 0x4615460c, 0x69c669a0, 0x78202101, 0x92012200, 0xc323ab02, + 0x79329200, 0x23007831, 0xf7ff4638, 0x9006f998, 0xb0079806, 0xb5ffbdf0, 0x460cb087, 0x461f4615, + 0x1c404858, 0x2d009006, 0x69a0d015, 0x98059005, 0x22016946, 0x79317820, 0x92039704, 0x90029101, + 0x68009805, 0x79329000, 0x462b7831, 0xf7ff9807, 0x9006f976, 0x9806bf00, 0xbdf0b00b, 0xb087b5ff, + 0x4616460d, 0x1c7f4f47, 0x900569a8, 0x6a049805, 0xd0342e00, 0x6a419805, 0x42819810, 0x6968d32f, + 0xd1012800, 0xe0007828, 0x90067d28, 0x79622300, 0x98069912, 0x92019303, 0x90029104, 0x68009805, + 0x79229000, 0x46337821, 0xf7ff9807, 0x4607f948, 0xd1072f00, 0x28006920, 0x6921d004, 0xf7ff9807, + 0x4607fa3a, 0xd10a2f00, 0x98119912, 0x90009101, 0x9a107d23, 0x9807990a, 0xf981f7ff, 0x46384607, + 0xbdf0b00b, 0xb087b5ff, 0x9f12460d, 0x1c764e25, 0x900569a8, 0x68849805, 0x28009809, 0x6968d03f, + 0xd1012800, 0xe0007828, 0x90067d28, 0x79612200, 0xab029806, 0x9101c385, 0x68009805, 0x79229000, + 0x9b097821, 0xf7ff9807, 0x4606f90a, 0xd1072e00, 0x28006920, 0x6921d904, 0xf7ff9807, 0x4606f9fc, + 0xd1102e00, 0x68a01e71, 0xd00c4288, 0x98062100, 0xaa029101, 0x9100c283, 0x7a217d22, 0x98072300, + 0xf8edf7ff, 0x2e004606, 0x9811d109, 0x90009701, 0x9a107d23, 0x9807990a, 0xf967f7ff, 0x46304606, + 0xbdf0b00b, 0x00b20003, 0x4602b530, 0x1a1048f2, 0x012009c4, 0x19434df1, 0x60106808, 0x629068c8, + 0x62d06908, 0x63106948, 0x62506888, 0x61906848, 0x63506988, 0x601869c8, 0x60586a08, 0xbd302000, + 0xb089b500, 0x210748e6, 0x184001c9, 0x09006880, 0x49e30100, 0x01d22207, 0x60881889, 0x49e02000, + 0x0192220d, 0x60881889, 0x680048de, 0x43080651, 0x600849dc, 0x210748da, 0x184001c9, 0x06096840, + 0x49d74308, 0x01d22207, 0x60481889, 0x461148d4, 0x68801840, 0x43080609, 0x188949d1, 0x22246088, + 0x447949d1, 0xf7fd4668, 0x4669ff03, 0xf7ff48cf, 0x2224ffab, 0x447949cc, 0x46683110, 0xfef8f7fd, + 0x48cb4669, 0xffa0f7ff, 0x49c72224, 0x311e4479, 0xf7fd4668, 0x4669feed, 0x308048c5, 0xff94f7ff, + 0x49c12224, 0x312a4479, 0xf7fd4668, 0x4669fee1, 0x308048b9, 0xff88f7ff, 0x49bb2224, 0x31364479, + 0xf7fd4668, 0x4669fed5, 0xf7ff48ba, 0xb009ff7d, 0xb510bd00, 0x00a14604, 0xf7fd1860, 0xbd10fec1, + 0x4605b530, 0x2d012400, 0x48b3d134, 0x68004448, 0x220749ab, 0x188901d2, 0x48b06088, 0x68004448, + 0x600849a8, 0x444848ae, 0x49a56800, 0x60481889, 0x444848ac, 0x49a26800, 0x60881889, 0x444949aa, + 0x3080489d, 0xff50f7ff, 0x444949a8, 0xf7ff48a1, 0x49a7ff4b, 0x489d4449, 0xff46f7ff, 0x444949a5, + 0xf7ff489b, 0x49a4ff41, 0x48994449, 0xf7ff3080, 0xe120ff3b, 0x01012001, 0x188c4a90, 0x3180498e, + 0x4a996809, 0x6011444a, 0x3180498b, 0x60d16a89, 0x31804989, 0x61116ac9, 0x31804987, 0x61516b09, + 0x31804985, 0x60916a49, 0x31804983, 0x60516989, 0x31804981, 0x61916b49, 0x61d16821, 0x62116861, + 0x01012005, 0x188c4a7d, 0x68094982, 0x444a4a87, 0x49796011, 0x188901c2, 0x4a846a89, 0x60d1444a, + 0x01c24975, 0x6ac91889, 0x444a4a80, 0x49726111, 0x188901c2, 0x4a7d6b09, 0x6151444a, 0x01c2496e, + 0x6a491889, 0x444a4a79, 0x496b6091, 0x188901c2, 0x4a766989, 0x6051444a, 0x01c24967, 0x6b491889, + 0x444a4a72, 0x68216191, 0x686161d1, 0x20086211, 0x4a620101, 0x4965188c, 0x4a6d6809, 0x6011444a, + 0x01c2495d, 0x6a891889, 0x444a4a69, 0x495a60d1, 0x188901c2, 0x4a666ac9, 0x6111444a, 0x01c24956, + 0x6b091889, 0x444a4a62, 0x49536151, 0x188901c2, 0x4a5f6a49, 0x6091444a, 0x01c2494f, 0x69891889, + 0x444a4a5b, 0x494c6051, 0x188901c2, 0x4a586b49, 0x6191444a, 0x61d16821, 0x62116861, 0x0101200b, + 0x188c4a46, 0x6809494a, 0x444a4a52, 0x49426011, 0x188901c2, 0x4a4f6a89, 0x60d1444a, 0x01c2493e, + 0x6ac91889, 0x444a4a4b, 0x493b6111, 0x188901c2, 0x4a486b09, 0x6151444a, 0x01c24937, 0x6a491889, + 0x444a4a44, 0x49346091, 0x188901c2, 0x4a416989, 0x6051444a, 0x01c24930, 0x6b491889, 0x444a4a3d, + 0x68216191, 0x686161d1, 0x200c6211, 0x4a2b0101, 0x492f188c, 0x68093180, 0x444a4a37, 0x49266011, + 0x188901c2, 0x4a346a89, 0x60d1444a, 0x01c24922, 0x6ac91889, 0x444a4a30, 0x491f6111, 0x188901c2, + 0x4a2d6b09, 0x6151444a, 0x01c2491b, 0x6a491889, 0x444a4a29, 0x49186091, 0x188901c2, 0x4a266989, + 0x6051444a, 0x01c24914, 0x6b491889, 0x444a4a22, 0x68216191, 0x686161d1, 0x49116211, 0x01d22207, + 0x68891889, 0x444a4a14, 0x490e6011, 0x4a136809, 0x6011444a, 0x2207490a, 0x188901d2, 0x4a106849, + 0x6011444a, 0x22074906, 0x188901d2, 0x4a0d6889, 0x6011444a, 0xbd30bf00, 0x40320000, 0x40310000, + 0x40260000, 0x40260380, 0x00000432, 0x40320400, 0x40320580, 0x40320280, 0x0000005c, 0x00000060, + 0x00000064, 0x00000068, 0x0000006c, 0x00000090, 0x000000b4, 0x000000d8, 0x000000fc, 0x44484819, + 0x44494919, 0x48196008, 0x49164448, 0x60484449, 0x44484817, 0x44494915, 0x48166008, 0x49144448, + 0x61884449, 0x44484814, 0x44494912, 0x48136088, 0x60c84448, 0x44484812, 0x48126108, 0x61484448, + 0x44484811, 0x481161c8, 0x62084448, 0x44484810, 0x481062c8, 0x62884448, 0x4448480f, 0x48026308, + 0x47704448, 0x00000264, 0x00000274, 0x00000260, 0x00000244, 0x000001f8, 0x00000120, 0x00000138, + 0x00000150, 0x00000168, 0x00000180, 0x00000198, 0x000001b0, 0x000001c8, 0x000001e0, 0x4674b430, + 0x78251e64, 0x42ab1c64, 0x5d63d304, 0x18e3005b, 0x4718bc30, 0xe7f8461d, 0x00000003, 0x00000000, + 0x00000000, 0x00000068, 0x00000000, 0x00000000, 0x00000000, 0x00001212, 0x00000000, 0x000000ff, + 0x00000000, 0x00000000, 0x6eeee666, 0x00000000, 0x00000000, 0x00000000, 0x11111111, 0x11111111, + 0x0000001f, 0x00000000, 0x00000000, 0x0006eeee, 0x00000000, 0x00000000, 0x00000000, 0x11111111, + 0x00000011, 0x00000001, 0x00000000, 0x00000000, 0x0000000b, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x000000e0, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40420000, 0x00000000, 0x00000000, 0x00000000, + 0x00000001, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000007, 0x00000001, 0x00000000, 0x00000001, 0x00000007, + 0x00000001, 0x00000000, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, + 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, + 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, + 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, + 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, + 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, + 0x00000001, 0x00000001, 0x00000001, 0x000000eb, 0x00000200, 0x00000001, 0x00000002, 0x00000004, + 0x00000002, 0x00000006, 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000004, + 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x000000d8, 0x00000000, 0xffffffff, + 0x00000000, 0x00000000, 0x00000000, 0x00000060, 0x00000000, 0xffffffff, 0x00000000, 0x00000000, + 0x00000000, 0x00000038, 0x00000000, 0xffffffff, 0x00000002, 0x00000000, 0x00000002, 0x00000035, + 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000005, 0x00000000, 0xffffffff, + 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0xffffffff, 0x00000000, 0x00000000, + 0x00000000, 0x00000003, 0x04000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000, + 0x00000000, 0x00000000, 0x00000200, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, + 0x00000002, 0x00000208, 0x00020b70, 0x00000154, 0x00000001, 0x00000003, 0x00000000, 0x18000000, + 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 +}; + +static const program_target_t CY8C6xx7_sb_flash_prog = + // Main Flash + { + .init = 0x08000021, // Init + .uninit = 0x08000027, // UnInit + .erase_chip = 0x0800002d, // EraseChip + .erase_sector = 0x08000035, // EraseSector + .program_page = 0x08000041, // ProgramPage + .verify = 0x08000055, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08000a14, + 0x08000d00 + }, + .program_buffer = 0x08000000 + 0x00000D00, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xx7_sb_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xx7_sb_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00000200, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; + +static const program_target_t CY8C6xxx_sb_WFLASH_flash_prog = + // WFLASH (Work) + { + .init = 0x08000021, // Init + .uninit = 0x08000027, // UnInit + .erase_chip = 0x0800002d, // EraseChip + .erase_sector = 0x08000035, // EraseSector + .program_page = 0x08000041, // ProgramPage + .verify = 0x08000055, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08000a18, + 0x08000d00 + }, + .program_buffer = 0x08000000 + 0x00000D00, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxx_sb_WFLASH_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxx_sb_WFLASH_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00000200, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; + +static const program_target_t CY8C6xxx_sb_SFLASH_USER_flash_prog = + // SFLASH: User Data + { + .init = 0x08000021, // Init + .uninit = 0x08000027, // UnInit + .erase_chip = 0x0800002d, // EraseChip + .erase_sector = 0x08000035, // EraseSector + .program_page = 0x08000041, // ProgramPage + .verify = 0x08000055, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08000a1c, + 0x08000d00 + }, + .program_buffer = 0x08000000 + 0x00000D00, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxx_sb_SFLASH_USER_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxx_sb_SFLASH_USER_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00000200, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; + +static const program_target_t CY8C6xxx_sb_SFLASH_NAR_flash_prog = + // SFLASH: NAR + { + .init = 0x08000021, // Init + .uninit = 0x08000027, // UnInit + .erase_chip = 0x0800002d, // EraseChip + .erase_sector = 0x08000035, // EraseSector + .program_page = 0x08000041, // ProgramPage + .verify = 0x08000055, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08000a1c, + 0x08000d00 + }, + .program_buffer = 0x08000000 + 0x00000D00, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxx_sb_SFLASH_NAR_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxx_sb_SFLASH_NAR_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00000200, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; + +static const program_target_t CY8C6xxx_sb_SFLASH_PKEY_flash_prog = + // SFLASH: Public Key + { + .init = 0x08000021, // Init + .uninit = 0x08000027, // UnInit + .erase_chip = 0x0800002d, // EraseChip + .erase_sector = 0x08000035, // EraseSector + .program_page = 0x08000041, // ProgramPage + .verify = 0x08000055, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08000a1c, + 0x08000d00 + }, + .program_buffer = 0x08000000 + 0x00000D00, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxx_sb_SFLASH_PKEY_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxx_sb_SFLASH_PKEY_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00000200, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; + +static const program_target_t CY8C6xxx_sb_SFLASH_TOC2_flash_prog = + // SFLASH: TOC2 + { + .init = 0x08000021, // Init + .uninit = 0x08000027, // UnInit + .erase_chip = 0x0800002d, // EraseChip + .erase_sector = 0x08000035, // EraseSector + .program_page = 0x08000041, // ProgramPage + .verify = 0x08000055, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x08000a1c, + 0x08000d00 + }, + .program_buffer = 0x08000000 + 0x00000D00, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxx_sb_SFLASH_TOC2_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxx_sb_SFLASH_TOC2_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00000200, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; + +static const program_target_t CY8C6xxx_sb_SMIF_flash_prog = + // SMIF + { + .init = 0x08000069, // Init + .uninit = 0x0800007f, // UnInit + .erase_chip = 0x0800008f, // EraseChip + .erase_sector = 0x0800009d, // EraseSector + .program_page = 0x080000c7, // ProgramPage + .verify = 0x080000e3, // Verify + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + .sys_call_s = + { + 0x08000001, + 0x0800270c, + 0x08004000 + }, + .program_buffer = 0x08000000 + 0x00004000, // mem buffer location + .algo_start = 0x08000000, // location to write prog_blob in target RAM + .algo_size = sizeof(CY8C6xxx_sb_SMIF_flash_prog_blob), // prog_blob size + .algo_blob = CY8C6xxx_sb_SMIF_flash_prog_blob, // address of prog_blob + .program_buffer_size = 0x00010000, // ram_to_flash_bytes_to_be_written + .algo_flags = (kAlgoVerifyReturnsAddress | kAlgoSingleInitType) + }; + diff --git a/source/family/cypress/target.c b/source/family/cypress/target.c new file mode 100644 index 0000000000..a96f9910b3 --- /dev/null +++ b/source/family/cypress/target.c @@ -0,0 +1,119 @@ +/******************************************************************************* +* @file target.c +* @brief Target information for the target MCU +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "target_config.h" +#include "error.h" +#include "PSOC6xxx.h" +#include "stdbool.h" + +// The files xxx_flash_blob.c must only be included in target.c +#include "p6_2m_flash_blob.c" +#include "p6_ble_flash_blob.c" +#include "p6_sb_flash_blob.c" + +extern bool kit_has_sflash_restriction(void); + +const sector_info_t p6_sectors_info[] = +{ + { 0x10000000, 0x00000200 }, // Main FLASH + { 0x14000000, 0x00000200 }, // WFLASH (Work) + { 0x16000800, 0x00000200 }, // SFLASH: User Data + { 0x16001A00, 0x00000200 }, // SFLASH: NAR + { 0x16005A00, 0x00000200 }, // SFLASH: Public Key + { 0x16007C00, 0x00000200 }, // SFLASH: TOC2 + { 0x18000000, 0x00010000 }, // SMIF +}; + +// default target information +target_cfg_t target_device = { + .sector_size = 4096, + .sector_cnt = (MB(2) / 4096), + .flash_start = 0x10000000, + .flash_end = 0x10000000 + 0x00200000, + .ram_start = 0x08000000, + .ram_end = 0x08048000, + .flash_algo = (program_target_t *) &CY8C6xxA_flash_prog, + //(program_target_t *) &p6_2m_flash[0], + .extra_flash = { + { .start = 0x14000000, .end = 0x14000000 + 0x00008000, .flash_algo = (program_target_t *) &CY8C6xxA_WFLASH_flash_prog }, // WFLASH (Work) + { .start = 0x16000800, .end = 0x16000800 + 0x00000800, .flash_algo = (program_target_t *) &CY8C6xxA_SFLASH_USER_flash_prog }, // SFLASH: User Data + { .start = 0x16001A00, .end = 0x16001A00 + 0x00000200, .flash_algo = (program_target_t *) &CY8C6xxA_SFLASH_NAR_flash_prog }, // SFLASH: NAR + { .start = 0x16005A00, .end = 0x16005A00 + 0x00000C00, .flash_algo = (program_target_t *) &CY8C6xxA_SFLASH_PKEY_flash_prog }, // SFLASH: Public Key + { .start = 0x16007C00, .end = 0x16007C00 + 0x00000400, .flash_algo = (program_target_t *) &CY8C6xxA_SFLASH_TOC2_flash_prog }, // SFLASH: TOC2 + { .start = 0x18000000, .end = 0x18000000 + 0x08000000, .flash_algo = (program_target_t *) &CY8C6xxA_SMIF_flash_prog }, // SMIF + }, + .sectors_info = p6_sectors_info, + .sector_info_length = 7 +}; + +void init_flash_algo(uint32_t si_id) +{ + // Initialize main flash,WFlash, SFlash and SMIF programming algorithms + // and set proper flsash geometry based on family type/silicon ID + + if (kit_has_sflash_restriction()) + { + // PSoC64 + target_device.sector_cnt = (MB(1) / 4096); + target_device.flash_algo = (program_target_t *) &CY8C6xx7_sb_flash_prog; + target_device.flash_end = 0x10000000 + 0x00100000; + target_device.extra_flash[0].flash_algo = (program_target_t *) &CY8C6xxx_sb_WFLASH_flash_prog; + target_device.extra_flash[1].flash_algo = (program_target_t *) &CY8C6xxx_sb_SFLASH_USER_flash_prog; + target_device.extra_flash[2].flash_algo = (program_target_t *) &CY8C6xxx_sb_SFLASH_NAR_flash_prog; + target_device.extra_flash[3].flash_algo = (program_target_t *) &CY8C6xxx_sb_SFLASH_PKEY_flash_prog; + target_device.extra_flash[4].flash_algo = (program_target_t *) &CY8C6xxx_sb_SFLASH_TOC2_flash_prog; + target_device.extra_flash[5].flash_algo = (program_target_t *) &CY8C6xxx_sb_SMIF_flash_prog; +} + else + { + switch (si_id & PSOC6_FAMILY_ID_LO_MSK) + { + // PSoC6-BLE family + case PSOC6_BLE_FAMILY_ID_LO: + target_device.sector_cnt = (MB(1) / 4096); + target_device.flash_algo = (program_target_t *) &CY8C6xx7_flash_prog; + target_device.flash_end = 0x10000000 + 0x00100000; + target_device.extra_flash[0].flash_algo = (program_target_t *) &CY8C6xxx_WFLASH_flash_prog; + target_device.extra_flash[1].flash_algo = (program_target_t *) &CY8C6xxx_SFLASH_USER_flash_prog; + target_device.extra_flash[2].flash_algo = (program_target_t *) &CY8C6xxx_SFLASH_NAR_flash_prog; + target_device.extra_flash[3].flash_algo = (program_target_t *) &CY8C6xxx_SFLASH_PKEY_flash_prog; + target_device.extra_flash[4].flash_algo = (program_target_t *) &CY8C6xxx_SFLASH_TOC2_flash_prog; + target_device.extra_flash[5].flash_algo = (program_target_t *) &CY8C6xxx_SMIF_flash_prog; + break; + + // PSoC6-2M family + case PSOC6_2M_FAMILY_ID_LO: + target_device.sector_cnt = (MB(2) / 4096); + target_device.flash_algo = (program_target_t *) &CY8C6xxA_flash_prog; + target_device.flash_end = 0x10000000 + 0x00200000; + target_device.extra_flash[0].flash_algo = (program_target_t *) &CY8C6xxA_WFLASH_flash_prog; + target_device.extra_flash[1].flash_algo = (program_target_t *) &CY8C6xxA_SFLASH_USER_flash_prog; + target_device.extra_flash[2].flash_algo = (program_target_t *) &CY8C6xxA_SFLASH_NAR_flash_prog; + target_device.extra_flash[3].flash_algo = (program_target_t *) &CY8C6xxA_SFLASH_PKEY_flash_prog; + target_device.extra_flash[4].flash_algo = (program_target_t *) &CY8C6xxA_SFLASH_TOC2_flash_prog; + target_device.extra_flash[5].flash_algo = (program_target_t *) &CY8C6xxA_SMIF_flash_prog; + break; + + default: + break; + } + } +} diff --git a/source/family/cypress/target_reset.c b/source/family/cypress/target_reset.c new file mode 100644 index 0000000000..bb6406bce7 --- /dev/null +++ b/source/family/cypress/target_reset.c @@ -0,0 +1,160 @@ +/******************************************************************************* +* @file target_reset.c +* @brief Target reset for the PSoC6 target +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "target_reset.h" +#include "swd_host.h" +#include "swd.h" +#include "cyfitter.h" +#include "PSOC6xxx.h" +#include "target_config.h" +#include "target_family.h" +#include "IO_Config.h" + +#define MAX_AP (2u) +#define CM4_AP (2u << 24u) +#define CPU_ID (0xE000ED00u) +#define READY_ADDR (0x4023004Cu) +#define CPUSS_CM4_PWR_CTL (0x40210080u) +#define READY_VAL_SEQ (0x12344321u) +#define ACQUIRE_WAIT_MS (60000u) +#define ASQUIRE_CHK_INTERVAL_MS (10u) +#define CSW_ACCESS_MASK (0x23000052u) +#define CM4_PWR_MASK (0x00000003u) +#define CM4_PWR_VALUE (0x05fa0003u) + +extern uint32_t DAP_AP; + +volatile bool isTargetAcquired; +extern uint32_t SWDAcquirePSoC6BLE(uint8_t acquireMode, uint8_t attempts); +extern uint8_t SWD_SelectAP(uint32_t ap); +extern uint8_t SWD_WriteCSW(uint32_t csw_val); +extern uint8_t SWD_Send(uint32_t addr_32, uint32_t data_32); +extern uint8_t SWD_Receive(uint32_t adr_32, uint32_t *data_32); +extern uint8_t SWD_Abort(void); + +void target_before_init_debug(void) +{ + // any target specific sequences needed before attaching + // to the DAP across JTAG or SWD + if (!isTargetAcquired) + { + uint32_t status = SWDAcquirePSoC6BLE(0, 1); + if (kit_has_sflash_restriction()) + { + uint32_t ready_val = 0; + for (uint32_t i = 0; i < ACQUIRE_WAIT_MS; i++) + { + ready_val = 0; + if ((SWD_Receive(READY_ADDR, &ready_val) == SWD_ACK) && (ready_val == READY_VAL_SEQ)) + { + isTargetAcquired = true; + break; + } + CyDelay(ASQUIRE_CHK_INTERVAL_MS); + } + } + else + { + if (status == ACQUIRE_PASS) + { + isTargetAcquired = true; + } + } + + if (!isTargetAcquired) + { + return; + } + + // find valid AP with core + uint32_t cpu_id = 0; + for (uint32_t ap_index = 0; cpu_id == 0 && ap_index <= MAX_AP; ap_index++) + { + DAP_AP = ap_index << 24; + if ((SWD_SelectAP(DAP_AP) != SWD_ACK) || (SWD_Receive(CPU_ID, &cpu_id) != SWD_ACK)) + { + SWD_Abort(); + cpu_id = 0; + } + } + + // wake up CM4 + if ((cpu_id != 0) && (DAP_AP == CM4_AP) && (SWD_WriteCSW(CSW_ACCESS_MASK) == SWD_ACK)) + { + uint32_t pwr_ctl; + if ((SWD_Receive(CPUSS_CM4_PWR_CTL, &pwr_ctl) == SWD_ACK) + && ((pwr_ctl & CM4_PWR_MASK) != CM4_PWR_MASK)) + { + SWD_Send(CPUSS_CM4_PWR_CTL, CM4_PWR_VALUE); + } + } + } + return; +} + +uint8_t target_unlock_sequence(void) +{ + // if the device can secure the flash and there is a way to + // erase all it should be implemented here. + return 1; +} + +//uint8_t target_set_state(TARGET_RESET_STATE state) +static uint8_t target_set_state(TARGET_RESET_STATE state) +{ + // invoke reset by sw (VECT_REQ or SYS_REQ) or hw (hardware IO toggle) + //return swd_set_target_state_sw(state); + //or + + if (state == RESET_PROGRAM) + { + target_before_init_debug(); + uint32_t status = swd_set_target_state_sw(HALT); + return status; + } + + return swd_set_target_state_hw(state); +} + +uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size) +{ + // if there are security bits in the programmable flash region + // a check should be performed. This method is used when programming + // by drag-n-drop and should refuse to program an image requesting + // to set the device security. This can be performed with the debug channel + // if needed. + return 0; +} + +void prerun_target_config(void); + +const target_family_descriptor_t g_target_family_psoc6 = { + .family_id = kCypress_psoc6_FamilyID, + .target_set_state = target_set_state, + .prerun_target_config = prerun_target_config, + .security_bits_set = security_bits_set, + .target_unlock_sequence = target_unlock_sequence, + .target_before_init_debug = target_before_init_debug, +}; + +const target_family_descriptor_t *g_target_family = &g_target_family_psoc6; + + diff --git a/source/hic_hal/cypress/psoc5lp/CY8C5xxLP.h b/source/hic_hal/cypress/psoc5lp/CY8C5xxLP.h new file mode 100644 index 0000000000..59d62c5291 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/CY8C5xxLP.h @@ -0,0 +1,52 @@ +/******************************************************************************* + +* @file CY8C5xxLP.h +* @brief This file provides specific registers/constants of CY8C5xLP device. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +//PSoC 5 LP Registers +#define REG_PANTHER_DBG_CFG 0x4008000C +#define REG_PM_ACT_CFG0 0x400043A0 +#define REG_SPC_CPU_DATA 0x40004720 +#define REG_SPC_SR 0x40004722 +#define REG_FASTCLK_IMO_CR 0x40004200 +#define REG_PM_ACT_CFG12 0x400043AC +#define EEPROM_START_ADDR 0x40008000 +#define EEPROM_HEX_START_ADDR 0x00040000 +#define EEPROM_HEX_END_ADDR 0x00040800 + +//PSoC5 LP SPC User Commands +#define SPC_LD_ROW 0x02 +#define SPC_ER_ALL 0x09 +#define SPC_ER_ROW 0x13 +#define SPC_WR_ROW 0x05 +#define SPC_CHECKSUM 0x0C +#define SPC_RD_MULTI_BYTE 0x04 +#define SPC_GET_TEMP 0x0E +#define SPC_ER_SECTOR 0x08 + +//Auxiliary constants +#define SPC_KEY1 0x000000B6 +#define SPC_KEY2 0x000000D3 +#define SPC_RD_BYTE 0x00000003 +#define SPC_ready 0x00000001 +#define SPC_idle 0x00000002 + +//Timeout constants +#define SPC_PollSR_TimeOut 2000 diff --git a/source/hic_hal/cypress/psoc5lp/DAP_config.h b/source/hic_hal/cypress/psoc5lp/DAP_config.h new file mode 100644 index 0000000000..d6ff173083 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/DAP_config.h @@ -0,0 +1,515 @@ +/**************************************************************************//** + * @file DAP_config.h + * @brief CMSIS-DAP Configuration File + * @Version 1.05 (based on version V1.10 ARM DAP_config.h) + * + * @note + * Copyright (C) 2012-2015 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +/******************************************************************************* +* Copyright 2019, Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +*****************************************************************************/ + +#ifndef __DAP_CONFIG_H__ +#define __DAP_CONFIG_H__ + +#include "swd.h" +#include "stdbool.h" + +extern volatile uint8_t kit42identifier; +extern volatile bool isTargetAcquired; + +//************************************************************************************************** +/** +\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information +\ingroup DAP_ConfigIO_gr +@{ +Provides definitions about the hardware and configuration of the Debug Unit. + +This information includes: + - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. + - Debug Unit communication packet size. + - Debug Access Port communication mode (JTAG or SWD). + - Optional information about a connected Target Device (for Evaluation Boards). +*/ + +#include "IO_Config.h" // Debug Unit Cortex-M Processor Header File + +/// Processor Clock of the Cortex-M MCU used in the Debug Unit. +/// This value is used to calculate the SWD/JTAG clock speed. +#define CPU_CLOCK 64000000u ///< Specifies the CPU Clock in Hz + +/// Reset delay in microseconds +/// This value is used to keep XRES low during target reset command . +#define RESET_DELAY (400u) ///< Specifies delay in uSec + +/// Number of processor cycles for I/O Port write operations. +/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O +/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors +/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses +/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be +/// required. +#define IO_PORT_WRITE_CYCLES 2u ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0 + +/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available + +/// Indicate that JTAG communication mode is available at the Debug Port. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available. +//#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available. + +/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port. +/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255. +#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain +//#define DAP_JTAG_DEV_CNT 0 ///< Maximum number of JTAG devices on scan chain + +/// Default communication mode on the Debug Access Port. +/// Used for the command \ref DAP_Connect when Port Default mode is selected. +#define DAP_DEFAULT_PORT 1u ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG. + +/// Default communication speed on the Debug Access Port for SWD and JTAG mode. +/// Used to initialize the default SWD/JTAG clock frequency. +/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting. +#define DAP_DEFAULT_SWJ_CLOCK 1000000u ///< Default SWD/JTAG clock frequency in Hz. + +/// Maximum Package Size for Command and Response data. +/// This configuration settings is used to optimized the communication performance with the +/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB. +#define DAP_PACKET_SIZE 64u ///< USB: 64 = Full-Speed, 1024 = High-Speed. + +/// Maximum Package Buffers for Command and Response data. +/// This configuration settings is used to optimized the communication performance with the +/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the +/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB. +//#define DAP_PACKET_COUNT 64U ///< Buffers: 64 = Full-Speed, 4 = High-Speed. +#define DAP_PACKET_COUNT 4U ///< Buffers: 64 = Full-Speed, 4 = High-Speed. + +/// Indicate that UART Serial Wire Output (SWO) trace is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available + +/// Maximum SWO UART Baudrate +#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz + +/// Indicate that Manchester Serial Wire Output (SWO) trace is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available + +/// SWO Trace Buffer Size. +#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n). + +/// SWO Streaming Trace. +#define SWO_STREAM 0U ///< SWO Streaming Trace: 1 = available, 0 = not available. + +/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. +#define TIMESTAMP_CLOCK 0U ///< Timestamp clock in Hz (0 = timestamps not supported). +/// Debug Unit is connected to fixed Target Device. +/// The Debug Unit may be part of an evaluation board and always connected to a fixed +/// known device. In this case a Device Vendor and Device Name string is stored which +/// may be used by the debugger or IDE to configure device parameters. +#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown; + +#if TARGET_DEVICE_FIXED +#define TARGET_DEVICE_VENDOR "ARM" ///< String indicating the Silicon Vendor +#define TARGET_DEVICE_NAME "Cortex-M0" ///< String indicating the Target Device +#endif + +/** Get Vendor ID string. +\param str Pointer to buffer to store the string. +\return String length. +*/ +__STATIC_INLINE uint8_t DAP_GetVendorString(char *str) +{ + (void) str; + return (0U); +} + +/** Get Product ID string. +\param str Pointer to buffer to store the string. +\return String length. +*/ +__STATIC_INLINE uint8_t DAP_GetProductString(char *str) +{ + (void) str; + return (0U); +} + +/** Get Serial Number string. +\param str Pointer to buffer to store the string. +\return String length. +*/ +__STATIC_INLINE uint8_t DAP_GetSerNumString(char *str) +{ + (void) str; + return (0U); +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access +\ingroup DAP_ConfigIO_gr +@{ + +Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode +and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug +interface of a device. The following I/O Pins are provided: + +JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode +---------------------------- | -------------------- | --------------------------------------------- +TCK: Test Clock | SWCLK: Clock | Output Push/Pull +TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data) +TDI: Test Data Input | | Output Push/Pull +TDO: Test Data Output | | Input +nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor +nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor + + +DAP Hardware I/O Pin Access Functions +------------------------------------- +The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to +these I/O Pins. + +For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only. +This functions are provided to achieve faster I/O that is possible with some advanced GPIO +peripherals that can independently write/read a single I/O pin without affecting any other pins +of the same I/O port. The following SWDIO I/O Pin functions are provided: + - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware. + - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware. + - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed. + - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed. +*/ + + +// Configure DAP I/O pins ------------------------------ + +/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET. +Configures the DAP Hardware I/O pins for JTAG mode: + - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level. + - TDO to input mode. +*/ +static __inline void PORT_JTAG_SETUP (void) { + ; +} + +/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. +Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: + - SWCLK, SWDIO, nRESET to output mode and set to default high level. + - TDI, nTRST to HighZ mode (pins are unused in SWD mode). +*/ +static __inline void PORT_SWD_SETUP(void) +{ + /* Modified ANMD */ + SWD_SET_SCK_HI; + SWD_SET_SDA_HI; + SWD_SET_XRES_HI; + SWD_SET_SDA_OUT; + SWD_SET_SCK_OUT; + SWD_SET_XRES_OUT; +} + +/** Disable JTAG/SWD I/O Pins. +Disables the DAP Hardware I/O pins which configures: + - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode. +*/ +static __inline void PORT_OFF(void) +{ + SWD_SET_SCK_IN; + SWD_SET_SDA_IN; + SWD_SET_XRES_IN; + + isTargetAcquired = false; +} + + +// SWCLK/TCK I/O pin ------------------------------------- + +/** SWCLK/TCK I/O pin: Get Input. +\return Current status of the SWCLK/TCK DAP hardware I/O pin. +*/ +static __inline uint32_t PIN_SWCLK_TCK_IN(void) +{ + return (SWD_GET_SCL); +} + +/** SWCLK/TCK I/O pin: Set Output to High. +Set the SWCLK/TCK DAP hardware I/O pin to high level. +*/ +static __inline void PIN_SWCLK_TCK_SET(void) +{ + SWD_SET_SCK_HI; +} + +/** SWCLK/TCK I/O pin: Set Output to Low. +Set the SWCLK/TCK DAP hardware I/O pin to low level. +*/ +static __inline void PIN_SWCLK_TCK_CLR(void) +{ + SWD_SET_SCK_LO; +} + + +// SWDIO/TMS Pin I/O -------------------------------------- + +/** SWDIO/TMS I/O pin: Get Input. +\return Current status of the SWDIO/TMS DAP hardware I/O pin. +*/ +static __inline uint32_t PIN_SWDIO_TMS_IN(void) +{ + return (SWD_GET_SDA); +} + +/** SWDIO/TMS I/O pin: Set Output to High. +Set the SWDIO/TMS DAP hardware I/O pin to high level. +*/ +static __inline void PIN_SWDIO_TMS_SET(void) +{ + SWD_SET_SDA_HI; +} + +/** SWDIO/TMS I/O pin: Set Output to Low. +Set the SWDIO/TMS DAP hardware I/O pin to low level. +*/ +static __inline void PIN_SWDIO_TMS_CLR(void) +{ + SWD_SET_SDA_LO; +} + +/** SWDIO I/O pin: Get Input (used in SWD mode only). +\return Current status of the SWDIO DAP hardware I/O pin. +*/ +static __inline uint32_t PIN_SWDIO_IN(void) +{ + return (SWD_GET_SDA); +} + +/** SWDIO I/O pin: Set Output (used in SWD mode only). +\param bit Output value for the SWDIO DAP hardware I/O pin. +*/ +static __inline void PIN_SWDIO_OUT(uint32_t bit) +{ + SWD_SDA = bit; +} + +/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only). +Configure the SWDIO DAP hardware I/O pin to output mode. This function is +called prior \ref PIN_SWDIO_OUT function calls. +*/ +static __inline void PIN_SWDIO_OUT_ENABLE(void) +{ + SWD_SET_SDA_OUT; +} + +/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). +Configure the SWDIO DAP hardware I/O pin to input mode. This function is +called prior \ref PIN_SWDIO_IN function calls. +*/ +static __inline void PIN_SWDIO_OUT_DISABLE(void) +{ + SWD_SET_SDA_IN; +} + + +// TDI Pin I/O --------------------------------------------- + +// TDI Pin I/O --------------------------------------------- + +/** TDI I/O pin: Get Input. +\return Current status of the TDI DAP hardware I/O pin. +*/ +static __inline uint32_t PIN_TDI_IN(void) +{ + return (0); +} + +/** TDI I/O pin: Set Output. +\param bit Output value for the TDI DAP hardware I/O pin. +*/ +static __inline void PIN_TDI_OUT(uint32_t bit) +{ + (void) (bit); +} + + +// TDO Pin I/O --------------------------------------------- + +/** TDO I/O pin: Get Input. +\return Current status of the TDO DAP hardware I/O pin. +*/ +static __inline uint32_t PIN_TDO_IN(void) +{ + return (0); +} + + +// nTRST Pin I/O ------------------------------------------- + +/** nTRST I/O pin: Get Input. +\return Current status of the nTRST DAP hardware I/O pin. +*/ +static __inline uint32_t PIN_nTRST_IN(void) +{ + return (0); +} + +/** nTRST I/O pin: Set Output. +\param bit JTAG TRST Test Reset pin status: + - 0: issue a JTAG TRST Test Reset. + - 1: release JTAG TRST Test Reset. +*/ +static __inline void PIN_nTRST_OUT(uint32_t bit) +{ + (void) (bit); +} + +// nRESET Pin I/O------------------------------------------ + +/** nRESET I/O pin: Get Input. +\return Current status of the nRESET DAP hardware I/O pin. +*/ +static __inline uint32_t PIN_nRESET_IN(void) +{ + return (SWD_GET_XRES); +} + +/** nRESET I/O pin: Set Output. +\param bit target device hardware reset pin status: + - 0: issue a device hardware reset. + - 1: release device hardware reset. +*/ +static __inline void PIN_nRESET_OUT(uint32_t bit) +{ + if (bit) + { + SWD_SET_XRES_HI; + } + else + { + SWD_SET_XRES_LO; + } +} + +///@} + + + +//************************************************************************************************** +/** +\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs +\ingroup DAP_ConfigIO_gr +@{ + +CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit. + +It is recommended to provide the following LEDs for status indication: + - Connect LED: is active when the DAP hardware is connected to a debugger. + - Running LED: is active when the debugger has put the target device into running state. +*/ + +/** Debug Unit: Set status of Connected LED. +\param bit status of the Connect LED. + - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit. + - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit. +*/ +static __inline void LED_CONNECTED_OUT(uint32_t bit) +{ + (void) (bit); +} + +/** Debug Unit: Set status Target Running LED. +\param bit status of the Target Running LED. + - 1: Target Running LED ON: program execution in target started. + - 0: Target Running LED OFF: program execution in target stopped. +*/ +/*static __inline void LED_RUNNING_OUT (uint32_t bit) {}*/ +static __inline void LED_RUNNING_OUT(uint32_t bit) +{ + (void) (bit); +} +/** Get timestamp of Test Domain Timer. +\return Current timestamp value. +*/ +__STATIC_INLINE uint32_t TIMESTAMP_GET(void) +{ + return (DWT->CYCCNT); +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization +\ingroup DAP_ConfigIO_gr +@{ + +CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP. +*/ + +/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized). +This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the +Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set: + - I/O clock system enabled. + - all I/O pins: input buffer enabled, output pins are set to HighZ mode. + - for nTRST, nRESET a weak pull-up (if available) is enabled. + - LED output pins are enabled and LEDs are turned off. +*/ +static __inline void DAP_SETUP(void) +{ + SWD_SET_SCK_IN; + SWD_SET_SDA_IN; + SWD_SET_XRES_IN; + + SWD_SET_SDA_HI; + SWD_SET_SCK_HI; + SWD_SET_XRES_HI; +} + +/** Reset Target Device with custom specific I/O pin or command sequence. +This function allows the optional implementation of a device specific reset sequence. +It is called when the command \ref DAP_ResetTarget and is for example required +when a device needs a time-critical unlock sequence that enables the debug port. +\return 0 = no device specific reset sequence is implemented.\n + 1 = a device specific reset sequence is implemented. +*/ +static __inline uint8_t RESET_TARGET(void) +{ + /* preserve current reset drive mode */ + uint8_t resetDriveMode = CyPins_ReadPinDriveMode(SWDXRES_0); + + /* set XRES to low for RESET_DELAY usec*/ + CyPins_SetPinDriveMode(SWDXRES_0, SWDXRES_DM_STRONG); + SWD_SET_XRES_LO; + CyDelayUs(RESET_DELAY); + + /* set XRES hi, than restore original drive mode */ + SWD_SET_XRES_HI; + CyPins_SetPinDriveMode(SWDXRES_0, resetDriveMode); + + /* "1u" indicated that device reset is implemeted */ + return (1u); +} + +///@} + + +#endif /* __DAP_CONFIG_H__ */ + diff --git a/source/hic_hal/cypress/psoc5lp/FlashPrg.c b/source/hic_hal/cypress/psoc5lp/FlashPrg.c new file mode 100644 index 0000000000..b9ca517ee9 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/FlashPrg.c @@ -0,0 +1,214 @@ +/******************************************************************************* + +* @file FlashPrg.C +* @brief Flash Programming Functions adapted for CY8C5xxLP Device 258kB Flash +* from Cypress Semiconductor +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "CY8C5xxLP.H" //Registers/constants of CY8C5xLP device +#include "CyFlash.h" + +//Results constants +#define SUCCESS (0x00) +#define FAIL (0x01) + +//Chip characteristics constants +#define ROW_SIZE (0x100u) +#define ROW_ADDITIONAL_SIZE (0x020u) +#define ROWS_COUNT (0x100u) +#define EEPROM_ARRAY_ID (0x40u) +#define EEPROM_ROW_SIZE (0x10u) +#define ERASED_VALUE (0x00u) + +#define ARRAY_ID(addr) ((addr >> 16) & 0xFFu) +#define ROW_ID(addr) ((addr >> 8) & 0xFFu) +#define EEPROM_ROW_ID(addr) ((addr >> 4) & 0xFFu) + +/************************************************************************* + * Purpose: Checks if all bytes in given row are 0s + * Parameters: + * IN addr - address of row + * IN blockSize - size of row + * Return: + * 0 - empty, 1 - non-empty (at least one bit is HIGH) + *************************************************************************/ +int IsBlockEmpty(unsigned long addr, unsigned long blockSize) +{ + int i; + unsigned char* chipData = (unsigned char*) addr; //read directly from FLASH + for (i = 0; i < blockSize; i++) + { + if (chipData[i] != ERASED_VALUE) + return FAIL; + } + return SUCCESS; +} + +/************************************************************************* +* Purpose: Verify if two buffers are identical +* Parameters: +* IN size - size of buffers to be compared +* IN buf1 - first buffer +* IN buf1 - second buffer +* Return: +* 0 - empty, 1 - non-empty (at least one bit is HIGH) +*************************************************************************/ +int AreBuffersIdentical(unsigned int size, unsigned char *buf1, + unsigned char *buf2) +{ + int i; + for (i = 0; i < size; i++) + { + if (buf1[i] != buf2[i]) + return FAIL; + } + return SUCCESS; +} + +/************************************************************************* +* Purpose: Erases the addressed row and then programs it with data +* both user data and ECC/configurtation data. +* Parameter: +* IN arrayID - Array ID address +* IN rowID - Row ID +* IN size - Size of Row +* OUT buf - Buffer which is writing to the Flash +* Return: +* 0 - empty, 1 - non-empty (at least one bit is HIGH) +*************************************************************************/ +long WriteRow(unsigned int arrayID, long rowID, long size, unsigned char *buf) +{ + return CyWriteRowData(arrayID, rowID, buf); +} + +/************************************************************************* +* Purpose: Erases the addressed row. +* Parameter: +* IN address - flash address +* Return: +* 0 - empty, 1 - non-empty (at least one bit is HIGH) +*************************************************************************/ +int EraseSector(unsigned long addr) +{ + long hr = SUCCESS; + unsigned int arrayID = ARRAY_ID(addr); + unsigned int rowID = ROW_ID(addr); + + hr = CyFlash_EraseRow(arrayID, rowID); + + return hr; +} + + +/************************************************************************* +* Purpose: Initialize Flash Programming Functions +* Parameter: +* IN adr - Device Base Address +* IN clk - Clock Frequency (Hz) +* IN fnc - Function Code (1 - Erase, 2 - Program, 3 - Verify) +* Return: +* 0 - empty, 1 - non-empty (at least one bit is HIGH) +*************************************************************************/ +int Init(unsigned long adr, unsigned long clk, unsigned long fnc) +{ + CySetTemp(); + return SUCCESS; // Finished without Errors +} + +/************************************************************************* +* Purpose: De-Initialize Flash Programming Functions +* Parameter: +* IN fnc - Function Code (1 - Erase, 2 - Program, 3 - Verify) +* Return: +* 0 - empty, 1 - non-empty (at least one bit is HIGH) +*************************************************************************/ +int UnInit(unsigned long fnc) +{ + return SUCCESS; // Finished without Errors +} + +/************************************************************************* +* Purpose: Program Page in Flash Memory +* Parameter: +* IN adr - Page Start Address +* IN sz - Page Size +* IN buf - Page Data +* Return: +* 0 - empty, 1 - non-empty (at least one bit is HIGH) +*************************************************************************/ +int ProgramPage(unsigned long addr, unsigned long sz, unsigned char *buf) +{ + unsigned int hr, i; + unsigned char data[ROW_SIZE+ROW_ADDITIONAL_SIZE]; + unsigned char* eepromData; //read directly from EEPROM + + unsigned int arrayID = ARRAY_ID(addr); + unsigned int rowID = ROW_ID(addr); + + if (sz > ROW_SIZE) + { + sz = ROW_SIZE; + } + for (i = 0; i < sz; i++) + { + data[i] = buf[i]; + } + for (i = sz; i < (ROW_SIZE+ROW_ADDITIONAL_SIZE); i++) + { + data[i] = 0x00u; + } + + //Programming Row Size is 256 bytes, but each row has additional 32-bytes + //Configuration Data. + //During programming process, the row latch needs to be loaded with all + //the 288 bytes. In this scenario, the 256 code bytes are concatenated + //with the 32 zero bytes: + //There are two reasons for this: + // 1. uVision doesn't support Configuration data programming. + // 2. We always program rows by 288 bytes, since it coveres two cases: + // a) When Configuration data is supported by the silicon. + // Then 32-bytes will be programmed with zero bytes. + // b) And when configuration data isn't supported by the silicon. + // Then these extra 32-bytes will be ignored by SPC. + //This step is done to program all flash rows. + + if ((addr >= EEPROM_HEX_START_ADDR) && (addr < EEPROM_HEX_END_ADDR)) //Program EEPROM if the address in range of 0x00040000 ... 0x00040800 + { + for (i = 0; i < ROW_SIZE; i += EEPROM_ROW_SIZE) + { + rowID = EEPROM_ROW_ID((addr + i)); //Calculate rowID + eepromData = (unsigned char *) (EEPROM_START_ADDR + (addr & 0xFFFFu) + i); //Set address to EEPROM memory by given address - adr + + if (SUCCESS != AreBuffersIdentical(EEPROM_ROW_SIZE, data + i, eepromData)) //If 16 byte EEPROM row buffer is not identical with 16 byte hex EEPROM row buffer + { //then program row to the EEPROM memory + if (SUCCESS != WriteRow(EEPROM_ARRAY_ID, rowID, EEPROM_ROW_SIZE, data + i)) + { + return FAIL; + } + } + } + return SUCCESS; + } + else + { //Program Flash if the address in range of 0x00000000 .. 0x00040000 + hr = WriteRow(arrayID, rowID, ROW_SIZE+ROW_ADDITIONAL_SIZE, data); + } + + return hr; +} diff --git a/source/hic_hal/cypress/psoc5lp/IO_Config.h b/source/hic_hal/cypress/psoc5lp/IO_Config.h new file mode 100644 index 0000000000..b5b8540082 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/IO_Config.h @@ -0,0 +1,38 @@ +/******************************************************************************* + +* @file CY8C5xxLP.h +* @brief This file provides special hw functions for Cypress kits +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "psoc5lp.h" +#include "CyLib.h" +#include "compiler.h" +#include "daplink.h" + +// This GPIO configuration is only valid for the PSOC5LP HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_PSOC5LP); + +bool kit_has_three_led(void); +bool kit_has_two_buttons(void); +bool kit_has_sflash_restriction(void); + +#endif diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/ApplicationButton.c b/source/hic_hal/cypress/psoc5lp/PSoC5/ApplicationButton.c new file mode 100644 index 0000000000..9181197a78 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/ApplicationButton.c @@ -0,0 +1,234 @@ +/******************************************************************************* +* File Name: ApplicationButton.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "cytypes.h" +#include "ApplicationButton.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + ApplicationButton__PORT == 15 && ((ApplicationButton__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: ApplicationButton_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet ApplicationButton_SUT.c usage_ApplicationButton_Write +*******************************************************************************/ +void ApplicationButton_Write(uint8 value) +{ + uint8 staticBits = (ApplicationButton_DR & (uint8)(~ApplicationButton_MASK)); + ApplicationButton_DR = staticBits | ((uint8)(value << ApplicationButton_SHIFT) & ApplicationButton_MASK); +} + + +/******************************************************************************* +* Function Name: ApplicationButton_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet ApplicationButton_SUT.c usage_ApplicationButton_SetDriveMode +*******************************************************************************/ +void ApplicationButton_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(ApplicationButton_0, mode); +} + + +/******************************************************************************* +* Function Name: ApplicationButton_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet ApplicationButton_SUT.c usage_ApplicationButton_Read +*******************************************************************************/ +uint8 ApplicationButton_Read(void) +{ + return (ApplicationButton_PS & ApplicationButton_MASK) >> ApplicationButton_SHIFT; +} + + +/******************************************************************************* +* Function Name: ApplicationButton_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred ApplicationButton_Read() API because the +* ApplicationButton_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet ApplicationButton_SUT.c usage_ApplicationButton_ReadDataReg +*******************************************************************************/ +uint8 ApplicationButton_ReadDataReg(void) +{ + return (ApplicationButton_DR & ApplicationButton_MASK) >> ApplicationButton_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(ApplicationButton_INTSTAT) + + /******************************************************************************* + * Function Name: ApplicationButton_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use ApplicationButton_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - ApplicationButton_0_INTR (First pin in the list) + * - ApplicationButton_1_INTR (Second pin in the list) + * - ... + * - ApplicationButton_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet ApplicationButton_SUT.c usage_ApplicationButton_SetInterruptMode + *******************************************************************************/ + void ApplicationButton_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & ApplicationButton_0_INTR) != 0u) + { + ApplicationButton_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: ApplicationButton_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet ApplicationButton_SUT.c usage_ApplicationButton_ClearInterrupt + *******************************************************************************/ + uint8 ApplicationButton_ClearInterrupt(void) + { + return (ApplicationButton_INTSTAT & ApplicationButton_MASK) >> ApplicationButton_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/ApplicationButton.h b/source/hic_hal/cypress/psoc5lp/PSoC5/ApplicationButton.h new file mode 100644 index 0000000000..67c714acaf --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/ApplicationButton.h @@ -0,0 +1,173 @@ +/******************************************************************************* +* File Name: ApplicationButton.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_ApplicationButton_H) /* Pins ApplicationButton_H */ +#define CY_PINS_ApplicationButton_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "ApplicationButton_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + ApplicationButton__PORT == 15 && ((ApplicationButton__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void ApplicationButton_Write(uint8 value); +void ApplicationButton_SetDriveMode(uint8 mode); +uint8 ApplicationButton_ReadDataReg(void); +uint8 ApplicationButton_Read(void); +void ApplicationButton_SetInterruptMode(uint16 position, uint16 mode); +uint8 ApplicationButton_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the ApplicationButton_SetDriveMode() function. + * @{ + */ + #define ApplicationButton_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define ApplicationButton_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define ApplicationButton_DM_RES_UP PIN_DM_RES_UP + #define ApplicationButton_DM_RES_DWN PIN_DM_RES_DWN + #define ApplicationButton_DM_OD_LO PIN_DM_OD_LO + #define ApplicationButton_DM_OD_HI PIN_DM_OD_HI + #define ApplicationButton_DM_STRONG PIN_DM_STRONG + #define ApplicationButton_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define ApplicationButton_MASK ApplicationButton__MASK +#define ApplicationButton_SHIFT ApplicationButton__SHIFT +#define ApplicationButton_WIDTH 1u + +/* Interrupt constants */ +#if defined(ApplicationButton__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in ApplicationButton_SetInterruptMode() function. + * @{ + */ + #define ApplicationButton_INTR_NONE (uint16)(0x0000u) + #define ApplicationButton_INTR_RISING (uint16)(0x0001u) + #define ApplicationButton_INTR_FALLING (uint16)(0x0002u) + #define ApplicationButton_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define ApplicationButton_INTR_MASK (0x01u) +#endif /* (ApplicationButton__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define ApplicationButton_PS (* (reg8 *) ApplicationButton__PS) +/* Data Register */ +#define ApplicationButton_DR (* (reg8 *) ApplicationButton__DR) +/* Port Number */ +#define ApplicationButton_PRT_NUM (* (reg8 *) ApplicationButton__PRT) +/* Connect to Analog Globals */ +#define ApplicationButton_AG (* (reg8 *) ApplicationButton__AG) +/* Analog MUX bux enable */ +#define ApplicationButton_AMUX (* (reg8 *) ApplicationButton__AMUX) +/* Bidirectional Enable */ +#define ApplicationButton_BIE (* (reg8 *) ApplicationButton__BIE) +/* Bit-mask for Aliased Register Access */ +#define ApplicationButton_BIT_MASK (* (reg8 *) ApplicationButton__BIT_MASK) +/* Bypass Enable */ +#define ApplicationButton_BYP (* (reg8 *) ApplicationButton__BYP) +/* Port wide control signals */ +#define ApplicationButton_CTL (* (reg8 *) ApplicationButton__CTL) +/* Drive Modes */ +#define ApplicationButton_DM0 (* (reg8 *) ApplicationButton__DM0) +#define ApplicationButton_DM1 (* (reg8 *) ApplicationButton__DM1) +#define ApplicationButton_DM2 (* (reg8 *) ApplicationButton__DM2) +/* Input Buffer Disable Override */ +#define ApplicationButton_INP_DIS (* (reg8 *) ApplicationButton__INP_DIS) +/* LCD Common or Segment Drive */ +#define ApplicationButton_LCD_COM_SEG (* (reg8 *) ApplicationButton__LCD_COM_SEG) +/* Enable Segment LCD */ +#define ApplicationButton_LCD_EN (* (reg8 *) ApplicationButton__LCD_EN) +/* Slew Rate Control */ +#define ApplicationButton_SLW (* (reg8 *) ApplicationButton__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define ApplicationButton_PRTDSI__CAPS_SEL (* (reg8 *) ApplicationButton__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define ApplicationButton_PRTDSI__DBL_SYNC_IN (* (reg8 *) ApplicationButton__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define ApplicationButton_PRTDSI__OE_SEL0 (* (reg8 *) ApplicationButton__PRTDSI__OE_SEL0) +#define ApplicationButton_PRTDSI__OE_SEL1 (* (reg8 *) ApplicationButton__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define ApplicationButton_PRTDSI__OUT_SEL0 (* (reg8 *) ApplicationButton__PRTDSI__OUT_SEL0) +#define ApplicationButton_PRTDSI__OUT_SEL1 (* (reg8 *) ApplicationButton__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define ApplicationButton_PRTDSI__SYNC_OUT (* (reg8 *) ApplicationButton__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(ApplicationButton__SIO_CFG) + #define ApplicationButton_SIO_HYST_EN (* (reg8 *) ApplicationButton__SIO_HYST_EN) + #define ApplicationButton_SIO_REG_HIFREQ (* (reg8 *) ApplicationButton__SIO_REG_HIFREQ) + #define ApplicationButton_SIO_CFG (* (reg8 *) ApplicationButton__SIO_CFG) + #define ApplicationButton_SIO_DIFF (* (reg8 *) ApplicationButton__SIO_DIFF) +#endif /* (ApplicationButton__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(ApplicationButton__INTSTAT) + #define ApplicationButton_INTSTAT (* (reg8 *) ApplicationButton__INTSTAT) + #define ApplicationButton_SNAP (* (reg8 *) ApplicationButton__SNAP) + + #define ApplicationButton_0_INTTYPE_REG (* (reg8 *) ApplicationButton__0__INTTYPE) +#endif /* (ApplicationButton__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_ApplicationButton_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/ApplicationButton_aliases.h b/source/hic_hal/cypress/psoc5lp/PSoC5/ApplicationButton_aliases.h new file mode 100644 index 0000000000..6a217b454d --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/ApplicationButton_aliases.h @@ -0,0 +1,44 @@ +/******************************************************************************* +* File Name: ApplicationButton.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_ApplicationButton_ALIASES_H) /* Pins ApplicationButton_ALIASES_H */ +#define CY_PINS_ApplicationButton_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define ApplicationButton_0 (ApplicationButton__0__PC) +#define ApplicationButton_0_INTR ((uint16)((uint16)0x0001u << ApplicationButton__0__SHIFT)) + +#define ApplicationButton_INTR_ALL ((uint16)(ApplicationButton_0_INTR)) + +#endif /* End Pins ApplicationButton_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Bootloadable.c b/source/hic_hal/cypress/psoc5lp/PSoC5/Bootloadable.c new file mode 100644 index 0000000000..0a56bc49a1 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Bootloadable.c @@ -0,0 +1,279 @@ +/****************************************************************************//** +* \file Bootloadable.c +* \version 1.60 +* +* \brief +* Provides an API for the Bootloadable application. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "Bootloadable.h" + +/** + \defgroup functions_group Functions + @{ +*/ + +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) +static cystatus Bootloadable_WriteFlashByte(const uint32 address, const uint8 inputValue) CYLARGE \ + ; +#endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ + +/******************************************************************************* +* Function Name: Bootloadable_Load +****************************************************************************//** +* +* \brief +* Schedules the Bootloader/Launcher to be launched and then performs +* a software reset to launch it +* +* \return +* This method will never return. It will load a new application and reset +* the device. +* +*******************************************************************************/ +void Bootloadable_Load(void) +{ + /* Schedule Bootloader to start after reset */ + Bootloadable_SET_RUN_TYPE(Bootloadable_SCHEDULE_BTLDR); + + CySoftwareReset(); +} + +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) +/******************************************************************************* +* Function Name: Bootloadable_GetActiveApplication +****************************************************************************//** +* +* \brief +* Gets the application which will be loaded after a next reset event. +* NOTE Intended for the combination project type ONLY! +* +* \return +* A number of the current active application set in the metadata section. +* \n 0 - app#0 is set as active. +* \n 1 - app#1 is set as active. +* +* \note If neither of the applications is set active, then the API returns 0x02. +* +*******************************************************************************/ +uint8 Bootloadable_GetActiveApplication(void) CYSMALL \ + +{ + uint8 result = Bootloadable_MD_BTLDB_ACTIVE_NONE; + + if (0u != Bootloadable_GET_CODE_DATA( \ + Bootloadable_MD_BTLDB_ACTIVE_OFFSET(Bootloadable_MD_BTLDB_ACTIVE_0))) + { + result = Bootloadable_MD_BTLDB_ACTIVE_0; + } + else if (0u != Bootloadable_GET_CODE_DATA( \ + Bootloadable_MD_BTLDB_ACTIVE_OFFSET(Bootloadable_MD_BTLDB_ACTIVE_1))) + { + result = Bootloadable_MD_BTLDB_ACTIVE_1; + } + else + { + /*Do nothing, result is none*/ + } + + return (result); +} + +/******************************************************************************* +* Function Name: Bootloadable_SetActiveApplication +****************************************************************************//** +* +* \brief +* Sets the application which will be loaded after a next reset event. +* +* \details +* Theory: +* This API sets in the Flash (metadata section) the given active application +* number. +* +* NOTE The active application number is not set directly, but the boolean +* mark instead means that the application is active or not for the relative +* metadata. Both metadata sections are updated. For example, if the second +* application is to be set active, then in the metadata section for the first +* application there will be a "0" written, which means that it is not active, and +* for the second metadata section there will be a "1" written, which means that it is +* active. +* +* NOTE Intended for the combination project type ONLY! +* +* \param appId +* The active application number to be written to flash (metadata section) +* NOTE Possible values are: +* 0 - for the first application +* 1 - for the second application. +* Any other number is considered invalid. +* +* \return +* A status of writing to flash operation. +* \n CYRET_SUCCESS - Returned if appId was successfully changed. +* \n CYRET_BAD_PARAM - Returned if the parameter appID passed to the function has the +* same value as the active application ID. +* \note - The other non-zero value is considered as a failure during writing to flash. +* +* \note - This API does not update Bootloader_activeApp variable. +* +*******************************************************************************/ +cystatus Bootloadable_SetActiveApplication(uint8 appId) CYSMALL \ + +{ + cystatus result = CYRET_SUCCESS; + + uint8 CYDATA idx; + + /* If invalid application number */ + if (appId > Bootloadable_MD_BTLDB_ACTIVE_1) + { + result = CYRET_BAD_PARAM; + } + else + { + /* If appID has same value as active application ID */ + if (1u == Bootloadable_GET_CODE_DATA(Bootloadable_MD_BTLDB_ACTIVE_OFFSET(appId))) + { + result = CYRET_BAD_PARAM; + } + else + { + /* Updating metadata section */ + for(idx = 0u; idx < Bootloadable_MAX_NUM_OF_BTLDB; idx++) + { + result |= Bootloadable_WriteFlashByte((uint32) Bootloadable_MD_BTLDB_ACTIVE_OFFSET(idx), \ + (uint8)(idx == appId)); + } + } + } + + return (result); +} + +/******************************************************************************* +* Function Name: Bootloadable_WriteFlashByte +****************************************************************************//** +* +* \brief +* This API writes to flash the specified data. +* +* \param address +* The address in flash. +* +* \param inputValue +* One-byte data. +* +* \return +* A status of the writing to flash procedure. +* +*******************************************************************************/ +static cystatus Bootloadable_WriteFlashByte(const uint32 address, const uint8 inputValue) CYLARGE \ + +{ + cystatus result = CYRET_SUCCESS; + uint32 flsAddr = address - CYDEV_FLASH_BASE; + uint8 rowData[CYDEV_FLS_ROW_SIZE]; + + #if !(CY_PSOC4) + uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE); + #endif /* !(CY_PSOC4) */ + + #if (CY_PSOC4) + uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE); + #else + uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE); + #endif /* (CY_PSOC4) */ + + uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE); + uint16 idx; + + for(idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++) + { + rowData[idx] = (uint8)Bootloadable_GET_CODE_DATA(baseAddr + idx); + } + + rowData[address % CYDEV_FLS_ROW_SIZE] = inputValue; + + #if(CY_PSOC4) + result = CySysFlashWriteRow((uint32) rowNum, rowData); + #else + result = CyWriteRowData(arrayId, rowNum, rowData); + #endif /* (CY_PSOC4) */ + + #if(CY_PSOC5) + /*************************************************************************** + * When writing to flash, data in the instruction cache can become stale. + * Therefore, the cache data does not correlate to the data just written to + * flash. A call to CyFlushCache() is required to invalidate the data in the + * cache and force fresh information to be loaded from flash. + ***************************************************************************/ + CyFlushCache(); + #endif /* (CY_PSOC5) */ + return (result); +} +#endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ +/** @} functions_group */ + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +*******************************************************************************/ +void Bootloadable_SetFlashByte(uint32 address, uint8 runType) +{ + uint32 flsAddr = address - CYDEV_FLASH_BASE; + uint8 rowData[CYDEV_FLS_ROW_SIZE]; + + #if !(CY_PSOC4) + uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE); + #endif /* !(CY_PSOC4) */ + + #if (CY_PSOC4) + uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE); + #else + uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE); + #endif /* (CY_PSOC4) */ + + uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE); + uint16 idx; + + + for (idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++) + { + rowData[idx] = Bootloadable_GET_CODE_DATA(baseAddr + idx); + } + rowData[address % CYDEV_FLS_ROW_SIZE] = runType; + + #if(CY_PSOC4) + (void) CySysFlashWriteRow((uint32) rowNum, rowData); + #else + (void) CyWriteRowData(arrayId, rowNum, rowData); + #endif /* (CY_PSOC4) */ + + #if(CY_PSOC5) + /*************************************************************************** + * When writing to flash, data in the instruction cache can become obsolete. + * Therefore, the cache data does not correlate to the data just written to + * flash. A call to CyFlushCache() is required to invalidate the data in the + * cache and force fresh information to be loaded from flash. + ***************************************************************************/ + CyFlushCache(); + #endif /* (CY_PSOC5) */ +} + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Bootloadable.h b/source/hic_hal/cypress/psoc5lp/PSoC5/Bootloadable.h new file mode 100644 index 0000000000..84b52073e3 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Bootloadable.h @@ -0,0 +1,209 @@ +/****************************************************************************//** +* \file Bootloadable.c +* \version 1.60 +* +* \brief +* Provides an API for the Bootloadable application. The API includes a +* single function for starting the Bootloader. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + + +#ifndef CY_BOOTLOADABLE_Bootloadable_H +#define CY_BOOTLOADABLE_Bootloadable_H + +#include "cydevice_trm.h" +#include "CyFlash.h" + + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component Bootloadable_v1_60 requires cy_boot v3.0 or later +#endif /* !defined (CY_PSOC5LP) */ + + +#ifndef CYDEV_FLASH_BASE + #define CYDEV_FLASH_BASE CYDEV_FLS_BASE + #define CYDEV_FLASH_SIZE CYDEV_FLS_SIZE +#endif /* CYDEV_FLASH_BASE */ + +#if(CY_PSOC3) + #define Bootloadable_GET_CODE_DATA(idx) (*((uint8 CYCODE *) (idx))) +#else + #define Bootloadable_GET_CODE_DATA(idx) (*((uint8 *)(CYDEV_FLASH_BASE + (idx)))) +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* This variable is used by the Bootloader/Bootloadable components to schedule which +* application will be started after a software reset. +*******************************************************************************/ +#if (CY_PSOC4) + #if defined(__ARMCC_VERSION) + __attribute__ ((section(".bootloaderruntype"), zero_init)) + #elif defined (__GNUC__) + __attribute__ ((section(".bootloaderruntype"))) + #elif defined (__ICCARM__) + #pragma location=".bootloaderruntype" + #endif /* defined(__ARMCC_VERSION) */ + extern volatile uint32 cyBtldrRunType; +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* Gets the reason for a device reset +*******************************************************************************/ +#if(CY_PSOC4) + #define Bootloadable_RES_CAUSE_RESET_SOFT (0x10u) + #define Bootloadable_GET_RUN_TYPE \ + (((CY_GET_REG32(CYREG_RES_CAUSE) & Bootloadable_RES_CAUSE_RESET_SOFT) > 0u) \ + ? (cyBtldrRunType) \ + : 0u) +#else + #define Bootloadable_GET_RUN_TYPE (CY_GET_REG8(CYREG_RESET_SR0) & \ + (Bootloadable_START_BTLDR | Bootloadable_START_APP)) +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* Schedule the Bootloader/Bootloadable to be run after a software reset. +*******************************************************************************/ +#if(CY_PSOC4) + #define Bootloadable_SET_RUN_TYPE(x) (cyBtldrRunType = (x)) +#else + #define Bootloadable_SET_RUN_TYPE(x) CY_SET_REG8(CYREG_RESET_SR0, (x)) +#endif /* (CY_PSOC4) */ + + + +/*************************************** +* Function Prototypes +***************************************/ +extern void Bootloadable_Load(void) ; + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting from version 1.10. +*******************************************************************************/ +#define CYBTDLR_SET_RUN_TYPE(x) Bootloadable_SET_RUN_TYPE(x) + +/******************************************************************************* +* Bootloadable's declarations for in-app bootloading. +*******************************************************************************/ +#define Bootloadable_MD_BTLDB_ACTIVE_0 (0x00u) + +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + #define Bootloadable_MAX_NUM_OF_BTLDB (0x02u) + #define Bootloadable_MD_BTLDB_ACTIVE_1 (0x01u) + #define Bootloadable_MD_BTLDB_ACTIVE_NONE (0x02u) + #define Bootloadable_MD_SIZEOF (64u) + #define Bootloadable_MD_BASE_ADDR(appId) (CYDEV_FLASH_BASE + (CYDEV_FLASH_SIZE - ((uint32)(appId) * CYDEV_FLS_ROW_SIZE) - \ + Bootloadable_MD_SIZEOF)) + #define Bootloadable_MD_BTLDB_ACTIVE_OFFSET(appId) (Bootloadable_MD_BASE_ADDR(appId) + 16u) + +#else + #define Bootloadable_MAX_NUM_OF_BTLDB (0x01u) +#endif /* (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ + +/* Mask used to indicate starting application */ +#define Bootloadable_SCHEDULE_BTLDB (0x80u) +#define Bootloadable_SCHEDULE_BTLDR (0x40u) +#define Bootloadable_SCHEDULE_MASK (0xC0u) +/******************************************************************************* +* API prototypes +*******************************************************************************/ +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + uint8 Bootloadable_GetActiveApplication(void) CYSMALL \ + ; + cystatus Bootloadable_SetActiveApplication(uint8 appId) CYSMALL \ + ; +#endif /* (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting from version 1.20 +*******************************************************************************/ +#define Bootloadable_START_APP (0x80u) +#define Bootloadable_START_BTLDR (0x40u) +#define Bootloadable_META_DATA_SIZE (64u) +#define Bootloadable_META_APP_CHECKSUM_OFFSET (0u) + +#if(CY_PSOC3) + + #define Bootloadable_APP_ADDRESS uint16 + #define Bootloadable_GET_CODE_WORD(idx) (*((uint32 CYCODE *) (idx))) + + /* Offset by 2 from 32 bit start because only 16 bits are needed */ + #define Bootloadable_META_APP_ADDR_OFFSET (3u) + #define Bootloadable_META_APP_BL_LAST_ROW_OFFSET (7u) + #define Bootloadable_META_APP_BYTE_LEN_OFFSET (11u) + #define Bootloadable_META_APP_RUN_TYPE_OFFSET (15u) + +#else + + #define Bootloadable_APP_ADDRESS uint32 + #define Bootloadable_GET_CODE_WORD(idx) (*((uint32 *)(CYDEV_FLASH_BASE + (idx)))) + + #define Bootloadable_META_APP_ADDR_OFFSET (1u) + #define Bootloadable_META_APP_BL_LAST_ROW_OFFSET (5u) + #define Bootloadable_META_APP_BYTE_LEN_OFFSET (9u) + #define Bootloadable_META_APP_RUN_TYPE_OFFSET (13u) + +#endif /* (CY_PSOC3) */ + +#define Bootloadable_META_APP_ACTIVE_OFFSET (16u) +#define Bootloadable_META_APP_VERIFIED_OFFSET (17u) + +#define Bootloadable_META_APP_BL_BUILD_VER_OFFSET (18u) +#define Bootloadable_META_APP_ID_OFFSET (20u) +#define Bootloadable_META_APP_VER_OFFSET (22u) +#define Bootloadable_META_APP_CUST_ID_OFFSET (24u) + +#define Bootloadable_SetFlashRunType(runType) \ + Bootloadable_SetFlashByte(Bootloadable_MD_APP_RUN_ADDR(0), (runType)) + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +* +* If the obsoleted macro definitions are intended for the application, use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* NOTE Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +void Bootloadable_SetFlashByte(uint32 address, uint8 runType) ; +#if(CY_PSOC4) + #define Bootloadable_SOFTWARE_RESET CySoftwareReset() +#else + #define Bootloadable_SOFTWARE_RESET CySoftwareReset() +#endif /* (CY_PSOC4) */ + +#if(CY_PSOC4) + extern uint8 appRunType; +#endif /* (CY_PSOC4) */ + + +#endif /* CY_BOOTLOADABLE_Bootloadable_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Clk_Brea1.c b/source/hic_hal/cypress/psoc5lp/PSoC5/Clk_Brea1.c new file mode 100644 index 0000000000..339a5add51 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Clk_Brea1.c @@ -0,0 +1,531 @@ +/******************************************************************************* +* File Name: Clk_Brea1.c +* Version 2.20 +* +* Description: +* This file provides the source code to the API for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include +#include "Clk_Brea1.h" + +/* Clock Distribution registers. */ +#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD) +#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2) +#define BCFG2_MASK (0x80u) +#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK) +#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK) + +#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: Clk_Brea1_Start +******************************************************************************** +* +* Summary: +* Starts the clock. Note that on startup, clocks may be already running if the +* "Start on Reset" option is enabled in the DWR. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void Clk_Brea1_Start(void) +{ + /* Set the bit to enable the clock. */ + Clk_Brea1_CLKEN |= Clk_Brea1_CLKEN_MASK; + Clk_Brea1_CLKSTBY |= Clk_Brea1_CLKSTBY_MASK; +} + + +/******************************************************************************* +* Function Name: Clk_Brea1_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. If the settings of the clock are changed after calling this +* function, the clock may glitch when it is started. To avoid the clock +* glitch, use the StopBlock function. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void Clk_Brea1_Stop(void) +{ + /* Clear the bit to disable the clock. */ + Clk_Brea1_CLKEN &= (uint8)(~Clk_Brea1_CLKEN_MASK); + Clk_Brea1_CLKSTBY &= (uint8)(~Clk_Brea1_CLKSTBY_MASK); +} + + +#if(CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: Clk_Brea1_StopBlock +******************************************************************************** +* +* Summary: +* Stops the clock and waits for the hardware to actually be disabled before +* returning. This ensures that the clock is never truncated (high part of the +* cycle will terminate before the clock is disabled and the API returns). +* Note that the source clock must be running or this API will never return as +* a stopped clock cannot be disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void Clk_Brea1_StopBlock(void) +{ + if ((Clk_Brea1_CLKEN & Clk_Brea1_CLKEN_MASK) != 0u) + { +#if HAS_CLKDIST_LD_DISABLE + uint16 oldDivider; + + CLK_DIST_LD = 0u; + + /* Clear all the mask bits except ours. */ +#if defined(Clk_Brea1__CFG3) + CLK_DIST_AMASK = Clk_Brea1_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = Clk_Brea1_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* Clk_Brea1__CFG3 */ + + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + oldDivider = CY_GET_REG16(Clk_Brea1_DIV_PTR); + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + /* Clear the bit to disable the clock. */ + Clk_Brea1_CLKEN &= (uint8)(~Clk_Brea1_CLKEN_MASK); + Clk_Brea1_CLKSTBY &= (uint8)(~Clk_Brea1_CLKSTBY_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; + CY_SET_REG16(Clk_Brea1_DIV_PTR, oldDivider); +#endif /* HAS_CLKDIST_LD_DISABLE */ + } +} +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/******************************************************************************* +* Function Name: Clk_Brea1_StandbyPower +******************************************************************************** +* +* Summary: +* Sets whether the clock is active in standby mode. +* +* Parameters: +* state: 0 to disable clock during standby, nonzero to enable. +* +* Returns: +* None +* +*******************************************************************************/ +void Clk_Brea1_StandbyPower(uint8 state) +{ + if(state == 0u) + { + Clk_Brea1_CLKSTBY &= (uint8)(~Clk_Brea1_CLKSTBY_MASK); + } + else + { + Clk_Brea1_CLKSTBY |= Clk_Brea1_CLKSTBY_MASK; + } +} + + +/******************************************************************************* +* Function Name: Clk_Brea1_SetDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and, thus, the frequency. When the clock divider +* register is set to zero or changed from zero, the clock will be temporarily +* disabled in order to change the SSS mode bit. If the clock is enabled when +* SetDividerRegister is called, then the source clock must be running. +* +* Parameters: +* clkDivider: Divider register value (0-65,535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* restart: If nonzero, restarts the clock divider: the current clock cycle +* will be truncated and the new divide value will take effect immediately. If +* zero, the new divide value will take effect at the end of the current clock +* cycle. +* +* Returns: +* None +* +*******************************************************************************/ +void Clk_Brea1_SetDividerRegister(uint16 clkDivider, uint8 restart) + +{ + uint8 enabled; + + uint8 currSrc = Clk_Brea1_GetSourceRegister(); + uint16 oldDivider = Clk_Brea1_GetDividerRegister(); + + if (clkDivider != oldDivider) + { + enabled = Clk_Brea1_CLKEN & Clk_Brea1_CLKEN_MASK; + + if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u))) + { + /* Moving to/from SSS requires correct ordering to prevent halting the clock */ + if (oldDivider == 0u) + { + /* Moving away from SSS, set the divider first so when SSS is cleared we */ + /* don't halt the clock. Using the shadow load isn't required as the */ + /* divider is ignored while SSS is set. */ + CY_SET_REG16(Clk_Brea1_DIV_PTR, clkDivider); + Clk_Brea1_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + /* Moving to SSS, set SSS which then ignores the divider and we can set */ + /* it without bothering with the shadow load. */ + Clk_Brea1_MOD_SRC |= CYCLK_SSS; + CY_SET_REG16(Clk_Brea1_DIV_PTR, clkDivider); + } + } + else + { + + if (enabled != 0u) + { + CLK_DIST_LD = 0x00u; + + /* Clear all the mask bits except ours. */ +#if defined(Clk_Brea1__CFG3) + CLK_DIST_AMASK = Clk_Brea1_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = Clk_Brea1_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* Clk_Brea1__CFG3 */ + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + /* If clock is currently enabled, disable it if async or going from N-to-1*/ + if (((Clk_Brea1_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u)) + { +#if HAS_CLKDIST_LD_DISABLE + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + Clk_Brea1_CLKEN &= (uint8)(~Clk_Brea1_CLKEN_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; +#endif /* HAS_CLKDIST_LD_DISABLE */ + } + } + + /* Load divide value. */ + if ((Clk_Brea1_CLKEN & Clk_Brea1_CLKEN_MASK) != 0u) + { + /* If the clock is still enabled, use the shadow registers */ + CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider); + + CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u)); + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } + } + else + { + /* If the clock is disabled, set the divider directly */ + CY_SET_REG16(Clk_Brea1_DIV_PTR, clkDivider); + Clk_Brea1_CLKEN |= enabled; + } + } + } +} + + +/******************************************************************************* +* Function Name: Clk_Brea1_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 Clk_Brea1_GetDividerRegister(void) +{ + return CY_GET_REG16(Clk_Brea1_DIV_PTR); +} + + +/******************************************************************************* +* Function Name: Clk_Brea1_SetModeRegister +******************************************************************************** +* +* Summary: +* Sets flags that control the operating mode of the clock. This function only +* changes flags from 0 to 1; flags that are already 1 will remain unchanged. +* To clear flags, use the ClearModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void Clk_Brea1_SetModeRegister(uint8 modeBitMask) +{ + Clk_Brea1_MOD_SRC |= modeBitMask & (uint8)Clk_Brea1_MODE_MASK; +} + + +/******************************************************************************* +* Function Name: Clk_Brea1_ClearModeRegister +******************************************************************************** +* +* Summary: +* Clears flags that control the operating mode of the clock. This function +* only changes flags from 1 to 0; flags that are already 0 will remain +* unchanged. To set flags, use the SetModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void Clk_Brea1_ClearModeRegister(uint8 modeBitMask) +{ + Clk_Brea1_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(Clk_Brea1_MODE_MASK)); +} + + +/******************************************************************************* +* Function Name: Clk_Brea1_GetModeRegister +******************************************************************************** +* +* Summary: +* Gets the clock mode register value. +* +* Parameters: +* None +* +* Returns: +* Bit mask representing the enabled mode bits. See the SetModeRegister and +* ClearModeRegister descriptions for details about the mode bits. +* +*******************************************************************************/ +uint8 Clk_Brea1_GetModeRegister(void) +{ + return Clk_Brea1_MOD_SRC & (uint8)(Clk_Brea1_MODE_MASK); +} + + +/******************************************************************************* +* Function Name: Clk_Brea1_SetSourceRegister +******************************************************************************** +* +* Summary: +* Sets the input source of the clock. The clock must be disabled before +* changing the source. The old and new clock sources must be running. +* +* Parameters: +* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the +* following input sources: +* - CYCLK_SRC_SEL_SYNC_DIG +* - CYCLK_SRC_SEL_IMO +* - CYCLK_SRC_SEL_XTALM +* - CYCLK_SRC_SEL_ILO +* - CYCLK_SRC_SEL_PLL +* - CYCLK_SRC_SEL_XTALK +* - CYCLK_SRC_SEL_DSI_G +* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A +* See the Technical Reference Manual for details on clock sources. +* +* Returns: +* None +* +*******************************************************************************/ +void Clk_Brea1_SetSourceRegister(uint8 clkSource) +{ + uint16 currDiv = Clk_Brea1_GetDividerRegister(); + uint8 oldSrc = Clk_Brea1_GetSourceRegister(); + + if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching to Master and divider is 1, set SSS, which will output master, */ + /* then set the source so we are consistent. */ + Clk_Brea1_MOD_SRC |= CYCLK_SSS; + Clk_Brea1_MOD_SRC = + (Clk_Brea1_MOD_SRC & (uint8)(~Clk_Brea1_SRC_SEL_MSK)) | clkSource; + } + else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching from Master to not and divider is 1, set source, so we don't */ + /* lock when we clear SSS. */ + Clk_Brea1_MOD_SRC = + (Clk_Brea1_MOD_SRC & (uint8)(~Clk_Brea1_SRC_SEL_MSK)) | clkSource; + Clk_Brea1_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + Clk_Brea1_MOD_SRC = + (Clk_Brea1_MOD_SRC & (uint8)(~Clk_Brea1_SRC_SEL_MSK)) | clkSource; + } +} + + +/******************************************************************************* +* Function Name: Clk_Brea1_GetSourceRegister +******************************************************************************** +* +* Summary: +* Gets the input source of the clock. +* +* Parameters: +* None +* +* Returns: +* The input source of the clock. See SetSourceRegister for details. +* +*******************************************************************************/ +uint8 Clk_Brea1_GetSourceRegister(void) +{ + return Clk_Brea1_MOD_SRC & Clk_Brea1_SRC_SEL_MSK; +} + + +#if defined(Clk_Brea1__CFG3) + + +/******************************************************************************* +* Function Name: Clk_Brea1_SetPhaseRegister +******************************************************************************** +* +* Summary: +* Sets the phase delay of the analog clock. This function is only available +* for analog clocks. The clock must be disabled before changing the phase +* delay to avoid glitches. +* +* Parameters: +* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments. +* clkPhase must be from 1 to 11 inclusive. Other values, including 0, +* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 +* produces a 10ns delay. +* +* Returns: +* None +* +*******************************************************************************/ +void Clk_Brea1_SetPhaseRegister(uint8 clkPhase) +{ + Clk_Brea1_PHASE = clkPhase & Clk_Brea1_PHASE_MASK; +} + + +/******************************************************************************* +* Function Name: Clk_Brea1_GetPhase +******************************************************************************** +* +* Summary: +* Gets the phase delay of the analog clock. This function is only available +* for analog clocks. +* +* Parameters: +* None +* +* Returns: +* Phase of the analog clock. See SetPhaseRegister for details. +* +*******************************************************************************/ +uint8 Clk_Brea1_GetPhaseRegister(void) +{ + return Clk_Brea1_PHASE & Clk_Brea1_PHASE_MASK; +} + +#endif /* Clk_Brea1__CFG3 */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Clk_Brea1.h b/source/hic_hal/cypress/psoc5lp/PSoC5/Clk_Brea1.h new file mode 100644 index 0000000000..4768067c91 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Clk_Brea1.h @@ -0,0 +1,134 @@ +/******************************************************************************* +* File Name: Clk_Brea1.h +* Version 2.20 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_CLOCK_Clk_Brea1_H) +#define CY_CLOCK_Clk_Brea1_H + +#include +#include + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component cy_clock_v2_20 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +void Clk_Brea1_Start(void) ; +void Clk_Brea1_Stop(void) ; + +#if(CY_PSOC3 || CY_PSOC5LP) +void Clk_Brea1_StopBlock(void) ; +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +void Clk_Brea1_StandbyPower(uint8 state) ; +void Clk_Brea1_SetDividerRegister(uint16 clkDivider, uint8 restart) + ; +uint16 Clk_Brea1_GetDividerRegister(void) ; +void Clk_Brea1_SetModeRegister(uint8 modeBitMask) ; +void Clk_Brea1_ClearModeRegister(uint8 modeBitMask) ; +uint8 Clk_Brea1_GetModeRegister(void) ; +void Clk_Brea1_SetSourceRegister(uint8 clkSource) ; +uint8 Clk_Brea1_GetSourceRegister(void) ; +#if defined(Clk_Brea1__CFG3) +void Clk_Brea1_SetPhaseRegister(uint8 clkPhase) ; +uint8 Clk_Brea1_GetPhaseRegister(void) ; +#endif /* defined(Clk_Brea1__CFG3) */ + +#define Clk_Brea1_Enable() Clk_Brea1_Start() +#define Clk_Brea1_Disable() Clk_Brea1_Stop() +#define Clk_Brea1_SetDivider(clkDivider) Clk_Brea1_SetDividerRegister(clkDivider, 1u) +#define Clk_Brea1_SetDividerValue(clkDivider) Clk_Brea1_SetDividerRegister((clkDivider) - 1u, 1u) +#define Clk_Brea1_SetMode(clkMode) Clk_Brea1_SetModeRegister(clkMode) +#define Clk_Brea1_SetSource(clkSource) Clk_Brea1_SetSourceRegister(clkSource) +#if defined(Clk_Brea1__CFG3) +#define Clk_Brea1_SetPhase(clkPhase) Clk_Brea1_SetPhaseRegister(clkPhase) +#define Clk_Brea1_SetPhaseValue(clkPhase) Clk_Brea1_SetPhaseRegister((clkPhase) + 1u) +#endif /* defined(Clk_Brea1__CFG3) */ + + +/*************************************** +* Registers +***************************************/ + +/* Register to enable or disable the clock */ +#define Clk_Brea1_CLKEN (* (reg8 *) Clk_Brea1__PM_ACT_CFG) +#define Clk_Brea1_CLKEN_PTR ((reg8 *) Clk_Brea1__PM_ACT_CFG) + +/* Register to enable or disable the clock */ +#define Clk_Brea1_CLKSTBY (* (reg8 *) Clk_Brea1__PM_STBY_CFG) +#define Clk_Brea1_CLKSTBY_PTR ((reg8 *) Clk_Brea1__PM_STBY_CFG) + +/* Clock LSB divider configuration register. */ +#define Clk_Brea1_DIV_LSB (* (reg8 *) Clk_Brea1__CFG0) +#define Clk_Brea1_DIV_LSB_PTR ((reg8 *) Clk_Brea1__CFG0) +#define Clk_Brea1_DIV_PTR ((reg16 *) Clk_Brea1__CFG0) + +/* Clock MSB divider configuration register. */ +#define Clk_Brea1_DIV_MSB (* (reg8 *) Clk_Brea1__CFG1) +#define Clk_Brea1_DIV_MSB_PTR ((reg8 *) Clk_Brea1__CFG1) + +/* Mode and source configuration register */ +#define Clk_Brea1_MOD_SRC (* (reg8 *) Clk_Brea1__CFG2) +#define Clk_Brea1_MOD_SRC_PTR ((reg8 *) Clk_Brea1__CFG2) + +#if defined(Clk_Brea1__CFG3) +/* Analog clock phase configuration register */ +#define Clk_Brea1_PHASE (* (reg8 *) Clk_Brea1__CFG3) +#define Clk_Brea1_PHASE_PTR ((reg8 *) Clk_Brea1__CFG3) +#endif /* defined(Clk_Brea1__CFG3) */ + + +/************************************** +* Register Constants +**************************************/ + +/* Power manager register masks */ +#define Clk_Brea1_CLKEN_MASK Clk_Brea1__PM_ACT_MSK +#define Clk_Brea1_CLKSTBY_MASK Clk_Brea1__PM_STBY_MSK + +/* CFG2 field masks */ +#define Clk_Brea1_SRC_SEL_MSK Clk_Brea1__CFG2_SRC_SEL_MASK +#define Clk_Brea1_MODE_MASK (~(Clk_Brea1_SRC_SEL_MSK)) + +#if defined(Clk_Brea1__CFG3) +/* CFG3 phase mask */ +#define Clk_Brea1_PHASE_MASK Clk_Brea1__CFG3_PHASE_DLY_MASK +#endif /* defined(Clk_Brea1__CFG3) */ + +#endif /* CY_CLOCK_Clk_Brea1_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Clk_Brea2.c b/source/hic_hal/cypress/psoc5lp/PSoC5/Clk_Brea2.c new file mode 100644 index 0000000000..8c6d196968 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Clk_Brea2.c @@ -0,0 +1,531 @@ +/******************************************************************************* +* File Name: Clk_Brea2.c +* Version 2.20 +* +* Description: +* This file provides the source code to the API for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include +#include "Clk_Brea2.h" + +/* Clock Distribution registers. */ +#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD) +#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2) +#define BCFG2_MASK (0x80u) +#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK) +#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK) + +#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: Clk_Brea2_Start +******************************************************************************** +* +* Summary: +* Starts the clock. Note that on startup, clocks may be already running if the +* "Start on Reset" option is enabled in the DWR. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void Clk_Brea2_Start(void) +{ + /* Set the bit to enable the clock. */ + Clk_Brea2_CLKEN |= Clk_Brea2_CLKEN_MASK; + Clk_Brea2_CLKSTBY |= Clk_Brea2_CLKSTBY_MASK; +} + + +/******************************************************************************* +* Function Name: Clk_Brea2_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. If the settings of the clock are changed after calling this +* function, the clock may glitch when it is started. To avoid the clock +* glitch, use the StopBlock function. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void Clk_Brea2_Stop(void) +{ + /* Clear the bit to disable the clock. */ + Clk_Brea2_CLKEN &= (uint8)(~Clk_Brea2_CLKEN_MASK); + Clk_Brea2_CLKSTBY &= (uint8)(~Clk_Brea2_CLKSTBY_MASK); +} + + +#if(CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: Clk_Brea2_StopBlock +******************************************************************************** +* +* Summary: +* Stops the clock and waits for the hardware to actually be disabled before +* returning. This ensures that the clock is never truncated (high part of the +* cycle will terminate before the clock is disabled and the API returns). +* Note that the source clock must be running or this API will never return as +* a stopped clock cannot be disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void Clk_Brea2_StopBlock(void) +{ + if ((Clk_Brea2_CLKEN & Clk_Brea2_CLKEN_MASK) != 0u) + { +#if HAS_CLKDIST_LD_DISABLE + uint16 oldDivider; + + CLK_DIST_LD = 0u; + + /* Clear all the mask bits except ours. */ +#if defined(Clk_Brea2__CFG3) + CLK_DIST_AMASK = Clk_Brea2_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = Clk_Brea2_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* Clk_Brea2__CFG3 */ + + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + oldDivider = CY_GET_REG16(Clk_Brea2_DIV_PTR); + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + /* Clear the bit to disable the clock. */ + Clk_Brea2_CLKEN &= (uint8)(~Clk_Brea2_CLKEN_MASK); + Clk_Brea2_CLKSTBY &= (uint8)(~Clk_Brea2_CLKSTBY_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; + CY_SET_REG16(Clk_Brea2_DIV_PTR, oldDivider); +#endif /* HAS_CLKDIST_LD_DISABLE */ + } +} +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/******************************************************************************* +* Function Name: Clk_Brea2_StandbyPower +******************************************************************************** +* +* Summary: +* Sets whether the clock is active in standby mode. +* +* Parameters: +* state: 0 to disable clock during standby, nonzero to enable. +* +* Returns: +* None +* +*******************************************************************************/ +void Clk_Brea2_StandbyPower(uint8 state) +{ + if(state == 0u) + { + Clk_Brea2_CLKSTBY &= (uint8)(~Clk_Brea2_CLKSTBY_MASK); + } + else + { + Clk_Brea2_CLKSTBY |= Clk_Brea2_CLKSTBY_MASK; + } +} + + +/******************************************************************************* +* Function Name: Clk_Brea2_SetDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and, thus, the frequency. When the clock divider +* register is set to zero or changed from zero, the clock will be temporarily +* disabled in order to change the SSS mode bit. If the clock is enabled when +* SetDividerRegister is called, then the source clock must be running. +* +* Parameters: +* clkDivider: Divider register value (0-65,535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* restart: If nonzero, restarts the clock divider: the current clock cycle +* will be truncated and the new divide value will take effect immediately. If +* zero, the new divide value will take effect at the end of the current clock +* cycle. +* +* Returns: +* None +* +*******************************************************************************/ +void Clk_Brea2_SetDividerRegister(uint16 clkDivider, uint8 restart) + +{ + uint8 enabled; + + uint8 currSrc = Clk_Brea2_GetSourceRegister(); + uint16 oldDivider = Clk_Brea2_GetDividerRegister(); + + if (clkDivider != oldDivider) + { + enabled = Clk_Brea2_CLKEN & Clk_Brea2_CLKEN_MASK; + + if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u))) + { + /* Moving to/from SSS requires correct ordering to prevent halting the clock */ + if (oldDivider == 0u) + { + /* Moving away from SSS, set the divider first so when SSS is cleared we */ + /* don't halt the clock. Using the shadow load isn't required as the */ + /* divider is ignored while SSS is set. */ + CY_SET_REG16(Clk_Brea2_DIV_PTR, clkDivider); + Clk_Brea2_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + /* Moving to SSS, set SSS which then ignores the divider and we can set */ + /* it without bothering with the shadow load. */ + Clk_Brea2_MOD_SRC |= CYCLK_SSS; + CY_SET_REG16(Clk_Brea2_DIV_PTR, clkDivider); + } + } + else + { + + if (enabled != 0u) + { + CLK_DIST_LD = 0x00u; + + /* Clear all the mask bits except ours. */ +#if defined(Clk_Brea2__CFG3) + CLK_DIST_AMASK = Clk_Brea2_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = Clk_Brea2_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* Clk_Brea2__CFG3 */ + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + /* If clock is currently enabled, disable it if async or going from N-to-1*/ + if (((Clk_Brea2_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u)) + { +#if HAS_CLKDIST_LD_DISABLE + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + Clk_Brea2_CLKEN &= (uint8)(~Clk_Brea2_CLKEN_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; +#endif /* HAS_CLKDIST_LD_DISABLE */ + } + } + + /* Load divide value. */ + if ((Clk_Brea2_CLKEN & Clk_Brea2_CLKEN_MASK) != 0u) + { + /* If the clock is still enabled, use the shadow registers */ + CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider); + + CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u)); + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } + } + else + { + /* If the clock is disabled, set the divider directly */ + CY_SET_REG16(Clk_Brea2_DIV_PTR, clkDivider); + Clk_Brea2_CLKEN |= enabled; + } + } + } +} + + +/******************************************************************************* +* Function Name: Clk_Brea2_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 Clk_Brea2_GetDividerRegister(void) +{ + return CY_GET_REG16(Clk_Brea2_DIV_PTR); +} + + +/******************************************************************************* +* Function Name: Clk_Brea2_SetModeRegister +******************************************************************************** +* +* Summary: +* Sets flags that control the operating mode of the clock. This function only +* changes flags from 0 to 1; flags that are already 1 will remain unchanged. +* To clear flags, use the ClearModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void Clk_Brea2_SetModeRegister(uint8 modeBitMask) +{ + Clk_Brea2_MOD_SRC |= modeBitMask & (uint8)Clk_Brea2_MODE_MASK; +} + + +/******************************************************************************* +* Function Name: Clk_Brea2_ClearModeRegister +******************************************************************************** +* +* Summary: +* Clears flags that control the operating mode of the clock. This function +* only changes flags from 1 to 0; flags that are already 0 will remain +* unchanged. To set flags, use the SetModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void Clk_Brea2_ClearModeRegister(uint8 modeBitMask) +{ + Clk_Brea2_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(Clk_Brea2_MODE_MASK)); +} + + +/******************************************************************************* +* Function Name: Clk_Brea2_GetModeRegister +******************************************************************************** +* +* Summary: +* Gets the clock mode register value. +* +* Parameters: +* None +* +* Returns: +* Bit mask representing the enabled mode bits. See the SetModeRegister and +* ClearModeRegister descriptions for details about the mode bits. +* +*******************************************************************************/ +uint8 Clk_Brea2_GetModeRegister(void) +{ + return Clk_Brea2_MOD_SRC & (uint8)(Clk_Brea2_MODE_MASK); +} + + +/******************************************************************************* +* Function Name: Clk_Brea2_SetSourceRegister +******************************************************************************** +* +* Summary: +* Sets the input source of the clock. The clock must be disabled before +* changing the source. The old and new clock sources must be running. +* +* Parameters: +* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the +* following input sources: +* - CYCLK_SRC_SEL_SYNC_DIG +* - CYCLK_SRC_SEL_IMO +* - CYCLK_SRC_SEL_XTALM +* - CYCLK_SRC_SEL_ILO +* - CYCLK_SRC_SEL_PLL +* - CYCLK_SRC_SEL_XTALK +* - CYCLK_SRC_SEL_DSI_G +* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A +* See the Technical Reference Manual for details on clock sources. +* +* Returns: +* None +* +*******************************************************************************/ +void Clk_Brea2_SetSourceRegister(uint8 clkSource) +{ + uint16 currDiv = Clk_Brea2_GetDividerRegister(); + uint8 oldSrc = Clk_Brea2_GetSourceRegister(); + + if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching to Master and divider is 1, set SSS, which will output master, */ + /* then set the source so we are consistent. */ + Clk_Brea2_MOD_SRC |= CYCLK_SSS; + Clk_Brea2_MOD_SRC = + (Clk_Brea2_MOD_SRC & (uint8)(~Clk_Brea2_SRC_SEL_MSK)) | clkSource; + } + else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching from Master to not and divider is 1, set source, so we don't */ + /* lock when we clear SSS. */ + Clk_Brea2_MOD_SRC = + (Clk_Brea2_MOD_SRC & (uint8)(~Clk_Brea2_SRC_SEL_MSK)) | clkSource; + Clk_Brea2_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + Clk_Brea2_MOD_SRC = + (Clk_Brea2_MOD_SRC & (uint8)(~Clk_Brea2_SRC_SEL_MSK)) | clkSource; + } +} + + +/******************************************************************************* +* Function Name: Clk_Brea2_GetSourceRegister +******************************************************************************** +* +* Summary: +* Gets the input source of the clock. +* +* Parameters: +* None +* +* Returns: +* The input source of the clock. See SetSourceRegister for details. +* +*******************************************************************************/ +uint8 Clk_Brea2_GetSourceRegister(void) +{ + return Clk_Brea2_MOD_SRC & Clk_Brea2_SRC_SEL_MSK; +} + + +#if defined(Clk_Brea2__CFG3) + + +/******************************************************************************* +* Function Name: Clk_Brea2_SetPhaseRegister +******************************************************************************** +* +* Summary: +* Sets the phase delay of the analog clock. This function is only available +* for analog clocks. The clock must be disabled before changing the phase +* delay to avoid glitches. +* +* Parameters: +* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments. +* clkPhase must be from 1 to 11 inclusive. Other values, including 0, +* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 +* produces a 10ns delay. +* +* Returns: +* None +* +*******************************************************************************/ +void Clk_Brea2_SetPhaseRegister(uint8 clkPhase) +{ + Clk_Brea2_PHASE = clkPhase & Clk_Brea2_PHASE_MASK; +} + + +/******************************************************************************* +* Function Name: Clk_Brea2_GetPhase +******************************************************************************** +* +* Summary: +* Gets the phase delay of the analog clock. This function is only available +* for analog clocks. +* +* Parameters: +* None +* +* Returns: +* Phase of the analog clock. See SetPhaseRegister for details. +* +*******************************************************************************/ +uint8 Clk_Brea2_GetPhaseRegister(void) +{ + return Clk_Brea2_PHASE & Clk_Brea2_PHASE_MASK; +} + +#endif /* Clk_Brea2__CFG3 */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Clk_Brea2.h b/source/hic_hal/cypress/psoc5lp/PSoC5/Clk_Brea2.h new file mode 100644 index 0000000000..46886f5ac1 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Clk_Brea2.h @@ -0,0 +1,134 @@ +/******************************************************************************* +* File Name: Clk_Brea2.h +* Version 2.20 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_CLOCK_Clk_Brea2_H) +#define CY_CLOCK_Clk_Brea2_H + +#include +#include + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component cy_clock_v2_20 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +void Clk_Brea2_Start(void) ; +void Clk_Brea2_Stop(void) ; + +#if(CY_PSOC3 || CY_PSOC5LP) +void Clk_Brea2_StopBlock(void) ; +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +void Clk_Brea2_StandbyPower(uint8 state) ; +void Clk_Brea2_SetDividerRegister(uint16 clkDivider, uint8 restart) + ; +uint16 Clk_Brea2_GetDividerRegister(void) ; +void Clk_Brea2_SetModeRegister(uint8 modeBitMask) ; +void Clk_Brea2_ClearModeRegister(uint8 modeBitMask) ; +uint8 Clk_Brea2_GetModeRegister(void) ; +void Clk_Brea2_SetSourceRegister(uint8 clkSource) ; +uint8 Clk_Brea2_GetSourceRegister(void) ; +#if defined(Clk_Brea2__CFG3) +void Clk_Brea2_SetPhaseRegister(uint8 clkPhase) ; +uint8 Clk_Brea2_GetPhaseRegister(void) ; +#endif /* defined(Clk_Brea2__CFG3) */ + +#define Clk_Brea2_Enable() Clk_Brea2_Start() +#define Clk_Brea2_Disable() Clk_Brea2_Stop() +#define Clk_Brea2_SetDivider(clkDivider) Clk_Brea2_SetDividerRegister(clkDivider, 1u) +#define Clk_Brea2_SetDividerValue(clkDivider) Clk_Brea2_SetDividerRegister((clkDivider) - 1u, 1u) +#define Clk_Brea2_SetMode(clkMode) Clk_Brea2_SetModeRegister(clkMode) +#define Clk_Brea2_SetSource(clkSource) Clk_Brea2_SetSourceRegister(clkSource) +#if defined(Clk_Brea2__CFG3) +#define Clk_Brea2_SetPhase(clkPhase) Clk_Brea2_SetPhaseRegister(clkPhase) +#define Clk_Brea2_SetPhaseValue(clkPhase) Clk_Brea2_SetPhaseRegister((clkPhase) + 1u) +#endif /* defined(Clk_Brea2__CFG3) */ + + +/*************************************** +* Registers +***************************************/ + +/* Register to enable or disable the clock */ +#define Clk_Brea2_CLKEN (* (reg8 *) Clk_Brea2__PM_ACT_CFG) +#define Clk_Brea2_CLKEN_PTR ((reg8 *) Clk_Brea2__PM_ACT_CFG) + +/* Register to enable or disable the clock */ +#define Clk_Brea2_CLKSTBY (* (reg8 *) Clk_Brea2__PM_STBY_CFG) +#define Clk_Brea2_CLKSTBY_PTR ((reg8 *) Clk_Brea2__PM_STBY_CFG) + +/* Clock LSB divider configuration register. */ +#define Clk_Brea2_DIV_LSB (* (reg8 *) Clk_Brea2__CFG0) +#define Clk_Brea2_DIV_LSB_PTR ((reg8 *) Clk_Brea2__CFG0) +#define Clk_Brea2_DIV_PTR ((reg16 *) Clk_Brea2__CFG0) + +/* Clock MSB divider configuration register. */ +#define Clk_Brea2_DIV_MSB (* (reg8 *) Clk_Brea2__CFG1) +#define Clk_Brea2_DIV_MSB_PTR ((reg8 *) Clk_Brea2__CFG1) + +/* Mode and source configuration register */ +#define Clk_Brea2_MOD_SRC (* (reg8 *) Clk_Brea2__CFG2) +#define Clk_Brea2_MOD_SRC_PTR ((reg8 *) Clk_Brea2__CFG2) + +#if defined(Clk_Brea2__CFG3) +/* Analog clock phase configuration register */ +#define Clk_Brea2_PHASE (* (reg8 *) Clk_Brea2__CFG3) +#define Clk_Brea2_PHASE_PTR ((reg8 *) Clk_Brea2__CFG3) +#endif /* defined(Clk_Brea2__CFG3) */ + + +/************************************** +* Register Constants +**************************************/ + +/* Power manager register masks */ +#define Clk_Brea2_CLKEN_MASK Clk_Brea2__PM_ACT_MSK +#define Clk_Brea2_CLKSTBY_MASK Clk_Brea2__PM_STBY_MSK + +/* CFG2 field masks */ +#define Clk_Brea2_SRC_SEL_MSK Clk_Brea2__CFG2_SRC_SEL_MASK +#define Clk_Brea2_MODE_MASK (~(Clk_Brea2_SRC_SEL_MSK)) + +#if defined(Clk_Brea2__CFG3) +/* CFG3 phase mask */ +#define Clk_Brea2_PHASE_MASK Clk_Brea2__CFG3_PHASE_DLY_MASK +#endif /* defined(Clk_Brea2__CFG3) */ + +#endif /* CY_CLOCK_Clk_Brea2_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Clock_UART.c b/source/hic_hal/cypress/psoc5lp/PSoC5/Clock_UART.c new file mode 100644 index 0000000000..aa9d6b8a0c --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Clock_UART.c @@ -0,0 +1,529 @@ +/******************************************************************************* +* File Name: Clock_UART.c +* Version 2.20 +* +* Description: +* This file provides the source code to the API for the clock component. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include +#include "Clock_UART.h" + +/* Clock Distribution registers. */ +#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD) +#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2) +#define BCFG2_MASK (0x80u) +#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK) +#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK) + +#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: Clock_UART_Start +******************************************************************************** +* +* Summary: +* Starts the clock. Note that on startup, clocks may be already running if the +* "Start on Reset" option is enabled in the DWR. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void Clock_UART_Start(void) +{ + /* Set the bit to enable the clock. */ + Clock_UART_CLKEN |= Clock_UART_CLKEN_MASK; + Clock_UART_CLKSTBY |= Clock_UART_CLKSTBY_MASK; +} + + +/******************************************************************************* +* Function Name: Clock_UART_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. If the settings of the clock are changed after calling this +* function, the clock may glitch when it is started. To avoid the clock +* glitch, use the StopBlock function. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void Clock_UART_Stop(void) +{ + /* Clear the bit to disable the clock. */ + Clock_UART_CLKEN &= (uint8)(~Clock_UART_CLKEN_MASK); + Clock_UART_CLKSTBY &= (uint8)(~Clock_UART_CLKSTBY_MASK); +} + + +#if(CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: Clock_UART_StopBlock +******************************************************************************** +* +* Summary: +* Stops the clock and waits for the hardware to actually be disabled before +* returning. This ensures that the clock is never truncated (high part of the +* cycle will terminate before the clock is disabled and the API returns). +* Note that the source clock must be running or this API will never return as +* a stopped clock cannot be disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void Clock_UART_StopBlock(void) +{ + if ((Clock_UART_CLKEN & Clock_UART_CLKEN_MASK) != 0u) + { +#if HAS_CLKDIST_LD_DISABLE + uint16 oldDivider; + + CLK_DIST_LD = 0u; + + /* Clear all the mask bits except ours. */ +#if defined(Clock_UART__CFG3) + CLK_DIST_AMASK = Clock_UART_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = Clock_UART_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* Clock_UART__CFG3 */ + + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + oldDivider = CY_GET_REG16(Clock_UART_DIV_PTR); + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + /* Clear the bit to disable the clock. */ + Clock_UART_CLKEN &= (uint8)(~Clock_UART_CLKEN_MASK); + Clock_UART_CLKSTBY &= (uint8)(~Clock_UART_CLKSTBY_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; + CY_SET_REG16(Clock_UART_DIV_PTR, oldDivider); +#endif /* HAS_CLKDIST_LD_DISABLE */ + } +} +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/******************************************************************************* +* Function Name: Clock_UART_StandbyPower +******************************************************************************** +* +* Summary: +* Sets whether the clock is active in standby mode. +* +* Parameters: +* state: 0 to disable clock during standby, nonzero to enable. +* +* Returns: +* None +* +*******************************************************************************/ +void Clock_UART_StandbyPower(uint8 state) +{ + if(state == 0u) + { + Clock_UART_CLKSTBY &= (uint8)(~Clock_UART_CLKSTBY_MASK); + } + else + { + Clock_UART_CLKSTBY |= Clock_UART_CLKSTBY_MASK; + } +} + + +/******************************************************************************* +* Function Name: Clock_UART_SetDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and, thus, the frequency. When the clock divider +* register is set to zero or changed from zero, the clock will be temporarily +* disabled in order to change the SSS mode bit. If the clock is enabled when +* SetDividerRegister is called, then the source clock must be running. +* +* Parameters: +* clkDivider: Divider register value (0-65,535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* restart: If nonzero, restarts the clock divider: the current clock cycle +* will be truncated and the new divide value will take effect immediately. If +* zero, the new divide value will take effect at the end of the current clock +* cycle. +* +* Returns: +* None +* +*******************************************************************************/ +void Clock_UART_SetDividerRegister(uint16 clkDivider, uint8 restart) + +{ + uint8 enabled; + + uint8 currSrc = Clock_UART_GetSourceRegister(); + uint16 oldDivider = Clock_UART_GetDividerRegister(); + + if (clkDivider != oldDivider) + { + enabled = Clock_UART_CLKEN & Clock_UART_CLKEN_MASK; + + if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u))) + { + /* Moving to/from SSS requires correct ordering to prevent halting the clock */ + if (oldDivider == 0u) + { + /* Moving away from SSS, set the divider first so when SSS is cleared we */ + /* don't halt the clock. Using the shadow load isn't required as the */ + /* divider is ignored while SSS is set. */ + CY_SET_REG16(Clock_UART_DIV_PTR, clkDivider); + Clock_UART_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + /* Moving to SSS, set SSS which then ignores the divider and we can set */ + /* it without bothering with the shadow load. */ + Clock_UART_MOD_SRC |= CYCLK_SSS; + CY_SET_REG16(Clock_UART_DIV_PTR, clkDivider); + } + } + else + { + + if (enabled != 0u) + { + CLK_DIST_LD = 0x00u; + + /* Clear all the mask bits except ours. */ +#if defined(Clock_UART__CFG3) + CLK_DIST_AMASK = Clock_UART_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = Clock_UART_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* Clock_UART__CFG3 */ + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + /* If clock is currently enabled, disable it if async or going from N-to-1*/ + if (((Clock_UART_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u)) + { +#if HAS_CLKDIST_LD_DISABLE + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + Clock_UART_CLKEN &= (uint8)(~Clock_UART_CLKEN_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; +#endif /* HAS_CLKDIST_LD_DISABLE */ + } + } + + /* Load divide value. */ + if ((Clock_UART_CLKEN & Clock_UART_CLKEN_MASK) != 0u) + { + /* If the clock is still enabled, use the shadow registers */ + CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider); + + CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u)); + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } + } + else + { + /* If the clock is disabled, set the divider directly */ + CY_SET_REG16(Clock_UART_DIV_PTR, clkDivider); + Clock_UART_CLKEN |= enabled; + } + } + } +} + + +/******************************************************************************* +* Function Name: Clock_UART_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 Clock_UART_GetDividerRegister(void) +{ + return CY_GET_REG16(Clock_UART_DIV_PTR); +} + + +/******************************************************************************* +* Function Name: Clock_UART_SetModeRegister +******************************************************************************** +* +* Summary: +* Sets flags that control the operating mode of the clock. This function only +* changes flags from 0 to 1; flags that are already 1 will remain unchanged. +* To clear flags, use the ClearModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void Clock_UART_SetModeRegister(uint8 modeBitMask) +{ + Clock_UART_MOD_SRC |= modeBitMask & (uint8)Clock_UART_MODE_MASK; +} + + +/******************************************************************************* +* Function Name: Clock_UART_ClearModeRegister +******************************************************************************** +* +* Summary: +* Clears flags that control the operating mode of the clock. This function +* only changes flags from 1 to 0; flags that are already 0 will remain +* unchanged. To set flags, use the SetModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void Clock_UART_ClearModeRegister(uint8 modeBitMask) +{ + Clock_UART_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(Clock_UART_MODE_MASK)); +} + + +/******************************************************************************* +* Function Name: Clock_UART_GetModeRegister +******************************************************************************** +* +* Summary: +* Gets the clock mode register value. +* +* Parameters: +* None +* +* Returns: +* Bit mask representing the enabled mode bits. See the SetModeRegister and +* ClearModeRegister descriptions for details about the mode bits. +* +*******************************************************************************/ +uint8 Clock_UART_GetModeRegister(void) +{ + return Clock_UART_MOD_SRC & (uint8)(Clock_UART_MODE_MASK); +} + + +/******************************************************************************* +* Function Name: Clock_UART_SetSourceRegister +******************************************************************************** +* +* Summary: +* Sets the input source of the clock. The clock must be disabled before +* changing the source. The old and new clock sources must be running. +* +* Parameters: +* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the +* following input sources: +* - CYCLK_SRC_SEL_SYNC_DIG +* - CYCLK_SRC_SEL_IMO +* - CYCLK_SRC_SEL_XTALM +* - CYCLK_SRC_SEL_ILO +* - CYCLK_SRC_SEL_PLL +* - CYCLK_SRC_SEL_XTALK +* - CYCLK_SRC_SEL_DSI_G +* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A +* See the Technical Reference Manual for details on clock sources. +* +* Returns: +* None +* +*******************************************************************************/ +void Clock_UART_SetSourceRegister(uint8 clkSource) +{ + uint16 currDiv = Clock_UART_GetDividerRegister(); + uint8 oldSrc = Clock_UART_GetSourceRegister(); + + if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching to Master and divider is 1, set SSS, which will output master, */ + /* then set the source so we are consistent. */ + Clock_UART_MOD_SRC |= CYCLK_SSS; + Clock_UART_MOD_SRC = + (Clock_UART_MOD_SRC & (uint8)(~Clock_UART_SRC_SEL_MSK)) | clkSource; + } + else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching from Master to not and divider is 1, set source, so we don't */ + /* lock when we clear SSS. */ + Clock_UART_MOD_SRC = + (Clock_UART_MOD_SRC & (uint8)(~Clock_UART_SRC_SEL_MSK)) | clkSource; + Clock_UART_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + Clock_UART_MOD_SRC = + (Clock_UART_MOD_SRC & (uint8)(~Clock_UART_SRC_SEL_MSK)) | clkSource; + } +} + + +/******************************************************************************* +* Function Name: Clock_UART_GetSourceRegister +******************************************************************************** +* +* Summary: +* Gets the input source of the clock. +* +* Parameters: +* None +* +* Returns: +* The input source of the clock. See SetSourceRegister for details. +* +*******************************************************************************/ +uint8 Clock_UART_GetSourceRegister(void) +{ + return Clock_UART_MOD_SRC & Clock_UART_SRC_SEL_MSK; +} + + +#if defined(Clock_UART__CFG3) + + +/******************************************************************************* +* Function Name: Clock_UART_SetPhaseRegister +******************************************************************************** +* +* Summary: +* Sets the phase delay of the analog clock. This function is only available +* for analog clocks. The clock must be disabled before changing the phase +* delay to avoid glitches. +* +* Parameters: +* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments. +* clkPhase must be from 1 to 11 inclusive. Other values, including 0, +* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 +* produces a 10ns delay. +* +* Returns: +* None +* +*******************************************************************************/ +void Clock_UART_SetPhaseRegister(uint8 clkPhase) +{ + Clock_UART_PHASE = clkPhase & Clock_UART_PHASE_MASK; +} + + +/******************************************************************************* +* Function Name: Clock_UART_GetPhase +******************************************************************************** +* +* Summary: +* Gets the phase delay of the analog clock. This function is only available +* for analog clocks. +* +* Parameters: +* None +* +* Returns: +* Phase of the analog clock. See SetPhaseRegister for details. +* +*******************************************************************************/ +uint8 Clock_UART_GetPhaseRegister(void) +{ + return Clock_UART_PHASE & Clock_UART_PHASE_MASK; +} + +#endif /* Clock_UART__CFG3 */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Clock_UART.h b/source/hic_hal/cypress/psoc5lp/PSoC5/Clock_UART.h new file mode 100644 index 0000000000..9f64834d65 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Clock_UART.h @@ -0,0 +1,132 @@ +/******************************************************************************* +* File Name: Clock_UART.h +* Version 2.20 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_CLOCK_Clock_UART_H) +#define CY_CLOCK_Clock_UART_H + +#include +#include + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component cy_clock_v2_20 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +void Clock_UART_Start(void) ; +void Clock_UART_Stop(void) ; + +#if(CY_PSOC3 || CY_PSOC5LP) +void Clock_UART_StopBlock(void) ; +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +void Clock_UART_StandbyPower(uint8 state) ; +void Clock_UART_SetDividerRegister(uint16 clkDivider, uint8 restart) + ; +uint16 Clock_UART_GetDividerRegister(void) ; +void Clock_UART_SetModeRegister(uint8 modeBitMask) ; +void Clock_UART_ClearModeRegister(uint8 modeBitMask) ; +uint8 Clock_UART_GetModeRegister(void) ; +void Clock_UART_SetSourceRegister(uint8 clkSource) ; +uint8 Clock_UART_GetSourceRegister(void) ; +#if defined(Clock_UART__CFG3) +void Clock_UART_SetPhaseRegister(uint8 clkPhase) ; +uint8 Clock_UART_GetPhaseRegister(void) ; +#endif /* defined(Clock_UART__CFG3) */ + +#define Clock_UART_Enable() Clock_UART_Start() +#define Clock_UART_Disable() Clock_UART_Stop() +#define Clock_UART_SetDivider(clkDivider) Clock_UART_SetDividerRegister(clkDivider, 1u) +#define Clock_UART_SetDividerValue(clkDivider) Clock_UART_SetDividerRegister((clkDivider) - 1u, 1u) +#define Clock_UART_SetMode(clkMode) Clock_UART_SetModeRegister(clkMode) +#define Clock_UART_SetSource(clkSource) Clock_UART_SetSourceRegister(clkSource) +#if defined(Clock_UART__CFG3) +#define Clock_UART_SetPhase(clkPhase) Clock_UART_SetPhaseRegister(clkPhase) +#define Clock_UART_SetPhaseValue(clkPhase) Clock_UART_SetPhaseRegister((clkPhase) + 1u) +#endif /* defined(Clock_UART__CFG3) */ + + +/*************************************** +* Registers +***************************************/ + +/* Register to enable or disable the clock */ +#define Clock_UART_CLKEN (* (reg8 *) Clock_UART__PM_ACT_CFG) +#define Clock_UART_CLKEN_PTR ((reg8 *) Clock_UART__PM_ACT_CFG) + +/* Register to enable or disable the clock */ +#define Clock_UART_CLKSTBY (* (reg8 *) Clock_UART__PM_STBY_CFG) +#define Clock_UART_CLKSTBY_PTR ((reg8 *) Clock_UART__PM_STBY_CFG) + +/* Clock LSB divider configuration register. */ +#define Clock_UART_DIV_LSB (* (reg8 *) Clock_UART__CFG0) +#define Clock_UART_DIV_LSB_PTR ((reg8 *) Clock_UART__CFG0) +#define Clock_UART_DIV_PTR ((reg16 *) Clock_UART__CFG0) + +/* Clock MSB divider configuration register. */ +#define Clock_UART_DIV_MSB (* (reg8 *) Clock_UART__CFG1) +#define Clock_UART_DIV_MSB_PTR ((reg8 *) Clock_UART__CFG1) + +/* Mode and source configuration register */ +#define Clock_UART_MOD_SRC (* (reg8 *) Clock_UART__CFG2) +#define Clock_UART_MOD_SRC_PTR ((reg8 *) Clock_UART__CFG2) + +#if defined(Clock_UART__CFG3) +/* Analog clock phase configuration register */ +#define Clock_UART_PHASE (* (reg8 *) Clock_UART__CFG3) +#define Clock_UART_PHASE_PTR ((reg8 *) Clock_UART__CFG3) +#endif /* defined(Clock_UART__CFG3) */ + + +/************************************** +* Register Constants +**************************************/ + +/* Power manager register masks */ +#define Clock_UART_CLKEN_MASK Clock_UART__PM_ACT_MSK +#define Clock_UART_CLKSTBY_MASK Clock_UART__PM_STBY_MSK + +/* CFG2 field masks */ +#define Clock_UART_SRC_SEL_MSK Clock_UART__CFG2_SRC_SEL_MASK +#define Clock_UART_MODE_MASK (~(Clock_UART_SRC_SEL_MSK)) + +#if defined(Clock_UART__CFG3) +/* CFG3 phase mask */ +#define Clock_UART_PHASE_MASK Clock_UART__CFG3_PHASE_DLY_MASK +#endif /* defined(Clock_UART__CFG3) */ + +#endif /* CY_CLOCK_Clock_UART_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Cm3Start.c b/source/hic_hal/cypress/psoc5lp/PSoC5/Cm3Start.c new file mode 100644 index 0000000000..be908e32a9 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Cm3Start.c @@ -0,0 +1,488 @@ +/***************************************************************************//** +* \file Cm3Start.c +* \version 5.70 +* +* \brief +* Startup code for the ARM CM3. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include +#include "cydevice_trm.h" +#include "cytypes.h" +#include "cyfitter_cfg.h" +#include "CyLib.h" +#include "CyDmac.h" +#include "cyfitter.h" +#include "daplink_addr.h" + + +#define CY_NUM_INTERRUPTS (32u) +#define CY_NUM_VECTORS (CYINT_IRQ_BASE + CY_NUM_INTERRUPTS) +#define CY_NUM_ROM_VECTORS (4u) +#define CY_NVIC_APINT_PTR ((reg32 *) CYREG_NVIC_APPLN_INTR) +#define CY_NVIC_CFG_CTRL_PTR ((reg32 *) CYREG_NVIC_CFG_CONTROL) +#define CY_NVIC_APINT_PRIGROUP_3_5 (0x00000400u) /* Priority group 3.5 split */ +#define CY_NVIC_APINT_VECTKEY (0x05FA0000u) /* This key is required in order to write the NVIC_APINT register */ +#define CY_NVIC_CFG_STACKALIGN (0x00000200u) /* This specifies that the exception stack must be 8 byte aligned */ + +//#if defined(__ARMCC_VERSION) +// #define Image$$ARM_LIB_STACK$$ZI$$Limit __initial_sp +// #define INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit) +//#elif defined (__GNUC__) +// #define INITIAL_STACK_POINTER (&__cy_stack) +//#elif defined (__ICCARM__) +// #pragma language=extended +// #pragma segment="CSTACK" +// #define INITIAL_STACK_POINTER { .__ptr = __sfe( "CSTACK" ) } + +// extern void __iar_program_start( void ); +// extern void __iar_data_init3 (void); +//#endif /* (__ARMCC_VERSION) */ + +#if defined(__GNUC__) + #include + extern int end; +#endif /* defined(__GNUC__) */ + +/* Extern functions */ +extern void CyBtldr_CheckLaunch(void); + +/* Function prototypes */ +void initialize_psoc(void); +CY_ISR(IntDefaultHandler); +void Reset(void); + +/* Global variables */ +#if !defined (__ICCARM__) + CY_NOINIT static uint32 cySysNoInitDataValid; +#endif /* !defined (__ICCARM__) */ + + +/******************************************************************************* +* Default Ram Interrupt Vector table storage area. Must be 256-byte aligned. +*******************************************************************************/ +#if defined (__ICCARM__) + #pragma location=".ramvectors" + #pragma data_alignment=256 +#else + CY_SECTION(".ramvectors") + CY_ALIGN(256) +#endif /* defined (__ICCARM__) */ +cyisraddress CyRamVectors[CY_NUM_VECTORS]; + + +/******************************************************************************* +* Function Name: IntDefaultHandler +****************************************************************************//** +* +* This function is called for all interrupts, other than a reset that gets +* called before the system is setup. +* +* Theory: +* Any value other than zero is acceptable. +* +*******************************************************************************/ +CY_ISR(IntDefaultHandler) +{ + /*************************************************************************** + * We must not get here. If we do, a serious problem occurs, so go into + * an infinite loop. + ***************************************************************************/ + + #if defined(__GNUC__) + if (errno == ENOMEM) + { + #ifdef CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK + CyBoot_IntDefaultHandler_Enomem_Exception_Callback(); + #endif /* CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK */ + + while(1) + { + /* Out Of Heap Space + * This can be increased in the System tab of the Design Wide Resources. + */ + } + } + else + #endif + { + #ifdef CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK + CyBoot_IntDefaultHandler_Exception_EntryCallback(); + #endif /* CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK */ + + while(1) + { + + } + } +} + + +#if defined(__ARMCC_VERSION) + +/* Local function for device reset. */ +extern void Reset(void); + +/* Application entry point. */ +extern void $Super$$main(void); + +///* Linker-generated Stack Base addresses, Two Region and One Region */ +//extern uint32 Image$$ARM_LIB_STACK$$ZI$$Limit; + +/* RealView C Library initialization. */ +extern int __main(void); + + +/******************************************************************************* +* Function Name: Reset +****************************************************************************//** +* +* This function handles the reset interrupt for the RVDS/MDK toolchains. +* This is the first bit of code that is executed at startup. +* +*******************************************************************************/ +void Reset(void) +{ + #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + /* For PSoC 5LP, debugging is enabled by default */ + #if(CYDEV_DEBUGGING_ENABLE == 0) + *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; + #endif /* (CYDEV_DEBUGGING_ENABLE) */ + + /* Reset Status Register has Read-to-clear SW access mode. + * Preserve current RESET_SR0 state to make it available for next reading. + */ + *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); + + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */ + + #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + CyBtldr_CheckLaunch(); + #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */ + + __main(); +} + + +/******************************************************************************* +* Function Name: $Sub$$main +****************************************************************************//** +* +* This function is called immediately before the users main +* +*******************************************************************************/ +void $Sub$$main(void) +{ + initialize_psoc(); + + /* Call original main */ + $Super$$main(); + + while (1) + { + /* If main returns, it is undefined what we should do. */ + } +} + +#elif defined(__GNUC__) + +void Start_c(void); + +/* Stack Base address */ +extern void __cy_stack(void); + +/* Application entry point. */ +extern int main(void); + +/* Static objects constructors initializer */ +extern void __libc_init_array(void); + +typedef unsigned char __cy_byte_align8 __attribute ((aligned (8))); + +struct __cy_region +{ + __cy_byte_align8 *init; /* Initial contents of this region. */ + __cy_byte_align8 *data; /* Start address of region. */ + size_t init_size; /* Size of initial data. */ + size_t zero_size; /* Additional size to be zeroed. */ +}; + +extern const struct __cy_region __cy_regions[]; +extern const char __cy_region_num __attribute__((weak)); +#define __cy_region_num ((size_t)&__cy_region_num) + + +/******************************************************************************* +* System Calls of the Red Hat newlib C Library +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: _exit +****************************************************************************//** +* +* Exit a program without cleaning up files. If your system doesn't provide +* this, it is best to avoid linking with subroutines that require it (exit, +* system). +* +* \param status: Status caused program exit. +* +*******************************************************************************/ +__attribute__((weak)) +void _exit(int status) +{ + CyHalt((uint8) status); + while(1) + { + + } +} + + +/******************************************************************************* +* Function Name: _sbrk +****************************************************************************//** +* +* Increase program data space. As malloc and related functions depend on this, +* it is useful to have a working implementation. The following suffices for a +* standalone system; it exploits the symbol end automatically defined by the +* GNU linker. +* +* \param nbytes: The number of bytes requested (if the parameter value is positive) +* from the heap or returned back to the heap (if the parameter value is +* negative). +* +*******************************************************************************/ +__attribute__((weak)) +void * _sbrk (int nbytes) +{ + extern int end; /* Symbol defined by linker map. Start of free memory (as symbol). */ + void * returnValue; + + /* The statically held previous end of the heap, with its initialization. */ + static uint8 *heapPointer = (uint8 *) &end; /* Previous end */ + + if (((heapPointer + nbytes) - (uint8 *) &end) <= CYDEV_HEAP_SIZE) + { + returnValue = (void *) heapPointer; + heapPointer += nbytes; + } + else + { + errno = ENOMEM; + returnValue = (void *) -1; + } + + return (returnValue); +} + + +/******************************************************************************* +* Function Name: Reset +****************************************************************************//** +* +* This function handles the reset interrupt for the GCC toolchain. This is the +* first bit of code that is executed at startup. +* +*******************************************************************************/ +void Reset(void) +{ + #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + /* For PSoC 5LP, debugging is enabled by default */ + #if(CYDEV_DEBUGGING_ENABLE == 0) + *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; + #endif /* (CYDEV_DEBUGGING_ENABLE) */ + + /* Reset Status Register has Read-to-clear SW access mode. + * Preserve current RESET_SR0 state to make it available for next reading. + */ + *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); + + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */ + + #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + CyBtldr_CheckLaunch(); + #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */ + + Start_c(); +} + + +/******************************************************************************* +* Function Name: Start_c +****************************************************************************//** +* +* This function handles initializing the .data and .bss sections in +* preparation for running the standard C code. Once initialization is complete +* it will call main(). This function will never return. +* +*******************************************************************************/ +void Start_c(void) __attribute__ ((noreturn)); +void Start_c(void) +{ + unsigned regions = __cy_region_num; + const struct __cy_region *rptr = __cy_regions; + + /* Initialize memory */ + for (regions = __cy_region_num; regions != 0u; regions--) + { + uint32 *src = (uint32 *)rptr->init; + uint32 *dst = (uint32 *)rptr->data; + unsigned limit = rptr->init_size; + unsigned count; + + for (count = 0u; count != limit; count += sizeof (uint32)) + { + *dst = *src; + dst++; + src++; + } + limit = rptr->zero_size; + for (count = 0u; count != limit; count += sizeof (uint32)) + { + *dst = 0u; + dst++; + } + + rptr++; + } + + /* Invoke static objects constructors */ + __libc_init_array(); + (void) main(); + + while (1) + { + /* If main returns, make sure we don't return. */ + } +} + + +#elif defined (__ICCARM__) + +/******************************************************************************* +* Function Name: __low_level_init +****************************************************************************//** +* +* This function performs early initializations for the IAR Embedded +* Workbench IDE. It is executed in the context of a reset interrupt handler +* before the data sections are initialized. +* +* \return +* The value that determines whether or not data sections should be initialized +* by the system startup code: +* 0 - skip data sections initialization; +* 1 - initialize data sections; +* +*******************************************************************************/ +int __low_level_init(void) +{ + #if (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + /* For PSoC 5LP, debugging is enabled by default */ + #if(CYDEV_DEBUGGING_ENABLE == 0) + *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; + #endif /* (CYDEV_DEBUGGING_ENABLE) */ + + /* Reset Status Register has Read-to-clear SW access mode. + * Preserve current RESET_SR0 state to make it available for next reading. + */ + *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); + + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */ + + #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + CyBtldr_CheckLaunch(); + #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */ + + /* Initialize data sections */ + __iar_data_init3(); + + initialize_psoc(); + + return 0; +} + +#endif /* __GNUC__ */ + + +/******************************************************************************* +* +* Default Rom Interrupt Vector table. +* +*******************************************************************************/ +const cyisraddress *RomVectors = (cyisraddress *) DAPLINK_ROM_APP_START; + +/******************************************************************************* +* Function Name: initialize_psoc +****************************************************************************//** +* +* This function used to initialize the PSoC chip before calling main. +* +*******************************************************************************/ +#if (defined(__GNUC__) && !defined(__ARMCC_VERSION)) +__attribute__ ((constructor(101))) +#endif +void initialize_psoc(void) +{ + uint32 i; + + /* Set Priority group 5. */ + + /* Writes to NVIC_APINT register require the VECTKEY in the upper half */ + *CY_NVIC_APINT_PTR = CY_NVIC_APINT_VECTKEY | CY_NVIC_APINT_PRIGROUP_3_5; + *CY_NVIC_CFG_CTRL_PTR |= CY_NVIC_CFG_STACKALIGN; + + /* Set Ram interrupt vectors to default functions. */ + for (i = 0u; i < CY_NUM_VECTORS; i++) + { + #if defined (__ICCARM__) + CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? __vector_table[i].__fun : &IntDefaultHandler; + #else + CyRamVectors[i] = RomVectors[i]; + #endif /* defined (__ICCARM__) */ + + } + + /* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */ + CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1); + + /* Point NVIC at RAM vector table. */ + *CYINT_VECT_TABLE = CyRamVectors; + + /* Initialize the configuration registers. */ + cyfitter_cfg(); + + #if(0u != DMA_CHANNELS_USED__MASK0) + + /* Setup DMA - only necessary if design contains DMA component. */ + CyDmacConfigure(); + + #endif /* (0u != DMA_CHANNELS_USED__MASK0) */ + + #if !defined (__ICCARM__) + /* Actually, no need to clean this variable, just to make compiler happy. */ + cySysNoInitDataValid = 0u; + #endif /* !defined (__ICCARM__) */ +} + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/CyDmac.h b/source/hic_hal/cypress/psoc5lp/PSoC5/CyDmac.h new file mode 100644 index 0000000000..7c95991b1c --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/CyDmac.h @@ -0,0 +1,234 @@ +/***************************************************************************//** +* \file CyDmac.h +* \version 5.70 +* +* \brief Provides the function definitions for the DMA Controller. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_BOOT_CYDMAC_H) +#define CY_BOOT_CYDMAC_H + + +#include "cytypes.h" +#include "cyfitter.h" +#include "cydevice_trm.h" +#include "CyLib.h" + + +/*************************************** +* Function Prototypes +***************************************/ + +/* DMA Controller functions. */ +void CyDmacConfigure(void) ; +uint8 CyDmacError(void) ; +void CyDmacClearError(uint8 error) ; +uint32 CyDmacErrorAddress(void) ; + +/* Channel specific functions. */ +uint8 CyDmaChAlloc(void) ; +cystatus CyDmaChFree(uint8 chHandle) ; +cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) ; +cystatus CyDmaChDisable(uint8 chHandle) ; +cystatus CyDmaClearPendingDrq(uint8 chHandle) ; +cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) ; +cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination)\ +; +cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) ; +cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) ; +cystatus CyDmaChGetRequest(uint8 chHandle) ; +cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) ; +cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0, + uint8 tdDone1, uint8 tdStop) ; +cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) ; + +/* Transfer Descriptor functions. */ +uint8 CyDmaTdAllocate(void) ; +void CyDmaTdFree(uint8 tdHandle) ; +uint8 CyDmaTdFreeCount(void) ; +cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration)\ +; +cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration)\ +; +cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) ; +cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) ; + + +/*************************************** +* Data Struct Definitions +***************************************/ + +typedef struct dmac_ch_struct +{ + volatile uint8 basic_cfg[4]; + volatile uint8 action[4]; + volatile uint8 basic_status[4]; + volatile uint8 reserved[4]; + +} dmac_ch; + + +typedef struct dmac_cfgmem_struct +{ + volatile uint8 CFG0[4]; + volatile uint8 CFG1[4]; + +} dmac_cfgmem; + + +typedef struct dmac_tdmem_struct +{ + volatile uint8 TD0[4]; + volatile uint8 TD1[4]; + +} dmac_tdmem; + + +typedef struct dmac_tdmem2_struct +{ + volatile uint16 xfercnt; + volatile uint8 next_td_ptr; + volatile uint8 flags; + volatile uint16 src_adr; + volatile uint16 dst_adr; +} dmac_tdmem2; + + +/*************************************** +* API Constants +***************************************/ + +#define CY_DMA_INVALID_CHANNEL 0xFFu /* Invalid Channel ID */ +#define CY_DMA_INVALID_TD 0xFFu /* Invalid TD */ +#define CY_DMA_END_CHAIN_TD 0xFFu /* End of chain TD */ +#define CY_DMA_DISABLE_TD 0xFEu + +#define CY_DMA_TD_SIZE 0x08u + +/* "u" was removed as workaround for Keil compiler bug */ +#define CY_DMA_TD_SWAP_EN 0x80 +#define CY_DMA_TD_SWAP_SIZE4 0x40 +#define CY_DMA_TD_AUTO_EXEC_NEXT 0x20 +#define CY_DMA_TD_TERMIN_EN 0x10 +#define CY_DMA_TD_TERMOUT1_EN 0x08 +#define CY_DMA_TD_TERMOUT0_EN 0x04 +#define CY_DMA_TD_INC_DST_ADR 0x02 +#define CY_DMA_TD_INC_SRC_ADR 0x01 + +#define CY_DMA_NUMBEROF_TDS 128u +#define CY_DMA_NUMBEROF_CHANNELS ((uint8)(CYDEV_DMA_CHANNELS_AVAILABLE)) + +/* Action register bits */ +#define CY_DMA_CPU_REQ ((uint8)(1u << 0u)) +#define CY_DMA_CPU_TERM_TD ((uint8)(1u << 1u)) +#define CY_DMA_CPU_TERM_CHAIN ((uint8)(1u << 2u)) + +/* Basic Status register bits */ +#define CY_DMA_STATUS_CHAIN_ACTIVE ((uint8)(1u << 0u)) +#define CY_DMA_STATUS_TD_ACTIVE ((uint8)(1u << 1u)) + +/* DMA controller register error bits */ +#define CY_DMA_BUS_TIMEOUT (1u << 1u) +#define CY_DMA_UNPOP_ACC (1u << 2u) +#define CY_DMA_PERIPH_ERR (1u << 3u) + +/* Round robin bits */ +#define CY_DMA_ROUND_ROBIN_ENABLE ((uint8)(1u << 4u)) + + +/******************************************************************************* +* CyDmaChEnable() / CyDmaChDisable() API constants +*******************************************************************************/ +#define CY_DMA_CH_BASIC_CFG_EN (0x01u) +#define CY_DMA_CH_BASIC_CFG_WORK_SEP (0x20u) + + +/*************************************** +* Registers +***************************************/ + +#define CY_DMA_CFG_REG (*(reg32 *) CYREG_PHUB_CFG) +#define CY_DMA_CFG_PTR ( (reg32 *) CYREG_PHUB_CFG) + +#define CY_DMA_ERR_REG (*(reg32 *) CYREG_PHUB_ERR) +#define CY_DMA_ERR_PTR ( (reg32 *) CYREG_PHUB_ERR) + +#define CY_DMA_ERR_ADR_REG (*(reg32 *) CYREG_PHUB_ERR_ADR) +#define CY_DMA_ERR_ADR_PTR ( (reg32 *) CYREG_PHUB_ERR_ADR) + +#define CY_DMA_CH_STRUCT_REG (*(dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE) +#define CY_DMA_CH_STRUCT_PTR ( (dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE) + +#define CY_DMA_CFGMEM_STRUCT_REG (*(dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE) +#define CY_DMA_CFGMEM_STRUCT_PTR ( (dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE) + +#define CY_DMA_TDMEM_STRUCT_REG (*(dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE) +#define CY_DMA_TDMEM_STRUCT_PTR ( (dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE) + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define DMA_INVALID_CHANNEL (CY_DMA_INVALID_CHANNEL) +#define DMA_INVALID_TD (CY_DMA_INVALID_TD) +#define DMA_END_CHAIN_TD (CY_DMA_END_CHAIN_TD) +#define DMAC_TD_SIZE (CY_DMA_TD_SIZE) +#define TD_SWAP_EN (CY_DMA_TD_SWAP_EN) +#define TD_SWAP_SIZE4 (CY_DMA_TD_SWAP_SIZE4) +#define TD_AUTO_EXEC_NEXT (CY_DMA_TD_AUTO_EXEC_NEXT) +#define TD_TERMIN_EN (CY_DMA_TD_TERMIN_EN) +#define TD_TERMOUT1_EN (CY_DMA_TD_TERMOUT1_EN) +#define TD_TERMOUT0_EN (CY_DMA_TD_TERMOUT0_EN) +#define TD_INC_DST_ADR (CY_DMA_TD_INC_DST_ADR) +#define TD_INC_SRC_ADR (CY_DMA_TD_INC_SRC_ADR) +#define NUMBEROF_TDS (CY_DMA_NUMBEROF_TDS) +#define NUMBEROF_CHANNELS (CY_DMA_NUMBEROF_CHANNELS) +#define CPU_REQ (CY_DMA_CPU_REQ) +#define CPU_TERM_TD (CY_DMA_CPU_TERM_TD) +#define CPU_TERM_CHAIN (CY_DMA_CPU_TERM_CHAIN) +#define STATUS_CHAIN_ACTIVE (CY_DMA_STATUS_CHAIN_ACTIVE) +#define STATUS_TD_ACTIVE (CY_DMA_STATUS_TD_ACTIVE) +#define DMAC_BUS_TIMEOUT (CY_DMA_BUS_TIMEOUT) +#define DMAC_UNPOP_ACC (CY_DMA_UNPOP_ACC) +#define DMAC_PERIPH_ERR (CY_DMA_PERIPH_ERR) +#define ROUND_ROBIN_ENABLE (CY_DMA_ROUND_ROBIN_ENABLE) +#define DMA_DISABLE_TD (CY_DMA_DISABLE_TD) + +#define DMAC_CFG (CY_DMA_CFG_PTR) +#define DMAC_ERR (CY_DMA_ERR_PTR) +#define DMAC_ERR_ADR (CY_DMA_ERR_ADR_PTR) +#define DMAC_CH (CY_DMA_CH_STRUCT_PTR) +#define DMAC_CFGMEM (CY_DMA_CFGMEM_STRUCT_PTR) +#define DMAC_TDMEM (CY_DMA_TDMEM_STRUCT_PTR) + +#endif /* (CY_BOOT_CYDMAC_H) */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/CyFlash.c b/source/hic_hal/cypress/psoc5lp/PSoC5/CyFlash.c new file mode 100644 index 0000000000..a7b38c5761 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/CyFlash.c @@ -0,0 +1,762 @@ +/***************************************************************************//** +* \file CyFlash.c +* \version 5.70 +* +* \brief Provides an API for the FLASH/EEPROM. +* +* \note This code is endian agnostic. +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "CyFlash.h" + +/* The number of EEPROM arrays */ +#define CY_FLASH_EEPROM_NUMBER_ARRAYS (1u) + + +/******************************************************************************* +* Holds the die temperature, updated by CySetTemp(). Used for flash writing. +* The first byte is the sign of the temperature (0 = negative, 1 = positive). +* The second byte is the magnitude. +*******************************************************************************/ +uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE]; + +#if(CYDEV_ECC_ENABLE == 0) + static uint8 * rowBuffer = 0; +#endif /* (CYDEV_ECC_ENABLE == 0) */ + + +static cystatus CySetTempInt(void); + + +/******************************************************************************* +* Function Name: CyFlash_Start +****************************************************************************//** +* +* Enable the Flash. +* +*******************************************************************************/ +void CyFlash_Start(void) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + + /*************************************************************************** + * Enable SPC clock. This also internally enables the 36MHz IMO, since this + * is required for the SPC to function. + ***************************************************************************/ + CY_FLASH_PM_ACT_CFG0_REG |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC; + CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC; + + + /*************************************************************************** + * The wake count defines the number of Bus Clock cycles it takes for the + * flash or eeprom to wake up from a low power mode independent of the chip + * power mode. Wake up time for these blocks is 5 us. + * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E + * (30d) defines the wake up time as 60 cycles of the Bus Clock. + * This register needs to be written with a value dependent on the Bus Clock + * frequency so that the duration of the cycles is equal to or greater than + * the 5 us delay required. + ***************************************************************************/ + CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ; + + + /*************************************************************************** + * Enable flash. Active flash macros consume current, but re-enabling a + * disabled flash macro takes 5us. If the CPU attempts to fetch out of the + * macro during that time, it will be stalled. This bit allows the flash to + * be enabled even if the CPU is disabled, which allows a quicker return to + * code execution. + ***************************************************************************/ + CY_FLASH_PM_ACT_CFG12_REG |= CY_FLASH_PM_ACT_CFG12_EN_FM; + CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_FM; + + while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE)) + { + /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */ + } + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyFlash_Stop +****************************************************************************//** +* +* Disable the Flash. +* +* \sideeffect +* This setting is ignored as long as the CPU is currently running. This will +* only take effect when the CPU is later disabled. +* +*******************************************************************************/ +void CyFlash_Stop(void) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + CY_FLASH_PM_ACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_FM)); + CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_FM)); + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyFlash_EraseRow +****************************************************************************//** +* +* Erases a single row of flash. Reports success or reason for failure. +* The API does not return until the erase operation is complete. +* +* \param arrayID: ID of the array to erase. +* The arrays in the part are sequential starting at the first ID for the +* Flash memory type. +* \param rowAddress: Row address within the specified arrayId. +* +* \return +* status: +* CYRET_SUCCESS if successful. +* CYRET_LOCKED if the SPC is already in use. +* CYRET_CANCELED if command not accepted +* CYRET_UNKNOWN if there was an SPC error. +* CYRET_BAD_PARAM if one or more invalid parameters +* +*******************************************************************************/ +cystatus CyFlash_EraseRow(uint8 arrayId, uint16 rowAddress) +{ + cystatus status = CYRET_SUCCESS; + + if (arrayId > CY_SPC_LAST_FLASH_ARRAYID) + { + status = CYRET_BAD_PARAM; + } + else if(rowAddress > (CY_FLASH_NUMBER_ROWS/CY_FLASH_NUMBER_ARRAYS)) + { + status = CYRET_BAD_PARAM; + } + else + { + if(CySpcLock() == CYRET_SUCCESS) + { + /* Erase flash row */ + status = CySpcEraseRow(arrayId, rowAddress, dieTemperature[0u], dieTemperature[1u]); + + if(CYRET_STARTED == status) + { + while(CY_SPC_BUSY) + { + /* Wait for SPC to finish and get SPC status */ + CyDelayUs(1u); + } + + /* Hide SPC status */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + else + { + status = CYRET_UNKNOWN; + } + } + else + { + status = CYRET_CANCELED; + } + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySetTempInt +****************************************************************************//** +* +* Sends a command to the SPC to read the die temperature. Sets a global value +* used by the Write function. This function must be called once before +* executing a series of Flash writing functions. +* +* \return +* status: +* CYRET_SUCCESS - if successful +* CYRET_LOCKED - if Flash writing already in use +* CYRET_UNKNOWN - if there was an SPC error +* +*******************************************************************************/ +static cystatus CySetTempInt(void) +{ + cystatus status; + + /* Make sure SPC is powered */ + CySpcStart(); + + /* Plan for failure. */ + status = CYRET_UNKNOWN; + + if(CySpcLock() == CYRET_SUCCESS) + { + /* Write the command. */ + if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES)) + { + do + { + if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE) + { + status = CYRET_SUCCESS; + + while(CY_SPC_BUSY) + { + /* Spin until idle. */ + CyDelayUs(1u); + } + break; + } + + } while(CY_SPC_BUSY); + } + + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CyFlashGetSpcAlgorithm +****************************************************************************//** +* +* Sends a command to the SPC to download code into RAM. +* +* \return +* status: +* CYRET_SUCCESS - if successful +* CYRET_LOCKED - if Flash writing already in use +* CYRET_UNKNOWN - if there was an SPC error +* +*******************************************************************************/ +cystatus CyFlashGetSpcAlgorithm(void) +{ + cystatus status; + + /* Make sure SPC is powered */ + CySpcStart(); + + if(CySpcLock() == CYRET_SUCCESS) + { + status = CySpcGetAlgorithm(); + + if(CYRET_STARTED == status) + { + while(CY_SPC_BUSY) + { + /* Spin until idle. */ + CyDelayUs(1u); + } + + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + } + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CySetTemp +****************************************************************************//** +* +* This is a wraparound for CySetTempInt(). It is used to return the second +* successful read of the temperature value. +* +* \return +* status: +* CYRET_SUCCESS if successful. +* CYRET_LOCKED if Flash writing already in use +* CYRET_UNKNOWN if there was an SPC error. +* +* uint8 dieTemperature[2]: +* Holds the die temperature for the flash writing algorithm. The first byte is +* the sign of the temperature (0 = negative, 1 = positive). The second byte is +* the magnitude. +* +*******************************************************************************/ +cystatus CySetTemp(void) +{ + cystatus status = CyFlashGetSpcAlgorithm(); + + if(status == CYRET_SUCCESS) + { + status = CySetTempInt(); + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CySetFlashEEBuffer +****************************************************************************//** +* +* Sets the user supplied temporary buffer to store SPC data while performing +* Flash and EEPROM commands. This buffer is only necessary when the Flash ECC +* is disabled. +* +* \param buffer: +* The address of a block of memory to store temporary memory. The size of the +* block of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE. +* +* \return +* status: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if the buffer is NULL +* +*******************************************************************************/ +cystatus CySetFlashEEBuffer(uint8 * buffer) +{ + cystatus status = CYRET_SUCCESS; + + CySpcStart(); + + #if(CYDEV_ECC_ENABLE == 0) + + if(NULL == buffer) + { + rowBuffer = rowBuffer; + status = CYRET_BAD_PARAM; + } + else if(CySpcLock() != CYRET_SUCCESS) + { + rowBuffer = rowBuffer; + status = CYRET_LOCKED; + } + else + { + rowBuffer = buffer; + CySpcUnlock(); + } + + #else + + /* To suppress warning */ + buffer = buffer; + + #endif /* (CYDEV_ECC_ENABLE == 0u) */ + + return(status); +} + + +/******************************************************************************* +* Function Name: CyWriteRowData +****************************************************************************//** +* +* Sends a command to the SPC to load and program a row of data in +* Flash or EEPROM. +* +* \param arrayID: ID of the array to write. +* The type of write, Flash or EEPROM, is determined from the array ID. +* The arrays in the part are sequential starting at the first ID for the +* specific memory type. The array ID for the Flash memory lasts from 0x00 to +* 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F. +* \param rowAddress: rowAddress of flash row to program. +* \param rowData: Array of bytes to write. +* +* \return +* status: +* CYRET_SUCCESS if successful. +* CYRET_LOCKED if the SPC is already in use. +* CYRET_CANCELED if command not accepted +* CYRET_UNKNOWN if there was an SPC error. +* +*******************************************************************************/ +cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) +{ + uint16 rowSize; + cystatus status; + + rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE; + status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize); + + return(status); +} + + +/******************************************************************* +* If "Enable Error Correcting Code (ECC)" and "Store Configuration +* Data in ECC" DWR options are disabled, ECC section is available +* for user data. +*******************************************************************/ +#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) + + /******************************************************************************* + * Function Name: CyWriteRowConfig + ****************************************************************************//** + * + * Sends a command to the SPC to load and program a row of config data in the + * Flash. This function is only valid for Flash array IDs (not for EEPROM). + * + * \param arrayId: ID of the array to write + * The arrays in the part are sequential starting at the first ID for the + * specific memory type. The array ID for the Flash memory lasts + * from 0x00 to 0x3F. + * \param rowAddress: The address of the sector to erase. + * \param rowECC: The array of bytes to write. + * + * \return + * status: + * CYRET_SUCCESS if successful. + * CYRET_LOCKED if the SPC is already in use. + * CYRET_CANCELED if command not accepted + * CYRET_UNKNOWN if there was an SPC error. + * + *******************************************************************************/ + cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\ + + { + cystatus status; + + status = CyWriteRowFull(arrayId, rowAddress, rowECC, CYDEV_ECC_ROW_SIZE); + + return (status); + } + +#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ + + + +/******************************************************************************* +* Function Name: CyWriteRowFull +****************************************************************************//** +* Sends a command to the SPC to load and program a row of data in the Flash. +* rowData array is expected to contain Flash and ECC data if needed. +* +* \param arrayId: FLASH or EEPROM array id. +* \param rowData: Pointer to a row of data to write. +* \param rowNumber: Zero based number of the row. +* \param rowSize: Size of the row. +* +* \return +* CYRET_SUCCESS if successful. +* CYRET_LOCKED if the SPC is already in use. +* CYRET_CANCELED if command not accepted +* CYRET_UNKNOWN if there was an SPC error. +* +*******************************************************************************/ +cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \ + +{ + cystatus status = CYRET_SUCCESS; + + if((arrayId <= CY_SPC_LAST_FLASH_ARRAYID) && (arrayId > (CY_FLASH_NUMBER_ARRAYS + CY_SPC_FIRST_FLASH_ARRAYID))) + { + status = CYRET_BAD_PARAM; + } + + if(arrayId > CY_SPC_LAST_EE_ARRAYID) + { + status = CYRET_BAD_PARAM; + } + + if((arrayId >= CY_SPC_FIRST_EE_ARRAYID) && (arrayId > (CY_FLASH_EEPROM_NUMBER_ARRAYS + CY_SPC_FIRST_EE_ARRAYID))) + { + status = CYRET_BAD_PARAM; + } + + if(arrayId <= CY_SPC_LAST_FLASH_ARRAYID) + { + /* Flash */ + if(rowNumber > (CY_FLASH_NUMBER_ROWS/CY_FLASH_NUMBER_ARRAYS)) + { + status = CYRET_BAD_PARAM; + } + } + else + { + /* EEPROM */ + if(rowNumber > (CY_EEPROM_NUMBER_ROWS/CY_FLASH_EEPROM_NUMBER_ARRAYS)) + { + status = CYRET_BAD_PARAM; + } + + if(CY_EEPROM_SIZEOF_ROW != rowSize) + { + status = CYRET_BAD_PARAM; + } + } + + if(rowData == NULL) + { + status = CYRET_BAD_PARAM; + } + + + if(status == CYRET_SUCCESS) + { + if(CySpcLock() == CYRET_SUCCESS) + { + /* Load row data into SPC internal latch */ + status = CySpcLoadRowFull(arrayId, rowNumber, rowData, rowSize); + + if(CYRET_STARTED == status) + { + while(CY_SPC_BUSY) + { + /* Wait for SPC to finish and get SPC status */ + CyDelayUs(1u); + } + + /* Hide SPC status */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + else + { + status = CYRET_UNKNOWN; + } + + if(CYRET_SUCCESS == status) + { + /* Erase and program flash with data from SPC interval latch */ + status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]); + + if(CYRET_STARTED == status) + { + while(CY_SPC_BUSY) + { + /* Wait for SPC to finish and get SPC status */ + CyDelayUs(1u); + } + + /* Hide SPC status */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + else + { + status = CYRET_UNKNOWN; + } + } + } + } + CySpcUnlock(); + } /* if(CySpcLock() == CYRET_SUCCESS) */ + else + { + status = CYRET_LOCKED; + } + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyFlash_SetWaitCycles +****************************************************************************//** +* +* Sets the number of clock cycles the cache will wait before it samples data +* coming back from the Flash. This function must be called before increasing +* the CPU clock frequency. It can optionally be called after lowering the CPU +* clock frequency in order to improve the CPU performance. +* +* \param uint8 freq: +* Frequency of operation in Megahertz. +* +*******************************************************************************/ +void CyFlash_SetWaitCycles(uint8 freq) +{ + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + /*************************************************************************** + * The number of clock cycles the cache will wait before it samples data + * coming back from the Flash must be equal or greater to to the CPU frequency + * outlined in clock cycles. + ***************************************************************************/ + + if (freq < CY_FLASH_CACHE_WS_1_FREQ_MAX) + { + CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) | + CY_FLASH_CACHE_WS_1_VALUE_MASK; + } + else if (freq < CY_FLASH_CACHE_WS_2_FREQ_MAX) + { + CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) | + CY_FLASH_CACHE_WS_2_VALUE_MASK; + } + else if (freq < CY_FLASH_CACHE_WS_3_FREQ_MAX) + { + CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) | + CY_FLASH_CACHE_WS_3_VALUE_MASK; + } +#if (CY_PSOC5) + else if (freq < CY_FLASH_CACHE_WS_4_FREQ_MAX) + { + CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) | + CY_FLASH_CACHE_WS_4_VALUE_MASK; + } + else if (freq <= CY_FLASH_CACHE_WS_5_FREQ_MAX) + { + CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) | + CY_FLASH_CACHE_WS_5_VALUE_MASK; + } +#endif /* (CY_PSOC5) */ + else + { + /* Halt CPU in debug mode if frequency is invalid */ + CYASSERT(0u != 0u); + } + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyEEPROM_Start +****************************************************************************//** +* +* Enable the EEPROM. +* +*******************************************************************************/ +void CyEEPROM_Start(void) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + + /*************************************************************************** + * Enable SPC clock. This also internally enables the 36MHz IMO, since this + * is required for the SPC to function. + ***************************************************************************/ + CY_FLASH_PM_ACT_CFG0_REG |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC; + CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC; + + + /*************************************************************************** + * The wake count defines the number of Bus Clock cycles it takes for the + * flash or EEPROM to wake up from a low power mode independent of the chip + * power mode. Wake up time for these blocks is 5 us. + * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E + * (30d) defines the wake up time as 60 cycles of the Bus Clock. + * This register needs to be written with a value dependent on the Bus Clock + * frequency so that the duration of the cycles is equal to or greater than + * the 5 us delay required. + ***************************************************************************/ + CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ; + + + /*************************************************************************** + * Enable EEPROM. Re-enabling an EEPROM macro takes 5us. During this time, + * the EE will not acknowledge a PHUB request. + ***************************************************************************/ + CY_FLASH_PM_ACT_CFG12_REG |= CY_FLASH_PM_ACT_CFG12_EN_EE; + CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_EE; + + while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE)) + { + /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */ + } + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyEEPROM_Stop +****************************************************************************//** +* +* Disable the EEPROM. +* +*******************************************************************************/ +void CyEEPROM_Stop (void) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + CY_FLASH_PM_ACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_EE)); + CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_EE)); + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyEEPROM_ReadReserve +****************************************************************************//** +* +* Request access to the EEPROM for reading and wait until access is available. +* +*******************************************************************************/ +void CyEEPROM_ReadReserve(void) +{ + /* Make request for PHUB to have access */ + CY_FLASH_EE_SCR_REG |= CY_FLASH_EE_SCR_AHB_EE_REQ; + + while (0u == (CY_FLASH_EE_SCR_REG & CY_FLASH_EE_SCR_AHB_EE_ACK)) + { + /* Wait for acknowledgment from PHUB */ + } +} + + +/******************************************************************************* +* Function Name: CyEEPROM_ReadRelease +****************************************************************************//** +* +* Release the read reservation of the EEPROM. +* +*******************************************************************************/ +void CyEEPROM_ReadRelease(void) +{ + CY_FLASH_EE_SCR_REG &= (uint8)(~CY_FLASH_EE_SCR_AHB_EE_REQ); +} + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/CyFlash.h b/source/hic_hal/cypress/psoc5lp/PSoC5/CyFlash.h new file mode 100644 index 0000000000..2d3a19c8a7 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/CyFlash.h @@ -0,0 +1,329 @@ +/***************************************************************************//** +* \file CyFlash.h +* \version 5.70 +* +* \brief Provides the function definitions for the FLASH/EEPROM. +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_BOOT_CYFLASH_H) +#define CY_BOOT_CYFLASH_H + +#include "cydevice_trm.h" +#include "cytypes.h" +#include "CyLib.h" +#include "CySpc.h" + +#define CY_FLASH_DIE_TEMP_DATA_SIZE (2u) /* Die temperature data size */ + +extern uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE]; + + +/*************************************** +* API Constants +***************************************/ + +#define CY_FLASH_BASE (CYDEV_FLASH_BASE) +#define CY_FLASH_SIZE (CYDEV_FLS_SIZE) +#define CY_FLASH_SIZEOF_ARRAY (CYDEV_FLS_SECTOR_SIZE) +#define CY_FLASH_SIZEOF_ROW (CYDEV_FLS_ROW_SIZE) +#define CY_FLASH_SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE) +#define CY_FLASH_NUMBER_ROWS (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE) +#define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE) + +#if(CYDEV_ECC_ENABLE == 0) + #define CY_FLASH_SIZEOF_FULL_ROW (CY_FLASH_SIZEOF_ROW + CY_FLASH_SIZEOF_ECC_ROW) +#else + #define CY_FLASH_SIZEOF_FULL_ROW (CY_FLASH_SIZEOF_ROW) +#endif /* (CYDEV_ECC_ENABLE == 0) */ +#define CY_EEPROM_BASE (CYDEV_EE_BASE) +#define CY_EEPROM_SIZE (CYDEV_EE_SIZE) +#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EE_SIZE) /* EEPROM has one array */ +#define CY_EEPROM_SIZEOF_ROW (CYDEV_EEPROM_ROW_SIZE) +#define CY_EEPROM_NUMBER_ROWS (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE) +#define CY_EEPROM_NUMBER_ARRAYS (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY) +#define CY_EEPROM_NUMBER_SECTORS (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE) +#define CY_EEPROM_SIZEOF_SECTOR (CYDEV_EEPROM_SECTOR_SIZE) + +#if !defined(CYDEV_FLS_BASE) + #define CYDEV_FLS_BASE CYDEV_FLASH_BASE +#endif /* !defined(CYDEV_FLS_BASE) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/* Flash Functions */ +void CyFlash_Start(void); +void CyFlash_Stop(void); +cystatus CyFlash_EraseRow(uint8 arrayId, uint16 rowAddress); +cystatus CySetTemp(void); +cystatus CySetFlashEEBuffer(uint8 * buffer); +cystatus CyFlashGetSpcAlgorithm(void); +cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8 * rowData, uint16 rowSize) \ + ; +cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData); + +#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) + cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) \ + ; +#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ + +void CyFlash_SetWaitCycles(uint8 freq) ; + +/* EEPROM Functions */ +void CyEEPROM_Start(void) ; +void CyEEPROM_Stop(void) ; + +void CyEEPROM_ReadReserve(void) ; +void CyEEPROM_ReadRelease(void) ; + + +/*************************************** +* Registers +***************************************/ +/* Active Power Mode Configuration Register 0 */ +#define CY_FLASH_PM_ACT_CFG0_REG (* (reg8 *) CYREG_PM_ACT_CFG0) +#define CY_FLASH_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0) + +/* Alternate Active Power Mode Configuration Register 0 */ +#define CY_FLASH_PM_ALTACT_CFG0_REG (* (reg8 *) CYREG_PM_STBY_CFG0) +#define CY_FLASH_PM_ALTACT_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0) + +/* Active Power Mode Configuration Register 12 */ +#define CY_FLASH_PM_ACT_CFG12_REG (* (reg8 *) CYREG_PM_ACT_CFG12) +#define CY_FLASH_PM_ACT_CFG12_PTR ( (reg8 *) CYREG_PM_ACT_CFG12) + +/* Alternate Active Power Mode Configuration Register 12 */ +#define CY_FLASH_PM_ALTACT_CFG12_REG (* (reg8 *) CYREG_PM_STBY_CFG12) +#define CY_FLASH_PM_ALTACT_CFG12_PTR ( (reg8 *) CYREG_PM_STBY_CFG12) + +/* Wake count (BUS_CLK cycles) it takes for the Flash and EEPROM to wake up */ +#define CY_FLASH_SPC_FM_EE_WAKE_CNT_REG (* (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT) +#define CY_FLASH_SPC_FM_EE_WAKE_CNT_PTR ( (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT) + +/* Flash macro control register */ +#define CY_FLASH_SPC_FM_EE_CR_REG (* (reg8 *) CYREG_SPC_FM_EE_CR) +#define CY_FLASH_SPC_FM_EE_CR_PTR ( (reg8 *) CYREG_SPC_FM_EE_CR) + + +/* Cache Control Register */ +#if (CY_PSOC3) + + #define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CR ) + #define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CR ) + +#else + + #define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CC_CTL ) + #define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CC_CTL ) + +#endif /* (CY_PSOC3) */ + + +/* EEPROM Status & Control Register */ +#define CY_FLASH_EE_SCR_REG (* (reg8 *) CYREG_SPC_EE_SCR) +#define CY_FLASH_EE_SCR_PTR ( (reg8 *) CYREG_SPC_EE_SCR) + + + +/*************************************** +* Register Constants +***************************************/ + +/* Power Mode Masks */ + +/* Enable EEPROM */ +#define CY_FLASH_PM_ACT_CFG12_EN_EE (0x10u) +#define CY_FLASH_PM_ALTACT_CFG12_EN_EE (0x10u) + +/* Enable Flash */ +#if (CY_PSOC3) + #define CY_FLASH_PM_ACT_CFG12_EN_FM (0x01u) + #define CY_FLASH_PM_ALTACT_CFG12_EN_FM (0x01u) +#else + #define CY_FLASH_PM_ACT_CFG12_EN_FM (0x0Fu) + #define CY_FLASH_PM_ALTACT_CFG12_EN_FM (0x0Fu) +#endif /* (CY_PSOC3) */ + + + +/* Frequency Constants */ +#if (CY_PSOC3) + #define CY_FLASH_CACHE_WS_VALUE_MASK (0xC0u) + #define CY_FLASH_CACHE_WS_1_VALUE_MASK (0x40u) + #define CY_FLASH_CACHE_WS_2_VALUE_MASK (0x80u) + #define CY_FLASH_CACHE_WS_3_VALUE_MASK (0xC0u) + + #define CY_FLASH_CACHE_WS_1_FREQ_MAX (22u) + #define CY_FLASH_CACHE_WS_2_FREQ_MAX (44u) + #define CY_FLASH_CACHE_WS_3_FREQ_MAX (67u) +#endif /* (CY_PSOC3) */ + +#if (CY_PSOC5) + #define CY_FLASH_CACHE_WS_VALUE_MASK (0xE0u) + #define CY_FLASH_CACHE_WS_1_VALUE_MASK (0x40u) + #define CY_FLASH_CACHE_WS_2_VALUE_MASK (0x80u) + #define CY_FLASH_CACHE_WS_3_VALUE_MASK (0xC0u) + #define CY_FLASH_CACHE_WS_4_VALUE_MASK (0x00u) + #define CY_FLASH_CACHE_WS_5_VALUE_MASK (0x20u) + + #define CY_FLASH_CACHE_WS_1_FREQ_MAX (16u) + #define CY_FLASH_CACHE_WS_2_FREQ_MAX (33u) + #define CY_FLASH_CACHE_WS_3_FREQ_MAX (50u) + #define CY_FLASH_CACHE_WS_4_FREQ_MAX (67u) + #define CY_FLASH_CACHE_WS_5_FREQ_MAX (83u) +#endif /* (CY_PSOC5) */ + +#define CY_FLASH_CYCLES_MASK_SHIFT (0x06u) +#define CY_FLASH_CYCLES_MASK ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT))) + +#define CY_FLASH_EE_SCR_AHB_EE_REQ (0x01u) +#define CY_FLASH_EE_SCR_AHB_EE_ACK (0x02u) + + +#define CY_FLASH_EE_EE_AWAKE (0x20u) + +/* 5(us) * BUS_CLK(80 MHz) / granularity(2) */ +#define CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ (0xC8u) + +/* Enable clk_spc. This also internally enables the 36MHz IMO. */ +#define CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC (0x08u) +#define CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC (0x08u) + +/* Default values for getting temperature. */ + +#define CY_TEMP_NUMBER_OF_SAMPLES (0x1u) +#define CY_TEMP_TIMER_PERIOD (0xFFFu) +#define CY_TEMP_CLK_DIV_SELECT (0x4u) +#define CY_TEMP_NUM_SAMPLES (1 << (CY_TEMP_NUMBER_OF_SAMPLES)) +#define CY_SPC_CLK_PERIOD (120u) /* nS */ +#define CY_SYS_ns_PER_TICK (1000u) +#define CY_FRM_EXEC_TIME (1000u) /* nS */ + +#define CY_GET_TEMP_TIME ((1 << (CY_TEMP_NUM_SAMPLES + 1)) * \ + (CY_SPC_CLK_PERIOD * CY_TEMP_CLK_DIV_SELECT) * \ + CY_TEMP_TIMER_PERIOD + CY_FRM_EXEC_TIME) + +#define CY_TEMP_MAX_WAIT ((CY_GET_TEMP_TIME) / CY_SYS_ns_PER_TICK) /* In system ticks. */ + + +/******************************************************************************* +* Thne following code is OBSOLETE and must not be used starting with cy_boot +* 4.20. +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#if (CY_PSOC5) + #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u) + #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u) + #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u) + #define CY_FLASH_GREATER_51MHz (0x00u) +#endif /* (CY_PSOC5) */ + +#if (CY_PSOC3) + #define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u) + #define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u) + #define CY_FLASH_GREATER_44MHz (0x03u) +#endif /* (CY_PSOC3) */ + +#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12) +#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12) +#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12) +#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12) +#define CY_FLASH_PM_EE_MASK (0x10u) +#define CY_FLASH_PM_FLASH_MASK (0x01u) + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting with cy_boot 3.0 +*******************************************************************************/ +#define FLASH_SIZE (CY_FLASH_SIZE) +#define FLASH_SIZEOF_SECTOR (CY_FLASH_SIZEOF_ARRAY) +#define FLASH_NUMBER_ROWS (CY_FLASH_NUMBER_ROWS) +#define FLASH_NUMBER_SECTORS (CY_FLASH_NUMBER_ARRAYS) +#define EEPROM_SIZE (CY_EEPROM_SIZE) +#define EEPROM_SIZEOF_SECTOR (CYDEV_EEPROM_SECTOR_SIZE) +#define EEPROM_NUMBER_ROWS (CY_EEPROM_NUMBER_ROWS) +#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_SECTORS) + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting with cy_boot 3.30 +*******************************************************************************/ +#define FLASH_CYCLES_PTR (CY_FLASH_CONTROL_PTR) + +#define TEMP_NUMBER_OF_SAMPLES (CY_TEMP_NUMBER_OF_SAMPLES) +#define TEMP_TIMER_PERIOD (CY_TEMP_TIMER_PERIOD) +#define TEMP_CLK_DIV_SELECT (CY_TEMP_CLK_DIV_SELECT) +#define NUM_SAMPLES (CY_TEMP_NUM_SAMPLES) +#define SPC_CLK_PERIOD (CY_SPC_CLK_PERIOD) +#define FRM_EXEC_TIME (CY_FRM_EXEC_TIME) +#define GET_TEMP_TIME (CY_GET_TEMP_TIME) +#define TEMP_MAX_WAIT (CY_TEMP_MAX_WAIT) + +#define ECC_ADDR (0x80u) + + +#define PM_ACT_EE_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR) +#define PM_ACT_FLASH_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR) + +#define PM_STBY_EE_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR) +#define PM_STBY_FLASH_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR) + +#define PM_EE_MASK (CY_FLASH_PM_EE_MASK) +#define PM_FLASH_MASK (CY_FLASH_PM_FLASH_MASK) + +#define FLASH_CYCLES_MASK_SHIFT (CY_FLASH_CYCLES_MASK_SHIFT) +#define FLASH_CYCLES_MASK (CY_FLASH_CYCLES_MASK) + + +#if (CY_PSOC3) + + #define LESSER_OR_EQUAL_22MHz (CY_FLASH_LESSER_OR_EQUAL_22MHz) + #define LESSER_OR_EQUAL_44MHz (CY_FLASH_LESSER_OR_EQUAL_44MHz) + #define GREATER_44MHz (CY_FLASH_GREATER_44MHz) + +#endif /* (CY_PSOC3) */ + +#if (CY_PSOC5) + + #define LESSER_OR_EQUAL_16MHz (CY_FLASH_LESSER_OR_EQUAL_16MHz) + #define LESSER_OR_EQUAL_33MHz (CY_FLASH_LESSER_OR_EQUAL_33MHz) + #define LESSER_OR_EQUAL_50MHz (CY_FLASH_LESSER_OR_EQUAL_50MHz) + #define LESSER_OR_EQUAL_67MHz (CY_FLASH_LESSER_OR_EQUAL_67MHz) + #define GREATER_67MHz (CY_FLASH_GREATER_67MHz) + #define GREATER_51MHz (CY_FLASH_GREATER_51MHz) + +#endif /* (CY_PSOC5) */ + +#define AHUB_EE_REQ_ACK_PTR (CY_FLASH_EE_SCR_PTR) + + +#endif /* (CY_BOOT_CYFLASH_H) */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/CyLib.c b/source/hic_hal/cypress/psoc5lp/PSoC5/CyLib.c new file mode 100644 index 0000000000..4dc4460387 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/CyLib.c @@ -0,0 +1,2935 @@ +/***************************************************************************//** +* \file CyLib.c +* \version 5.70 +* +* \brief Provides a system API for the clocking, interrupts and watchdog timer. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "CyLib.h" + + +/******************************************************************************* +* The CyResetStatus variable is used to obtain value of RESET_SR0 register after +* a device reset. It is set from initialize_psoc() at the early initialization +* stage. In case of IAR EW IDE, initialize_psoc() is executed before the data +* sections are initialized. To avoid zeroing, CyResetStatus should be placed +* to the .noinit section. +*******************************************************************************/ +CY_NOINIT uint8 CYXDATA CyResetStatus; + + +/* Variable Vdda */ +#if(CYDEV_VARIABLE_VDDA == 1) + + uint8 CyScPumpEnabled = (uint8)(CYDEV_VDDA_MV < 2700); + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/* Do not use these definitions directly in your application */ +uint32 cydelay_freq_hz = BCLK__BUS_CLK__HZ; +uint32 cydelay_freq_khz = (BCLK__BUS_CLK__HZ + 999u) / 1000u; +uint8 cydelay_freq_mhz = (uint8)((BCLK__BUS_CLK__HZ + 999999u) / 1000000u); +uint32 cydelay_32k_ms = 32768u * ((BCLK__BUS_CLK__HZ + 999u) / 1000u); + + +/* Function Prototypes */ +static uint8 CyUSB_PowerOnCheck(void) ; +static void CyIMO_SetTrimValue(uint8 freq) ; +static void CyBusClk_Internal_SetDivider(uint16 divider); + +#if(CY_PSOC5) + static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS]; + static void CySysTickServiceCallbacks(void); + uint32 CySysTickInitVar = 0u; +#endif /* (CY_PSOC5) */ + + +#if(CY_PSOC3) + CY_ISR_PROTO(IntDefaultHandler); +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Function Name: CyPLL_OUT_Start +****************************************************************************//** +* +* Enables the PLL. Optionally waits for it to become stable. +* Waits at least 250 us or until it is detected that the PLL is stable. +* +* \param wait: +* \param 0: Return immediately after configuration +* \param 1: Wait for PLL lock or timeout. +* +* \return +* Status +* CYRET_SUCCESS - Completed successfully +* CYRET_TIMEOUT - Timeout occurred without detecting a stable clock. +* If the input source of the clock is jittery, then the lock indication +* may not occur. However, after the timeout has expired the generated PLL +* clock can still be used. +* +* \sideeffect +* If wait is enabled: This function uses the Fast Time Wheel to time the wait. +* Any other use of the Fast Time Wheel will be stopped during the period of +* this function and then restored. This function also uses the 100 KHz ILO. +* If not enabled, this function will enable the 100 KHz ILO for the period of +* this function. +* +* No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or +* Once Per Second interrupt may be made by interrupt routines during the period +* of this function execution. The current operation of the ILO, Central Time +* Wheel and Once Per Second interrupt are maintained during the operation of +* this function provided the reading of the Power Manager Interrupt Status +* Register is only done using the CyPmReadStatus() function. +* +*******************************************************************************/ +cystatus CyPLL_OUT_Start(uint8 wait) +{ + cystatus status = CYRET_SUCCESS; + + uint8 iloEnableState; + uint8 pmTwCfg0State; + uint8 pmTwCfg2State; + + + /* Enables PLL circuit */ + CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE; + + if(wait != 0u) + { + /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */ + iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; + pmTwCfg0State = CY_LIB_PM_TW_CFG0_REG; + pmTwCfg2State = CY_LIB_PM_TW_CFG2_REG; + + CyPmFtwSetInterval(CY_CLK_PLL_FTW_INTERVAL); + + status = CYRET_TIMEOUT; + + while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) + { + /* Wait for interrupt status */ + if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS)) + { + if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS)) + { + status = CYRET_SUCCESS; + break; + } + } + } + + /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */ + if(0u == iloEnableState) + { + CyILO_Stop100K(); + } + + CY_LIB_PM_TW_CFG0_REG = pmTwCfg0State; + CY_LIB_PM_TW_CFG2_REG = pmTwCfg2State; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyPLL_OUT_Stop +****************************************************************************//** +* +* Disables the PLL. +* +*******************************************************************************/ +void CyPLL_OUT_Stop(void) +{ + CY_CLK_PLL_CFG0_REG &= ((uint8)(~CY_CLK_PLL_ENABLE)); +} + + +/******************************************************************************* +* Function Name: CyPLL_OUT_SetPQ +****************************************************************************//** +* +* Sets the P and Q dividers and the charge pump current. +* The Frequency Out will be P/Q * Frequency In. +* The PLL must be disabled before calling this function. +* +* \param uint8 pDiv: +* Valid range [8 - 255]. +* +* \param uint8 qDiv: +* Valid range [1 - 16]. Input Frequency / Q must be in range of 1 to 3 MHz. + +* \param uint8 current: +* Valid range [1 - 7]. Charge pump current in uA. Refer to the device TRM and +* datasheet for more information. +* +* \sideeffect +* If this function execution results in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) +{ + /* Halt CPU in debug mode if PLL is enabled */ + CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE)); + + if((pDiv >= CY_CLK_PLL_MIN_P_VALUE ) && + (qDiv <= CY_CLK_PLL_MAX_Q_VALUE ) && (qDiv >= CY_CLK_PLL_MIN_Q_VALUE ) && + (current >= CY_CLK_PLL_MIN_CUR_VALUE) && (current <= CY_CLK_PLL_MAX_CUR_VALUE)) + { + /* Set new values */ + CY_CLK_PLL_P_REG = pDiv; + CY_CLK_PLL_Q_REG = ((uint8)(qDiv - 1u)); + CY_CLK_PLL_CFG1_REG = (CY_CLK_PLL_CFG1_REG & CY_CLK_PLL_CURRENT_MASK) | + ((uint8)(((uint8)(current - 1u)) << CY_CLK_PLL_CURRENT_POSITION)); + } + else + { + /*********************************************************************** + * Halt CPU in debug mode if: + * - P divider is less than required + * - Q divider is out of range + * - pump current is out of range + ***********************************************************************/ + CYASSERT(0u != 0u); + } + +} + + +/******************************************************************************* +* Function Name: CyPLL_OUT_SetSource +****************************************************************************//** +* +* Sets the input clock source to the PLL. The PLL must be disabled before +* calling this function. +* +* \param source: One of the three available PLL clock sources +* \param CY_PLL_SOURCE_IMO : IMO +* \param CY_PLL_SOURCE_XTAL : MHz Crystal +* \param CY_PLL_SOURCE_DSI : DSI +* +* \sideeffect +* If this function execution results in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the3 Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyPLL_OUT_SetSource(uint8 source) +{ + /* Halt CPU in debug mode if PLL is enabled */ + CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE)); + + switch(source) + { + case CY_PLL_SOURCE_IMO: + case CY_PLL_SOURCE_XTAL: + case CY_PLL_SOURCE_DSI: + CY_LIB_CLKDIST_CR_REG = ((CY_LIB_CLKDIST_CR_REG & CY_LIB_CLKDIST_CR_PLL_SCR_MASK) | source); + break; + + default: + CYASSERT(0u != 0u); + break; + } +} + + +/******************************************************************************* +* Function Name: CyIMO_Start +****************************************************************************//** +* +* Enables the IMO. Optionally waits at least 6 us for it to settle. +* +* \param uint8 wait: +* \param 0: Return immediately after configuration +* \param 1: Wait for at least 6 us for the IMO to settle. +* +* \sideeffect +* If wait is enabled: This function uses the Fast Time Wheel to time the wait. +* Any other use of the Fast Time Wheel will be stopped during the period of +* this function and then restored. This function also uses the 100 KHz ILO. +* If not enabled, this function will enable the 100 KHz ILO for the period of +* this function. +* +* No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or +* Once Per Second interrupt may be made by interrupt routines during the period +* of this function execution. The current operation of the ILO, Central Time +* Wheel and Once Per Second interrupt are maintained during the operation of +* this function provided the reading of the Power Manager Interrupt Status +* Register is only done using the CyPmReadStatus() function. +* +*******************************************************************************/ +void CyIMO_Start(uint8 wait) +{ + uint8 pmFtwCfg2Reg; + uint8 pmFtwCfg0Reg; + uint8 ilo100KhzEnable; + + + CY_LIB_PM_ACT_CFG0_REG |= CY_LIB_PM_ACT_CFG0_IMO_EN; + CY_LIB_PM_STBY_CFG0_REG |= CY_LIB_PM_STBY_CFG0_IMO_EN; + + if(0u != wait) + { + /* Need to turn on 100KHz ILO if it happens to not already be running.*/ + ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; + pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG; + pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG; + + CyPmFtwSetInterval(CY_LIB_CLK_IMO_FTW_TIMEOUT); + + while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) + { + /* Wait for interrupt status */ + } + + if(0u == ilo100KhzEnable) + { + CyILO_Stop100K(); + } + + CY_LIB_PM_TW_CFG0_REG = pmFtwCfg0Reg; + CY_LIB_PM_TW_CFG2_REG = pmFtwCfg2Reg; + } +} + + +/******************************************************************************* +* Function Name: CyIMO_Stop +****************************************************************************//** +* +* Disables the IMO. +* +*******************************************************************************/ +void CyIMO_Stop(void) +{ + CY_LIB_PM_ACT_CFG0_REG &= ((uint8) (~CY_LIB_PM_ACT_CFG0_IMO_EN)); + CY_LIB_PM_STBY_CFG0_REG &= ((uint8) (~CY_LIB_PM_STBY_CFG0_IMO_EN)); +} + + +/******************************************************************************* +* Function Name: CyUSB_PowerOnCheck +****************************************************************************//** +* +* Returns the USB power status value. A private function to cy_boot. +* +* \return +* uint8: one if the USB is enabled, 0 if not enabled. +* +*******************************************************************************/ +static uint8 CyUSB_PowerOnCheck(void) +{ + uint8 poweredOn = 0u; + + /* Check whether device is in Active or AltActive and if USB is powered on */ + if((((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ACTIVE ) && + (0u != (CY_LIB_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED ))) || + (((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) && + (0u != (CY_LIB_PM_STBY_CFG5_REG & CY_ALT_ACT_USB_ENABLED)))) + { + poweredOn = 1u; + } + + return (poweredOn); +} + + +/******************************************************************************* +* Function Name: CyIMO_SetTrimValue +****************************************************************************//** +* +* Sets the IMO factory trim values. +* +* uint8 freq - frequency for which trims must be set +* +*******************************************************************************/ +static void CyIMO_SetTrimValue(uint8 freq) +{ + uint8 usbPowerOn = CyUSB_PowerOnCheck(); + + /* If USB is powered */ + if(usbPowerOn == 1u) + { + /* Unlock USB write */ + CY_LIB_USB_CR1_REG &= ((uint8)(~CY_LIB_USB_CLK_EN)); + } + switch(freq) + { + case CY_IMO_FREQ_3MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_3MHZ_PTR); + break; + + case CY_IMO_FREQ_6MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_6MHZ_PTR); + break; + + case CY_IMO_FREQ_12MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_12MHZ_PTR); + break; + + case CY_IMO_FREQ_24MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_24MHZ_PTR); + break; + + case CY_IMO_FREQ_48MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_TR1_PTR); + break; + + case CY_IMO_FREQ_62MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_67MHZ_PTR); + break; + +#if(CY_PSOC5) + case CY_IMO_FREQ_74MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_80MHZ_PTR); + break; +#endif /* (CY_PSOC5) */ + + case CY_IMO_FREQ_USB: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_USB_PTR); + + /* If USB is powered */ + if(usbPowerOn == 1u) + { + /* Lock USB Oscillator */ + CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN; + } + break; + + default: + CYASSERT(0u != 0u); + break; + } + +} + + +/******************************************************************************* +* Function Name: CyIMO_SetFreq +****************************************************************************//** +* +* Sets the frequency of the IMO. Changes may be made while the IMO is running. +* +* \param freq: Frequency of IMO operation +* CY_IMO_FREQ_3MHZ to set 3 MHz +* CY_IMO_FREQ_6MHZ to set 6 MHz +* CY_IMO_FREQ_12MHZ to set 12 MHz +* CY_IMO_FREQ_24MHZ to set 24 MHz +* CY_IMO_FREQ_48MHZ to set 48 MHz +* CY_IMO_FREQ_62MHZ to set 62.6 MHz +* CY_IMO_FREQ_74MHZ to set 74.7 MHz (not applicable for PSoC 3) +* CY_IMO_FREQ_USB to set 24 MHz (Trimmed for USB operation) +* +* \sideeffect +* If this function execution results in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. +* +* When the USB setting is chosen, the USB clock locking circuit is enabled. +* Otherwise this circuit is disabled. The USB block must be powered before +* selecting the USB setting. +* +*******************************************************************************/ +void CyIMO_SetFreq(uint8 freq) +{ + uint8 currentFreq; + uint8 nextFreq; + + /*************************************************************************** + * If the IMO frequency is changed,the Trim values must also be set + * accordingly.This requires reading the current frequency. If the new + * frequency is faster, then set a new trim and then change the frequency, + * otherwise change the frequency and then set new trim values. + ***************************************************************************/ + + currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK)); + + /* Check if requested frequency is USB. */ + nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq; + + switch (currentFreq) + { + case 0u: + currentFreq = CY_IMO_FREQ_12MHZ; + break; + + case 1u: + currentFreq = CY_IMO_FREQ_6MHZ; + break; + + case 2u: + currentFreq = CY_IMO_FREQ_24MHZ; + break; + + case 3u: + currentFreq = CY_IMO_FREQ_3MHZ; + break; + + case 4u: + currentFreq = CY_IMO_FREQ_48MHZ; + break; + + case 5u: + currentFreq = CY_IMO_FREQ_62MHZ; + break; + +#if(CY_PSOC5) + case 6u: + currentFreq = CY_IMO_FREQ_74MHZ; + break; +#endif /* (CY_PSOC5) */ + + default: + CYASSERT(0u != 0u); + break; + } + + if (nextFreq >= currentFreq) + { + /* Set new trim first */ + CyIMO_SetTrimValue(freq); + } + + /* Set usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */ + switch(freq) + { + case CY_IMO_FREQ_3MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_3MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_6MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_6MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_12MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_12MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_24MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_24MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_48MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_48MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_62MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_62MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + +#if(CY_PSOC5) + case CY_IMO_FREQ_74MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_74MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; +#endif /* (CY_PSOC5) */ + + case CY_IMO_FREQ_USB: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_24MHZ_VALUE) | CY_LIB_IMO_USBCLK_ON_SET; + break; + + default: + CYASSERT(0u != 0u); + break; + } + + /* Tu rn onIMO Doubler, if switching to CY_IMO_FREQ_USB */ + if (freq == CY_IMO_FREQ_USB) + { + CyIMO_EnableDoubler(); + } + else + { + CyIMO_DisableDoubler(); + } + + if (nextFreq < currentFreq) + { + /* Set the trim after setting frequency */ + CyIMO_SetTrimValue(freq); + } +} + + +/******************************************************************************* +* Function Name: CyIMO_SetSource +****************************************************************************//** +* +* Sets the source of the clock output from the IMO block. +* +* The output from the IMO is by default the IMO itself. Optionally the MHz +* Crystal or DSI input can be the source of the IMO output instead. +* +* \param source: CY_IMO_SOURCE_DSI to set the DSI as source. +* CY_IMO_SOURCE_XTAL to set the MHz as source. +* CY_IMO_SOURCE_IMO to set the IMO itself. +* +* \sideeffect +* If this function execution resulted in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyIMO_SetSource(uint8 source) +{ + switch(source) + { + case CY_IMO_SOURCE_DSI: + CY_LIB_CLKDIST_CR_REG &= ((uint8)(~CY_LIB_CLKDIST_CR_IMO2X)); + CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO; + break; + + case CY_IMO_SOURCE_XTAL: + CY_LIB_CLKDIST_CR_REG |= CY_LIB_CLKDIST_CR_IMO2X; + CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO; + break; + + case CY_IMO_SOURCE_IMO: + CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_IMO)); + break; + + default: + /* Incorrect source value */ + CYASSERT(0u != 0u); + break; + } +} + + +/******************************************************************************* +* Function Name: CyIMO_EnableDoubler +****************************************************************************//** +* +* Enables the IMO doubler. The 2x frequency clock is used to convert a 24 MHz +* input to a 48 MHz output for use by the USB block. +* +*******************************************************************************/ +void CyIMO_EnableDoubler(void) +{ + /* Set FASTCLK_IMO_CR_PTR regigster's 4th bit */ + CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER; +} + + +/******************************************************************************* +* Function Name: CyIMO_DisableDoubler +****************************************************************************//** +* +* Disables the IMO doubler. +* +*******************************************************************************/ +void CyIMO_DisableDoubler(void) +{ + CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_DOUBLER)); +} + + +/******************************************************************************* +* Function Name: CyMasterClk_SetSource +****************************************************************************//** +* +* Sets the source of the master clock. +* +* \param source: One of the four available Master clock sources. +* CY_MASTER_SOURCE_IMO +* CY_MASTER_SOURCE_PLL +* CY_MASTER_SOURCE_XTAL +* CY_MASTER_SOURCE_DSI +* +* \sideeffect +* The current source and the new source must both be running and stable before +* calling this function. +* +* If this function execution resulted in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyMasterClk_SetSource(uint8 source) +{ + CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & MASTER_CLK_SRC_CLEAR) | + (source & ((uint8)(~MASTER_CLK_SRC_CLEAR))); +} + + +/******************************************************************************* +* Function Name: CyMasterClk_SetDivider +****************************************************************************//** +* +* Sets the divider value used to generate Master Clock. +* +* \param uint8 divider: +* The valid range is [0-255]. The clock will be divided by this value + 1. +* For example to divide this parameter by two should be set to 1. +* +* \sideeffect +* If this function execution resulted in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. +* +* When changing the Master or Bus clock divider value from div-by-n to div-by-1 +* the first clock cycle output after the div-by-1 can be up to 4 ns shorter +* than the final/expected div-by-1 period. +* +*******************************************************************************/ +void CyMasterClk_SetDivider(uint8 divider) +{ + CY_LIB_CLKDIST_MSTR0_REG = divider; +} + + +/******************************************************************************* +* Function Name: CyBusClk_Internal_SetDivider +****************************************************************************//** +* +* The function used by CyBusClk_SetDivider(). For internal use only. +* +* \param divider: Valid range [0-65535]. +* The clock will be divided by this value + 1. +* For example, to divide this parameter by two should be set to 1. +* +*******************************************************************************/ +static void CyBusClk_Internal_SetDivider(uint16 divider) +{ + /* Mask bits to enable shadow loads */ + CY_LIB_CLKDIST_AMASK_REG &= CY_LIB_CLKDIST_AMASK_MASK; + CY_LIB_CLKDIST_DMASK_REG = CY_LIB_CLKDIST_DMASK_MASK; + + /* Enable mask bits to enable shadow loads */ + CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK; + + /* Update Shadow Divider Value Register with new divider */ + CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider); + CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider); + + + /*************************************************************************** + * Copy shadow value defined in Shadow Divider Value Register + * (CY_LIB_CLKDIST_WRK_LSB_REG and CY_LIB_CLKDIST_WRK_MSB_REG) to all + * dividers selected in Analog and Digital Clock Mask Registers + * (CY_LIB_CLKDIST_AMASK_REG and CY_LIB_CLKDIST_DMASK_REG). + ***************************************************************************/ + CY_LIB_CLKDIST_LD_REG |= CY_LIB_CLKDIST_LD_LOAD; +} + + +/******************************************************************************* +* Function Name: CyBusClk_SetDivider +****************************************************************************//** +* +* Sets the divider value used to generate the Bus Clock. +* +* \param divider: Valid range [0-65535]. The clock will be divided by this value + 1. +* For example, to divide this parameter by two should be set to 1. +* +* \sideeffect +* If this function execution resulted in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyBusClk_SetDivider(uint16 divider) +{ + uint8 masterClkDiv; + uint16 busClkDiv; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Work around to set bus clock divider value */ + busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u); + busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG; + + if ((divider == 0u) || (busClkDiv == 0u)) + { + /* Save away master clock divider value */ + masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG; + + if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV) + { + /* Set master clock divider to 7 */ + CyMasterClk_SetDivider(CY_LIB_CLKDIST_MASTERCLK_DIV); + } + + if (divider == 0u) + { + /* Set SSS bit and divider register desired value */ + CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS; + CyBusClk_Internal_SetDivider(divider); + } + else + { + CyBusClk_Internal_SetDivider(divider); + CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS)); + } + + /* Restore master clock */ + CyMasterClk_SetDivider(masterClkDiv); + } + else + { + CyBusClk_Internal_SetDivider(divider); + } + + CyExitCriticalSection(interruptState); +} + + +#if(CY_PSOC3) + + /******************************************************************************* + * Function Name: CyCpuClk_SetDivider + ****************************************************************************//** + * + * Sets the divider value used to generate the CPU Clock. Only applicable for + * PSoC 3 parts. + * + * \param divider: Valid range [0-15]. The clock will be divided by this value + 1. + * For example, to divide this parameter by two should be set to 1. + * + * \sideeffect + * If this function execution resulted in the CPU clock frequency increasing, + * then the number of clock cycles the cache will wait before it samples data + * coming back from the Flash must be adjusted by calling + * CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally + * called if the CPU clock frequency is lowered in order to improve the CPU + * performance. See CyFlash_SetWaitCycles() description for more information. + * + *******************************************************************************/ + void CyCpuClk_SetDivider(uint8 divider) + { + CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & CY_LIB_CLKDIST_MSTR1_DIV_MASK) | + ((uint8)(divider << CY_LIB_CLKDIST_DIV_POSITION)); + } + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Function Name: CyUsbClk_SetSource +****************************************************************************//** +* +* Sets the source of the USB clock. +* +* \param source: One of the four available USB clock sources +* CY_LIB_USB_CLK_IMO2X - IMO 2x +* CY_LIB_USB_CLK_IMO - IMO +* CY_LIB_USB_CLK_PLL - PLL +* CY_LIB_USB_CLK_DSI - DSI +* +*******************************************************************************/ +void CyUsbClk_SetSource(uint8 source) +{ + CY_LIB_CLKDIST_UCFG_REG = (CY_LIB_CLKDIST_UCFG_REG & ((uint8)(~CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK))) | + (CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK & source); +} + + +/******************************************************************************* +* Function Name: CyILO_Start1K +****************************************************************************//** +* +* Enables the ILO 1 KHz oscillator. +* +* Note The ILO 1 KHz oscillator is always enabled by default, regardless of the +* selection in the Clock Editor. Therefore, this API is only needed if the +* oscillator was turned off manually. +* +*******************************************************************************/ +void CyILO_Start1K(void) +{ + /* Set bit 1 of ILO RS */ + CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ; +} + + +/******************************************************************************* +* Function Name: CyILO_Stop1K +****************************************************************************//** +* +* Disables the ILO 1 KHz oscillator. +* +* Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low +* power mode APIs are expected to be used. For more information, refer to the +* Power Management section of this document. +* +* \sideeffect +* PSoC5: Stopping the ILO 1 kHz could break the active WDT functionality. +* +*******************************************************************************/ +void CyILO_Stop1K(void) +{ + /* Clear bit 1 of ILO RS */ + CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ)); +} + + +/******************************************************************************* +* Function Name: CyILO_Start100K +****************************************************************************//** +* +* Enables the ILO 100 KHz oscillator. +* +*******************************************************************************/ +void CyILO_Start100K(void) +{ + CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; +} + + +/******************************************************************************* +* Function Name: CyILO_Stop100K +****************************************************************************//** +* +* Disables the ILO 100 KHz oscillator. +* +*******************************************************************************/ +void CyILO_Stop100K(void) +{ + CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ)); +} + + +/******************************************************************************* +* Function Name: CyILO_Enable33K +****************************************************************************//** +* +* Enables the ILO 33 KHz divider. +* +* Note that the 33 KHz clock is generated from the 100 KHz oscillator, +* so it must also be running in order to generate the 33 KHz output. +* +*******************************************************************************/ +void CyILO_Enable33K(void) +{ + /* Set bit 5 of ILO RS */ + CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ; +} + + +/******************************************************************************* +* Function Name: CyILO_Disable33K +****************************************************************************//** +* +* Disables the ILO 33 KHz divider. +* +* Note that the 33 KHz clock is generated from the 100 KHz oscillator, but this +* API does not disable the 100 KHz clock. +* +*******************************************************************************/ +void CyILO_Disable33K(void) +{ + CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ)); +} + + +/******************************************************************************* +* Function Name: CyILO_SetSource +****************************************************************************//** +* +* Sets the source of the clock output from the ILO block. +* +* \param source: One of the three available ILO output sources +* Value Define Source +* 0 CY_ILO_SOURCE_100K ILO 100 KHz +* 1 CY_ILO_SOURCE_33K ILO 33 KHz +* 2 CY_ILO_SOURCE_1K ILO 1 KHz +* +*******************************************************************************/ +void CyILO_SetSource(uint8 source) +{ + CY_LIB_CLKDIST_CR_REG = (CY_LIB_CLKDIST_CR_REG & CY_ILO_SOURCE_BITS_CLEAR) | + (((uint8) (source << 2u)) & ((uint8)(~CY_ILO_SOURCE_BITS_CLEAR))); +} + + +/******************************************************************************* +* Function Name: CyILO_SetPowerMode +****************************************************************************//** +* +* Sets the power mode used by the ILO during power down. Allows for lower power +* down power usage resulting in a slower startup time. +* +* \param mode +* CY_ILO_FAST_START - Faster start-up, internal bias left on when powered down +* CY_ILO_SLOW_START - Slower start-up, internal bias off when powered down +* +* \return Prevous power mode state. +* +*******************************************************************************/ +uint8 CyILO_SetPowerMode(uint8 mode) +{ + uint8 state; + + /* Get current state. */ + state = CY_LIB_SLOWCLK_ILO_CR0_REG; + + /* Set the oscillator power mode. */ + if(mode != CY_ILO_FAST_START) + { + CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE); + } + else + { + CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE))); + } + + /* Return old mode. */ + return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION); +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_Start +****************************************************************************//** +* +* Enables the 32 KHz Crystal Oscillator. +* +*******************************************************************************/ +void CyXTAL_32KHZ_Start(void) +{ + volatile uint16 i; + + CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_STARTUP; + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_DEFAULT; + + #if(CY_PSOC3) + CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN; + #endif /* (CY_PSOC3) */ + + /* Enable operation of 32K Crystal Oscillator */ + CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN; + + for (i = 1000u; i > 0u; i--) + { + if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT)) + { + /* Ready - switch to high power mode */ + (void) CyXTAL_32KHZ_SetPowerMode(0u); + + break; + } + CyDelayUs(1u); + } +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_Stop +****************************************************************************//** +* +* Disables the 32KHz Crystal Oscillator. +* +*******************************************************************************/ +void CyXTAL_32KHZ_Stop(void) +{ + CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_POWERDOWN; + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_DEFAULT; + CY_CLK_XTAL32_CR_REG &= ((uint8)(~(CY_CLK_XTAL32_CR_EN | CY_CLK_XTAL32_CR_LPM))); + + #if(CY_PSOC3) + CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_PDBEN)); + #endif /* (CY_PSOC3) */ +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_ReadStatus +****************************************************************************//** +* +* Returns status of the 32 KHz oscillator. +* +* \return +* Value Define Source +* 20 CY_XTAL32K_ANA_STAT Analog measurement +* 1: Stable +* 0: Not stable +* +*******************************************************************************/ +uint8 CyXTAL_32KHZ_ReadStatus(void) +{ + return(CY_CLK_XTAL32_CR_REG & CY_XTAL32K_ANA_STAT); +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_SetPowerMode +****************************************************************************//** +* +* Sets the power mode for the 32 KHz oscillator used during the sleep mode. +* Allows for lower power during sleep when there are fewer sources of noise. +* During the active mode the oscillator is always run in the high power mode. +* +* uint8 mode +* \param 0: High power mode +* \param 1: Low power mode during sleep +* +* \return +* Previous power mode. +* +*******************************************************************************/ +uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) +{ + uint8 state = (0u != (CY_CLK_XTAL32_CR_REG & CY_CLK_XTAL32_CR_LPM)) ? 1u : 0u; + + CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; + + if(1u == mode) + { + /* Low power mode during Sleep */ + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_LOW_POWER; + CyDelayUs(10u); + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_LOWPOWER; + CyDelayUs(20u); + CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_LPM; + } + else + { + /* High power mode */ + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_HIGH_POWER; + CyDelayUs(10u); + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_DEFAULT; + CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_LPM)); + } + + return(state); +} + + +/******************************************************************************* +* Function Name: CyXTAL_Start +****************************************************************************//** +* +* Enables the megahertz crystal. +* +* PSoC 3: +* Waits until the XERR bit is low (no error) for a millisecond or until the +* number of milliseconds specified by the wait parameter has expired. +* +* \param wait: Valid range [0-255]. +* This is the timeout value in milliseconds. +* The appropriate value is crystal specific. +* +* \return +* CYRET_SUCCESS - Completed successfully +* CYRET_TIMEOUT - Timeout occurred without detecting a low value on XERR. +* +* Side Effects and Restrictions: +* If wait is enabled (non-zero wait). Uses the Fast Timewheel to time the wait. +* Any other use of the Fast Timewheel (FTW) will be stopped during the period +* of this function and then restored. +* +* Uses the 100KHz ILO. If not enabled, this function will enable the 100KHz +* ILO for the period of this function. No changes to the setup of the ILO, +* Fast Timewheel, Central Timewheel or Once Per Second interrupt may be made +* by interrupt routines during the period of this function. +* +* The current operation of the ILO, Central Timewheel and Once Per Second +* interrupt are maintained during the operation of this function provided the +* reading of the Power Manager Interrupt Status Register is only done using the +* CyPmReadStatus() function. +* +*******************************************************************************/ +cystatus CyXTAL_Start(uint8 wait) +{ + cystatus status = CYRET_SUCCESS; + volatile uint8 timeout = wait; + volatile uint8 count; + uint8 iloEnableState; + uint8 pmTwCfg0Tmp; + uint8 pmTwCfg2Tmp; + + + /* Enables MHz crystal oscillator circuit */ + CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE; + + + if(wait > 0u) + { + /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */ + iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG; + pmTwCfg0Tmp = CY_LIB_PM_TW_CFG0_REG; + pmTwCfg2Tmp = CY_LIB_PM_TW_CFG2_REG; + + /* Set 250 us interval */ + CyPmFtwSetInterval(CY_CLK_XMHZ_FTW_INTERVAL); + status = CYRET_TIMEOUT; + + + for( ; timeout > 0u; timeout--) + { + /* Read XERR bit to clear it */ + (void) CY_CLK_XMHZ_CSR_REG; + + /* Wait for 1 millisecond - 4 x 250 us */ + for(count = 4u; count > 0u; count--) + { + while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) + { + /* Wait for FTW interrupt event */ + } + } + + + /******************************************************************* + * High output indicates an oscillator failure. + * Only can be used after a start-up interval (1 ms) is completed. + *******************************************************************/ + if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) + { + status = CYRET_SUCCESS; + break; + } + } + + + /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */ + if(0u == (iloEnableState & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ)) + { + CyILO_Stop100K(); + } + CY_LIB_PM_TW_CFG0_REG = pmTwCfg0Tmp; + CY_LIB_PM_TW_CFG2_REG = pmTwCfg2Tmp; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyXTAL_Stop +****************************************************************************//** +* +* Disables the megahertz crystal oscillator. +* +*******************************************************************************/ +void CyXTAL_Stop(void) +{ + /* Disable oscillator. */ + FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_EnableErrStatus +****************************************************************************//** +* +* Enables the generation of the XERR status bit for the megahertz crystal. +* This function is not available for PSoC5. +* +*******************************************************************************/ +void CyXTAL_EnableErrStatus(void) +{ + /* If oscillator has insufficient amplitude, XERR bit will be high. */ + CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XFB)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_DisableErrStatus +****************************************************************************//** +* +* Disables the generation of the XERR status bit for the megahertz crystal. +* This function is not available for PSoC5. +* +*******************************************************************************/ +void CyXTAL_DisableErrStatus(void) +{ + /* If oscillator has insufficient amplitude, XERR bit will be high. */ + CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XFB; +} + + +/******************************************************************************* +* Function Name: CyXTAL_ReadStatus +****************************************************************************//** +* +* Reads the XERR status bit for the megahertz crystal. This status bit is a +* sticky, clear on read. This function is not available for PSoC5. +* +* \return +* Status +* 0: No error +* 1: Error +* +*******************************************************************************/ +uint8 CyXTAL_ReadStatus(void) +{ + /*************************************************************************** + * High output indicates an oscillator failure. Only use this after a start-up + * interval is completed. This can be used for the status and failure recovery. + ***************************************************************************/ + return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u); +} + + +/******************************************************************************* +* Function Name: CyXTAL_EnableFaultRecovery +****************************************************************************//** +* +* Enables the fault recovery circuit which will switch to the IMO in the case +* of a fault in the megahertz crystal circuit. The crystal must be up and +* running with the XERR bit at 0, before calling this function to prevent +* an immediate fault switchover. This function is not available for PSoC5. +* +*******************************************************************************/ +void CyXTAL_EnableFaultRecovery(void) +{ + CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XPROT; +} + + +/******************************************************************************* +* Function Name: CyXTAL_DisableFaultRecovery +****************************************************************************//** +* +* Disables the fault recovery circuit which will switch to the IMO in the case +* of a fault in the megahertz crystal circuit. This function is not available +* for PSoC5. +* +*******************************************************************************/ +void CyXTAL_DisableFaultRecovery(void) +{ + CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XPROT)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_SetStartup +****************************************************************************//** +* +* Sets the startup settings for the crystal. The logic model outputs a +* frequency (setting + 4) MHz when enabled. +* +* This is artificial as the actual frequency is determined by an attached +* external crystal. +* +* \param setting: Valid range [0-31]. +* The value is dependent on the frequency and quality of the crystal being +* used. Refer to the device TRM and datasheet for more information. +* +*******************************************************************************/ +void CyXTAL_SetStartup(uint8 setting) +{ + CY_CLK_XMHZ_CFG0_REG = (CY_CLK_XMHZ_CFG0_REG & ((uint8)(~CY_CLK_XMHZ_CFG0_XCFG_MASK))) | + (setting & CY_CLK_XMHZ_CFG0_XCFG_MASK); +} + + + +/******************************************************************************* +* Function Name: CyXTAL_SetFbVoltage +****************************************************************************//** +* +* Sets the feedback reference voltage to use for the crystal circuit. +* This function is only available for PSoC3 and PSoC 5LP. +* +* \param setting: Valid range [0-15]. +* Refer to the device TRM and datasheet for more information. +* +*******************************************************************************/ +void CyXTAL_SetFbVoltage(uint8 setting) +{ + CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_FB_MASK))) | + (setting & CY_CLK_XMHZ_CFG1_VREF_FB_MASK)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_SetWdVoltage +****************************************************************************//** +* +* Sets the reference voltage used by the watchdog to detect a failure in the +* crystal circuit. This function is only available for PSoC3 and PSoC 5LP. +* +* \param setting: Valid range [0-7]. +* Refer to the device TRM and datasheet for more information. +* +*******************************************************************************/ +void CyXTAL_SetWdVoltage(uint8 setting) +{ + CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_WD_MASK))) | + (((uint8)(setting << 4u)) & CY_CLK_XMHZ_CFG1_VREF_WD_MASK)); +} + + +/******************************************************************************* +* Function Name: CyHalt +****************************************************************************//** +* +* Halts the CPU. +* +* \param uint8 reason: Value to be used during debugging. +* +*******************************************************************************/ +void CyHalt(uint8 reason) CYREENTRANT +{ + if(0u != reason) + { + /* To remove unreferenced local variable warning */ + } + + #if defined (__ARMCC_VERSION) + __breakpoint(0x0); + #elif defined(__GNUC__) || defined (__ICCARM__) + __asm(" bkpt 1"); + #elif defined(__C51__) + CYDEV_HALT_CPU; + #endif /* (__ARMCC_VERSION) */ +} + + +/******************************************************************************* +* Function Name: CySoftwareReset +****************************************************************************//** +* +* Forces a device software reset. +* +*******************************************************************************/ +void CySoftwareReset(void) +{ + CY_LIB_RESET_CR2_REG |= CY_LIB_RESET_CR2_RESET; +} + + +/******************************************************************************* +* Function Name: CyDelay +****************************************************************************//** +* +* Blocks for milliseconds. +* +* Note: +* CyDelay has been implemented with the instruction cache assumed enabled. When +* the instruction cache is disabled on PSoC5, CyDelay will be two times larger. +* For example, with instruction cache disabled CyDelay(100) would result in +* about 200 ms delay instead of 100 ms. +* +* \param milliseconds: number of milliseconds to delay. +* +*******************************************************************************/ +void CyDelay(uint32 milliseconds) CYREENTRANT +{ + while (milliseconds > 32768u) + { + /*********************************************************************** + * This loop prevents overflow.At 100MHz, milliseconds * delay_freq_khz + * overflows at about 42 seconds. + ***********************************************************************/ + CyDelayCycles(cydelay_32k_ms); + milliseconds = ((uint32)(milliseconds - 32768u)); + } + + CyDelayCycles(milliseconds * cydelay_freq_khz); +} + + +#if(!CY_PSOC3) + + /* For PSoC3 devices function is defined in CyBootAsmKeil.a51 file */ + + /******************************************************************************* + * Function Name: CyDelayUs + ****************************************************************************//** + * + * Blocks for microseconds. + * + * Note: + * CyDelay has been implemented with the instruction cache assumed enabled. + * When instruction cache is disabled on PSoC5, CyDelayUs will be two times + * larger. Ex: With instruction cache disabled CyDelayUs(100) would result + * in about 200us delay instead of 100us. + * + * \param uint16 microseconds: number of microseconds to delay. + * + * \sideeffect + * CyDelayUS has been implemented with the instruction cache assumed enabled. + * When the instruction cache is disabled on PSoC 5, CyDelayUs will be two times + * larger. For example, with the instruction cache disabled CyDelayUs(100) would + * result in about 200 us delay instead of 100 us. + * + * If the bus clock frequency is a small non-integer number, the actual delay + * can be up to twice as long as the nominal value. The actual delay cannot be + * shorter than the nominal one. + *******************************************************************************/ + void CyDelayUs(uint16 microseconds) CYREENTRANT + { + CyDelayCycles((uint32)microseconds * cydelay_freq_mhz); + } + +#endif /* (!CY_PSOC3) */ + + +/******************************************************************************* +* Function Name: CyDelayFreq +****************************************************************************//** +* +* Sets the clock frequency for CyDelay. +* +* \param freq: The frequency of the bus clock in Hertz. +* +*******************************************************************************/ +void CyDelayFreq(uint32 freq) CYREENTRANT +{ + if (freq != 0u) + { + cydelay_freq_hz = freq; + } + else + { + cydelay_freq_hz = BCLK__BUS_CLK__HZ; + } + + cydelay_freq_mhz = (uint8)((cydelay_freq_hz + 999999u) / 1000000u); + cydelay_freq_khz = (cydelay_freq_hz + 999u) / 1000u; + cydelay_32k_ms = 32768u * cydelay_freq_khz; +} + + +/******************************************************************************* +* Function Name: CyWdtStart +****************************************************************************//** +* +* Enables the watchdog timer. +* +* The timer is configured for the specified count interval, the central +* timewheel is cleared, the setting for the low power mode is configured and +* the watchdog timer is enabled. +* +* Once enabled the watchdog cannot be disabled. The watchdog counts each time +* the Central Time Wheel (CTW) reaches the period specified. The watchdog must +* be cleared using the CyWdtClear() function before three ticks of the watchdog +* timer occur. The CTW is free running, so this will occur after between 2 and +* 3 timer periods elapse. +* +* PSoC5: The watchdog timer should not be used during sleep modes. Since the +* WDT cannot be disabled after it is enabled, the WDT timeout period can be +* set to be greater than the sleep wakeup period, then feed the dog on each +* wakeup from Sleep. +* +* \param ticks: One of the four available timer periods. Once WDT enabled, the + interval cannot be changed. +* CYWDT_2_TICKS - 4 - 6 ms +* CYWDT_16_TICKS - 32 - 48 ms +* CYWDT_128_TICKS - 256 - 384 ms +* CYWDT_1024_TICKS - 2.048 - 3.072 s +* +* \param lpMode: Low power mode configuration. This parameter is ignored for PSoC 5. +* The WDT always acts as if CYWDT_LPMODE_NOCHANGE is passed. +* +* CYWDT_LPMODE_NOCHANGE - No Change +* CYWDT_LPMODE_MAXINTER - Switch to longest timer mode during low power +* mode +* CYWDT_LPMODE_DISABLED - Disable WDT during low power mode +* +* \sideeffect +* PSoC5: The ILO 1 KHz must be enabled for proper WDT operation. Stopping the +* ILO 1 kHz could break the active WDT functionality. +* +*******************************************************************************/ +void CyWdtStart(uint8 ticks, uint8 lpMode) +{ + /* Set WDT interval */ + CY_WDT_CFG_REG = (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_INTERVAL_MASK))) | (ticks & CY_WDT_CFG_INTERVAL_MASK); + + /* Reset CTW to ensure that first watchdog period is full */ + CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET; + CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET)); + + /* Setting low power mode */ + CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) | + (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK))); + + /* Enables watchdog reset */ + CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN; +} + + +/******************************************************************************* +* Function Name: CyWdtClear +****************************************************************************//** +* +* Clears (feeds) the watchdog timer. +* +*******************************************************************************/ +void CyWdtClear(void) +{ + CY_WDT_CR_REG = CY_WDT_CR_FEED; +} + + + +/******************************************************************************* +* Function Name: CyVdLvDigitEnable +****************************************************************************//** +* +* Sets the voltage trip level, enables the output of the digital low-voltage +* monitor, and optionally configures voltage monitor to reset device upon the +* low-voltage event instead of generating an interrupt. +* +* Note The associated interrupt enable/disable state is not changed by the +* function. The Interrupt component API should be used to register the +* interrupt service routine and to enable/disable associated interrupt. +* +* \param reset: Enables device reset on digital low-voltage event: +* Zero - Interrupt on digital low-voltage event +* Non-zero - Reset on digital low-voltage event +* +* \param threshold: Sets the trip point of the digital low-voltage monitoring circuit +* in steps of approximately 250 mV in range from 1.70 V (0x00) to 5.45 V +* (0x0F). For example, the trip point is set to 1.80 V when the threshold +* parameter value is 0x04. Refer to the device TRM for the exact trip voltage +* values. +* +* Side Effects and Restrictions: +* The voltage resets are momentary. When a voltage reset (analog/digital +* low-voltage and analog high-voltage) occurs, the RESET_CR1 and RESET_CR3 +* registers are restored to their default values. This means that the voltage +* monitor circuit is no longer enabled and the device exits reset. If the +* supply is below the trip level and firmware enables the voltage reset +* functionality, the device will reset again. This will continue as long as the +* supply is below the trip level or as long as the user enables the reset +* functionality of the voltage monitor functionality. +* +* When any voltage reset occurs, the RESET_SR0 and RESET_SR2 status registers +* are cleared. This means that analog low-voltage, digital low-voltage and +* analog high-voltage status bits are not persistent across any voltage reset. +* +*******************************************************************************/ +void CyVdLvDigitEnable(uint8 reset, uint8 threshold) +{ + uint32 intRegTmp; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Store interrupt enable state */ + intRegTmp = CY_INT_ENABLE_REG & CY_VD_INT_MASK; + + /* Disable VD interrupt (write 1) to protect against glitches */ + CY_INT_CLEAR_REG = CY_VD_INT_MASK; + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + + CY_VD_LVI_TRIP_REG = (threshold & CY_VD_LVI_TRIP_LVID_MASK) | + (CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK))); + CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN; + + /* Timeout to eliminate glitches on LVI/HVI when enabling (ID # 127412) */ + CyDelayUs(1u); + + (void) CyVdStickyStatus(CY_VD_LVID); + + if(0u != reset) + { + CY_VD_PRES_CONTROL_REG |= CY_VD_PRESD_EN; + } + else + { + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + } + + /* Clear pending interrupt */ + CY_INT_CLR_PEND_REG = CY_VD_INT_MASK; + + /* Restore interrupt enable state */ + CY_INT_ENABLE_REG = intRegTmp; + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyVdLvAnalogEnable +****************************************************************************//** +* +* Sets the voltage trip level, enables the output of the analog low-voltage +* monitor, and optionally configures voltage monitor to reset device upon the +* low-voltage event instead of generating an interrupt. +* +* Note The associated interrupt enable/disable state is not changed by the +* function. The Interrupt component API should be used to register the +* interrupt service routine and to enable/disable associated interrupt. +* +* \param reset: Enables device reset on analog low-voltage event: +* Zero - Interrupt on analog low-voltage event +* Non-zero - Reset on analog low-voltage event +* +* \param threshold: Sets the trip point of the analog low-voltage monitoring circuit +* in steps of approximately 250 mV in range from 1.70 V (0x00) to 5.45 V +* (0x0F). For example, the trip point is set to 1.80 V when value of the +* threshold parameter is 0x04. Please refer to the device TRM for the exact +* trip voltage values. +* +* Side Effects and Restrictions: +* The voltage resets are momentary. When a voltage reset (analog/digital +* low-voltage and analog high-voltage) occurs, the RESET_CR1 and RESET_CR3 +* registers are restored to their default values. This means that the voltage +* monitor circuit is no longer enabled and the device exits reset. If the +* supply is below the trip level and firmware enables the voltage reset +* functionality, the device will reset again. This will continue as long as +* the supply is below the trip level or as long as the user enables the reset +* functionality of the voltage monitor functionality. +* +* When any voltage reset occurs, the RESET_SR0 and RESET_SR2 status registers +* are cleared. This means that analog low-voltage, digital low-voltage and +* analog high-voltage status bits are not persistent across any voltage reset. +* +*******************************************************************************/ +void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) +{ + uint32 intRegTmp; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Store interrupt enable state */ + intRegTmp = CY_INT_ENABLE_REG & CY_VD_INT_MASK; + + /* Disable VD interrupt (write 1) to protect against glitches */ + CY_INT_CLEAR_REG = CY_VD_INT_MASK; + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + + CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu); + CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN; + + /* Timeout to eliminate glitches on LVI/HVI when enabling (ID # 127412) */ + CyDelayUs(1u); + + (void) CyVdStickyStatus(CY_VD_LVIA); + + if(0u != reset) + { + CY_VD_PRES_CONTROL_REG |= CY_VD_PRESA_EN; + } + else + { + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + } + + /* Clear pending interrupt */ + CY_INT_CLR_PEND_REG = CY_VD_INT_MASK; + + /* Restore interrupt enable state */ + CY_INT_ENABLE_REG = intRegTmp; + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyVdLvDigitDisable +****************************************************************************//** +* +* Disables the digital low-voltage monitor, turns off device reset upon the +* digital low-voltage event, and clears the associated persistent status bit. +* +* Note The associated interrupt enable/disable state is not changed by the +* function. The pending interrupt status is not cleared. The Interrupt +* component API should be used to manipulate with the associated interrupts. +* +*******************************************************************************/ +void CyVdLvDigitDisable(void) +{ + CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVID_EN)); + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + (void) CyVdStickyStatus(CY_VD_LVID); + + while(0u != (CyVdStickyStatus(CY_VD_LVID) & CY_VD_LVID)) + { + + } +} + + +/******************************************************************************* +* Function Name: CyVdLvAnalogDisable +****************************************************************************//** +* +* Disables the analog low-voltage monitor, turns off device reset upon the +* analog low-voltage event, and clears the associated persistent status bit. +* +* Note The associated interrupt enable/disable state is not changed by the +* function. The pending interrupt status is not cleared. The Interrupt +* component API should be used to manipulate with the associated interrupts. +* +*******************************************************************************/ +void CyVdLvAnalogDisable(void) +{ + CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVIA_EN)); + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + while(0u != (CyVdStickyStatus(CY_VD_LVIA) & CY_VD_LVIA)) + { + + } +} + + +/******************************************************************************* +* Function Name: CyVdHvAnalogEnable +****************************************************************************//** +* +* Enables the output of the analog high-voltage monitor and sets 5.75 V +* threshold detection for Vdda. +* +* Note The associated interrupt enable/disable state is not changed by the +* function. The Interrupt component API should be used to register the +* interrupt service routine and to enable/disable associated interrupt. +* +*******************************************************************************/ +void CyVdHvAnalogEnable(void) +{ + uint32 intRegTmp; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Store interrupt enable state */ + intRegTmp = CY_INT_ENABLE_REG & CY_VD_INT_MASK; + + /* Disable VD interrupt (write 1) to protect against glitches */ + CY_INT_CLEAR_REG = CY_VD_INT_MASK; + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + + CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_HVIA_EN; + + /* Timeout to eliminate glitches on the LVI/HVI when enabling (ID # 127412) */ + CyDelayUs(1u); + + (void) CyVdStickyStatus(CY_VD_HVIA); + + /* Clear pending interrupt */ + CY_INT_CLR_PEND_REG = CY_VD_INT_MASK; + + /* Restore interrupt enable state */ + CY_INT_ENABLE_REG = intRegTmp; + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyVdHvAnalogDisable +****************************************************************************//** +* +* Disables the analog high-voltage monitor and clears the associated persistent +* status bit. +* +* Note The associated interrupt enable/disable state is not changed by the +* function. The pending interrupt status is not cleared. The Interrupt +* component API should be used to manipulate with the associated interrupts. +* +*******************************************************************************/ +void CyVdHvAnalogDisable(void) +{ + CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_HVIA_EN)); + while(0u != (CyVdStickyStatus(CY_VD_HVIA) & CY_VD_HVIA)) + { + + } +} + + +/******************************************************************************* +* Function Name: CyVdStickyStatus +****************************************************************************//** +* +* Reads and clears the voltage detection status bits in the RESET_SR0 register. +* The bits are set to 1 by the voltage monitor circuit when the supply is +* outside the detector trip point. They stay set to 1 until they are read or +* a POR / LVI / PRES reset occurs. This function uses a shadow register, so +* only the bits passed in the parameter will be cleared in the shadow register. +* +* \param mask: Bits in the RESET_SR0 shadow register to clear and return. +* Define Definition +* CY_VD_LVID Persistent status of digital LVI. +* CY_VD_LVIA Persistent status of analog LVI. +* CY_VD_HVIA Persistent status of analog HVI. +* +* \return +* Status. Same enumerated bit values as used for the mask parameter. A zero is +* returned for bits not used in the mask parameter. +* +* Side Effects and Restrictions: +* When an LVI reset occurs, the RESET_SR0 status registers are cleared. This +* means that the voltage detection status bits are not persistent across an LVI +* reset and cannot be used to determine a reset source. +* +*******************************************************************************/ +uint8 CyVdStickyStatus(uint8 mask) +{ + static uint8 interruptStatus; + uint8 interruptState; + uint8 tmpStatus; + + interruptState = CyEnterCriticalSection(); + + interruptStatus |= CY_VD_PERSISTENT_STATUS_REG; + tmpStatus = interruptStatus & (uint8)(CY_VD_LVID | CY_VD_LVIA | CY_VD_HVIA); + interruptStatus &= ((uint8)(~mask)); + + CyExitCriticalSection(interruptState); + + return(tmpStatus); +} + + +/******************************************************************************* +* Function Name: CyVdRealTimeStatus +****************************************************************************//** +* +* Reads the real-time voltage detection status bits in the RESET_SR2 register. +* The bits are set to 1 by the voltage monitor circuit when the supply is +* outside the detector’s trip point, and set to 0 when the supply is inside the +* trip point. +* +* \return +* Status of the LVID, LVIA, and HVIA bits in the RESET_SR2 register. +* Define Definition +* CY_VD_LVID Real-time status of digital LVI. +* CY_VD_LVIA Real-time status of analog LVI. +* CY_VD_HVIA Real-time status of analog HVI. +* +* Side Effects and Restrictions: +* When an LVI reset occurs, the RESET_SR2 status registers are cleared. This +* means that the voltage detection status bits are not persistent across an LVI +* reset and cannot be used to determine a reset source. +* +*******************************************************************************/ +uint8 CyVdRealTimeStatus(void) +{ + uint8 interruptState; + uint8 vdFlagsState; + + interruptState = CyEnterCriticalSection(); + vdFlagsState = CY_VD_RT_STATUS_REG & (CY_VD_LVID | CY_VD_LVIA | CY_VD_HVIA); + CyExitCriticalSection(interruptState); + + return(vdFlagsState); +} + + +/******************************************************************************* +* Function Name: CyDisableInts +****************************************************************************//** +* +* Disables the interrupt enable for each interrupt. +* +* \return +* 32 bit mask of previously enabled interrupts. +* +*******************************************************************************/ +uint32 CyDisableInts(void) +{ + uint32 intState; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + #if(CY_PSOC3) + + /* Get the current interrupt state. */ + intState = ((uint32) CY_GET_REG8(CY_INT_CLR_EN0_PTR)); + intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN1_PTR)) << 8u)); + intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN2_PTR)) << 16u)); + intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN3_PTR)) << 24u)); + + + /* Disable all of the interrupts. */ + CY_SET_REG8(CY_INT_CLR_EN0_PTR, 0xFFu); + CY_SET_REG8(CY_INT_CLR_EN1_PTR, 0xFFu); + CY_SET_REG8(CY_INT_CLR_EN2_PTR, 0xFFu); + CY_SET_REG8(CY_INT_CLR_EN3_PTR, 0xFFu); + + #else + + /* Get the current interrupt state. */ + intState = CY_GET_REG32(CY_INT_CLEAR_PTR); + + /* Disable all of the interrupts. */ + CY_SET_REG32(CY_INT_CLEAR_PTR, 0xFFFFFFFFu); + + #endif /* (CY_PSOC3) */ + + CyExitCriticalSection(interruptState); + + return (intState); +} + + +/******************************************************************************* +* Function Name: CyEnableInts +****************************************************************************//** +* +* Enables interrupts to a given state. +* +* \param uint32 mask: 32 bit mask of interrupts to enable. +* +*******************************************************************************/ +void CyEnableInts(uint32 mask) +{ + + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + #if(CY_PSOC3) + + /* Set interrupts as enabled. */ + CY_SET_REG8(CY_INT_SET_EN3_PTR, ((uint8) (mask >> 24u))); + CY_SET_REG8(CY_INT_SET_EN2_PTR, ((uint8) (mask >> 16u))); + CY_SET_REG8(CY_INT_SET_EN1_PTR, ((uint8) (mask >> 8u ))); + CY_SET_REG8(CY_INT_SET_EN0_PTR, ((uint8) (mask ))); + + #else + + CY_SET_REG32(CY_INT_ENABLE_PTR, mask); + + #endif /* (CY_PSOC3) */ + + CyExitCriticalSection(interruptState); + +} + +#if(CY_PSOC5) + + /******************************************************************************* + * Function Name: CyFlushCache + ****************************************************************************//** + * Call this API after a flash row erase/write operation to invalidate or flush + * any of that particular flash region content already present in the cache. + * After a cache flush operation, any access to that flash region after the + * erase/write operation would reload the cache with the modified data from the + * flash region. If the flash region update involves multiple flash row write + * operations, then the flushing of the cache can be done once at the end of + * the operation as long as the flash data would not be accessed in the middle + * of the multiple row update process. Else, flush the cache after every flash + * row write. + * + *******************************************************************************/ + void CyFlushCache(void) + { + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + /* Fill instruction prefectch unit to insure data integrity */ + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + + /* All entries in cache are invalidated on next clock cycle. */ + CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH; + + /* Once this is executed it's guaranteed the cache has been flushed */ + (void) CY_CACHE_CONTROL_REG; + + /* Flush the pipeline */ + CY_SYS_ISB; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CyIntSetSysVector + ****************************************************************************//** + * Sets the interrupt vector of the specified system interrupt number. System + * interrupts are present only for the ARM platform. These interrupts are for + * SysTick, PendSV and others. + * + * \param number: System interrupt number: + * CY_INT_NMI_IRQN - Non Maskable Interrupt + * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt + * CY_INT_MEM_MANAGE_IRQN - Memory Management Interrupt + * CY_INT_BUS_FAULT_IRQN - Bus Fault Interrupt + * CY_INT_USAGE_FAULT_IRQN - Usage Fault Interrupt + * CY_INT_SVCALL_IRQN - SV Call Interrupt + * CY_INT_DEBUG_MONITOR_IRQN - Debug Monitor Interrupt + * CY_INT_PEND_SV_IRQN - Pend SV Interrupt + * CY_INT_SYSTICK_IRQN - System Tick Interrupt + * + * \param address: Pointer to an interrupt service routine. + * + * \return + * The old ISR vector at this location. + * + *******************************************************************************/ + cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) + { + cyisraddress oldIsr; + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + + CYASSERT(number <= CY_INT_SYS_NUMBER_MAX); + + /* Save old Interrupt service routine. */ + oldIsr = ramVectorTable[number & CY_INT_SYS_NUMBER_MASK]; + + /* Set new Interrupt service routine. */ + ramVectorTable[number & CY_INT_SYS_NUMBER_MASK] = address; + + return (oldIsr); + } + + + /******************************************************************************* + * Function Name: CyIntGetSysVector + ****************************************************************************//** + * + * Gets the interrupt vector of the specified system interrupt number. System + * interrupts are present only for the ARM platform. These interrupts are for + * SysTick, PendSV and others. + * + * \param number: System interrupt number: + * CY_INT_NMI_IRQN - Non Maskable Interrupt + * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt + * CY_INT_MEMORY_MANAGEMENT_IRQN - Memory Management Interrupt + * CY_INT_BUS_FAULT_IRQN - Bus Fault Interrupt + * CY_INT_USAGE_FAULT_IRQN - Usage Fault Interrupt + * CY_INT_SVCALL_IRQN - SV Call Interrupt + * CY_INT_DEBUG_MONITOR_IRQN - Debug Monitor Interrupt + * CY_INT_PEND_SV_IRQN - Pend SV Interrupt + * CY_INT_SYSTICK_IRQN - System Tick Interrupt + * + * \return + * Address of the ISR in the interrupt vector table. + * + *******************************************************************************/ + cyisraddress CyIntGetSysVector(uint8 number) + { + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + CYASSERT(number <= CY_INT_SYS_NUMBER_MAX); + + return ramVectorTable[number & CY_INT_SYS_NUMBER_MASK]; + } + + + /******************************************************************************* + * Function Name: CyIntSetVector + ****************************************************************************//** + * + * Sets the interrupt vector of the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number + * \param address: Pointer to an interrupt service routine + * + * \return + * Previous interrupt vector value. + * + *******************************************************************************/ + cyisraddress CyIntSetVector(uint8 number, cyisraddress address) + { + cyisraddress oldIsr; + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + uint32_t i = CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK); + + /* Save old Interrupt service routine. */ + oldIsr = ramVectorTable[i]; + + /* Set new Interrupt service routine. */ + ramVectorTable[i] = address; + + return (oldIsr); + } + + + /******************************************************************************* + * Function Name: CyIntGetVector + ****************************************************************************//** + * + * Gets the interrupt vector of the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number + * + * \return + * The address of the ISR in the interrupt vector table. + * + *******************************************************************************/ + cyisraddress CyIntGetVector(uint8 number) + { + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + CYASSERT(number <= CY_INT_NUMBER_MAX); + + return (ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]); + } + + + /******************************************************************************* + * Function Name: CyIntSetPriority + ****************************************************************************//** + * + * Sets the Priority of the Interrupt. + * + * \param priority: Priority of the interrupt. 0 - 7, 0 being the highest. + * \param number: The number of the interrupt, 0 - 31. + * + *******************************************************************************/ + void CyIntSetPriority(uint8 number, uint8 priority) + { + CYASSERT(priority <= CY_INT_PRIORITY_MAX); + CYASSERT(number <= CY_INT_NUMBER_MAX); + CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = (priority & CY_INT_PRIORITY_MASK)<< 5; + } + + + /******************************************************************************* + * Function Name: CyIntGetPriority + ****************************************************************************//** + * + * Gets the Priority of the Interrupt. + * + * \param number: The number of the interrupt, 0 - 31. + * + * \return + * Priority of the interrupt. 0 - 7, 0 being the highest. + * + *******************************************************************************/ + uint8 CyIntGetPriority(uint8 number) + { + uint8 priority; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5; + + return (priority); + } + + + /******************************************************************************* + * Function Name: CyIntGetState + ****************************************************************************//** + * + * Gets the enable state of the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number. + * + * \return + * Enable status: 1 if enabled, 0 if disabled + * + *******************************************************************************/ + uint8 CyIntGetState(uint8 number) + { + reg32 * stateReg; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Get pointer to Interrupt enable register. */ + stateReg = CY_INT_ENABLE_PTR; + + /* Get state of interrupt. */ + return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u)); + } + + +#else /* PSoC3 */ + + /******************************************************************************* + * Function Name: IntDefaultHandler + ****************************************************************************//** + * + * This function is called for all interrupts, other than a reset that gets + * called before the system is setup. + * + * Theory: + * Any value other than zero is acceptable. + * + *******************************************************************************/ + CY_ISR(IntDefaultHandler) + { + #ifdef CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK + CyBoot_IntDefaultHandler_Exception_EntryCallback(); + #endif /* CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK */ + + while(1) + { + /*********************************************************************** + * We must not get here. If we do, a serious problem occurs, so go + * into an infinite loop. + ***********************************************************************/ + } + } + + + /******************************************************************************* + * Function Name: IntDefaultHandler + ****************************************************************************//** + * + * This function is called during startup to initialize interrupt address vector + * registers with the address of the IntDefaultHandler(). + * + *******************************************************************************/ + void CyIntInitVectors(void) + { + uint8 i; + + for (i = 0; i <= CY_INT_NUMBER_MAX; i++) + { + CY_SET_REG16(&CY_INT_VECT_TABLE[i], (uint16) &IntDefaultHandler); + } + } + + + /******************************************************************************* + * Function Name: CyIntSetVector + ****************************************************************************//** + * + * Sets the interrupt vector of the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number + * \param address: Pointer to an interrupt service routine + * + * \return + * Previous interrupt vector value. + * + *******************************************************************************/ + cyisraddress CyIntSetVector(uint8 number, cyisraddress address) + { + cyisraddress oldIsr; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Save old Interrupt service routine. */ + oldIsr = (cyisraddress) \ + CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK]); + + /* Set new Interrupt service routine. */ + CY_SET_REG16(&CY_INT_VECT_TABLE[number], (uint16) address); + + return (oldIsr); + } + + + /******************************************************************************* + * Function Name: CyIntGetVector + ****************************************************************************//** + * + * Gets the interrupt vector of the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number + * + * \return + * Address of the ISR in the interrupt vector table. + * + *******************************************************************************/ + cyisraddress CyIntGetVector(uint8 number) + { + CYASSERT(number <= CY_INT_NUMBER_MAX); + + return ((cyisraddress) \ + CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK])); + } + + + /******************************************************************************* + * Function Name: CyIntSetPriority + ****************************************************************************//** + * + * Sets the Priority of the Interrupt. + * + * \param priority: Priority of the interrupt. 0 - 7, 0 being the highest. + * \param number: The number of the interrupt, 0 - 31. + * + *******************************************************************************/ + void CyIntSetPriority(uint8 number, uint8 priority) + { + CYASSERT(priority <= CY_INT_PRIORITY_MAX); + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = + (priority & CY_INT_PRIORITY_MASK) << 5; + } + + + /******************************************************************************* + * Function Name: CyIntGetPriority + ****************************************************************************//** + * + * Gets the Priority of the Interrupt. + * + * \param number: The number of the interrupt, 0 - 31. + * + * \return + * Priority of the interrupt. 0 - 7, 0 being the highest. + * + *******************************************************************************/ + uint8 CyIntGetPriority(uint8 number) + { + uint8 priority; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5; + + return (priority); + } + + + /******************************************************************************* + * Function Name: CyIntGetState + ****************************************************************************//** + * + * Gets the enable state of the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number. + * + * \return + * Enable status: 1 if enabled, 0 if disabled + * + *******************************************************************************/ + uint8 CyIntGetState(uint8 number) + { + reg8 * stateReg; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Get pointer to Interrupt enable register. */ + stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u); + + /* Get state of interrupt. */ + return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u))); + } + +#endif /* (CY_PSOC5) */ + + +#if(CYDEV_VARIABLE_VDDA == 1) + + /******************************************************************************* + * Function Name: CySetScPumps + ****************************************************************************//** + * + * If 1 is passed as a parameter: + * - if any of the SC blocks are used - enable pumps for the SC blocks and + * start boost clock. + * - For each enabled SC block set a boost clock index and enable the boost + * clock. + * + * If non-1 value is passed as a parameter: + * - If all SC blocks are not used - disable pumps for the SC blocks and + * stop the boost clock. + * - For each enabled SC block clear the boost clock index and disable the + * boost clock. + * + * The global variable CyScPumpEnabled is updated to be equal to passed the + * parameter. + * + * \param uint8 enable: Enable/disable SC pumps and the boost clock for the enabled + * \param SC block: + * 1 - Enable + * 0 - Disable + * + *******************************************************************************/ + void CySetScPumps(uint8 enable) + { + if(1u == enable) + { + /* The SC pumps should be enabled */ + CyScPumpEnabled = 1u; + /* Enable pumps if any of SC blocks are used */ + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAPS_MASK)) + { + CY_LIB_SC_MISC_REG |= CY_LIB_SC_MISC_PUMP_FORCE; + CyScBoostClk_Start(); + } + /* Set positive pump for each enabled SC block: set clock index and enable it */ + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP0_EN)) + { + CY_LIB_SC0_BST_REG = (CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC0_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP1_EN)) + { + CY_LIB_SC1_BST_REG = (CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC1_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP2_EN)) + { + CY_LIB_SC2_BST_REG = (CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC2_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP3_EN)) + { + CY_LIB_SC3_BST_REG = (CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC3_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + } + else + { + /* The SC pumps should be disabled */ + CyScPumpEnabled = 0u; + /* Disable pumps for all SC blocks and stop boost clock */ + CY_LIB_SC_MISC_REG &= ((uint8)(~CY_LIB_SC_MISC_PUMP_FORCE)); + CyScBoostClk_Stop(); + /* Disable boost clock and clear clock index for each SC block */ + CY_LIB_SC0_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC0_BST_REG = CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + CY_LIB_SC1_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC1_BST_REG = CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + CY_LIB_SC2_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC2_BST_REG = CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + CY_LIB_SC3_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC3_BST_REG = CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + } + } + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +#if(CY_PSOC5) + /******************************************************************************* + * Function Name: CySysTickStart + ****************************************************************************//** + * + * Configures the SysTick timer to generate interrupt every 1 ms by call to the + * CySysTickInit() function and starts it by calling CySysTickEnable() function. + * Refer to the corresponding function description for the details. + + * \sideeffect + * Clears SysTick count flag if it was set + * + *******************************************************************************/ + void CySysTickStart(void) + { + if (0u == CySysTickInitVar) + { + CySysTickInit(); + CySysTickInitVar = 1u; + } + + CySysTickEnable(); + } + + + /******************************************************************************* + * Function Name: CySysTickInit + ****************************************************************************//** + * + * Initializes the callback addresses with pointers to NULL, associates the + * SysTick system vector with the function that is responsible for calling + * registered callback functions, configures SysTick timer to generate interrupt + * every 1 ms. + * + * \sideeffect + * Clears SysTick count flag if it was set. + * + * The 1 ms interrupt interval is configured based on the frequency determined + * by PSoC Creator at build time. If System clock frequency is changed in + * runtime, the CyDelayFreq() with the appropriate parameter should be called. + * + *******************************************************************************/ + void CySysTickInit(void) + { + uint32 i; + + for (i = 0u; i> CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT) & CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ); + } + + + /******************************************************************************* + * Function Name: CySysTickGetCountFlag + ****************************************************************************//** + * + * The count flag is set once SysTick counter reaches zero. + * The flag cleared on read. + * + * \return + * Returns non-zero value if flag is set, otherwise zero is returned. + * + * + * \sideeffect + * Clears SysTick count flag if it was set. + * + *******************************************************************************/ + uint32 CySysTickGetCountFlag(void) + { + return ((CY_SYS_SYST_CSR_REG >> CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u); + } + + + /******************************************************************************* + * Function Name: CySysTickClear + ****************************************************************************//** + * + * Clears the SysTick counter for well-defined startup. + * + *******************************************************************************/ + void CySysTickClear(void) + { + CY_SYS_SYST_CVR_REG = 0u; + } + + + /******************************************************************************* + * Function Name: CySysTickSetCallback + ****************************************************************************//** + * + * This function allows up to five user-defined interrupt service routine + * functions to be associated with the SysTick interrupt. These are specified + * through the use of pointers to the function. + * + * To set a custom callback function without the overhead of the system provided + * one, use CyIntSetSysVector(CY_INT_SYSTICK_IRQN, cyisraddress
), + * where
is address of the custom defined interrupt service routine. + * Note: a custom callback function overrides the system defined callback + * functions. + * + * \param number: The number of the callback function addresses to be set. The valid + * range is from 0 to 4. + * + * void(*CallbackFunction(void): A pointer to the function that will be + * associated with the SysTick ISR for the + * specified number. + * + * \return + * Returns the address of the previous callback function. + * The NULL is returned if the specified address in not set. + * + * \sideeffect + * The registered callback functions will be executed in the interrupt. + * + *******************************************************************************/ + cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function) + { + cySysTickCallback retVal; + + retVal = CySysTickCallbacks[number]; + CySysTickCallbacks[number] = function; + return (retVal); + } + + + /******************************************************************************* + * Function Name: CySysTickGetCallback + ****************************************************************************//** + * + * The function get the specified callback pointer. + * + * \param number: The number of callback function address to get. The valid + * range is from 0 to 4. + * + * \return + * Returns the address of the specified callback function. + * The NULL is returned if the specified address in not initialized. + * + *******************************************************************************/ + cySysTickCallback CySysTickGetCallback(uint32 number) + { + return ((cySysTickCallback) CySysTickCallbacks[number]); + } + + + /******************************************************************************* + * Function Name: CySysTickServiceCallbacks + ****************************************************************************//** + * + * System Tick timer interrupt routine + * + *******************************************************************************/ + static void CySysTickServiceCallbacks(void) + { + uint32 i; + + /* Verify that tick timer flag was set */ + if (1u == CySysTickGetCountFlag()) + { + for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++) + { + if (CySysTickCallbacks[i] != (void *) 0) + { + (void)(CySysTickCallbacks[i])(); + } + } + } + } +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Function Name: CyGetUniqueId +****************************************************************************//** +* +* Returns the 64-bit unique ID of the device. The uniqueness of the number is +* guaranteed for 10 years due to the die lot number having a cycle life of 10 +* years and even after 10 years, the probability of getting two identical +* numbers is very small. +* +* \param uniqueId: The pointer to a two element 32-bit unsigned integer array. Returns +* the 64-bit unique ID of the device by loading them into the integer array +* pointed to by uniqueId. +* +*******************************************************************************/ +void CyGetUniqueId(uint32* uniqueId) +{ +#if(CY_PSOC4) + uniqueId[0u] = (uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT0 ); + uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT1 ) << 8u); + uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT2 ) << 16u); + uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_WAFER ) << 24u); + + uniqueId[1u] = (uint32)(* (reg8 *) CYREG_SFLASH_DIE_X ); + uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_Y ) << 8u); + uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_SORT ) << 16u); + uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_MINOR ) << 24u); +#else + uniqueId[0u] = (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_LSB )); + uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_MSB )) << 8u); + uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_MLOGIC_REV_ID )) << 16u); + uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WAFER_NUM )) << 24u); + + uniqueId[1u] = (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_X_LOC )); + uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_Y_LOC )) << 8u); + uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WRK_WK )) << 16u); + uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_FAB_YR )) << 24u); +#endif /* (CY_PSOC4) */ +} + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/CyLib.h b/source/hic_hal/cypress/psoc5lp/PSoC5/CyLib.h new file mode 100644 index 0000000000..b2aa31e6aa --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/CyLib.h @@ -0,0 +1,1326 @@ +/***************************************************************************//** +* \file CyLib.h +* \version 5.70 +* +* \brief Provides the function definitions for the system, clocking, interrupts +* and watchdog timer API. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_BOOT_CYLIB_H) +#define CY_BOOT_CYLIB_H + +#include +#include +#include + +#include "cytypes.h" +#include "cyfitter.h" +#include "cydevice_trm.h" +#include "cyPm.h" + +#if(CY_PSOC3) + #include +#endif /* (CY_PSOC3) */ + + +#if(CYDEV_VARIABLE_VDDA == 1) + + #include "CyScBoostClk.h" + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/* Global variable with preserved reset status */ +extern uint8 CYXDATA CyResetStatus; + + +/* Variable Vdda */ +#if(CYDEV_VARIABLE_VDDA == 1) + + extern uint8 CyScPumpEnabled; + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/* Do not use these definitions directly in your application */ +extern uint32 cydelay_freq_hz; +extern uint32 cydelay_freq_khz; +extern uint8 cydelay_freq_mhz; +extern uint32 cydelay_32k_ms; + + +/*************************************** +* Function Prototypes +***************************************/ +cystatus CyPLL_OUT_Start(uint8 wait) ; +void CyPLL_OUT_Stop(void) ; +void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) ; +void CyPLL_OUT_SetSource(uint8 source) ; + +void CyIMO_Start(uint8 wait) ; +void CyIMO_Stop(void) ; +void CyIMO_SetFreq(uint8 freq) ; +void CyIMO_SetSource(uint8 source) ; +void CyIMO_EnableDoubler(void) ; +void CyIMO_DisableDoubler(void) ; + +void CyMasterClk_SetSource(uint8 source) ; +void CyMasterClk_SetDivider(uint8 divider) ; +void CyBusClk_SetDivider(uint16 divider) ; + +#if(CY_PSOC3) + void CyCpuClk_SetDivider(uint8 divider) ; +#endif /* (CY_PSOC3) */ + +void CyUsbClk_SetSource(uint8 source) ; + +void CyILO_Start1K(void) ; +void CyILO_Stop1K(void) ; +void CyILO_Start100K(void) ; +void CyILO_Stop100K(void) ; +void CyILO_Enable33K(void) ; +void CyILO_Disable33K(void) ; +void CyILO_SetSource(uint8 source) ; +uint8 CyILO_SetPowerMode(uint8 mode) ; + +uint8 CyXTAL_32KHZ_ReadStatus(void) ; +uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) ; +void CyXTAL_32KHZ_Start(void) ; +void CyXTAL_32KHZ_Stop(void) ; + +cystatus CyXTAL_Start(uint8 wait) ; +void CyXTAL_Stop(void) ; +void CyXTAL_SetStartup(uint8 setting) ; + +void CyXTAL_EnableErrStatus(void) ; +void CyXTAL_DisableErrStatus(void) ; +uint8 CyXTAL_ReadStatus(void) ; +void CyXTAL_EnableFaultRecovery(void) ; +void CyXTAL_DisableFaultRecovery(void) ; + +void CyXTAL_SetFbVoltage(uint8 setting) ; +void CyXTAL_SetWdVoltage(uint8 setting) ; + +void CyWdtStart(uint8 ticks, uint8 lpMode) ; +void CyWdtClear(void) ; + +/* System Function Prototypes */ +void CyDelay(uint32 milliseconds) CYREENTRANT; +void CyDelayUs(uint16 microseconds); +void CyDelayFreq(uint32 freq) CYREENTRANT; +void CyDelayCycles(uint32 cycles); + +void CySoftwareReset(void) ; + +uint8 CyEnterCriticalSection(void); +void CyExitCriticalSection(uint8 savedIntrStatus); +void CyHalt(uint8 reason) CYREENTRANT; + + +/* Interrupt Function Prototypes */ +#if(CY_PSOC5) + cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) ; + cyisraddress CyIntGetSysVector(uint8 number) ; +#endif /* (CY_PSOC5) */ + +cyisraddress CyIntSetVector(uint8 number, cyisraddress address) ; +cyisraddress CyIntGetVector(uint8 number) ; + +void CyIntSetPriority(uint8 number, uint8 priority) ; +uint8 CyIntGetPriority(uint8 number) ; + +uint8 CyIntGetState(uint8 number) ; + +uint32 CyDisableInts(void) ; +void CyEnableInts(uint32 mask) ; + + +#if(CY_PSOC5) + void CyFlushCache(void); +#endif /* (CY_PSOC5) */ + + +/* Voltage Detection Function Prototypes */ +void CyVdLvDigitEnable(uint8 reset, uint8 threshold) ; +void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) ; +void CyVdLvDigitDisable(void) ; +void CyVdLvAnalogDisable(void) ; +void CyVdHvAnalogEnable(void) ; +void CyVdHvAnalogDisable(void) ; +uint8 CyVdStickyStatus(uint8 mask) ; +uint8 CyVdRealTimeStatus(void) ; + +void CySetScPumps(uint8 enable) ; + +#if(CY_PSOC5) + /* Default interrupt handler */ + CY_ISR_PROTO(IntDefaultHandler); +#endif /* (CY_PSOC5) */ + +#if(CY_PSOC5) + /** System tick timer APIs */ + typedef void (*cySysTickCallback)(void); + + void CySysTickStart(void); + void CySysTickInit(void); + void CySysTickEnable(void); + void CySysTickStop(void); + void CySysTickEnableInterrupt(void); + void CySysTickDisableInterrupt(void); + void CySysTickSetReload(uint32 value); + uint32 CySysTickGetReload(void); + uint32 CySysTickGetValue(void); + cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function); + cySysTickCallback CySysTickGetCallback(uint32 number); + void CySysTickSetClockSource(uint32 clockSource); + uint32 CySysTickGetCountFlag(void); + void CySysTickClear(void); +#endif /* (CY_PSOC5) */ + +void CyGetUniqueId(uint32* uniqueId); + + +/*************************************** +* API Constants +***************************************/ + + +/******************************************************************************* +* PLL API Constants +*******************************************************************************/ +#define CY_CLK_PLL_ENABLE (0x01u) +#define CY_CLK_PLL_LOCK_STATUS (0x01u) + +#define CY_CLK_PLL_FTW_INTERVAL (24u) + +#define CY_CLK_PLL_MAX_Q_VALUE (16u) +#define CY_CLK_PLL_MIN_Q_VALUE (1u) +#define CY_CLK_PLL_MIN_P_VALUE (8u) +#define CY_CLK_PLL_MIN_CUR_VALUE (1u) +#define CY_CLK_PLL_MAX_CUR_VALUE (7u) + +#define CY_CLK_PLL_CURRENT_POSITION (4u) +#define CY_CLK_PLL_CURRENT_MASK (0x8Fu) + + +/******************************************************************************* +* External 32kHz Crystal Oscillator API Constants +*******************************************************************************/ +#define CY_XTAL32K_ANA_STAT (0x20u) + +#define CY_CLK_XTAL32_CR_LPM (0x02u) +#define CY_CLK_XTAL32_CR_EN (0x01u) +#if(CY_PSOC3) + #define CY_CLK_XTAL32_CR_PDBEN (0x04u) +#endif /* (CY_PSOC3) */ + +#define CY_CLK_XTAL32_TR_MASK (0x07u) +#define CY_CLK_XTAL32_TR_STARTUP (0x03u) +#define CY_CLK_XTAL32_TR_HIGH_POWER (0x06u) +#define CY_CLK_XTAL32_TR_LOW_POWER (0x01u) +#define CY_CLK_XTAL32_TR_POWERDOWN (0x00u) + +#define CY_CLK_XTAL32_TST_DEFAULT (0xF3u) + +#define CY_CLK_XTAL32_CFG_LP_DEFAULT (0x04u) +#define CY_CLK_XTAL32_CFG_LP_LOWPOWER (0x08u) +#define CY_CLK_XTAL32_CFG_LP_MASK (0x0Cu) + +#define CY_CLK_XTAL32_CFG_LP_ALLOW (0x80u) + + +/******************************************************************************* +* External MHz Crystal Oscillator API Constants +*******************************************************************************/ +#define CY_CLK_XMHZ_FTW_INTERVAL (24u) +#define CY_CLK_XMHZ_MIN_TIMEOUT (130u) + +#define CY_CLK_XMHZ_CSR_ENABLE (0x01u) +#define CY_CLK_XMHZ_CSR_XERR (0x80u) +#define CY_CLK_XMHZ_CSR_XFB (0x04u) +#define CY_CLK_XMHZ_CSR_XPROT (0x40u) + +#define CY_CLK_XMHZ_CFG0_XCFG_MASK (0x1Fu) +#define CY_CLK_XMHZ_CFG1_VREF_FB_MASK (0x0Fu) +#define CY_CLK_XMHZ_CFG1_VREF_WD_MASK (0x70u) + + +/******************************************************************************* +* Watchdog Timer API Constants +*******************************************************************************/ +#define CYWDT_2_TICKS (0x0u) /* 4 - 6 ms */ +#define CYWDT_16_TICKS (0x1u) /* 32 - 48 ms */ +#define CYWDT_128_TICKS (0x2u) /* 256 - 384 ms */ +#define CYWDT_1024_TICKS (0x3u) /* 2048 - 3072 ms */ + +#define CYWDT_LPMODE_NOCHANGE (0x00u) +#define CYWDT_LPMODE_MAXINTER (0x01u) +#define CYWDT_LPMODE_DISABLED (0x03u) + +#define CY_WDT_CFG_INTERVAL_MASK (0x03u) +#define CY_WDT_CFG_CTW_RESET (0x80u) +#define CY_WDT_CFG_LPMODE_SHIFT (5u) +#define CY_WDT_CFG_LPMODE_MASK (0x60u) +#define CY_WDT_CFG_WDR_EN (0x10u) +#define CY_WDT_CFG_CLEAR_ALL (0x00u) +#define CY_WDT_CR_FEED (0x01u) + + +/******************************************************************************* +* Voltage Detection API Constants +*******************************************************************************/ + +#define CY_VD_LVID_EN (0x01u) +#define CY_VD_LVIA_EN (0x02u) +#define CY_VD_HVIA_EN (0x04u) + +#define CY_VD_PRESD_EN (0x40u) +#define CY_VD_PRESA_EN (0x80u) + +#define CY_VD_LVID (0x01u) +#define CY_VD_LVIA (0x02u) +#define CY_VD_HVIA (0x04u) + +#define CY_VD_LVI_TRIP_LVID_MASK (0x0Fu) +#define CY_VD_INT_MASK ((uint32) (0x01u)) + + +/******************************************************************************* +* Variable VDDA API Constants +*******************************************************************************/ +#if(CYDEV_VARIABLE_VDDA == 1) + + /* Active Power Mode Configuration Register 9 */ + #define CY_LIB_ACT_CFG9_SWCAP0_EN (0x01u) + #define CY_LIB_ACT_CFG9_SWCAP1_EN (0x02u) + #define CY_LIB_ACT_CFG9_SWCAP2_EN (0x04u) + #define CY_LIB_ACT_CFG9_SWCAP3_EN (0x08u) + #define CY_LIB_ACT_CFG9_SWCAPS_MASK (0x0Fu) + + /* Switched Cap Miscellaneous Control Register */ + #define CY_LIB_SC_MISC_PUMP_FORCE (0x20u) + + /* Switched Capacitor 0 Boost Clock Selection Register */ + #define CY_LIB_SC_BST_CLK_EN (0x08u) + #define CY_LIB_SC_BST_CLK_INDEX_MASK (0xF8u) + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/******************************************************************************* +* Clock Distribution API Constants +*******************************************************************************/ +#define CY_LIB_CLKDIST_AMASK_MASK (0xF0u) +#define CY_LIB_CLKDIST_DMASK_MASK (0x00u) +#define CY_LIB_CLKDIST_LD_LOAD (0x01u) +#define CY_LIB_CLKDIST_BCFG2_MASK (0x80u) +#define CY_LIB_CLKDIST_MASTERCLK_DIV (7u) +#define CY_LIB_CLKDIST_BCFG2_SSS (0x40u) +#define CY_LIB_CLKDIST_MSTR1_SRC_MASK (0xFCu) +#define CY_LIB_FASTCLK_IMO_DOUBLER (0x10u) +#define CY_LIB_FASTCLK_IMO_IMO (0x20u) +#define CY_LIB_CLKDIST_CR_IMO2X (0x40u) +#define CY_LIB_FASTCLK_IMO_CR_RANGE_MASK (0xF8u) + +#define CY_LIB_CLKDIST_CR_PLL_SCR_MASK (0xFCu) + + +/* CyILO_SetPowerMode() */ +#define CY_ILO_CONTROL_PD_MODE (0x10u) +#define CY_ILO_CONTROL_PD_POSITION (4u) + +#define CY_ILO_SOURCE_100K (0u) +#define CY_ILO_SOURCE_33K (1u) +#define CY_ILO_SOURCE_1K (2u) + +#define CY_ILO_FAST_START (0u) +#define CY_ILO_SLOW_START (1u) + +#define CY_ILO_SOURCE_BITS_CLEAR (0xF3u) +#define CY_ILO_SOURCE_1K_SET (0x08u) +#define CY_ILO_SOURCE_33K_SET (0x04u) +#define CY_ILO_SOURCE_100K_SET (0x00u) + +#define CY_MASTER_SOURCE_IMO (0u) +#define CY_MASTER_SOURCE_PLL (1u) +#define CY_MASTER_SOURCE_XTAL (2u) +#define CY_MASTER_SOURCE_DSI (3u) + +#define CY_IMO_SOURCE_IMO (0u) +#define CY_IMO_SOURCE_XTAL (1u) +#define CY_IMO_SOURCE_DSI (2u) + + +/* CyIMO_Start() */ +#define CY_LIB_PM_ACT_CFG0_IMO_EN (0x10u) +#define CY_LIB_PM_STBY_CFG0_IMO_EN (0x10u) +#define CY_LIB_CLK_IMO_FTW_TIMEOUT (0x00u) + +#define CY_LIB_IMO_3MHZ_VALUE (0x03u) +#define CY_LIB_IMO_6MHZ_VALUE (0x01u) +#define CY_LIB_IMO_12MHZ_VALUE (0x00u) +#define CY_LIB_IMO_24MHZ_VALUE (0x02u) +#define CY_LIB_IMO_48MHZ_VALUE (0x04u) +#define CY_LIB_IMO_62MHZ_VALUE (0x05u) +#define CY_LIB_IMO_74MHZ_VALUE (0x06u) + + +/* CyIMO_SetFreq() */ +#define CY_IMO_FREQ_3MHZ (0u) +#define CY_IMO_FREQ_6MHZ (1u) +#define CY_IMO_FREQ_12MHZ (2u) +#define CY_IMO_FREQ_24MHZ (3u) +#define CY_IMO_FREQ_48MHZ (4u) +#define CY_IMO_FREQ_62MHZ (5u) +#if(CY_PSOC5) + #define CY_IMO_FREQ_74MHZ (6u) +#endif /* (CY_PSOC5) */ +#define CY_IMO_FREQ_USB (8u) + +#define CY_LIB_IMO_USBCLK_ON_SET (0x40u) + + +/* CyCpuClk_SetDivider() */ +#define CY_LIB_CLKDIST_DIV_POSITION (4u) +#define CY_LIB_CLKDIST_MSTR1_DIV_MASK (0x0Fu) + + +/* CyIMO_SetTrimValue() */ +#define CY_LIB_USB_CLK_EN (0x02u) + + +/* CyPLL_OUT_SetSource() - parameters */ +#define CY_PLL_SOURCE_IMO (0u) +#define CY_PLL_SOURCE_XTAL (1u) +#define CY_PLL_SOURCE_DSI (2u) + + +/* CyILO_[Start|Stop][1|100K](), CyILO_[Enable|Disable]33K() */ +#define CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ (0x02u) +#define CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ (0x20u) +#define CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ (0x04u) + + +/* CyUsbClk_SetSource() */ +#define CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK (0x03u) + + +/* CyUsbClk_SetSource() - parameters */ +#define CY_LIB_USB_CLK_IMO2X (0x00u) +#define CY_LIB_USB_CLK_IMO (0x01u) +#define CY_LIB_USB_CLK_PLL (0x02u) +#define CY_LIB_USB_CLK_DSI (0x03u) + + +/* CyUSB_PowerOnCheck() */ +#define CY_ACT_USB_ENABLED (0x01u) +#define CY_ALT_ACT_USB_ENABLED (0x01u) + + +#if(CY_PSOC5) + + /*************************************************************************** + * Instruction Synchronization Barrier flushes the pipeline in the processor, + * so that all instructions following the ISB are fetched from cache or + * memory, after the instruction has been completed. + ***************************************************************************/ + + #if defined(__ARMCC_VERSION) + #define CY_SYS_ISB __isb(0x0f) + #else /* ASM for GCC & IAR */ + #define CY_SYS_ISB __asm volatile ("isb \n") + #endif /* (__ARMCC_VERSION) */ + +#endif /* (CY_PSOC5) */ + + +/*************************************** +* Registers +***************************************/ + + +/******************************************************************************* +* System Registers +*******************************************************************************/ + +/* Software Reset Control Register */ +#define CY_LIB_RESET_CR2_REG (* (reg8 *) CYREG_RESET_CR2) +#define CY_LIB_RESET_CR2_PTR ( (reg8 *) CYREG_RESET_CR2) + +/* Timewheel Configuration Register 0 */ +#define CY_LIB_PM_TW_CFG0_REG (*(reg8 *) CYREG_PM_TW_CFG0) +#define CY_LIB_PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0) + +/* Timewheel Configuration Register 2 */ +#define CY_LIB_PM_TW_CFG2_REG (*(reg8 *) CYREG_PM_TW_CFG2) +#define CY_LIB_PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2) + +/* USB Configuration Register */ +#define CY_LIB_CLKDIST_UCFG_REG (*(reg8 *) CYREG_CLKDIST_UCFG) +#define CY_LIB_CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) + +/* Internal Main Oscillator Trim Register 1 */ +#define CY_LIB_IMO_TR1_REG (*(reg8 *) CYREG_IMO_TR1) +#define CY_LIB_IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1) + +/* USB control 1 Register */ +#define CY_LIB_USB_CR1_REG (*(reg8 *) CYREG_USB_CR1 ) +#define CY_LIB_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 ) + +/* Active Power Mode Configuration Register 0 */ +#define CY_LIB_PM_ACT_CFG0_REG (*(reg8 *) CYREG_PM_ACT_CFG0) +#define CY_LIB_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0) + +/* Standby Power Mode Configuration Register 0 */ +#define CY_LIB_PM_STBY_CFG0_REG (*(reg8 *) CYREG_PM_STBY_CFG0) +#define CY_LIB_PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0) + +/* Active Power Mode Configuration Register 5 */ +#define CY_LIB_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 ) +#define CY_LIB_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 ) + +/* Standby Power Mode Configuration Register 5 */ +#define CY_LIB_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 ) +#define CY_LIB_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 ) + +/* CyIMO_SetTrimValue() */ +#if(CY_PSOC3) + #define CY_LIB_TRIM_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define CY_LIB_TRIM_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define CY_LIB_TRIM_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define CY_LIB_TRIM_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define CY_LIB_TRIM_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define CY_LIB_TRIM_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define CY_LIB_TRIM_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define CY_LIB_TRIM_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) + #else + #define CY_LIB_TRIM_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define CY_LIB_TRIM_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define CY_LIB_TRIM_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define CY_LIB_TRIM_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define CY_LIB_TRIM_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define CY_LIB_TRIM_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define CY_LIB_TRIM_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define CY_LIB_TRIM_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* PLL Registers +*******************************************************************************/ + +/* PLL Configuration Register 0 */ +#define CY_CLK_PLL_CFG0_REG (*(reg8 *) CYREG_FASTCLK_PLL_CFG0) +#define CY_CLK_PLL_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG0) + +/* PLL Configuration Register 1 */ +#define CY_CLK_PLL_CFG1_REG (*(reg8 *) CYREG_FASTCLK_PLL_CFG1) +#define CY_CLK_PLL_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG1) + +/* PLL Status Register */ +#define CY_CLK_PLL_SR_REG (*(reg8 *) CYREG_FASTCLK_PLL_SR) +#define CY_CLK_PLL_SR_PTR ( (reg8 *) CYREG_FASTCLK_PLL_SR) + +/* PLL Q-Counter Configuration Register */ +#define CY_CLK_PLL_Q_REG (*(reg8 *) CYREG_FASTCLK_PLL_Q) +#define CY_CLK_PLL_Q_PTR ( (reg8 *) CYREG_FASTCLK_PLL_Q) + +/* PLL P-Counter Configuration Register */ +#define CY_CLK_PLL_P_REG (*(reg8 *) CYREG_FASTCLK_PLL_P) +#define CY_CLK_PLL_P_PTR ( (reg8 *) CYREG_FASTCLK_PLL_P) + + +/******************************************************************************* +* External MHz Crystal Oscillator Registers +*******************************************************************************/ + +/* External MHz Crystal Oscillator Status and Control Register */ +#define CY_CLK_XMHZ_CSR_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CSR) +#define CY_CLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR) + +/* External MHz Crystal Oscillator Configuration Register 0 */ +#define CY_CLK_XMHZ_CFG0_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG0) +#define CY_CLK_XMHZ_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG0) + +/* External MHz Crystal Oscillator Configuration Register 1 */ +#define CY_CLK_XMHZ_CFG1_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG1) +#define CY_CLK_XMHZ_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG1) + + +/******************************************************************************* +* External 32kHz Crystal Oscillator Registers +*******************************************************************************/ + +/* 32 kHz Watch Crystal Oscillator Trim Register */ +#define CY_CLK_XTAL32_TR_REG (*(reg8 *) CYREG_X32_TR) +#define CY_CLK_XTAL32_TR_PTR ( (reg8 *) CYREG_X32_TR) + +/* External 32kHz Crystal Oscillator Test Register */ +#define CY_CLK_XTAL32_TST_REG (*(reg8 *) CYREG_SLOWCLK_X32_TST) +#define CY_CLK_XTAL32_TST_PTR ( (reg8 *) CYREG_SLOWCLK_X32_TST) + +/* External 32kHz Crystal Oscillator Control Register */ +#define CY_CLK_XTAL32_CR_REG (*(reg8 *) CYREG_SLOWCLK_X32_CR) +#define CY_CLK_XTAL32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR) + +/* External 32kHz Crystal Oscillator Configuration Register */ +#define CY_CLK_XTAL32_CFG_REG (*(reg8 *) CYREG_SLOWCLK_X32_CFG) +#define CY_CLK_XTAL32_CFG_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CFG) + + +/******************************************************************************* +* Watchdog Timer Registers +*******************************************************************************/ + +/* Watchdog Timer Configuration Register */ +#define CY_WDT_CFG_REG (*(reg8 *) CYREG_PM_WDT_CFG) +#define CY_WDT_CFG_PTR ( (reg8 *) CYREG_PM_WDT_CFG) + +/* Watchdog Timer Control Register */ +#define CY_WDT_CR_REG (*(reg8 *) CYREG_PM_WDT_CR) +#define CY_WDT_CR_PTR ( (reg8 *) CYREG_PM_WDT_CR) + + +/******************************************************************************* +* LVI/HVI Registers +*******************************************************************************/ + +#define CY_VD_LVI_TRIP_REG (* (reg8 *) CYREG_RESET_CR0) +#define CY_VD_LVI_TRIP_PTR ( (reg8 *) CYREG_RESET_CR0) + +#define CY_VD_LVI_HVI_CONTROL_REG (* (reg8 *) CYREG_RESET_CR1) +#define CY_VD_LVI_HVI_CONTROL_PTR ( (reg8 *) CYREG_RESET_CR1) + +#define CY_VD_PRES_CONTROL_REG (* (reg8 *) CYREG_RESET_CR3) +#define CY_VD_PRES_CONTROL_PTR ( (reg8 *) CYREG_RESET_CR3) + +#define CY_VD_PERSISTENT_STATUS_REG (* (reg8 *) CYREG_RESET_SR0) +#define CY_VD_PERSISTENT_STATUS_PTR ( (reg8 *) CYREG_RESET_SR0) + +#define CY_VD_RT_STATUS_REG (* (reg8 *) CYREG_RESET_SR2) +#define CY_VD_RT_STATUS_PTR ( (reg8 *) CYREG_RESET_SR2) + + +/******************************************************************************* +* Variable VDDA +*******************************************************************************/ +#if(CYDEV_VARIABLE_VDDA == 1) + + /* Active Power Mode Configuration Register 9 */ + #define CY_LIB_ACT_CFG9_REG (* (reg8 *) CYREG_PM_ACT_CFG9 ) + #define CY_LIB_ACT_CFG9_PTR ( (reg8 *) CYREG_PM_ACT_CFG9 ) + + /* Switched Capacitor 0 Boost Clock Selection Register */ + #define CY_LIB_SC0_BST_REG (* (reg8 *) CYREG_SC0_BST ) + #define CY_LIB_SC0_BST_PTR ( (reg8 *) CYREG_SC0_BST ) + + /* Switched Capacitor 1 Boost Clock Selection Register */ + #define CY_LIB_SC1_BST_REG (* (reg8 *) CYREG_SC1_BST ) + #define CY_LIB_SC1_BST_PTR ( (reg8 *) CYREG_SC1_BST ) + + /* Switched Capacitor 2 Boost Clock Selection Register */ + #define CY_LIB_SC2_BST_REG (* (reg8 *) CYREG_SC2_BST ) + #define CY_LIB_SC2_BST_PTR ( (reg8 *) CYREG_SC2_BST ) + + /* Switched Capacitor 3 Boost Clock Selection Register */ + #define CY_LIB_SC3_BST_REG (* (reg8 *) CYREG_SC3_BST ) + #define CY_LIB_SC3_BST_PTR ( (reg8 *) CYREG_SC3_BST ) + + /* Switched Cap Miscellaneous Control Register */ + #define CY_LIB_SC_MISC_REG (* (reg8 *) CYREG_SC_MISC ) + #define CY_LIB_SC_MISC_PTR ( (reg8 *) CYREG_SC_MISC ) + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/******************************************************************************* +* Clock Distribution Registers +*******************************************************************************/ + +/* Analog Clock Mask Register */ +#define CY_LIB_CLKDIST_AMASK_REG (* (reg8 *) CYREG_CLKDIST_AMASK ) +#define CY_LIB_CLKDIST_AMASK_PTR ( (reg8 *) CYREG_CLKDIST_AMASK ) + +/* Digital Clock Mask Register */ +#define CY_LIB_CLKDIST_DMASK_REG (*(reg8 *) CYREG_CLKDIST_DMASK) +#define CY_LIB_CLKDIST_DMASK_PTR ( (reg8 *) CYREG_CLKDIST_DMASK) + +/* CLK_BUS Configuration Register */ +#define CY_LIB_CLKDIST_BCFG2_REG (*(reg8 *) CYREG_CLKDIST_BCFG2) +#define CY_LIB_CLKDIST_BCFG2_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2) + +/* LSB Shadow Divider Value Register */ +#define CY_LIB_CLKDIST_WRK_LSB_REG (*(reg8 *) CYREG_CLKDIST_WRK0) +#define CY_LIB_CLKDIST_WRK_LSB_PTR ( (reg8 *) CYREG_CLKDIST_WRK0) + +/* MSB Shadow Divider Value Register */ +#define CY_LIB_CLKDIST_WRK_MSB_REG (*(reg8 *) CYREG_CLKDIST_WRK1) +#define CY_LIB_CLKDIST_WRK_MSB_PTR ( (reg8 *) CYREG_CLKDIST_WRK1) + +/* LOAD Register */ +#define CY_LIB_CLKDIST_LD_REG (*(reg8 *) CYREG_CLKDIST_LD) +#define CY_LIB_CLKDIST_LD_PTR ( (reg8 *) CYREG_CLKDIST_LD) + +/* CLK_BUS LSB Divider Value Register */ +#define CY_LIB_CLKDIST_BCFG_LSB_REG (*(reg8 *) CYREG_CLKDIST_BCFG0) +#define CY_LIB_CLKDIST_BCFG_LSB_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0) + +/* CLK_BUS MSB Divider Value Register */ +#define CY_LIB_CLKDIST_BCFG_MSB_REG (*(reg8 *) CYREG_CLKDIST_BCFG1) +#define CY_LIB_CLKDIST_BCFG_MSB_PTR ( (reg8 *) CYREG_CLKDIST_BCFG1) + +/* Master clock (clk_sync_d) Divider Value Register */ +#define CY_LIB_CLKDIST_MSTR0_REG (*(reg8 *) CYREG_CLKDIST_MSTR0) +#define CY_LIB_CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0) + +/* Master (clk_sync_d) Configuration Register/CPU Divider Value */ +#define CY_LIB_CLKDIST_MSTR1_REG (*(reg8 *) CYREG_CLKDIST_MSTR1) +#define CY_LIB_CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1) + +/* Internal Main Oscillator Control Register */ +#define CY_LIB_FASTCLK_IMO_CR_REG (*(reg8 *) CYREG_FASTCLK_IMO_CR) +#define CY_LIB_FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR) + +/* Configuration Register CR */ +#define CY_LIB_CLKDIST_CR_REG (*(reg8 *) CYREG_CLKDIST_CR) +#define CY_LIB_CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR) + +/* Internal Low-speed Oscillator Control Register 0 */ +#define CY_LIB_SLOWCLK_ILO_CR0_REG (*(reg8 *) CYREG_SLOWCLK_ILO_CR0) +#define CY_LIB_SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0) + + +/******************************************************************************* +* Interrupt Registers +*******************************************************************************/ + +#if(CY_PSOC5) + + /* Interrupt Vector Table Offset */ + #define CY_INT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) + + /* Interrupt Priority 0-31 */ + #define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_NVIC_PRI_0) + #define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_NVIC_PRI_0) + + /* Interrupt Enable Set 0-31 */ + #define CY_INT_ENABLE_REG (* (reg32 *) CYREG_NVIC_SETENA0) + #define CY_INT_ENABLE_PTR ( (reg32 *) CYREG_NVIC_SETENA0) + + /* Interrupt Enable Clear 0-31 */ + #define CY_INT_CLEAR_REG (* (reg32 *) CYREG_NVIC_CLRENA0) + #define CY_INT_CLEAR_PTR ( (reg32 *) CYREG_NVIC_CLRENA0) + + /* Interrupt Pending Set 0-31 */ + #define CY_INT_SET_PEND_REG (* (reg32 *) CYREG_NVIC_SETPEND0) + #define CY_INT_SET_PEND_PTR ( (reg32 *) CYREG_NVIC_SETPEND0) + + /* Interrupt Pending Clear 0-31 */ + #define CY_INT_CLR_PEND_REG (* (reg32 *) CYREG_NVIC_CLRPEND0) + #define CY_INT_CLR_PEND_PTR ( (reg32 *) CYREG_NVIC_CLRPEND0) + + /* Cache Control Register */ + #define CY_CACHE_CONTROL_REG (* (reg16 *) CYREG_CACHE_CC_CTL ) + #define CY_CACHE_CONTROL_PTR ( (reg16 *) CYREG_CACHE_CC_CTL ) + + /* System tick registers */ + #define CY_SYS_SYST_CSR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CTL) + #define CY_SYS_SYST_CSR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CTL) + + #define CY_SYS_SYST_RVR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_RELOAD) + #define CY_SYS_SYST_RVR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_RELOAD) + + #define CY_SYS_SYST_CVR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CURRENT) + #define CY_SYS_SYST_CVR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CURRENT) + + #define CY_SYS_SYST_CALIB_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CAL) + #define CY_SYS_SYST_CALIB_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CAL) + +#elif (CY_PSOC3) + + /* Interrupt Address Vector registers */ + #define CY_INT_VECT_TABLE ((cyisraddress CYXDATA *) CYREG_INTC_VECT_MBASE) + + /* Interrupt Controller Priority Registers */ + #define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_INTC_PRIOR0) + #define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_INTC_PRIOR0) + + /* Interrupt Controller Set Enable Registers */ + #define CY_INT_ENABLE_REG (* (reg8 *) CYREG_INTC_SET_EN0) + #define CY_INT_ENABLE_PTR ( (reg8 *) CYREG_INTC_SET_EN0) + + #define CY_INT_SET_EN0_REG (* (reg8 *) CYREG_INTC_SET_EN0) + #define CY_INT_SET_EN0_PTR ( (reg8 *) CYREG_INTC_SET_EN0) + + #define CY_INT_SET_EN1_REG (* (reg8 *) CYREG_INTC_SET_EN1) + #define CY_INT_SET_EN1_PTR ( (reg8 *) CYREG_INTC_SET_EN1) + + #define CY_INT_SET_EN2_REG (* (reg8 *) CYREG_INTC_SET_EN2) + #define CY_INT_SET_EN2_PTR ( (reg8 *) CYREG_INTC_SET_EN2) + + #define CY_INT_SET_EN3_REG (* (reg8 *) CYREG_INTC_SET_EN3) + #define CY_INT_SET_EN3_PTR ( (reg8 *) CYREG_INTC_SET_EN3) + + /* Interrupt Controller Clear Enable Registers */ + #define CY_INT_CLEAR_REG (* (reg8 *) CYREG_INTC_CLR_EN0) + #define CY_INT_CLEAR_PTR ( (reg8 *) CYREG_INTC_CLR_EN0) + + #define CY_INT_CLR_EN0_REG (* (reg8 *) CYREG_INTC_CLR_EN0) + #define CY_INT_CLR_EN0_PTR ( (reg8 *) CYREG_INTC_CLR_EN0) + + #define CY_INT_CLR_EN1_REG (* (reg8 *) CYREG_INTC_CLR_EN1) + #define CY_INT_CLR_EN1_PTR ( (reg8 *) CYREG_INTC_CLR_EN1) + + #define CY_INT_CLR_EN2_REG (* (reg8 *) CYREG_INTC_CLR_EN2) + #define CY_INT_CLR_EN2_PTR ( (reg8 *) CYREG_INTC_CLR_EN2) + + #define CY_INT_CLR_EN3_REG (* (reg8 *) CYREG_INTC_CLR_EN3) + #define CY_INT_CLR_EN3_PTR ( (reg8 *) CYREG_INTC_CLR_EN3) + + + /* Interrupt Controller Set Pend Registers */ + #define CY_INT_SET_PEND_REG (* (reg8 *) CYREG_INTC_SET_PD0) + #define CY_INT_SET_PEND_PTR ( (reg8 *) CYREG_INTC_SET_PD0) + + /* Interrupt Controller Clear Pend Registers */ + #define CY_INT_CLR_PEND_REG (* (reg8 *) CYREG_INTC_CLR_PD0) + #define CY_INT_CLR_PEND_PTR ( (reg8 *) CYREG_INTC_CLR_PD0) + + + /* Access Interrupt Controller Registers based on interrupt number */ + #define CY_INT_SET_EN_INDX_PTR(number) ((reg8 *) (CYREG_INTC_SET_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + #define CY_INT_CLR_EN_INDX_PTR(number) ((reg8 *) (CYREG_INTC_CLR_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + #define CY_INT_CLR_PEND_INDX_PTR(number) ((reg8 *) (CYREG_INTC_CLR_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + #define CY_INT_SET_PEND_INDX_PTR(number) ((reg8 *) (CYREG_INTC_SET_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Macro Name: CyAssert +****************************************************************************//** +* The macro that evaluates the expression and if it is false (evaluates to 0) +* then the processor is halted. +* +* This macro is evaluated unless NDEBUG is defined. +* +* If NDEBUG is defined, then no code is generated for this macro. NDEBUG is +* defined by default for a Release build setting and not defined for a Debug +* build setting. +* +* \param expr: Logical expression. Asserts if false. +* +*******************************************************************************/ +#if !defined(NDEBUG) + #define CYASSERT(x) { \ + if(!(x)) \ + { \ + CyHalt((uint8) 0u); \ + } \ + } +#else + #define CYASSERT(x) +#endif /* !defined(NDEBUG) */ + + +/* Reset register fields of RESET_SR0 (CyResetStatus) */ +#define CY_RESET_LVID (0x01u) +#define CY_RESET_LVIA (0x02u) +#define CY_RESET_HVIA (0x04u) +#define CY_RESET_WD (0x08u) +#define CY_RESET_SW (0x20u) +#define CY_RESET_GPIO0 (0x40u) +#define CY_RESET_GPIO1 (0x80u) + + +/* Interrupt Controller Configuration and Status Register */ +#if(CY_PSOC3) + #define INTERRUPT_CSR ((reg8 *) CYREG_INTC_CSR_EN) + #define DISABLE_IRQ_SET ((uint8)(0x01u << 1u)) /* INTC_CSR_EN */ + #define INTERRUPT_DISABLE_IRQ {*INTERRUPT_CSR |= DISABLE_IRQ_SET;} + #define INTERRUPT_ENABLE_IRQ {*INTERRUPT_CSR = (uint8)(~DISABLE_IRQ_SET);} +#endif /* (CY_PSOC3) */ + + +#if defined(__ARMCC_VERSION) + #define CyGlobalIntEnable {__enable_irq();} + #define CyGlobalIntDisable {__disable_irq();} +#elif defined(__GNUC__) || defined (__ICCARM__) + #define CyGlobalIntEnable {__asm("CPSIE i");} + #define CyGlobalIntDisable {__asm("CPSID i");} +#elif defined(__C51__) + #define CyGlobalIntEnable {\ + EA = 1u; \ + INTERRUPT_ENABLE_IRQ\ + } + + #define CyGlobalIntDisable {\ + INTERRUPT_DISABLE_IRQ; \ + CY_NOP; \ + EA = 0u;\ + } +#else + #error No compiler toolchain defined + #define CyGlobalIntEnable + #define CyGlobalIntDisable +#endif /* (__ARMCC_VERSION) */ + + +#ifdef CYREG_MLOGIC_CPU_SCR_CPU_SCR + #define CYDEV_HALT_CPU CY_SET_REG8(CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x01u) +#else + #define CYDEV_HALT_CPU CY_SET_REG8(CYREG_MLOGIC_CPU_SCR, 0x01u) +#endif /* (CYREG_MLOGIC_CPU_SCR_CPU_SCR) */ + + +#ifdef CYREG_MLOGIC_REV_ID_REV_ID + #define CYDEV_CHIP_REV_ACTUAL (CY_GET_REG8(CYREG_MLOGIC_REV_ID_REV_ID)) +#else + #define CYDEV_CHIP_REV_ACTUAL (CY_GET_REG8(CYREG_MLOGIC_REV_ID)) +#endif /* (CYREG_MLOGIC_REV_ID_REV_ID) */ + + +/******************************************************************************* +* System API constants +*******************************************************************************/ +#define CY_CACHE_CONTROL_FLUSH (0x0004u) +#define CY_LIB_RESET_CR2_RESET (0x01u) + +#if(CY_PSOC5) + /* System tick API constants */ + #define CY_SYS_SYST_CSR_ENABLE ((uint32) (0x01u)) + #define CY_SYS_SYST_CSR_ENABLE_INT ((uint32) (0x02u)) + #define CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT ((uint32) (0x02u)) + #define CY_SYS_SYST_CSR_COUNTFLAG_SHIFT ((uint32) (16u)) + #define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ((uint32) (1u)) + #define CY_SYS_SYST_CSR_CLK_SRC_LFCLK ((uint32) (0u)) + #define CY_SYS_SYST_RVR_CNT_MASK ((uint32) (0x00FFFFFFu)) + #define CY_SYS_SYST_CVR_CNT_MASK ((uint32) (0x00FFFFFFu)) + #define CY_SYS_SYST_NUM_OF_CALLBACKS ((uint32) (5u)) +#endif /* (CY_PSOC5) */ + + + +/******************************************************************************* +* Interrupt API constants +*******************************************************************************/ +#if(CY_PSOC5) + + #define CY_INT_IRQ_BASE (16u) + +#elif (CY_PSOC3) + + #define CY_INT_IRQ_BASE (0u) + +#endif /* (CY_PSOC5) */ + +/* Valid range of interrupt 0-31 */ +#define CY_INT_NUMBER_MAX (31u) + +/* Valid range of system interrupt 0-15 */ +#define CY_INT_SYS_NUMBER_MAX (15u) + +/* Valid range of system priority 0-7 */ +#define CY_INT_PRIORITY_MAX (7u) + +/* Mask to get valid range of interrupt 0-31 */ +#define CY_INT_NUMBER_MASK (0x1Fu) + +/* Mask to get valid range of system priority 0-7 */ +#define CY_INT_PRIORITY_MASK (0x7u) + +/* Mask to get valid range of system interrupt 0-15 */ +#define CY_INT_SYS_NUMBER_MASK (0xFu) + +#if(CY_PSOC5) + + /* CyIntSetSysVector()/CyIntGetSysVector() - parameter definitions */ + #define CY_INT_NMI_IRQN ( 2u) /* Non Maskable Interrupt */ + #define CY_INT_HARD_FAULT_IRQN ( 3u) /* Hard Fault Interrupt */ + #define CY_INT_MEM_MANAGE_IRQN ( 4u) /* Memory Management Interrupt */ + #define CY_INT_BUS_FAULT_IRQN ( 5u) /* Bus Fault Interrupt */ + #define CY_INT_USAGE_FAULT_IRQN ( 6u) /* Usage Fault Interrupt */ + #define CY_INT_SVCALL_IRQN (11u) /* SV Call Interrupt */ + #define CY_INT_DEBUG_MONITOR_IRQN (12u) /* Debug Monitor Interrupt */ + #define CY_INT_PEND_SV_IRQN (14u) /* Pend SV Interrupt */ + #define CY_INT_SYSTICK_IRQN (15u) /* System Tick Interrupt */ + +#endif /* (CY_PSOC5) */ + +/******************************************************************************* +* Interrupt Macros +*******************************************************************************/ + +#if(CY_PSOC5) + + /******************************************************************************* + * Macro Name: CyIntEnable + ****************************************************************************//** + * + * Enables the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number + * + *******************************************************************************/ + #define CyIntEnable(number) CY_SET_REG32(CY_INT_ENABLE_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + /******************************************************************************* + * Macro Name: CyIntDisable + ****************************************************************************//** + * + * Disables the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number. + * + *******************************************************************************/ + #define CyIntDisable(number) CY_SET_REG32(CY_INT_CLEAR_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntSetPending + ****************************************************************************//** + * + * Forces the specified interrupt number to be pending. + * + * \param number: Valid range [0-31]. Interrupt number. + * + *******************************************************************************/ + #define CyIntSetPending(number) CY_SET_REG32(CY_INT_SET_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntClearPending + ****************************************************************************//** + * + * Clears any pending interrupt for the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number. + * + *******************************************************************************/ + #define CyIntClearPending(number) CY_SET_REG32(CY_INT_CLR_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + +#else /* PSoC3 */ + + + /******************************************************************************* + * Macro Name: CyIntEnable + ****************************************************************************//** + * + * Enables the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number + * + *******************************************************************************/ + #define CyIntEnable(number) CY_SET_REG8(CY_INT_SET_EN_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntDisable + ****************************************************************************//** + * + * Disables the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number. + * + *******************************************************************************/ + #define CyIntDisable(number) CY_SET_REG8(CY_INT_CLR_EN_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntSetPending + ****************************************************************************//** + * + * Forces the specified interrupt number to be pending. + * + * \param number: Valid range [0-31]. Interrupt number. + * + *******************************************************************************/ + #define CyIntSetPending(number) CY_SET_REG8(CY_INT_SET_PEND_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntClearPending + ****************************************************************************//** + * Clears any pending interrupt for the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number. + * + *******************************************************************************/ + #define CyIntClearPending(number) CY_SET_REG8(CY_INT_CLR_PEND_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ + +#define CYGlobalIntEnable CyGlobalIntEnable +#define CYGlobalIntDisable CyGlobalIntDisable + +#define cymemset(s,c,n) memset((s),(c),(n)) +#define cymemcpy(d,s,n) memcpy((d),(s),(n)) + +#define MFGCFG_X32_TR_PTR (CY_CLK_XTAL32_TR_PTR) +#define MFGCFG_X32_TR (CY_CLK_XTAL32_TR_REG) +#define SLOWCLK_X32_TST_PTR (CY_CLK_XTAL32_TST_PTR) +#define SLOWCLK_X32_TST (CY_CLK_XTAL32_TST_REG) +#define SLOWCLK_X32_CR_PTR (CY_CLK_XTAL32_CR_PTR) +#define SLOWCLK_X32_CR (CY_CLK_XTAL32_CR_REG) +#define SLOWCLK_X32_CFG_PTR (CY_CLK_XTAL32_CFG_PTR) +#define SLOWCLK_X32_CFG (CY_CLK_XTAL32_CFG_REG) + +#define X32_CONTROL_ANA_STAT (CY_CLK_XTAL32_CR_ANA_STAT) +#define X32_CONTROL_DIG_STAT (0x10u) +#define X32_CONTROL_LPM (CY_CLK_XTAL32_CR_LPM) +#define X32_CONTROL_LPM_POSITION (1u) +#define X32_CONTROL_X32EN (CY_CLK_XTAL32_CR_EN) +#define X32_CONTROL_PDBEN (CY_CLK_XTAL32_CR_PDBEN) +#define X32_TR_DPMODE (CY_CLK_XTAL32_TR_STARTUP) +#define X32_TR_CLEAR (CY_CLK_XTAL32_TR_POWERDOWN) +#define X32_TR_HPMODE (CY_CLK_XTAL32_TR_HIGH_POWER) +#define X32_TR_LPMODE (CY_CLK_XTAL32_TR_LOW_POWER) +#define X32_TST_SETALL (CY_CLK_XTAL32_TST_DEFAULT) +#define X32_CFG_LP_BITS_MASK (CY_CLK_XTAL32_CFG_LP_MASK) +#define X32_CFG_LP_DEFAULT (CY_CLK_XTAL32_CFG_LP_DEFAULT) +#define X32_CFG_LOWPOWERMODE (0x80u) +#define X32_CFG_LP_LOWPOWER (0x8u) +#define CY_X32_HIGHPOWER_MODE (0u) +#define CY_X32_LOWPOWER_MODE (1u) +#define CY_XTAL32K_DIG_STAT (0x10u) +#define CY_XTAL32K_STAT_FIELDS (0x30u) +#define CY_XTAL32K_DIG_STAT_UNSTABLE (0u) +#define CY_XTAL32K_ANA_STAT_UNSTABLE (0x0u) +#define CY_XTAL32K_STATUS (0x20u) + +#define FASTCLK_XMHZ_CSR_PTR (CY_CLK_XMHZ_CSR_PTR) +#define FASTCLK_XMHZ_CSR (CY_CLK_XMHZ_CSR_REG) +#define FASTCLK_XMHZ_CFG0_PTR (CY_CLK_XMHZ_CFG0_PTR) +#define FASTCLK_XMHZ_CFG0 (CY_CLK_XMHZ_CFG0_REG) +#define FASTCLK_XMHZ_CFG1_PTR (CY_CLK_XMHZ_CFG1_PTR) +#define FASTCLK_XMHZ_CFG1 (CY_CLK_XMHZ_CFG1_REG) +#define FASTCLK_XMHZ_GAINMASK (CY_CLK_XMHZ_CFG0_XCFG_MASK) +#define FASTCLK_XMHZ_VREFMASK (CY_CLK_XMHZ_CFG1_VREF_FB_MASK) +#define FASTCLK_XMHZ_VREF_WD_MASK (CY_CLK_XMHZ_CFG1_VREF_WD_MASK) +#define XMHZ_CONTROL_ENABLE (CY_CLK_XMHZ_CSR_ENABLE) +#define X32_CONTROL_XERR_MASK (CY_CLK_XMHZ_CSR_XERR) +#define X32_CONTROL_XERR_DIS (CY_CLK_XMHZ_CSR_XFB) +#define X32_CONTROL_XERR_POSITION (7u) +#define X32_CONTROL_FAULT_RECOVER (CY_CLK_XMHZ_CSR_XPROT) + +#define CYWDT_CFG (CY_WDT_CFG_PTR) +#define CYWDT_CR (CY_WDT_CR_PTR) + +#define CYWDT_TICKS_MASK (CY_WDT_CFG_INTERVAL_MASK) +#define CYWDT_RESET (CY_WDT_CFG_CTW_RESET) +#define CYWDT_LPMODE_SHIFT (CY_WDT_CFG_LPMODE_SHIFT) +#define CYWDT_LPMODE_MASK (CY_WDT_CFG_LPMODE_MASK) +#define CYWDT_ENABLE_BIT (CY_WDT_CFG_WDR_EN) + +#define FASTCLK_PLL_CFG0_PTR (CY_CLK_PLL_CFG0_PTR) +#define FASTCLK_PLL_CFG0 (CY_CLK_PLL_CFG0_REG) +#define FASTCLK_PLL_SR_PTR (CY_CLK_PLL_SR_PTR) +#define FASTCLK_PLL_SR (CY_CLK_PLL_SR_REG) + +#define MAX_FASTCLK_PLL_Q_VALUE (CY_CLK_PLL_MAX_Q_VALUE) +#define MIN_FASTCLK_PLL_Q_VALUE (CY_CLK_PLL_MIN_Q_VALUE) +#define MIN_FASTCLK_PLL_P_VALUE (CY_CLK_PLL_MIN_P_VALUE) +#define MIN_FASTCLK_PLL_CUR_VALUE (CY_CLK_PLL_MIN_CUR_VALUE) +#define MAX_FASTCLK_PLL_CUR_VALUE (CY_CLK_PLL_MAX_CUR_VALUE) + +#define PLL_CONTROL_ENABLE (CY_CLK_PLL_ENABLE) +#define PLL_STATUS_LOCK (CY_CLK_PLL_LOCK_STATUS) +#define PLL_STATUS_ENABLED (CY_CLK_PLL_ENABLE) +#define PLL_CURRENT_POSITION (CY_CLK_PLL_CURRENT_POSITION) +#define PLL_VCO_GAIN_2 (2u) + +#define FASTCLK_PLL_Q_PTR (CY_CLK_PLL_Q_PTR) +#define FASTCLK_PLL_Q (CY_CLK_PLL_Q_REG) +#define FASTCLK_PLL_P_PTR (CY_CLK_PLL_P_PTR) +#define FASTCLK_PLL_P (CY_CLK_PLL_P_REG) +#define FASTCLK_PLL_CFG1_PTR (CY_CLK_PLL_CFG1_REG) +#define FASTCLK_PLL_CFG1 (CY_CLK_PLL_CFG1_REG) + +#define CY_VD_PRESISTENT_STATUS_REG (CY_VD_PERSISTENT_STATUS_REG) +#define CY_VD_PRESISTENT_STATUS_PTR (CY_VD_PERSISTENT_STATUS_PTR) + + +#if(CY_PSOC5) + + #define CYINT_IRQ_BASE (CY_INT_IRQ_BASE) + + #define CYINT_VECT_TABLE (CY_INT_VECT_TABLE) + #define CYINT_PRIORITY (CY_INT_PRIORITY_PTR) + #define CYINT_ENABLE (CY_INT_ENABLE_PTR) + #define CYINT_CLEAR (CY_INT_CLEAR_PTR) + #define CYINT_SET_PEND (CY_INT_SET_PEND_PTR) + #define CYINT_CLR_PEND (CY_INT_CLR_PEND_PTR) + #define CACHE_CC_CTL (CY_CACHE_CONTROL_PTR) + +#elif (CY_PSOC3) + + #define CYINT_IRQ_BASE (CY_INT_IRQ_BASE) + + #define CYINT_VECT_TABLE (CY_INT_VECT_TABLE) + #define CYINT_PRIORITY (CY_INT_PRIORITY_PTR) + #define CYINT_ENABLE (CY_INT_ENABLE_PTR) + #define CYINT_CLEAR (CY_INT_CLEAR_PTR) + #define CYINT_SET_PEND (CY_INT_SET_PEND_PTR) + #define CYINT_CLR_PEND (CY_INT_CLR_PEND_PTR) + +#endif /* (CY_PSOC5) */ + + + +#define BUS_AMASK_CLEAR (0xF0u) +#define BUS_DMASK_CLEAR (0x00u) +#define CLKDIST_LD_LOAD_SET (0x01u) +#define CLKDIST_WRK0_MASK_SET (0x80u) /* Enable shadow loads */ +#define MASTERCLK_DIVIDER_VALUE (7u) +#define CLKDIST_BCFG2_SSS_SET (0x40u) /* Sync source is same frequency */ +#define MASTER_CLK_SRC_CLEAR (0xFCu) +#define IMO_DOUBLER_ENABLE (0x10u) +#define CLOCK_IMO_IMO (0x20u) +#define CLOCK_IMO2X_XTAL (0x40u) +#define CLOCK_IMO_RANGE_CLEAR (0xF8u) +#define CLOCK_CONTROL_DIST_MASK (0xFCu) + + +#define CLKDIST_AMASK (*(reg8 *) CYREG_CLKDIST_AMASK) +#define CLKDIST_AMASK_PTR ( (reg8 *) CYREG_CLKDIST_AMASK) +#define CLKDIST_DMASK_PTR ( (reg8 *) CYREG_CLKDIST_DMASK) +#define CLKDIST_DMASK (*(reg8 *) CYREG_CLKDIST_DMASK) +#define CLKDIST_BCFG2_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2) +#define CLKDIST_BCFG2 (*(reg8 *) CYREG_CLKDIST_BCFG2) +#define CLKDIST_WRK0_PTR ( (reg8 *) CYREG_CLKDIST_WRK0) +#define CLKDIST_WRK0 (*(reg8 *) CYREG_CLKDIST_WRK0) +#define CLKDIST_LD_PTR ( (reg8 *) CYREG_CLKDIST_LD) +#define CLKDIST_LD (*(reg8 *) CYREG_CLKDIST_LD) +#define CLKDIST_BCFG0_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0) +#define CLKDIST_BCFG0 (*(reg8 *) CYREG_CLKDIST_BCFG0) +#define CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0) +#define CLKDIST_MSTR0 (*(reg8 *) CYREG_CLKDIST_MSTR0) +#define FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR) +#define FASTCLK_IMO_CR (*(reg8 *) CYREG_FASTCLK_IMO_CR) +#define CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR) +#define CLKDIST_CR (*(reg8 *) CYREG_CLKDIST_CR) + + +#define IMO_PM_ENABLE (0x10u) +#define PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0) +#define PM_ACT_CFG0 (*(reg8 *) CYREG_PM_ACT_CFG0) +#define SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0) +#define SLOWCLK_ILO_CR0 (*(reg8 *) CYREG_SLOWCLK_ILO_CR0) +#define ILO_CONTROL_PD_MODE (0x10u) +#define ILO_CONTROL_PD_POSITION (4u) +#define ILO_CONTROL_1KHZ_ON (0x02u) +#define ILO_CONTROL_100KHZ_ON (0x04u) +#define ILO_CONTROL_33KHZ_ON (0x20u) +#define PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0) +#define PM_TW_CFG0 (*(reg8 *) CYREG_PM_TW_CFG0) +#define PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2) +#define PM_TW_CFG2 (*(reg8 *) CYREG_PM_TW_CFG2) +#define RESET_CR2 ((reg8 *) CYREG_RESET_CR2) +#define FASTCLK_IMO_USBCLK_ON_SET (0x40u) +#define CLOCK_IMO_3MHZ_VALUE (0x03u) +#define CLOCK_IMO_6MHZ_VALUE (0x01u) +#define CLOCK_IMO_12MHZ_VALUE (0x00u) +#define CLOCK_IMO_24MHZ_VALUE (0x02u) +#define CLOCK_IMO_48MHZ_VALUE (0x04u) +#define CLOCK_IMO_62MHZ_VALUE (0x05u) +#define CLOCK_IMO_74MHZ_VALUE (0x06u) +#define CLKDIST_DIV_POSITION (4u) +#define CLKDIST_MSTR1_DIV_CLEAR (0x0Fu) +#define SFR_USER_CPUCLK_DIV_MASK (0x0Fu) +#define CLOCK_USB_ENABLE (0x02u) +#define CLOCK_IMO_OUT_X2 (0x10u) +#define CLOCK_IMO_OUT_X1 ((uint8)(~CLOCK_IMO_OUT_X2)) +#define CLOCK_IMO2X_ECO ((uint8)(~CLOCK_IMO2X_DSI)) +#define USB_CLKDIST_CONFIG_MASK (0x03u) +#define USB_CLK_IMO2X (0x00u) +#define USB_CLK_IMO (0x01u) +#define USB_CLK_PLL (0x02u) +#define USB_CLK_DSI (0x03u) +#define USB_CLK_DIV2_ON (0x04u) +#define USB_CLK_STOP_FLAG (0x00u) +#define USB_CLK_START_FLAG (0x01u) +#define FTW_CLEAR_ALL_BITS (0x00u) +#define FTW_CLEAR_FTW_BITS (0xFCu) +#define FTW_ENABLE (0x01u) +#define PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0) +#define PM_STBY_CFG0 (*(reg8 *) CYREG_PM_STBY_CFG0) +#define PM_AVAIL_CR2_PTR ( (reg8 *) CYREG_PM_AVAIL_CR2) +#define PM_AVAIL_CR2 (*(reg8 *) CYREG_PM_AVAIL_CR2) +#define CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) +#define CLKDIST_UCFG (*(reg8 *) CYREG_CLKDIST_UCFG) +#define CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1) +#define CLKDIST_MSTR1 (*(reg8 *) CYREG_CLKDIST_MSTR1) +#define SFR_USER_CPUCLK_DIV_PTR ((void far *) CYREG_SFR_USER_CPUCLK_DIV) +#define IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1) +#define IMO_TR1 (*(reg8 *) CYREG_IMO_TR1) +#define CLOCK_CONTROL ( (reg8 *) CYREG_CLKDIST_CR) +#define CY_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 ) +#define CY_USB_CR1 (*(reg8 *) CYREG_USB_CR1 ) +#define USB_CLKDIST_CONFIG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) +#define USB_CLKDIST_CONFIG (*(reg8 *) CYREG_CLKDIST_UCFG) +#define CY_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 ) +#define CY_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 ) +#define CY_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 ) +#define CY_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 ) +#if(CY_PSOC3) + #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define FLSHID_CUST_TABLES_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define FLSHID_MFG_CFG_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) + #else + #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define FLSHID_CUST_TABLES_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define FLSHID_MFG_CFG_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) +#endif /* (CY_PSOC3) */ + + +#endif /* (CY_BOOT_CYLIB_H) */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/CySpc.c b/source/hic_hal/cypress/psoc5lp/PSoC5/CySpc.c new file mode 100644 index 0000000000..3f39fb9ff8 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/CySpc.c @@ -0,0 +1,762 @@ +/***************************************************************************//** +* \file CySpc.c +* \version 5.70 +* +* \brief Provides an API for the System Performance Component. +* The SPC functions are not meant to be called directly by the user +* application. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "CySpc.h" + +#define CY_SPC_KEY_ONE (0xB6u) +#define CY_SPC_KEY_TWO(x) ((uint8) (((uint16) 0xD3u) + ((uint16) (x)))) + +/* Command Codes */ +#define CY_SPC_CMD_LD_BYTE (0x00u) +#define CY_SPC_CMD_LD_MULTI_BYTE (0x01u) +#define CY_SPC_CMD_LD_ROW (0x02u) +#define CY_SPC_CMD_RD_BYTE (0x03u) +#define CY_SPC_CMD_RD_MULTI_BYTE (0x04u) +#define CY_SPC_CMD_WR_ROW (0x05u) +#define CY_SPC_CMD_WR_USER_NVL (0x06u) +#define CY_SPC_CMD_PRG_ROW (0x07u) +#define CY_SPC_CMD_ER_SECTOR (0x08u) +#define CY_SPC_CMD_ER_ALL (0x09u) +#define CY_SPC_CMD_RD_HIDDEN (0x0Au) +#define CY_SPC_CMD_PRG_PROTECT (0x0Bu) +#define CY_SPC_CMD_CHECKSUM (0x0Cu) +#define CY_SPC_CMD_DWNLD_ALGORITHM (0x0Du) +#define CY_SPC_CMD_GET_TEMP (0x0Eu) +#define CY_SPC_CMD_GET_ADC (0x0Fu) +#define CY_SPC_CMD_RD_NVL_VOLATILE (0x10u) +#define CY_SPC_CMD_SETUP_TS (0x11u) +#define CY_SPC_CMD_DISABLE_TS (0x12u) +#define CY_SPC_CMD_ER_ROW (0x13u) + +/* Enable bit in Active and Alternate Active mode templates */ +#define PM_SPC_PM_EN (0x08u) + +/* Gate calls to the SPC. */ +uint8 SpcLockState = CY_SPC_UNLOCKED; + + +#if(CY_PSOC5) + + /*************************************************************************** + * The wait-state pipeline must be enabled prior to accessing the SPC + * register interface regardless of CPU frequency. The CySpcLock() saves + * current wait-state pipeline state and enables it. The CySpcUnlock() + * function, which must be called after SPC transaction, restores original + * state. + ***************************************************************************/ + static uint32 spcWaitPipeBypass = 0u; + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Function Name: CySpcStart +****************************************************************************//** +* Starts the SPC. +* +*******************************************************************************/ +void CySpcStart(void) +{ + /* Save current global interrupt enable and disable it */ + uint8 interruptState = CyEnterCriticalSection(); + + CY_SPC_PM_ACT_REG |= PM_SPC_PM_EN; + CY_SPC_PM_STBY_REG |= PM_SPC_PM_EN; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySpcStop +****************************************************************************//** +* Stops the SPC. +* +*******************************************************************************/ +void CySpcStop(void) +{ + /* Save current global interrupt enable and disable it */ + uint8 interruptState = CyEnterCriticalSection(); + + CY_SPC_PM_ACT_REG &= ((uint8)(~PM_SPC_PM_EN)); + CY_SPC_PM_STBY_REG &= ((uint8)(~PM_SPC_PM_EN)); + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySpcReadData +****************************************************************************//** +* Reads data from the SPC. +* +* \param uint8 buffer: +* Address to store data read. +* +* \param uint8 size: +* Number of bytes to read from the SPC. +* +* \return +* uint8: +* The number of bytes read from the SPC. +* +*******************************************************************************/ +uint8 CySpcReadData(uint8 buffer[], uint8 size) +{ + uint8 i; + + for(i = 0u; i < size; i++) + { + while(!CY_SPC_DATA_READY) + { + CyDelayUs(1u); + } + buffer[i] = CY_SPC_CPU_DATA_REG; + } + + return(i); +} + + +/******************************************************************************* +* Function Name: CySpcLoadMultiByte +****************************************************************************//** +* Loads 1 to 32 bytes of data into the row latch of a Flash/EEPROM array. +* +* \param uint8 array: +* Id of the array. +* +* \param uint16 address: +* Flash/eeprom addrress +* +* \param uint8* buffer: +* Data to load to the row latch +* +* \param uint16 number: +* Number bytes to load. +* +* \return +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* CYRET_BAD_PARAM +* +*******************************************************************************/ +cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\ + +{ + cystatus status = CYRET_STARTED; + uint8 i; + + /*************************************************************************** + * Check if number is correct for array. Number must be less than + * 32 for Flash or less than 16 for EEPROM. + ***************************************************************************/ + if(((array < CY_SPC_LAST_FLASH_ARRAYID) && (size < 32u)) || + ((array > CY_SPC_LAST_FLASH_ARRAYID) && (size < 16u))) + { + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_MULTI_BYTE); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_MULTI_BYTE; + + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = 1u & HI8(address); + CY_SPC_CPU_DATA_REG = LO8(address); + CY_SPC_CPU_DATA_REG = ((uint8)(size - 1u)); + + for(i = 0u; i < size; i++) + { + CY_SPC_CPU_DATA_REG = buffer[i]; + } + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcLoadRow +****************************************************************************//** +* Loads a row of data into the row latch of a Flash/EEPROM array. +* +* The buffer pointer should point to the data that should be written to the +* flash row directly (no data in ECC/flash will be preserved). It is Flash API +* responsibility to prepare data: the preserved data are copied from flash into +* array with the modified data. +* +* \param uint8 array: +* Id of the array. +* +* \param uint8* buffer: +* Data to be loaded to the row latch +* +* \param uint8 size: +* The number of data bytes that the SPC expects to be written. Depends on the +* type of the array and, if the array is Flash, whether ECC is being enabled +* or not. There are following values: flash row latch size with ECC enabled, +* flash row latch size with ECC disabled and EEPROM row latch size. +* +* \return +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size) +{ + cystatus status = CYRET_STARTED; + uint16 i; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + + for(i = 0u; i < size; i++) + { + CY_SPC_CPU_DATA_REG = buffer[i]; + } + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcLoadRowFull +****************************************************************************//** +* Loads a row of data into the row latch of a Flash/EEPROM array. +* +* The only data that are going to be changed should be passed. The function +* will handle unmodified data preservation based on DWR settings and input +* parameters. +* +* \param uint8 array: +* Id of the array. +* +* \param uint16 row: +* Flash row number to be loaded. +* +* \param uint8* buffer: +* Data to be loaded to the row latch +* +* \param uint8 size: +* The number of data bytes that the SPC expects to be written. Depends on the +* type of the array and, if the array is Flash, whether ECC is being enabled +* or not. There are following values: flash row latch size with ECC enabled, +* flash row latch size with ECC disabled and EEPROM row latch size. +* +* \return +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\ + +{ + cystatus status = CYRET_STARTED; + uint16 i; + + #if (CYDEV_ECC_ENABLE == 0) + uint32 offset; + #endif /* (CYDEV_ECC_ENABLE == 0) */ + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + + /******************************************************************* + * If "Enable Error Correcting Code (ECC)" and "Store Configuration + * Data in ECC" DWR options are disabled, ECC section is available + * for user data. + *******************************************************************/ + #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) + + /******************************************************************* + * If size parameter equals size of the ECC row and selected array + * identification corresponds to the flash array (but not to EEPROM + * array) then data are going to be written to the ECC section. + * In this case flash data must be preserved. The flash data copied + * from flash data section to the SPC data register. + *******************************************************************/ + if ((size == CYDEV_ECC_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID)) + { + offset = CYDEV_FLS_BASE + + ((uint32) array * CYDEV_FLS_SECTOR_SIZE) + + ((uint32) row * CYDEV_FLS_ROW_SIZE ); + + for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++) + { + CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i)); + } + } + + #endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ + + + for(i = 0u; i < size; i++) + { + CY_SPC_CPU_DATA_REG = buffer[i]; + } + + + /******************************************************************* + * If "Enable Error Correcting Code (ECC)" DWR option is disabled, + * ECC section can be used for storing device configuration data + * ("Store Configuration Data in ECC" DWR option is enabled) or for + * storing user data in the ECC section ("Store Configuration Data in + * ECC" DWR option is enabled). In both cases, the data in the ECC + * section must be preserved if flash data is written. + *******************************************************************/ + #if (CYDEV_ECC_ENABLE == 0) + + + /******************************************************************* + * If size parameter equals size of the flash row and selected array + * identification corresponds to the flash array (but not to EEPROM + * array) then data are going to be written to the flash data + * section. In this case, ECC section data must be preserved. + * The ECC section data copied from ECC section to the SPC data + * register. + *******************************************************************/ + if ((size == CYDEV_FLS_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID)) + { + offset = CYDEV_ECC_BASE + + ((uint32) array * CYDEV_ECC_SECTOR_SIZE) + + ((uint32) row * CYDEV_ECC_ROW_SIZE ); + + for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++) + { + CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i)); + } + } + + #else + + if(0u != row) + { + /* To remove unreferenced local variable warning */ + } + + #endif /* (CYDEV_ECC_ENABLE == 0) */ + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcWriteRow +****************************************************************************//** +* Erases then programs a row in Flash/EEPROM with data in row latch. +* +* \param uint8 array: +* Id of the array. +* +* \param uint16 address: +* flash/eeprom addrress +* +* \param uint8 tempPolarity: +* temperature polarity. +* \param 1: the Temp Magnitude is interpreted as a positive value +* \param 0: the Temp Magnitude is interpreted as a negative value +* +* \param uint8 tempMagnitude: +* temperature magnitude. +* +* \return +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\ + +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_WR_ROW); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_WR_ROW; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = HI8(address); + CY_SPC_CPU_DATA_REG = LO8(address); + CY_SPC_CPU_DATA_REG = tempPolarity; + CY_SPC_CPU_DATA_REG = tempMagnitude; + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcEraseSector +****************************************************************************//** +* Erases all data in the addressed sector (block of 64 rows). +* +* \param uint8 array: +* Id of the array. +* +* \param uint8 sectorNumber: +* Zero based sector number within Flash/EEPROM array +* +* \return +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber) +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_ER_SECTOR); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_ER_SECTOR; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = sectorNumber; + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcEraseRow +****************************************************************************//** +* Erases a row in Flash. +* +* \param uint8 array: +* Id of the array. +* +* \param uint16 address: +* Flash address +* +* \param uint8 tempPolarity: +* temperature polarity. +* \param 1: the Temp Magnitude is interpreted as a positive value +* \param 0: the Temp Magnitude is interpreted as a negative value +* +* \param uint8 tempMagnitude: +* temperature magnitude. +* +* \return +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcEraseRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\ + +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_ER_ROW); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_ER_ROW; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = HI8(address); + CY_SPC_CPU_DATA_REG = LO8(address); + CY_SPC_CPU_DATA_REG = tempPolarity; + CY_SPC_CPU_DATA_REG = tempMagnitude; + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcGetTemp +****************************************************************************//** +* Returns the internal die temperature +* +* \param uint8 numSamples: +* Number of samples. Valid values are 1-5, resulting in 2 - 32 samples +* respectively. +* +* \param uint16 timerPeriod: +* Number of ADC ACLK cycles. A valid 14 bit value is accepted, higher 2 bits +* of 16 bit values are ignored. +* +* \param uint8 clkDivSelect: +* ADC ACLK clock divide value. Valid values are 2 - 225. +* +* \return +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcGetTemp(uint8 numSamples) +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_GET_TEMP); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_GET_TEMP; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = numSamples; + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcLock +****************************************************************************//** +* Locks the SPC so it can not be used by someone else: +* - Saves wait-pipeline enable state and enable pipeline (PSoC5) +* +* \return +* CYRET_SUCCESS - if the resource was free. +* CYRET_LOCKED - if the SPC is in use. +* +*******************************************************************************/ +cystatus CySpcLock(void) +{ + cystatus status = CYRET_LOCKED; + uint8 interruptState; + + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + if(CY_SPC_UNLOCKED == SpcLockState) + { + SpcLockState = CY_SPC_LOCKED; + status = CYRET_SUCCESS; + + #if(CY_PSOC5) + + if(0u != (CY_SPC_CPU_WAITPIPE_REG & CY_SPC_CPU_WAITPIPE_BYPASS)) + { + /* Enable pipeline registers */ + CY_SPC_CPU_WAITPIPE_REG &= ((uint32)(~CY_SPC_CPU_WAITPIPE_BYPASS)); + + /* At least 2 NOP instructions are recommended */ + CY_NOP; + CY_NOP; + CY_NOP; + + spcWaitPipeBypass = CY_SPC_CPU_WAITPIPE_BYPASS; + } + + #endif /* (CY_PSOC5) */ + } + + /* Exit critical section */ + CyExitCriticalSection(interruptState); + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcUnlock +****************************************************************************//** +* Unlocks the SPC so it can be used by someone else: +* - Restores wait-pipeline enable state (PSoC5) +* +*******************************************************************************/ +void CySpcUnlock(void) +{ + uint8 interruptState; + + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + /* Release the SPC object */ + SpcLockState = CY_SPC_UNLOCKED; + + #if(CY_PSOC5) + + if(CY_SPC_CPU_WAITPIPE_BYPASS == spcWaitPipeBypass) + { + /* Force to bypass pipeline registers */ + CY_SPC_CPU_WAITPIPE_REG |= CY_SPC_CPU_WAITPIPE_BYPASS; + + /* At least 2 NOP instructions are recommended */ + CY_NOP; + CY_NOP; + CY_NOP; + + spcWaitPipeBypass = 0u; + } + + #endif /* (CY_PSOC5) */ + + /* Exit critical section */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySpcGetAlgorithm +****************************************************************************//** +* Downloads SPC algorithm from SPC SROM into SRAM. +* +* \return +* CYRET_STARTED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcGetAlgorithm(void) +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_DWNLD_ALGORITHM); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_DWNLD_ALGORITHM; + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + +/* [] END OF FILE */ + diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/CySpc.h b/source/hic_hal/cypress/psoc5lp/PSoC5/CySpc.h new file mode 100644 index 0000000000..201d4e0340 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/CySpc.h @@ -0,0 +1,179 @@ +/***************************************************************************//** +* \file CySpc.c +* \version 5.70 +* +* \brief Provides definitions for the System Performance Component API. +* The SPC functions are not meant to be called directly by the user +* application. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_BOOT_CYSPC_H) +#define CY_BOOT_CYSPC_H + +#include "cytypes.h" +#include "CyLib.h" +#include "cydevice_trm.h" + + +/*************************************** +* Global Variables +***************************************/ +extern uint8 SpcLockState; + + +/*************************************** +* Function Prototypes +***************************************/ +void CySpcStart(void); +void CySpcStop(void); +uint8 CySpcReadData(uint8 buffer[], uint8 size); +cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\ +; +cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size); +cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\ +; +cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\ +; +cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber); +cystatus CySpcEraseRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\ +; +cystatus CySpcGetTemp(uint8 numSamples); +cystatus CySpcGetAlgorithm(void); +cystatus CySpcLock(void); +void CySpcUnlock(void); + + +/*************************************** +* API Constants +***************************************/ + +#define CY_SPC_LOCKED (0x01u) +#define CY_SPC_UNLOCKED (0x00u) + +/******************************************************************************* +* The Array ID indicates the unique ID of the SONOS array being accessed: +* - 0x00-0x3E : Flash Arrays +* - 0x3F : Selects all Flash arrays simultaneously +* - 0x40-0x7F : Embedded EEPROM Arrays +*******************************************************************************/ +#define CY_SPC_FIRST_FLASH_ARRAYID (0x00u) +#define CY_SPC_LAST_FLASH_ARRAYID (0x3Fu) +#define CY_SPC_FIRST_EE_ARRAYID (0x40u) +#define CY_SPC_LAST_EE_ARRAYID (0x7Fu) + + +#define CY_SPC_STATUS_DATA_READY_MASK (0x01u) +#define CY_SPC_STATUS_IDLE_MASK (0x02u) +#define CY_SPC_STATUS_CODE_MASK (0xFCu) +#define CY_SPC_STATUS_CODE_SHIFT (0x02u) + +/* Status codes for SPC. */ +#define CY_SPC_STATUS_SUCCESS (0x00u) /* Operation Successful */ +#define CY_SPC_STATUS_INVALID_ARRAY_ID (0x01u) /* Invalid Array ID for given command */ +#define CY_SPC_STATUS_INVALID_2BYTEKEY (0x02u) /* Invalid 2-byte key */ +#define CY_SPC_STATUS_ARRAY_ASLEEP (0x03u) /* Addressed Array is Asleep */ +#define CY_SPC_STATUS_EXTERN_ACCESS (0x04u) /* External Access Failure (SPC is not in external access mode) */ +#define CY_SPC_STATUS_INVALID_NUMBER (0x05u) /* Invalid 'N' Value for given command */ +#define CY_SPC_STATUS_TEST_MODE (0x06u) /* Test Mode Failure (SPC is not in test mode) */ +#define CY_SPC_STATUS_ALG_CSUM (0x07u) /* Smart Write Algorithm Checksum Failure */ +#define CY_SPC_STATUS_PARAM_CSUM (0x08u) /* Smart Write Parameter Checksum Failure */ +#define CY_SPC_STATUS_PROTECTION (0x09u) /* Protection Check Failure */ +#define CY_SPC_STATUS_ADDRESS_PARAM (0x0Au) /* Invalid Address parameter for the given command */ +#define CY_SPC_STATUS_COMMAND_CODE (0x0Bu) /* Invalid Command Code */ +#define CY_SPC_STATUS_ROW_ID (0x0Cu) /* Invalid Row ID parameter for given command */ +#define CY_SPC_STATUS_TADC_INPUT (0x0Du) /* Invalid input value for Get Temp & Get ADC commands */ +#define CY_SPC_STATUS_BUSY (0xFFu) /* SPC is busy */ + +#if(CY_PSOC5) + + /* Wait-state pipeline */ + #define CY_SPC_CPU_WAITPIPE_BYPASS ((uint32)0x01u) + +#endif /* (CY_PSOC5) */ + + +/*************************************** +* Registers +***************************************/ + +/* SPC CPU Data Register */ +#define CY_SPC_CPU_DATA_REG (* (reg8 *) CYREG_SPC_CPU_DATA ) +#define CY_SPC_CPU_DATA_PTR ( (reg8 *) CYREG_SPC_CPU_DATA ) + +/* SPC Status Register */ +#define CY_SPC_STATUS_REG (* (reg8 *) CYREG_SPC_SR ) +#define CY_SPC_STATUS_PTR ( (reg8 *) CYREG_SPC_SR ) + +/* Active Power Mode Configuration Register 0 */ +#define CY_SPC_PM_ACT_REG (* (reg8 *) CYREG_PM_ACT_CFG0 ) +#define CY_SPC_PM_ACT_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 ) + +/* Standby Power Mode Configuration Register 0 */ +#define CY_SPC_PM_STBY_REG (* (reg8 *) CYREG_PM_STBY_CFG0 ) +#define CY_SPC_PM_STBY_PTR ( (reg8 *) CYREG_PM_STBY_CFG0 ) + +#if(CY_PSOC5) + + /* Wait State Pipeline */ + #define CY_SPC_CPU_WAITPIPE_REG (* (reg32 *) CYREG_PANTHER_WAITPIPE ) + #define CY_SPC_CPU_WAITPIPE_PTR ( (reg32 *) CYREG_PANTHER_WAITPIPE ) + +#endif /* (CY_PSOC5) */ + + +/*************************************** +* Macros +***************************************/ +#define CY_SPC_IDLE (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK)) +#define CY_SPC_BUSY (0u == (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK)) +#define CY_SPC_DATA_READY (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_DATA_READY_MASK)) + +/* SPC must be in idle state in order to obtain correct status */ +#define CY_SPC_READ_STATUS (CY_SPC_IDLE ? \ + ((uint8)(CY_SPC_STATUS_REG >> CY_SPC_STATUS_CODE_SHIFT)) : \ + ((uint8) CY_SPC_STATUS_BUSY)) + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define FIRST_FLASH_ARRAYID (CY_SPC_FIRST_FLASH_ARRAYID) +#define LAST_FLASH_ARRAYID (CY_SPC_LAST_FLASH_ARRAYID) +#define FIRST_EE_ARRAYID (CY_SPC_FIRST_EE_ARRAYID) +#define LAST_EE_ARRAYID (CY_SPC_LAST_EE_ARRAYID) +#define SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE) +#define SIZEOF_FLASH_ROW (CYDEV_FLS_ROW_SIZE) +#define SIZEOF_EEPROM_ROW (CYDEV_EEPROM_ROW_SIZE) + + +#endif /* (CY_BOOT_CYSPC_H) */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/EEPROM_ModeStorage.c b/source/hic_hal/cypress/psoc5lp/PSoC5/EEPROM_ModeStorage.c new file mode 100644 index 0000000000..b0006b48e1 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/EEPROM_ModeStorage.c @@ -0,0 +1,740 @@ +/******************************************************************************* +* File Name: EEPROM_ModeStorage.c +* Version 3.0 +* +* Description: +* Provides the source code to the API for the EEPROM component. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "EEPROM_ModeStorage.h" + + +/******************************************************************************* +* Function Name: EEPROM_ModeStorage_Enable +******************************************************************************** +* +* Summary: +* Enable the EEPROM block. Also reads the temperature and stores it for +* future writes. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void EEPROM_ModeStorage_Enable(void) +{ + /* Read temperature value */ + (void)CySetTemp(); + + /* Start EEPROM block */ + CyEEPROM_Start(); +} + + +/******************************************************************************* +* Function Name: EEPROM_ModeStorage_Start +******************************************************************************** +* +* Summary: +* Starts EEPROM. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void EEPROM_ModeStorage_Start(void) +{ + EEPROM_ModeStorage_Enable(); +} + + +/******************************************************************************* +* Function Name: EEPROM_ModeStorage_Stop +******************************************************************************** +* +* Summary: +* Stops and powers down EEPROM. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void EEPROM_ModeStorage_Stop (void) +{ + /* Stop and power down EEPROM block */ + CyEEPROM_Stop(); +} + + +/******************************************************************************* +* Function Name: EEPROM_ModeStorage_WriteByte +******************************************************************************** +* +* Summary: +* Writes a byte of data to the EEPROM. This function blocks until +* the function is complete. For a reliable write procedure to occur you should +* call EEPROM_ModeStorage_UpdateTemperature() function if the temperature of the +* silicon has been changed for more than 10C since the component was started. +* +* Parameters: +* dataByte: The byte of data to write to the EEPROM +* address: The address of data to be written. The maximum address is dependent +* on the EEPROM size. +* +* Return: +* CYRET_SUCCESS, if the operation was successful. +* CYRET_BAD_PARAM, if the parameter sectorNumber is out of range. +* CYRET_LOCKED, if the SPC is being used. +* CYRET_UNKNOWN, if there was an SPC error. +* +*******************************************************************************/ +cystatus EEPROM_ModeStorage_WriteByte(uint8 dataByte, uint16 address) +{ + cystatus status; + uint16 rowNumber; + uint16 byteNumber; + + CySpcStart(); + + if (address < CY_EEPROM_SIZE) + { + rowNumber = address/(uint16)CY_EEPROM_SIZEOF_ROW; + byteNumber = address - (rowNumber * ((uint16)CY_EEPROM_SIZEOF_ROW)); + if(CYRET_SUCCESS == CySpcLock()) + { + status = CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, byteNumber, &dataByte, \ + EEPROM_ModeStorage_SPC_BYTE_WRITE_SIZE); + if (CYRET_STARTED == status) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + /* Command to erase and program the row. */ + if(CYRET_SUCCESS == status) + { + if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u], + dieTemperature[1u]) == CYRET_STARTED) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + else + { + if (CYRET_BAD_PARAM != status) + { + status = CYRET_UNKNOWN; + } + } + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + + return (status); +} + + +/******************************************************************************* +* Function Name: EEPROM_ModeStorage_ReadByte +******************************************************************************** +* +* Summary: +* Reads and returns a byte of data from the on-chip EEPROM memory. Although +* the data is present in the CPU memory space, this function provides an +* intuitive user interface, addressing the EEPROM memory as a separate block with +* the first EERPOM byte address equal to 0x0000. +* +* Parameters: +* address: The address of data to be read. The maximum address is limited by the +* size of the EEPROM array on a specific device. +* +* Return: +* Data located at an address. +* +*******************************************************************************/ +uint8 EEPROM_ModeStorage_ReadByte(uint16 address) +{ + uint8 retByte; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Request access to EEPROM for reading. + This is needed to reserve PHUB for read operation from EEPROM */ + CyEEPROM_ReadReserve(); + + retByte = *((reg8 *) (CYDEV_EE_BASE + address)); + + /* Release EEPROM array */ + CyEEPROM_ReadRelease(); + + CyExitCriticalSection(interruptState); + + return (retByte); +} + + +/******************************************************************************* +* Function Name: EEPROM_ModeStorage_UpdateTemperature +******************************************************************************** +* +* Summary: +* Updates and stores the temperature value. This function should be called +* before EEPROM writes if the temperature may have been changed by more than +* 10 degrees Celsius. +* +* Parameters: +* None +* +* Return: +* Status of operation, 0 if operation complete, non-zero value if error +* was detected. +* +*******************************************************************************/ +uint8 EEPROM_ModeStorage_UpdateTemperature(void) +{ + return ((uint8)CySetTemp()); +} + + +/******************************************************************************* +* Function Name: EEPROM_ModeStorage_EraseSector +******************************************************************************** +* +* Summary: +* Erase an EEPROM sector (64 rows). This function blocks until the erase +* operation is complete. Using this API helps to erase the EEPROM sector at +* a time. This is faster than using individual writes but affects a cycle +* recourse of the whole EEPROM row. +* +* Parameters: +* sectorNumber: The sector number to erase. +* +* Return: +* CYRET_SUCCESS, if the operation was successful. +* CYRET_BAD_PARAM, if the parameter sectorNumber is out of range. +* CYRET_LOCKED, if the SPC is being used. +* CYRET_UNKNOWN, if there was an SPC error. +* +*******************************************************************************/ +cystatus EEPROM_ModeStorage_EraseSector(uint8 sectorNumber) +{ + cystatus status; + + CySpcStart(); + + if(sectorNumber < (uint8) EEPROM_ModeStorage_SECTORS_NUMBER) + { + /* See if we can get SPC. */ + if(CySpcLock() == CYRET_SUCCESS) + { + if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + } + else + { + status = CYRET_UNKNOWN; + } + + /* Unlock SPC so that someone else can use it. */ + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: EEPROM_ModeStorage_Write +******************************************************************************** +* +* Summary: +* Writes a row (16 bytes) of data to the EEPROM. This function blocks until +* the write operation is complete. Compared to functions that write one byte, +* this function allows writing a whole row (16 bytes) at a time. For +* a reliable write procedure to occur you should call the +* EEPROM_ModeStorage_UpdateTemperature() function if the temperature of the +* silicon has changed for more than 10C since component was started. +* +* Parameters: +* rowData: The address of the data to write to the EEPROM. +* rowNumber: The row number to write. +* +* Return: +* CYRET_SUCCESS, if the operation was successful. +* CYRET_BAD_PARAM, if the parameter rowNumber is out of range. +* CYRET_LOCKED, if the SPC is being used. +* CYRET_UNKNOWN, if there was an SPC error. +* +*******************************************************************************/ +cystatus EEPROM_ModeStorage_Write(const uint8 * rowData, uint8 rowNumber) +{ + cystatus status; + + CySpcStart(); + + if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) + { + /* See if we can get SPC. */ + if(CySpcLock() == CYRET_SUCCESS) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + /* Command to load a row of data */ + if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED) + { + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + + /* Command to erase and program the row. */ + if(status == CYRET_SUCCESS) + { + if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u], + dieTemperature[1u]) == CYRET_STARTED) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + + /* Unlock SPC so that someone else can use it. */ + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: EEPROM_ModeStorage_StartWrite +******************************************************************************** +* +* Summary: +* Starts a write of a row (16 bytes) of data to the EEPROM. +* This function does not block. The function returns once the SPC has begun +* writing the data. This function must be used in combination with +* EEPROM_ModeStorage_Query(). EEPROM_ModeStorage_Query() must be called +* until it returns a status other than CYRET_STARTED. That indicates that the +* write has completed. Until EEPROM_ModeStorage_Query() detects that +* the write is complete, the SPC is marked as locked to prevent another +* SPC operation from being performed. For a reliable write procedure to occur +* you should call EEPROM_ModeStorage_UpdateTemperature() API if the temperature +* of the silicon has changed for more than 10C since component was started. +* +* Parameters: +* rowData: The address of the data to write to the EEPROM. +* rowNumber: The row number to write. +* +* Return: +* CYRET_STARTED, if the SPC command to write was successfully started. +* CYRET_BAD_PARAM, if the parameter rowNumber is out of range. +* CYRET_LOCKED, if the SPC is being used. +* CYRET_UNKNOWN, if there was an SPC error. +* +* Side effects: +* After calling this API, the device should not be powered down, reset or switched +* to low power modes until EEPROM operation is complete. +* Ignoring this recommendation may lead to data corruption or silicon +* unexpected behavior. +* +*******************************************************************************/ +cystatus EEPROM_ModeStorage_StartWrite(const uint8 * rowData, uint8 rowNumber) \ + +{ + cystatus status; + + CySpcStart(); + + if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) + { + /* See if we can get SPC. */ + if(CySpcLock() == CYRET_SUCCESS) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + /* Command to load a row of data */ + if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED) + { + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + + /* Command to erase and program the row. */ + if(status == CYRET_SUCCESS) + { + if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u], + dieTemperature[1u]) == CYRET_STARTED) + { + status = CYRET_STARTED; + } + else + { + status = CYRET_UNKNOWN; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: EEPROM_ModeStorage_StartErase +******************************************************************************** +* +* Summary: +* Starts the EEPROM sector erase. This function does not block. +* The function returns once the SPC has begun writing the data. This function +* must be used in combination with EEPROM_ModeStorage_Query(). +* EEPROM_ModeStorage_Query() must be called until it returns a status +* other than CYRET_STARTED. That indicates the erase has been completed. +* Until EEPROM_ModeStorage_Query() detects that the erase is +* complete, the SPC is marked as locked to prevent another SPC operation +* from being performed. +* +* Parameters: +* sectorNumber: The sector number to erase. +* +* Return: +* CYRET_STARTED, if the SPC command to erase was successfully started. +* CYRET_BAD_PARAM, if the parameter sectorNumber is out of range. +* CYRET_LOCKED, if the SPC is being used. +* CYRET_UNKNOWN, if there was an SPC error. +* +* Side effects: +* After calling this API, the device should not be powered down, reset or switched +* to low power modes until EEPROM operation is complete. +* Ignoring this recommendation may lead to data corruption or silicon +* unexpected behavior. +* +*******************************************************************************/ +cystatus EEPROM_ModeStorage_StartErase(uint8 sectorNumber) +{ + cystatus status; + + CySpcStart(); + + if(sectorNumber < (uint8) CY_EEPROM_NUMBER_ARRAYS) + { + /* See if we can get SPC. */ + if(CySpcLock() == CYRET_SUCCESS) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + /* Command to load a row of data */ + if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED) + { + status = CYRET_SUCCESS; + } + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: EEPROM_ModeStorage_Query +******************************************************************************** +* +* Summary: +* Checks the status of an earlier call to EEPROM_ModeStorage_StartWrite() or +* EEPROM_ModeStorage_StartErase(). +* This function must be called until it returns a value other than +* CYRET_STARTED. Once that occurs, the write or erase has been completed and +* the SPC is unlocked. +* +* Parameters: +* None +* +* Return: +* CYRET_STARTED, if the SPC command is still processing. +* CYRET_SUCCESS, if the operation was completed successfully. +* CYRET_UNKNOWN, if there was an SPC error. +* +*******************************************************************************/ +cystatus EEPROM_ModeStorage_Query(void) +{ + cystatus status; + + CySpcStart(); + + /* Check if SPC is idle */ + if(CY_SPC_IDLE) + { + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + else + { + status = CYRET_UNKNOWN; + } + + /* Unlock SPC so that someone else can use it. */ + CySpcUnlock(); + } + else + { + status = CYRET_STARTED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: EEPROM_ModeStorage_ByteWritePos +******************************************************************************** +* +* Summary: +* Writes a byte of data to the EEPROM. This is a blocking call. It will not +* return until the write operation succeeds or fails. +* +* Parameters: +* dataByte: The byte of data to write to the EEPROM. +* rowNumber: The EEPROM row number to program. +* byteNumber: The byte number within the row to program. +* +* Return: +* CYRET_SUCCESS, if the operation was successful. +* CYRET_BAD_PARAM, if the parameter rowNumber or byteNumber is out of range. +* CYRET_LOCKED, if the SPC is being used. +* CYRET_UNKNOWN, if there was an SPC error. +* +*******************************************************************************/ +cystatus EEPROM_ModeStorage_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \ + +{ + cystatus status; + + /* Start SPC */ + CySpcStart(); + + if((rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) && (byteNumber < (uint8) SIZEOF_EEPROM_ROW)) + { + /* See if we can get SPC. */ + if(CySpcLock() == CYRET_SUCCESS) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + /* Command to load byte of data */ + if(CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, (uint16)byteNumber, &dataByte,\ + EEPROM_ModeStorage_SPC_BYTE_WRITE_SIZE) == CYRET_STARTED) + { + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + + /* Command to erase and program the row. */ + if(status == CYRET_SUCCESS) + { + if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u], + dieTemperature[1u]) == CYRET_STARTED) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + + /* Unlock SPC so that someone else can use it. */ + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/EEPROM_ModeStorage.h b/source/hic_hal/cypress/psoc5lp/PSoC5/EEPROM_ModeStorage.h new file mode 100644 index 0000000000..c737c98975 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/EEPROM_ModeStorage.h @@ -0,0 +1,89 @@ +/******************************************************************************* +* File Name: EEPROM_ModeStorage.h +* Version 3.0 +* +* Description: +* Provides the function definitions for the EEPROM APIs. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_EEPROM_EEPROM_ModeStorage_H) +#define CY_EEPROM_EEPROM_ModeStorage_H + +#include "cydevice_trm.h" +#include "CyFlash.h" + +#if !defined(CY_PSOC5LP) + #error Component EEPROM_v3_0 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +void EEPROM_ModeStorage_Enable(void) ; +void EEPROM_ModeStorage_Start(void) ; +void EEPROM_ModeStorage_Stop (void) ; +cystatus EEPROM_ModeStorage_WriteByte(uint8 dataByte, uint16 address) \ + ; +uint8 EEPROM_ModeStorage_ReadByte(uint16 address) ; +uint8 EEPROM_ModeStorage_UpdateTemperature(void) ; +cystatus EEPROM_ModeStorage_EraseSector(uint8 sectorNumber) ; +cystatus EEPROM_ModeStorage_Write(const uint8 * rowData, uint8 rowNumber) ; +cystatus EEPROM_ModeStorage_StartWrite(const uint8 * rowData, uint8 rowNumber) \ + ; +cystatus EEPROM_ModeStorage_StartErase(uint8 sectorNumber) ; +cystatus EEPROM_ModeStorage_Query(void) ; +cystatus EEPROM_ModeStorage_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \ + ; + + +/**************************************** +* API Constants +****************************************/ + +#define EEPROM_ModeStorage_EEPROM_SIZE CYDEV_EE_SIZE +#define EEPROM_ModeStorage_SPC_BYTE_WRITE_SIZE (0x01u) + +#define EEPROM_ModeStorage_SECTORS_NUMBER (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE) + +#define EEPROM_ModeStorage_AHB_REQ_SHIFT (0x00u) +#define EEPROM_ModeStorage_AHB_REQ ((uint8)(0x01u << EEPROM_ModeStorage_AHB_REQ_SHIFT)) +#define EEPROM_ModeStorage_AHB_ACK_SHIFT (0x01u) +#define EEPROM_ModeStorage_AHB_ACK_MASK ((uint8)(0x01u << EEPROM_ModeStorage_AHB_ACK_SHIFT)) + + +/*************************************** +* Registers +***************************************/ +#define EEPROM_ModeStorage_SPC_EE_SCR_REG (*(reg8 *) CYREG_SPC_EE_SCR) +#define EEPROM_ModeStorage_SPC_EE_SCR_PTR ( (reg8 *) CYREG_SPC_EE_SCR) + + + +/*************************************** +* The following code is DEPRECATED and +* should not be used in new projects. +***************************************/ +#define EEPROM_ModeStorage_ByteWrite EEPROM_ModeStorage_ByteWritePos +#define EEPROM_ModeStorage_QueryWrite EEPROM_ModeStorage_Query + +#endif /* CY_EEPROM_EEPROM_ModeStorage_H */ + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Amber.c b/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Amber.c new file mode 100644 index 0000000000..794f2b0e5a --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Amber.c @@ -0,0 +1,234 @@ +/******************************************************************************* +* File Name: LED_Amber.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "cytypes.h" +#include "LED_Amber.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + LED_Amber__PORT == 15 && ((LED_Amber__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: LED_Amber_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet LED_Amber_SUT.c usage_LED_Amber_Write +*******************************************************************************/ +void LED_Amber_Write(uint8 value) +{ + uint8 staticBits = (LED_Amber_DR & (uint8)(~LED_Amber_MASK)); + LED_Amber_DR = staticBits | ((uint8)(value << LED_Amber_SHIFT) & LED_Amber_MASK); +} + + +/******************************************************************************* +* Function Name: LED_Amber_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet LED_Amber_SUT.c usage_LED_Amber_SetDriveMode +*******************************************************************************/ +void LED_Amber_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(LED_Amber_0, mode); +} + + +/******************************************************************************* +* Function Name: LED_Amber_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet LED_Amber_SUT.c usage_LED_Amber_Read +*******************************************************************************/ +uint8 LED_Amber_Read(void) +{ + return (LED_Amber_PS & LED_Amber_MASK) >> LED_Amber_SHIFT; +} + + +/******************************************************************************* +* Function Name: LED_Amber_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred LED_Amber_Read() API because the +* LED_Amber_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet LED_Amber_SUT.c usage_LED_Amber_ReadDataReg +*******************************************************************************/ +uint8 LED_Amber_ReadDataReg(void) +{ + return (LED_Amber_DR & LED_Amber_MASK) >> LED_Amber_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(LED_Amber_INTSTAT) + + /******************************************************************************* + * Function Name: LED_Amber_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use LED_Amber_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - LED_Amber_0_INTR (First pin in the list) + * - LED_Amber_1_INTR (Second pin in the list) + * - ... + * - LED_Amber_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet LED_Amber_SUT.c usage_LED_Amber_SetInterruptMode + *******************************************************************************/ + void LED_Amber_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & LED_Amber_0_INTR) != 0u) + { + LED_Amber_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: LED_Amber_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet LED_Amber_SUT.c usage_LED_Amber_ClearInterrupt + *******************************************************************************/ + uint8 LED_Amber_ClearInterrupt(void) + { + return (LED_Amber_INTSTAT & LED_Amber_MASK) >> LED_Amber_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Amber.h b/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Amber.h new file mode 100644 index 0000000000..d60dec3bf1 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Amber.h @@ -0,0 +1,172 @@ +/******************************************************************************* +* File Name: LED_Amber.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ +#if !defined(CY_PINS_LED_Amber_H) /* Pins LED_Amber_H */ +#define CY_PINS_LED_Amber_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "LED_Amber_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + LED_Amber__PORT == 15 && ((LED_Amber__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void LED_Amber_Write(uint8 value); +void LED_Amber_SetDriveMode(uint8 mode); +uint8 LED_Amber_ReadDataReg(void); +uint8 LED_Amber_Read(void); +void LED_Amber_SetInterruptMode(uint16 position, uint16 mode); +uint8 LED_Amber_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the LED_Amber_SetDriveMode() function. + * @{ + */ + #define LED_Amber_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define LED_Amber_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define LED_Amber_DM_RES_UP PIN_DM_RES_UP + #define LED_Amber_DM_RES_DWN PIN_DM_RES_DWN + #define LED_Amber_DM_OD_LO PIN_DM_OD_LO + #define LED_Amber_DM_OD_HI PIN_DM_OD_HI + #define LED_Amber_DM_STRONG PIN_DM_STRONG + #define LED_Amber_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define LED_Amber_MASK LED_Amber__MASK +#define LED_Amber_SHIFT LED_Amber__SHIFT +#define LED_Amber_WIDTH 1u + +/* Interrupt constants */ +#if defined(LED_Amber__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in LED_Amber_SetInterruptMode() function. + * @{ + */ + #define LED_Amber_INTR_NONE (uint16)(0x0000u) + #define LED_Amber_INTR_RISING (uint16)(0x0001u) + #define LED_Amber_INTR_FALLING (uint16)(0x0002u) + #define LED_Amber_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define LED_Amber_INTR_MASK (0x01u) +#endif /* (LED_Amber__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define LED_Amber_PS (* (reg8 *) LED_Amber__PS) +/* Data Register */ +#define LED_Amber_DR (* (reg8 *) LED_Amber__DR) +/* Port Number */ +#define LED_Amber_PRT_NUM (* (reg8 *) LED_Amber__PRT) +/* Connect to Analog Globals */ +#define LED_Amber_AG (* (reg8 *) LED_Amber__AG) +/* Analog MUX bux enable */ +#define LED_Amber_AMUX (* (reg8 *) LED_Amber__AMUX) +/* Bidirectional Enable */ +#define LED_Amber_BIE (* (reg8 *) LED_Amber__BIE) +/* Bit-mask for Aliased Register Access */ +#define LED_Amber_BIT_MASK (* (reg8 *) LED_Amber__BIT_MASK) +/* Bypass Enable */ +#define LED_Amber_BYP (* (reg8 *) LED_Amber__BYP) +/* Port wide control signals */ +#define LED_Amber_CTL (* (reg8 *) LED_Amber__CTL) +/* Drive Modes */ +#define LED_Amber_DM0 (* (reg8 *) LED_Amber__DM0) +#define LED_Amber_DM1 (* (reg8 *) LED_Amber__DM1) +#define LED_Amber_DM2 (* (reg8 *) LED_Amber__DM2) +/* Input Buffer Disable Override */ +#define LED_Amber_INP_DIS (* (reg8 *) LED_Amber__INP_DIS) +/* LCD Common or Segment Drive */ +#define LED_Amber_LCD_COM_SEG (* (reg8 *) LED_Amber__LCD_COM_SEG) +/* Enable Segment LCD */ +#define LED_Amber_LCD_EN (* (reg8 *) LED_Amber__LCD_EN) +/* Slew Rate Control */ +#define LED_Amber_SLW (* (reg8 *) LED_Amber__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define LED_Amber_PRTDSI__CAPS_SEL (* (reg8 *) LED_Amber__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define LED_Amber_PRTDSI__DBL_SYNC_IN (* (reg8 *) LED_Amber__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define LED_Amber_PRTDSI__OE_SEL0 (* (reg8 *) LED_Amber__PRTDSI__OE_SEL0) +#define LED_Amber_PRTDSI__OE_SEL1 (* (reg8 *) LED_Amber__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define LED_Amber_PRTDSI__OUT_SEL0 (* (reg8 *) LED_Amber__PRTDSI__OUT_SEL0) +#define LED_Amber_PRTDSI__OUT_SEL1 (* (reg8 *) LED_Amber__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define LED_Amber_PRTDSI__SYNC_OUT (* (reg8 *) LED_Amber__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(LED_Amber__SIO_CFG) + #define LED_Amber_SIO_HYST_EN (* (reg8 *) LED_Amber__SIO_HYST_EN) + #define LED_Amber_SIO_REG_HIFREQ (* (reg8 *) LED_Amber__SIO_REG_HIFREQ) + #define LED_Amber_SIO_CFG (* (reg8 *) LED_Amber__SIO_CFG) + #define LED_Amber_SIO_DIFF (* (reg8 *) LED_Amber__SIO_DIFF) +#endif /* (LED_Amber__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(LED_Amber__INTSTAT) + #define LED_Amber_INTSTAT (* (reg8 *) LED_Amber__INTSTAT) + #define LED_Amber_SNAP (* (reg8 *) LED_Amber__SNAP) + + #define LED_Amber_0_INTTYPE_REG (* (reg8 *) LED_Amber__0__INTTYPE) +#endif /* (LED_Amber__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_LED_Amber_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Amber_aliases.h b/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Amber_aliases.h new file mode 100644 index 0000000000..5dff322384 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Amber_aliases.h @@ -0,0 +1,44 @@ +/******************************************************************************* +* File Name: LED_Amber.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_LED_Amber_ALIASES_H) /* Pins LED_Amber_ALIASES_H */ +#define CY_PINS_LED_Amber_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define LED_Amber_0 (LED_Amber__0__PC) +#define LED_Amber_0_INTR ((uint16)((uint16)0x0001u << LED_Amber__0__SHIFT)) + +#define LED_Amber_INTR_ALL ((uint16)(LED_Amber_0_INTR)) + +#endif /* End Pins LED_Amber_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Green.c b/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Green.c new file mode 100644 index 0000000000..91958b4cdc --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Green.c @@ -0,0 +1,234 @@ +/******************************************************************************* +* File Name: LED_Green.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "cytypes.h" +#include "LED_Green.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + LED_Green__PORT == 15 && ((LED_Green__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: LED_Green_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet LED_Green_SUT.c usage_LED_Green_Write +*******************************************************************************/ +void LED_Green_Write(uint8 value) +{ + uint8 staticBits = (LED_Green_DR & (uint8)(~LED_Green_MASK)); + LED_Green_DR = staticBits | ((uint8)(value << LED_Green_SHIFT) & LED_Green_MASK); +} + + +/******************************************************************************* +* Function Name: LED_Green_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet LED_Green_SUT.c usage_LED_Green_SetDriveMode +*******************************************************************************/ +void LED_Green_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(LED_Green_0, mode); +} + + +/******************************************************************************* +* Function Name: LED_Green_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet LED_Green_SUT.c usage_LED_Green_Read +*******************************************************************************/ +uint8 LED_Green_Read(void) +{ + return (LED_Green_PS & LED_Green_MASK) >> LED_Green_SHIFT; +} + + +/******************************************************************************* +* Function Name: LED_Green_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred LED_Green_Read() API because the +* LED_Green_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet LED_Green_SUT.c usage_LED_Green_ReadDataReg +*******************************************************************************/ +uint8 LED_Green_ReadDataReg(void) +{ + return (LED_Green_DR & LED_Green_MASK) >> LED_Green_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(LED_Green_INTSTAT) + + /******************************************************************************* + * Function Name: LED_Green_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use LED_Green_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - LED_Green_0_INTR (First pin in the list) + * - LED_Green_1_INTR (Second pin in the list) + * - ... + * - LED_Green_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet LED_Green_SUT.c usage_LED_Green_SetInterruptMode + *******************************************************************************/ + void LED_Green_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & LED_Green_0_INTR) != 0u) + { + LED_Green_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: LED_Green_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet LED_Green_SUT.c usage_LED_Green_ClearInterrupt + *******************************************************************************/ + uint8 LED_Green_ClearInterrupt(void) + { + return (LED_Green_INTSTAT & LED_Green_MASK) >> LED_Green_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Green.h b/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Green.h new file mode 100644 index 0000000000..4399f23ce1 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Green.h @@ -0,0 +1,173 @@ +/******************************************************************************* +* File Name: LED_Green.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_LED_Green_H) /* Pins LED_Green_H */ +#define CY_PINS_LED_Green_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "LED_Green_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + LED_Green__PORT == 15 && ((LED_Green__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void LED_Green_Write(uint8 value); +void LED_Green_SetDriveMode(uint8 mode); +uint8 LED_Green_ReadDataReg(void); +uint8 LED_Green_Read(void); +void LED_Green_SetInterruptMode(uint16 position, uint16 mode); +uint8 LED_Green_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the LED_Green_SetDriveMode() function. + * @{ + */ + #define LED_Green_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define LED_Green_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define LED_Green_DM_RES_UP PIN_DM_RES_UP + #define LED_Green_DM_RES_DWN PIN_DM_RES_DWN + #define LED_Green_DM_OD_LO PIN_DM_OD_LO + #define LED_Green_DM_OD_HI PIN_DM_OD_HI + #define LED_Green_DM_STRONG PIN_DM_STRONG + #define LED_Green_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define LED_Green_MASK LED_Green__MASK +#define LED_Green_SHIFT LED_Green__SHIFT +#define LED_Green_WIDTH 1u + +/* Interrupt constants */ +#if defined(LED_Green__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in LED_Green_SetInterruptMode() function. + * @{ + */ + #define LED_Green_INTR_NONE (uint16)(0x0000u) + #define LED_Green_INTR_RISING (uint16)(0x0001u) + #define LED_Green_INTR_FALLING (uint16)(0x0002u) + #define LED_Green_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define LED_Green_INTR_MASK (0x01u) +#endif /* (LED_Green__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define LED_Green_PS (* (reg8 *) LED_Green__PS) +/* Data Register */ +#define LED_Green_DR (* (reg8 *) LED_Green__DR) +/* Port Number */ +#define LED_Green_PRT_NUM (* (reg8 *) LED_Green__PRT) +/* Connect to Analog Globals */ +#define LED_Green_AG (* (reg8 *) LED_Green__AG) +/* Analog MUX bux enable */ +#define LED_Green_AMUX (* (reg8 *) LED_Green__AMUX) +/* Bidirectional Enable */ +#define LED_Green_BIE (* (reg8 *) LED_Green__BIE) +/* Bit-mask for Aliased Register Access */ +#define LED_Green_BIT_MASK (* (reg8 *) LED_Green__BIT_MASK) +/* Bypass Enable */ +#define LED_Green_BYP (* (reg8 *) LED_Green__BYP) +/* Port wide control signals */ +#define LED_Green_CTL (* (reg8 *) LED_Green__CTL) +/* Drive Modes */ +#define LED_Green_DM0 (* (reg8 *) LED_Green__DM0) +#define LED_Green_DM1 (* (reg8 *) LED_Green__DM1) +#define LED_Green_DM2 (* (reg8 *) LED_Green__DM2) +/* Input Buffer Disable Override */ +#define LED_Green_INP_DIS (* (reg8 *) LED_Green__INP_DIS) +/* LCD Common or Segment Drive */ +#define LED_Green_LCD_COM_SEG (* (reg8 *) LED_Green__LCD_COM_SEG) +/* Enable Segment LCD */ +#define LED_Green_LCD_EN (* (reg8 *) LED_Green__LCD_EN) +/* Slew Rate Control */ +#define LED_Green_SLW (* (reg8 *) LED_Green__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define LED_Green_PRTDSI__CAPS_SEL (* (reg8 *) LED_Green__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define LED_Green_PRTDSI__DBL_SYNC_IN (* (reg8 *) LED_Green__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define LED_Green_PRTDSI__OE_SEL0 (* (reg8 *) LED_Green__PRTDSI__OE_SEL0) +#define LED_Green_PRTDSI__OE_SEL1 (* (reg8 *) LED_Green__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define LED_Green_PRTDSI__OUT_SEL0 (* (reg8 *) LED_Green__PRTDSI__OUT_SEL0) +#define LED_Green_PRTDSI__OUT_SEL1 (* (reg8 *) LED_Green__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define LED_Green_PRTDSI__SYNC_OUT (* (reg8 *) LED_Green__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(LED_Green__SIO_CFG) + #define LED_Green_SIO_HYST_EN (* (reg8 *) LED_Green__SIO_HYST_EN) + #define LED_Green_SIO_REG_HIFREQ (* (reg8 *) LED_Green__SIO_REG_HIFREQ) + #define LED_Green_SIO_CFG (* (reg8 *) LED_Green__SIO_CFG) + #define LED_Green_SIO_DIFF (* (reg8 *) LED_Green__SIO_DIFF) +#endif /* (LED_Green__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(LED_Green__INTSTAT) + #define LED_Green_INTSTAT (* (reg8 *) LED_Green__INTSTAT) + #define LED_Green_SNAP (* (reg8 *) LED_Green__SNAP) + + #define LED_Green_0_INTTYPE_REG (* (reg8 *) LED_Green__0__INTTYPE) +#endif /* (LED_Green__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_LED_Green_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Green_aliases.h b/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Green_aliases.h new file mode 100644 index 0000000000..1dc269f4b4 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Green_aliases.h @@ -0,0 +1,44 @@ +/******************************************************************************* +* File Name: LED_Green.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_LED_Green_ALIASES_H) /* Pins LED_Green_ALIASES_H */ +#define CY_PINS_LED_Green_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define LED_Green_0 (LED_Green__0__PC) +#define LED_Green_0_INTR ((uint16)((uint16)0x0001u << LED_Green__0__SHIFT)) + +#define LED_Green_INTR_ALL ((uint16)(LED_Green_0_INTR)) + +#endif /* End Pins LED_Green_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Red.c b/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Red.c new file mode 100644 index 0000000000..8167146474 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Red.c @@ -0,0 +1,234 @@ +/******************************************************************************* +* File Name: LED_Red.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "cytypes.h" +#include "LED_Red.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + LED_Red__PORT == 15 && ((LED_Red__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: LED_Red_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet LED_Red_SUT.c usage_LED_Red_Write +*******************************************************************************/ +void LED_Red_Write(uint8 value) +{ + uint8 staticBits = (LED_Red_DR & (uint8)(~LED_Red_MASK)); + LED_Red_DR = staticBits | ((uint8)(value << LED_Red_SHIFT) & LED_Red_MASK); +} + + +/******************************************************************************* +* Function Name: LED_Red_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet LED_Red_SUT.c usage_LED_Red_SetDriveMode +*******************************************************************************/ +void LED_Red_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(LED_Red_0, mode); +} + + +/******************************************************************************* +* Function Name: LED_Red_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet LED_Red_SUT.c usage_LED_Red_Read +*******************************************************************************/ +uint8 LED_Red_Read(void) +{ + return (LED_Red_PS & LED_Red_MASK) >> LED_Red_SHIFT; +} + + +/******************************************************************************* +* Function Name: LED_Red_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred LED_Red_Read() API because the +* LED_Red_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet LED_Red_SUT.c usage_LED_Red_ReadDataReg +*******************************************************************************/ +uint8 LED_Red_ReadDataReg(void) +{ + return (LED_Red_DR & LED_Red_MASK) >> LED_Red_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(LED_Red_INTSTAT) + + /******************************************************************************* + * Function Name: LED_Red_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use LED_Red_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - LED_Red_0_INTR (First pin in the list) + * - LED_Red_1_INTR (Second pin in the list) + * - ... + * - LED_Red_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet LED_Red_SUT.c usage_LED_Red_SetInterruptMode + *******************************************************************************/ + void LED_Red_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & LED_Red_0_INTR) != 0u) + { + LED_Red_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: LED_Red_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet LED_Red_SUT.c usage_LED_Red_ClearInterrupt + *******************************************************************************/ + uint8 LED_Red_ClearInterrupt(void) + { + return (LED_Red_INTSTAT & LED_Red_MASK) >> LED_Red_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Red.h b/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Red.h new file mode 100644 index 0000000000..48c2e3bb5f --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Red.h @@ -0,0 +1,173 @@ +/******************************************************************************* +* File Name: LED_Red.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_LED_Red_H) /* Pins LED_Red_H */ +#define CY_PINS_LED_Red_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "LED_Red_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + LED_Red__PORT == 15 && ((LED_Red__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void LED_Red_Write(uint8 value); +void LED_Red_SetDriveMode(uint8 mode); +uint8 LED_Red_ReadDataReg(void); +uint8 LED_Red_Read(void); +void LED_Red_SetInterruptMode(uint16 position, uint16 mode); +uint8 LED_Red_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the LED_Red_SetDriveMode() function. + * @{ + */ + #define LED_Red_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define LED_Red_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define LED_Red_DM_RES_UP PIN_DM_RES_UP + #define LED_Red_DM_RES_DWN PIN_DM_RES_DWN + #define LED_Red_DM_OD_LO PIN_DM_OD_LO + #define LED_Red_DM_OD_HI PIN_DM_OD_HI + #define LED_Red_DM_STRONG PIN_DM_STRONG + #define LED_Red_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define LED_Red_MASK LED_Red__MASK +#define LED_Red_SHIFT LED_Red__SHIFT +#define LED_Red_WIDTH 1u + +/* Interrupt constants */ +#if defined(LED_Red__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in LED_Red_SetInterruptMode() function. + * @{ + */ + #define LED_Red_INTR_NONE (uint16)(0x0000u) + #define LED_Red_INTR_RISING (uint16)(0x0001u) + #define LED_Red_INTR_FALLING (uint16)(0x0002u) + #define LED_Red_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define LED_Red_INTR_MASK (0x01u) +#endif /* (LED_Red__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define LED_Red_PS (* (reg8 *) LED_Red__PS) +/* Data Register */ +#define LED_Red_DR (* (reg8 *) LED_Red__DR) +/* Port Number */ +#define LED_Red_PRT_NUM (* (reg8 *) LED_Red__PRT) +/* Connect to Analog Globals */ +#define LED_Red_AG (* (reg8 *) LED_Red__AG) +/* Analog MUX bux enable */ +#define LED_Red_AMUX (* (reg8 *) LED_Red__AMUX) +/* Bidirectional Enable */ +#define LED_Red_BIE (* (reg8 *) LED_Red__BIE) +/* Bit-mask for Aliased Register Access */ +#define LED_Red_BIT_MASK (* (reg8 *) LED_Red__BIT_MASK) +/* Bypass Enable */ +#define LED_Red_BYP (* (reg8 *) LED_Red__BYP) +/* Port wide control signals */ +#define LED_Red_CTL (* (reg8 *) LED_Red__CTL) +/* Drive Modes */ +#define LED_Red_DM0 (* (reg8 *) LED_Red__DM0) +#define LED_Red_DM1 (* (reg8 *) LED_Red__DM1) +#define LED_Red_DM2 (* (reg8 *) LED_Red__DM2) +/* Input Buffer Disable Override */ +#define LED_Red_INP_DIS (* (reg8 *) LED_Red__INP_DIS) +/* LCD Common or Segment Drive */ +#define LED_Red_LCD_COM_SEG (* (reg8 *) LED_Red__LCD_COM_SEG) +/* Enable Segment LCD */ +#define LED_Red_LCD_EN (* (reg8 *) LED_Red__LCD_EN) +/* Slew Rate Control */ +#define LED_Red_SLW (* (reg8 *) LED_Red__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define LED_Red_PRTDSI__CAPS_SEL (* (reg8 *) LED_Red__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define LED_Red_PRTDSI__DBL_SYNC_IN (* (reg8 *) LED_Red__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define LED_Red_PRTDSI__OE_SEL0 (* (reg8 *) LED_Red__PRTDSI__OE_SEL0) +#define LED_Red_PRTDSI__OE_SEL1 (* (reg8 *) LED_Red__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define LED_Red_PRTDSI__OUT_SEL0 (* (reg8 *) LED_Red__PRTDSI__OUT_SEL0) +#define LED_Red_PRTDSI__OUT_SEL1 (* (reg8 *) LED_Red__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define LED_Red_PRTDSI__SYNC_OUT (* (reg8 *) LED_Red__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(LED_Red__SIO_CFG) + #define LED_Red_SIO_HYST_EN (* (reg8 *) LED_Red__SIO_HYST_EN) + #define LED_Red_SIO_REG_HIFREQ (* (reg8 *) LED_Red__SIO_REG_HIFREQ) + #define LED_Red_SIO_CFG (* (reg8 *) LED_Red__SIO_CFG) + #define LED_Red_SIO_DIFF (* (reg8 *) LED_Red__SIO_DIFF) +#endif /* (LED_Red__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(LED_Red__INTSTAT) + #define LED_Red_INTSTAT (* (reg8 *) LED_Red__INTSTAT) + #define LED_Red_SNAP (* (reg8 *) LED_Red__SNAP) + + #define LED_Red_0_INTTYPE_REG (* (reg8 *) LED_Red__0__INTTYPE) +#endif /* (LED_Red__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_LED_Red_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Red_aliases.h b/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Red_aliases.h new file mode 100644 index 0000000000..47a3c3b782 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/LED_Red_aliases.h @@ -0,0 +1,44 @@ +/******************************************************************************* +* File Name: LED_Red.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_LED_Red_ALIASES_H) /* Pins LED_Red_ALIASES_H */ +#define CY_PINS_LED_Red_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define LED_Red_0 (LED_Red__0__PC) +#define LED_Red_0_INTR ((uint16)((uint16)0x0001u << LED_Red__0__SHIFT)) + +#define LED_Red_INTR_ALL ((uint16)(LED_Red_0_INTR)) + +#endif /* End Pins LED_Red_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/ModeButton.c b/source/hic_hal/cypress/psoc5lp/PSoC5/ModeButton.c new file mode 100644 index 0000000000..f7a79c708b --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/ModeButton.c @@ -0,0 +1,234 @@ +/******************************************************************************* +* File Name: ModeButton.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "cytypes.h" +#include "ModeButton.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + ModeButton__PORT == 15 && ((ModeButton__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: ModeButton_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet ModeButton_SUT.c usage_ModeButton_Write +*******************************************************************************/ +void ModeButton_Write(uint8 value) +{ + uint8 staticBits = (ModeButton_DR & (uint8)(~ModeButton_MASK)); + ModeButton_DR = staticBits | ((uint8)(value << ModeButton_SHIFT) & ModeButton_MASK); +} + + +/******************************************************************************* +* Function Name: ModeButton_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet ModeButton_SUT.c usage_ModeButton_SetDriveMode +*******************************************************************************/ +void ModeButton_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(ModeButton_0, mode); +} + + +/******************************************************************************* +* Function Name: ModeButton_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet ModeButton_SUT.c usage_ModeButton_Read +*******************************************************************************/ +uint8 ModeButton_Read(void) +{ + return (ModeButton_PS & ModeButton_MASK) >> ModeButton_SHIFT; +} + + +/******************************************************************************* +* Function Name: ModeButton_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred ModeButton_Read() API because the +* ModeButton_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet ModeButton_SUT.c usage_ModeButton_ReadDataReg +*******************************************************************************/ +uint8 ModeButton_ReadDataReg(void) +{ + return (ModeButton_DR & ModeButton_MASK) >> ModeButton_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(ModeButton_INTSTAT) + + /******************************************************************************* + * Function Name: ModeButton_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use ModeButton_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - ModeButton_0_INTR (First pin in the list) + * - ModeButton_1_INTR (Second pin in the list) + * - ... + * - ModeButton_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet ModeButton_SUT.c usage_ModeButton_SetInterruptMode + *******************************************************************************/ + void ModeButton_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & ModeButton_0_INTR) != 0u) + { + ModeButton_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: ModeButton_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet ModeButton_SUT.c usage_ModeButton_ClearInterrupt + *******************************************************************************/ + uint8 ModeButton_ClearInterrupt(void) + { + return (ModeButton_INTSTAT & ModeButton_MASK) >> ModeButton_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/ModeButton.h b/source/hic_hal/cypress/psoc5lp/PSoC5/ModeButton.h new file mode 100644 index 0000000000..17d8d55e3f --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/ModeButton.h @@ -0,0 +1,173 @@ +/******************************************************************************* +* File Name: ModeButton.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_ModeButton_H) /* Pins ModeButton_H */ +#define CY_PINS_ModeButton_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "ModeButton_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + ModeButton__PORT == 15 && ((ModeButton__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void ModeButton_Write(uint8 value); +void ModeButton_SetDriveMode(uint8 mode); +uint8 ModeButton_ReadDataReg(void); +uint8 ModeButton_Read(void); +void ModeButton_SetInterruptMode(uint16 position, uint16 mode); +uint8 ModeButton_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the ModeButton_SetDriveMode() function. + * @{ + */ + #define ModeButton_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define ModeButton_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define ModeButton_DM_RES_UP PIN_DM_RES_UP + #define ModeButton_DM_RES_DWN PIN_DM_RES_DWN + #define ModeButton_DM_OD_LO PIN_DM_OD_LO + #define ModeButton_DM_OD_HI PIN_DM_OD_HI + #define ModeButton_DM_STRONG PIN_DM_STRONG + #define ModeButton_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define ModeButton_MASK ModeButton__MASK +#define ModeButton_SHIFT ModeButton__SHIFT +#define ModeButton_WIDTH 1u + +/* Interrupt constants */ +#if defined(ModeButton__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in ModeButton_SetInterruptMode() function. + * @{ + */ + #define ModeButton_INTR_NONE (uint16)(0x0000u) + #define ModeButton_INTR_RISING (uint16)(0x0001u) + #define ModeButton_INTR_FALLING (uint16)(0x0002u) + #define ModeButton_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define ModeButton_INTR_MASK (0x01u) +#endif /* (ModeButton__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define ModeButton_PS (* (reg8 *) ModeButton__PS) +/* Data Register */ +#define ModeButton_DR (* (reg8 *) ModeButton__DR) +/* Port Number */ +#define ModeButton_PRT_NUM (* (reg8 *) ModeButton__PRT) +/* Connect to Analog Globals */ +#define ModeButton_AG (* (reg8 *) ModeButton__AG) +/* Analog MUX bux enable */ +#define ModeButton_AMUX (* (reg8 *) ModeButton__AMUX) +/* Bidirectional Enable */ +#define ModeButton_BIE (* (reg8 *) ModeButton__BIE) +/* Bit-mask for Aliased Register Access */ +#define ModeButton_BIT_MASK (* (reg8 *) ModeButton__BIT_MASK) +/* Bypass Enable */ +#define ModeButton_BYP (* (reg8 *) ModeButton__BYP) +/* Port wide control signals */ +#define ModeButton_CTL (* (reg8 *) ModeButton__CTL) +/* Drive Modes */ +#define ModeButton_DM0 (* (reg8 *) ModeButton__DM0) +#define ModeButton_DM1 (* (reg8 *) ModeButton__DM1) +#define ModeButton_DM2 (* (reg8 *) ModeButton__DM2) +/* Input Buffer Disable Override */ +#define ModeButton_INP_DIS (* (reg8 *) ModeButton__INP_DIS) +/* LCD Common or Segment Drive */ +#define ModeButton_LCD_COM_SEG (* (reg8 *) ModeButton__LCD_COM_SEG) +/* Enable Segment LCD */ +#define ModeButton_LCD_EN (* (reg8 *) ModeButton__LCD_EN) +/* Slew Rate Control */ +#define ModeButton_SLW (* (reg8 *) ModeButton__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define ModeButton_PRTDSI__CAPS_SEL (* (reg8 *) ModeButton__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define ModeButton_PRTDSI__DBL_SYNC_IN (* (reg8 *) ModeButton__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define ModeButton_PRTDSI__OE_SEL0 (* (reg8 *) ModeButton__PRTDSI__OE_SEL0) +#define ModeButton_PRTDSI__OE_SEL1 (* (reg8 *) ModeButton__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define ModeButton_PRTDSI__OUT_SEL0 (* (reg8 *) ModeButton__PRTDSI__OUT_SEL0) +#define ModeButton_PRTDSI__OUT_SEL1 (* (reg8 *) ModeButton__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define ModeButton_PRTDSI__SYNC_OUT (* (reg8 *) ModeButton__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(ModeButton__SIO_CFG) + #define ModeButton_SIO_HYST_EN (* (reg8 *) ModeButton__SIO_HYST_EN) + #define ModeButton_SIO_REG_HIFREQ (* (reg8 *) ModeButton__SIO_REG_HIFREQ) + #define ModeButton_SIO_CFG (* (reg8 *) ModeButton__SIO_CFG) + #define ModeButton_SIO_DIFF (* (reg8 *) ModeButton__SIO_DIFF) +#endif /* (ModeButton__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(ModeButton__INTSTAT) + #define ModeButton_INTSTAT (* (reg8 *) ModeButton__INTSTAT) + #define ModeButton_SNAP (* (reg8 *) ModeButton__SNAP) + + #define ModeButton_0_INTTYPE_REG (* (reg8 *) ModeButton__0__INTTYPE) +#endif /* (ModeButton__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_ModeButton_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/ModeButton_aliases.h b/source/hic_hal/cypress/psoc5lp/PSoC5/ModeButton_aliases.h new file mode 100644 index 0000000000..402292880b --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/ModeButton_aliases.h @@ -0,0 +1,44 @@ +/******************************************************************************* +* File Name: ModeButton.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_ModeButton_ALIASES_H) /* Pins ModeButton_ALIASES_H */ +#define CY_PINS_ModeButton_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define ModeButton_0 (ModeButton__0__PC) +#define ModeButton_0_INTR ((uint16)((uint16)0x0001u << ModeButton__0__SHIFT)) + +#define ModeButton_INTR_ALL ((uint16)(ModeButton_0_INTR)) + +#endif /* End Pins ModeButton_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_HWVersion.c b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_HWVersion.c new file mode 100644 index 0000000000..3414851d1b --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_HWVersion.c @@ -0,0 +1,254 @@ +/******************************************************************************* +* File Name: Pin_HWVersion.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "cytypes.h" +#include "Pin_HWVersion.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + Pin_HWVersion__PORT == 15 && ((Pin_HWVersion__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: Pin_HWVersion_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet Pin_HWVersion_SUT.c usage_Pin_HWVersion_Write +*******************************************************************************/ +void Pin_HWVersion_Write(uint8 value) +{ + uint8 staticBits = (Pin_HWVersion_DR & (uint8)(~Pin_HWVersion_MASK)); + Pin_HWVersion_DR = staticBits | ((uint8)(value << Pin_HWVersion_SHIFT) & Pin_HWVersion_MASK); +} + + +/******************************************************************************* +* Function Name: Pin_HWVersion_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet Pin_HWVersion_SUT.c usage_Pin_HWVersion_SetDriveMode +*******************************************************************************/ +void Pin_HWVersion_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(Pin_HWVersion_0, mode); + CyPins_SetPinDriveMode(Pin_HWVersion_1, mode); + CyPins_SetPinDriveMode(Pin_HWVersion_2, mode); + CyPins_SetPinDriveMode(Pin_HWVersion_3, mode); + CyPins_SetPinDriveMode(Pin_HWVersion_4, mode); +} + + +/******************************************************************************* +* Function Name: Pin_HWVersion_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet Pin_HWVersion_SUT.c usage_Pin_HWVersion_Read +*******************************************************************************/ +uint8 Pin_HWVersion_Read(void) +{ + return (Pin_HWVersion_PS & Pin_HWVersion_MASK) >> Pin_HWVersion_SHIFT; +} + + +/******************************************************************************* +* Function Name: Pin_HWVersion_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred Pin_HWVersion_Read() API because the +* Pin_HWVersion_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet Pin_HWVersion_SUT.c usage_Pin_HWVersion_ReadDataReg +*******************************************************************************/ +uint8 Pin_HWVersion_ReadDataReg(void) +{ + return (Pin_HWVersion_DR & Pin_HWVersion_MASK) >> Pin_HWVersion_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(Pin_HWVersion_INTSTAT) + + /******************************************************************************* + * Function Name: Pin_HWVersion_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use Pin_HWVersion_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - Pin_HWVersion_0_INTR (First pin in the list) + * - Pin_HWVersion_1_INTR (Second pin in the list) + * - ... + * - Pin_HWVersion_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet Pin_HWVersion_SUT.c usage_Pin_HWVersion_SetInterruptMode + *******************************************************************************/ + void Pin_HWVersion_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & Pin_HWVersion_0_INTR) != 0u) + { + Pin_HWVersion_0_INTTYPE_REG = (uint8)mode; + } + if((position & Pin_HWVersion_1_INTR) != 0u) + { + Pin_HWVersion_1_INTTYPE_REG = (uint8)mode; + } + if((position & Pin_HWVersion_2_INTR) != 0u) + { + Pin_HWVersion_2_INTTYPE_REG = (uint8)mode; + } + if((position & Pin_HWVersion_3_INTR) != 0u) + { + Pin_HWVersion_3_INTTYPE_REG = (uint8)mode; + } + if((position & Pin_HWVersion_4_INTR) != 0u) + { + Pin_HWVersion_4_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: Pin_HWVersion_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet Pin_HWVersion_SUT.c usage_Pin_HWVersion_ClearInterrupt + *******************************************************************************/ + uint8 Pin_HWVersion_ClearInterrupt(void) + { + return (Pin_HWVersion_INTSTAT & Pin_HWVersion_MASK) >> Pin_HWVersion_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_HWVersion.h b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_HWVersion.h new file mode 100644 index 0000000000..bd8f5cfc26 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_HWVersion.h @@ -0,0 +1,177 @@ +/******************************************************************************* +* File Name: Pin_HWVersion.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_Pin_HWVersion_H) /* Pins Pin_HWVersion_H */ +#define CY_PINS_Pin_HWVersion_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "Pin_HWVersion_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + Pin_HWVersion__PORT == 15 && ((Pin_HWVersion__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void Pin_HWVersion_Write(uint8 value); +void Pin_HWVersion_SetDriveMode(uint8 mode); +uint8 Pin_HWVersion_ReadDataReg(void); +uint8 Pin_HWVersion_Read(void); +void Pin_HWVersion_SetInterruptMode(uint16 position, uint16 mode); +uint8 Pin_HWVersion_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the Pin_HWVersion_SetDriveMode() function. + * @{ + */ + #define Pin_HWVersion_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define Pin_HWVersion_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define Pin_HWVersion_DM_RES_UP PIN_DM_RES_UP + #define Pin_HWVersion_DM_RES_DWN PIN_DM_RES_DWN + #define Pin_HWVersion_DM_OD_LO PIN_DM_OD_LO + #define Pin_HWVersion_DM_OD_HI PIN_DM_OD_HI + #define Pin_HWVersion_DM_STRONG PIN_DM_STRONG + #define Pin_HWVersion_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define Pin_HWVersion_MASK Pin_HWVersion__MASK +#define Pin_HWVersion_SHIFT Pin_HWVersion__SHIFT +#define Pin_HWVersion_WIDTH 5u + +/* Interrupt constants */ +#if defined(Pin_HWVersion__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in Pin_HWVersion_SetInterruptMode() function. + * @{ + */ + #define Pin_HWVersion_INTR_NONE (uint16)(0x0000u) + #define Pin_HWVersion_INTR_RISING (uint16)(0x0001u) + #define Pin_HWVersion_INTR_FALLING (uint16)(0x0002u) + #define Pin_HWVersion_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define Pin_HWVersion_INTR_MASK (0x01u) +#endif /* (Pin_HWVersion__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define Pin_HWVersion_PS (* (reg8 *) Pin_HWVersion__PS) +/* Data Register */ +#define Pin_HWVersion_DR (* (reg8 *) Pin_HWVersion__DR) +/* Port Number */ +#define Pin_HWVersion_PRT_NUM (* (reg8 *) Pin_HWVersion__PRT) +/* Connect to Analog Globals */ +#define Pin_HWVersion_AG (* (reg8 *) Pin_HWVersion__AG) +/* Analog MUX bux enable */ +#define Pin_HWVersion_AMUX (* (reg8 *) Pin_HWVersion__AMUX) +/* Bidirectional Enable */ +#define Pin_HWVersion_BIE (* (reg8 *) Pin_HWVersion__BIE) +/* Bit-mask for Aliased Register Access */ +#define Pin_HWVersion_BIT_MASK (* (reg8 *) Pin_HWVersion__BIT_MASK) +/* Bypass Enable */ +#define Pin_HWVersion_BYP (* (reg8 *) Pin_HWVersion__BYP) +/* Port wide control signals */ +#define Pin_HWVersion_CTL (* (reg8 *) Pin_HWVersion__CTL) +/* Drive Modes */ +#define Pin_HWVersion_DM0 (* (reg8 *) Pin_HWVersion__DM0) +#define Pin_HWVersion_DM1 (* (reg8 *) Pin_HWVersion__DM1) +#define Pin_HWVersion_DM2 (* (reg8 *) Pin_HWVersion__DM2) +/* Input Buffer Disable Override */ +#define Pin_HWVersion_INP_DIS (* (reg8 *) Pin_HWVersion__INP_DIS) +/* LCD Common or Segment Drive */ +#define Pin_HWVersion_LCD_COM_SEG (* (reg8 *) Pin_HWVersion__LCD_COM_SEG) +/* Enable Segment LCD */ +#define Pin_HWVersion_LCD_EN (* (reg8 *) Pin_HWVersion__LCD_EN) +/* Slew Rate Control */ +#define Pin_HWVersion_SLW (* (reg8 *) Pin_HWVersion__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define Pin_HWVersion_PRTDSI__CAPS_SEL (* (reg8 *) Pin_HWVersion__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define Pin_HWVersion_PRTDSI__DBL_SYNC_IN (* (reg8 *) Pin_HWVersion__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define Pin_HWVersion_PRTDSI__OE_SEL0 (* (reg8 *) Pin_HWVersion__PRTDSI__OE_SEL0) +#define Pin_HWVersion_PRTDSI__OE_SEL1 (* (reg8 *) Pin_HWVersion__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define Pin_HWVersion_PRTDSI__OUT_SEL0 (* (reg8 *) Pin_HWVersion__PRTDSI__OUT_SEL0) +#define Pin_HWVersion_PRTDSI__OUT_SEL1 (* (reg8 *) Pin_HWVersion__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define Pin_HWVersion_PRTDSI__SYNC_OUT (* (reg8 *) Pin_HWVersion__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(Pin_HWVersion__SIO_CFG) + #define Pin_HWVersion_SIO_HYST_EN (* (reg8 *) Pin_HWVersion__SIO_HYST_EN) + #define Pin_HWVersion_SIO_REG_HIFREQ (* (reg8 *) Pin_HWVersion__SIO_REG_HIFREQ) + #define Pin_HWVersion_SIO_CFG (* (reg8 *) Pin_HWVersion__SIO_CFG) + #define Pin_HWVersion_SIO_DIFF (* (reg8 *) Pin_HWVersion__SIO_DIFF) +#endif /* (Pin_HWVersion__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(Pin_HWVersion__INTSTAT) + #define Pin_HWVersion_INTSTAT (* (reg8 *) Pin_HWVersion__INTSTAT) + #define Pin_HWVersion_SNAP (* (reg8 *) Pin_HWVersion__SNAP) + + #define Pin_HWVersion_0_INTTYPE_REG (* (reg8 *) Pin_HWVersion__0__INTTYPE) + #define Pin_HWVersion_1_INTTYPE_REG (* (reg8 *) Pin_HWVersion__1__INTTYPE) + #define Pin_HWVersion_2_INTTYPE_REG (* (reg8 *) Pin_HWVersion__2__INTTYPE) + #define Pin_HWVersion_3_INTTYPE_REG (* (reg8 *) Pin_HWVersion__3__INTTYPE) + #define Pin_HWVersion_4_INTTYPE_REG (* (reg8 *) Pin_HWVersion__4__INTTYPE) +#endif /* (Pin_HWVersion__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_Pin_HWVersion_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_HWVersion_aliases.h b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_HWVersion_aliases.h new file mode 100644 index 0000000000..3d6eb0117f --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_HWVersion_aliases.h @@ -0,0 +1,56 @@ +/******************************************************************************* +* File Name: Pin_HWVersion.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_Pin_HWVersion_ALIASES_H) /* Pins Pin_HWVersion_ALIASES_H */ +#define CY_PINS_Pin_HWVersion_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define Pin_HWVersion_0 (Pin_HWVersion__0__PC) +#define Pin_HWVersion_0_INTR ((uint16)((uint16)0x0001u << Pin_HWVersion__0__SHIFT)) + +#define Pin_HWVersion_1 (Pin_HWVersion__1__PC) +#define Pin_HWVersion_1_INTR ((uint16)((uint16)0x0001u << Pin_HWVersion__1__SHIFT)) + +#define Pin_HWVersion_2 (Pin_HWVersion__2__PC) +#define Pin_HWVersion_2_INTR ((uint16)((uint16)0x0001u << Pin_HWVersion__2__SHIFT)) + +#define Pin_HWVersion_3 (Pin_HWVersion__3__PC) +#define Pin_HWVersion_3_INTR ((uint16)((uint16)0x0001u << Pin_HWVersion__3__SHIFT)) + +#define Pin_HWVersion_4 (Pin_HWVersion__4__PC) +#define Pin_HWVersion_4_INTR ((uint16)((uint16)0x0001u << Pin_HWVersion__4__SHIFT)) + +#define Pin_HWVersion_INTR_ALL ((uint16)(Pin_HWVersion_0_INTR| Pin_HWVersion_1_INTR| Pin_HWVersion_2_INTR| Pin_HWVersion_3_INTR| Pin_HWVersion_4_INTR)) + +#endif /* End Pins Pin_HWVersion_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_UART_Rx.c b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_UART_Rx.c new file mode 100644 index 0000000000..3ced1004e5 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_UART_Rx.c @@ -0,0 +1,234 @@ +/******************************************************************************* +* File Name: Pin_UART_Rx.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "cytypes.h" +#include "Pin_UART_Rx.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + Pin_UART_Rx__PORT == 15 && ((Pin_UART_Rx__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: Pin_UART_Rx_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet Pin_UART_Rx_SUT.c usage_Pin_UART_Rx_Write +*******************************************************************************/ +void Pin_UART_Rx_Write(uint8 value) +{ + uint8 staticBits = (Pin_UART_Rx_DR & (uint8)(~Pin_UART_Rx_MASK)); + Pin_UART_Rx_DR = staticBits | ((uint8)(value << Pin_UART_Rx_SHIFT) & Pin_UART_Rx_MASK); +} + + +/******************************************************************************* +* Function Name: Pin_UART_Rx_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet Pin_UART_Rx_SUT.c usage_Pin_UART_Rx_SetDriveMode +*******************************************************************************/ +void Pin_UART_Rx_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(Pin_UART_Rx_0, mode); +} + + +/******************************************************************************* +* Function Name: Pin_UART_Rx_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet Pin_UART_Rx_SUT.c usage_Pin_UART_Rx_Read +*******************************************************************************/ +uint8 Pin_UART_Rx_Read(void) +{ + return (Pin_UART_Rx_PS & Pin_UART_Rx_MASK) >> Pin_UART_Rx_SHIFT; +} + + +/******************************************************************************* +* Function Name: Pin_UART_Rx_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred Pin_UART_Rx_Read() API because the +* Pin_UART_Rx_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet Pin_UART_Rx_SUT.c usage_Pin_UART_Rx_ReadDataReg +*******************************************************************************/ +uint8 Pin_UART_Rx_ReadDataReg(void) +{ + return (Pin_UART_Rx_DR & Pin_UART_Rx_MASK) >> Pin_UART_Rx_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(Pin_UART_Rx_INTSTAT) + + /******************************************************************************* + * Function Name: Pin_UART_Rx_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use Pin_UART_Rx_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - Pin_UART_Rx_0_INTR (First pin in the list) + * - Pin_UART_Rx_1_INTR (Second pin in the list) + * - ... + * - Pin_UART_Rx_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet Pin_UART_Rx_SUT.c usage_Pin_UART_Rx_SetInterruptMode + *******************************************************************************/ + void Pin_UART_Rx_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & Pin_UART_Rx_0_INTR) != 0u) + { + Pin_UART_Rx_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: Pin_UART_Rx_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet Pin_UART_Rx_SUT.c usage_Pin_UART_Rx_ClearInterrupt + *******************************************************************************/ + uint8 Pin_UART_Rx_ClearInterrupt(void) + { + return (Pin_UART_Rx_INTSTAT & Pin_UART_Rx_MASK) >> Pin_UART_Rx_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_UART_Rx.h b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_UART_Rx.h new file mode 100644 index 0000000000..69d3f748ce --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_UART_Rx.h @@ -0,0 +1,173 @@ +/******************************************************************************* +* File Name: Pin_UART_Rx.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_Pin_UART_Rx_H) /* Pins Pin_UART_Rx_H */ +#define CY_PINS_Pin_UART_Rx_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "Pin_UART_Rx_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + Pin_UART_Rx__PORT == 15 && ((Pin_UART_Rx__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void Pin_UART_Rx_Write(uint8 value); +void Pin_UART_Rx_SetDriveMode(uint8 mode); +uint8 Pin_UART_Rx_ReadDataReg(void); +uint8 Pin_UART_Rx_Read(void); +void Pin_UART_Rx_SetInterruptMode(uint16 position, uint16 mode); +uint8 Pin_UART_Rx_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the Pin_UART_Rx_SetDriveMode() function. + * @{ + */ + #define Pin_UART_Rx_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define Pin_UART_Rx_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define Pin_UART_Rx_DM_RES_UP PIN_DM_RES_UP + #define Pin_UART_Rx_DM_RES_DWN PIN_DM_RES_DWN + #define Pin_UART_Rx_DM_OD_LO PIN_DM_OD_LO + #define Pin_UART_Rx_DM_OD_HI PIN_DM_OD_HI + #define Pin_UART_Rx_DM_STRONG PIN_DM_STRONG + #define Pin_UART_Rx_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define Pin_UART_Rx_MASK Pin_UART_Rx__MASK +#define Pin_UART_Rx_SHIFT Pin_UART_Rx__SHIFT +#define Pin_UART_Rx_WIDTH 1u + +/* Interrupt constants */ +#if defined(Pin_UART_Rx__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in Pin_UART_Rx_SetInterruptMode() function. + * @{ + */ + #define Pin_UART_Rx_INTR_NONE (uint16)(0x0000u) + #define Pin_UART_Rx_INTR_RISING (uint16)(0x0001u) + #define Pin_UART_Rx_INTR_FALLING (uint16)(0x0002u) + #define Pin_UART_Rx_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define Pin_UART_Rx_INTR_MASK (0x01u) +#endif /* (Pin_UART_Rx__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define Pin_UART_Rx_PS (* (reg8 *) Pin_UART_Rx__PS) +/* Data Register */ +#define Pin_UART_Rx_DR (* (reg8 *) Pin_UART_Rx__DR) +/* Port Number */ +#define Pin_UART_Rx_PRT_NUM (* (reg8 *) Pin_UART_Rx__PRT) +/* Connect to Analog Globals */ +#define Pin_UART_Rx_AG (* (reg8 *) Pin_UART_Rx__AG) +/* Analog MUX bux enable */ +#define Pin_UART_Rx_AMUX (* (reg8 *) Pin_UART_Rx__AMUX) +/* Bidirectional Enable */ +#define Pin_UART_Rx_BIE (* (reg8 *) Pin_UART_Rx__BIE) +/* Bit-mask for Aliased Register Access */ +#define Pin_UART_Rx_BIT_MASK (* (reg8 *) Pin_UART_Rx__BIT_MASK) +/* Bypass Enable */ +#define Pin_UART_Rx_BYP (* (reg8 *) Pin_UART_Rx__BYP) +/* Port wide control signals */ +#define Pin_UART_Rx_CTL (* (reg8 *) Pin_UART_Rx__CTL) +/* Drive Modes */ +#define Pin_UART_Rx_DM0 (* (reg8 *) Pin_UART_Rx__DM0) +#define Pin_UART_Rx_DM1 (* (reg8 *) Pin_UART_Rx__DM1) +#define Pin_UART_Rx_DM2 (* (reg8 *) Pin_UART_Rx__DM2) +/* Input Buffer Disable Override */ +#define Pin_UART_Rx_INP_DIS (* (reg8 *) Pin_UART_Rx__INP_DIS) +/* LCD Common or Segment Drive */ +#define Pin_UART_Rx_LCD_COM_SEG (* (reg8 *) Pin_UART_Rx__LCD_COM_SEG) +/* Enable Segment LCD */ +#define Pin_UART_Rx_LCD_EN (* (reg8 *) Pin_UART_Rx__LCD_EN) +/* Slew Rate Control */ +#define Pin_UART_Rx_SLW (* (reg8 *) Pin_UART_Rx__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define Pin_UART_Rx_PRTDSI__CAPS_SEL (* (reg8 *) Pin_UART_Rx__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define Pin_UART_Rx_PRTDSI__DBL_SYNC_IN (* (reg8 *) Pin_UART_Rx__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define Pin_UART_Rx_PRTDSI__OE_SEL0 (* (reg8 *) Pin_UART_Rx__PRTDSI__OE_SEL0) +#define Pin_UART_Rx_PRTDSI__OE_SEL1 (* (reg8 *) Pin_UART_Rx__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define Pin_UART_Rx_PRTDSI__OUT_SEL0 (* (reg8 *) Pin_UART_Rx__PRTDSI__OUT_SEL0) +#define Pin_UART_Rx_PRTDSI__OUT_SEL1 (* (reg8 *) Pin_UART_Rx__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define Pin_UART_Rx_PRTDSI__SYNC_OUT (* (reg8 *) Pin_UART_Rx__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(Pin_UART_Rx__SIO_CFG) + #define Pin_UART_Rx_SIO_HYST_EN (* (reg8 *) Pin_UART_Rx__SIO_HYST_EN) + #define Pin_UART_Rx_SIO_REG_HIFREQ (* (reg8 *) Pin_UART_Rx__SIO_REG_HIFREQ) + #define Pin_UART_Rx_SIO_CFG (* (reg8 *) Pin_UART_Rx__SIO_CFG) + #define Pin_UART_Rx_SIO_DIFF (* (reg8 *) Pin_UART_Rx__SIO_DIFF) +#endif /* (Pin_UART_Rx__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(Pin_UART_Rx__INTSTAT) + #define Pin_UART_Rx_INTSTAT (* (reg8 *) Pin_UART_Rx__INTSTAT) + #define Pin_UART_Rx_SNAP (* (reg8 *) Pin_UART_Rx__SNAP) + + #define Pin_UART_Rx_0_INTTYPE_REG (* (reg8 *) Pin_UART_Rx__0__INTTYPE) +#endif /* (Pin_UART_Rx__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_Pin_UART_Rx_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_UART_Rx_aliases.h b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_UART_Rx_aliases.h new file mode 100644 index 0000000000..9db21a72c8 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_UART_Rx_aliases.h @@ -0,0 +1,44 @@ +/******************************************************************************* +* File Name: Pin_UART_Rx.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_Pin_UART_Rx_ALIASES_H) /* Pins Pin_UART_Rx_ALIASES_H */ +#define CY_PINS_Pin_UART_Rx_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define Pin_UART_Rx_0 (Pin_UART_Rx__0__PC) +#define Pin_UART_Rx_0_INTR ((uint16)((uint16)0x0001u << Pin_UART_Rx__0__SHIFT)) + +#define Pin_UART_Rx_INTR_ALL ((uint16)(Pin_UART_Rx_0_INTR)) + +#endif /* End Pins Pin_UART_Rx_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_UART_Tx.c b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_UART_Tx.c new file mode 100644 index 0000000000..0b06bae231 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_UART_Tx.c @@ -0,0 +1,234 @@ +/******************************************************************************* +* File Name: Pin_UART_Tx.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "cytypes.h" +#include "Pin_UART_Tx.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + Pin_UART_Tx__PORT == 15 && ((Pin_UART_Tx__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: Pin_UART_Tx_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet Pin_UART_Tx_SUT.c usage_Pin_UART_Tx_Write +*******************************************************************************/ +void Pin_UART_Tx_Write(uint8 value) +{ + uint8 staticBits = (Pin_UART_Tx_DR & (uint8)(~Pin_UART_Tx_MASK)); + Pin_UART_Tx_DR = staticBits | ((uint8)(value << Pin_UART_Tx_SHIFT) & Pin_UART_Tx_MASK); +} + + +/******************************************************************************* +* Function Name: Pin_UART_Tx_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet Pin_UART_Tx_SUT.c usage_Pin_UART_Tx_SetDriveMode +*******************************************************************************/ +void Pin_UART_Tx_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(Pin_UART_Tx_0, mode); +} + + +/******************************************************************************* +* Function Name: Pin_UART_Tx_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet Pin_UART_Tx_SUT.c usage_Pin_UART_Tx_Read +*******************************************************************************/ +uint8 Pin_UART_Tx_Read(void) +{ + return (Pin_UART_Tx_PS & Pin_UART_Tx_MASK) >> Pin_UART_Tx_SHIFT; +} + + +/******************************************************************************* +* Function Name: Pin_UART_Tx_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred Pin_UART_Tx_Read() API because the +* Pin_UART_Tx_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet Pin_UART_Tx_SUT.c usage_Pin_UART_Tx_ReadDataReg +*******************************************************************************/ +uint8 Pin_UART_Tx_ReadDataReg(void) +{ + return (Pin_UART_Tx_DR & Pin_UART_Tx_MASK) >> Pin_UART_Tx_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(Pin_UART_Tx_INTSTAT) + + /******************************************************************************* + * Function Name: Pin_UART_Tx_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use Pin_UART_Tx_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - Pin_UART_Tx_0_INTR (First pin in the list) + * - Pin_UART_Tx_1_INTR (Second pin in the list) + * - ... + * - Pin_UART_Tx_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet Pin_UART_Tx_SUT.c usage_Pin_UART_Tx_SetInterruptMode + *******************************************************************************/ + void Pin_UART_Tx_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & Pin_UART_Tx_0_INTR) != 0u) + { + Pin_UART_Tx_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: Pin_UART_Tx_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet Pin_UART_Tx_SUT.c usage_Pin_UART_Tx_ClearInterrupt + *******************************************************************************/ + uint8 Pin_UART_Tx_ClearInterrupt(void) + { + return (Pin_UART_Tx_INTSTAT & Pin_UART_Tx_MASK) >> Pin_UART_Tx_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_UART_Tx.h b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_UART_Tx.h new file mode 100644 index 0000000000..58fd91d285 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_UART_Tx.h @@ -0,0 +1,173 @@ +/******************************************************************************* +* File Name: Pin_UART_Tx.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_Pin_UART_Tx_H) /* Pins Pin_UART_Tx_H */ +#define CY_PINS_Pin_UART_Tx_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "Pin_UART_Tx_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + Pin_UART_Tx__PORT == 15 && ((Pin_UART_Tx__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void Pin_UART_Tx_Write(uint8 value); +void Pin_UART_Tx_SetDriveMode(uint8 mode); +uint8 Pin_UART_Tx_ReadDataReg(void); +uint8 Pin_UART_Tx_Read(void); +void Pin_UART_Tx_SetInterruptMode(uint16 position, uint16 mode); +uint8 Pin_UART_Tx_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the Pin_UART_Tx_SetDriveMode() function. + * @{ + */ + #define Pin_UART_Tx_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define Pin_UART_Tx_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define Pin_UART_Tx_DM_RES_UP PIN_DM_RES_UP + #define Pin_UART_Tx_DM_RES_DWN PIN_DM_RES_DWN + #define Pin_UART_Tx_DM_OD_LO PIN_DM_OD_LO + #define Pin_UART_Tx_DM_OD_HI PIN_DM_OD_HI + #define Pin_UART_Tx_DM_STRONG PIN_DM_STRONG + #define Pin_UART_Tx_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define Pin_UART_Tx_MASK Pin_UART_Tx__MASK +#define Pin_UART_Tx_SHIFT Pin_UART_Tx__SHIFT +#define Pin_UART_Tx_WIDTH 1u + +/* Interrupt constants */ +#if defined(Pin_UART_Tx__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in Pin_UART_Tx_SetInterruptMode() function. + * @{ + */ + #define Pin_UART_Tx_INTR_NONE (uint16)(0x0000u) + #define Pin_UART_Tx_INTR_RISING (uint16)(0x0001u) + #define Pin_UART_Tx_INTR_FALLING (uint16)(0x0002u) + #define Pin_UART_Tx_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define Pin_UART_Tx_INTR_MASK (0x01u) +#endif /* (Pin_UART_Tx__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define Pin_UART_Tx_PS (* (reg8 *) Pin_UART_Tx__PS) +/* Data Register */ +#define Pin_UART_Tx_DR (* (reg8 *) Pin_UART_Tx__DR) +/* Port Number */ +#define Pin_UART_Tx_PRT_NUM (* (reg8 *) Pin_UART_Tx__PRT) +/* Connect to Analog Globals */ +#define Pin_UART_Tx_AG (* (reg8 *) Pin_UART_Tx__AG) +/* Analog MUX bux enable */ +#define Pin_UART_Tx_AMUX (* (reg8 *) Pin_UART_Tx__AMUX) +/* Bidirectional Enable */ +#define Pin_UART_Tx_BIE (* (reg8 *) Pin_UART_Tx__BIE) +/* Bit-mask for Aliased Register Access */ +#define Pin_UART_Tx_BIT_MASK (* (reg8 *) Pin_UART_Tx__BIT_MASK) +/* Bypass Enable */ +#define Pin_UART_Tx_BYP (* (reg8 *) Pin_UART_Tx__BYP) +/* Port wide control signals */ +#define Pin_UART_Tx_CTL (* (reg8 *) Pin_UART_Tx__CTL) +/* Drive Modes */ +#define Pin_UART_Tx_DM0 (* (reg8 *) Pin_UART_Tx__DM0) +#define Pin_UART_Tx_DM1 (* (reg8 *) Pin_UART_Tx__DM1) +#define Pin_UART_Tx_DM2 (* (reg8 *) Pin_UART_Tx__DM2) +/* Input Buffer Disable Override */ +#define Pin_UART_Tx_INP_DIS (* (reg8 *) Pin_UART_Tx__INP_DIS) +/* LCD Common or Segment Drive */ +#define Pin_UART_Tx_LCD_COM_SEG (* (reg8 *) Pin_UART_Tx__LCD_COM_SEG) +/* Enable Segment LCD */ +#define Pin_UART_Tx_LCD_EN (* (reg8 *) Pin_UART_Tx__LCD_EN) +/* Slew Rate Control */ +#define Pin_UART_Tx_SLW (* (reg8 *) Pin_UART_Tx__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define Pin_UART_Tx_PRTDSI__CAPS_SEL (* (reg8 *) Pin_UART_Tx__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define Pin_UART_Tx_PRTDSI__DBL_SYNC_IN (* (reg8 *) Pin_UART_Tx__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define Pin_UART_Tx_PRTDSI__OE_SEL0 (* (reg8 *) Pin_UART_Tx__PRTDSI__OE_SEL0) +#define Pin_UART_Tx_PRTDSI__OE_SEL1 (* (reg8 *) Pin_UART_Tx__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define Pin_UART_Tx_PRTDSI__OUT_SEL0 (* (reg8 *) Pin_UART_Tx__PRTDSI__OUT_SEL0) +#define Pin_UART_Tx_PRTDSI__OUT_SEL1 (* (reg8 *) Pin_UART_Tx__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define Pin_UART_Tx_PRTDSI__SYNC_OUT (* (reg8 *) Pin_UART_Tx__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(Pin_UART_Tx__SIO_CFG) + #define Pin_UART_Tx_SIO_HYST_EN (* (reg8 *) Pin_UART_Tx__SIO_HYST_EN) + #define Pin_UART_Tx_SIO_REG_HIFREQ (* (reg8 *) Pin_UART_Tx__SIO_REG_HIFREQ) + #define Pin_UART_Tx_SIO_CFG (* (reg8 *) Pin_UART_Tx__SIO_CFG) + #define Pin_UART_Tx_SIO_DIFF (* (reg8 *) Pin_UART_Tx__SIO_DIFF) +#endif /* (Pin_UART_Tx__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(Pin_UART_Tx__INTSTAT) + #define Pin_UART_Tx_INTSTAT (* (reg8 *) Pin_UART_Tx__INTSTAT) + #define Pin_UART_Tx_SNAP (* (reg8 *) Pin_UART_Tx__SNAP) + + #define Pin_UART_Tx_0_INTTYPE_REG (* (reg8 *) Pin_UART_Tx__0__INTTYPE) +#endif /* (Pin_UART_Tx__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_Pin_UART_Tx_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_UART_Tx_aliases.h b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_UART_Tx_aliases.h new file mode 100644 index 0000000000..103df045ca --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_UART_Tx_aliases.h @@ -0,0 +1,44 @@ +/******************************************************************************* +* File Name: Pin_UART_Tx.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_Pin_UART_Tx_ALIASES_H) /* Pins Pin_UART_Tx_ALIASES_H */ +#define CY_PINS_Pin_UART_Tx_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define Pin_UART_Tx_0 (Pin_UART_Tx__0__PC) +#define Pin_UART_Tx_0_INTR ((uint16)((uint16)0x0001u << Pin_UART_Tx__0__SHIFT)) + +#define Pin_UART_Tx_INTR_ALL ((uint16)(Pin_UART_Tx_0_INTR)) + +#endif /* End Pins Pin_UART_Tx_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_VoltageEn.c b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_VoltageEn.c new file mode 100644 index 0000000000..092940b5c5 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_VoltageEn.c @@ -0,0 +1,234 @@ +/******************************************************************************* +* File Name: Pin_VoltageEn.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "cytypes.h" +#include "Pin_VoltageEn.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + Pin_VoltageEn__PORT == 15 && ((Pin_VoltageEn__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: Pin_VoltageEn_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet Pin_VoltageEn_SUT.c usage_Pin_VoltageEn_Write +*******************************************************************************/ +void Pin_VoltageEn_Write(uint8 value) +{ + uint8 staticBits = (Pin_VoltageEn_DR & (uint8)(~Pin_VoltageEn_MASK)); + Pin_VoltageEn_DR = staticBits | ((uint8)(value << Pin_VoltageEn_SHIFT) & Pin_VoltageEn_MASK); +} + + +/******************************************************************************* +* Function Name: Pin_VoltageEn_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet Pin_VoltageEn_SUT.c usage_Pin_VoltageEn_SetDriveMode +*******************************************************************************/ +void Pin_VoltageEn_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(Pin_VoltageEn_0, mode); +} + + +/******************************************************************************* +* Function Name: Pin_VoltageEn_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet Pin_VoltageEn_SUT.c usage_Pin_VoltageEn_Read +*******************************************************************************/ +uint8 Pin_VoltageEn_Read(void) +{ + return (Pin_VoltageEn_PS & Pin_VoltageEn_MASK) >> Pin_VoltageEn_SHIFT; +} + + +/******************************************************************************* +* Function Name: Pin_VoltageEn_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred Pin_VoltageEn_Read() API because the +* Pin_VoltageEn_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet Pin_VoltageEn_SUT.c usage_Pin_VoltageEn_ReadDataReg +*******************************************************************************/ +uint8 Pin_VoltageEn_ReadDataReg(void) +{ + return (Pin_VoltageEn_DR & Pin_VoltageEn_MASK) >> Pin_VoltageEn_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(Pin_VoltageEn_INTSTAT) + + /******************************************************************************* + * Function Name: Pin_VoltageEn_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use Pin_VoltageEn_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - Pin_VoltageEn_0_INTR (First pin in the list) + * - Pin_VoltageEn_1_INTR (Second pin in the list) + * - ... + * - Pin_VoltageEn_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet Pin_VoltageEn_SUT.c usage_Pin_VoltageEn_SetInterruptMode + *******************************************************************************/ + void Pin_VoltageEn_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & Pin_VoltageEn_0_INTR) != 0u) + { + Pin_VoltageEn_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: Pin_VoltageEn_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet Pin_VoltageEn_SUT.c usage_Pin_VoltageEn_ClearInterrupt + *******************************************************************************/ + uint8 Pin_VoltageEn_ClearInterrupt(void) + { + return (Pin_VoltageEn_INTSTAT & Pin_VoltageEn_MASK) >> Pin_VoltageEn_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_VoltageEn.h b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_VoltageEn.h new file mode 100644 index 0000000000..2767f2cade --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_VoltageEn.h @@ -0,0 +1,173 @@ +/******************************************************************************* +* File Name: Pin_VoltageEn.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_Pin_VoltageEn_H) /* Pins Pin_VoltageEn_H */ +#define CY_PINS_Pin_VoltageEn_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "Pin_VoltageEn_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + Pin_VoltageEn__PORT == 15 && ((Pin_VoltageEn__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void Pin_VoltageEn_Write(uint8 value); +void Pin_VoltageEn_SetDriveMode(uint8 mode); +uint8 Pin_VoltageEn_ReadDataReg(void); +uint8 Pin_VoltageEn_Read(void); +void Pin_VoltageEn_SetInterruptMode(uint16 position, uint16 mode); +uint8 Pin_VoltageEn_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the Pin_VoltageEn_SetDriveMode() function. + * @{ + */ + #define Pin_VoltageEn_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define Pin_VoltageEn_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define Pin_VoltageEn_DM_RES_UP PIN_DM_RES_UP + #define Pin_VoltageEn_DM_RES_DWN PIN_DM_RES_DWN + #define Pin_VoltageEn_DM_OD_LO PIN_DM_OD_LO + #define Pin_VoltageEn_DM_OD_HI PIN_DM_OD_HI + #define Pin_VoltageEn_DM_STRONG PIN_DM_STRONG + #define Pin_VoltageEn_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define Pin_VoltageEn_MASK Pin_VoltageEn__MASK +#define Pin_VoltageEn_SHIFT Pin_VoltageEn__SHIFT +#define Pin_VoltageEn_WIDTH 1u + +/* Interrupt constants */ +#if defined(Pin_VoltageEn__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in Pin_VoltageEn_SetInterruptMode() function. + * @{ + */ + #define Pin_VoltageEn_INTR_NONE (uint16)(0x0000u) + #define Pin_VoltageEn_INTR_RISING (uint16)(0x0001u) + #define Pin_VoltageEn_INTR_FALLING (uint16)(0x0002u) + #define Pin_VoltageEn_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define Pin_VoltageEn_INTR_MASK (0x01u) +#endif /* (Pin_VoltageEn__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define Pin_VoltageEn_PS (* (reg8 *) Pin_VoltageEn__PS) +/* Data Register */ +#define Pin_VoltageEn_DR (* (reg8 *) Pin_VoltageEn__DR) +/* Port Number */ +#define Pin_VoltageEn_PRT_NUM (* (reg8 *) Pin_VoltageEn__PRT) +/* Connect to Analog Globals */ +#define Pin_VoltageEn_AG (* (reg8 *) Pin_VoltageEn__AG) +/* Analog MUX bux enable */ +#define Pin_VoltageEn_AMUX (* (reg8 *) Pin_VoltageEn__AMUX) +/* Bidirectional Enable */ +#define Pin_VoltageEn_BIE (* (reg8 *) Pin_VoltageEn__BIE) +/* Bit-mask for Aliased Register Access */ +#define Pin_VoltageEn_BIT_MASK (* (reg8 *) Pin_VoltageEn__BIT_MASK) +/* Bypass Enable */ +#define Pin_VoltageEn_BYP (* (reg8 *) Pin_VoltageEn__BYP) +/* Port wide control signals */ +#define Pin_VoltageEn_CTL (* (reg8 *) Pin_VoltageEn__CTL) +/* Drive Modes */ +#define Pin_VoltageEn_DM0 (* (reg8 *) Pin_VoltageEn__DM0) +#define Pin_VoltageEn_DM1 (* (reg8 *) Pin_VoltageEn__DM1) +#define Pin_VoltageEn_DM2 (* (reg8 *) Pin_VoltageEn__DM2) +/* Input Buffer Disable Override */ +#define Pin_VoltageEn_INP_DIS (* (reg8 *) Pin_VoltageEn__INP_DIS) +/* LCD Common or Segment Drive */ +#define Pin_VoltageEn_LCD_COM_SEG (* (reg8 *) Pin_VoltageEn__LCD_COM_SEG) +/* Enable Segment LCD */ +#define Pin_VoltageEn_LCD_EN (* (reg8 *) Pin_VoltageEn__LCD_EN) +/* Slew Rate Control */ +#define Pin_VoltageEn_SLW (* (reg8 *) Pin_VoltageEn__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define Pin_VoltageEn_PRTDSI__CAPS_SEL (* (reg8 *) Pin_VoltageEn__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define Pin_VoltageEn_PRTDSI__DBL_SYNC_IN (* (reg8 *) Pin_VoltageEn__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define Pin_VoltageEn_PRTDSI__OE_SEL0 (* (reg8 *) Pin_VoltageEn__PRTDSI__OE_SEL0) +#define Pin_VoltageEn_PRTDSI__OE_SEL1 (* (reg8 *) Pin_VoltageEn__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define Pin_VoltageEn_PRTDSI__OUT_SEL0 (* (reg8 *) Pin_VoltageEn__PRTDSI__OUT_SEL0) +#define Pin_VoltageEn_PRTDSI__OUT_SEL1 (* (reg8 *) Pin_VoltageEn__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define Pin_VoltageEn_PRTDSI__SYNC_OUT (* (reg8 *) Pin_VoltageEn__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(Pin_VoltageEn__SIO_CFG) + #define Pin_VoltageEn_SIO_HYST_EN (* (reg8 *) Pin_VoltageEn__SIO_HYST_EN) + #define Pin_VoltageEn_SIO_REG_HIFREQ (* (reg8 *) Pin_VoltageEn__SIO_REG_HIFREQ) + #define Pin_VoltageEn_SIO_CFG (* (reg8 *) Pin_VoltageEn__SIO_CFG) + #define Pin_VoltageEn_SIO_DIFF (* (reg8 *) Pin_VoltageEn__SIO_DIFF) +#endif /* (Pin_VoltageEn__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(Pin_VoltageEn__INTSTAT) + #define Pin_VoltageEn_INTSTAT (* (reg8 *) Pin_VoltageEn__INTSTAT) + #define Pin_VoltageEn_SNAP (* (reg8 *) Pin_VoltageEn__SNAP) + + #define Pin_VoltageEn_0_INTTYPE_REG (* (reg8 *) Pin_VoltageEn__0__INTTYPE) +#endif /* (Pin_VoltageEn__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_Pin_VoltageEn_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_VoltageEn_aliases.h b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_VoltageEn_aliases.h new file mode 100644 index 0000000000..cc068529c6 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Pin_VoltageEn_aliases.h @@ -0,0 +1,44 @@ +/******************************************************************************* +* File Name: Pin_VoltageEn.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_Pin_VoltageEn_ALIASES_H) /* Pins Pin_VoltageEn_ALIASES_H */ +#define CY_PINS_Pin_VoltageEn_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define Pin_VoltageEn_0 (Pin_VoltageEn__0__PC) +#define Pin_VoltageEn_0_INTR ((uint16)((uint16)0x0001u << Pin_VoltageEn__0__SHIFT)) + +#define Pin_VoltageEn_INTR_ALL ((uint16)(Pin_VoltageEn_0_INTR)) + +#endif /* End Pins Pin_VoltageEn_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/SWDCLK.h b/source/hic_hal/cypress/psoc5lp/PSoC5/SWDCLK.h new file mode 100644 index 0000000000..384f9c4dab --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/SWDCLK.h @@ -0,0 +1,173 @@ +/******************************************************************************* +* File Name: SWDCLK.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_SWDCLK_H) /* Pins SWDCLK_H */ +#define CY_PINS_SWDCLK_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SWDCLK_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SWDCLK__PORT == 15 && ((SWDCLK__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void SWDCLK_Write(uint8 value); +void SWDCLK_SetDriveMode(uint8 mode); +uint8 SWDCLK_ReadDataReg(void); +uint8 SWDCLK_Read(void); +void SWDCLK_SetInterruptMode(uint16 position, uint16 mode); +uint8 SWDCLK_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SWDCLK_SetDriveMode() function. + * @{ + */ + #define SWDCLK_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SWDCLK_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SWDCLK_DM_RES_UP PIN_DM_RES_UP + #define SWDCLK_DM_RES_DWN PIN_DM_RES_DWN + #define SWDCLK_DM_OD_LO PIN_DM_OD_LO + #define SWDCLK_DM_OD_HI PIN_DM_OD_HI + #define SWDCLK_DM_STRONG PIN_DM_STRONG + #define SWDCLK_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define SWDCLK_MASK SWDCLK__MASK +#define SWDCLK_SHIFT SWDCLK__SHIFT +#define SWDCLK_WIDTH 1u + +/* Interrupt constants */ +#if defined(SWDCLK__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SWDCLK_SetInterruptMode() function. + * @{ + */ + #define SWDCLK_INTR_NONE (uint16)(0x0000u) + #define SWDCLK_INTR_RISING (uint16)(0x0001u) + #define SWDCLK_INTR_FALLING (uint16)(0x0002u) + #define SWDCLK_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SWDCLK_INTR_MASK (0x01u) +#endif /* (SWDCLK__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SWDCLK_PS (* (reg8 *) SWDCLK__PS) +/* Data Register */ +#define SWDCLK_DR (* (reg8 *) SWDCLK__DR) +/* Port Number */ +#define SWDCLK_PRT_NUM (* (reg8 *) SWDCLK__PRT) +/* Connect to Analog Globals */ +#define SWDCLK_AG (* (reg8 *) SWDCLK__AG) +/* Analog MUX bux enable */ +#define SWDCLK_AMUX (* (reg8 *) SWDCLK__AMUX) +/* Bidirectional Enable */ +#define SWDCLK_BIE (* (reg8 *) SWDCLK__BIE) +/* Bit-mask for Aliased Register Access */ +#define SWDCLK_BIT_MASK (* (reg8 *) SWDCLK__BIT_MASK) +/* Bypass Enable */ +#define SWDCLK_BYP (* (reg8 *) SWDCLK__BYP) +/* Port wide control signals */ +#define SWDCLK_CTL (* (reg8 *) SWDCLK__CTL) +/* Drive Modes */ +#define SWDCLK_DM0 (* (reg8 *) SWDCLK__DM0) +#define SWDCLK_DM1 (* (reg8 *) SWDCLK__DM1) +#define SWDCLK_DM2 (* (reg8 *) SWDCLK__DM2) +/* Input Buffer Disable Override */ +#define SWDCLK_INP_DIS (* (reg8 *) SWDCLK__INP_DIS) +/* LCD Common or Segment Drive */ +#define SWDCLK_LCD_COM_SEG (* (reg8 *) SWDCLK__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SWDCLK_LCD_EN (* (reg8 *) SWDCLK__LCD_EN) +/* Slew Rate Control */ +#define SWDCLK_SLW (* (reg8 *) SWDCLK__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SWDCLK_PRTDSI__CAPS_SEL (* (reg8 *) SWDCLK__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SWDCLK_PRTDSI__DBL_SYNC_IN (* (reg8 *) SWDCLK__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SWDCLK_PRTDSI__OE_SEL0 (* (reg8 *) SWDCLK__PRTDSI__OE_SEL0) +#define SWDCLK_PRTDSI__OE_SEL1 (* (reg8 *) SWDCLK__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SWDCLK_PRTDSI__OUT_SEL0 (* (reg8 *) SWDCLK__PRTDSI__OUT_SEL0) +#define SWDCLK_PRTDSI__OUT_SEL1 (* (reg8 *) SWDCLK__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SWDCLK_PRTDSI__SYNC_OUT (* (reg8 *) SWDCLK__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(SWDCLK__SIO_CFG) + #define SWDCLK_SIO_HYST_EN (* (reg8 *) SWDCLK__SIO_HYST_EN) + #define SWDCLK_SIO_REG_HIFREQ (* (reg8 *) SWDCLK__SIO_REG_HIFREQ) + #define SWDCLK_SIO_CFG (* (reg8 *) SWDCLK__SIO_CFG) + #define SWDCLK_SIO_DIFF (* (reg8 *) SWDCLK__SIO_DIFF) +#endif /* (SWDCLK__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(SWDCLK__INTSTAT) + #define SWDCLK_INTSTAT (* (reg8 *) SWDCLK__INTSTAT) + #define SWDCLK_SNAP (* (reg8 *) SWDCLK__SNAP) + + #define SWDCLK_0_INTTYPE_REG (* (reg8 *) SWDCLK__0__INTTYPE) +#endif /* (SWDCLK__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SWDCLK_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/SWDCLK_aliases.h b/source/hic_hal/cypress/psoc5lp/PSoC5/SWDCLK_aliases.h new file mode 100644 index 0000000000..8bff1466f2 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/SWDCLK_aliases.h @@ -0,0 +1,44 @@ +/******************************************************************************* +* File Name: SWDCLK.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_SWDCLK_ALIASES_H) /* Pins SWDCLK_ALIASES_H */ +#define CY_PINS_SWDCLK_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define SWDCLK_0 (SWDCLK__0__PC) +#define SWDCLK_0_INTR ((uint16)((uint16)0x0001u << SWDCLK__0__SHIFT)) + +#define SWDCLK_INTR_ALL ((uint16)(SWDCLK_0_INTR)) + +#endif /* End Pins SWDCLK_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/SWDIO.h b/source/hic_hal/cypress/psoc5lp/PSoC5/SWDIO.h new file mode 100644 index 0000000000..9dad74d3c3 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/SWDIO.h @@ -0,0 +1,173 @@ +/******************************************************************************* +* File Name: SWDIO.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_SWDIO_H) /* Pins SWDIO_H */ +#define CY_PINS_SWDIO_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SWDIO_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SWDIO__PORT == 15 && ((SWDIO__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void SWDIO_Write(uint8 value); +void SWDIO_SetDriveMode(uint8 mode); +uint8 SWDIO_ReadDataReg(void); +uint8 SWDIO_Read(void); +void SWDIO_SetInterruptMode(uint16 position, uint16 mode); +uint8 SWDIO_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SWDIO_SetDriveMode() function. + * @{ + */ + #define SWDIO_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SWDIO_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SWDIO_DM_RES_UP PIN_DM_RES_UP + #define SWDIO_DM_RES_DWN PIN_DM_RES_DWN + #define SWDIO_DM_OD_LO PIN_DM_OD_LO + #define SWDIO_DM_OD_HI PIN_DM_OD_HI + #define SWDIO_DM_STRONG PIN_DM_STRONG + #define SWDIO_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define SWDIO_MASK SWDIO__MASK +#define SWDIO_SHIFT SWDIO__SHIFT +#define SWDIO_WIDTH 1u + +/* Interrupt constants */ +#if defined(SWDIO__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SWDIO_SetInterruptMode() function. + * @{ + */ + #define SWDIO_INTR_NONE (uint16)(0x0000u) + #define SWDIO_INTR_RISING (uint16)(0x0001u) + #define SWDIO_INTR_FALLING (uint16)(0x0002u) + #define SWDIO_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SWDIO_INTR_MASK (0x01u) +#endif /* (SWDIO__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SWDIO_PS (* (reg8 *) SWDIO__PS) +/* Data Register */ +#define SWDIO_DR (* (reg8 *) SWDIO__DR) +/* Port Number */ +#define SWDIO_PRT_NUM (* (reg8 *) SWDIO__PRT) +/* Connect to Analog Globals */ +#define SWDIO_AG (* (reg8 *) SWDIO__AG) +/* Analog MUX bux enable */ +#define SWDIO_AMUX (* (reg8 *) SWDIO__AMUX) +/* Bidirectional Enable */ +#define SWDIO_BIE (* (reg8 *) SWDIO__BIE) +/* Bit-mask for Aliased Register Access */ +#define SWDIO_BIT_MASK (* (reg8 *) SWDIO__BIT_MASK) +/* Bypass Enable */ +#define SWDIO_BYP (* (reg8 *) SWDIO__BYP) +/* Port wide control signals */ +#define SWDIO_CTL (* (reg8 *) SWDIO__CTL) +/* Drive Modes */ +#define SWDIO_DM0 (* (reg8 *) SWDIO__DM0) +#define SWDIO_DM1 (* (reg8 *) SWDIO__DM1) +#define SWDIO_DM2 (* (reg8 *) SWDIO__DM2) +/* Input Buffer Disable Override */ +#define SWDIO_INP_DIS (* (reg8 *) SWDIO__INP_DIS) +/* LCD Common or Segment Drive */ +#define SWDIO_LCD_COM_SEG (* (reg8 *) SWDIO__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SWDIO_LCD_EN (* (reg8 *) SWDIO__LCD_EN) +/* Slew Rate Control */ +#define SWDIO_SLW (* (reg8 *) SWDIO__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SWDIO_PRTDSI__CAPS_SEL (* (reg8 *) SWDIO__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SWDIO_PRTDSI__DBL_SYNC_IN (* (reg8 *) SWDIO__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SWDIO_PRTDSI__OE_SEL0 (* (reg8 *) SWDIO__PRTDSI__OE_SEL0) +#define SWDIO_PRTDSI__OE_SEL1 (* (reg8 *) SWDIO__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SWDIO_PRTDSI__OUT_SEL0 (* (reg8 *) SWDIO__PRTDSI__OUT_SEL0) +#define SWDIO_PRTDSI__OUT_SEL1 (* (reg8 *) SWDIO__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SWDIO_PRTDSI__SYNC_OUT (* (reg8 *) SWDIO__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(SWDIO__SIO_CFG) + #define SWDIO_SIO_HYST_EN (* (reg8 *) SWDIO__SIO_HYST_EN) + #define SWDIO_SIO_REG_HIFREQ (* (reg8 *) SWDIO__SIO_REG_HIFREQ) + #define SWDIO_SIO_CFG (* (reg8 *) SWDIO__SIO_CFG) + #define SWDIO_SIO_DIFF (* (reg8 *) SWDIO__SIO_DIFF) +#endif /* (SWDIO__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(SWDIO__INTSTAT) + #define SWDIO_INTSTAT (* (reg8 *) SWDIO__INTSTAT) + #define SWDIO_SNAP (* (reg8 *) SWDIO__SNAP) + + #define SWDIO_0_INTTYPE_REG (* (reg8 *) SWDIO__0__INTTYPE) +#endif /* (SWDIO__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SWDIO_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/SWDIO_aliases.h b/source/hic_hal/cypress/psoc5lp/PSoC5/SWDIO_aliases.h new file mode 100644 index 0000000000..1303259b4b --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/SWDIO_aliases.h @@ -0,0 +1,44 @@ +/******************************************************************************* +* File Name: SWDIO.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_SWDIO_ALIASES_H) /* Pins SWDIO_ALIASES_H */ +#define CY_PINS_SWDIO_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define SWDIO_0 (SWDIO__0__PC) +#define SWDIO_0_INTR ((uint16)((uint16)0x0001u << SWDIO__0__SHIFT)) + +#define SWDIO_INTR_ALL ((uint16)(SWDIO_0_INTR)) + +#endif /* End Pins SWDIO_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/SWDXRES.h b/source/hic_hal/cypress/psoc5lp/PSoC5/SWDXRES.h new file mode 100644 index 0000000000..e2b89c8428 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/SWDXRES.h @@ -0,0 +1,173 @@ +/******************************************************************************* +* File Name: SWDXRES.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_SWDXRES_H) /* Pins SWDXRES_H */ +#define CY_PINS_SWDXRES_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SWDXRES_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SWDXRES__PORT == 15 && ((SWDXRES__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void SWDXRES_Write(uint8 value); +void SWDXRES_SetDriveMode(uint8 mode); +uint8 SWDXRES_ReadDataReg(void); +uint8 SWDXRES_Read(void); +void SWDXRES_SetInterruptMode(uint16 position, uint16 mode); +uint8 SWDXRES_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SWDXRES_SetDriveMode() function. + * @{ + */ + #define SWDXRES_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SWDXRES_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SWDXRES_DM_RES_UP PIN_DM_RES_UP + #define SWDXRES_DM_RES_DWN PIN_DM_RES_DWN + #define SWDXRES_DM_OD_LO PIN_DM_OD_LO + #define SWDXRES_DM_OD_HI PIN_DM_OD_HI + #define SWDXRES_DM_STRONG PIN_DM_STRONG + #define SWDXRES_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define SWDXRES_MASK SWDXRES__MASK +#define SWDXRES_SHIFT SWDXRES__SHIFT +#define SWDXRES_WIDTH 1u + +/* Interrupt constants */ +#if defined(SWDXRES__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SWDXRES_SetInterruptMode() function. + * @{ + */ + #define SWDXRES_INTR_NONE (uint16)(0x0000u) + #define SWDXRES_INTR_RISING (uint16)(0x0001u) + #define SWDXRES_INTR_FALLING (uint16)(0x0002u) + #define SWDXRES_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SWDXRES_INTR_MASK (0x01u) +#endif /* (SWDXRES__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SWDXRES_PS (* (reg8 *) SWDXRES__PS) +/* Data Register */ +#define SWDXRES_DR (* (reg8 *) SWDXRES__DR) +/* Port Number */ +#define SWDXRES_PRT_NUM (* (reg8 *) SWDXRES__PRT) +/* Connect to Analog Globals */ +#define SWDXRES_AG (* (reg8 *) SWDXRES__AG) +/* Analog MUX bux enable */ +#define SWDXRES_AMUX (* (reg8 *) SWDXRES__AMUX) +/* Bidirectional Enable */ +#define SWDXRES_BIE (* (reg8 *) SWDXRES__BIE) +/* Bit-mask for Aliased Register Access */ +#define SWDXRES_BIT_MASK (* (reg8 *) SWDXRES__BIT_MASK) +/* Bypass Enable */ +#define SWDXRES_BYP (* (reg8 *) SWDXRES__BYP) +/* Port wide control signals */ +#define SWDXRES_CTL (* (reg8 *) SWDXRES__CTL) +/* Drive Modes */ +#define SWDXRES_DM0 (* (reg8 *) SWDXRES__DM0) +#define SWDXRES_DM1 (* (reg8 *) SWDXRES__DM1) +#define SWDXRES_DM2 (* (reg8 *) SWDXRES__DM2) +/* Input Buffer Disable Override */ +#define SWDXRES_INP_DIS (* (reg8 *) SWDXRES__INP_DIS) +/* LCD Common or Segment Drive */ +#define SWDXRES_LCD_COM_SEG (* (reg8 *) SWDXRES__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SWDXRES_LCD_EN (* (reg8 *) SWDXRES__LCD_EN) +/* Slew Rate Control */ +#define SWDXRES_SLW (* (reg8 *) SWDXRES__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SWDXRES_PRTDSI__CAPS_SEL (* (reg8 *) SWDXRES__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SWDXRES_PRTDSI__DBL_SYNC_IN (* (reg8 *) SWDXRES__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SWDXRES_PRTDSI__OE_SEL0 (* (reg8 *) SWDXRES__PRTDSI__OE_SEL0) +#define SWDXRES_PRTDSI__OE_SEL1 (* (reg8 *) SWDXRES__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SWDXRES_PRTDSI__OUT_SEL0 (* (reg8 *) SWDXRES__PRTDSI__OUT_SEL0) +#define SWDXRES_PRTDSI__OUT_SEL1 (* (reg8 *) SWDXRES__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SWDXRES_PRTDSI__SYNC_OUT (* (reg8 *) SWDXRES__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(SWDXRES__SIO_CFG) + #define SWDXRES_SIO_HYST_EN (* (reg8 *) SWDXRES__SIO_HYST_EN) + #define SWDXRES_SIO_REG_HIFREQ (* (reg8 *) SWDXRES__SIO_REG_HIFREQ) + #define SWDXRES_SIO_CFG (* (reg8 *) SWDXRES__SIO_CFG) + #define SWDXRES_SIO_DIFF (* (reg8 *) SWDXRES__SIO_DIFF) +#endif /* (SWDXRES__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(SWDXRES__INTSTAT) + #define SWDXRES_INTSTAT (* (reg8 *) SWDXRES__INTSTAT) + #define SWDXRES_SNAP (* (reg8 *) SWDXRES__SNAP) + + #define SWDXRES_0_INTTYPE_REG (* (reg8 *) SWDXRES__0__INTTYPE) +#endif /* (SWDXRES__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SWDXRES_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/SWDXRES_aliases.h b/source/hic_hal/cypress/psoc5lp/PSoC5/SWDXRES_aliases.h new file mode 100644 index 0000000000..4f0262cf38 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/SWDXRES_aliases.h @@ -0,0 +1,44 @@ +/******************************************************************************* +* File Name: SWDXRES.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_SWDXRES_ALIASES_H) /* Pins SWDXRES_ALIASES_H */ +#define CY_PINS_SWDXRES_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define SWDXRES_0 (SWDXRES__0__PC) +#define SWDXRES_0_INTR ((uint16)((uint16)0x0001u << SWDXRES__0__SHIFT)) + +#define SWDXRES_INTR_ALL ((uint16)(SWDXRES_0_INTR)) + +#endif /* End Pins SWDXRES_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Timer_CSTick.c b/source/hic_hal/cypress/psoc5lp/PSoC5/Timer_CSTick.c new file mode 100644 index 0000000000..ee6bf05034 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Timer_CSTick.c @@ -0,0 +1,782 @@ +/******************************************************************************* +* File Name: Timer_CSTick.c +* Version 2.80 +* +* Description: +* The Timer component consists of a 8, 16, 24 or 32-bit timer with +* a selectable period between 2 and 2^Width - 1. The timer may free run +* or be used as a capture timer as well. The capture can be initiated +* by a positive or negative edge signal as well as via software. +* A trigger input can be programmed to enable the timer on rising edge +* falling edge, either edge or continous run. +* Interrupts may be generated due to a terminal count condition +* or a capture event. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "Timer_CSTick.h" + +uint8 Timer_CSTick_initVar = 0u; + + +/******************************************************************************* +* Function Name: Timer_CSTick_Init +******************************************************************************** +* +* Summary: +* Initialize to the schematic state +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Timer_CSTick_Init(void) +{ + #if(!Timer_CSTick_UsingFixedFunction) + /* Interrupt State Backup for Critical Region*/ + uint8 Timer_CSTick_interruptState; + #endif /* Interrupt state back up for Fixed Function only */ + + #if (Timer_CSTick_UsingFixedFunction) + /* Clear all bits but the enable bit (if it's already set) for Timer operation */ + Timer_CSTick_CONTROL &= Timer_CSTick_CTRL_ENABLE; + + /* Clear the mode bits for continuous run mode */ + #if (CY_PSOC5A) + Timer_CSTick_CONTROL2 &= ((uint8)(~Timer_CSTick_CTRL_MODE_MASK)); + #endif /* Clear bits in CONTROL2 only in PSOC5A */ + + #if (CY_PSOC3 || CY_PSOC5LP) + Timer_CSTick_CONTROL3 &= ((uint8)(~Timer_CSTick_CTRL_MODE_MASK)); + #endif /* CONTROL3 register exists only in PSoC3 OR PSoC5LP */ + + /* Check if One Shot mode is enabled i.e. RunMode !=0*/ + #if (Timer_CSTick_RunModeUsed != 0x0u) + /* Set 3rd bit of Control register to enable one shot mode */ + Timer_CSTick_CONTROL |= 0x04u; + #endif /* One Shot enabled only when RunModeUsed is not Continuous*/ + + #if (Timer_CSTick_RunModeUsed == 2) + #if (CY_PSOC5A) + /* Set last 2 bits of control2 register if one shot(halt on + interrupt) is enabled*/ + Timer_CSTick_CONTROL2 |= 0x03u; + #endif /* Set One-Shot Halt on Interrupt bit in CONTROL2 for PSoC5A */ + + #if (CY_PSOC3 || CY_PSOC5LP) + /* Set last 2 bits of control3 register if one shot(halt on + interrupt) is enabled*/ + Timer_CSTick_CONTROL3 |= 0x03u; + #endif /* Set One-Shot Halt on Interrupt bit in CONTROL3 for PSoC3 or PSoC5LP */ + + #endif /* Remove section if One Shot Halt on Interrupt is not enabled */ + + #if (Timer_CSTick_UsingHWEnable != 0) + #if (CY_PSOC5A) + /* Set the default Run Mode of the Timer to Continuous */ + Timer_CSTick_CONTROL2 |= Timer_CSTick_CTRL_MODE_PULSEWIDTH; + #endif /* Set Continuous Run Mode in CONTROL2 for PSoC5A */ + + #if (CY_PSOC3 || CY_PSOC5LP) + /* Clear and Set ROD and COD bits of CFG2 register */ + Timer_CSTick_CONTROL3 &= ((uint8)(~Timer_CSTick_CTRL_RCOD_MASK)); + Timer_CSTick_CONTROL3 |= Timer_CSTick_CTRL_RCOD; + + /* Clear and Enable the HW enable bit in CFG2 register */ + Timer_CSTick_CONTROL3 &= ((uint8)(~Timer_CSTick_CTRL_ENBL_MASK)); + Timer_CSTick_CONTROL3 |= Timer_CSTick_CTRL_ENBL; + + /* Set the default Run Mode of the Timer to Continuous */ + Timer_CSTick_CONTROL3 |= Timer_CSTick_CTRL_MODE_CONTINUOUS; + #endif /* Set Continuous Run Mode in CONTROL3 for PSoC3ES3 or PSoC5A */ + + #endif /* Configure Run Mode with hardware enable */ + + /* Clear and Set SYNCTC and SYNCCMP bits of RT1 register */ + Timer_CSTick_RT1 &= ((uint8)(~Timer_CSTick_RT1_MASK)); + Timer_CSTick_RT1 |= Timer_CSTick_SYNC; + + /*Enable DSI Sync all all inputs of the Timer*/ + Timer_CSTick_RT1 &= ((uint8)(~Timer_CSTick_SYNCDSI_MASK)); + Timer_CSTick_RT1 |= Timer_CSTick_SYNCDSI_EN; + + /* Set the IRQ to use the status register interrupts */ + Timer_CSTick_CONTROL2 |= Timer_CSTick_CTRL2_IRQ_SEL; + #endif /* Configuring registers of fixed function implementation */ + + /* Set Initial values from Configuration */ + Timer_CSTick_WritePeriod(Timer_CSTick_INIT_PERIOD); + Timer_CSTick_WriteCounter(Timer_CSTick_INIT_PERIOD); + + #if (Timer_CSTick_UsingHWCaptureCounter)/* Capture counter is enabled */ + Timer_CSTick_CAPTURE_COUNT_CTRL |= Timer_CSTick_CNTR_ENABLE; + Timer_CSTick_SetCaptureCount(Timer_CSTick_INIT_CAPTURE_COUNT); + #endif /* Configure capture counter value */ + + #if (!Timer_CSTick_UsingFixedFunction) + #if (Timer_CSTick_SoftwareCaptureMode) + Timer_CSTick_SetCaptureMode(Timer_CSTick_INIT_CAPTURE_MODE); + #endif /* Set Capture Mode for UDB implementation if capture mode is software controlled */ + + #if (Timer_CSTick_SoftwareTriggerMode) + #if (!Timer_CSTick_UDB_CONTROL_REG_REMOVED) + if (0u == (Timer_CSTick_CONTROL & Timer_CSTick__B_TIMER__TM_SOFTWARE)) + { + Timer_CSTick_SetTriggerMode(Timer_CSTick_INIT_TRIGGER_MODE); + } + #endif /* (!Timer_CSTick_UDB_CONTROL_REG_REMOVED) */ + #endif /* Set trigger mode for UDB Implementation if trigger mode is software controlled */ + + /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/ + /* Enter Critical Region*/ + Timer_CSTick_interruptState = CyEnterCriticalSection(); + + /* Use the interrupt output of the status register for IRQ output */ + Timer_CSTick_STATUS_AUX_CTRL |= Timer_CSTick_STATUS_ACTL_INT_EN_MASK; + + /* Exit Critical Region*/ + CyExitCriticalSection(Timer_CSTick_interruptState); + + #if (Timer_CSTick_EnableTriggerMode) + Timer_CSTick_EnableTrigger(); + #endif /* Set Trigger enable bit for UDB implementation in the control register*/ + + + #if (Timer_CSTick_InterruptOnCaptureCount && !Timer_CSTick_UDB_CONTROL_REG_REMOVED) + Timer_CSTick_SetInterruptCount(Timer_CSTick_INIT_INT_CAPTURE_COUNT); + #endif /* Set interrupt count in UDB implementation if interrupt count feature is checked.*/ + + Timer_CSTick_ClearFIFO(); + #endif /* Configure additional features of UDB implementation */ + + Timer_CSTick_SetInterruptMode(Timer_CSTick_INIT_INTERRUPT_MODE); +} + + +/******************************************************************************* +* Function Name: Timer_CSTick_Enable +******************************************************************************** +* +* Summary: +* Enable the Timer +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Timer_CSTick_Enable(void) +{ + /* Globally Enable the Fixed Function Block chosen */ + #if (Timer_CSTick_UsingFixedFunction) + Timer_CSTick_GLOBAL_ENABLE |= Timer_CSTick_BLOCK_EN_MASK; + Timer_CSTick_GLOBAL_STBY_ENABLE |= Timer_CSTick_BLOCK_STBY_EN_MASK; + #endif /* Set Enable bit for enabling Fixed function timer*/ + + /* Remove assignment if control register is removed */ + #if (!Timer_CSTick_UDB_CONTROL_REG_REMOVED || Timer_CSTick_UsingFixedFunction) + Timer_CSTick_CONTROL |= Timer_CSTick_CTRL_ENABLE; + #endif /* Remove assignment if control register is removed */ +} + + +/******************************************************************************* +* Function Name: Timer_CSTick_Start +******************************************************************************** +* +* Summary: +* The start function initializes the timer with the default values, the +* enables the timerto begin counting. It does not enable interrupts, +* the EnableInt command should be called if interrupt generation is required. +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Timer_CSTick_initVar: Is modified when this function is called for the +* first time. Is used to ensure that initialization happens only once. +* +*******************************************************************************/ +void Timer_CSTick_Start(void) +{ + if(Timer_CSTick_initVar == 0u) + { + Timer_CSTick_Init(); + + Timer_CSTick_initVar = 1u; /* Clear this bit for Initialization */ + } + + /* Enable the Timer */ + Timer_CSTick_Enable(); +} + + +/******************************************************************************* +* Function Name: Timer_CSTick_Stop +******************************************************************************** +* +* Summary: +* The stop function halts the timer, but does not change any modes or disable +* interrupts. +* +* Parameters: +* void +* +* Return: +* void +* +* Side Effects: If the Enable mode is set to Hardware only then this function +* has no effect on the operation of the timer. +* +*******************************************************************************/ +void Timer_CSTick_Stop(void) +{ + /* Disable Timer */ + #if(!Timer_CSTick_UDB_CONTROL_REG_REMOVED || Timer_CSTick_UsingFixedFunction) + Timer_CSTick_CONTROL &= ((uint8)(~Timer_CSTick_CTRL_ENABLE)); + #endif /* Remove assignment if control register is removed */ + + /* Globally disable the Fixed Function Block chosen */ + #if (Timer_CSTick_UsingFixedFunction) + Timer_CSTick_GLOBAL_ENABLE &= ((uint8)(~Timer_CSTick_BLOCK_EN_MASK)); + Timer_CSTick_GLOBAL_STBY_ENABLE &= ((uint8)(~Timer_CSTick_BLOCK_STBY_EN_MASK)); + #endif /* Disable global enable for the Timer Fixed function block to stop the Timer*/ +} + + +/******************************************************************************* +* Function Name: Timer_CSTick_SetInterruptMode +******************************************************************************** +* +* Summary: +* This function selects which of the interrupt inputs may cause an interrupt. +* The twosources are caputure and terminal. One, both or neither may +* be selected. +* +* Parameters: +* interruptMode: This parameter is used to enable interrups on either/or +* terminal count or capture. +* +* Return: +* void +* +*******************************************************************************/ +void Timer_CSTick_SetInterruptMode(uint8 interruptMode) +{ + Timer_CSTick_STATUS_MASK = interruptMode; +} + + +/******************************************************************************* +* Function Name: Timer_CSTick_SoftwareCapture +******************************************************************************** +* +* Summary: +* This function forces a capture independent of the capture signal. +* +* Parameters: +* void +* +* Return: +* void +* +* Side Effects: +* An existing hardware capture could be overwritten. +* +*******************************************************************************/ +void Timer_CSTick_SoftwareCapture(void) +{ + /* Generate a software capture by reading the counter register */ + #if(Timer_CSTick_UsingFixedFunction) + (void)CY_GET_REG16(Timer_CSTick_COUNTER_LSB_PTR); + #else + (void)CY_GET_REG8(Timer_CSTick_COUNTER_LSB_PTR_8BIT); + #endif/* (Timer_CSTick_UsingFixedFunction) */ + /* Capture Data is now in the FIFO */ +} + + +/******************************************************************************* +* Function Name: Timer_CSTick_ReadStatusRegister +******************************************************************************** +* +* Summary: +* Reads the status register and returns it's state. This function should use +* defined types for the bit-field information as the bits in this register may +* be permuteable. +* +* Parameters: +* void +* +* Return: +* The contents of the status register +* +* Side Effects: +* Status register bits may be clear on read. +* +*******************************************************************************/ +uint8 Timer_CSTick_ReadStatusRegister(void) +{ + return (Timer_CSTick_STATUS); +} + + +#if (!Timer_CSTick_UDB_CONTROL_REG_REMOVED) /* Remove API if control register is unused */ + + +/******************************************************************************* +* Function Name: Timer_CSTick_ReadControlRegister +******************************************************************************** +* +* Summary: +* Reads the control register and returns it's value. +* +* Parameters: +* void +* +* Return: +* The contents of the control register +* +*******************************************************************************/ +uint8 Timer_CSTick_ReadControlRegister(void) +{ + #if (!Timer_CSTick_UDB_CONTROL_REG_REMOVED) + return ((uint8)Timer_CSTick_CONTROL); + #else + return (0); + #endif /* (!Timer_CSTick_UDB_CONTROL_REG_REMOVED) */ +} + + +/******************************************************************************* +* Function Name: Timer_CSTick_WriteControlRegister +******************************************************************************** +* +* Summary: +* Sets the bit-field of the control register. +* +* Parameters: +* control: The contents of the control register +* +* Return: +* +*******************************************************************************/ +void Timer_CSTick_WriteControlRegister(uint8 control) +{ + #if (!Timer_CSTick_UDB_CONTROL_REG_REMOVED) + Timer_CSTick_CONTROL = control; + #else + control = 0u; + #endif /* (!Timer_CSTick_UDB_CONTROL_REG_REMOVED) */ +} + +#endif /* Remove API if control register is unused */ + + +/******************************************************************************* +* Function Name: Timer_CSTick_ReadPeriod +******************************************************************************** +* +* Summary: +* This function returns the current value of the Period. +* +* Parameters: +* void +* +* Return: +* The present value of the counter. +* +*******************************************************************************/ +uint16 Timer_CSTick_ReadPeriod(void) +{ + #if(Timer_CSTick_UsingFixedFunction) + return ((uint16)CY_GET_REG16(Timer_CSTick_PERIOD_LSB_PTR)); + #else + return (CY_GET_REG16(Timer_CSTick_PERIOD_LSB_PTR)); + #endif /* (Timer_CSTick_UsingFixedFunction) */ +} + + +/******************************************************************************* +* Function Name: Timer_CSTick_WritePeriod +******************************************************************************** +* +* Summary: +* This function is used to change the period of the counter. The new period +* will be loaded the next time terminal count is detected. +* +* Parameters: +* period: This value may be between 1 and (2^Resolution)-1. A value of 0 will +* result in the counter remaining at zero. +* +* Return: +* void +* +*******************************************************************************/ +void Timer_CSTick_WritePeriod(uint16 period) +{ + #if(Timer_CSTick_UsingFixedFunction) + uint16 period_temp = (uint16)period; + CY_SET_REG16(Timer_CSTick_PERIOD_LSB_PTR, period_temp); + #else + CY_SET_REG16(Timer_CSTick_PERIOD_LSB_PTR, period); + #endif /*Write Period value with appropriate resolution suffix depending on UDB or fixed function implementation */ +} + + +/******************************************************************************* +* Function Name: Timer_CSTick_ReadCapture +******************************************************************************** +* +* Summary: +* This function returns the last value captured. +* +* Parameters: +* void +* +* Return: +* Present Capture value. +* +*******************************************************************************/ +uint16 Timer_CSTick_ReadCapture(void) +{ + #if(Timer_CSTick_UsingFixedFunction) + return ((uint16)CY_GET_REG16(Timer_CSTick_CAPTURE_LSB_PTR)); + #else + return (CY_GET_REG16(Timer_CSTick_CAPTURE_LSB_PTR)); + #endif /* (Timer_CSTick_UsingFixedFunction) */ +} + + +/******************************************************************************* +* Function Name: Timer_CSTick_WriteCounter +******************************************************************************** +* +* Summary: +* This funtion is used to set the counter to a specific value +* +* Parameters: +* counter: New counter value. +* +* Return: +* void +* +*******************************************************************************/ +void Timer_CSTick_WriteCounter(uint16 counter) +{ + #if(Timer_CSTick_UsingFixedFunction) + /* This functionality is removed until a FixedFunction HW update to + * allow this register to be written + */ + CY_SET_REG16(Timer_CSTick_COUNTER_LSB_PTR, (uint16)counter); + + #else + CY_SET_REG16(Timer_CSTick_COUNTER_LSB_PTR, counter); + #endif /* Set Write Counter only for the UDB implementation (Write Counter not available in fixed function Timer */ +} + + +/******************************************************************************* +* Function Name: Timer_CSTick_ReadCounter +******************************************************************************** +* +* Summary: +* This function returns the current counter value. +* +* Parameters: +* void +* +* Return: +* Present compare value. +* +*******************************************************************************/ +uint16 Timer_CSTick_ReadCounter(void) +{ + /* Force capture by reading Accumulator */ + /* Must first do a software capture to be able to read the counter */ + /* It is up to the user code to make sure there isn't already captured data in the FIFO */ + #if(Timer_CSTick_UsingFixedFunction) + (void)CY_GET_REG16(Timer_CSTick_COUNTER_LSB_PTR); + #else + (void)CY_GET_REG8(Timer_CSTick_COUNTER_LSB_PTR_8BIT); + #endif/* (Timer_CSTick_UsingFixedFunction) */ + + /* Read the data from the FIFO (or capture register for Fixed Function)*/ + #if(Timer_CSTick_UsingFixedFunction) + return ((uint16)CY_GET_REG16(Timer_CSTick_CAPTURE_LSB_PTR)); + #else + return (CY_GET_REG16(Timer_CSTick_CAPTURE_LSB_PTR)); + #endif /* (Timer_CSTick_UsingFixedFunction) */ +} + + +#if(!Timer_CSTick_UsingFixedFunction) /* UDB Specific Functions */ + + +/******************************************************************************* + * The functions below this point are only available using the UDB + * implementation. If a feature is selected, then the API is enabled. + ******************************************************************************/ + + +#if (Timer_CSTick_SoftwareCaptureMode) + + +/******************************************************************************* +* Function Name: Timer_CSTick_SetCaptureMode +******************************************************************************** +* +* Summary: +* This function sets the capture mode to either rising or falling edge. +* +* Parameters: +* captureMode: This parameter sets the capture mode of the UDB capture feature +* The parameter values are defined using the +* #define Timer_CSTick__B_TIMER__CM_NONE 0 +#define Timer_CSTick__B_TIMER__CM_RISINGEDGE 1 +#define Timer_CSTick__B_TIMER__CM_FALLINGEDGE 2 +#define Timer_CSTick__B_TIMER__CM_EITHEREDGE 3 +#define Timer_CSTick__B_TIMER__CM_SOFTWARE 4 + identifiers +* The following are the possible values of the parameter +* Timer_CSTick__B_TIMER__CM_NONE - Set Capture mode to None +* Timer_CSTick__B_TIMER__CM_RISINGEDGE - Rising edge of Capture input +* Timer_CSTick__B_TIMER__CM_FALLINGEDGE - Falling edge of Capture input +* Timer_CSTick__B_TIMER__CM_EITHEREDGE - Either edge of Capture input +* +* Return: +* void +* +*******************************************************************************/ +void Timer_CSTick_SetCaptureMode(uint8 captureMode) +{ + /* This must only set to two bits of the control register associated */ + captureMode = ((uint8)((uint8)captureMode << Timer_CSTick_CTRL_CAP_MODE_SHIFT)); + captureMode &= (Timer_CSTick_CTRL_CAP_MODE_MASK); + + #if (!Timer_CSTick_UDB_CONTROL_REG_REMOVED) + /* Clear the Current Setting */ + Timer_CSTick_CONTROL &= ((uint8)(~Timer_CSTick_CTRL_CAP_MODE_MASK)); + + /* Write The New Setting */ + Timer_CSTick_CONTROL |= captureMode; + #endif /* (!Timer_CSTick_UDB_CONTROL_REG_REMOVED) */ +} +#endif /* Remove API if Capture Mode is not Software Controlled */ + + +#if (Timer_CSTick_SoftwareTriggerMode) + + +/******************************************************************************* +* Function Name: Timer_CSTick_SetTriggerMode +******************************************************************************** +* +* Summary: +* This function sets the trigger input mode +* +* Parameters: +* triggerMode: Pass one of the pre-defined Trigger Modes (except Software) + #define Timer_CSTick__B_TIMER__TM_NONE 0x00u + #define Timer_CSTick__B_TIMER__TM_RISINGEDGE 0x04u + #define Timer_CSTick__B_TIMER__TM_FALLINGEDGE 0x08u + #define Timer_CSTick__B_TIMER__TM_EITHEREDGE 0x0Cu + #define Timer_CSTick__B_TIMER__TM_SOFTWARE 0x10u +* +* Return: +* void +* +*******************************************************************************/ +void Timer_CSTick_SetTriggerMode(uint8 triggerMode) +{ + /* This must only set to two bits of the control register associated */ + triggerMode &= Timer_CSTick_CTRL_TRIG_MODE_MASK; + + #if (!Timer_CSTick_UDB_CONTROL_REG_REMOVED) /* Remove assignment if control register is removed */ + + /* Clear the Current Setting */ + Timer_CSTick_CONTROL &= ((uint8)(~Timer_CSTick_CTRL_TRIG_MODE_MASK)); + + /* Write The New Setting */ + Timer_CSTick_CONTROL |= (triggerMode | Timer_CSTick__B_TIMER__TM_SOFTWARE); + #endif /* Remove code section if control register is not used */ +} +#endif /* Remove API if Trigger Mode is not Software Controlled */ + +#if (Timer_CSTick_EnableTriggerMode) + + +/******************************************************************************* +* Function Name: Timer_CSTick_EnableTrigger +******************************************************************************** +* +* Summary: +* Sets the control bit enabling Hardware Trigger mode +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Timer_CSTick_EnableTrigger(void) +{ + #if (!Timer_CSTick_UDB_CONTROL_REG_REMOVED) /* Remove assignment if control register is removed */ + Timer_CSTick_CONTROL |= Timer_CSTick_CTRL_TRIG_EN; + #endif /* Remove code section if control register is not used */ +} + + +/******************************************************************************* +* Function Name: Timer_CSTick_DisableTrigger +******************************************************************************** +* +* Summary: +* Clears the control bit enabling Hardware Trigger mode +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Timer_CSTick_DisableTrigger(void) +{ + #if (!Timer_CSTick_UDB_CONTROL_REG_REMOVED ) /* Remove assignment if control register is removed */ + Timer_CSTick_CONTROL &= ((uint8)(~Timer_CSTick_CTRL_TRIG_EN)); + #endif /* Remove code section if control register is not used */ +} +#endif /* Remove API is Trigger Mode is set to None */ + +#if(Timer_CSTick_InterruptOnCaptureCount) + + +/******************************************************************************* +* Function Name: Timer_CSTick_SetInterruptCount +******************************************************************************** +* +* Summary: +* This function sets the capture count before an interrupt is triggered. +* +* Parameters: +* interruptCount: A value between 0 and 3 is valid. If the value is 0, then +* an interrupt will occur each time a capture occurs. +* A value of 1 to 3 will cause the interrupt +* to delay by the same number of captures. +* +* Return: +* void +* +*******************************************************************************/ +void Timer_CSTick_SetInterruptCount(uint8 interruptCount) +{ + /* This must only set to two bits of the control register associated */ + interruptCount &= Timer_CSTick_CTRL_INTCNT_MASK; + + #if (!Timer_CSTick_UDB_CONTROL_REG_REMOVED) + /* Clear the Current Setting */ + Timer_CSTick_CONTROL &= ((uint8)(~Timer_CSTick_CTRL_INTCNT_MASK)); + /* Write The New Setting */ + Timer_CSTick_CONTROL |= interruptCount; + #endif /* (!Timer_CSTick_UDB_CONTROL_REG_REMOVED) */ +} +#endif /* Timer_CSTick_InterruptOnCaptureCount */ + + +#if (Timer_CSTick_UsingHWCaptureCounter) + + +/******************************************************************************* +* Function Name: Timer_CSTick_SetCaptureCount +******************************************************************************** +* +* Summary: +* This function sets the capture count +* +* Parameters: +* captureCount: A value between 2 and 127 inclusive is valid. A value of 1 +* to 127 will cause the interrupt to delay by the same number of +* captures. +* +* Return: +* void +* +*******************************************************************************/ +void Timer_CSTick_SetCaptureCount(uint8 captureCount) +{ + Timer_CSTick_CAP_COUNT = captureCount; +} + + +/******************************************************************************* +* Function Name: Timer_CSTick_ReadCaptureCount +******************************************************************************** +* +* Summary: +* This function reads the capture count setting +* +* Parameters: +* void +* +* Return: +* Returns the Capture Count Setting +* +*******************************************************************************/ +uint8 Timer_CSTick_ReadCaptureCount(void) +{ + return ((uint8)Timer_CSTick_CAP_COUNT); +} +#endif /* Timer_CSTick_UsingHWCaptureCounter */ + + +/******************************************************************************* +* Function Name: Timer_CSTick_ClearFIFO +******************************************************************************** +* +* Summary: +* This function clears all capture data from the capture FIFO +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Timer_CSTick_ClearFIFO(void) +{ + while(0u != (Timer_CSTick_ReadStatusRegister() & Timer_CSTick_STATUS_FIFONEMP)) + { + (void)Timer_CSTick_ReadCapture(); + } +} + +#endif /* UDB Specific Functions */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Timer_CSTick.h b/source/hic_hal/cypress/psoc5lp/PSoC5/Timer_CSTick.h new file mode 100644 index 0000000000..7ec15d1184 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Timer_CSTick.h @@ -0,0 +1,441 @@ +/******************************************************************************* +* File Name: Timer_CSTick.h +* Version 2.80 +* +* Description: +* Contains the function prototypes and constants available to the timer +* user module. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_TIMER_Timer_CSTick_H) +#define CY_TIMER_Timer_CSTick_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */ + +extern uint8 Timer_CSTick_initVar; + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component Timer_v2_80 requires cy_boot v3.0 or later +#endif /* (CY_ PSOC5LP) */ + + +/************************************** +* Parameter Defaults +**************************************/ + +#define Timer_CSTick_Resolution 16u +#define Timer_CSTick_UsingFixedFunction 1u +#define Timer_CSTick_UsingHWCaptureCounter 0u +#define Timer_CSTick_SoftwareCaptureMode 0u +#define Timer_CSTick_SoftwareTriggerMode 0u +#define Timer_CSTick_UsingHWEnable 0u +#define Timer_CSTick_EnableTriggerMode 0u +#define Timer_CSTick_InterruptOnCaptureCount 0u +#define Timer_CSTick_RunModeUsed 0u +#define Timer_CSTick_ControlRegRemoved 0u + +#if defined(Timer_CSTick_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG) + #define Timer_CSTick_UDB_CONTROL_REG_REMOVED (0u) +#elif (Timer_CSTick_UsingFixedFunction) + #define Timer_CSTick_UDB_CONTROL_REG_REMOVED (0u) +#else + #define Timer_CSTick_UDB_CONTROL_REG_REMOVED (1u) +#endif /* End Timer_CSTick_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG */ + + +/*************************************** +* Type defines +***************************************/ + + +/************************************************************************** + * Sleep Wakeup Backup structure for Timer Component + *************************************************************************/ +typedef struct +{ + uint8 TimerEnableState; + #if(!Timer_CSTick_UsingFixedFunction) + + uint16 TimerUdb; + uint8 InterruptMaskValue; + #if (Timer_CSTick_UsingHWCaptureCounter) + uint8 TimerCaptureCounter; + #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */ + + #if (!Timer_CSTick_UDB_CONTROL_REG_REMOVED) + uint8 TimerControlRegister; + #endif /* variable declaration for backing up enable state of the Timer */ + #endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */ + +}Timer_CSTick_backupStruct; + + +/*************************************** +* Function Prototypes +***************************************/ + +void Timer_CSTick_Start(void) ; +void Timer_CSTick_Stop(void) ; + +void Timer_CSTick_SetInterruptMode(uint8 interruptMode) ; +uint8 Timer_CSTick_ReadStatusRegister(void) ; +/* Deprecated function. Do not use this in future. Retained for backward compatibility */ +#define Timer_CSTick_GetInterruptSource() Timer_CSTick_ReadStatusRegister() + +#if(!Timer_CSTick_UDB_CONTROL_REG_REMOVED) + uint8 Timer_CSTick_ReadControlRegister(void) ; + void Timer_CSTick_WriteControlRegister(uint8 control) ; +#endif /* (!Timer_CSTick_UDB_CONTROL_REG_REMOVED) */ + +uint16 Timer_CSTick_ReadPeriod(void) ; +void Timer_CSTick_WritePeriod(uint16 period) ; +uint16 Timer_CSTick_ReadCounter(void) ; +void Timer_CSTick_WriteCounter(uint16 counter) ; +uint16 Timer_CSTick_ReadCapture(void) ; +void Timer_CSTick_SoftwareCapture(void) ; + +#if(!Timer_CSTick_UsingFixedFunction) /* UDB Prototypes */ + #if (Timer_CSTick_SoftwareCaptureMode) + void Timer_CSTick_SetCaptureMode(uint8 captureMode) ; + #endif /* (!Timer_CSTick_UsingFixedFunction) */ + + #if (Timer_CSTick_SoftwareTriggerMode) + void Timer_CSTick_SetTriggerMode(uint8 triggerMode) ; + #endif /* (Timer_CSTick_SoftwareTriggerMode) */ + + #if (Timer_CSTick_EnableTriggerMode) + void Timer_CSTick_EnableTrigger(void) ; + void Timer_CSTick_DisableTrigger(void) ; + #endif /* (Timer_CSTick_EnableTriggerMode) */ + + + #if(Timer_CSTick_InterruptOnCaptureCount) + void Timer_CSTick_SetInterruptCount(uint8 interruptCount) ; + #endif /* (Timer_CSTick_InterruptOnCaptureCount) */ + + #if (Timer_CSTick_UsingHWCaptureCounter) + void Timer_CSTick_SetCaptureCount(uint8 captureCount) ; + uint8 Timer_CSTick_ReadCaptureCount(void) ; + #endif /* (Timer_CSTick_UsingHWCaptureCounter) */ + + void Timer_CSTick_ClearFIFO(void) ; +#endif /* UDB Prototypes */ + +/* Sleep Retention APIs */ +void Timer_CSTick_Init(void) ; +void Timer_CSTick_Enable(void) ; +void Timer_CSTick_SaveConfig(void) ; +void Timer_CSTick_RestoreConfig(void) ; +void Timer_CSTick_Sleep(void) ; +void Timer_CSTick_Wakeup(void) ; + + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +/* Enumerated Type B_Timer__CaptureModes, Used in Capture Mode */ +#define Timer_CSTick__B_TIMER__CM_NONE 0 +#define Timer_CSTick__B_TIMER__CM_RISINGEDGE 1 +#define Timer_CSTick__B_TIMER__CM_FALLINGEDGE 2 +#define Timer_CSTick__B_TIMER__CM_EITHEREDGE 3 +#define Timer_CSTick__B_TIMER__CM_SOFTWARE 4 + + + +/* Enumerated Type B_Timer__TriggerModes, Used in Trigger Mode */ +#define Timer_CSTick__B_TIMER__TM_NONE 0x00u +#define Timer_CSTick__B_TIMER__TM_RISINGEDGE 0x04u +#define Timer_CSTick__B_TIMER__TM_FALLINGEDGE 0x08u +#define Timer_CSTick__B_TIMER__TM_EITHEREDGE 0x0Cu +#define Timer_CSTick__B_TIMER__TM_SOFTWARE 0x10u + + +/*************************************** +* Initialial Parameter Constants +***************************************/ + +#define Timer_CSTick_INIT_PERIOD 65535u +#define Timer_CSTick_INIT_CAPTURE_MODE ((uint8)((uint8)0u << Timer_CSTick_CTRL_CAP_MODE_SHIFT)) +#define Timer_CSTick_INIT_TRIGGER_MODE ((uint8)((uint8)0u << Timer_CSTick_CTRL_TRIG_MODE_SHIFT)) +#if (Timer_CSTick_UsingFixedFunction) + #define Timer_CSTick_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Timer_CSTick_STATUS_TC_INT_MASK_SHIFT)) | \ + ((uint8)((uint8)0 << Timer_CSTick_STATUS_CAPTURE_INT_MASK_SHIFT))) +#else + #define Timer_CSTick_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Timer_CSTick_STATUS_TC_INT_MASK_SHIFT)) | \ + ((uint8)((uint8)0 << Timer_CSTick_STATUS_CAPTURE_INT_MASK_SHIFT)) | \ + ((uint8)((uint8)0 << Timer_CSTick_STATUS_FIFOFULL_INT_MASK_SHIFT))) +#endif /* (Timer_CSTick_UsingFixedFunction) */ +#define Timer_CSTick_INIT_CAPTURE_COUNT (2u) +#define Timer_CSTick_INIT_INT_CAPTURE_COUNT ((uint8)((uint8)(1u - 1u) << Timer_CSTick_CTRL_INTCNT_SHIFT)) + + +/*************************************** +* Registers +***************************************/ + +#if (Timer_CSTick_UsingFixedFunction) /* Implementation Specific Registers and Register Constants */ + + + /*************************************** + * Fixed Function Registers + ***************************************/ + + #define Timer_CSTick_STATUS (*(reg8 *) Timer_CSTick_TimerHW__SR0 ) + /* In Fixed Function Block Status and Mask are the same register */ + #define Timer_CSTick_STATUS_MASK (*(reg8 *) Timer_CSTick_TimerHW__SR0 ) + #define Timer_CSTick_CONTROL (*(reg8 *) Timer_CSTick_TimerHW__CFG0) + #define Timer_CSTick_CONTROL2 (*(reg8 *) Timer_CSTick_TimerHW__CFG1) + #define Timer_CSTick_CONTROL2_PTR ( (reg8 *) Timer_CSTick_TimerHW__CFG1) + #define Timer_CSTick_RT1 (*(reg8 *) Timer_CSTick_TimerHW__RT1) + #define Timer_CSTick_RT1_PTR ( (reg8 *) Timer_CSTick_TimerHW__RT1) + + #if (CY_PSOC3 || CY_PSOC5LP) + #define Timer_CSTick_CONTROL3 (*(reg8 *) Timer_CSTick_TimerHW__CFG2) + #define Timer_CSTick_CONTROL3_PTR ( (reg8 *) Timer_CSTick_TimerHW__CFG2) + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + #define Timer_CSTick_GLOBAL_ENABLE (*(reg8 *) Timer_CSTick_TimerHW__PM_ACT_CFG) + #define Timer_CSTick_GLOBAL_STBY_ENABLE (*(reg8 *) Timer_CSTick_TimerHW__PM_STBY_CFG) + + #define Timer_CSTick_CAPTURE_LSB (* (reg16 *) Timer_CSTick_TimerHW__CAP0 ) + #define Timer_CSTick_CAPTURE_LSB_PTR ((reg16 *) Timer_CSTick_TimerHW__CAP0 ) + #define Timer_CSTick_PERIOD_LSB (* (reg16 *) Timer_CSTick_TimerHW__PER0 ) + #define Timer_CSTick_PERIOD_LSB_PTR ((reg16 *) Timer_CSTick_TimerHW__PER0 ) + #define Timer_CSTick_COUNTER_LSB (* (reg16 *) Timer_CSTick_TimerHW__CNT_CMP0 ) + #define Timer_CSTick_COUNTER_LSB_PTR ((reg16 *) Timer_CSTick_TimerHW__CNT_CMP0 ) + + + /*************************************** + * Register Constants + ***************************************/ + + /* Fixed Function Block Chosen */ + #define Timer_CSTick_BLOCK_EN_MASK Timer_CSTick_TimerHW__PM_ACT_MSK + #define Timer_CSTick_BLOCK_STBY_EN_MASK Timer_CSTick_TimerHW__PM_STBY_MSK + + /* Control Register Bit Locations */ + /* Interrupt Count - Not valid for Fixed Function Block */ + #define Timer_CSTick_CTRL_INTCNT_SHIFT 0x00u + /* Trigger Polarity - Not valid for Fixed Function Block */ + #define Timer_CSTick_CTRL_TRIG_MODE_SHIFT 0x00u + /* Trigger Enable - Not valid for Fixed Function Block */ + #define Timer_CSTick_CTRL_TRIG_EN_SHIFT 0x00u + /* Capture Polarity - Not valid for Fixed Function Block */ + #define Timer_CSTick_CTRL_CAP_MODE_SHIFT 0x00u + /* Timer Enable - As defined in Register Map, part of TMRX_CFG0 register */ + #define Timer_CSTick_CTRL_ENABLE_SHIFT 0x00u + + /* Control Register Bit Masks */ + #define Timer_CSTick_CTRL_ENABLE ((uint8)((uint8)0x01u << Timer_CSTick_CTRL_ENABLE_SHIFT)) + + /* Control2 Register Bit Masks */ + /* As defined in Register Map, Part of the TMRX_CFG1 register */ + #define Timer_CSTick_CTRL2_IRQ_SEL_SHIFT 0x00u + #define Timer_CSTick_CTRL2_IRQ_SEL ((uint8)((uint8)0x01u << Timer_CSTick_CTRL2_IRQ_SEL_SHIFT)) + + #if (CY_PSOC5A) + /* Use CFG1 Mode bits to set run mode */ + /* As defined by Verilog Implementation */ + #define Timer_CSTick_CTRL_MODE_SHIFT 0x01u + #define Timer_CSTick_CTRL_MODE_MASK ((uint8)((uint8)0x07u << Timer_CSTick_CTRL_MODE_SHIFT)) + #endif /* (CY_PSOC5A) */ + #if (CY_PSOC3 || CY_PSOC5LP) + /* Control3 Register Bit Locations */ + #define Timer_CSTick_CTRL_RCOD_SHIFT 0x02u + #define Timer_CSTick_CTRL_ENBL_SHIFT 0x00u + #define Timer_CSTick_CTRL_MODE_SHIFT 0x00u + + /* Control3 Register Bit Masks */ + #define Timer_CSTick_CTRL_RCOD_MASK ((uint8)((uint8)0x03u << Timer_CSTick_CTRL_RCOD_SHIFT)) /* ROD and COD bit masks */ + #define Timer_CSTick_CTRL_ENBL_MASK ((uint8)((uint8)0x80u << Timer_CSTick_CTRL_ENBL_SHIFT)) /* HW_EN bit mask */ + #define Timer_CSTick_CTRL_MODE_MASK ((uint8)((uint8)0x03u << Timer_CSTick_CTRL_MODE_SHIFT)) /* Run mode bit mask */ + + #define Timer_CSTick_CTRL_RCOD ((uint8)((uint8)0x03u << Timer_CSTick_CTRL_RCOD_SHIFT)) + #define Timer_CSTick_CTRL_ENBL ((uint8)((uint8)0x80u << Timer_CSTick_CTRL_ENBL_SHIFT)) + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + /*RT1 Synch Constants: Applicable for PSoC3 and PSoC5LP */ + #define Timer_CSTick_RT1_SHIFT 0x04u + /* Sync TC and CMP bit masks */ + #define Timer_CSTick_RT1_MASK ((uint8)((uint8)0x03u << Timer_CSTick_RT1_SHIFT)) + #define Timer_CSTick_SYNC ((uint8)((uint8)0x03u << Timer_CSTick_RT1_SHIFT)) + #define Timer_CSTick_SYNCDSI_SHIFT 0x00u + /* Sync all DSI inputs with Mask */ + #define Timer_CSTick_SYNCDSI_MASK ((uint8)((uint8)0x0Fu << Timer_CSTick_SYNCDSI_SHIFT)) + /* Sync all DSI inputs */ + #define Timer_CSTick_SYNCDSI_EN ((uint8)((uint8)0x0Fu << Timer_CSTick_SYNCDSI_SHIFT)) + + #define Timer_CSTick_CTRL_MODE_PULSEWIDTH ((uint8)((uint8)0x01u << Timer_CSTick_CTRL_MODE_SHIFT)) + #define Timer_CSTick_CTRL_MODE_PERIOD ((uint8)((uint8)0x02u << Timer_CSTick_CTRL_MODE_SHIFT)) + #define Timer_CSTick_CTRL_MODE_CONTINUOUS ((uint8)((uint8)0x00u << Timer_CSTick_CTRL_MODE_SHIFT)) + + /* Status Register Bit Locations */ + /* As defined in Register Map, part of TMRX_SR0 register */ + #define Timer_CSTick_STATUS_TC_SHIFT 0x07u + /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */ + #define Timer_CSTick_STATUS_CAPTURE_SHIFT 0x06u + /* As defined in Register Map, part of TMRX_SR0 register */ + #define Timer_CSTick_STATUS_TC_INT_MASK_SHIFT (Timer_CSTick_STATUS_TC_SHIFT - 0x04u) + /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */ + #define Timer_CSTick_STATUS_CAPTURE_INT_MASK_SHIFT (Timer_CSTick_STATUS_CAPTURE_SHIFT - 0x04u) + + /* Status Register Bit Masks */ + #define Timer_CSTick_STATUS_TC ((uint8)((uint8)0x01u << Timer_CSTick_STATUS_TC_SHIFT)) + #define Timer_CSTick_STATUS_CAPTURE ((uint8)((uint8)0x01u << Timer_CSTick_STATUS_CAPTURE_SHIFT)) + /* Interrupt Enable Bit-Mask for interrupt on TC */ + #define Timer_CSTick_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << Timer_CSTick_STATUS_TC_INT_MASK_SHIFT)) + /* Interrupt Enable Bit-Mask for interrupt on Capture */ + #define Timer_CSTick_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << Timer_CSTick_STATUS_CAPTURE_INT_MASK_SHIFT)) + +#else /* UDB Registers and Register Constants */ + + + /*************************************** + * UDB Registers + ***************************************/ + + #define Timer_CSTick_STATUS (* (reg8 *) Timer_CSTick_TimerUDB_rstSts_stsreg__STATUS_REG ) + #define Timer_CSTick_STATUS_MASK (* (reg8 *) Timer_CSTick_TimerUDB_rstSts_stsreg__MASK_REG) + #define Timer_CSTick_STATUS_AUX_CTRL (* (reg8 *) Timer_CSTick_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG) + #define Timer_CSTick_CONTROL (* (reg8 *) Timer_CSTick_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG ) + + #if(Timer_CSTick_Resolution <= 8u) /* 8-bit Timer */ + #define Timer_CSTick_CAPTURE_LSB (* (reg8 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_CSTick_CAPTURE_LSB_PTR ((reg8 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_CSTick_PERIOD_LSB (* (reg8 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_CSTick_PERIOD_LSB_PTR ((reg8 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_CSTick_COUNTER_LSB (* (reg8 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define Timer_CSTick_COUNTER_LSB_PTR ((reg8 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__A0_REG ) + #elif(Timer_CSTick_Resolution <= 16u) /* 8-bit Timer */ + #if(CY_PSOC3) /* 8-bit addres space */ + #define Timer_CSTick_CAPTURE_LSB (* (reg16 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_CSTick_CAPTURE_LSB_PTR ((reg16 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_CSTick_PERIOD_LSB (* (reg16 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_CSTick_PERIOD_LSB_PTR ((reg16 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_CSTick_COUNTER_LSB (* (reg16 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define Timer_CSTick_COUNTER_LSB_PTR ((reg16 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__A0_REG ) + #else /* 16-bit address space */ + #define Timer_CSTick_CAPTURE_LSB (* (reg16 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG ) + #define Timer_CSTick_CAPTURE_LSB_PTR ((reg16 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG ) + #define Timer_CSTick_PERIOD_LSB (* (reg16 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG ) + #define Timer_CSTick_PERIOD_LSB_PTR ((reg16 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG ) + #define Timer_CSTick_COUNTER_LSB (* (reg16 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG ) + #define Timer_CSTick_COUNTER_LSB_PTR ((reg16 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG ) + #endif /* CY_PSOC3 */ + #elif(Timer_CSTick_Resolution <= 24u)/* 24-bit Timer */ + #define Timer_CSTick_CAPTURE_LSB (* (reg32 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_CSTick_CAPTURE_LSB_PTR ((reg32 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_CSTick_PERIOD_LSB (* (reg32 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_CSTick_PERIOD_LSB_PTR ((reg32 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_CSTick_COUNTER_LSB (* (reg32 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define Timer_CSTick_COUNTER_LSB_PTR ((reg32 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__A0_REG ) + #else /* 32-bit Timer */ + #if(CY_PSOC3 || CY_PSOC5) /* 8-bit address space */ + #define Timer_CSTick_CAPTURE_LSB (* (reg32 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_CSTick_CAPTURE_LSB_PTR ((reg32 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_CSTick_PERIOD_LSB (* (reg32 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_CSTick_PERIOD_LSB_PTR ((reg32 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_CSTick_COUNTER_LSB (* (reg32 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define Timer_CSTick_COUNTER_LSB_PTR ((reg32 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__A0_REG ) + #else /* 32-bit address space */ + #define Timer_CSTick_CAPTURE_LSB (* (reg32 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG ) + #define Timer_CSTick_CAPTURE_LSB_PTR ((reg32 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG ) + #define Timer_CSTick_PERIOD_LSB (* (reg32 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG ) + #define Timer_CSTick_PERIOD_LSB_PTR ((reg32 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG ) + #define Timer_CSTick_COUNTER_LSB (* (reg32 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG ) + #define Timer_CSTick_COUNTER_LSB_PTR ((reg32 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG ) + #endif /* CY_PSOC3 || CY_PSOC5 */ + #endif + + #define Timer_CSTick_COUNTER_LSB_PTR_8BIT ((reg8 *) Timer_CSTick_TimerUDB_sT16_timerdp_u0__A0_REG ) + + #if (Timer_CSTick_UsingHWCaptureCounter) + #define Timer_CSTick_CAP_COUNT (*(reg8 *) Timer_CSTick_TimerUDB_sCapCount_counter__PERIOD_REG ) + #define Timer_CSTick_CAP_COUNT_PTR ( (reg8 *) Timer_CSTick_TimerUDB_sCapCount_counter__PERIOD_REG ) + #define Timer_CSTick_CAPTURE_COUNT_CTRL (*(reg8 *) Timer_CSTick_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG ) + #define Timer_CSTick_CAPTURE_COUNT_CTRL_PTR ( (reg8 *) Timer_CSTick_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG ) + #endif /* (Timer_CSTick_UsingHWCaptureCounter) */ + + + /*************************************** + * Register Constants + ***************************************/ + + /* Control Register Bit Locations */ + #define Timer_CSTick_CTRL_INTCNT_SHIFT 0x00u /* As defined by Verilog Implementation */ + #define Timer_CSTick_CTRL_TRIG_MODE_SHIFT 0x02u /* As defined by Verilog Implementation */ + #define Timer_CSTick_CTRL_TRIG_EN_SHIFT 0x04u /* As defined by Verilog Implementation */ + #define Timer_CSTick_CTRL_CAP_MODE_SHIFT 0x05u /* As defined by Verilog Implementation */ + #define Timer_CSTick_CTRL_ENABLE_SHIFT 0x07u /* As defined by Verilog Implementation */ + + /* Control Register Bit Masks */ + #define Timer_CSTick_CTRL_INTCNT_MASK ((uint8)((uint8)0x03u << Timer_CSTick_CTRL_INTCNT_SHIFT)) + #define Timer_CSTick_CTRL_TRIG_MODE_MASK ((uint8)((uint8)0x03u << Timer_CSTick_CTRL_TRIG_MODE_SHIFT)) + #define Timer_CSTick_CTRL_TRIG_EN ((uint8)((uint8)0x01u << Timer_CSTick_CTRL_TRIG_EN_SHIFT)) + #define Timer_CSTick_CTRL_CAP_MODE_MASK ((uint8)((uint8)0x03u << Timer_CSTick_CTRL_CAP_MODE_SHIFT)) + #define Timer_CSTick_CTRL_ENABLE ((uint8)((uint8)0x01u << Timer_CSTick_CTRL_ENABLE_SHIFT)) + + /* Bit Counter (7-bit) Control Register Bit Definitions */ + /* As defined by the Register map for the AUX Control Register */ + #define Timer_CSTick_CNTR_ENABLE 0x20u + + /* Status Register Bit Locations */ + #define Timer_CSTick_STATUS_TC_SHIFT 0x00u /* As defined by Verilog Implementation */ + #define Timer_CSTick_STATUS_CAPTURE_SHIFT 0x01u /* As defined by Verilog Implementation */ + #define Timer_CSTick_STATUS_TC_INT_MASK_SHIFT Timer_CSTick_STATUS_TC_SHIFT + #define Timer_CSTick_STATUS_CAPTURE_INT_MASK_SHIFT Timer_CSTick_STATUS_CAPTURE_SHIFT + #define Timer_CSTick_STATUS_FIFOFULL_SHIFT 0x02u /* As defined by Verilog Implementation */ + #define Timer_CSTick_STATUS_FIFONEMP_SHIFT 0x03u /* As defined by Verilog Implementation */ + #define Timer_CSTick_STATUS_FIFOFULL_INT_MASK_SHIFT Timer_CSTick_STATUS_FIFOFULL_SHIFT + + /* Status Register Bit Masks */ + /* Sticky TC Event Bit-Mask */ + #define Timer_CSTick_STATUS_TC ((uint8)((uint8)0x01u << Timer_CSTick_STATUS_TC_SHIFT)) + /* Sticky Capture Event Bit-Mask */ + #define Timer_CSTick_STATUS_CAPTURE ((uint8)((uint8)0x01u << Timer_CSTick_STATUS_CAPTURE_SHIFT)) + /* Interrupt Enable Bit-Mask */ + #define Timer_CSTick_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << Timer_CSTick_STATUS_TC_SHIFT)) + /* Interrupt Enable Bit-Mask */ + #define Timer_CSTick_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << Timer_CSTick_STATUS_CAPTURE_SHIFT)) + /* NOT-Sticky FIFO Full Bit-Mask */ + #define Timer_CSTick_STATUS_FIFOFULL ((uint8)((uint8)0x01u << Timer_CSTick_STATUS_FIFOFULL_SHIFT)) + /* NOT-Sticky FIFO Not Empty Bit-Mask */ + #define Timer_CSTick_STATUS_FIFONEMP ((uint8)((uint8)0x01u << Timer_CSTick_STATUS_FIFONEMP_SHIFT)) + /* Interrupt Enable Bit-Mask */ + #define Timer_CSTick_STATUS_FIFOFULL_INT_MASK ((uint8)((uint8)0x01u << Timer_CSTick_STATUS_FIFOFULL_SHIFT)) + + #define Timer_CSTick_STATUS_ACTL_INT_EN 0x10u /* As defined for the ACTL Register */ + + /* Datapath Auxillary Control Register definitions */ + #define Timer_CSTick_AUX_CTRL_FIFO0_CLR 0x01u /* As defined by Register map */ + #define Timer_CSTick_AUX_CTRL_FIFO1_CLR 0x02u /* As defined by Register map */ + #define Timer_CSTick_AUX_CTRL_FIFO0_LVL 0x04u /* As defined by Register map */ + #define Timer_CSTick_AUX_CTRL_FIFO1_LVL 0x08u /* As defined by Register map */ + #define Timer_CSTick_STATUS_ACTL_INT_EN_MASK 0x10u /* As defined for the ACTL Register */ + +#endif /* Implementation Specific Registers and Register Constants */ + +#endif /* CY_TIMER_Timer_CSTick_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/Timer_CSTick_PM.c b/source/hic_hal/cypress/psoc5lp/PSoC5/Timer_CSTick_PM.c new file mode 100644 index 0000000000..d1dd8a7fb4 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/Timer_CSTick_PM.c @@ -0,0 +1,169 @@ +/******************************************************************************* +* File Name: Timer_CSTick_PM.c +* Version 2.80 +* +* Description: +* This file provides the power management source code to API for the +* Timer. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "Timer_CSTick.h" + +static Timer_CSTick_backupStruct Timer_CSTick_backup; + + +/******************************************************************************* +* Function Name: Timer_CSTick_SaveConfig +******************************************************************************** +* +* Summary: +* Save the current user configuration +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Timer_CSTick_backup: Variables of this global structure are modified to +* store the values of non retention configuration registers when Sleep() API is +* called. +* +*******************************************************************************/ +void Timer_CSTick_SaveConfig(void) +{ + #if (!Timer_CSTick_UsingFixedFunction) + Timer_CSTick_backup.TimerUdb = Timer_CSTick_ReadCounter(); + Timer_CSTick_backup.InterruptMaskValue = Timer_CSTick_STATUS_MASK; + #if (Timer_CSTick_UsingHWCaptureCounter) + Timer_CSTick_backup.TimerCaptureCounter = Timer_CSTick_ReadCaptureCount(); + #endif /* Back Up capture counter register */ + + #if(!Timer_CSTick_UDB_CONTROL_REG_REMOVED) + Timer_CSTick_backup.TimerControlRegister = Timer_CSTick_ReadControlRegister(); + #endif /* Backup the enable state of the Timer component */ + #endif /* Backup non retention registers in UDB implementation. All fixed function registers are retention */ +} + + +/******************************************************************************* +* Function Name: Timer_CSTick_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the current user configuration. +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Timer_CSTick_backup: Variables of this global structure are used to +* restore the values of non retention registers on wakeup from sleep mode. +* +*******************************************************************************/ +void Timer_CSTick_RestoreConfig(void) +{ + #if (!Timer_CSTick_UsingFixedFunction) + + Timer_CSTick_WriteCounter(Timer_CSTick_backup.TimerUdb); + Timer_CSTick_STATUS_MASK =Timer_CSTick_backup.InterruptMaskValue; + #if (Timer_CSTick_UsingHWCaptureCounter) + Timer_CSTick_SetCaptureCount(Timer_CSTick_backup.TimerCaptureCounter); + #endif /* Restore Capture counter register*/ + + #if(!Timer_CSTick_UDB_CONTROL_REG_REMOVED) + Timer_CSTick_WriteControlRegister(Timer_CSTick_backup.TimerControlRegister); + #endif /* Restore the enable state of the Timer component */ + #endif /* Restore non retention registers in the UDB implementation only */ +} + + +/******************************************************************************* +* Function Name: Timer_CSTick_Sleep +******************************************************************************** +* +* Summary: +* Stop and Save the user configuration +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Timer_CSTick_backup.TimerEnableState: Is modified depending on the +* enable state of the block before entering sleep mode. +* +*******************************************************************************/ +void Timer_CSTick_Sleep(void) +{ + #if(!Timer_CSTick_UDB_CONTROL_REG_REMOVED) + /* Save Counter's enable state */ + if(Timer_CSTick_CTRL_ENABLE == (Timer_CSTick_CONTROL & Timer_CSTick_CTRL_ENABLE)) + { + /* Timer is enabled */ + Timer_CSTick_backup.TimerEnableState = 1u; + } + else + { + /* Timer is disabled */ + Timer_CSTick_backup.TimerEnableState = 0u; + } + #endif /* Back up enable state from the Timer control register */ + Timer_CSTick_Stop(); + Timer_CSTick_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: Timer_CSTick_Wakeup +******************************************************************************** +* +* Summary: +* Restores and enables the user configuration +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Timer_CSTick_backup.enableState: Is used to restore the enable state of +* block on wakeup from sleep mode. +* +*******************************************************************************/ +void Timer_CSTick_Wakeup(void) +{ + Timer_CSTick_RestoreConfig(); + #if(!Timer_CSTick_UDB_CONTROL_REG_REMOVED) + if(Timer_CSTick_backup.TimerEnableState == 1u) + { /* Enable Timer's operation */ + Timer_CSTick_Enable(); + } /* Do nothing if Timer was disabled before */ + #endif /* Remove this code section if Control register is removed */ +} + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/UART_Bridge.c b/source/hic_hal/cypress/psoc5lp/PSoC5/UART_Bridge.c new file mode 100644 index 0000000000..50c98cb926 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/UART_Bridge.c @@ -0,0 +1,1670 @@ +/******************************************************************************* +* File Name: UART_Bridge.c +* Version 2.50 +* +* Description: +* This file provides all API functionality of the UART component +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "UART_Bridge.h" +#if (UART_Bridge_INTERNAL_CLOCK_USED) + #include "UART_Bridge_IntClock.h" +#endif /* End UART_Bridge_INTERNAL_CLOCK_USED */ + + +/*************************************** +* Global data allocation +***************************************/ + +uint8 UART_Bridge_initVar = 0u; + +#if (UART_Bridge_TX_INTERRUPT_ENABLED && UART_Bridge_TX_ENABLED) + volatile uint8 UART_Bridge_txBuffer[UART_Bridge_TX_BUFFER_SIZE]; + volatile uint16 UART_Bridge_txBufferRead = 0u; + uint16 UART_Bridge_txBufferWrite = 0u; +#endif /* (UART_Bridge_TX_INTERRUPT_ENABLED && UART_Bridge_TX_ENABLED) */ + +#if (UART_Bridge_RX_INTERRUPT_ENABLED && (UART_Bridge_RX_ENABLED || UART_Bridge_HD_ENABLED)) + uint8 UART_Bridge_errorStatus = 0u; + volatile uint8 UART_Bridge_rxBuffer[UART_Bridge_RX_BUFFER_SIZE]; + volatile uint16 UART_Bridge_rxBufferRead = 0u; + volatile uint16 UART_Bridge_rxBufferWrite = 0u; + volatile uint8 UART_Bridge_rxBufferLoopDetect = 0u; + volatile uint8 UART_Bridge_rxBufferOverflow = 0u; + #if (UART_Bridge_RXHW_ADDRESS_ENABLED) + volatile uint8 UART_Bridge_rxAddressMode = UART_Bridge_RX_ADDRESS_MODE; + volatile uint8 UART_Bridge_rxAddressDetected = 0u; + #endif /* (UART_Bridge_RXHW_ADDRESS_ENABLED) */ +#endif /* (UART_Bridge_RX_INTERRUPT_ENABLED && (UART_Bridge_RX_ENABLED || UART_Bridge_HD_ENABLED)) */ + + +/******************************************************************************* +* Function Name: UART_Bridge_Start +******************************************************************************** +* +* Summary: +* This is the preferred method to begin component operation. +* UART_Bridge_Start() sets the initVar variable, calls the +* UART_Bridge_Init() function, and then calls the +* UART_Bridge_Enable() function. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* The UART_Bridge_intiVar variable is used to indicate initial +* configuration of this component. The variable is initialized to zero (0u) +* and set to one (1u) the first time UART_Bridge_Start() is called. This +* allows for component initialization without re-initialization in all +* subsequent calls to the UART_Bridge_Start() routine. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void UART_Bridge_Start(void) +{ + /* If not initialized then initialize all required hardware and software */ + if(UART_Bridge_initVar == 0u) + { + UART_Bridge_Init(); + UART_Bridge_initVar = 1u; + } + + UART_Bridge_Enable(); +} + + +/******************************************************************************* +* Function Name: UART_Bridge_Init +******************************************************************************** +* +* Summary: +* Initializes or restores the component according to the customizer Configure +* dialog settings. It is not necessary to call UART_Bridge_Init() because +* the UART_Bridge_Start() API calls this function and is the preferred +* method to begin component operation. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void UART_Bridge_Init(void) +{ + #if(UART_Bridge_RX_ENABLED || UART_Bridge_HD_ENABLED) + + #if (UART_Bridge_RX_INTERRUPT_ENABLED) + /* Set RX interrupt vector and priority */ + (void) CyIntSetVector(UART_Bridge_RX_VECT_NUM, &UART_Bridge_RXISR); + CyIntSetPriority(UART_Bridge_RX_VECT_NUM, UART_Bridge_RX_PRIOR_NUM); + UART_Bridge_errorStatus = 0u; + #endif /* (UART_Bridge_RX_INTERRUPT_ENABLED) */ + + #if (UART_Bridge_RXHW_ADDRESS_ENABLED) + UART_Bridge_SetRxAddressMode(UART_Bridge_RX_ADDRESS_MODE); + UART_Bridge_SetRxAddress1(UART_Bridge_RX_HW_ADDRESS1); + UART_Bridge_SetRxAddress2(UART_Bridge_RX_HW_ADDRESS2); + #endif /* End UART_Bridge_RXHW_ADDRESS_ENABLED */ + + /* Init Count7 period */ + UART_Bridge_RXBITCTR_PERIOD_REG = UART_Bridge_RXBITCTR_INIT; + /* Configure the Initial RX interrupt mask */ + UART_Bridge_RXSTATUS_MASK_REG = UART_Bridge_INIT_RX_INTERRUPTS_MASK; + #endif /* End UART_Bridge_RX_ENABLED || UART_Bridge_HD_ENABLED*/ + + #if(UART_Bridge_TX_ENABLED) + #if (UART_Bridge_TX_INTERRUPT_ENABLED) + /* Set TX interrupt vector and priority */ + (void) CyIntSetVector(UART_Bridge_TX_VECT_NUM, &UART_Bridge_TXISR); + CyIntSetPriority(UART_Bridge_TX_VECT_NUM, UART_Bridge_TX_PRIOR_NUM); + #endif /* (UART_Bridge_TX_INTERRUPT_ENABLED) */ + + /* Write Counter Value for TX Bit Clk Generator*/ + #if (UART_Bridge_TXCLKGEN_DP) + UART_Bridge_TXBITCLKGEN_CTR_REG = UART_Bridge_BIT_CENTER; + UART_Bridge_TXBITCLKTX_COMPLETE_REG = ((UART_Bridge_NUMBER_OF_DATA_BITS + + UART_Bridge_NUMBER_OF_START_BIT) * UART_Bridge_OVER_SAMPLE_COUNT) - 1u; + #else + UART_Bridge_TXBITCTR_PERIOD_REG = ((UART_Bridge_NUMBER_OF_DATA_BITS + + UART_Bridge_NUMBER_OF_START_BIT) * UART_Bridge_OVER_SAMPLE_8) - 1u; + #endif /* End UART_Bridge_TXCLKGEN_DP */ + + /* Configure the Initial TX interrupt mask */ + #if (UART_Bridge_TX_INTERRUPT_ENABLED) + UART_Bridge_TXSTATUS_MASK_REG = UART_Bridge_TX_STS_FIFO_EMPTY; + #else + UART_Bridge_TXSTATUS_MASK_REG = UART_Bridge_INIT_TX_INTERRUPTS_MASK; + #endif /*End UART_Bridge_TX_INTERRUPT_ENABLED*/ + + #endif /* End UART_Bridge_TX_ENABLED */ + + #if(UART_Bridge_PARITY_TYPE_SW) /* Write Parity to Control Register */ + UART_Bridge_WriteControlRegister( \ + (UART_Bridge_ReadControlRegister() & (uint8)~UART_Bridge_CTRL_PARITY_TYPE_MASK) | \ + (uint8)(UART_Bridge_PARITY_TYPE << UART_Bridge_CTRL_PARITY_TYPE0_SHIFT) ); + #endif /* End UART_Bridge_PARITY_TYPE_SW */ +} + + +/******************************************************************************* +* Function Name: UART_Bridge_Enable +******************************************************************************** +* +* Summary: +* Activates the hardware and begins component operation. It is not necessary +* to call UART_Bridge_Enable() because the UART_Bridge_Start() API +* calls this function, which is the preferred method to begin component +* operation. + +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* UART_Bridge_rxAddressDetected - set to initial state (0). +* +*******************************************************************************/ +void UART_Bridge_Enable(void) +{ + uint8 enableInterrupts; + enableInterrupts = CyEnterCriticalSection(); + + #if (UART_Bridge_RX_ENABLED || UART_Bridge_HD_ENABLED) + /* RX Counter (Count7) Enable */ + UART_Bridge_RXBITCTR_CONTROL_REG |= UART_Bridge_CNTR_ENABLE; + + /* Enable the RX Interrupt */ + UART_Bridge_RXSTATUS_ACTL_REG |= UART_Bridge_INT_ENABLE; + + #if (UART_Bridge_RX_INTERRUPT_ENABLED) + UART_Bridge_EnableRxInt(); + + #if (UART_Bridge_RXHW_ADDRESS_ENABLED) + UART_Bridge_rxAddressDetected = 0u; + #endif /* (UART_Bridge_RXHW_ADDRESS_ENABLED) */ + #endif /* (UART_Bridge_RX_INTERRUPT_ENABLED) */ + #endif /* (UART_Bridge_RX_ENABLED || UART_Bridge_HD_ENABLED) */ + + #if(UART_Bridge_TX_ENABLED) + /* TX Counter (DP/Count7) Enable */ + #if(!UART_Bridge_TXCLKGEN_DP) + UART_Bridge_TXBITCTR_CONTROL_REG |= UART_Bridge_CNTR_ENABLE; + #endif /* End UART_Bridge_TXCLKGEN_DP */ + + /* Enable the TX Interrupt */ + UART_Bridge_TXSTATUS_ACTL_REG |= UART_Bridge_INT_ENABLE; + #if (UART_Bridge_TX_INTERRUPT_ENABLED) + UART_Bridge_ClearPendingTxInt(); /* Clear history of TX_NOT_EMPTY */ + UART_Bridge_EnableTxInt(); + #endif /* (UART_Bridge_TX_INTERRUPT_ENABLED) */ + #endif /* (UART_Bridge_TX_INTERRUPT_ENABLED) */ + + #if (UART_Bridge_INTERNAL_CLOCK_USED) + UART_Bridge_IntClock_Start(); /* Enable the clock */ + #endif /* (UART_Bridge_INTERNAL_CLOCK_USED) */ + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: UART_Bridge_Stop +******************************************************************************** +* +* Summary: +* Disables the UART operation. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void UART_Bridge_Stop(void) +{ + uint8 enableInterrupts; + enableInterrupts = CyEnterCriticalSection(); + + /* Write Bit Counter Disable */ + #if (UART_Bridge_RX_ENABLED || UART_Bridge_HD_ENABLED) + UART_Bridge_RXBITCTR_CONTROL_REG &= (uint8) ~UART_Bridge_CNTR_ENABLE; + #endif /* (UART_Bridge_RX_ENABLED || UART_Bridge_HD_ENABLED) */ + + #if (UART_Bridge_TX_ENABLED) + #if(!UART_Bridge_TXCLKGEN_DP) + UART_Bridge_TXBITCTR_CONTROL_REG &= (uint8) ~UART_Bridge_CNTR_ENABLE; + #endif /* (!UART_Bridge_TXCLKGEN_DP) */ + #endif /* (UART_Bridge_TX_ENABLED) */ + + #if (UART_Bridge_INTERNAL_CLOCK_USED) + UART_Bridge_IntClock_Stop(); /* Disable the clock */ + #endif /* (UART_Bridge_INTERNAL_CLOCK_USED) */ + + /* Disable internal interrupt component */ + #if (UART_Bridge_RX_ENABLED || UART_Bridge_HD_ENABLED) + UART_Bridge_RXSTATUS_ACTL_REG &= (uint8) ~UART_Bridge_INT_ENABLE; + + #if (UART_Bridge_RX_INTERRUPT_ENABLED) + UART_Bridge_DisableRxInt(); + #endif /* (UART_Bridge_RX_INTERRUPT_ENABLED) */ + #endif /* (UART_Bridge_RX_ENABLED || UART_Bridge_HD_ENABLED) */ + + #if (UART_Bridge_TX_ENABLED) + UART_Bridge_TXSTATUS_ACTL_REG &= (uint8) ~UART_Bridge_INT_ENABLE; + + #if (UART_Bridge_TX_INTERRUPT_ENABLED) + UART_Bridge_DisableTxInt(); + #endif /* (UART_Bridge_TX_INTERRUPT_ENABLED) */ + #endif /* (UART_Bridge_TX_ENABLED) */ + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: UART_Bridge_ReadControlRegister +******************************************************************************** +* +* Summary: +* Returns the current value of the control register. +* +* Parameters: +* None. +* +* Return: +* Contents of the control register. +* +*******************************************************************************/ +uint8 UART_Bridge_ReadControlRegister(void) +{ + #if (UART_Bridge_CONTROL_REG_REMOVED) + return(0u); + #else + return(UART_Bridge_CONTROL_REG); + #endif /* (UART_Bridge_CONTROL_REG_REMOVED) */ +} + + +/******************************************************************************* +* Function Name: UART_Bridge_WriteControlRegister +******************************************************************************** +* +* Summary: +* Writes an 8-bit value into the control register +* +* Parameters: +* control: control register value +* +* Return: +* None. +* +*******************************************************************************/ +void UART_Bridge_WriteControlRegister(uint8 control) +{ + #if (UART_Bridge_CONTROL_REG_REMOVED) + if(0u != control) + { + /* Suppress compiler warning */ + } + #else + UART_Bridge_CONTROL_REG = control; + #endif /* (UART_Bridge_CONTROL_REG_REMOVED) */ +} + + +#if(UART_Bridge_RX_ENABLED || UART_Bridge_HD_ENABLED) + /******************************************************************************* + * Function Name: UART_Bridge_SetRxInterruptMode + ******************************************************************************** + * + * Summary: + * Configures the RX interrupt sources enabled. + * + * Parameters: + * IntSrc: Bit field containing the RX interrupts to enable. Based on the + * bit-field arrangement of the status register. This value must be a + * combination of status register bit-masks shown below: + * UART_Bridge_RX_STS_FIFO_NOTEMPTY Interrupt on byte received. + * UART_Bridge_RX_STS_PAR_ERROR Interrupt on parity error. + * UART_Bridge_RX_STS_STOP_ERROR Interrupt on stop error. + * UART_Bridge_RX_STS_BREAK Interrupt on break. + * UART_Bridge_RX_STS_OVERRUN Interrupt on overrun error. + * UART_Bridge_RX_STS_ADDR_MATCH Interrupt on address match. + * UART_Bridge_RX_STS_MRKSPC Interrupt on address detect. + * + * Return: + * None. + * + * Theory: + * Enables the output of specific status bits to the interrupt controller + * + *******************************************************************************/ + void UART_Bridge_SetRxInterruptMode(uint8 intSrc) + { + UART_Bridge_RXSTATUS_MASK_REG = intSrc; + } + + + /******************************************************************************* + * Function Name: UART_Bridge_ReadRxData + ******************************************************************************** + * + * Summary: + * Returns the next byte of received data. This function returns data without + * checking the status. You must check the status separately. + * + * Parameters: + * None. + * + * Return: + * Received data from RX register + * + * Global Variables: + * UART_Bridge_rxBuffer - RAM buffer pointer for save received data. + * UART_Bridge_rxBufferWrite - cyclic index for write to rxBuffer, + * checked to identify new data. + * UART_Bridge_rxBufferRead - cyclic index for read from rxBuffer, + * incremented after each byte has been read from buffer. + * UART_Bridge_rxBufferLoopDetect - cleared if loop condition was detected + * in RX ISR. + * + * Reentrant: + * No. + * + *******************************************************************************/ + uint8 UART_Bridge_ReadRxData(void) + { + uint8 rxData; + + #if (UART_Bridge_RX_INTERRUPT_ENABLED) + + uint16 locRxBufferRead; + uint16 locRxBufferWrite; + + /* Protect variables that could change on interrupt */ + UART_Bridge_DisableRxInt(); + + locRxBufferRead = UART_Bridge_rxBufferRead; + locRxBufferWrite = UART_Bridge_rxBufferWrite; + + if( (UART_Bridge_rxBufferLoopDetect != 0u) || (locRxBufferRead != locRxBufferWrite) ) + { + rxData = UART_Bridge_rxBuffer[locRxBufferRead]; + locRxBufferRead++; + + if(locRxBufferRead >= UART_Bridge_RX_BUFFER_SIZE) + { + locRxBufferRead = 0u; + } + /* Update the real pointer */ + UART_Bridge_rxBufferRead = locRxBufferRead; + + if(UART_Bridge_rxBufferLoopDetect != 0u) + { + UART_Bridge_rxBufferLoopDetect = 0u; + #if ((UART_Bridge_RX_INTERRUPT_ENABLED) && (UART_Bridge_FLOW_CONTROL != 0u)) + /* When Hardware Flow Control selected - return RX mask */ + #if( UART_Bridge_HD_ENABLED ) + if((UART_Bridge_CONTROL_REG & UART_Bridge_CTRL_HD_SEND) == 0u) + { /* In Half duplex mode return RX mask only in RX + * configuration set, otherwise + * mask will be returned in LoadRxConfig() API. + */ + UART_Bridge_RXSTATUS_MASK_REG |= UART_Bridge_RX_STS_FIFO_NOTEMPTY; + } + #else + UART_Bridge_RXSTATUS_MASK_REG |= UART_Bridge_RX_STS_FIFO_NOTEMPTY; + #endif /* end UART_Bridge_HD_ENABLED */ + #endif /* ((UART_Bridge_RX_INTERRUPT_ENABLED) && (UART_Bridge_FLOW_CONTROL != 0u)) */ + } + } + else + { /* Needs to check status for RX_STS_FIFO_NOTEMPTY bit */ + rxData = UART_Bridge_RXDATA_REG; + } + + UART_Bridge_EnableRxInt(); + + #else + + /* Needs to check status for RX_STS_FIFO_NOTEMPTY bit */ + rxData = UART_Bridge_RXDATA_REG; + + #endif /* (UART_Bridge_RX_INTERRUPT_ENABLED) */ + + return(rxData); + } + + + /******************************************************************************* + * Function Name: UART_Bridge_ReadRxStatus + ******************************************************************************** + * + * Summary: + * Returns the current state of the receiver status register and the software + * buffer overflow status. + * + * Parameters: + * None. + * + * Return: + * Current state of the status register. + * + * Side Effect: + * All status register bits are clear-on-read except + * UART_Bridge_RX_STS_FIFO_NOTEMPTY. + * UART_Bridge_RX_STS_FIFO_NOTEMPTY clears immediately after RX data + * register read. + * + * Global Variables: + * UART_Bridge_rxBufferOverflow - used to indicate overload condition. + * It set to one in RX interrupt when there isn't free space in + * UART_Bridge_rxBufferRead to write new data. This condition returned + * and cleared to zero by this API as an + * UART_Bridge_RX_STS_SOFT_BUFF_OVER bit along with RX Status register + * bits. + * + *******************************************************************************/ + uint8 UART_Bridge_ReadRxStatus(void) + { + uint8 status; + + status = UART_Bridge_RXSTATUS_REG & UART_Bridge_RX_HW_MASK; + + #if (UART_Bridge_RX_INTERRUPT_ENABLED) + if(UART_Bridge_rxBufferOverflow != 0u) + { + status |= UART_Bridge_RX_STS_SOFT_BUFF_OVER; + UART_Bridge_rxBufferOverflow = 0u; + } + #endif /* (UART_Bridge_RX_INTERRUPT_ENABLED) */ + + return(status); + } + + + /******************************************************************************* + * Function Name: UART_Bridge_GetChar + ******************************************************************************** + * + * Summary: + * Returns the last received byte of data. UART_Bridge_GetChar() is + * designed for ASCII characters and returns a uint8 where 1 to 255 are values + * for valid characters and 0 indicates an error occurred or no data is present. + * + * Parameters: + * None. + * + * Return: + * Character read from UART RX buffer. ASCII characters from 1 to 255 are valid. + * A returned zero signifies an error condition or no data available. + * + * Global Variables: + * UART_Bridge_rxBuffer - RAM buffer pointer for save received data. + * UART_Bridge_rxBufferWrite - cyclic index for write to rxBuffer, + * checked to identify new data. + * UART_Bridge_rxBufferRead - cyclic index for read from rxBuffer, + * incremented after each byte has been read from buffer. + * UART_Bridge_rxBufferLoopDetect - cleared if loop condition was detected + * in RX ISR. + * + * Reentrant: + * No. + * + *******************************************************************************/ + uint8 UART_Bridge_GetChar(void) + { + uint8 rxData = 0u; + uint8 rxStatus; + + #if (UART_Bridge_RX_INTERRUPT_ENABLED) + uint16 locRxBufferRead; + uint16 locRxBufferWrite; + + /* Protect variables that could change on interrupt */ + UART_Bridge_DisableRxInt(); + + locRxBufferRead = UART_Bridge_rxBufferRead; + locRxBufferWrite = UART_Bridge_rxBufferWrite; + + if( (UART_Bridge_rxBufferLoopDetect != 0u) || (locRxBufferRead != locRxBufferWrite) ) + { + rxData = UART_Bridge_rxBuffer[locRxBufferRead]; + locRxBufferRead++; + if(locRxBufferRead >= UART_Bridge_RX_BUFFER_SIZE) + { + locRxBufferRead = 0u; + } + /* Update the real pointer */ + UART_Bridge_rxBufferRead = locRxBufferRead; + + if(UART_Bridge_rxBufferLoopDetect != 0u) + { + UART_Bridge_rxBufferLoopDetect = 0u; + #if( (UART_Bridge_RX_INTERRUPT_ENABLED) && (UART_Bridge_FLOW_CONTROL != 0u) ) + /* When Hardware Flow Control selected - return RX mask */ + #if( UART_Bridge_HD_ENABLED ) + if((UART_Bridge_CONTROL_REG & UART_Bridge_CTRL_HD_SEND) == 0u) + { /* In Half duplex mode return RX mask only if + * RX configuration set, otherwise + * mask will be returned in LoadRxConfig() API. + */ + UART_Bridge_RXSTATUS_MASK_REG |= UART_Bridge_RX_STS_FIFO_NOTEMPTY; + } + #else + UART_Bridge_RXSTATUS_MASK_REG |= UART_Bridge_RX_STS_FIFO_NOTEMPTY; + #endif /* end UART_Bridge_HD_ENABLED */ + #endif /* UART_Bridge_RX_INTERRUPT_ENABLED and Hardware flow control*/ + } + + } + else + { rxStatus = UART_Bridge_RXSTATUS_REG; + if((rxStatus & UART_Bridge_RX_STS_FIFO_NOTEMPTY) != 0u) + { /* Read received data from FIFO */ + rxData = UART_Bridge_RXDATA_REG; + /*Check status on error*/ + if((rxStatus & (UART_Bridge_RX_STS_BREAK | UART_Bridge_RX_STS_PAR_ERROR | + UART_Bridge_RX_STS_STOP_ERROR | UART_Bridge_RX_STS_OVERRUN)) != 0u) + { + rxData = 0u; + } + } + } + + UART_Bridge_EnableRxInt(); + + #else + + rxStatus =UART_Bridge_RXSTATUS_REG; + if((rxStatus & UART_Bridge_RX_STS_FIFO_NOTEMPTY) != 0u) + { + /* Read received data from FIFO */ + rxData = UART_Bridge_RXDATA_REG; + + /*Check status on error*/ + if((rxStatus & (UART_Bridge_RX_STS_BREAK | UART_Bridge_RX_STS_PAR_ERROR | + UART_Bridge_RX_STS_STOP_ERROR | UART_Bridge_RX_STS_OVERRUN)) != 0u) + { + rxData = 0u; + } + } + #endif /* (UART_Bridge_RX_INTERRUPT_ENABLED) */ + + return(rxData); + } + + + /******************************************************************************* + * Function Name: UART_Bridge_GetByte + ******************************************************************************** + * + * Summary: + * Reads UART RX buffer immediately, returns received character and error + * condition. + * + * Parameters: + * None. + * + * Return: + * MSB contains status and LSB contains UART RX data. If the MSB is nonzero, + * an error has occurred. + * + * Reentrant: + * No. + * + *******************************************************************************/ + uint16 UART_Bridge_GetByte(void) + { + + #if (UART_Bridge_RX_INTERRUPT_ENABLED) + uint16 locErrorStatus; + /* Protect variables that could change on interrupt */ + UART_Bridge_DisableRxInt(); + locErrorStatus = (uint16)UART_Bridge_errorStatus; + UART_Bridge_errorStatus = 0u; + UART_Bridge_EnableRxInt(); + return ( (uint16)(locErrorStatus << 8u) | UART_Bridge_ReadRxData() ); + #else + return ( ((uint16)UART_Bridge_ReadRxStatus() << 8u) | UART_Bridge_ReadRxData() ); + #endif /* UART_Bridge_RX_INTERRUPT_ENABLED */ + + } + + + /******************************************************************************* + * Function Name: UART_Bridge_GetRxBufferSize + ******************************************************************************** + * + * Summary: + * Returns the number of received bytes available in the RX buffer. + * * RX software buffer is disabled (RX Buffer Size parameter is equal to 4): + * returns 0 for empty RX FIFO or 1 for not empty RX FIFO. + * * RX software buffer is enabled: returns the number of bytes available in + * the RX software buffer. Bytes available in the RX FIFO do not take to + * account. + * + * Parameters: + * None. + * + * Return: + * uint16: Number of bytes in the RX buffer. + * Return value type depends on RX Buffer Size parameter. + * + * Global Variables: + * UART_Bridge_rxBufferWrite - used to calculate left bytes. + * UART_Bridge_rxBufferRead - used to calculate left bytes. + * UART_Bridge_rxBufferLoopDetect - checked to decide left bytes amount. + * + * Reentrant: + * No. + * + * Theory: + * Allows the user to find out how full the RX Buffer is. + * + *******************************************************************************/ + uint16 UART_Bridge_GetRxBufferSize(void) + + { + uint16 size; + + #if (UART_Bridge_RX_INTERRUPT_ENABLED) + + /* Protect variables that could change on interrupt */ + UART_Bridge_DisableRxInt(); + + if(UART_Bridge_rxBufferRead == UART_Bridge_rxBufferWrite) + { + if(UART_Bridge_rxBufferLoopDetect != 0u) + { + size = UART_Bridge_RX_BUFFER_SIZE; + } + else + { + size = 0u; + } + } + else if(UART_Bridge_rxBufferRead < UART_Bridge_rxBufferWrite) + { + size = (UART_Bridge_rxBufferWrite - UART_Bridge_rxBufferRead); + } + else + { + size = (UART_Bridge_RX_BUFFER_SIZE - UART_Bridge_rxBufferRead) + UART_Bridge_rxBufferWrite; + } + + UART_Bridge_EnableRxInt(); + + #else + + /* We can only know if there is data in the fifo. */ + size = ((UART_Bridge_RXSTATUS_REG & UART_Bridge_RX_STS_FIFO_NOTEMPTY) != 0u) ? 1u : 0u; + + #endif /* (UART_Bridge_RX_INTERRUPT_ENABLED) */ + + return(size); + } + + + /******************************************************************************* + * Function Name: UART_Bridge_ClearRxBuffer + ******************************************************************************** + * + * Summary: + * Clears the receiver memory buffer and hardware RX FIFO of all received data. + * + * Parameters: + * None. + * + * Return: + * None. + * + * Global Variables: + * UART_Bridge_rxBufferWrite - cleared to zero. + * UART_Bridge_rxBufferRead - cleared to zero. + * UART_Bridge_rxBufferLoopDetect - cleared to zero. + * UART_Bridge_rxBufferOverflow - cleared to zero. + * + * Reentrant: + * No. + * + * Theory: + * Setting the pointers to zero makes the system believe there is no data to + * read and writing will resume at address 0 overwriting any data that may + * have remained in the RAM. + * + * Side Effects: + * Any received data not read from the RAM or FIFO buffer will be lost. + * + *******************************************************************************/ + void UART_Bridge_ClearRxBuffer(void) + { + uint8 enableInterrupts; + + /* Clear the HW FIFO */ + enableInterrupts = CyEnterCriticalSection(); + UART_Bridge_RXDATA_AUX_CTL_REG |= (uint8) UART_Bridge_RX_FIFO_CLR; + UART_Bridge_RXDATA_AUX_CTL_REG &= (uint8) ~UART_Bridge_RX_FIFO_CLR; + CyExitCriticalSection(enableInterrupts); + + #if (UART_Bridge_RX_INTERRUPT_ENABLED) + + /* Protect variables that could change on interrupt. */ + UART_Bridge_DisableRxInt(); + + UART_Bridge_rxBufferRead = 0u; + UART_Bridge_rxBufferWrite = 0u; + UART_Bridge_rxBufferLoopDetect = 0u; + UART_Bridge_rxBufferOverflow = 0u; + + UART_Bridge_EnableRxInt(); + + #endif /* (UART_Bridge_RX_INTERRUPT_ENABLED) */ + + } + + + /******************************************************************************* + * Function Name: UART_Bridge_SetRxAddressMode + ******************************************************************************** + * + * Summary: + * Sets the software controlled Addressing mode used by the RX portion of the + * UART. + * + * Parameters: + * addressMode: Enumerated value indicating the mode of RX addressing + * UART_Bridge__B_UART__AM_SW_BYTE_BYTE - Software Byte-by-Byte address + * detection + * UART_Bridge__B_UART__AM_SW_DETECT_TO_BUFFER - Software Detect to Buffer + * address detection + * UART_Bridge__B_UART__AM_HW_BYTE_BY_BYTE - Hardware Byte-by-Byte address + * detection + * UART_Bridge__B_UART__AM_HW_DETECT_TO_BUFFER - Hardware Detect to Buffer + * address detection + * UART_Bridge__B_UART__AM_NONE - No address detection + * + * Return: + * None. + * + * Global Variables: + * UART_Bridge_rxAddressMode - the parameter stored in this variable for + * the farther usage in RX ISR. + * UART_Bridge_rxAddressDetected - set to initial state (0). + * + *******************************************************************************/ + void UART_Bridge_SetRxAddressMode(uint8 addressMode) + + { + #if(UART_Bridge_RXHW_ADDRESS_ENABLED) + #if(UART_Bridge_CONTROL_REG_REMOVED) + if(0u != addressMode) + { + /* Suppress compiler warning */ + } + #else /* UART_Bridge_CONTROL_REG_REMOVED */ + uint8 tmpCtrl; + tmpCtrl = UART_Bridge_CONTROL_REG & (uint8)~UART_Bridge_CTRL_RXADDR_MODE_MASK; + tmpCtrl |= (uint8)(addressMode << UART_Bridge_CTRL_RXADDR_MODE0_SHIFT); + UART_Bridge_CONTROL_REG = tmpCtrl; + + #if(UART_Bridge_RX_INTERRUPT_ENABLED && \ + (UART_Bridge_RXBUFFERSIZE > UART_Bridge_FIFO_LENGTH) ) + UART_Bridge_rxAddressMode = addressMode; + UART_Bridge_rxAddressDetected = 0u; + #endif /* End UART_Bridge_RXBUFFERSIZE > UART_Bridge_FIFO_LENGTH*/ + #endif /* End UART_Bridge_CONTROL_REG_REMOVED */ + #else /* UART_Bridge_RXHW_ADDRESS_ENABLED */ + if(0u != addressMode) + { + /* Suppress compiler warning */ + } + #endif /* End UART_Bridge_RXHW_ADDRESS_ENABLED */ + } + + + /******************************************************************************* + * Function Name: UART_Bridge_SetRxAddress1 + ******************************************************************************** + * + * Summary: + * Sets the first of two hardware-detectable receiver addresses. + * + * Parameters: + * address: Address #1 for hardware address detection. + * + * Return: + * None. + * + *******************************************************************************/ + void UART_Bridge_SetRxAddress1(uint8 address) + { + UART_Bridge_RXADDRESS1_REG = address; + } + + + /******************************************************************************* + * Function Name: UART_Bridge_SetRxAddress2 + ******************************************************************************** + * + * Summary: + * Sets the second of two hardware-detectable receiver addresses. + * + * Parameters: + * address: Address #2 for hardware address detection. + * + * Return: + * None. + * + *******************************************************************************/ + void UART_Bridge_SetRxAddress2(uint8 address) + { + UART_Bridge_RXADDRESS2_REG = address; + } + +#endif /* UART_Bridge_RX_ENABLED || UART_Bridge_HD_ENABLED*/ + + +#if( (UART_Bridge_TX_ENABLED) || (UART_Bridge_HD_ENABLED) ) + /******************************************************************************* + * Function Name: UART_Bridge_SetTxInterruptMode + ******************************************************************************** + * + * Summary: + * Configures the TX interrupt sources to be enabled, but does not enable the + * interrupt. + * + * Parameters: + * intSrc: Bit field containing the TX interrupt sources to enable + * UART_Bridge_TX_STS_COMPLETE Interrupt on TX byte complete + * UART_Bridge_TX_STS_FIFO_EMPTY Interrupt when TX FIFO is empty + * UART_Bridge_TX_STS_FIFO_FULL Interrupt when TX FIFO is full + * UART_Bridge_TX_STS_FIFO_NOT_FULL Interrupt when TX FIFO is not full + * + * Return: + * None. + * + * Theory: + * Enables the output of specific status bits to the interrupt controller + * + *******************************************************************************/ + void UART_Bridge_SetTxInterruptMode(uint8 intSrc) + { + UART_Bridge_TXSTATUS_MASK_REG = intSrc; + } + + + /******************************************************************************* + * Function Name: UART_Bridge_WriteTxData + ******************************************************************************** + * + * Summary: + * Places a byte of data into the transmit buffer to be sent when the bus is + * available without checking the TX status register. You must check status + * separately. + * + * Parameters: + * txDataByte: data byte + * + * Return: + * None. + * + * Global Variables: + * UART_Bridge_txBuffer - RAM buffer pointer for save data for transmission + * UART_Bridge_txBufferWrite - cyclic index for write to txBuffer, + * incremented after each byte saved to buffer. + * UART_Bridge_txBufferRead - cyclic index for read from txBuffer, + * checked to identify the condition to write to FIFO directly or to TX buffer + * UART_Bridge_initVar - checked to identify that the component has been + * initialized. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void UART_Bridge_WriteTxData(uint8 txDataByte) + { + /* If not Initialized then skip this function*/ + if(UART_Bridge_initVar != 0u) + { + #if (UART_Bridge_TX_INTERRUPT_ENABLED) + + /* Protect variables that could change on interrupt. */ + UART_Bridge_DisableTxInt(); + + if( (UART_Bridge_txBufferRead == UART_Bridge_txBufferWrite) && + ((UART_Bridge_TXSTATUS_REG & UART_Bridge_TX_STS_FIFO_FULL) == 0u) ) + { + /* Add directly to the FIFO. */ + UART_Bridge_TXDATA_REG = txDataByte; + } + else + { + if(UART_Bridge_txBufferWrite >= UART_Bridge_TX_BUFFER_SIZE) + { + UART_Bridge_txBufferWrite = 0u; + } + + UART_Bridge_txBuffer[UART_Bridge_txBufferWrite] = txDataByte; + + /* Add to the software buffer. */ + UART_Bridge_txBufferWrite++; + } + + UART_Bridge_EnableTxInt(); + + #else + + /* Add directly to the FIFO. */ + UART_Bridge_TXDATA_REG = txDataByte; + + #endif /*(UART_Bridge_TX_INTERRUPT_ENABLED) */ + } + } + + + /******************************************************************************* + * Function Name: UART_Bridge_ReadTxStatus + ******************************************************************************** + * + * Summary: + * Reads the status register for the TX portion of the UART. + * + * Parameters: + * None. + * + * Return: + * Contents of the status register + * + * Theory: + * This function reads the TX status register, which is cleared on read. + * It is up to the user to handle all bits in this return value accordingly, + * even if the bit was not enabled as an interrupt source the event happened + * and must be handled accordingly. + * + *******************************************************************************/ + uint8 UART_Bridge_ReadTxStatus(void) + { + return(UART_Bridge_TXSTATUS_REG); + } + + + /******************************************************************************* + * Function Name: UART_Bridge_PutChar + ******************************************************************************** + * + * Summary: + * Puts a byte of data into the transmit buffer to be sent when the bus is + * available. This is a blocking API that waits until the TX buffer has room to + * hold the data. + * + * Parameters: + * txDataByte: Byte containing the data to transmit + * + * Return: + * None. + * + * Global Variables: + * UART_Bridge_txBuffer - RAM buffer pointer for save data for transmission + * UART_Bridge_txBufferWrite - cyclic index for write to txBuffer, + * checked to identify free space in txBuffer and incremented after each byte + * saved to buffer. + * UART_Bridge_txBufferRead - cyclic index for read from txBuffer, + * checked to identify free space in txBuffer. + * UART_Bridge_initVar - checked to identify that the component has been + * initialized. + * + * Reentrant: + * No. + * + * Theory: + * Allows the user to transmit any byte of data in a single transfer + * + *******************************************************************************/ + void UART_Bridge_PutChar(uint8 txDataByte) + { + #if (UART_Bridge_TX_INTERRUPT_ENABLED) + /* The temporary output pointer is used since it takes two instructions + * to increment with a wrap, and we can't risk doing that with the real + * pointer and getting an interrupt in between instructions. + */ + uint16 locTxBufferWrite; + uint16 locTxBufferRead; + + do + { /* Block if software buffer is full, so we don't overwrite. */ + + #if ((UART_Bridge_TX_BUFFER_SIZE > UART_Bridge_MAX_BYTE_VALUE) && (CY_PSOC3)) + /* Disable TX interrupt to protect variables from modification */ + UART_Bridge_DisableTxInt(); + #endif /* (UART_Bridge_TX_BUFFER_SIZE > UART_Bridge_MAX_BYTE_VALUE) && (CY_PSOC3) */ + + locTxBufferWrite = UART_Bridge_txBufferWrite; + locTxBufferRead = UART_Bridge_txBufferRead; + + #if ((UART_Bridge_TX_BUFFER_SIZE > UART_Bridge_MAX_BYTE_VALUE) && (CY_PSOC3)) + /* Enable interrupt to continue transmission */ + UART_Bridge_EnableTxInt(); + #endif /* (UART_Bridge_TX_BUFFER_SIZE > UART_Bridge_MAX_BYTE_VALUE) && (CY_PSOC3) */ + } + while( (locTxBufferWrite < locTxBufferRead) ? (locTxBufferWrite == (locTxBufferRead - 1u)) : + ((locTxBufferWrite - locTxBufferRead) == + (uint16)(UART_Bridge_TX_BUFFER_SIZE - 1u)) ); + + if( (locTxBufferRead == locTxBufferWrite) && + ((UART_Bridge_TXSTATUS_REG & UART_Bridge_TX_STS_FIFO_FULL) == 0u) ) + { + /* Add directly to the FIFO */ + UART_Bridge_TXDATA_REG = txDataByte; + } + else + { + if(locTxBufferWrite >= UART_Bridge_TX_BUFFER_SIZE) + { + locTxBufferWrite = 0u; + } + /* Add to the software buffer. */ + UART_Bridge_txBuffer[locTxBufferWrite] = txDataByte; + locTxBufferWrite++; + + /* Finally, update the real output pointer */ + #if ((UART_Bridge_TX_BUFFER_SIZE > UART_Bridge_MAX_BYTE_VALUE) && (CY_PSOC3)) + UART_Bridge_DisableTxInt(); + #endif /* (UART_Bridge_TX_BUFFER_SIZE > UART_Bridge_MAX_BYTE_VALUE) && (CY_PSOC3) */ + + UART_Bridge_txBufferWrite = locTxBufferWrite; + + #if ((UART_Bridge_TX_BUFFER_SIZE > UART_Bridge_MAX_BYTE_VALUE) && (CY_PSOC3)) + UART_Bridge_EnableTxInt(); + #endif /* (UART_Bridge_TX_BUFFER_SIZE > UART_Bridge_MAX_BYTE_VALUE) && (CY_PSOC3) */ + + if(0u != (UART_Bridge_TXSTATUS_REG & UART_Bridge_TX_STS_FIFO_EMPTY)) + { + /* Trigger TX interrupt to send software buffer */ + UART_Bridge_SetPendingTxInt(); + } + } + + #else + + while((UART_Bridge_TXSTATUS_REG & UART_Bridge_TX_STS_FIFO_FULL) != 0u) + { + /* Wait for room in the FIFO */ + } + + /* Add directly to the FIFO */ + UART_Bridge_TXDATA_REG = txDataByte; + + #endif /* UART_Bridge_TX_INTERRUPT_ENABLED */ + } + + + /******************************************************************************* + * Function Name: UART_Bridge_PutString + ******************************************************************************** + * + * Summary: + * Sends a NULL terminated string to the TX buffer for transmission. + * + * Parameters: + * string[]: Pointer to the null terminated string array residing in RAM or ROM + * + * Return: + * None. + * + * Global Variables: + * UART_Bridge_initVar - checked to identify that the component has been + * initialized. + * + * Reentrant: + * No. + * + * Theory: + * If there is not enough memory in the TX buffer for the entire string, this + * function blocks until the last character of the string is loaded into the + * TX buffer. + * + *******************************************************************************/ + void UART_Bridge_PutString(const char8 string[]) + { + uint16 bufIndex = 0u; + + /* If not Initialized then skip this function */ + if(UART_Bridge_initVar != 0u) + { + /* This is a blocking function, it will not exit until all data is sent */ + while(string[bufIndex] != (char8) 0) + { + UART_Bridge_PutChar((uint8)string[bufIndex]); + bufIndex++; + } + } + } + + + /******************************************************************************* + * Function Name: UART_Bridge_PutArray + ******************************************************************************** + * + * Summary: + * Places N bytes of data from a memory array into the TX buffer for + * transmission. + * + * Parameters: + * string[]: Address of the memory array residing in RAM or ROM. + * byteCount: Number of bytes to be transmitted. The type depends on TX Buffer + * Size parameter. + * + * Return: + * None. + * + * Global Variables: + * UART_Bridge_initVar - checked to identify that the component has been + * initialized. + * + * Reentrant: + * No. + * + * Theory: + * If there is not enough memory in the TX buffer for the entire string, this + * function blocks until the last character of the string is loaded into the + * TX buffer. + * + *******************************************************************************/ + void UART_Bridge_PutArray(const uint8 string[], uint16 byteCount) + + { + uint16 bufIndex = 0u; + + /* If not Initialized then skip this function */ + if(UART_Bridge_initVar != 0u) + { + while(bufIndex < byteCount) + { + UART_Bridge_PutChar(string[bufIndex]); + bufIndex++; + } + } + } + + + /******************************************************************************* + * Function Name: UART_Bridge_PutCRLF + ******************************************************************************** + * + * Summary: + * Writes a byte of data followed by a carriage return (0x0D) and line feed + * (0x0A) to the transmit buffer. + * + * Parameters: + * txDataByte: Data byte to transmit before the carriage return and line feed. + * + * Return: + * None. + * + * Global Variables: + * UART_Bridge_initVar - checked to identify that the component has been + * initialized. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void UART_Bridge_PutCRLF(uint8 txDataByte) + { + /* If not Initialized then skip this function */ + if(UART_Bridge_initVar != 0u) + { + UART_Bridge_PutChar(txDataByte); + UART_Bridge_PutChar(0x0Du); + UART_Bridge_PutChar(0x0Au); + } + } + + + /******************************************************************************* + * Function Name: UART_Bridge_GetTxBufferSize + ******************************************************************************** + * + * Summary: + * Returns the number of bytes in the TX buffer which are waiting to be + * transmitted. + * * TX software buffer is disabled (TX Buffer Size parameter is equal to 4): + * returns 0 for empty TX FIFO, 1 for not full TX FIFO or 4 for full TX FIFO. + * * TX software buffer is enabled: returns the number of bytes in the TX + * software buffer which are waiting to be transmitted. Bytes available in the + * TX FIFO do not count. + * + * Parameters: + * None. + * + * Return: + * Number of bytes used in the TX buffer. Return value type depends on the TX + * Buffer Size parameter. + * + * Global Variables: + * UART_Bridge_txBufferWrite - used to calculate left space. + * UART_Bridge_txBufferRead - used to calculate left space. + * + * Reentrant: + * No. + * + * Theory: + * Allows the user to find out how full the TX Buffer is. + * + *******************************************************************************/ + uint16 UART_Bridge_GetTxBufferSize(void) + + { + uint16 size; + + #if (UART_Bridge_TX_INTERRUPT_ENABLED) + + /* Protect variables that could change on interrupt. */ + UART_Bridge_DisableTxInt(); + + if(UART_Bridge_txBufferRead == UART_Bridge_txBufferWrite) + { + size = 0u; + } + else if(UART_Bridge_txBufferRead < UART_Bridge_txBufferWrite) + { + size = (UART_Bridge_txBufferWrite - UART_Bridge_txBufferRead); + } + else + { + size = (UART_Bridge_TX_BUFFER_SIZE - UART_Bridge_txBufferRead) + + UART_Bridge_txBufferWrite; + } + + UART_Bridge_EnableTxInt(); + + #else + + size = UART_Bridge_TXSTATUS_REG; + + /* Is the fifo is full. */ + if((size & UART_Bridge_TX_STS_FIFO_FULL) != 0u) + { + size = UART_Bridge_FIFO_LENGTH; + } + else if((size & UART_Bridge_TX_STS_FIFO_EMPTY) != 0u) + { + size = 0u; + } + else + { + /* We only know there is data in the fifo. */ + size = 1u; + } + + #endif /* (UART_Bridge_TX_INTERRUPT_ENABLED) */ + + return(size); + } + + + /******************************************************************************* + * Function Name: UART_Bridge_ClearTxBuffer + ******************************************************************************** + * + * Summary: + * Clears all data from the TX buffer and hardware TX FIFO. + * + * Parameters: + * None. + * + * Return: + * None. + * + * Global Variables: + * UART_Bridge_txBufferWrite - cleared to zero. + * UART_Bridge_txBufferRead - cleared to zero. + * + * Reentrant: + * No. + * + * Theory: + * Setting the pointers to zero makes the system believe there is no data to + * read and writing will resume at address 0 overwriting any data that may have + * remained in the RAM. + * + * Side Effects: + * Data waiting in the transmit buffer is not sent; a byte that is currently + * transmitting finishes transmitting. + * + *******************************************************************************/ + void UART_Bridge_ClearTxBuffer(void) + { + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + /* Clear the HW FIFO */ + UART_Bridge_TXDATA_AUX_CTL_REG |= (uint8) UART_Bridge_TX_FIFO_CLR; + UART_Bridge_TXDATA_AUX_CTL_REG &= (uint8) ~UART_Bridge_TX_FIFO_CLR; + CyExitCriticalSection(enableInterrupts); + + #if (UART_Bridge_TX_INTERRUPT_ENABLED) + + /* Protect variables that could change on interrupt. */ + UART_Bridge_DisableTxInt(); + + UART_Bridge_txBufferRead = 0u; + UART_Bridge_txBufferWrite = 0u; + + /* Enable Tx interrupt. */ + UART_Bridge_EnableTxInt(); + + #endif /* (UART_Bridge_TX_INTERRUPT_ENABLED) */ + } + + + /******************************************************************************* + * Function Name: UART_Bridge_SendBreak + ******************************************************************************** + * + * Summary: + * Transmits a break signal on the bus. + * + * Parameters: + * uint8 retMode: Send Break return mode. See the following table for options. + * UART_Bridge_SEND_BREAK - Initialize registers for break, send the Break + * signal and return immediately. + * UART_Bridge_WAIT_FOR_COMPLETE_REINIT - Wait until break transmission is + * complete, reinitialize registers to normal transmission mode then return + * UART_Bridge_REINIT - Reinitialize registers to normal transmission mode + * then return. + * UART_Bridge_SEND_WAIT_REINIT - Performs both options: + * UART_Bridge_SEND_BREAK and UART_Bridge_WAIT_FOR_COMPLETE_REINIT. + * This option is recommended for most cases. + * + * Return: + * None. + * + * Global Variables: + * UART_Bridge_initVar - checked to identify that the component has been + * initialized. + * txPeriod - static variable, used for keeping TX period configuration. + * + * Reentrant: + * No. + * + * Theory: + * SendBreak function initializes registers to send 13-bit break signal. It is + * important to return the registers configuration to normal for continue 8-bit + * operation. + * There are 3 variants for this API usage: + * 1) SendBreak(3) - function will send the Break signal and take care on the + * configuration returning. Function will block CPU until transmission + * complete. + * 2) User may want to use blocking time if UART configured to the low speed + * operation + * Example for this case: + * SendBreak(0); - initialize Break signal transmission + * Add your code here to use CPU time + * SendBreak(1); - complete Break operation + * 3) Same to 2) but user may want to initialize and use the interrupt to + * complete break operation. + * Example for this case: + * Initialize TX interrupt with "TX - On TX Complete" parameter + * SendBreak(0); - initialize Break signal transmission + * Add your code here to use CPU time + * When interrupt appear with UART_Bridge_TX_STS_COMPLETE status: + * SendBreak(2); - complete Break operation + * + * Side Effects: + * The UART_Bridge_SendBreak() function initializes registers to send a + * break signal. + * Break signal length depends on the break signal bits configuration. + * The register configuration should be reinitialized before normal 8-bit + * communication can continue. + * + *******************************************************************************/ + void UART_Bridge_SendBreak(uint8 retMode) + { + + /* If not Initialized then skip this function*/ + if(UART_Bridge_initVar != 0u) + { + /* Set the Counter to 13-bits and transmit a 00 byte */ + /* When that is done then reset the counter value back */ + uint8 tmpStat; + + #if(UART_Bridge_HD_ENABLED) /* Half Duplex mode*/ + + if( (retMode == UART_Bridge_SEND_BREAK) || + (retMode == UART_Bridge_SEND_WAIT_REINIT ) ) + { + /* CTRL_HD_SEND_BREAK - sends break bits in HD mode */ + UART_Bridge_WriteControlRegister(UART_Bridge_ReadControlRegister() | + UART_Bridge_CTRL_HD_SEND_BREAK); + /* Send zeros */ + UART_Bridge_TXDATA_REG = 0u; + + do /* Wait until transmit starts */ + { + tmpStat = UART_Bridge_TXSTATUS_REG; + } + while((tmpStat & UART_Bridge_TX_STS_FIFO_EMPTY) != 0u); + } + + if( (retMode == UART_Bridge_WAIT_FOR_COMPLETE_REINIT) || + (retMode == UART_Bridge_SEND_WAIT_REINIT) ) + { + do /* Wait until transmit complete */ + { + tmpStat = UART_Bridge_TXSTATUS_REG; + } + while(((uint8)~tmpStat & UART_Bridge_TX_STS_COMPLETE) != 0u); + } + + if( (retMode == UART_Bridge_WAIT_FOR_COMPLETE_REINIT) || + (retMode == UART_Bridge_REINIT) || + (retMode == UART_Bridge_SEND_WAIT_REINIT) ) + { + UART_Bridge_WriteControlRegister(UART_Bridge_ReadControlRegister() & + (uint8)~UART_Bridge_CTRL_HD_SEND_BREAK); + } + + #else /* UART_Bridge_HD_ENABLED Full Duplex mode */ + + static uint8 txPeriod; + + if( (retMode == UART_Bridge_SEND_BREAK) || + (retMode == UART_Bridge_SEND_WAIT_REINIT) ) + { + /* CTRL_HD_SEND_BREAK - skip to send parity bit at Break signal in Full Duplex mode */ + #if( (UART_Bridge_PARITY_TYPE != UART_Bridge__B_UART__NONE_REVB) || \ + (UART_Bridge_PARITY_TYPE_SW != 0u) ) + UART_Bridge_WriteControlRegister(UART_Bridge_ReadControlRegister() | + UART_Bridge_CTRL_HD_SEND_BREAK); + #endif /* End UART_Bridge_PARITY_TYPE != UART_Bridge__B_UART__NONE_REVB */ + + #if(UART_Bridge_TXCLKGEN_DP) + txPeriod = UART_Bridge_TXBITCLKTX_COMPLETE_REG; + UART_Bridge_TXBITCLKTX_COMPLETE_REG = UART_Bridge_TXBITCTR_BREAKBITS; + #else + txPeriod = UART_Bridge_TXBITCTR_PERIOD_REG; + UART_Bridge_TXBITCTR_PERIOD_REG = UART_Bridge_TXBITCTR_BREAKBITS8X; + #endif /* End UART_Bridge_TXCLKGEN_DP */ + + /* Send zeros */ + UART_Bridge_TXDATA_REG = 0u; + + do /* Wait until transmit starts */ + { + tmpStat = UART_Bridge_TXSTATUS_REG; + } + while((tmpStat & UART_Bridge_TX_STS_FIFO_EMPTY) != 0u); + } + + if( (retMode == UART_Bridge_WAIT_FOR_COMPLETE_REINIT) || + (retMode == UART_Bridge_SEND_WAIT_REINIT) ) + { + do /* Wait until transmit complete */ + { + tmpStat = UART_Bridge_TXSTATUS_REG; + } + while(((uint8)~tmpStat & UART_Bridge_TX_STS_COMPLETE) != 0u); + } + + if( (retMode == UART_Bridge_WAIT_FOR_COMPLETE_REINIT) || + (retMode == UART_Bridge_REINIT) || + (retMode == UART_Bridge_SEND_WAIT_REINIT) ) + { + + #if(UART_Bridge_TXCLKGEN_DP) + UART_Bridge_TXBITCLKTX_COMPLETE_REG = txPeriod; + #else + UART_Bridge_TXBITCTR_PERIOD_REG = txPeriod; + #endif /* End UART_Bridge_TXCLKGEN_DP */ + + #if( (UART_Bridge_PARITY_TYPE != UART_Bridge__B_UART__NONE_REVB) || \ + (UART_Bridge_PARITY_TYPE_SW != 0u) ) + UART_Bridge_WriteControlRegister(UART_Bridge_ReadControlRegister() & + (uint8) ~UART_Bridge_CTRL_HD_SEND_BREAK); + #endif /* End UART_Bridge_PARITY_TYPE != NONE */ + } + #endif /* End UART_Bridge_HD_ENABLED */ + } + } + + + /******************************************************************************* + * Function Name: UART_Bridge_SetTxAddressMode + ******************************************************************************** + * + * Summary: + * Configures the transmitter to signal the next bytes is address or data. + * + * Parameters: + * addressMode: + * UART_Bridge_SET_SPACE - Configure the transmitter to send the next + * byte as a data. + * UART_Bridge_SET_MARK - Configure the transmitter to send the next + * byte as an address. + * + * Return: + * None. + * + * Side Effects: + * This function sets and clears UART_Bridge_CTRL_MARK bit in the Control + * register. + * + *******************************************************************************/ + void UART_Bridge_SetTxAddressMode(uint8 addressMode) + { + /* Mark/Space sending enable */ + if(addressMode != 0u) + { + #if( UART_Bridge_CONTROL_REG_REMOVED == 0u ) + UART_Bridge_WriteControlRegister(UART_Bridge_ReadControlRegister() | + UART_Bridge_CTRL_MARK); + #endif /* End UART_Bridge_CONTROL_REG_REMOVED == 0u */ + } + else + { + #if( UART_Bridge_CONTROL_REG_REMOVED == 0u ) + UART_Bridge_WriteControlRegister(UART_Bridge_ReadControlRegister() & + (uint8) ~UART_Bridge_CTRL_MARK); + #endif /* End UART_Bridge_CONTROL_REG_REMOVED == 0u */ + } + } + +#endif /* EndUART_Bridge_TX_ENABLED */ + +#if(UART_Bridge_HD_ENABLED) + + + /******************************************************************************* + * Function Name: UART_Bridge_LoadRxConfig + ******************************************************************************** + * + * Summary: + * Loads the receiver configuration in half duplex mode. After calling this + * function, the UART is ready to receive data. + * + * Parameters: + * None. + * + * Return: + * None. + * + * Side Effects: + * Valid only in half duplex mode. You must make sure that the previous + * transaction is complete and it is safe to unload the transmitter + * configuration. + * + *******************************************************************************/ + void UART_Bridge_LoadRxConfig(void) + { + UART_Bridge_WriteControlRegister(UART_Bridge_ReadControlRegister() & + (uint8)~UART_Bridge_CTRL_HD_SEND); + UART_Bridge_RXBITCTR_PERIOD_REG = UART_Bridge_HD_RXBITCTR_INIT; + + #if (UART_Bridge_RX_INTERRUPT_ENABLED) + /* Enable RX interrupt after set RX configuration */ + UART_Bridge_SetRxInterruptMode(UART_Bridge_INIT_RX_INTERRUPTS_MASK); + #endif /* (UART_Bridge_RX_INTERRUPT_ENABLED) */ + } + + + /******************************************************************************* + * Function Name: UART_Bridge_LoadTxConfig + ******************************************************************************** + * + * Summary: + * Loads the transmitter configuration in half duplex mode. After calling this + * function, the UART is ready to transmit data. + * + * Parameters: + * None. + * + * Return: + * None. + * + * Side Effects: + * Valid only in half duplex mode. You must make sure that the previous + * transaction is complete and it is safe to unload the receiver configuration. + * + *******************************************************************************/ + void UART_Bridge_LoadTxConfig(void) + { + #if (UART_Bridge_RX_INTERRUPT_ENABLED) + /* Disable RX interrupts before set TX configuration */ + UART_Bridge_SetRxInterruptMode(0u); + #endif /* (UART_Bridge_RX_INTERRUPT_ENABLED) */ + + UART_Bridge_WriteControlRegister(UART_Bridge_ReadControlRegister() | UART_Bridge_CTRL_HD_SEND); + UART_Bridge_RXBITCTR_PERIOD_REG = UART_Bridge_HD_TXBITCTR_INIT; + } + +#endif /* UART_Bridge_HD_ENABLED */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/UART_Bridge.h b/source/hic_hal/cypress/psoc5lp/PSoC5/UART_Bridge.h new file mode 100644 index 0000000000..50f743e526 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/UART_Bridge.h @@ -0,0 +1,597 @@ +/******************************************************************************* +* File Name: UART_Bridge.h +* Version 2.50 +* +* Description: +* Contains the function prototypes and constants available to the UART +* user module. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + + +#if !defined(CY_UART_UART_Bridge_H) +#define CY_UART_UART_Bridge_H + +#include "cyfitter.h" +#include "cytypes.h" +#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +#define UART_Bridge_RX_ENABLED (1u) +#define UART_Bridge_TX_ENABLED (1u) +#define UART_Bridge_HD_ENABLED (0u) +#define UART_Bridge_RX_INTERRUPT_ENABLED (1u) +#define UART_Bridge_TX_INTERRUPT_ENABLED (1u) +#define UART_Bridge_INTERNAL_CLOCK_USED (0u) +#define UART_Bridge_RXHW_ADDRESS_ENABLED (0u) +#define UART_Bridge_OVER_SAMPLE_COUNT (8u) +#define UART_Bridge_PARITY_TYPE (0u) +#define UART_Bridge_PARITY_TYPE_SW (0u) +#define UART_Bridge_BREAK_DETECT (0u) +#define UART_Bridge_BREAK_BITS_TX (13u) +#define UART_Bridge_BREAK_BITS_RX (13u) +#define UART_Bridge_TXCLKGEN_DP (1u) +#define UART_Bridge_USE23POLLING (1u) +#define UART_Bridge_FLOW_CONTROL (1u) +#define UART_Bridge_CLK_FREQ (1u) +#define UART_Bridge_TX_BUFFER_SIZE (512u) +#define UART_Bridge_RX_BUFFER_SIZE (512u) + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component UART_v2_50 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + +#if defined(UART_Bridge_BUART_sCR_SyncCtl_CtrlReg__CONTROL_REG) + #define UART_Bridge_CONTROL_REG_REMOVED (0u) +#else + #define UART_Bridge_CONTROL_REG_REMOVED (1u) +#endif /* End UART_Bridge_BUART_sCR_SyncCtl_CtrlReg__CONTROL_REG */ + + +/*************************************** +* Data Structure Definition +***************************************/ + +/* Sleep Mode API Support */ +typedef struct UART_Bridge_backupStruct_ +{ + uint8 enableState; + + #if(UART_Bridge_CONTROL_REG_REMOVED == 0u) + uint8 cr; + #endif /* End UART_Bridge_CONTROL_REG_REMOVED */ + +} UART_Bridge_BACKUP_STRUCT; + + +/*************************************** +* Function Prototypes +***************************************/ + +void UART_Bridge_Start(void) ; +void UART_Bridge_Stop(void) ; +uint8 UART_Bridge_ReadControlRegister(void) ; +void UART_Bridge_WriteControlRegister(uint8 control) ; + +void UART_Bridge_Init(void) ; +void UART_Bridge_Enable(void) ; +void UART_Bridge_SaveConfig(void) ; +void UART_Bridge_RestoreConfig(void) ; +void UART_Bridge_Sleep(void) ; +void UART_Bridge_Wakeup(void) ; + +/* Only if RX is enabled */ +#if( (UART_Bridge_RX_ENABLED) || (UART_Bridge_HD_ENABLED) ) + + #if (UART_Bridge_RX_INTERRUPT_ENABLED) + #define UART_Bridge_EnableRxInt() CyIntEnable (UART_Bridge_RX_VECT_NUM) + #define UART_Bridge_DisableRxInt() CyIntDisable(UART_Bridge_RX_VECT_NUM) + CY_ISR_PROTO(UART_Bridge_RXISR); + #endif /* UART_Bridge_RX_INTERRUPT_ENABLED */ + + void UART_Bridge_SetRxAddressMode(uint8 addressMode) + ; + void UART_Bridge_SetRxAddress1(uint8 address) ; + void UART_Bridge_SetRxAddress2(uint8 address) ; + + void UART_Bridge_SetRxInterruptMode(uint8 intSrc) ; + uint8 UART_Bridge_ReadRxData(void) ; + uint8 UART_Bridge_ReadRxStatus(void) ; + uint8 UART_Bridge_GetChar(void) ; + uint16 UART_Bridge_GetByte(void) ; + uint16 UART_Bridge_GetRxBufferSize(void) + ; + void UART_Bridge_ClearRxBuffer(void) ; + + /* Obsolete functions, defines for backward compatible */ + #define UART_Bridge_GetRxInterruptSource UART_Bridge_ReadRxStatus + +#endif /* End (UART_Bridge_RX_ENABLED) || (UART_Bridge_HD_ENABLED) */ + +/* Only if TX is enabled */ +#if(UART_Bridge_TX_ENABLED || UART_Bridge_HD_ENABLED) + + #if(UART_Bridge_TX_INTERRUPT_ENABLED) + #define UART_Bridge_EnableTxInt() CyIntEnable (UART_Bridge_TX_VECT_NUM) + #define UART_Bridge_DisableTxInt() CyIntDisable(UART_Bridge_TX_VECT_NUM) + #define UART_Bridge_SetPendingTxInt() CyIntSetPending(UART_Bridge_TX_VECT_NUM) + #define UART_Bridge_ClearPendingTxInt() CyIntClearPending(UART_Bridge_TX_VECT_NUM) + CY_ISR_PROTO(UART_Bridge_TXISR); + #endif /* UART_Bridge_TX_INTERRUPT_ENABLED */ + + void UART_Bridge_SetTxInterruptMode(uint8 intSrc) ; + void UART_Bridge_WriteTxData(uint8 txDataByte) ; + uint8 UART_Bridge_ReadTxStatus(void) ; + void UART_Bridge_PutChar(uint8 txDataByte) ; + void UART_Bridge_PutString(const char8 string[]) ; + void UART_Bridge_PutArray(const uint8 string[], uint16 byteCount) + ; + void UART_Bridge_PutCRLF(uint8 txDataByte) ; + void UART_Bridge_ClearTxBuffer(void) ; + void UART_Bridge_SetTxAddressMode(uint8 addressMode) ; + void UART_Bridge_SendBreak(uint8 retMode) ; + uint16 UART_Bridge_GetTxBufferSize(void) + ; + /* Obsolete functions, defines for backward compatible */ + #define UART_Bridge_PutStringConst UART_Bridge_PutString + #define UART_Bridge_PutArrayConst UART_Bridge_PutArray + #define UART_Bridge_GetTxInterruptSource UART_Bridge_ReadTxStatus + +#endif /* End UART_Bridge_TX_ENABLED || UART_Bridge_HD_ENABLED */ + +#if(UART_Bridge_HD_ENABLED) + void UART_Bridge_LoadRxConfig(void) ; + void UART_Bridge_LoadTxConfig(void) ; +#endif /* End UART_Bridge_HD_ENABLED */ + + +/* Communication bootloader APIs */ +#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_UART_Bridge) || \ + (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)) + /* Physical layer functions */ + void UART_Bridge_CyBtldrCommStart(void) CYSMALL ; + void UART_Bridge_CyBtldrCommStop(void) CYSMALL ; + void UART_Bridge_CyBtldrCommReset(void) CYSMALL ; + cystatus UART_Bridge_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 * count, uint8 timeOut) CYSMALL + ; + cystatus UART_Bridge_CyBtldrCommRead(uint8 pData[], uint16 size, uint16 * count, uint8 timeOut) CYSMALL + ; + + #if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_UART_Bridge) + #define CyBtldrCommStart UART_Bridge_CyBtldrCommStart + #define CyBtldrCommStop UART_Bridge_CyBtldrCommStop + #define CyBtldrCommReset UART_Bridge_CyBtldrCommReset + #define CyBtldrCommWrite UART_Bridge_CyBtldrCommWrite + #define CyBtldrCommRead UART_Bridge_CyBtldrCommRead + #endif /* (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_UART_Bridge) */ + + /* Byte to Byte time out for detecting end of block data from host */ + #define UART_Bridge_BYTE2BYTE_TIME_OUT (25u) + #define UART_Bridge_PACKET_EOP (0x17u) /* End of packet defined by bootloader */ + #define UART_Bridge_WAIT_EOP_DELAY (5u) /* Additional 5ms to wait for End of packet */ + #define UART_Bridge_BL_CHK_DELAY_MS (1u) /* Time Out quantity equal 1mS */ + +#endif /* CYDEV_BOOTLOADER_IO_COMP */ + + +/*************************************** +* API Constants +***************************************/ +/* Parameters for SetTxAddressMode API*/ +#define UART_Bridge_SET_SPACE (0x00u) +#define UART_Bridge_SET_MARK (0x01u) + +/* Status Register definitions */ +#if( (UART_Bridge_TX_ENABLED) || (UART_Bridge_HD_ENABLED) ) + #if(UART_Bridge_TX_INTERRUPT_ENABLED) + #define UART_Bridge_TX_VECT_NUM (uint8)UART_Bridge_TXInternalInterrupt__INTC_NUMBER + #define UART_Bridge_TX_PRIOR_NUM (uint8)UART_Bridge_TXInternalInterrupt__INTC_PRIOR_NUM + #endif /* UART_Bridge_TX_INTERRUPT_ENABLED */ + + #define UART_Bridge_TX_STS_COMPLETE_SHIFT (0x00u) + #define UART_Bridge_TX_STS_FIFO_EMPTY_SHIFT (0x01u) + #define UART_Bridge_TX_STS_FIFO_NOT_FULL_SHIFT (0x03u) + #if(UART_Bridge_TX_ENABLED) + #define UART_Bridge_TX_STS_FIFO_FULL_SHIFT (0x02u) + #else /* (UART_Bridge_HD_ENABLED) */ + #define UART_Bridge_TX_STS_FIFO_FULL_SHIFT (0x05u) /* Needs MD=0 */ + #endif /* (UART_Bridge_TX_ENABLED) */ + + #define UART_Bridge_TX_STS_COMPLETE (uint8)(0x01u << UART_Bridge_TX_STS_COMPLETE_SHIFT) + #define UART_Bridge_TX_STS_FIFO_EMPTY (uint8)(0x01u << UART_Bridge_TX_STS_FIFO_EMPTY_SHIFT) + #define UART_Bridge_TX_STS_FIFO_FULL (uint8)(0x01u << UART_Bridge_TX_STS_FIFO_FULL_SHIFT) + #define UART_Bridge_TX_STS_FIFO_NOT_FULL (uint8)(0x01u << UART_Bridge_TX_STS_FIFO_NOT_FULL_SHIFT) +#endif /* End (UART_Bridge_TX_ENABLED) || (UART_Bridge_HD_ENABLED)*/ + +#if( (UART_Bridge_RX_ENABLED) || (UART_Bridge_HD_ENABLED) ) + #if(UART_Bridge_RX_INTERRUPT_ENABLED) + #define UART_Bridge_RX_VECT_NUM (uint8)UART_Bridge_RXInternalInterrupt__INTC_NUMBER + #define UART_Bridge_RX_PRIOR_NUM (uint8)UART_Bridge_RXInternalInterrupt__INTC_PRIOR_NUM + #endif /* UART_Bridge_RX_INTERRUPT_ENABLED */ + #define UART_Bridge_RX_STS_MRKSPC_SHIFT (0x00u) + #define UART_Bridge_RX_STS_BREAK_SHIFT (0x01u) + #define UART_Bridge_RX_STS_PAR_ERROR_SHIFT (0x02u) + #define UART_Bridge_RX_STS_STOP_ERROR_SHIFT (0x03u) + #define UART_Bridge_RX_STS_OVERRUN_SHIFT (0x04u) + #define UART_Bridge_RX_STS_FIFO_NOTEMPTY_SHIFT (0x05u) + #define UART_Bridge_RX_STS_ADDR_MATCH_SHIFT (0x06u) + #define UART_Bridge_RX_STS_SOFT_BUFF_OVER_SHIFT (0x07u) + + #define UART_Bridge_RX_STS_MRKSPC (uint8)(0x01u << UART_Bridge_RX_STS_MRKSPC_SHIFT) + #define UART_Bridge_RX_STS_BREAK (uint8)(0x01u << UART_Bridge_RX_STS_BREAK_SHIFT) + #define UART_Bridge_RX_STS_PAR_ERROR (uint8)(0x01u << UART_Bridge_RX_STS_PAR_ERROR_SHIFT) + #define UART_Bridge_RX_STS_STOP_ERROR (uint8)(0x01u << UART_Bridge_RX_STS_STOP_ERROR_SHIFT) + #define UART_Bridge_RX_STS_OVERRUN (uint8)(0x01u << UART_Bridge_RX_STS_OVERRUN_SHIFT) + #define UART_Bridge_RX_STS_FIFO_NOTEMPTY (uint8)(0x01u << UART_Bridge_RX_STS_FIFO_NOTEMPTY_SHIFT) + #define UART_Bridge_RX_STS_ADDR_MATCH (uint8)(0x01u << UART_Bridge_RX_STS_ADDR_MATCH_SHIFT) + #define UART_Bridge_RX_STS_SOFT_BUFF_OVER (uint8)(0x01u << UART_Bridge_RX_STS_SOFT_BUFF_OVER_SHIFT) + #define UART_Bridge_RX_HW_MASK (0x7Fu) +#endif /* End (UART_Bridge_RX_ENABLED) || (UART_Bridge_HD_ENABLED) */ + +/* Control Register definitions */ +#define UART_Bridge_CTRL_HD_SEND_SHIFT (0x00u) /* 1 enable TX part in Half Duplex mode */ +#define UART_Bridge_CTRL_HD_SEND_BREAK_SHIFT (0x01u) /* 1 send BREAK signal in Half Duplez mode */ +#define UART_Bridge_CTRL_MARK_SHIFT (0x02u) /* 1 sets mark, 0 sets space */ +#define UART_Bridge_CTRL_PARITY_TYPE0_SHIFT (0x03u) /* Defines the type of parity implemented */ +#define UART_Bridge_CTRL_PARITY_TYPE1_SHIFT (0x04u) /* Defines the type of parity implemented */ +#define UART_Bridge_CTRL_RXADDR_MODE0_SHIFT (0x05u) +#define UART_Bridge_CTRL_RXADDR_MODE1_SHIFT (0x06u) +#define UART_Bridge_CTRL_RXADDR_MODE2_SHIFT (0x07u) + +#define UART_Bridge_CTRL_HD_SEND (uint8)(0x01u << UART_Bridge_CTRL_HD_SEND_SHIFT) +#define UART_Bridge_CTRL_HD_SEND_BREAK (uint8)(0x01u << UART_Bridge_CTRL_HD_SEND_BREAK_SHIFT) +#define UART_Bridge_CTRL_MARK (uint8)(0x01u << UART_Bridge_CTRL_MARK_SHIFT) +#define UART_Bridge_CTRL_PARITY_TYPE_MASK (uint8)(0x03u << UART_Bridge_CTRL_PARITY_TYPE0_SHIFT) +#define UART_Bridge_CTRL_RXADDR_MODE_MASK (uint8)(0x07u << UART_Bridge_CTRL_RXADDR_MODE0_SHIFT) + +/* StatusI Register Interrupt Enable Control Bits. As defined by the Register map for the AUX Control Register */ +#define UART_Bridge_INT_ENABLE (0x10u) + +/* Bit Counter (7-bit) Control Register Bit Definitions. As defined by the Register map for the AUX Control Register */ +#define UART_Bridge_CNTR_ENABLE (0x20u) + +/* Constants for SendBreak() "retMode" parameter */ +#define UART_Bridge_SEND_BREAK (0x00u) +#define UART_Bridge_WAIT_FOR_COMPLETE_REINIT (0x01u) +#define UART_Bridge_REINIT (0x02u) +#define UART_Bridge_SEND_WAIT_REINIT (0x03u) + +#define UART_Bridge_OVER_SAMPLE_8 (8u) +#define UART_Bridge_OVER_SAMPLE_16 (16u) + +#define UART_Bridge_BIT_CENTER (UART_Bridge_OVER_SAMPLE_COUNT - 2u) + +#define UART_Bridge_FIFO_LENGTH (4u) +#define UART_Bridge_NUMBER_OF_START_BIT (1u) +#define UART_Bridge_MAX_BYTE_VALUE (0xFFu) + +/* 8X always for count7 implementation */ +#define UART_Bridge_TXBITCTR_BREAKBITS8X ((UART_Bridge_BREAK_BITS_TX * UART_Bridge_OVER_SAMPLE_8) - 1u) +/* 8X or 16X for DP implementation */ +#define UART_Bridge_TXBITCTR_BREAKBITS ((UART_Bridge_BREAK_BITS_TX * UART_Bridge_OVER_SAMPLE_COUNT) - 1u) + +#define UART_Bridge_HALF_BIT_COUNT \ + (((UART_Bridge_OVER_SAMPLE_COUNT / 2u) + (UART_Bridge_USE23POLLING * 1u)) - 2u) +#if (UART_Bridge_OVER_SAMPLE_COUNT == UART_Bridge_OVER_SAMPLE_8) + #define UART_Bridge_HD_TXBITCTR_INIT (((UART_Bridge_BREAK_BITS_TX + \ + UART_Bridge_NUMBER_OF_START_BIT) * UART_Bridge_OVER_SAMPLE_COUNT) - 1u) + + /* This parameter is increased on the 2 in 2 out of 3 mode to sample voting in the middle */ + #define UART_Bridge_RXBITCTR_INIT ((((UART_Bridge_BREAK_BITS_RX + UART_Bridge_NUMBER_OF_START_BIT) \ + * UART_Bridge_OVER_SAMPLE_COUNT) + UART_Bridge_HALF_BIT_COUNT) - 1u) + +#else /* UART_Bridge_OVER_SAMPLE_COUNT == UART_Bridge_OVER_SAMPLE_16 */ + #define UART_Bridge_HD_TXBITCTR_INIT ((8u * UART_Bridge_OVER_SAMPLE_COUNT) - 1u) + /* 7bit counter need one more bit for OverSampleCount = 16 */ + #define UART_Bridge_RXBITCTR_INIT (((7u * UART_Bridge_OVER_SAMPLE_COUNT) - 1u) + \ + UART_Bridge_HALF_BIT_COUNT) +#endif /* End UART_Bridge_OVER_SAMPLE_COUNT */ + +#define UART_Bridge_HD_RXBITCTR_INIT UART_Bridge_RXBITCTR_INIT + + +/*************************************** +* Global variables external identifier +***************************************/ + +extern uint8 UART_Bridge_initVar; +#if (UART_Bridge_TX_INTERRUPT_ENABLED && UART_Bridge_TX_ENABLED) + extern volatile uint8 UART_Bridge_txBuffer[UART_Bridge_TX_BUFFER_SIZE]; + extern volatile uint16 UART_Bridge_txBufferRead; + extern uint16 UART_Bridge_txBufferWrite; +#endif /* (UART_Bridge_TX_INTERRUPT_ENABLED && UART_Bridge_TX_ENABLED) */ +#if (UART_Bridge_RX_INTERRUPT_ENABLED && (UART_Bridge_RX_ENABLED || UART_Bridge_HD_ENABLED)) + extern uint8 UART_Bridge_errorStatus; + extern volatile uint8 UART_Bridge_rxBuffer[UART_Bridge_RX_BUFFER_SIZE]; + extern volatile uint16 UART_Bridge_rxBufferRead; + extern volatile uint16 UART_Bridge_rxBufferWrite; + extern volatile uint8 UART_Bridge_rxBufferLoopDetect; + extern volatile uint8 UART_Bridge_rxBufferOverflow; + #if (UART_Bridge_RXHW_ADDRESS_ENABLED) + extern volatile uint8 UART_Bridge_rxAddressMode; + extern volatile uint8 UART_Bridge_rxAddressDetected; + #endif /* (UART_Bridge_RXHW_ADDRESS_ENABLED) */ +#endif /* (UART_Bridge_RX_INTERRUPT_ENABLED && (UART_Bridge_RX_ENABLED || UART_Bridge_HD_ENABLED)) */ + + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +#define UART_Bridge__B_UART__AM_SW_BYTE_BYTE 1 +#define UART_Bridge__B_UART__AM_SW_DETECT_TO_BUFFER 2 +#define UART_Bridge__B_UART__AM_HW_BYTE_BY_BYTE 3 +#define UART_Bridge__B_UART__AM_HW_DETECT_TO_BUFFER 4 +#define UART_Bridge__B_UART__AM_NONE 0 + +#define UART_Bridge__B_UART__NONE_REVB 0 +#define UART_Bridge__B_UART__EVEN_REVB 1 +#define UART_Bridge__B_UART__ODD_REVB 2 +#define UART_Bridge__B_UART__MARK_SPACE_REVB 3 + + + +/*************************************** +* Initial Parameter Constants +***************************************/ + +/* UART shifts max 8 bits, Mark/Space functionality working if 9 selected */ +#define UART_Bridge_NUMBER_OF_DATA_BITS ((8u > 8u) ? 8u : 8u) +#define UART_Bridge_NUMBER_OF_STOP_BITS (1u) + +#if (UART_Bridge_RXHW_ADDRESS_ENABLED) + #define UART_Bridge_RX_ADDRESS_MODE (0u) + #define UART_Bridge_RX_HW_ADDRESS1 (0u) + #define UART_Bridge_RX_HW_ADDRESS2 (0u) +#endif /* (UART_Bridge_RXHW_ADDRESS_ENABLED) */ + +#define UART_Bridge_INIT_RX_INTERRUPTS_MASK \ + (uint8)((1 << UART_Bridge_RX_STS_FIFO_NOTEMPTY_SHIFT) \ + | (0 << UART_Bridge_RX_STS_MRKSPC_SHIFT) \ + | (0 << UART_Bridge_RX_STS_ADDR_MATCH_SHIFT) \ + | (0 << UART_Bridge_RX_STS_PAR_ERROR_SHIFT) \ + | (0 << UART_Bridge_RX_STS_STOP_ERROR_SHIFT) \ + | (0 << UART_Bridge_RX_STS_BREAK_SHIFT) \ + | (0 << UART_Bridge_RX_STS_OVERRUN_SHIFT)) + +#define UART_Bridge_INIT_TX_INTERRUPTS_MASK \ + (uint8)((0 << UART_Bridge_TX_STS_COMPLETE_SHIFT) \ + | (1 << UART_Bridge_TX_STS_FIFO_EMPTY_SHIFT) \ + | (0 << UART_Bridge_TX_STS_FIFO_FULL_SHIFT) \ + | (0 << UART_Bridge_TX_STS_FIFO_NOT_FULL_SHIFT)) + + +/*************************************** +* Registers +***************************************/ + +#ifdef UART_Bridge_BUART_sCR_SyncCtl_CtrlReg__CONTROL_REG + #define UART_Bridge_CONTROL_REG \ + (* (reg8 *) UART_Bridge_BUART_sCR_SyncCtl_CtrlReg__CONTROL_REG ) + #define UART_Bridge_CONTROL_PTR \ + ( (reg8 *) UART_Bridge_BUART_sCR_SyncCtl_CtrlReg__CONTROL_REG ) +#endif /* End UART_Bridge_BUART_sCR_SyncCtl_CtrlReg__CONTROL_REG */ + +#if(UART_Bridge_TX_ENABLED) + #define UART_Bridge_TXDATA_REG (* (reg8 *) UART_Bridge_BUART_sTX_TxShifter_u0__F0_REG) + #define UART_Bridge_TXDATA_PTR ( (reg8 *) UART_Bridge_BUART_sTX_TxShifter_u0__F0_REG) + #define UART_Bridge_TXDATA_AUX_CTL_REG (* (reg8 *) UART_Bridge_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG) + #define UART_Bridge_TXDATA_AUX_CTL_PTR ( (reg8 *) UART_Bridge_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG) + #define UART_Bridge_TXSTATUS_REG (* (reg8 *) UART_Bridge_BUART_sTX_TxSts__STATUS_REG) + #define UART_Bridge_TXSTATUS_PTR ( (reg8 *) UART_Bridge_BUART_sTX_TxSts__STATUS_REG) + #define UART_Bridge_TXSTATUS_MASK_REG (* (reg8 *) UART_Bridge_BUART_sTX_TxSts__MASK_REG) + #define UART_Bridge_TXSTATUS_MASK_PTR ( (reg8 *) UART_Bridge_BUART_sTX_TxSts__MASK_REG) + #define UART_Bridge_TXSTATUS_ACTL_REG (* (reg8 *) UART_Bridge_BUART_sTX_TxSts__STATUS_AUX_CTL_REG) + #define UART_Bridge_TXSTATUS_ACTL_PTR ( (reg8 *) UART_Bridge_BUART_sTX_TxSts__STATUS_AUX_CTL_REG) + + /* DP clock */ + #if(UART_Bridge_TXCLKGEN_DP) + #define UART_Bridge_TXBITCLKGEN_CTR_REG \ + (* (reg8 *) UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG) + #define UART_Bridge_TXBITCLKGEN_CTR_PTR \ + ( (reg8 *) UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG) + #define UART_Bridge_TXBITCLKTX_COMPLETE_REG \ + (* (reg8 *) UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG) + #define UART_Bridge_TXBITCLKTX_COMPLETE_PTR \ + ( (reg8 *) UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG) + #else /* Count7 clock*/ + #define UART_Bridge_TXBITCTR_PERIOD_REG \ + (* (reg8 *) UART_Bridge_BUART_sTX_sCLOCK_TxBitCounter__PERIOD_REG) + #define UART_Bridge_TXBITCTR_PERIOD_PTR \ + ( (reg8 *) UART_Bridge_BUART_sTX_sCLOCK_TxBitCounter__PERIOD_REG) + #define UART_Bridge_TXBITCTR_CONTROL_REG \ + (* (reg8 *) UART_Bridge_BUART_sTX_sCLOCK_TxBitCounter__CONTROL_AUX_CTL_REG) + #define UART_Bridge_TXBITCTR_CONTROL_PTR \ + ( (reg8 *) UART_Bridge_BUART_sTX_sCLOCK_TxBitCounter__CONTROL_AUX_CTL_REG) + #define UART_Bridge_TXBITCTR_COUNTER_REG \ + (* (reg8 *) UART_Bridge_BUART_sTX_sCLOCK_TxBitCounter__COUNT_REG) + #define UART_Bridge_TXBITCTR_COUNTER_PTR \ + ( (reg8 *) UART_Bridge_BUART_sTX_sCLOCK_TxBitCounter__COUNT_REG) + #endif /* UART_Bridge_TXCLKGEN_DP */ + +#endif /* End UART_Bridge_TX_ENABLED */ + +#if(UART_Bridge_HD_ENABLED) + + #define UART_Bridge_TXDATA_REG (* (reg8 *) UART_Bridge_BUART_sRX_RxShifter_u0__F1_REG ) + #define UART_Bridge_TXDATA_PTR ( (reg8 *) UART_Bridge_BUART_sRX_RxShifter_u0__F1_REG ) + #define UART_Bridge_TXDATA_AUX_CTL_REG (* (reg8 *) UART_Bridge_BUART_sRX_RxShifter_u0__DP_AUX_CTL_REG) + #define UART_Bridge_TXDATA_AUX_CTL_PTR ( (reg8 *) UART_Bridge_BUART_sRX_RxShifter_u0__DP_AUX_CTL_REG) + + #define UART_Bridge_TXSTATUS_REG (* (reg8 *) UART_Bridge_BUART_sRX_RxSts__STATUS_REG ) + #define UART_Bridge_TXSTATUS_PTR ( (reg8 *) UART_Bridge_BUART_sRX_RxSts__STATUS_REG ) + #define UART_Bridge_TXSTATUS_MASK_REG (* (reg8 *) UART_Bridge_BUART_sRX_RxSts__MASK_REG ) + #define UART_Bridge_TXSTATUS_MASK_PTR ( (reg8 *) UART_Bridge_BUART_sRX_RxSts__MASK_REG ) + #define UART_Bridge_TXSTATUS_ACTL_REG (* (reg8 *) UART_Bridge_BUART_sRX_RxSts__STATUS_AUX_CTL_REG ) + #define UART_Bridge_TXSTATUS_ACTL_PTR ( (reg8 *) UART_Bridge_BUART_sRX_RxSts__STATUS_AUX_CTL_REG ) +#endif /* End UART_Bridge_HD_ENABLED */ + +#if( (UART_Bridge_RX_ENABLED) || (UART_Bridge_HD_ENABLED) ) + #define UART_Bridge_RXDATA_REG (* (reg8 *) UART_Bridge_BUART_sRX_RxShifter_u0__F0_REG ) + #define UART_Bridge_RXDATA_PTR ( (reg8 *) UART_Bridge_BUART_sRX_RxShifter_u0__F0_REG ) + #define UART_Bridge_RXADDRESS1_REG (* (reg8 *) UART_Bridge_BUART_sRX_RxShifter_u0__D0_REG ) + #define UART_Bridge_RXADDRESS1_PTR ( (reg8 *) UART_Bridge_BUART_sRX_RxShifter_u0__D0_REG ) + #define UART_Bridge_RXADDRESS2_REG (* (reg8 *) UART_Bridge_BUART_sRX_RxShifter_u0__D1_REG ) + #define UART_Bridge_RXADDRESS2_PTR ( (reg8 *) UART_Bridge_BUART_sRX_RxShifter_u0__D1_REG ) + #define UART_Bridge_RXDATA_AUX_CTL_REG (* (reg8 *) UART_Bridge_BUART_sRX_RxShifter_u0__DP_AUX_CTL_REG) + + #define UART_Bridge_RXBITCTR_PERIOD_REG (* (reg8 *) UART_Bridge_BUART_sRX_RxBitCounter__PERIOD_REG ) + #define UART_Bridge_RXBITCTR_PERIOD_PTR ( (reg8 *) UART_Bridge_BUART_sRX_RxBitCounter__PERIOD_REG ) + #define UART_Bridge_RXBITCTR_CONTROL_REG \ + (* (reg8 *) UART_Bridge_BUART_sRX_RxBitCounter__CONTROL_AUX_CTL_REG ) + #define UART_Bridge_RXBITCTR_CONTROL_PTR \ + ( (reg8 *) UART_Bridge_BUART_sRX_RxBitCounter__CONTROL_AUX_CTL_REG ) + #define UART_Bridge_RXBITCTR_COUNTER_REG (* (reg8 *) UART_Bridge_BUART_sRX_RxBitCounter__COUNT_REG ) + #define UART_Bridge_RXBITCTR_COUNTER_PTR ( (reg8 *) UART_Bridge_BUART_sRX_RxBitCounter__COUNT_REG ) + + #define UART_Bridge_RXSTATUS_REG (* (reg8 *) UART_Bridge_BUART_sRX_RxSts__STATUS_REG ) + #define UART_Bridge_RXSTATUS_PTR ( (reg8 *) UART_Bridge_BUART_sRX_RxSts__STATUS_REG ) + #define UART_Bridge_RXSTATUS_MASK_REG (* (reg8 *) UART_Bridge_BUART_sRX_RxSts__MASK_REG ) + #define UART_Bridge_RXSTATUS_MASK_PTR ( (reg8 *) UART_Bridge_BUART_sRX_RxSts__MASK_REG ) + #define UART_Bridge_RXSTATUS_ACTL_REG (* (reg8 *) UART_Bridge_BUART_sRX_RxSts__STATUS_AUX_CTL_REG ) + #define UART_Bridge_RXSTATUS_ACTL_PTR ( (reg8 *) UART_Bridge_BUART_sRX_RxSts__STATUS_AUX_CTL_REG ) +#endif /* End (UART_Bridge_RX_ENABLED) || (UART_Bridge_HD_ENABLED) */ + +#if(UART_Bridge_INTERNAL_CLOCK_USED) + /* Register to enable or disable the digital clocks */ + #define UART_Bridge_INTCLOCK_CLKEN_REG (* (reg8 *) UART_Bridge_IntClock__PM_ACT_CFG) + #define UART_Bridge_INTCLOCK_CLKEN_PTR ( (reg8 *) UART_Bridge_IntClock__PM_ACT_CFG) + + /* Clock mask for this clock. */ + #define UART_Bridge_INTCLOCK_CLKEN_MASK UART_Bridge_IntClock__PM_ACT_MSK +#endif /* End UART_Bridge_INTERNAL_CLOCK_USED */ + + +/*************************************** +* Register Constants +***************************************/ + +#if(UART_Bridge_TX_ENABLED) + #define UART_Bridge_TX_FIFO_CLR (0x01u) /* FIFO0 CLR */ +#endif /* End UART_Bridge_TX_ENABLED */ + +#if(UART_Bridge_HD_ENABLED) + #define UART_Bridge_TX_FIFO_CLR (0x02u) /* FIFO1 CLR */ +#endif /* End UART_Bridge_HD_ENABLED */ + +#if( (UART_Bridge_RX_ENABLED) || (UART_Bridge_HD_ENABLED) ) + #define UART_Bridge_RX_FIFO_CLR (0x01u) /* FIFO0 CLR */ +#endif /* End (UART_Bridge_RX_ENABLED) || (UART_Bridge_HD_ENABLED) */ + + +/*************************************** +* The following code is DEPRECATED and +* should not be used in new projects. +***************************************/ + +/* UART v2_40 obsolete definitions */ +#define UART_Bridge_WAIT_1_MS UART_Bridge_BL_CHK_DELAY_MS + +#define UART_Bridge_TXBUFFERSIZE UART_Bridge_TX_BUFFER_SIZE +#define UART_Bridge_RXBUFFERSIZE UART_Bridge_RX_BUFFER_SIZE + +#if (UART_Bridge_RXHW_ADDRESS_ENABLED) + #define UART_Bridge_RXADDRESSMODE UART_Bridge_RX_ADDRESS_MODE + #define UART_Bridge_RXHWADDRESS1 UART_Bridge_RX_HW_ADDRESS1 + #define UART_Bridge_RXHWADDRESS2 UART_Bridge_RX_HW_ADDRESS2 + /* Backward compatible define */ + #define UART_Bridge_RXAddressMode UART_Bridge_RXADDRESSMODE +#endif /* (UART_Bridge_RXHW_ADDRESS_ENABLED) */ + +/* UART v2_30 obsolete definitions */ +#define UART_Bridge_initvar UART_Bridge_initVar + +#define UART_Bridge_RX_Enabled UART_Bridge_RX_ENABLED +#define UART_Bridge_TX_Enabled UART_Bridge_TX_ENABLED +#define UART_Bridge_HD_Enabled UART_Bridge_HD_ENABLED +#define UART_Bridge_RX_IntInterruptEnabled UART_Bridge_RX_INTERRUPT_ENABLED +#define UART_Bridge_TX_IntInterruptEnabled UART_Bridge_TX_INTERRUPT_ENABLED +#define UART_Bridge_InternalClockUsed UART_Bridge_INTERNAL_CLOCK_USED +#define UART_Bridge_RXHW_Address_Enabled UART_Bridge_RXHW_ADDRESS_ENABLED +#define UART_Bridge_OverSampleCount UART_Bridge_OVER_SAMPLE_COUNT +#define UART_Bridge_ParityType UART_Bridge_PARITY_TYPE + +#if( UART_Bridge_TX_ENABLED && (UART_Bridge_TXBUFFERSIZE > UART_Bridge_FIFO_LENGTH)) + #define UART_Bridge_TXBUFFER UART_Bridge_txBuffer + #define UART_Bridge_TXBUFFERREAD UART_Bridge_txBufferRead + #define UART_Bridge_TXBUFFERWRITE UART_Bridge_txBufferWrite +#endif /* End UART_Bridge_TX_ENABLED */ +#if( ( UART_Bridge_RX_ENABLED || UART_Bridge_HD_ENABLED ) && \ + (UART_Bridge_RXBUFFERSIZE > UART_Bridge_FIFO_LENGTH) ) + #define UART_Bridge_RXBUFFER UART_Bridge_rxBuffer + #define UART_Bridge_RXBUFFERREAD UART_Bridge_rxBufferRead + #define UART_Bridge_RXBUFFERWRITE UART_Bridge_rxBufferWrite + #define UART_Bridge_RXBUFFERLOOPDETECT UART_Bridge_rxBufferLoopDetect + #define UART_Bridge_RXBUFFER_OVERFLOW UART_Bridge_rxBufferOverflow +#endif /* End UART_Bridge_RX_ENABLED */ + +#ifdef UART_Bridge_BUART_sCR_SyncCtl_CtrlReg__CONTROL_REG + #define UART_Bridge_CONTROL UART_Bridge_CONTROL_REG +#endif /* End UART_Bridge_BUART_sCR_SyncCtl_CtrlReg__CONTROL_REG */ + +#if(UART_Bridge_TX_ENABLED) + #define UART_Bridge_TXDATA UART_Bridge_TXDATA_REG + #define UART_Bridge_TXSTATUS UART_Bridge_TXSTATUS_REG + #define UART_Bridge_TXSTATUS_MASK UART_Bridge_TXSTATUS_MASK_REG + #define UART_Bridge_TXSTATUS_ACTL UART_Bridge_TXSTATUS_ACTL_REG + /* DP clock */ + #if(UART_Bridge_TXCLKGEN_DP) + #define UART_Bridge_TXBITCLKGEN_CTR UART_Bridge_TXBITCLKGEN_CTR_REG + #define UART_Bridge_TXBITCLKTX_COMPLETE UART_Bridge_TXBITCLKTX_COMPLETE_REG + #else /* Count7 clock*/ + #define UART_Bridge_TXBITCTR_PERIOD UART_Bridge_TXBITCTR_PERIOD_REG + #define UART_Bridge_TXBITCTR_CONTROL UART_Bridge_TXBITCTR_CONTROL_REG + #define UART_Bridge_TXBITCTR_COUNTER UART_Bridge_TXBITCTR_COUNTER_REG + #endif /* UART_Bridge_TXCLKGEN_DP */ +#endif /* End UART_Bridge_TX_ENABLED */ + +#if(UART_Bridge_HD_ENABLED) + #define UART_Bridge_TXDATA UART_Bridge_TXDATA_REG + #define UART_Bridge_TXSTATUS UART_Bridge_TXSTATUS_REG + #define UART_Bridge_TXSTATUS_MASK UART_Bridge_TXSTATUS_MASK_REG + #define UART_Bridge_TXSTATUS_ACTL UART_Bridge_TXSTATUS_ACTL_REG +#endif /* End UART_Bridge_HD_ENABLED */ + +#if( (UART_Bridge_RX_ENABLED) || (UART_Bridge_HD_ENABLED) ) + #define UART_Bridge_RXDATA UART_Bridge_RXDATA_REG + #define UART_Bridge_RXADDRESS1 UART_Bridge_RXADDRESS1_REG + #define UART_Bridge_RXADDRESS2 UART_Bridge_RXADDRESS2_REG + #define UART_Bridge_RXBITCTR_PERIOD UART_Bridge_RXBITCTR_PERIOD_REG + #define UART_Bridge_RXBITCTR_CONTROL UART_Bridge_RXBITCTR_CONTROL_REG + #define UART_Bridge_RXBITCTR_COUNTER UART_Bridge_RXBITCTR_COUNTER_REG + #define UART_Bridge_RXSTATUS UART_Bridge_RXSTATUS_REG + #define UART_Bridge_RXSTATUS_MASK UART_Bridge_RXSTATUS_MASK_REG + #define UART_Bridge_RXSTATUS_ACTL UART_Bridge_RXSTATUS_ACTL_REG +#endif /* End (UART_Bridge_RX_ENABLED) || (UART_Bridge_HD_ENABLED) */ + +#if(UART_Bridge_INTERNAL_CLOCK_USED) + #define UART_Bridge_INTCLOCK_CLKEN UART_Bridge_INTCLOCK_CLKEN_REG +#endif /* End UART_Bridge_INTERNAL_CLOCK_USED */ + +#define UART_Bridge_WAIT_FOR_COMLETE_REINIT UART_Bridge_WAIT_FOR_COMPLETE_REINIT + +#endif /* CY_UART_UART_Bridge_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/UART_Bridge_INT.c b/source/hic_hal/cypress/psoc5lp/PSoC5/UART_Bridge_INT.c new file mode 100644 index 0000000000..932f19048c --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/UART_Bridge_INT.c @@ -0,0 +1,277 @@ +/******************************************************************************* +* File Name: UART_BridgeINT.c +* Version 2.50 +* +* Description: +* This file provides all Interrupt Service functionality of the UART component +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "UART_Bridge.h" + + + +/*************************************** +* Custom Declarations +***************************************/ +/* `#START CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + +#if (UART_Bridge_RX_INTERRUPT_ENABLED && (UART_Bridge_RX_ENABLED || UART_Bridge_HD_ENABLED)) + /******************************************************************************* + * Function Name: UART_Bridge_RXISR + ******************************************************************************** + * + * Summary: + * Interrupt Service Routine for RX portion of the UART + * + * Parameters: + * None. + * + * Return: + * None. + * + * Global Variables: + * UART_Bridge_rxBuffer - RAM buffer pointer for save received data. + * UART_Bridge_rxBufferWrite - cyclic index for write to rxBuffer, + * increments after each byte saved to buffer. + * UART_Bridge_rxBufferRead - cyclic index for read from rxBuffer, + * checked to detect overflow condition. + * UART_Bridge_rxBufferOverflow - software overflow flag. Set to one + * when UART_Bridge_rxBufferWrite index overtakes + * UART_Bridge_rxBufferRead index. + * UART_Bridge_rxBufferLoopDetect - additional variable to detect overflow. + * Set to one when UART_Bridge_rxBufferWrite is equal to + * UART_Bridge_rxBufferRead + * UART_Bridge_rxAddressMode - this variable contains the Address mode, + * selected in customizer or set by UART_SetRxAddressMode() API. + * UART_Bridge_rxAddressDetected - set to 1 when correct address received, + * and analysed to store following addressed data bytes to the buffer. + * When not correct address received, set to 0 to skip following data bytes. + * + *******************************************************************************/ + CY_ISR(UART_Bridge_RXISR) + { + uint8 readData; + uint8 readStatus; + uint8 increment_pointer = 0u; + + #if(CY_PSOC3) + uint8 int_en; + #endif /* (CY_PSOC3) */ + + #ifdef UART_Bridge_RXISR_ENTRY_CALLBACK + UART_Bridge_RXISR_EntryCallback(); + #endif /* UART_Bridge_RXISR_ENTRY_CALLBACK */ + + /* User code required at start of ISR */ + /* `#START UART_Bridge_RXISR_START` */ + + /* `#END` */ + + #if(CY_PSOC3) /* Make sure nested interrupt is enabled */ + int_en = EA; + CyGlobalIntEnable; + #endif /* (CY_PSOC3) */ + + do + { + /* Read receiver status register */ + readStatus = UART_Bridge_RXSTATUS_REG; + /* Copy the same status to readData variable for backward compatibility support + * of the user code in UART_Bridge_RXISR_ERROR` section. + */ + readData = readStatus; + + if((readStatus & (UART_Bridge_RX_STS_BREAK | + UART_Bridge_RX_STS_PAR_ERROR | + UART_Bridge_RX_STS_STOP_ERROR | + UART_Bridge_RX_STS_OVERRUN)) != 0u) + { + /* ERROR handling. */ + UART_Bridge_errorStatus |= readStatus & ( UART_Bridge_RX_STS_BREAK | + UART_Bridge_RX_STS_PAR_ERROR | + UART_Bridge_RX_STS_STOP_ERROR | + UART_Bridge_RX_STS_OVERRUN); + /* `#START UART_Bridge_RXISR_ERROR` */ + + /* `#END` */ + + #ifdef UART_Bridge_RXISR_ERROR_CALLBACK + UART_Bridge_RXISR_ERROR_Callback(); + #endif /* UART_Bridge_RXISR_ERROR_CALLBACK */ + } + + if((readStatus & UART_Bridge_RX_STS_FIFO_NOTEMPTY) != 0u) + { + /* Read data from the RX data register */ + readData = UART_Bridge_RXDATA_REG; + #if (UART_Bridge_RXHW_ADDRESS_ENABLED) + if(UART_Bridge_rxAddressMode == (uint8)UART_Bridge__B_UART__AM_SW_DETECT_TO_BUFFER) + { + if((readStatus & UART_Bridge_RX_STS_MRKSPC) != 0u) + { + if ((readStatus & UART_Bridge_RX_STS_ADDR_MATCH) != 0u) + { + UART_Bridge_rxAddressDetected = 1u; + } + else + { + UART_Bridge_rxAddressDetected = 0u; + } + } + if(UART_Bridge_rxAddressDetected != 0u) + { /* Store only addressed data */ + UART_Bridge_rxBuffer[UART_Bridge_rxBufferWrite] = readData; + increment_pointer = 1u; + } + } + else /* Without software addressing */ + { + UART_Bridge_rxBuffer[UART_Bridge_rxBufferWrite] = readData; + increment_pointer = 1u; + } + #else /* Without addressing */ + UART_Bridge_rxBuffer[UART_Bridge_rxBufferWrite] = readData; + increment_pointer = 1u; + #endif /* (UART_Bridge_RXHW_ADDRESS_ENABLED) */ + + /* Do not increment buffer pointer when skip not addressed data */ + if(increment_pointer != 0u) + { + if(UART_Bridge_rxBufferLoopDetect != 0u) + { /* Set Software Buffer status Overflow */ + UART_Bridge_rxBufferOverflow = 1u; + } + /* Set next pointer. */ + UART_Bridge_rxBufferWrite++; + + /* Check pointer for a loop condition */ + if(UART_Bridge_rxBufferWrite >= UART_Bridge_RX_BUFFER_SIZE) + { + UART_Bridge_rxBufferWrite = 0u; + } + + /* Detect pre-overload condition and set flag */ + if(UART_Bridge_rxBufferWrite == UART_Bridge_rxBufferRead) + { + UART_Bridge_rxBufferLoopDetect = 1u; + /* When Hardware Flow Control selected */ + #if (UART_Bridge_FLOW_CONTROL != 0u) + /* Disable RX interrupt mask, it is enabled when user read data from the buffer using APIs */ + UART_Bridge_RXSTATUS_MASK_REG &= (uint8)~UART_Bridge_RX_STS_FIFO_NOTEMPTY; + CyIntClearPending(UART_Bridge_RX_VECT_NUM); + break; /* Break the reading of the FIFO loop, leave the data there for generating RTS signal */ + #endif /* (UART_Bridge_FLOW_CONTROL != 0u) */ + } + } + } + }while((readStatus & UART_Bridge_RX_STS_FIFO_NOTEMPTY) != 0u); + + /* User code required at end of ISR (Optional) */ + /* `#START UART_Bridge_RXISR_END` */ + + /* `#END` */ + + #ifdef UART_Bridge_RXISR_EXIT_CALLBACK + UART_Bridge_RXISR_ExitCallback(); + #endif /* UART_Bridge_RXISR_EXIT_CALLBACK */ + + #if(CY_PSOC3) + EA = int_en; + #endif /* (CY_PSOC3) */ + } + +#endif /* (UART_Bridge_RX_INTERRUPT_ENABLED && (UART_Bridge_RX_ENABLED || UART_Bridge_HD_ENABLED)) */ + + +#if (UART_Bridge_TX_INTERRUPT_ENABLED && UART_Bridge_TX_ENABLED) + /******************************************************************************* + * Function Name: UART_Bridge_TXISR + ******************************************************************************** + * + * Summary: + * Interrupt Service Routine for the TX portion of the UART + * + * Parameters: + * None. + * + * Return: + * None. + * + * Global Variables: + * UART_Bridge_txBuffer - RAM buffer pointer for transmit data from. + * UART_Bridge_txBufferRead - cyclic index for read and transmit data + * from txBuffer, increments after each transmitted byte. + * UART_Bridge_rxBufferWrite - cyclic index for write to txBuffer, + * checked to detect available for transmission bytes. + * + *******************************************************************************/ + CY_ISR(UART_Bridge_TXISR) + { + #if(CY_PSOC3) + uint8 int_en; + #endif /* (CY_PSOC3) */ + + #ifdef UART_Bridge_TXISR_ENTRY_CALLBACK + UART_Bridge_TXISR_EntryCallback(); + #endif /* UART_Bridge_TXISR_ENTRY_CALLBACK */ + + /* User code required at start of ISR */ + /* `#START UART_Bridge_TXISR_START` */ + + /* `#END` */ + + #if(CY_PSOC3) /* Make sure nested interrupt is enabled */ + int_en = EA; + CyGlobalIntEnable; + #endif /* (CY_PSOC3) */ + + while((UART_Bridge_txBufferRead != UART_Bridge_txBufferWrite) && + ((UART_Bridge_TXSTATUS_REG & UART_Bridge_TX_STS_FIFO_FULL) == 0u)) + { + /* Check pointer wrap around */ + if(UART_Bridge_txBufferRead >= UART_Bridge_TX_BUFFER_SIZE) + { + UART_Bridge_txBufferRead = 0u; + } + + UART_Bridge_TXDATA_REG = UART_Bridge_txBuffer[UART_Bridge_txBufferRead]; + + /* Set next pointer */ + UART_Bridge_txBufferRead++; + } + + /* User code required at end of ISR (Optional) */ + /* `#START UART_Bridge_TXISR_END` */ + + /* `#END` */ + + #ifdef UART_Bridge_TXISR_EXIT_CALLBACK + UART_Bridge_TXISR_ExitCallback(); + #endif /* UART_Bridge_TXISR_EXIT_CALLBACK */ + + #if(CY_PSOC3) + EA = int_en; + #endif /* (CY_PSOC3) */ + } +#endif /* (UART_Bridge_TX_INTERRUPT_ENABLED && UART_Bridge_TX_ENABLED) */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS.c b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS.c new file mode 100644 index 0000000000..76e9fb70a3 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS.c @@ -0,0 +1,2829 @@ +/***************************************************************************//** +* \file USBFS.c +* \version 3.20 +* +* \brief +* This file contains the global USBFS API functions. +* +* Note: +* Many of the functions use an endpoint number. SRAM arrays are sized with 9 +* elements, so they are indexed directly by epNumber. The SIE and ARB +* registers are indexed by variations of epNumber - 1. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "USBFS_pvt.h" +#include "USBFS_cydmac.h" +#include "USBFS_hid.h" +#include "USBFS_Dp.h" + + +/*************************************** +* Global data allocation +***************************************/ + +/** Indicates whether the USBFS has been initialized. The variable is +* initialized to 0 after device reset and set to 1 the first time USBFS_Start() +* is called. This allows the Component to restart without reinitialization after +* the first call to the USBFS_Start() routine. +* If re-initialization of the Component is required, the variable should be set +* to 0 before the USBFS_Start() routine is called. Alternatively, the USBFS can +* be reinitialized by calling both USBFS_Init() and USBFS_InitComponent() +* functions. +*/ +uint8 USBFS_initVar = 0u; + +#if (USBFS_EP_MANAGEMENT_DMA) + #if (CY_PSOC4) + static void USBFS_InitEpDma(void); + + /* DMA chanels assigend for endpoints. */ + const uint8 USBFS_DmaChan[USBFS_MAX_EP] = + { + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + }; + #else + /* DMA chanels assigend for endpoints. */ + uint8 USBFS_DmaChan[USBFS_MAX_EP]; + + /* DMA TDs require for PSoC 3/5LP operation. */ + uint8 USBFS_DmaTd[USBFS_MAX_EP]; + #endif /* (CY_PSOC4) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) +#if (CY_PSOC4) + /* Number of DMA bursts. */ + uint8 USBFS_DmaEpBurstCnt [USBFS_MAX_EP]; + + /* Number of bytes to transfer in last DMA burst. */ + uint8 USBFS_DmaEpLastBurstEl[USBFS_MAX_EP]; + + /* Storage for arrays above. */ + uint8 USBFS_DmaEpBurstCntBackup [USBFS_MAX_EP]; + uint32 USBFS_DmaEpBufferAddrBackup[USBFS_MAX_EP]; + + /* DMA trigger mux output for usb.dma_req[0-7]. */ + const uint8 USBFS_DmaReqOut[USBFS_MAX_EP] = + { + 0u, + USBFS_ep1_dma__TR_OUTPUT, + USBFS_ep2_dma__TR_OUTPUT, + USBFS_ep3_dma__TR_OUTPUT, + USBFS_ep4_dma__TR_OUTPUT, + USBFS_ep5_dma__TR_OUTPUT, + USBFS_ep6_dma__TR_OUTPUT, + USBFS_ep7_dma__TR_OUTPUT, + 0u, + }; + + /* DMA trigger mux output for usb.dma_burstend[0-7]. */ + const uint8 USBFS_DmaBurstEndOut[USBFS_MAX_EP] = + { + 0u, + USBFS_BURSTEND_0_TR_OUTPUT, + USBFS_BURSTEND_1_TR_OUTPUT, + USBFS_BURSTEND_2_TR_OUTPUT, + USBFS_BURSTEND_3_TR_OUTPUT, + USBFS_BURSTEND_4_TR_OUTPUT, + USBFS_BURSTEND_5_TR_OUTPUT, + USBFS_BURSTEND_6_TR_OUTPUT, + USBFS_BURSTEND_7_TR_OUTPUT + }; + +#else + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT; + uint8 USBFS_DmaNextTd[USBFS_MAX_EP]; + const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] = + { + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + }; + + volatile uint16 USBFS_inLength[USBFS_MAX_EP]; + const uint8 *USBFS_inDataPointer[USBFS_MAX_EP]; + volatile uint8 USBFS_inBufFull[USBFS_MAX_EP]; + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ +#endif /* (CY_PSOC4) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + +/******************************************************************************* +* Function Name: USBFS_Start +****************************************************************************//** +* +* This function performs all required initialization for the USBFS component. +* After this function call, the USB device initiates communication with the +* host by pull-up D+ line. This is the preferred method to begin component +* operation. +* +* Note that global interrupts have to be enabled because interrupts are +* required for USBFS component operation. +* +* PSoC 4200L devices: when USBFS component configured to DMA with Automatic +* Buffer Management, the DMA interrupt priority is changed to the highest +* (priority 0) inside this function. +* +* PSoC 3/PSoC 5LP devices: when USBFS component configured to DMA with +* Automatic Buffer Management, the Arbiter interrupt priority is changed to +* the highest (priority 0) inside this function. +* +* \param device +* Contains the device number of the desired device descriptor. +* The device number can be found in the Device Descriptor Tab of +* "Configure" dialog, under the settings of desired Device Descriptor, +* in the "Device Number" field. +* \param mode: +* The operating voltage. This determines whether the voltage regulator +* is enabled for 5V operation or if pass through mode is used for 3.3V +* operation. Symbolic names and their associated values are given in the +* following list. +* +* *USBFS_3V_OPERATION* - Disable voltage regulator and pass- +* through Vcc for pull-up +* +* *USBFS_5V_OPERATION* - Enable voltage regulator and use +* regulator for pull-up +* +* *USBFS_DWR_POWER_OPERATION* - Enable or disable the voltage +* regulator depending on the power supply +* voltage configuration in the DWR tab. +* For PSoC 3/5LP devices, the VDDD supply +* voltage is considered and for PSoC 4A-L, +* the VBUS supply voltage is considered.* +* \globalvars +* \ref USBFS_initVar +* +* \sideeffect +* This function will reset all communication states to default. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_Start(uint8 device, uint8 mode) +{ + if (0u == USBFS_initVar) + { + USBFS_Init(); + USBFS_initVar = 1u; + } + + USBFS_InitComponent(device, mode); +} + + +/******************************************************************************* +* Function Name: USBFS_Init +****************************************************************************//** +* +* This function initializes or restores the component according to the +* customizer Configure dialog settings. It is not necessary to call +* USBFS_Init() because the USBFS_Start() routine calls +* this function and is the preferred method to begin component operation. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_Init(void) +{ +#if (CY_PSOC4) + /* Enable clock to USB IP. */ + USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_CSR_CLK_EN; + + /* The internal regulator (CR1.REG_ENABLE) is enabled in + * USBFS_InitComponent() if it is required. + */ + + /* Enable USBIO control on drive mode of D+ and D- pins. */ + USBFS_USBIO_CR1_REG &= ~ (uint32) USBFS_USBIO_CR1_IOMODE; + + /* Set number of LF CLK to detect UBS bus reset. */ + USBFS_BUS_RST_CNT_REG = USBFS_DEFUALT_BUS_RST_CNT; + + /* Select VBUS detection source and clear PHY isolate. The application level + * must ensure that VBUS is valid. There is no need to wait 2us before VBUS is valid. + */ + USBFS_POWER_CTRL_REG = USBFS_DEFAULT_POWER_CTRL_VBUS; + + /* Enable PHY detector and single-ended and differential receivers. */ + USBFS_POWER_CTRL_REG |= USBFS_DEFAULT_POWER_CTRL_PHY; + + /* Suspend clear sequence. */ + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND; + CyDelayUs(USBFS_WAIT_SUSPEND_DEL_DISABLE); + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND_DEL; + + /* Sets IMO lock options and clear all other bits. */ + USBFS_CR1_REG = USBFS_DEFUALT_CR1; + + /* Configure level (hi, lo, med) for each interrupt source. */ + USBFS_INTR_LVL_SEL_REG = USBFS_DEFAULT_INTR_LVL_SEL; + + /* Configure interrupt sources from: SOF, Bus Reset and EP0. */ + USBFS_INTR_SIE_MASK_REG = USBFS_DEFAULT_INTR_SIE_MASK; + +#else + uint8 enableInterrupts = CyEnterCriticalSection(); + +#if (USBFS_EP_MANAGEMENT_DMA) + uint16 i; +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + /* Enable USB block. */ + USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB; + /* Enable USB block for Standby Power Mode. */ + USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB; + + /* Enable core clock. */ + USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_ENABLE; + + USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; + + /* ENABLING USBIO PADS IN USB MODE FROM I/O MODE. */ + /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled. */ + USBFS_USBIO_CR0_REG &= (uint8) ~USBFS_USBIO_CR0_TEN; + CyDelayUs(USBFS_WAIT_REG_STABILITY_50NS); /* ~50ns delay. */ + /* Disable USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted. + * high. These bits will be set low by the power manager out-of-reset. + * Also confirm USBIO pull-up is disabled. + */ + USBFS_PM_USB_CR0_REG &= (uint8) ~(USBFS_PM_USB_CR0_PD_N | + USBFS_PM_USB_CR0_PD_PULLUP_N); + + /* Select IOMODE to USB mode. */ + USBFS_USBIO_CR1_REG &= (uint8) ~USBFS_USBIO_CR1_IOMODE; + + /* Enable USBIO reference by setting PM.USB_CR0.fsusbio_ref_en. */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN; + /* Reference is available for 1us after regulator is enabled. */ + CyDelayUs(USBFS_WAIT_REG_STABILITY_1US); + /* OR 40us after power is restored. */ + CyDelayUs(USBFS_WAIT_VREF_RESTORE); + /* Ensure single-ended disable bits are low (PRT15.INP_DIS[7:6])(input receiver enabled). */ + USBFS_DM_INP_DIS_REG &= (uint8) ~USBFS_DM_MASK; + USBFS_DP_INP_DIS_REG &= (uint8) ~USBFS_DP_MASK; + + /* Enable USBIO. */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N; + CyDelayUs(USBFS_WAIT_PD_PULLUP_N_ENABLE); + /* Set USBIO pull-up enable. */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N; + + /* Reset Arbiter Write Address register for endpoint 1. */ + CY_SET_REG8(USBFS_ARB_RW1_WA_PTR, 0u); + CY_SET_REG8(USBFS_ARB_RW1_WA_MSB_PTR, 0u); + +#if (USBFS_EP_MANAGEMENT_DMA) + /* Initialize transfer descriptor. This will be used to detect DMA state - initialized or not. */ + for (i = 0u; i < USBFS_MAX_EP; ++i) + { + USBFS_DmaTd[i] = DMA_INVALID_TD; + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) + USBFS_DmaNextTd[i] = DMA_INVALID_TD; + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + } +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + CyExitCriticalSection(enableInterrupts); +#endif /* (CY_PSOC4) */ + + /* Configure interrupts from USB block. */ +#if (CY_PSOC4) + /* Configure hi_int: set handler and priority. */ + CyIntSetPriority (USBFS_INTR_HI_VECT_NUM, USBFS_INTR_HI_PRIORITY); + (void) CyIntSetVector(USBFS_INTR_HI_VECT_NUM, &USBFS_INTR_HI_ISR); + + /* Configure lo_int: set handler and priority. */ + CyIntSetPriority (USBFS_INTR_LO_VECT_NUM, USBFS_INTR_LO_PRIORITY); + (void) CyIntSetVector(USBFS_INTR_LO_VECT_NUM, &USBFS_INTR_LO_ISR); + + /* Configure med_int: set handler and priority (routed through DSI). */ + CyIntSetPriority (USBFS_INTR_MED_VECT_NUM, USBFS_INTR_MED_PRIORITY); + (void) CyIntSetVector(USBFS_INTR_MED_VECT_NUM, &USBFS_INTR_MED_ISR); + +#else + /* Set bus reset interrupt. */ + CyIntSetPriority(USBFS_BUS_RESET_VECT_NUM, USBFS_BUS_RESET_PRIOR); + (void) CyIntSetVector(USBFS_BUS_RESET_VECT_NUM, &USBFS_BUS_RESET_ISR); + + /* Set Control Endpoint Interrupt. */ + CyIntSetPriority(USBFS_EP_0_VECT_NUM, USBFS_EP_0_PRIOR); + (void) CyIntSetVector(USBFS_EP_0_VECT_NUM, &USBFS_EP_0_ISR); + + /* Set SOF interrupt. */ + #if (USBFS_SOF_ISR_ACTIVE) + CyIntSetPriority (USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR); + (void) CyIntSetVector(USBFS_SOF_VECT_NUM, &USBFS_SOF_ISR); + #endif /* (USBFS_SOF_ISR_ACTIVE) */ + + /* Set Data Endpoint 1 Interrupt. */ + #if (USBFS_EP1_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR); + (void) CyIntSetVector(USBFS_EP_1_VECT_NUM, &USBFS_EP_1_ISR); + #endif /* (USBFS_EP1_ISR_ACTIVE) */ + + /* Set Data Endpoint 2 Interrupt. */ + #if (USBFS_EP2_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR); + (void) CyIntSetVector(USBFS_EP_2_VECT_NUM, &USBFS_EP_2_ISR); + #endif /* (USBFS_EP2_ISR_ACTIVE) */ + + /* Set Data Endpoint 3 Interrupt. */ + #if (USBFS_EP3_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR); + (void) CyIntSetVector(USBFS_EP_3_VECT_NUM, &USBFS_EP_3_ISR); + #endif /* (USBFS_EP3_ISR_ACTIVE) */ + + /* Set Data Endpoint 4 Interrupt. */ + #if (USBFS_EP4_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR); + (void) CyIntSetVector(USBFS_EP_4_VECT_NUM, &USBFS_EP_4_ISR); + #endif /* (USBFS_EP4_ISR_ACTIVE) */ + + /* Set Data Endpoint 5 Interrupt. */ + #if (USBFS_EP5_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR); + (void) CyIntSetVector(USBFS_EP_5_VECT_NUM, &USBFS_EP_5_ISR); + #endif /* (USBFS_EP5_ISR_ACTIVE) */ + + /* Set Data Endpoint 6 Interrupt. */ + #if (USBFS_EP6_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR); + (void) CyIntSetVector(USBFS_EP_6_VECT_NUM, &USBFS_EP_6_ISR); + #endif /* (USBFS_EP6_ISR_ACTIVE) */ + + /* Set Data Endpoint 7 Interrupt. */ + #if (USBFS_EP7_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR); + (void) CyIntSetVector(USBFS_EP_7_VECT_NUM, &USBFS_EP_7_ISR); + #endif /* (USBFS_EP7_ISR_ACTIVE) */ + + /* Set Data Endpoint 8 Interrupt. */ + #if (USBFS_EP8_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR); + (void) CyIntSetVector(USBFS_EP_8_VECT_NUM, &USBFS_EP_8_ISR); + #endif /* (USBFS_EP8_ISR_ACTIVE) */ + + /* Set ARB Interrupt. */ + #if (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) + CyIntSetPriority (USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR); + (void) CyIntSetVector(USBFS_ARB_VECT_NUM, &USBFS_ARB_ISR); + #endif /* (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) */ +#endif /* (CY_PSOC4) */ + + /* Common: Configure GPIO interrupt for wakeup. */ +#if (USBFS_DP_ISR_ACTIVE) + CyIntSetPriority (USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIORITY); + (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR); +#endif /* (USBFS_DP_ISR_ACTIVE) */ + +#if (USBFS_EP_MANAGEMENT_DMA && CY_PSOC4) + /* Initialize DMA channels. */ + USBFS_InitEpDma(); +#endif /* (USBFS_EP_MANAGEMENT_DMA && CY_PSOC4) */ +} + + +/******************************************************************************* +* Function Name: USBFS_InitComponent +****************************************************************************//** +* +* This function initializes the component’s global variables and initiates +* communication with the host by pull-up D+ line. +* +* \param device: +* Contains the device number of the desired device descriptor. The device +* number can be found in the Device Descriptor Tab of "Configure" dialog, +* under the settings of desired Device Descriptor, in the *Device Number* +* field. +* \param mode: +* The operating voltage. This determines whether the voltage regulator +* is enabled for 5V operation or if pass through mode is used for 3.3V +* operation. Symbolic names and their associated values are given in the +* following list. +* +* *USBFS_3V_OPERATION* - Disable voltage regulator and pass- +* through Vcc for pull-up +* +* *USBFS_5V_OPERATION* - Enable voltage regulator and use +* regulator for pull-up +* +* *USBFS_DWR_POWER_OPERATION* - Enable or disable the voltage +* regulator depending on the power supply +* voltage configuration in the DWR tab. +* For PSoC 3/5LP devices, the VDDD supply +* voltage is considered and for PSoC 4A-L, +* the VBUS supply voltage is considered. +* +* \globalvars +* \ref USBFS_device +* \ref USBFS_transferState +* \ref USBFS_configuration +* \ref USBFS_deviceStatus +* +* \ref USBFS_deviceAddress - Contains the current device address. This +* variable is initialized to zero in this API. The Host starts to communicate +* to the device with address 0 and then sets it to a whatever value using a +* SET_ADDRESS request. +* +* \ref USBFS_lastPacketSize - Initialized to 0; +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_InitComponent(uint8 device, uint8 mode) +{ + /* Initialize _hidProtocol variable to comply with + * HID 7.2.6 Set_Protocol Request: + * "When initialized, all devices default to report protocol." + */ +#if defined(USBFS_ENABLE_HID_CLASS) + uint8 i; + + for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) + { + USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; + } +#endif /* USBFS_ENABLE_HID_CLASS */ + + /* Store device number to access descriptor. */ + USBFS_device = device; + + /* Reset component internal variables. */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + USBFS_configurationChanged = 0u; + USBFS_configuration = 0u; + USBFS_interfaceNumber = 0u; + USBFS_deviceAddress = 0u; + USBFS_deviceStatus = 0u; + USBFS_lastPacketSize = 0u; + + /* Enable component interrupts. */ +#if (CY_PSOC4) + CyIntEnable(USBFS_INTR_HI_VECT_NUM); + CyIntEnable(USBFS_INTR_MED_VECT_NUM); + CyIntEnable(USBFS_INTR_LO_VECT_NUM); +#else + CyIntEnable(USBFS_BUS_RESET_VECT_NUM); + CyIntEnable(USBFS_EP_0_VECT_NUM); + + #if (USBFS_SOF_ISR_ACTIVE) + CyIntEnable(USBFS_SOF_VECT_NUM); + #endif /* (USBFS_SOF_ISR_ACTIVE) */ + + #if (USBFS_EP1_ISR_ACTIVE) + CyIntEnable(USBFS_EP_1_VECT_NUM); + #endif /* (USBFS_EP1_ISR_ACTIVE) */ + + #if (USBFS_EP2_ISR_ACTIVE) + CyIntEnable(USBFS_EP_2_VECT_NUM); + #endif /* (USBFS_EP5_ISR_ACTIVE) */ + + #if (USBFS_EP3_ISR_ACTIVE) + CyIntEnable(USBFS_EP_3_VECT_NUM); + #endif /* (USBFS_EP5_ISR_ACTIVE) */ + + #if (USBFS_EP4_ISR_ACTIVE) + CyIntEnable(USBFS_EP_4_VECT_NUM); + #endif /* (USBFS_EP5_ISR_ACTIVE) */ + + #if (USBFS_EP5_ISR_ACTIVE) + CyIntEnable(USBFS_EP_5_VECT_NUM); + #endif /* (USBFS_EP5_ISR_ACTIVE) */ + + #if (USBFS_EP6_ISR_ACTIVE) + CyIntEnable(USBFS_EP_6_VECT_NUM); + #endif /* USBFS_EP6_ISR_REMOVE */ + + #if (USBFS_EP7_ISR_ACTIVE) + CyIntEnable(USBFS_EP_7_VECT_NUM); + #endif /* (USBFS_EP7_ISR_ACTIVE) */ + + #if (USBFS_EP8_ISR_ACTIVE) + CyIntEnable(USBFS_EP_8_VECT_NUM); + #endif /* (USBFS_EP8_ISR_ACTIVE) */ +#endif /* (CY_PSOC4) */ + +#if (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) + /* Enable ARB EP interrupt sources. */ + USBFS_ARB_INT_EN_REG = USBFS_DEFAULT_ARB_INT_EN; + + #if (CY_PSOC3 || CY_PSOC5) + CyIntEnable(USBFS_ARB_VECT_NUM); + #endif /* (CY_PSOC3 || CY_PSOC5) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) */ + +/* Arbiter configuration for DMA transfers. */ +#if (USBFS_EP_MANAGEMENT_DMA) + /* Configure Arbiter for Manual or Auto DMA operation and clear configuration completion. */ + USBFS_ARB_CFG_REG = USBFS_DEFAULT_ARB_CFG; + + #if (CY_PSOC4) + /* Enable DMA operation. */ + CyDmaEnable(); + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Change DMA priority to be highest. */ + CyIntSetPriority(CYDMA_INTR_NUMBER, USBFS_DMA_AUTO_INTR_PRIO); + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + #endif /* (CY_PSOC4) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + #if (CY_PSOC4) + /* Enable DMA interrupt to handle DMA management. */ + CyIntEnable(CYDMA_INTR_NUMBER); + #else + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + /* Initialize interrupts which handle verification of successful DMA transaction. */ + USBFS_EP_DMA_Done_isr_StartEx(&USBFS_EP_DMA_DONE_ISR); + USBFS_EP17_DMA_Done_SR_InterruptEnable(); + USBFS_EP8_DMA_Done_SR_InterruptEnable(); + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ + #endif /* (CY_PSOC4) */ + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + /* Enable USB regulator depends on operation voltage. IMO Locking is enabled in Init(). */ + switch(mode) + { + case USBFS_3V_OPERATION: + /* Disable regulator for 3V operation. */ + USBFS_CR1_REG &= (uint8) ~USBFS_CR1_REG_ENABLE; + break; + + case USBFS_5V_OPERATION: + /* Enable regulator for 5V operation. */ + USBFS_CR1_REG |= (uint8) USBFS_CR1_REG_ENABLE; + break; + + default: /* Check DWR settings of USB power supply. */ + #if (USBFS_VDDD_MV < USBFS_3500MV) + /* Disable regulator for 3V operation. */ + USBFS_CR1_REG &= (uint8) ~USBFS_CR1_REG_ENABLE; + #else + /* Enable regulator for 5V operation. */ + USBFS_CR1_REG |= (uint8) USBFS_CR1_REG_ENABLE; + #endif /* (USBFS_VDDD_MV < USBFS_3500MV) */ + break; + } + +#if (CY_PSOC4) + /* Clear bus activity. */ + USBFS_CR1_REG &= (uint32) ~USBFS_CR1_BUS_ACTIVITY; + + /* Clear EP0 count register. */ + USBFS_EP0_CNT_REG = USBFS_CLEAR_REG; + + /* Set EP0.CR: ACK Setup, NAK IN/OUT. */ + USBFS_EP0_CR_REG = USBFS_MODE_NAK_IN_OUT; + + #if (USBFS_LPM_ACTIVE) + if (NULL != USBFS_GetBOSPtr()) + { + /* Enable LPM and acknowledge LPM packets for active device. + * Reset NYET_EN and SUB_RESP bits in the LPM_CTRL register. + */ + USBFS_LPM_CTRL_REG = (USBFS_LPM_CTRL_LPM_EN | \ + USBFS_LPM_CTRL_LPM_ACK_RESP); + } + else + { + /* Disable LPM for active device. */ + USBFS_LPM_CTRL_REG &= (uint32) ~USBFS_LPM_CTRL_LPM_EN; + } + #endif /* (USBFS_LPM_ACTIVE) */ + + /* Enable device to responds to USB traffic with address 0. */ + USBFS_CR0_REG = USBFS_DEFUALT_CR0; + +#else + /* Set EP0.CR: ACK Setup, STALL IN/OUT. */ + USBFS_EP0_CR_REG = USBFS_MODE_STALL_IN_OUT; + + /* Enable device to respond to USB traffic with address 0. */ + USBFS_CR0_REG = USBFS_DEFUALT_CR0; + CyDelayCycles(USBFS_WAIT_CR0_REG_STABILITY); +#endif /* (CY_PSOC4) */ + + /* Enable D+ pull-up and keep USB control on IO. */ + USBFS_USBIO_CR1_REG = USBFS_USBIO_CR1_USBPUEN; +} + + +/******************************************************************************* +* Function Name: USBFS_ReInitComponent +****************************************************************************//** +* +* This function reinitialize the component configuration and is +* intend to be called from the Reset interrupt. +* +* \globalvars +* USBFS_device - Contains the device number of the desired Device +* Descriptor. The device number can be found in the Device Descriptor tab +* of the Configure dialog, under the settings of the desired Device Descriptor, +* in the Device Number field. +* USBFS_transferState - This variable is used by the communication +* functions to handle the current transfer state. Initialized to +* TRANS_STATE_IDLE in this API. +* USBFS_configuration - Contains the current configuration number +* set by the Host using a SET_CONFIGURATION request. +* Initialized to zero in this API. +* USBFS_deviceAddress - Contains the current device address. This +* variable is initialized to zero in this API. The Host starts to communicate +* to the device with address 0 and then sets it to a whatever value using +* a SET_ADDRESS request. +* USBFS_deviceStatus - Initialized to 0. +* This is a two-bit variable which contains the power status in the first bit +* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and the remote +* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in the second bit. +* USBFS_lastPacketSize - Initialized to 0; +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_ReInitComponent(void) +{ + /* Initialize _hidProtocol variable to comply with HID 7.2.6 Set_Protocol + * Request: "When initialized, all devices default to report protocol." + */ +#if defined(USBFS_ENABLE_HID_CLASS) + uint8 i; + + for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) + { + USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; + } +#endif /* USBFS_ENABLE_HID_CLASS */ + + /* Reset component internal variables. */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + USBFS_configurationChanged = 0u; + USBFS_configuration = 0u; + USBFS_interfaceNumber = 0u; + USBFS_deviceAddress = 0u; + USBFS_deviceStatus = 0u; + USBFS_lastPacketSize = 0u; + +#if (CY_PSOC4) + /* Set EP0.CR: ACK Setup, NAK IN/OUT. */ + USBFS_EP0_CR_REG = USBFS_MODE_NAK_IN_OUT; +#else + /* Set EP0.CR: ACK Setup, STALL IN/OUT. */ + USBFS_EP0_CR_REG = USBFS_MODE_STALL_IN_OUT; +#endif /* (CY_PSOC4) */ + + /* Enable device to respond to USB traffic with address 0. */ + USBFS_CR0_REG = USBFS_DEFUALT_CR0; +} + + +/******************************************************************************* +* Function Name: USBFS_Stop +****************************************************************************//** +* +* This function shuts down the USB function including to release +* the D+ pull-up and disabling the SIE. +* +* \globalvars +* \ref USBFS_configuration +* +* USBFS_deviceAddress - Contains the current device address. This +* variable is initialized to zero in this API. The Host starts to communicate +* to the device with address 0 and then sets it to a whatever value using +* a SET_ADDRESS request. +* +* \ref USBFS_deviceStatus +* +* \ref USBFS_configurationChanged +* +* USBFS_intiVar - This variable is set to zero +* +*******************************************************************************/ +void USBFS_Stop(void) +{ + uint8 enableInterrupts; + +#if (USBFS_EP_MANAGEMENT_DMA) + /* Stop all DMA channels. */ + USBFS_Stop_DMA(USBFS_MAX_EP); +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + enableInterrupts = CyEnterCriticalSection(); + + /* Disable USB IP to respond to USB traffic. */ + USBFS_CR0_REG &= (uint8) ~USBFS_CR0_ENABLE; + + /* Disable D+ pull-up. */ + USBFS_USBIO_CR1_REG &= (uint8) ~ USBFS_USBIO_CR1_USBPUEN; + +#if (CY_PSOC4) + /* Disable USBFS block. */ + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_ENABLE; +#else + /* Clear power active and standby mode templates. */ + USBFS_PM_ACT_CFG_REG &= (uint8) ~USBFS_PM_ACT_EN_FSUSB; + USBFS_PM_STBY_CFG_REG &= (uint8) ~USBFS_PM_STBY_EN_FSUSB; + + /* Ensure single-ended disable bits are high (PRT15.INP_DIS[7:6]) + * (input receiver disabled). */ + USBFS_DM_INP_DIS_REG |= (uint8) USBFS_DM_MASK; + USBFS_DP_INP_DIS_REG |= (uint8) USBFS_DP_MASK; + +#endif /* (CY_PSOC4) */ + + CyExitCriticalSection(enableInterrupts); + + /* Disable component interrupts. */ +#if (CY_PSOC4) + CyIntDisable(USBFS_INTR_HI_VECT_NUM); + CyIntDisable(USBFS_INTR_LO_VECT_NUM); + CyIntDisable(USBFS_INTR_MED_VECT_NUM); +#else + + CyIntDisable(USBFS_BUS_RESET_VECT_NUM); + CyIntDisable(USBFS_EP_0_VECT_NUM); + + #if (USBFS_SOF_ISR_ACTIVE) + CyIntDisable(USBFS_SOF_VECT_NUM); + #endif /* (USBFS_SOF_ISR_ACTIVE) */ + + #if (USBFS_EP1_ISR_ACTIVE) + CyIntDisable(USBFS_EP_1_VECT_NUM); + #endif /* (USBFS_EP1_ISR_ACTIVE) */ + + #if (USBFS_EP2_ISR_ACTIVE) + CyIntDisable(USBFS_EP_2_VECT_NUM); + #endif /* (USBFS_EP2_ISR_ACTIVE) */ + + #if (USBFS_EP3_ISR_ACTIVE) + CyIntDisable(USBFS_EP_3_VECT_NUM); + #endif /* (USBFS_EP3_ISR_ACTIVE) */ + + #if (USBFS_EP4_ISR_ACTIVE) + CyIntDisable(USBFS_EP_4_VECT_NUM); + #endif /* (USBFS_EP4_ISR_ACTIVE) */ + + #if (USBFS_EP5_ISR_ACTIVE) + CyIntDisable(USBFS_EP_5_VECT_NUM); + #endif /* (USBFS_EP5_ISR_ACTIVE) */ + + #if (USBFS_EP6_ISR_ACTIVE) + CyIntDisable(USBFS_EP_6_VECT_NUM); + #endif /* USBFS_EP6_ISR_REMOVE */ + + #if (USBFS_EP7_ISR_ACTIVE) + CyIntDisable(USBFS_EP_7_VECT_NUM); + #endif /* (USBFS_EP7_ISR_ACTIVE) */ + + #if (USBFS_EP8_ISR_ACTIVE) + CyIntDisable(USBFS_EP_8_VECT_NUM); + #endif /* (USBFS_EP8_ISR_ACTIVE) */ + + #if (USBFS_DP_ISR_ACTIVE) + /* Clear active mode Dp interrupt source history. */ + (void) USBFS_Dp_ClearInterrupt(); + CyIntClearPending(USBFS_DP_INTC_VECT_NUM); + #endif /* (USBFS_DP_ISR_ACTIVE). */ + +#endif /* (CY_PSOC4) */ + + /* Reset component internal variables. */ + USBFS_configurationChanged = 0u; + USBFS_configuration = 0u; + USBFS_interfaceNumber = 0u; + USBFS_deviceAddress = 0u; + USBFS_deviceStatus = 0u; + + /* It is mandatory for correct device startup. */ + USBFS_initVar = 0u; +} + + +/******************************************************************************* +* Function Name: USBFS_CheckActivity +****************************************************************************//** +* +* This function returns the activity status of the bus. It clears the hardware +* status to provide updated status on the next call of this function. It +* provides a way to determine whether any USB bus activity occurred. The +* application should use this function to determine if the USB suspend +* conditions are met. +* +* +* \return +* cystatus: Status of the bus since the last call of the function. +* Return Value | Description +* -------------|--------------------------------------------------------------- +* 1 |Bus activity was detected since the last call to this function +* 0 |Bus activity was not detected since the last call to this function +* +* +*******************************************************************************/ +uint8 USBFS_CheckActivity(void) +{ + uint8 cr1Reg = USBFS_CR1_REG; + + /* Clear bus activity. */ + USBFS_CR1_REG = (cr1Reg & (uint8) ~USBFS_CR1_BUS_ACTIVITY); + + /* Get bus activity. */ + return ((0u != (cr1Reg & USBFS_CR1_BUS_ACTIVITY)) ? (1u) : (0u)); +} + + +/******************************************************************************* +* Function Name: USBFS_GetConfiguration +****************************************************************************//** +* +* This function gets the current configuration of the USB device. +* +* \return +* Returns the currently assigned configuration. Returns 0 if the device +* is not configured +* +*******************************************************************************/ +uint8 USBFS_GetConfiguration(void) +{ + return (USBFS_configuration); +} + + +/******************************************************************************* +* Function Name: USBFS_IsConfigurationChanged +****************************************************************************//** +* +* This function returns the clear-on-read configuration state. It is useful +* when the host sends double SET_CONFIGURATION request with the same +* configuration number or changes alternate settings of the interface. +* After configuration has been changed the OUT endpoints must be enabled and IN +* endpoint must be loaded with data to start communication with the host. +* +* \return +* None-zero value when new configuration has been changed, otherwise zero is +* returned. +* +* \globalvars +* +* \ref USBFS_configurationChanged - This variable is set to 1 after +* a SET_CONFIGURATION request and cleared in this function. +* +*******************************************************************************/ +uint8 USBFS_IsConfigurationChanged(void) +{ + uint8 res = 0u; + + if (USBFS_configurationChanged != 0u) + { + res = USBFS_configurationChanged; + USBFS_configurationChanged = 0u; + } + + return (res); +} + + +/******************************************************************************* +* Function Name: USBFS_GetInterfaceSetting +****************************************************************************//** +* +* This function gets the current alternate setting for the specified interface. +* It is useful to identify which alternate settings are active in the specified +* interface. +* +* \param +* interfaceNumber interface number +* +* \return +* Returns the current alternate setting for the specified interface. +* +*******************************************************************************/ +uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber) + +{ + return (USBFS_interfaceSetting[interfaceNumber]); +} + + +/******************************************************************************* +* Function Name: USBFS_GetEPState +****************************************************************************//** +* +* This function returns the state of the requested endpoint. +* +* \param epNumber Data endpoint number +* +* \return +* Returns the current state of the specified USBFS endpoint. Symbolic names and +* their associated values are given in the following table. Use these constants +* whenever you write code to change the state of the endpoints, such as ISR +* code, to handle data sent or received. +* +* Return Value | Description +* -----------------------|----------------------------------------------------- +* USBFS_NO_EVENT_PENDING |The endpoint is awaiting SIE action +* USBFS_EVENT_PENDING |The endpoint is awaiting CPU action +* USBFS_NO_EVENT_ALLOWED |The endpoint is locked from access +* USBFS_IN_BUFFER_FULL |The IN endpoint is loaded and the mode is set to ACK IN +* USBFS_IN_BUFFER_EMPTY |An IN transaction occurred and more data can be loaded +* USBFS_OUT_BUFFER_EMPTY |The OUT endpoint is set to ACK OUT and is waiting for data +* USBFS_OUT_BUFFER_FULL |An OUT transaction has occurred and data can be read +* +*******************************************************************************/ +uint8 USBFS_GetEPState(uint8 epNumber) +{ + return (USBFS_EP[epNumber].apiEpState); +} + + +/******************************************************************************* +* Function Name: USBFS_GetEPCount +****************************************************************************//** +* +* This function supports Data Endpoints only(EP1-EP8). +* Returns the transfer count for the requested endpoint. The value from +* the count registers includes 2 counts for the two byte checksum of the +* packet. This function subtracts the two counts. +* +* \param epNumber Data Endpoint Number. +* Valid values are between 1 and 8. +* +* \return +* Returns the current byte count from the specified endpoint or 0 for an +* invalid endpoint. +* +*******************************************************************************/ +uint16 USBFS_GetEPCount(uint8 epNumber) +{ + uint16 cntr = 0u; + + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + /* Get 11-bits EP counter where epCnt0 - 3 bits MSB and epCnt1 - 8 bits LSB. */ + cntr = ((uint16) USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt0) & USBFS_EPX_CNT0_MASK; + cntr = ((uint16) (cntr << 8u)) | ((uint16) USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt1); + cntr -= USBFS_EPX_CNTX_CRC_COUNT; + } + + return (cntr); +} + + +#if (USBFS_EP_MANAGEMENT_DMA) +#if (CY_PSOC4) + /******************************************************************************* + * Function Name: USBFS_InitEpDma + ****************************************************************************//** + * + * This function configures priority for all DMA channels utilized by the + * component. Also sets callbacks for DMA auto mode. + * + *******************************************************************************/ + static void USBFS_InitEpDma(void) + { + #if (USBFS_DMA1_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep1_dma_CHANNEL] = USBFS_ep1_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA1_ACTIVE) */ + + #if (USBFS_DMA2_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep2_dma_CHANNEL] = USBFS_ep2_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA2_ACTIVE) */ + + #if (USBFS_DMA3_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep3_dma_CHANNEL] = USBFS_ep3_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA3_ACTIVE) */ + + #if (USBFS_DMA4_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep4_dma_CHANNEL] = USBFS_ep4_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA4_ACTIVE) */ + + #if (USBFS_DMA5_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep5_dma_CHANNEL] = USBFS_ep5_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA5_ACTIVE) */ + + #if (USBFS_DMA6_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep6_dma_CHANNEL] = USBFS_ep6_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA6_ACTIVE) */ + + #if (USBFS_DMA7_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep7_dma_CHANNEL] = USBFS_ep7_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA7_ACTIVE) */ + + #if (USBFS_DMA8_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep8_dma_CHANNEL] = USBFS_ep8_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA8_ACTIVE) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Initialize DMA channel callbacks. */ + #if (USBFS_DMA1_ACTIVE) + (void) USBFS_ep1_dma_SetInterruptCallback(&USBFS_EP1_DMA_DONE_ISR); + #endif /* (USBFS_DMA1_ACTIVE) */ + + #if (USBFS_DMA2_ACTIVE) + (void) USBFS_ep2_dma_SetInterruptCallback(&USBFS_EP2_DMA_DONE_ISR); + #endif /* (USBFS_DMA2_ACTIVE) */ + + #if (USBFS_DMA3_ACTIVE) + (void) USBFS_ep3_dma_SetInterruptCallback(&USBFS_EP3_DMA_DONE_ISR); + #endif /* (USBFS_DMA3_ACTIVE) */ + + #if (USBFS_DMA4_ACTIVE) + (void) USBFS_ep4_dma_SetInterruptCallback(&USBFS_EP4_DMA_DONE_ISR); + #endif /* (USBFS_DMA4_ACTIVE) */ + + #if (USBFS_DMA5_ACTIVE) + (void) USBFS_ep5_dma_SetInterruptCallback(&USBFS_EP5_DMA_DONE_ISR); + #endif /* (USBFS_DMA5_ACTIVE) */ + + #if (USBFS_DMA6_ACTIVE) + (void) USBFS_ep6_dma_SetInterruptCallback(&USBFS_EP6_DMA_DONE_ISR); + #endif /* (USBFS_DMA6_ACTIVE) */ + + #if (USBFS_DMA7_ACTIVE) + (void) USBFS_ep7_dma_SetInterruptCallback(&USBFS_EP7_DMA_DONE_ISR); + #endif /* (USBFS_DMA7_ACTIVE) */ + + #if (USBFS_DMA8_ACTIVE) + (void) USBFS_ep8_dma_SetInterruptCallback(&USBFS_EP8_DMA_DONE_ISR); + #endif /* (USBFS_DMA8_ACTIVE) */ + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + } +#else + + + /*************************************************************************** + * Function Name: USBFS_InitEP_DMA + ************************************************************************//** + * + * This function allocates and initializes a DMA channel to be used by the + * USBFS_LoadInEP() or USBFS_ReadOutEP() APIs for data + * transfer. It is available when the Endpoint Memory Management parameter + * is set to DMA. + * + * This function is automatically called from the USBFS_LoadInEP() and USBFS_ReadOutEP() APIs. + * + * \param epNumber Contains the data endpoint number. + * Valid values are between 1 and 8. + * \param *pData Pointer to a data array that is related to the EP transfers. + * + * \reentrant No. + * + ***************************************************************************/ + void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData) + + { + uint16 src; + uint16 dst; + + #if (CY_PSOC3) + src = HI16(CYDEV_SRAM_BASE); + dst = HI16(CYDEV_PERIPH_BASE); + pData = pData; + #else + if ((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u) + { + /* IN endpoint: source is memory buffer. */ + src = HI16(pData); + dst = HI16(CYDEV_PERIPH_BASE); + } + else + { + /* OUT endpoint: source is USB IP memory buffer. */ + src = HI16(CYDEV_PERIPH_BASE); + dst = HI16(pData); + } + #endif /* (CY_PSOC3) */ + + switch(epNumber) + { + #if (USBFS_DMA1_ACTIVE) + case USBFS_EP1: + USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA1_ACTIVE) */ + + #if (USBFS_DMA2_ACTIVE) + case USBFS_EP2: + USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA2_ACTIVE) */ + + #if (USBFS_DMA3_ACTIVE) + case USBFS_EP3: + USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA3_ACTIVE) */ + + #if (USBFS_DMA4_ACTIVE) + case USBFS_EP4: + USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA4_ACTIVE) */ + + #if (USBFS_DMA5_ACTIVE) + case USBFS_EP5: + USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA5_ACTIVE) */ + + #if (USBFS_DMA6_ACTIVE) + case USBFS_EP6: + USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA6_ACTIVE) */ + + #if (USBFS_DMA7_ACTIVE) + case USBFS_EP7: + USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA7_ACTIVE) */ + + #if (USBFS_DMA8_ACTIVE) + case USBFS_EP8: + USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA8_ACTIVE) */ + + default: + /* Do nothing for endpoints other than 1-8. */ + break; + } + + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + USBFS_DmaTd[epNumber] = CyDmaTdAllocate(); + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) + USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate(); + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + } + } +#endif /* (CY_PSOC4) */ + + /*************************************************************************** + * Function Name: USBFS_Stop_DMA + ************************************************************************//** + * + * This function stops DMA channel associated with endpoint. It is available + * when the Endpoint Buffer Management parameter is set to DMA. Call this + * function when endpoint direction is changed from IN to OUT or vice versa + * to trigger DMA re-configuration when USBFS_LoadInEP() or + * USBFS_ReadOutEP() functions are called the first time. + * + * \param epNumber: The data endpoint number for which associated DMA + * channel is stopped. The range of valid values is between 1 and 8. To stop + * all DMAs associated with endpoints call this function with + * USBFS_MAX_EP argument. + * + * \reentrant + * No. + * + ***************************************************************************/ + void USBFS_Stop_DMA(uint8 epNumber) + { + uint8 i; + + i = (epNumber < USBFS_MAX_EP) ? epNumber : USBFS_EP1; + + do + { + #if (CY_PSOC4) + if (0u != USBFS_DmaChan[i]) + { + USBFS_CyDmaChDisable(USBFS_DmaChan[i]); + } + #else + if(USBFS_DmaTd[i] != DMA_INVALID_TD) + { + (void) CyDmaChDisable(USBFS_DmaChan[i]); + CyDmaTdFree(USBFS_DmaTd[i]); + USBFS_DmaTd[i] = DMA_INVALID_TD; + } + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) + if(USBFS_DmaNextTd[i] != DMA_INVALID_TD) + { + CyDmaTdFree(USBFS_DmaNextTd[i]); + USBFS_DmaNextTd[i] = DMA_INVALID_TD; + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + + #endif /* (CY_PSOC4) */ + i++; + } + while ((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP)); + } +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + +#if (CY_PSOC3 || CY_PSOC5) +#if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) + /*************************************************************************** + * Function Name: USBFS_LoadNextInEP + ************************************************************************//** + * + * Summary: + * This internal function is used for IN endpoint DMA reconfiguration in + * Auto DMA mode. + * + * Parameters: + * epNumber: Contains the data endpoint number. + * mode: 0 - Configure DMA to send the the rest of data. + * 1 - Configure DMA to repeat 2 last bytes of the first burst. + * + ***************************************************************************/ + void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) + { + reg16 *convert; + + if (mode == 0u) + { + /* Configure DMA to send rest of data. */ + /* CyDmaTdSetConfiguration API is optimized to change transfer length only and configure TD. */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u]; + /* Set transfer length. */ + CY_SET_REG16(convert, USBFS_inLength[epNumber] - USBFS_DMA_BYTES_PER_BURST); + /* CyDmaTdSetAddress API is optimized to change source address only. */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u]; + CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] + + USBFS_DMA_BYTES_PER_BURST)); + USBFS_inBufFull[epNumber] = 1u; + } + else + { + /* Configure DMA to repeat 2 last bytes of the first burst. */ + /* CyDmaTdSetConfiguration API is optimized to change transfer length only and configure TD. */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u]; + /* Set transfer length. */ + CY_SET_REG16(convert, USBFS_DMA_BYTES_REPEAT); + /* CyDmaTdSetAddress API is optimized to change source address only. */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u]; + CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] + + (USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT))); + } + + /* CyDmaChSetInitialTd API is optimized to initialize TD. */ + CY_DMA_CH_STRUCT_PTR[USBFS_DmaChan[epNumber]].basic_status[1u] = USBFS_DmaTd[epNumber]; + } +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ +#endif /* (CY_PSOC3 || CY_PSOC5) */ + + +/******************************************************************************* +* Function Name: USBFS_LoadInEP +****************************************************************************//** +* +* This function performs different functionality depending on the Component’s +* configured Endpoint Buffer Management. This parameter is defined in +* the Descriptor Root in Component Configure window. +* +* *Manual (Static/Dynamic Allocation):* +* This function loads and enables the specified USB data endpoint for an IN +* data transfer. +* +* *DMA with Manual Buffer Management:* +* Configures DMA for a data transfer from system RAM to endpoint buffer. +* Generates request for a transfer. +* +* *DMA with Automatic Buffer Management:* +* Configures DMA. This is required only once, so it is done only when parameter +* pData is not NULL. When the pData pointer is NULL, the function skips this +* task. Sets Data ready status: This generates the first DMA transfer and +* prepares data in endpoint buffer. +* +* \param epNumber Contains the data endpoint number. +* Valid values are between 1 and 8. +* \param *pData A pointer to a data array from which the data for the endpoint space +* is loaded. +* \param length The number of bytes to transfer from the array and then send as +* a result of an IN request. Valid values are between 0 and 512 +* (1023 for DMA with Automatic Buffer Management mode). The value 512 +* is applicable if only one endpoint is used. +* +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length) + +{ + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Limit length to available buffer USB IP buffer size.*/ + if (length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset)) + { + length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset; + } + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + /* Set count and data toggle. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt0 = (uint8) HI8(length) | USBFS_EP[epNumber].epToggle; + USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt1 = (uint8) LO8(length); + + #if (USBFS_EP_MANAGEMENT_MANUAL) + if (NULL != pData) + { + /* Copy data using arbiter data register. */ + uint16 i; + for (i = 0u; i < length; ++i) + { + USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr = pData[i]; + } + } + + /* IN endpoint buffer is full - read to be read. */ + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + + /* Arm IN endpoint. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + + #else + + #if (CY_PSOC3 || CY_PSOC5LP) + /* Initialize DMA if it was not initialized. */ + if (DMA_INVALID_TD == USBFS_DmaTd[epNumber]) + { + USBFS_InitEP_DMA(epNumber, pData); + } + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* IN endpoint buffer will be fully loaded by DMA shortly. */ + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + + if ((pData != NULL) && (length > 0u)) + { + #if (CY_PSOC4) + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Configure source and destination. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr); + + /* Configure DMA descriptor. */ + --length; + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | length | + CYDMA_BYTE | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE); + + /* Validate descriptor to execute on following DMA request. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + #else + /* Configure DMA to transfer data. */ + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, TD_TERMIN_EN | TD_INC_SRC_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) pData), LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr)); + + /* Enable DMA channel. */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + #endif /* (CY_PSOC4) */ + + /* Generate DMA request. */ + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint8) USBFS_ARB_EPX_CFG_DMA_REQ; + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_DMA_REQ; + + /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */ + } + else + { + /* When zero-length packet: arm IN endpoint directly. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + if (pData != NULL) + { + #if (CY_PSOC4) + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Store address of buffer. */ + USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData; + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Set destination address. */ + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | + CYDMA_BYTE | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG | + CYDMA_BYTE | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Enable interrupt from DMA channel. */ + USBFS_CyDmaSetInterruptMask(channelNum); + + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + #else + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + USBFS_inLength[epNumber] = length; + USBFS_inDataPointer[epNumber] = pData; + + /* Configure DMA to send data only for first burst */ + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], + (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length, + USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) pData), + LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr)); + + /* The second TD will be executed only when the first one fails. + * The intention of this TD is to generate NRQ interrupt + * and repeat 2 last bytes of the first burst. + */ + (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u, + USBFS_DmaNextTd[epNumber], + USBFS_epX_TD_TERMOUT_EN[epNumber]); + + /* Configure DmaNextTd to clear Data Ready status. */ + (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber], LO16((uint32) &clearInDataRdyStatus), + LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg)); + #else + /* Configure DMA to send all data. */ + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, + USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) pData), + LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr)); + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ + + /* Clear any potential pending DMA requests before starting DMA channel to transfer data. */ + (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); + /* Enable DMA. */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + #endif /* (CY_PSOC4) */ + } + else + { + /* IN endpoint buffer (32 bytes) will shortly be preloaded by DMA. */ + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + + if (length > 0u) + { + #if (CY_PSOC4) + uint32 lengthDescr0, lengthDescr1; + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Get number of full bursts. */ + USBFS_DmaEpBurstCnt[epNumber] = (uint8) (length / USBFS_DMA_BYTES_PER_BURST); + + /* Get number of elements in the last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (length % USBFS_DMA_BYTES_PER_BURST); + + /* Get total number of bursts. */ + USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u; + + /* Adjust number of data elements transferred in last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? + (USBFS_DmaEpLastBurstEl[epNumber] - 1u) : + (USBFS_DMA_BYTES_PER_BURST - 1u); + + /* Get number of data elements to transfer for descriptor 0 and 1. */ + lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u); + lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u); + + + /* Mark which descriptor is last one to execute. */ + USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ? + USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK; + + /* Restore DMA settings for current transfer. */ + USBFS_CyDmaChDisable(channelNum); + + /* Restore destination address for input endpoint. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber])); + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber] + + USBFS_DMA_BYTES_PER_BURST)); + + /* Set number of elements to transfer. */ + USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR0, lengthDescr0); + USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR1, lengthDescr1); + + /* Validate descriptor 0 and command to start with it. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + USBFS_CyDmaSetDescriptor0Next(channelNum); + + /* Validate descriptor 1. */ + if (USBFS_DmaEpBurstCnt[epNumber] > 1u) + { + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1); + } + + /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */ + USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + #elif (USBFS_EP_DMA_AUTO_OPT == 0u) + USBFS_inLength[epNumber] = length; + USBFS_inBufFull[epNumber] = 0u; + + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + /* Configure DMA to send data only for first burst. */ + (void) CyDmaTdSetConfiguration( + USBFS_DmaTd[epNumber], (length > USBFS_DMA_BYTES_PER_BURST) ? + USBFS_DMA_BYTES_PER_BURST : length, + USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR ); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) USBFS_inDataPointer[epNumber]), + LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr)); + /* Clear Any potential pending DMA requests before starting DMA channel to transfer data. */ + (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); + /* Enable DMA. */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + #endif /* (CY_PSOC4) */ + + #if !defined (USBFS_MANUAL_IN_EP_ARM) + /* Set IN data ready to generate DMA request to load data into endpoint buffer. */ + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= USBFS_ARB_EPX_CFG_IN_DATA_RDY; + #endif /* (USBFS_MANUAL_IN_EP_ARM) */ + + /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */ + } + else + { + /* When zero-length packet: arm IN endpoint directly. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + } + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */ + } +} + + +/******************************************************************************* +* Function Name: USBFS_ReadOutEP +****************************************************************************//** +* +* This function performs different functionality depending on the Component’s +* configured Endpoint Buffer Management. This parameter is defined in the +* Descriptor Root in Component Configure window. +* +* *Manual (Static/Dynamic Allocation):* +* This function moves the specified number of bytes from endpoint buffer to +* system RAM. The number of bytes actually transferred from endpoint buffer to +* system RAM is the lesser of the actual number of bytes sent by the host or +* the number of bytes requested by the length parameter. +* +* *DMA with Manual Buffer Management:* +* Configure DMA to transfer data from endpoint buffer to system RAM. Generate +* a DMA request. The firmware must wait until the DMA completes the data +* transfer after calling the USBFS_ReadOutEP() API. For example, +* by checking EPstate: +* +* \snippet /USBFS_sut_02.cydsn/main.c checking EPstatey +* +* The USBFS_EnableOutEP() has to be called to allow host to write data into +* the endpoint buffer after DMA has completed transfer data from OUT endpoint +* buffer to SRAM. +* +* *DMA with Automatic Buffer Management:* +* Configure DMA. This is required only once and automatically generates DMA +* requests as data arrives +* +* \param epNumber: Contains the data endpoint number. +* Valid values are between 1 and 8. +* \param pData: A pointer to a data array from which the data for the endpoint +* space is loaded. +* \param length: The number of bytes to transfer from the USB Out endpoint and +* loads it into data array. Valid values are between 0 and 1023. The +* function moves fewer than the requested number of bytes if the host +* sends fewer bytes than requested. +* +* \return +* Number of bytes received, 0 for an invalid endpoint. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length) + +{ + if ((pData != NULL) && (epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Adjust requested length to available data. */ + length = (length > USBFS_GetEPCount(epNumber)) ? USBFS_GetEPCount(epNumber) : length; + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + #if (USBFS_EP_MANAGEMENT_MANUAL) + { + /* Copy data using arbiter data register. */ + uint16 i; + for (i = 0u; i < length; ++i) + { + pData[i] = (uint8) USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr; + } + } + + /* Arm OUT endpoint after data has been copied from endpoint buffer. */ + USBFS_EnableOutEP(epNumber); + #else + + #if (CY_PSOC3 || CY_PSOC5LP) + /* Initialize DMA if it was not initialized. */ + if (DMA_INVALID_TD == USBFS_DmaTd[epNumber]) + { + USBFS_InitEP_DMA(epNumber, pData); + } + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + #if (CY_PSOC4) + { + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Configure source and destination. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | (uint16)(length - 1u) | + CYDMA_BYTE | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE); + + /* Validate descriptor to execute on following DMA request. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + } + #else + /* Configure DMA to transfer data. */ + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, TD_TERMIN_EN | TD_INC_DST_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr), LO16((uint32)pData)); + + /* Enable DMA channel. */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + #endif /* (CY_PSOC4) */ + + /* Generate DMA request. */ + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint8) USBFS_ARB_EPX_CFG_DMA_REQ; + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_DMA_REQ; + + /* OUT endpoint has to be armed again by user when DMA transfers have been completed. + * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer. + */ + + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + #if (CY_PSOC4) + { + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + uint32 lengthDescr0, lengthDescr1; + + /* Get number of full bursts. */ + USBFS_DmaEpBurstCnt[epNumber] = (uint8) (length / USBFS_DMA_BYTES_PER_BURST); + + /* Get number of elements in the last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (length % USBFS_DMA_BYTES_PER_BURST); + + /* Get total number of bursts. */ + USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u; + + /* Adjust number of the data elements transfered in last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? + (USBFS_DmaEpLastBurstEl[epNumber] - 1u) : + (USBFS_DMA_BYTES_PER_BURST - 1u); + + /* Get number of data elements to transfer for descriptor 0 and 1. */ + lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u); + lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u); + + /* Mark if revert number of data elements in descriptor after transfer completion. */ + USBFS_DmaEpLastBurstEl[epNumber] |= (USBFS_DmaEpBurstCnt[epNumber] > 2u) ? USBFS_DMA_DESCR_REVERT : 0u; + + /* Mark last descriptor to be executed. */ + USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ? + USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK; + + /* Store address of buffer and burst counter for endpoint. */ + USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData; + USBFS_DmaEpBurstCntBackup[epNumber] = USBFS_DmaEpBurstCnt[epNumber]; + + /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */ + USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]); + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Set destination address. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr); + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr); + + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) pData)); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) pData + USBFS_DMA_BYTES_PER_BURST)); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | lengthDescr0 | + CYDMA_BYTE | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG | lengthDescr1 | + CYDMA_BYTE | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Enable interrupt from DMA channel. */ + USBFS_CyDmaSetInterruptMask(channelNum); + + /* Validate DMA descriptor 0 and 1. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + + if (USBFS_DmaEpBurstCntBackup[epNumber] > 1u) + { + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1); + } + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + } + #else + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_DST_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr), LO16((uint32) pData)); + + /* Clear Any potential pending DMA requests before starting DMA channel to transfer data. */ + (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); + + /* Enable DMA channel. */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + #endif /* (CY_PSOC4) */ + + /* OUT endpoint has to be armed again by user when DMA transfers have been completed. + * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer. + */ + + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */ + } + else + { + length = 0u; + } + + return (length); +} + + +#if (USBFS_16BITS_EP_ACCESS_ENABLE) +/******************************************************************************* +* Function Name: USBFS_LoadInEP16 +****************************************************************************//** +* +* This function performs different functionality depending on the Component’s +* configured Endpoint Buffer Management. This parameter is defined in +* the Descriptor Root in Component Configure window. +* +* *Manual (Static/Dynamic Allocation):* +* This function loads and enables the specified USB data endpoint for an IN +* data transfer. +* +* *DMA with Manual Buffer Management:* +* Configures DMA for a data transfer from system RAM to endpoint buffer. +* Generates request for a transfer. +* +* *DMA with Automatic Buffer Management:* +* Configures DMA. This is required only once, so it is done only when parameter +* pData is not NULL. When the pData pointer is NULL, the function skips this +* task. Sets Data ready status: This generates the first DMA transfer and +* prepares data in endpoint buffer. +* +* \param epNumber Contains the data endpoint number. +* Valid values are between 1 and 8. +* \param *pData A pointer to a data array from which the data for the endpoint +* space is loaded. It shall be ensured that this pointer address is even +* to ensure the 16-bit transfer is aligned to even address. Else, a hard +* fault condition can occur. +* \param length The number of bytes to transfer from the array and then send as +* a result of an IN request. Valid values are between 0 and 512 (1023 for +* DMA with Automatic Buffer Management mode). The value 512 is applicable +* if only one endpoint is used. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_LoadInEP16(uint8 epNumber, const uint8 pData[], uint16 length) +{ + /* Check array alignment on half-word boundary. */ + CYASSERT(0u == (((uint32) pData) & 0x01u)); + + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Limit length to available buffer USB IP buffer size. */ + if (length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset)) + { + length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset; + } + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + /* Set count and data toggle. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt0 = (uint32) HI8(length) | USBFS_EP[epNumber].epToggle; + USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt1 = (uint32) LO8(length); + + /* Adjust requested length: 2 bytes are handled at one data register access. */ + length += (length & 0x01u); + + #if (USBFS_EP_MANAGEMENT_MANUAL) + if (NULL != pData) + { + /* Convert uint8 array to uint16. */ + const uint16 *dataBuf = (uint16 *) pData; + + /* Copy data using 16-bits arbiter data register. */ + uint16 i; + for (i = 0u; i < (length >> 1u); ++i) + { + USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16 = dataBuf[i]; + } + } + + /* IN endpoint buffer is full - read to be read. */ + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + + /* Arm IN endpoint. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + + #else + + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* IN endpoint buffer will be fully loaded by DMA shortly. */ + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + + if ((pData != NULL) && (length > 0u)) + { + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Configure source and destination. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16); + + /* Configure DMA descriptor. */ + length = (length >> 1u) - 1u; + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | length | + CYDMA_HALFWORD | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE); + + /* Validate descriptor to execute on following DMA request. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + /* Generate DMA request. */ + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint32) USBFS_ARB_EPX_CFG_DMA_REQ; + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint32) ~USBFS_ARB_EPX_CFG_DMA_REQ; + + /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */ + } + else + { + /* When zero-length packet: arm IN endpoint directly. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + if (pData != NULL) + { + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Store address of buffer. */ + USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData; + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Set destination address. */ + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | + CYDMA_HALFWORD | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG | + CYDMA_HALFWORD | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Enable interrupt from DMA channel. */ + USBFS_CyDmaSetInterruptMask(channelNum); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + } + else + { + /* IN endpoint buffer (32 bytes) will shortly be preloaded by DMA. */ + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + + if (length > 0u) + { + uint32 lengthDescr0, lengthDescr1; + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Get number of full bursts. */ + USBFS_DmaEpBurstCnt[epNumber] = (uint8) (length / USBFS_DMA_BYTES_PER_BURST); + + /* Get number of elements in the last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (length % USBFS_DMA_BYTES_PER_BURST); + + /* Get total number of bursts. */ + USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u; + + /* Adjust number of data elements transferred in last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? + ((USBFS_DmaEpLastBurstEl[epNumber] >> 1u) - 1u) : + (USBFS_DMA_HALFWORDS_PER_BURST - 1u); + + /* Get number of data elements to transfer for descriptor 0 and 1. */ + lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u); + lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u); + + /* Mark which descriptor is last one to execute. */ + USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ? + USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK; + + /* Restore DMA settings for current transfer. */ + USBFS_CyDmaChDisable(channelNum); + + /* Restore destination address for input endpoint. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber])); + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber] + + USBFS_DMA_BYTES_PER_BURST)); + + /* Set number of elements to transfer. */ + USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR0, lengthDescr0); + USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR1, lengthDescr1); + + /* Validate descriptor 0 and command to start with it. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + USBFS_CyDmaSetDescriptor0Next(channelNum); + + /* Validate descriptor 1. */ + if (USBFS_DmaEpBurstCnt[epNumber] > 1u) + { + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1); + } + + /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */ + USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + #if !defined (USBFS_MANUAL_IN_EP_ARM) + /* Set IN data ready to generate DMA request to load data into endpoint buffer. */ + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= USBFS_ARB_EPX_CFG_IN_DATA_RDY; + #endif /* (USBFS_MANUAL_IN_EP_ARM) */ + + /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */ + } + else + { + /* When zero-length packet: arm IN endpoint directly. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + } + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */ + } +} + + +/******************************************************************************* +* Function Name: USBFS_ReadOutEP16 +****************************************************************************//** +* +* This function performs different functionality depending on the Component’s +* configured Endpoint Buffer Management. This parameter is defined in the +* Descriptor Root in Component Configure window. +* +* *Manual (Static/Dynamic Allocation):* +* This function moves the specified number of bytes from endpoint buffer to +* system RAM. The number of bytes actually transferred from endpoint buffer to +* system RAM is the lesser of the actual number of bytes sent by the host or +* the number of bytes requested by the length parameter. +* +* *DMA with Manual Buffer Management:* +* Configure DMA to transfer data from endpoint buffer to system RAM. Generate +* a DMA request. The firmware must wait until the DMA completes the data +* transfer after calling the USBFS_ReadOutEP() API. For example, +* by checking EPstate: +* +* \snippet /USBFS_sut_02.cydsn/main.c checking EPstatey +* +* The USBFS_EnableOutEP() has to be called to allow host to write data into +* the endpoint buffer after DMA has completed transfer data from OUT endpoint +* buffer to SRAM. +* +* *DMA with Automatic Buffer Management:* +* Configure DMA. This is required only once and automatically generates DMA +* requests as data arrives +* +* \param epNumber: Contains the data endpoint number. +* Valid values are between 1 and 8. +* \param pData: A pointer to a data array into which the data for the endpoint +* space is copied. It shall be ensured that this pointer address is +* even to ensure the 16-bit transfer is aligned to even address. Else, +* a hard fault condition can occur. +* \param length: The number of bytes to transfer from the USB Out endpoint and +* loads it into data array. Valid values are between 0 and 1023. The +* function moves fewer than the requested number of bytes if the host +* sends fewer bytes than requested. +* +* \return +* Number of bytes received, 0 for an invalid endpoint. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint16 USBFS_ReadOutEP16(uint8 epNumber, uint8 pData[], uint16 length) +{ + uint32 adjLength; + + /* Check array alignment on half-word boundary */ + CYASSERT(0u == (((uint32) pData) & 0x01u)); + + if ((pData != NULL) && (epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Adjust requested length to available data. */ + length = (length > USBFS_GetEPCount(epNumber)) ? USBFS_GetEPCount(epNumber) : length; + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + /* Adjust requested length: 2 bytes are handled at one data register access. */ + adjLength = length + ((uint32)length & 1u); + + #if (USBFS_EP_MANAGEMENT_MANUAL) + { + /* Convert uint8 array to uint16. */ + uint16 *dataBuf = (uint16 *) pData; + + /* Copy data using 16-bits arbiter data register. */ + uint16 i; + for (i = 0u; i < (adjLength >> 1u); ++i) + { + dataBuf[i] = (uint16) USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16; + } + } + + /* Arm OUT endpoint after data has been read from endpoint buffer. */ + USBFS_EnableOutEP(epNumber); + #else + + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + { + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Configure source and destination. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | (uint16)((adjLength >> 1u) - 1u) | + CYDMA_HALFWORD | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE); + + /* Validate descriptor to execute on following DMA request. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + /* Generate DMA request. */ + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint32) USBFS_ARB_EPX_CFG_DMA_REQ; + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint32) ~USBFS_ARB_EPX_CFG_DMA_REQ; + + /* OUT endpoint has to be armed again by user when DMA transfers have been completed. + * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer. + */ + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + { + uint32 lengthDescr0, lengthDescr1; + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Get number of full bursts. */ + USBFS_DmaEpBurstCnt[epNumber] = (uint8) (adjLength / USBFS_DMA_BYTES_PER_BURST); + + /* Get number of elements in last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (adjLength % USBFS_DMA_BYTES_PER_BURST); + + /* Get total number of bursts. */ + USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u; + + /* Adjust number of data elements transferred in last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? + ((USBFS_DmaEpLastBurstEl[epNumber] >> 1u) - 1u) : + (USBFS_DMA_HALFWORDS_PER_BURST - 1u); + + /* Get number of data elements to transfer for descriptor 0 and 1. */ + lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u); + lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u); + + /* Mark last descriptor to be executed. */ + USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ? + USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK; + + /* Mark if revert number of data elements in descriptor after transfer completion. */ + USBFS_DmaEpLastBurstEl[epNumber] |= (USBFS_DmaEpBurstCnt[epNumber] > 2u) ? USBFS_DMA_DESCR_REVERT : 0u; + + /* Mark that 16-bits access to data register is performed. */ + USBFS_DmaEpLastBurstEl[epNumber] |= USBFS_DMA_DESCR_16BITS; + + /* Store address of buffer and burst counter for endpoint. */ + USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData; + USBFS_DmaEpBurstCntBackup[epNumber] = USBFS_DmaEpBurstCnt[epNumber]; + + /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */ + USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]); + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Set destination address. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16); + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16); + + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) pData)); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) pData + USBFS_DMA_BYTES_PER_BURST)); + + /* Configure DMA descriptor 0. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | lengthDescr0 | + CYDMA_HALFWORD | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Configure DMA descriptor 1. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG | lengthDescr1 | + CYDMA_HALFWORD | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Enable interrupt from DMA channel. */ + USBFS_CyDmaSetInterruptMask(channelNum); + + /* Validate DMA descriptor 0 and 1. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + + if (USBFS_DmaEpBurstCntBackup[epNumber] > 1u) + { + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1); + } + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + /* OUT endpoint has to be armed again by user when DMA transfers have been completed. + * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer. + */ + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */ + } + else + { + length = 0u; + } + + return (length); +} +#endif /* (USBFS_16BITS_EP_ACCESS_ENABLE) */ + + +/******************************************************************************* +* Function Name: USBFS_EnableOutEP +****************************************************************************//** +* +* This function enables the specified endpoint for OUT transfers. Do not call +* this function for IN endpoints. +* +* \param epNumber: Contains the data endpoint number. Valid values are between +* 1 and 8. +* +* \globalvars +* +* \ref USBFS_EP[epNumber].apiEpState - set to NO_EVENT_PENDING +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_EnableOutEP(uint8 epNumber) +{ + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + + /* Enable OUT endpoint to be written by Host. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + + } +} + + +/******************************************************************************* +* Function Name: USBFS_DisableOutEP +****************************************************************************//** +* +* This function disables the specified USBFS OUT endpoint. Do not call this +* function for IN endpoints. +* +* \param epNumber: Contains the data endpoint number. +* Valid values are between 1 and 8. +* +*******************************************************************************/ +void USBFS_DisableOutEP(uint8 epNumber) +{ + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + /* Set NAK response for OUT endpoint. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_MODE_NAK_OUT; + } +} + + +/******************************************************************************* +* Function Name: USBFS_Force +****************************************************************************//** +* +* This function forces a USB J, K, or SE0 state on the D+/D– lines. It provides +* the necessary mechanism for a USB device application to perform a USB Remote +* Wakeup. For more information, see the USB 2.0 Specification for details on +* Suspend and Resume. +* +* \param state A byte indicating which of the four bus states to enable. +* Symbolic names and their associated values are listed here: +* State |Description +* ---------------------------|---------------------------------------------- +* USBFS_FORCE_J | Force a J State onto the D+/D– lines +* USBFS_FORCE_K | Force a K State onto the D+/D– lines +* USBFS_FORCE_SE0 | Force a Single Ended 0 onto the D+/D– lines +* USBFS_FORCE_NONE| Return bus to SIE control +* +* +*******************************************************************************/ +void USBFS_Force(uint8 bState) +{ + /* This registers is used only for manual control of SIE (no masking is + * needed before write into it). + */ + USBFS_USBIO_CR0_REG = bState; +} + + +/******************************************************************************* +* Function Name: USBFS_GetEPAckState +****************************************************************************//** +* +* This function determines whether an ACK transaction occurred on this endpoint +* by reading the ACK bit in the control register of the endpoint. It does not +* clear the ACK bit. +* +* \param epNumber Contains the data endpoint number. +* Valid values are between 1 and 8. +* +* \return +* If an ACKed transaction occurred, this function returns a non-zero value. +* Otherwise, it returns zero. +* +*******************************************************************************/ +uint8 USBFS_GetEPAckState(uint8 epNumber) +{ + uint8 cr = 0u; + + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + cr = USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 & USBFS_MODE_ACKD; + } + + return ((uint8) cr); +} + + +/******************************************************************************* +* Function Name: USBFS_SetPowerStatus +****************************************************************************//** +* +* This function sets the current power status. The device replies to USB +* GET_STATUS requests based on this value. This allows the device to properly +* report its status for USB Chapter 9 compliance. Devices can change their +* power source from self powered to bus powered at any time and report their +* current power source as part of the device status. You should call this +* function any time your device changes from self powered to bus powered or +* vice versa, and set the status appropriately. +* +* \param powerStatus: Contains the desired power status, one for self powered +* or zero for bus powered. Symbolic names and their associated values are +* given here: +* Power Status |Description +* --------------------------------------------|--------------------------- +* USBFS_DEVICE_STATUS_BUS_POWERED | Set the device to bus powered +* USBFS_DEVICE_STATUS_SELF_POWERED | Set the device to self powered +* +* \globalvars +* +* \ref USBFS_deviceStatus - set power status +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_SetPowerStatus(uint8 powerStatus) +{ + if (powerStatus != USBFS_DEVICE_STATUS_BUS_POWERED) + { + USBFS_deviceStatus |= (uint8) USBFS_DEVICE_STATUS_SELF_POWERED; + } + else + { + USBFS_deviceStatus &= (uint8) ~USBFS_DEVICE_STATUS_SELF_POWERED; + } +} + + +#if (USBFS_VBUS_MONITORING_ENABLE) + /*************************************************************************** + * Function Name: USBFS_VBusPresent + ************************************************************************//** + * + * Determines VBUS presence for self-powered devices. This function is + * available when the VBUS Monitoring option is enabled in the Advanced tab. + * + * \return + * The return value can be the following: + * Return Value | Description + * -------------|----------------- + * 1 | VBUS is present + * 0 | VBUS is absent + * + * + ***************************************************************************/ + uint8 USBFS_VBusPresent(void) + { + return ((0u != (USBFS_VBUS_STATUS_REG & USBFS_VBUS_VALID)) ? (uint8) 1u : (uint8) 0u); + } +#endif /* (USBFS_VBUS_MONITORING_ENABLE) */ + + +/******************************************************************************* +* Function Name: USBFS_RWUEnabled +****************************************************************************//** +* +* This function returns the current remote wakeup status. +* If the device supports remote wakeup, the application should use this +* function to determine if remote wakeup was enabled by the host. When the +* device is suspended and it determines the conditions to initiate a remote +* wakeup are met, the application should use the USBFS_Force() function to +* force the appropriate J and K states onto the USB bus, signaling a remote +* wakeup. +* +* +* \return +* Returns non-zero value if remote wakeup is enabled and zero otherwise. +* +* \globalvars +* USBFS_deviceStatus - checked to determine remote status +* +*******************************************************************************/ +uint8 USBFS_RWUEnabled(void) +{ + uint8 result = USBFS_FALSE; + + if (0u != (USBFS_deviceStatus & USBFS_DEVICE_STATUS_REMOTE_WAKEUP)) + { + result = USBFS_TRUE; + } + + return (result); +} + + +/******************************************************************************* +* Function Name: USBFS_GetDeviceAddress +****************************************************************************//** +* +* This function returns the currently assigned address for the USB device. +* +* \return +* Returns the currently assigned address. +* Returns 0 if the device has not yet been assigned an address. +* +*******************************************************************************/ +uint8 USBFS_GetDeviceAddress(void) +{ + return (uint8)(USBFS_CR0_REG & USBFS_CR0_DEVICE_ADDRESS_MASK); +} + + +/******************************************************************************* +* Function Name: USBFS_EnableSofInt +****************************************************************************//** +* +* This function enables interrupt generation when a Start-of-Frame (SOF) +* packet is received from the host. +* +*******************************************************************************/ +void USBFS_EnableSofInt(void) +{ +#if (CY_PSOC4) + /* Enable SOF interrupt interrupt source. */ + USBFS_INTR_SIE_MASK_REG |= (uint32) USBFS_INTR_SIE_SOF_INTR; +#else + /* Enable SOF interrupt if it is present. */ + #if (USBFS_SOF_ISR_ACTIVE) + CyIntEnable(USBFS_SOF_VECT_NUM); + #endif /* (USBFS_SOF_ISR_ACTIVE) */ +#endif /* (CY_PSOC4) */ +} + + +/******************************************************************************* +* Function Name: USBFS_DisableSofInt +****************************************************************************//** +* +* This function disables interrupt generation when a Start-of-Frame (SOF) +* packet is received from the host. +* +*******************************************************************************/ +void USBFS_DisableSofInt(void) +{ +#if (CY_PSOC4) + /* Disable SOF interrupt interrupt source. */ + USBFS_INTR_SIE_MASK_REG &= (uint32) ~USBFS_INTR_SIE_SOF_INTR; +#else + /* Disable SOF interrupt if it is present. */ + #if (USBFS_SOF_ISR_ACTIVE) + CyIntDisable(USBFS_SOF_VECT_NUM); + #endif /* (USBFS_SOF_ISR_ACTIVE) */ +#endif /* (CY_PSOC4) */ +} + + +#if (USBFS_BATT_CHARG_DET_ENABLE) + /*************************************************************************** + * Function Name: USBFS_DetectPortType + ************************************************************************//** + * + * This function implements the USB Battery Charger Detection (BCD) + * algorithm to determine the type of USB host downstream port. This API + * is available only for PSoC 4 devices, and should be called when the VBUS + * voltage transition (OFF to ON) is detected on the bus. If the USB device + * functionality is enabled, this API first calls USBFS_Stop() API + * internally to disable the USB device functionality, and then proceeds to + * implement the BCD algorithm to detect the USB host port type. + * The USBFS_Start() API should be called after this API if the USB + * communication needs to be initiated with the host. + * *Note* This API is generated only if the “Enable Battery Charging + * Detection†option is enabled in the “Advanced†tab of the component GUI. + * *Note* API implements the steps 2-4 of the BCD algorithm which are + * - Data Contact Detect + * - Primary Detection + * - Secondary Detection + * + * The first step of BCD algorithm, namely, VBUS detection shall be handled + * at the application firmware level. + * + * \return + * The return value can be the following: + * Return Value |Description + * ----------------------------------|------------------------------------- + * USBFS_BCD_PORT_SDP | Standard downstream port detected + * USBFS_BCD_PORT_CDP | Charging downstream port detected + * USBFS_BCD_PORT_DCP | Dedicated charging port detected + * USBFS_BCD_PORT_UNKNOWN | Unable to detect charging port type (proprietary charger type) + * USBFS_BCD_PORT_ERR | Error condition in detection process + * + * + * \sideeffects + * + * USB device functionality is disabled by this API if not already disabled. + * + ***************************************************************************/ + uint8 USBFS_Bcd_DetectPortType(void) + { + uint32 bkPwrCtrl; + uint32 cr1RegVal; + uint32 secondaryDetection = 0u; + uint8 result = USBFS_BCD_PORT_UNKNOWN; + + /*Check USB Started and Stop it*/ + if(0u != USBFS_initVar) + { + USBFS_Stop(); + } + /*Initialize USBFS IP for Charger detection*/ + + /*Enable clock to USB IP. */ + USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_CSR_CLK_EN; + + /* Enable USBIO control on drive mode of D+ and D- pins. */ + USBFS_USBIO_CR1_REG &= ~ (uint32) USBFS_USBIO_CR1_IOMODE; + + /* Select VBUS detection source and clear PHY isolate. The application + * level must ensure that VBUS is valid. There is no need to wait 2us + * before VBUS is valid. + */ + bkPwrCtrl = USBFS_POWER_CTRL_REG; + USBFS_POWER_CTRL_REG = USBFS_DEFAULT_POWER_CTRL_VBUS\ + & (~USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN)\ + & (~USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN); + + + /* Enable PHY detector and single-ended and differential receivers. + * Enable charger detection. */ + USBFS_POWER_CTRL_REG |= USBFS_DEFAULT_POWER_CTRL_PHY\ + | USBFS_POWER_CTRL_ENABLE_CHGDET; + + /* Suspend clear sequence. */ + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND; + CyDelayUs(USBFS_WAIT_SUSPEND_DEL_DISABLE); + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND_DEL; + + /* Data connection detection + * Realization with delay as Hard IP does not support DCD 300 ms. + */ + #if defined (USBFS_NO_DCD) + CyDelay(USBFS_BCD_TIMEOUT); + #else + /* DCD implementation:*/ + + { + uint16 timeout = USBFS_BCD_TIMEOUT; + uint8 connectionApproved = 0u; + uint8 connected = 0u; + + /* BCD spec 1.2: Turns on Idp_src and D- pull-down resistor */ + USBFS_POWER_CTRL_REG |= USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN; + USBFS_CHGDET_CTRL_REG |= USBFS_CHGDET_CTRL_DCD_SRC_EN; + + /* BCD spec 1.2: Waits for D+ to be low for a time of Tdcd_dbnc*/ + while ((0u != timeout) && (0u == connectionApproved)) + { + if (0u == (USBFS_USBIO_CR1_REG & USBFS_USBIO_CR1_DP0)) + { + connected++; + } + else + { + connected = 0u; + } + connectionApproved = (USBFS_BCD_TDCD_DBNC < connected) ? 1u:0u; + CyDelay(1u); + timeout--; + } + + /* BCD spec 1.2: Turns off Idp_src. */ + USBFS_CHGDET_CTRL_REG &= ~USBFS_CHGDET_CTRL_DCD_SRC_EN; + } + #endif /*(USBFS_NO_DCD)*/ + + /* Primary detection: enable VDP_SRC on D+ and IDM_SINK on D-. */ + USBFS_CHGDET_CTRL_REG = USBFS_CHGDET_CTRL_PRIMARY; + CyDelay(USBFS_BCD_PRIMARY_WAIT); + cr1RegVal = USBFS_USBIO_CR1_REG; + + /* Check is it SDP or DCP/CDP, read comparator 2 output. */ + if (0u == (USBFS_CHGDET_CTRL_REG & USBFS_CHGDET_CTRL_COMP_OUT)) + { + /* Check status of D- line. */ + if (0u == (cr1RegVal & USBFS_USBIO_CR1_DM0)) + { + result = USBFS_BCD_PORT_SDP; + } + else + { + /* ERROR: such combination is impossible. Abort charger + * detection. + */ + result = USBFS_BCD_PORT_ERR; + } + } + else + { + /* Need Secondary detection. Charging port: DCP or proprietary*/ + secondaryDetection = 1u; + } + + /* Secondary detection: Set CHGDET_CTRL register to enable VDM_SRC on D- and IDP_SINK on D+. */ + + if (0u != secondaryDetection) + { + USBFS_CHGDET_CTRL_REG = USBFS_CHGDET_CTRL_DEFAULT \ + | USBFS_CHGDET_CTRL_SECONDARY; + CyDelay(USBFS_BCD_SECONDARY_WAIT); + cr1RegVal = USBFS_USBIO_CR1_REG; + + /* Check is it SDP or DCP/CDP, read comparator 1 output. */ + if (0u == (USBFS_CHGDET_CTRL_REG & USBFS_CHGDET_CTRL_COMP_OUT)) + { + /* Check status of D+ line. */ + if (0u == (cr1RegVal & USBFS_USBIO_CR1_DP0)) + { + result = USBFS_BCD_PORT_CDP; + } + else + { + /* ERROR: such combination is impossible. Abort charger + * detection. + */ + result = USBFS_BCD_PORT_ERR; + } + } + else + { + /* Check status of D+ line. */ + if (0u == (cr1RegVal & USBFS_USBIO_CR1_DP0)) + { + result = USBFS_BCD_PORT_DCP; + } + else + { + /* It is may be proprietary charger. Proprietary charge is + * not supported byHardware IP block. + */ + result = USBFS_BCD_PORT_UNKNOWN; + } + } + } + + /* Restore CHGDET_CTRL. */ + USBFS_CHGDET_CTRL_REG = 0u; + + /*Revert registers back*/ + USBFS_POWER_CTRL_REG = bkPwrCtrl; + USBFS_USBIO_CR1_REG |= (uint32) USBFS_USBIO_CR1_IOMODE; + USBFS_USB_CLK_EN_REG = ~USBFS_USB_CLK_CSR_CLK_EN; + + return (result); + } +#endif /* (USBFS_BATT_CHARG_DET_ENABLE) */ + + +#if (USBFS_LPM_ACTIVE) + /*************************************************************************** + * Function Name: USBFS_Lpm_GetBeslValue + ************************************************************************//** + * + * This function returns the Best Effort Service Latency (BESL) value + * sent by the host as part of the LPM token transaction. + * + * \return + * 4-bit BESL value received in the LPM token packet from the host + * + * + ***************************************************************************/ + uint32 USBFS_Lpm_GetBeslValue(void) + { + return (uint32) (USBFS_LPM_STAT_REG & USBFS_LPM_STAT_LPM_BESL_MASK); + } + + + /*************************************************************************** + * Function Name: USBFS_Lpm_RemoteWakeUpAllowed + ************************************************************************//** + * + * This function returns the remote wakeup permission set for the device by + * the host as part of the LPM token transaction. + * + * \return + * 0 - remote wakeup not allowed, 1 - remote wakeup allowed + * + * + ***************************************************************************/ + uint32 USBFS_Lpm_RemoteWakeUpAllowed(void) + { + return (uint32) (USBFS_LPM_STAT_REG & USBFS_LPM_STAT_LPM_REMOTE_WAKE); + } + + + /*************************************************************************** + * Function Name: USBFS_Lpm_SetResponse + ************************************************************************//** + * + * This function configures the response in the handshake packet the device + * has to send when an LPM token packet is received. + * + * \param response + * type of response to return for an LPM token packet + * Allowed response values: + * - USBFS_LPM_REQ_ACK - next LPM request will be + * responded with ACK + * - USBFS_LPM_REQ_NACK - next LPM request will be + * responded with NACK + * - USBFS_LPM_REQ_NYET - next LPM request will be + * responded with NYET + * + ***************************************************************************/ + void USBFS_Lpm_SetResponse(uint32 response) + { + uint32 lpmCtrl = USBFS_LPM_CTRL_REG & (uint32) ~USBFS_LPM_CTRL_ACK_NYET_MASK; + + USBFS_LPM_CTRL_REG = lpmCtrl | ((uint32) response & USBFS_LPM_CTRL_ACK_NYET_MASK); + } + + + /*************************************************************************** + * Function Name: USBFS_Lpm_GetResponse + ************************************************************************//** + * + * This function returns the currently configured response value that the + * device will send as part of the handshake packet when an LPM token + * packet is received. + * + * \return + * type of handshake response that will be returned by the device + * for an LPM token packet + * Possible response values: + * - USBFS_LPM_REQ_ACK - next LPM request will be responded + * with ACK + * - USBFS_LPM_REQ_NACK - next LPM request will be responded + * with NACK + * - USBFS_LPM_REQ_NYET - next LPM request will be responded + * with NYET + * + ***************************************************************************/ + uint32 USBFS_Lpm_GetResponse(void) + { + + return ((uint32) USBFS_LPM_CTRL_REG & (uint32)USBFS_LPM_CTRL_ACK_NYET_MASK); + } + + +#endif /* (USBFS_LPM_ACTIVE) */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS.h b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS.h new file mode 100644 index 0000000000..945bf8ee3b --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS.h @@ -0,0 +1,2106 @@ +/***************************************************************************//** +* \file USBFS.h +* \version 3.20 +* +* \brief +* This file provides function prototypes and constants for the USBFS component. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_USBFS_USBFS_H) +#define CY_USBFS_USBFS_H + +#include "cydevice_trm.h" +#include "cyfitter.h" +#include "cytypes.h" +#include "CyLib.h" + + +/* User supplied definitions. */ +/* `#START USER_DEFINITIONS` Place your declaration here */ + +/* `#END` */ + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +/* USB IP memory management options. */ +#define USBFS__EP_MANUAL (0u) +#define USBFS__EP_DMAMANUAL (1u) +#define USBFS__EP_DMAAUTO (2u) + +/* USB IP memory allocation options. */ +#define USBFS__MA_STATIC (0u) +#define USBFS__MA_DYNAMIC (1u) + + +/*************************************** +* Initial Parameter Constants +***************************************/ + +#define USBFS_NUM_DEVICES (1u) +#if defined(DAPLINK_IF) +#define USBFS_ENABLE_CDC_CLASS +#endif +#define USBFS_ENABLE_MIDI_CLASS (0u) +#define USBFS_ENABLE_MSC_CLASS (1u) +#define USBFS_BOS_ENABLE (0u) +#define USBFS_ENABLE_DESCRIPTOR_STRINGS +#define USBFS_ENABLE_MSOS_STRING +#define USBFS_ENABLE_SN_STRING +#define USBFS_ENABLE_FWSN_STRING +#define USBFS_ENABLE_STRINGS +#if defined(DAPLINK_IF) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_IN_BUF_SIZE (65u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_NUM_IN_RPTS (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_OUT_BUF_SIZE (65u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_NUM_OUT_RPTS (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_FEATURE_BUF_SIZE (2u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_NUM_FEATURE_RPTS (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_COUNT (1u) +#endif +#define USBFS_ENABLE_HID_CLASS +#define USBFS_HID_RPT_1_SIZE_LSB (0x2Bu) +#define USBFS_HID_RPT_1_SIZE_MSB (0x00u) +#define USBFS_HID_RPT_2_SIZE_LSB (0x21u) +#define USBFS_HID_RPT_2_SIZE_MSB (0x00u) +#define USBFS_MAX_REPORTID_NUMBER (0u) + +#define USBFS_MON_VBUS (1u) +#define USBFS_EXTERN_VBUS (0u) +#define USBFS_POWER_PAD_VBUS (0u) +#define USBFS_EXTERN_VND (0u) +#define USBFS_EXTERN_CLS (0u) +#if defined(DAPLINK_IF) +#define USBFS_MAX_INTERFACES_NUMBER (4u) +#else +#define USBFS_MAX_INTERFACES_NUMBER (1u) +#endif +#define USBFS_EP_MM (0u) +#define USBFS_EP_MA (0u) +#define USBFS_ENABLE_BATT_CHARG_DET (0u) +#define USBFS_GEN_16BITS_EP_ACCESS (0u) + +/* Enable Class APIs: MIDI, CDC, MSC. */ +#define USBFS_ENABLE_CDC_CLASS_API (0u != (1u)) + +/* General parameters */ +#define USBFS_EP_ALLOC_STATIC (USBFS_EP_MA == USBFS__MA_STATIC) +#define USBFS_EP_ALLOC_DYNAMIC (USBFS_EP_MA == USBFS__MA_DYNAMIC) +#define USBFS_EP_MANAGEMENT_MANUAL (USBFS_EP_MM == USBFS__EP_MANUAL) +#define USBFS_EP_MANAGEMENT_DMA (USBFS_EP_MM != USBFS__EP_MANUAL) +#define USBFS_EP_MANAGEMENT_DMA_MANUAL (USBFS_EP_MM == USBFS__EP_DMAMANUAL) +#define USBFS_EP_MANAGEMENT_DMA_AUTO (USBFS_EP_MM == USBFS__EP_DMAAUTO) +#define USBFS_BATT_CHARG_DET_ENABLE (CY_PSOC4 && (0u != USBFS_ENABLE_BATT_CHARG_DET)) +#define USBFS_16BITS_EP_ACCESS_ENABLE (CY_PSOC4 && (0u != USBFS_GEN_16BITS_EP_ACCESS)) +#define USBFS_VBUS_MONITORING_ENABLE (0u != USBFS_MON_VBUS) +#define USBFS_VBUS_MONITORING_INTERNAL (0u == USBFS_EXTERN_VBUS) +#define USBFS_VBUS_POWER_PAD_ENABLE (0u != USBFS_POWER_PAD_VBUS) + +/* Control endpoints availability */ +#define USBFS_SOF_ISR_REMOVE (0u) +#define USBFS_BUS_RESET_ISR_REMOVE (0u) +#define USBFS_EP0_ISR_REMOVE (0u) +#define USBFS_ARB_ISR_REMOVE (0u) +#define USBFS_DP_ISR_REMOVE (0u) +#define USBFS_LPM_REMOVE (1u) +#define USBFS_SOF_ISR_ACTIVE ((0u == USBFS_SOF_ISR_REMOVE) ? 1u: 0u) +#define USBFS_BUS_RESET_ISR_ACTIVE ((0u == USBFS_BUS_RESET_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP0_ISR_ACTIVE ((0u == USBFS_EP0_ISR_REMOVE) ? 1u: 0u) +#define USBFS_ARB_ISR_ACTIVE ((0u == USBFS_ARB_ISR_REMOVE) ? 1u: 0u) +#define USBFS_DP_ISR_ACTIVE ((0u == USBFS_DP_ISR_REMOVE) ? 1u: 0u) +#define USBFS_LPM_ACTIVE ((CY_PSOC4 && (0u == USBFS_LPM_REMOVE)) ? 1u: 0u) + +/* Data endpoints availability */ +#define USBFS_EP1_ISR_REMOVE (0u) +#define USBFS_EP2_ISR_REMOVE (0u) +#if defined(DAPLINK_IF) +#define USBFS_EP3_ISR_REMOVE (0u) +#define USBFS_EP4_ISR_REMOVE (0u) +#define USBFS_EP5_ISR_REMOVE (0u) +#define USBFS_EP6_ISR_REMOVE (0u) +#define USBFS_EP7_ISR_REMOVE (0u) +#else +#define USBFS_EP3_ISR_REMOVE (1u) +#define USBFS_EP4_ISR_REMOVE (1u) +#define USBFS_EP5_ISR_REMOVE (1u) +#define USBFS_EP6_ISR_REMOVE (1u) +#define USBFS_EP7_ISR_REMOVE (1u) +#endif +#define USBFS_EP8_ISR_REMOVE (1u) +#define USBFS_EP1_ISR_ACTIVE ((0u == USBFS_EP1_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP2_ISR_ACTIVE ((0u == USBFS_EP2_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP3_ISR_ACTIVE ((0u == USBFS_EP3_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP4_ISR_ACTIVE ((0u == USBFS_EP4_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP5_ISR_ACTIVE ((0u == USBFS_EP5_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP6_ISR_ACTIVE ((0u == USBFS_EP6_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP7_ISR_ACTIVE ((0u == USBFS_EP7_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP8_ISR_ACTIVE ((0u == USBFS_EP8_ISR_REMOVE) ? 1u: 0u) + +#define USBFS_EP_DMA_AUTO_OPT ((CY_PSOC4) ? (1u) : (0u)) +#define USBFS_DMA1_REMOVE (1u) +#define USBFS_DMA2_REMOVE (1u) +#define USBFS_DMA3_REMOVE (1u) +#define USBFS_DMA4_REMOVE (1u) +#define USBFS_DMA5_REMOVE (1u) +#define USBFS_DMA6_REMOVE (1u) +#define USBFS_DMA7_REMOVE (1u) +#define USBFS_DMA8_REMOVE (1u) +#define USBFS_DMA1_ACTIVE ((0u == USBFS_DMA1_REMOVE) ? 1u: 0u) +#define USBFS_DMA2_ACTIVE ((0u == USBFS_DMA2_REMOVE) ? 1u: 0u) +#define USBFS_DMA3_ACTIVE ((0u == USBFS_DMA3_REMOVE) ? 1u: 0u) +#define USBFS_DMA4_ACTIVE ((0u == USBFS_DMA4_REMOVE) ? 1u: 0u) +#define USBFS_DMA5_ACTIVE ((0u == USBFS_DMA5_REMOVE) ? 1u: 0u) +#define USBFS_DMA6_ACTIVE ((0u == USBFS_DMA6_REMOVE) ? 1u: 0u) +#define USBFS_DMA7_ACTIVE ((0u == USBFS_DMA7_REMOVE) ? 1u: 0u) +#define USBFS_DMA8_ACTIVE ((0u == USBFS_DMA8_REMOVE) ? 1u: 0u) + + +/*************************************** +* Data Structures Definition +***************************************/ + +typedef struct +{ + uint8 attrib; + uint8 apiEpState; + uint8 hwEpState; + uint8 epToggle; + uint8 addr; + uint8 epMode; + uint16 buffOffset; + uint16 bufferSize; + uint8 interface; +} T_USBFS_EP_CTL_BLOCK; + +typedef struct +{ + uint8 interface; + uint8 altSetting; + uint8 addr; + uint8 attributes; + uint16 bufferSize; + uint8 bMisc; +} T_USBFS_EP_SETTINGS_BLOCK; + +typedef struct +{ + uint8 status; + uint16 length; +} T_USBFS_XFER_STATUS_BLOCK; + +typedef struct +{ + uint16 count; + volatile uint8 *pData; + T_USBFS_XFER_STATUS_BLOCK *pStatusBlock; +} T_USBFS_TD; + +typedef struct +{ + uint8 c; + const void *p_list; +} T_USBFS_LUT; + +/* Resume/Suspend API Support */ +typedef struct +{ + uint8 enableState; + uint8 mode; +#if (CY_PSOC4) + uint8 intrSeiMask; +#endif /* (CY_PSOC4) */ +} USBFS_BACKUP_STRUCT; + +/* Number of endpoint 0 data registers. */ +#define USBFS_EP0_DR_MAPPED_REG_CNT (8u) + +/* Structure to access data registers for EP0. */ +typedef struct +{ + uint8 epData[USBFS_EP0_DR_MAPPED_REG_CNT]; +} USBFS_ep0_data_struct; + +/* Number of SIE endpoint registers group. */ +#define USBFS_SIE_EP_REG_SIZE (USBFS_USB__SIE_EP1_CR0 - \ + USBFS_USB__SIE_EP1_CNT0) + +/* Size of gap between SIE endpoint registers groups. */ +#define USBFS_SIE_GAP_CNT (((USBFS_USB__SIE_EP2_CNT0 - \ + (USBFS_USB__SIE_EP1_CNT0 + \ + USBFS_SIE_EP_REG_SIZE)) / sizeof(reg8)) - 1u) + +/* Structure to access to SIE registers for endpoint. */ +typedef struct +{ + uint8 epCnt0; + uint8 epCnt1; + uint8 epCr0; + uint8 gap[USBFS_SIE_GAP_CNT]; +} USBFS_sie_ep_struct; + +/* Number of ARB endpoint registers group. */ +#define USBFS_ARB_EP_REG_SIZE (USBFS_USB__ARB_RW1_DR - \ + USBFS_USB__ARB_EP1_CFG) + +/* Size of gap between ARB endpoint registers groups. */ +#define USBFS_ARB_GAP_CNT (((USBFS_USB__ARB_EP2_CFG - \ + (USBFS_USB__ARB_EP1_CFG + \ + USBFS_ARB_EP_REG_SIZE)) / sizeof(reg8)) - 1u) + +/* Structure to access to ARB registers for endpoint. */ +typedef struct +{ + uint8 epCfg; + uint8 epIntEn; + uint8 epSr; + uint8 reserved; + uint8 rwWa; + uint8 rwWaMsb; + uint8 rwRa; + uint8 rwRaMsb; + uint8 rwDr; + uint8 gap[USBFS_ARB_GAP_CNT]; +} USBFS_arb_ep_struct; + +#if (CY_PSOC4) + /* Number of ARB endpoint registers group (16-bits access). */ + #define USBFS_ARB_EP_REG16_SIZE (USBFS_USB__ARB_RW1_DR16 - \ + USBFS_USB__ARB_RW1_WA16) + + /* Size of gap between ARB endpoint registers groups (16-bits access). */ + #define USBFS_ARB_EP_REG16_GAP_CNT (((USBFS_USB__ARB_RW2_WA16 - \ + (USBFS_USB__ARB_RW1_WA16 + \ + USBFS_ARB_EP_REG16_SIZE)) / sizeof(reg8)) - 1u) + + /* Structure to access to ARB registers for endpoint (16-bits access). */ + typedef struct + { + uint8 rwWa16; + uint8 reserved0; + uint8 rwRa16; + uint8 reserved1; + uint8 rwDr16; + uint8 gap[USBFS_ARB_EP_REG16_GAP_CNT]; + } USBFS_arb_ep_reg16_struct; +#endif /* (CY_PSOC4) */ + +/* Number of endpoint (takes to account that endpoints numbers are 1-8). */ +#define USBFS_NUMBER_EP (9u) + +/* Consoled SIE register groups for endpoints 1-8. */ +typedef struct +{ + USBFS_sie_ep_struct sieEp[USBFS_NUMBER_EP]; +} USBFS_sie_eps_struct; + +/* Consolidate ARB register groups for endpoints 1-8.*/ +typedef struct +{ + USBFS_arb_ep_struct arbEp[USBFS_NUMBER_EP]; +} USBFS_arb_eps_struct; + +#if (CY_PSOC4) + /* Consolidate ARB register groups for endpoints 1-8 (16-bits access). */ + typedef struct + { + USBFS_arb_ep_reg16_struct arbEp[USBFS_NUMBER_EP]; + } USBFS_arb_eps_reg16_struct; +#endif /* (CY_PSOC4) */ + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_general +* @{ +*/ +void USBFS_InitComponent(uint8 device, uint8 mode) ; +void USBFS_Start(uint8 device, uint8 mode) ; +void USBFS_Init(void) ; +void USBFS_Stop(void) ; +uint8 USBFS_GetConfiguration(void) ; +uint8 USBFS_IsConfigurationChanged(void) ; +uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber) ; +uint8 USBFS_GetEPState(uint8 epNumber) ; +uint16 USBFS_GetEPCount(uint8 epNumber) ; +void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length) + ; +uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length) + ; +void USBFS_EnableOutEP(uint8 epNumber) ; +void USBFS_DisableOutEP(uint8 epNumber) ; +void USBFS_Force(uint8 bState) ; +uint8 USBFS_GetEPAckState(uint8 epNumber) ; +void USBFS_SetPowerStatus(uint8 powerStatus) ; +void USBFS_TerminateEP(uint8 epNumber) ; + +uint8 USBFS_GetDeviceAddress(void) ; + +void USBFS_EnableSofInt(void) ; +void USBFS_DisableSofInt(void) ; + + +#if defined(USBFS_ENABLE_FWSN_STRING) + void USBFS_SerialNumString(uint8 snString[]) ; +#endif /* USBFS_ENABLE_FWSN_STRING */ + +#if (USBFS_VBUS_MONITORING_ENABLE) + uint8 USBFS_VBusPresent(void) ; +#endif /* (USBFS_VBUS_MONITORING_ENABLE) */ + +#if (USBFS_16BITS_EP_ACCESS_ENABLE) + /* PSoC4 specific functions for 16-bit data register access. */ + void USBFS_LoadInEP16 (uint8 epNumber, const uint8 pData[], uint16 length); + uint16 USBFS_ReadOutEP16(uint8 epNumber, uint8 pData[], uint16 length); +#endif /* (USBFS_16BITS_EP_ACCESS_ENABLE) */ + +#if (USBFS_BATT_CHARG_DET_ENABLE) + uint8 USBFS_Bcd_DetectPortType(void); +#endif /* (USBFS_BATT_CHARG_DET_ENABLE) */ + +#if (USBFS_EP_MANAGEMENT_DMA) + void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData) ; + void USBFS_Stop_DMA(uint8 epNumber) ; +/** @} general */ +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + +/** +* \addtogroup group_power +* @{ +*/ +uint8 USBFS_CheckActivity(void) ; +void USBFS_Suspend(void) ; +void USBFS_Resume(void) ; +uint8 USBFS_RWUEnabled(void) ; + +#if (USBFS_LPM_ACTIVE) + uint32 USBFS_Lpm_GetBeslValue(void); + uint32 USBFS_Lpm_RemoteWakeUpAllowed(void); + void USBFS_Lpm_SetResponse(uint32 response); + uint32 USBFS_Lpm_GetResponse(void); +#endif /* (USBFS_LPM_ACTIVE) */ + +/** @} power */ + + +#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \ + (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)) +/** +* \addtogroup group_bootloader +* @{ +*/ + void USBFS_CyBtldrCommStart(void) ; + void USBFS_CyBtldrCommStop(void) ; + void USBFS_CyBtldrCommReset(void) ; + cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL + ; + cystatus USBFS_CyBtldrCommRead (uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL + ; +/** @} bootloader */ + + #define USBFS_BTLDR_OUT_EP (0x01u) + #define USBFS_BTLDR_IN_EP (0x02u) + + #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* Endpoint 1 (OUT) buffer size. */ + #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* Endpoint 2 (IN) buffer size. */ + #define USBFS_BTLDR_MAX_PACKET_SIZE USBFS_BTLDR_SIZEOF_WRITE_BUFFER + + #define USBFS_BTLDR_WAIT_1_MS (1u) /* Time Out quantity equal 1mS */ + + /* Map-specific USB bootloader communication functions to common bootloader functions */ + #if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) + #define CyBtldrCommStart USBFS_CyBtldrCommStart + #define CyBtldrCommStop USBFS_CyBtldrCommStop + #define CyBtldrCommReset USBFS_CyBtldrCommReset + #define CyBtldrCommWrite USBFS_CyBtldrCommWrite + #define CyBtldrCommRead USBFS_CyBtldrCommRead + #endif /* (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) */ +#endif /* CYDEV_BOOTLOADER_IO_COMP */ + + +/*************************************** +* API Constants +***************************************/ + +#define USBFS_EP0 (0u) +#define USBFS_EP1 (1u) +#define USBFS_EP2 (2u) +#define USBFS_EP3 (3u) +#define USBFS_EP4 (4u) +#define USBFS_EP5 (5u) +#define USBFS_EP6 (6u) +#define USBFS_EP7 (7u) +#define USBFS_EP8 (8u) +#define USBFS_MAX_EP (9u) + +#define USBFS_TRUE (1u) +#define USBFS_FALSE (0u) + +#define USBFS_NO_EVENT_ALLOWED (2u) +#define USBFS_EVENT_PENDING (1u) +#define USBFS_NO_EVENT_PENDING (0u) + +#define USBFS_IN_BUFFER_FULL USBFS_NO_EVENT_PENDING +#define USBFS_IN_BUFFER_EMPTY USBFS_EVENT_PENDING +#define USBFS_OUT_BUFFER_FULL USBFS_EVENT_PENDING +#define USBFS_OUT_BUFFER_EMPTY USBFS_NO_EVENT_PENDING + +#define USBFS_FORCE_J (0xA0u) +#define USBFS_FORCE_K (0x80u) +#define USBFS_FORCE_SE0 (0xC0u) +#define USBFS_FORCE_NONE (0x00u) + +#define USBFS_IDLE_TIMER_RUNNING (0x02u) +#define USBFS_IDLE_TIMER_EXPIRED (0x01u) +#define USBFS_IDLE_TIMER_INDEFINITE (0x00u) + +#define USBFS_DEVICE_STATUS_BUS_POWERED (0x00u) +#define USBFS_DEVICE_STATUS_SELF_POWERED (0x01u) + +#define USBFS_3V_OPERATION (0x00u) +#define USBFS_5V_OPERATION (0x01u) +#define USBFS_DWR_POWER_OPERATION (0x02u) + +#define USBFS_MODE_DISABLE (0x00u) +#define USBFS_MODE_NAK_IN_OUT (0x01u) +#define USBFS_MODE_STATUS_OUT_ONLY (0x02u) +#define USBFS_MODE_STALL_IN_OUT (0x03u) +#define USBFS_MODE_RESERVED_0100 (0x04u) +#define USBFS_MODE_ISO_OUT (0x05u) +#define USBFS_MODE_STATUS_IN_ONLY (0x06u) +#define USBFS_MODE_ISO_IN (0x07u) +#define USBFS_MODE_NAK_OUT (0x08u) +#define USBFS_MODE_ACK_OUT (0x09u) +#define USBFS_MODE_RESERVED_1010 (0x0Au) +#define USBFS_MODE_ACK_OUT_STATUS_IN (0x0Bu) +#define USBFS_MODE_NAK_IN (0x0Cu) +#define USBFS_MODE_ACK_IN (0x0Du) +#define USBFS_MODE_RESERVED_1110 (0x0Eu) +#define USBFS_MODE_ACK_IN_STATUS_OUT (0x0Fu) +#define USBFS_MODE_MASK (0x0Fu) +#define USBFS_MODE_STALL_DATA_EP (0x80u) + +#define USBFS_MODE_ACKD (0x10u) +#define USBFS_MODE_OUT_RCVD (0x20u) +#define USBFS_MODE_IN_RCVD (0x40u) +#define USBFS_MODE_SETUP_RCVD (0x80u) + +#define USBFS_RQST_TYPE_MASK (0x60u) +#define USBFS_RQST_TYPE_STD (0x00u) +#define USBFS_RQST_TYPE_CLS (0x20u) +#define USBFS_RQST_TYPE_VND (0x40u) +#define USBFS_RQST_DIR_MASK (0x80u) +#define USBFS_RQST_DIR_D2H (0x80u) +#define USBFS_RQST_DIR_H2D (0x00u) +#define USBFS_RQST_RCPT_MASK (0x03u) +#define USBFS_RQST_RCPT_DEV (0x00u) +#define USBFS_RQST_RCPT_IFC (0x01u) +#define USBFS_RQST_RCPT_EP (0x02u) +#define USBFS_RQST_RCPT_OTHER (0x03u) + +#if (USBFS_LPM_ACTIVE) + #define USBFS_LPM_REQ_ACK (0x01u << USBFS_LPM_CTRL_LPM_ACK_RESP_POS) + #define USBFS_LPM_REQ_NACK (0x00u) + #define USBFS_LPM_REQ_NYET (0x01u << USBFS_LPM_CTRL_NYET_EN_POS) +#endif /*(USBFS_LPM_ACTIVE)*/ + +/* USB Class Codes */ +#define USBFS_CLASS_DEVICE (0x00u) /* Use class code info from Interface Descriptors */ +#define USBFS_CLASS_AUDIO (0x01u) /* Audio device */ +#define USBFS_CLASS_CDC (0x02u) /* Communication device class */ +#define USBFS_CLASS_HID (0x03u) /* Human Interface Device */ +#define USBFS_CLASS_PDC (0x05u) /* Physical device class */ +#define USBFS_CLASS_IMAGE (0x06u) /* Still Imaging device */ +#define USBFS_CLASS_PRINTER (0x07u) /* Printer device */ +#define USBFS_CLASS_MSD (0x08u) /* Mass Storage device */ +#define USBFS_CLASS_HUB (0x09u) /* Full/Hi speed Hub */ +#define USBFS_CLASS_CDC_DATA (0x0Au) /* CDC data device */ +#define USBFS_CLASS_SMART_CARD (0x0Bu) /* Smart Card device */ +#define USBFS_CLASS_CSD (0x0Du) /* Content Security device */ +#define USBFS_CLASS_VIDEO (0x0Eu) /* Video device */ +#define USBFS_CLASS_PHD (0x0Fu) /* Personal Health care device */ +#define USBFS_CLASS_WIRELESSD (0xDCu) /* Wireless Controller */ +#define USBFS_CLASS_MIS (0xE0u) /* Miscellaneous */ +#define USBFS_CLASS_APP (0xEFu) /* Application Specific */ +#define USBFS_CLASS_VENDOR (0xFFu) /* Vendor specific */ + +/* Standard Request Types (Table 9-4) */ +#define USBFS_GET_STATUS (0x00u) +#define USBFS_CLEAR_FEATURE (0x01u) +#define USBFS_SET_FEATURE (0x03u) +#define USBFS_SET_ADDRESS (0x05u) +#define USBFS_GET_DESCRIPTOR (0x06u) +#define USBFS_SET_DESCRIPTOR (0x07u) +#define USBFS_GET_CONFIGURATION (0x08u) +#define USBFS_SET_CONFIGURATION (0x09u) +#define USBFS_GET_INTERFACE (0x0Au) +#define USBFS_SET_INTERFACE (0x0Bu) +#define USBFS_SYNCH_FRAME (0x0Cu) + +/* Vendor Specific Request Types */ +/* Request for Microsoft OS String Descriptor */ +#define USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR (0x01u) + +/* Descriptor Types (Table 9-5) */ +#define USBFS_DESCR_DEVICE (1u) +#define USBFS_DESCR_CONFIG (2u) +#define USBFS_DESCR_STRING (3u) +#define USBFS_DESCR_INTERFACE (4u) +#define USBFS_DESCR_ENDPOINT (5u) +#define USBFS_DESCR_DEVICE_QUALIFIER (6u) +#define USBFS_DESCR_OTHER_SPEED (7u) +#define USBFS_DESCR_INTERFACE_POWER (8u) +#if (USBFS_BOS_ENABLE) + #define USBFS_DESCR_BOS (15u) +#endif /* (USBFS_BOS_ENABLE) */ +/* Device Descriptor Defines */ +#define USBFS_DEVICE_DESCR_LENGTH (18u) +#define USBFS_DEVICE_DESCR_SN_SHIFT (16u) + +/* Config Descriptor Shifts and Masks */ +#define USBFS_CONFIG_DESCR_LENGTH (0u) +#define USBFS_CONFIG_DESCR_TYPE (1u) +#define USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW (2u) +#define USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI (3u) +#define USBFS_CONFIG_DESCR_NUM_INTERFACES (4u) +#define USBFS_CONFIG_DESCR_CONFIG_VALUE (5u) +#define USBFS_CONFIG_DESCR_CONFIGURATION (6u) +#define USBFS_CONFIG_DESCR_ATTRIB (7u) +#define USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED (0x40u) +#define USBFS_CONFIG_DESCR_ATTRIB_RWU_EN (0x20u) + +#if (USBFS_BOS_ENABLE) + /* Config Descriptor BOS */ + #define USBFS_BOS_DESCR_LENGTH (0u) + #define USBFS_BOS_DESCR_TYPE (1u) + #define USBFS_BOS_DESCR_TOTAL_LENGTH_LOW (2u) + #define USBFS_BOS_DESCR_TOTAL_LENGTH_HI (3u) + #define USBFS_BOS_DESCR_NUM_DEV_CAPS (4u) +#endif /* (USBFS_BOS_ENABLE) */ + +/* Feature Selectors (Table 9-6) */ +#define USBFS_DEVICE_REMOTE_WAKEUP (0x01u) +#define USBFS_ENDPOINT_HALT (0x00u) +#define USBFS_TEST_MODE (0x02u) + +/* USB Device Status (Figure 9-4) */ +#define USBFS_DEVICE_STATUS_BUS_POWERED (0x00u) +#define USBFS_DEVICE_STATUS_SELF_POWERED (0x01u) +#define USBFS_DEVICE_STATUS_REMOTE_WAKEUP (0x02u) + +/* USB Endpoint Status (Figure 9-4) */ +#define USBFS_ENDPOINT_STATUS_HALT (0x01u) + +/* USB Endpoint Directions */ +#define USBFS_DIR_IN (0x80u) +#define USBFS_DIR_OUT (0x00u) +#define USBFS_DIR_UNUSED (0x7Fu) + +/* USB Endpoint Attributes */ +#define USBFS_EP_TYPE_CTRL (0x00u) +#define USBFS_EP_TYPE_ISOC (0x01u) +#define USBFS_EP_TYPE_BULK (0x02u) +#define USBFS_EP_TYPE_INT (0x03u) +#define USBFS_EP_TYPE_MASK (0x03u) + +#define USBFS_EP_SYNC_TYPE_NO_SYNC (0x00u) +#define USBFS_EP_SYNC_TYPE_ASYNC (0x04u) +#define USBFS_EP_SYNC_TYPE_ADAPTIVE (0x08u) +#define USBFS_EP_SYNC_TYPE_SYNCHRONOUS (0x0Cu) +#define USBFS_EP_SYNC_TYPE_MASK (0x0Cu) + +#define USBFS_EP_USAGE_TYPE_DATA (0x00u) +#define USBFS_EP_USAGE_TYPE_FEEDBACK (0x10u) +#define USBFS_EP_USAGE_TYPE_IMPLICIT (0x20u) +#define USBFS_EP_USAGE_TYPE_RESERVED (0x30u) +#define USBFS_EP_USAGE_TYPE_MASK (0x30u) + +/* Point Status defines */ +#define USBFS_EP_STATUS_LENGTH (0x02u) + +/* Point Device defines */ +#define USBFS_DEVICE_STATUS_LENGTH (0x02u) + +#define USBFS_STATUS_LENGTH_MAX \ + ((USBFS_EP_STATUS_LENGTH > USBFS_DEVICE_STATUS_LENGTH) ? \ + USBFS_EP_STATUS_LENGTH : USBFS_DEVICE_STATUS_LENGTH) + +/* Transfer Completion Notification */ +#define USBFS_XFER_IDLE (0x00u) +#define USBFS_XFER_STATUS_ACK (0x01u) +#define USBFS_XFER_PREMATURE (0x02u) +#define USBFS_XFER_ERROR (0x03u) + +/* Driver State defines */ +#define USBFS_TRANS_STATE_IDLE (0x00u) +#define USBFS_TRANS_STATE_CONTROL_READ (0x02u) +#define USBFS_TRANS_STATE_CONTROL_WRITE (0x04u) +#define USBFS_TRANS_STATE_NO_DATA_CONTROL (0x06u) + +/* String Descriptor defines */ +#define USBFS_STRING_MSOS (0xEEu) +#define USBFS_MSOS_DESCRIPTOR_LENGTH (18u) +#define USBFS_MSOS_CONF_DESCR_LENGTH (40u) + +/* Return values */ +#define USBFS_BCD_PORT_SDP (1u) /* Standard downstream port detected */ +#define USBFS_BCD_PORT_CDP (2u) /* Charging downstream port detected */ +#define USBFS_BCD_PORT_DCP (3u) /* Dedicated charging port detected */ +#define USBFS_BCD_PORT_UNKNOWN (0u) /* Unable to detect charging port */ +#define USBFS_BCD_PORT_ERR (4u) /* Error condition in detection process*/ + + +/* Timeouts for BCD */ +#define USBFS_BCD_TIMEOUT (400u) /* Copied from PBK#163 TIMEOUT (300 ms) */ +#define USBFS_BCD_TDCD_DBNC (10u) /*BCD v1.2: DCD debounce time 10 ms*/ +#define USBFS_BCD_PRIMARY_WAIT (40u) /* Copied from PBK#163 TIMEOUT (40 ms) */ +#define USBFS_BCD_SECONDARY_WAIT (47u) /* Copied from PBK#163 TIMEOUT (40 ms) */ +#define USBFS_BCD_SUSPEND_DISABLE_WAIT (2u) /* Copied from PBK#163 TIMEOUT (2 us) */ + +/* Wait cycles required before clearing SUSPEND_DEL in POWER_CTRL: 2us */ +#define USBFS_WAIT_SUSPEND_DEL_DISABLE (2u) + +/* Wait cycles required for USB regulator stabilization after it is enabled : 50ns */ +#define USBFS_WAIT_VREF_STABILITY (0u) + +#if (CY_PSOC3 || CY_PSOC5LP) +/* Wait cycles required for USB reference restore: 40us */ +#define USBFS_WAIT_VREF_RESTORE (40u) + +/* Wait cycles required for stabilization after register is written : 50ns */ +#define USBFS_WAIT_REG_STABILITY_50NS (0u) +#define USBFS_WAIT_REG_STABILITY_1US (1u) + +/* Wait cycles required after CR0 register write: 1 cycle */ +#define USBFS_WAIT_CR0_REG_STABILITY (1u) + +/* Wait cycles required after PD_PULLUP_N bit is set in PM_USB_CR0: 2us */ +#define USBFS_WAIT_PD_PULLUP_N_ENABLE (2u) +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +#if (CY_PSOC4) + #if (USBFS_EP_MANAGEMENT_DMA) + #define USBFS_DMA_DESCR0 (0u) + #define USBFS_DMA_DESCR1 (1u) + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* BUF_SIZE-BYTES_PER_BURST examples: 0x55 - 32 bytes, 0x44 - 16 bytes, 0x33 - 8 bytes, etc. */ + #define USBFS_DMA_BUF_SIZE (0x55u) + #define USBFS_DMA_BYTES_PER_BURST (32u) + #define USBFS_DMA_HALFWORDS_PER_BURST (16u) + #define USBFS_DMA_BURST_BYTES_MASK (USBFS_DMA_BYTES_PER_BURST - 1u) + + #define USBFS_DMA_DESCR0_MASK (0x00u) + #define USBFS_DMA_DESCR1_MASK (0x80u) + #define USBFS_DMA_DESCR_REVERT (0x40u) + #define USBFS_DMA_DESCR_16BITS (0x20u) + #define USBFS_DMA_DESCR_SHIFT (7u) + + #define USBFS_DMA_GET_DESCR_NUM(desrc) + #define USBFS_DMA_GET_BURST_CNT(dmaBurstCnt) \ + (((dmaBurstCnt) > 2u)? ((dmaBurstCnt) - 2u) : 0u) + + #define USBFS_DMA_GET_MAX_ELEM_PER_BURST(dmaLastBurstEl) \ + ((0u != ((dmaLastBurstEl) & USBFS_DMA_DESCR_16BITS)) ? \ + (USBFS_DMA_HALFWORDS_PER_BURST - 1u) : (USBFS_DMA_BYTES_PER_BURST - 1u)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ +#else + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + #define USBFS_DMA_BYTES_PER_BURST (0u) + #define USBFS_DMA_REQUEST_PER_BURST (0u) + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + #define USBFS_DMA_BYTES_PER_BURST (32u) + #define USBFS_DMA_BYTES_REPEAT (2u) + + /* BUF_SIZE-BYTES_PER_BURST examples: 0x55 - 32 bytes, 0x44 - 16 bytes, 0x33 - 8 bytes, etc. */ + #define USBFS_DMA_BUF_SIZE (0x55u) + #define USBFS_DMA_REQUEST_PER_BURST (1u) + + #define USBFS_EP17_SR_MASK (0x7Fu) + #define USBFS_EP8_SR_MASK (0x03u) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ +#endif /* (CY_PSOC4) */ + +/* DIE ID string descriptor defines */ +#if defined(USBFS_ENABLE_IDSN_STRING) + #define USBFS_IDSN_DESCR_LENGTH (0x22u) +#endif /* (USBFS_ENABLE_IDSN_STRING) */ + + +/*************************************** +* Vars with External Linkage +***************************************/ + +/** +* \addtogroup group_globals +* @{ +*/ +extern uint8 USBFS_initVar; +extern volatile uint8 USBFS_device; +extern volatile uint8 USBFS_transferState; +extern volatile uint8 USBFS_configuration; +extern volatile uint8 USBFS_configurationChanged; +extern volatile uint8 USBFS_deviceStatus; +/** @} globals */ + +/** +* \addtogroup group_hid +* @{ +*/ +/* HID Variables */ +#if defined(USBFS_ENABLE_HID_CLASS) + extern volatile uint8 USBFS_hidProtocol [USBFS_MAX_INTERFACES_NUMBER]; + extern volatile uint8 USBFS_hidIdleRate [USBFS_MAX_INTERFACES_NUMBER]; + extern volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER]; +#endif /* (USBFS_ENABLE_HID_CLASS) */ +/** @} hid */ + + +/*************************************** +* Registers +***************************************/ + +/* Common registers for all PSoCs: 3/4/5LP */ +#define USBFS_ARB_CFG_PTR ( (reg8 *) USBFS_USB__ARB_CFG) +#define USBFS_ARB_CFG_REG (*(reg8 *) USBFS_USB__ARB_CFG) + +#define USBFS_ARB_EP1_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP1_CFG) +#define USBFS_ARB_EP1_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP1_CFG) +#define USBFS_ARB_EP1_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP1_INT_EN) +#define USBFS_ARB_EP1_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP1_INT_EN) +#define USBFS_ARB_EP1_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP1_SR) +#define USBFS_ARB_EP1_SR_REG (*(reg8 *) USBFS_USB__ARB_EP1_SR) +#define USBFS_ARB_EP1_CFG_IND USBFS_USB__ARB_EP1_CFG +#define USBFS_ARB_EP1_INT_EN_IND USBFS_USB__ARB_EP1_INT_EN +#define USBFS_ARB_EP1_SR_IND USBFS_USB__ARB_EP1_SR +#define USBFS_ARB_EP_BASE (*(volatile USBFS_arb_eps_struct CYXDATA *) \ + (USBFS_USB__ARB_EP1_CFG - sizeof(USBFS_arb_ep_struct))) + +#define USBFS_ARB_EP2_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP2_CFG) +#define USBFS_ARB_EP2_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP2_CFG) +#define USBFS_ARB_EP2_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP2_INT_EN) +#define USBFS_ARB_EP2_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP2_INT_EN) +#define USBFS_ARB_EP2_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP2_SR) +#define USBFS_ARB_EP2_SR_REG (*(reg8 *) USBFS_USB__ARB_EP2_SR) + +#define USBFS_ARB_EP3_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP3_CFG) +#define USBFS_ARB_EP3_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP3_CFG) +#define USBFS_ARB_EP3_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP3_INT_EN) +#define USBFS_ARB_EP3_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP3_INT_EN) +#define USBFS_ARB_EP3_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP3_SR) +#define USBFS_ARB_EP3_SR_REG (*(reg8 *) USBFS_USB__ARB_EP3_SR) + +#define USBFS_ARB_EP4_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP4_CFG) +#define USBFS_ARB_EP4_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP4_CFG) +#define USBFS_ARB_EP4_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP4_INT_EN) +#define USBFS_ARB_EP4_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP4_INT_EN) +#define USBFS_ARB_EP4_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP4_SR) +#define USBFS_ARB_EP4_SR_REG (*(reg8 *) USBFS_USB__ARB_EP4_SR) + +#define USBFS_ARB_EP5_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP5_CFG) +#define USBFS_ARB_EP5_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP5_CFG) +#define USBFS_ARB_EP5_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP5_INT_EN) +#define USBFS_ARB_EP5_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP5_INT_EN) +#define USBFS_ARB_EP5_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP5_SR) +#define USBFS_ARB_EP5_SR_REG (*(reg8 *) USBFS_USB__ARB_EP5_SR) + +#define USBFS_ARB_EP6_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP6_CFG) +#define USBFS_ARB_EP6_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP6_CFG) +#define USBFS_ARB_EP6_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP6_INT_EN) +#define USBFS_ARB_EP6_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP6_INT_EN) +#define USBFS_ARB_EP6_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP6_SR) +#define USBFS_ARB_EP6_SR_REG (*(reg8 *) USBFS_USB__ARB_EP6_SR) + +#define USBFS_ARB_EP7_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP7_CFG) +#define USBFS_ARB_EP7_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP7_CFG) +#define USBFS_ARB_EP7_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP7_INT_EN) +#define USBFS_ARB_EP7_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP7_INT_EN) +#define USBFS_ARB_EP7_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP7_SR) +#define USBFS_ARB_EP7_SR_REG (*(reg8 *) USBFS_USB__ARB_EP7_SR) + +#define USBFS_ARB_EP8_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP8_CFG) +#define USBFS_ARB_EP8_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP8_CFG) +#define USBFS_ARB_EP8_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP8_INT_EN) +#define USBFS_ARB_EP8_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP8_INT_EN) +#define USBFS_ARB_EP8_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP8_SR) +#define USBFS_ARB_EP8_SR_REG (*(reg8 *) USBFS_USB__ARB_EP8_SR) + +#define USBFS_ARB_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_INT_EN) +#define USBFS_ARB_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_INT_EN) +#define USBFS_ARB_INT_SR_PTR ( (reg8 *) USBFS_USB__ARB_INT_SR) +#define USBFS_ARB_INT_SR_REG (*(reg8 *) USBFS_USB__ARB_INT_SR) + +#define USBFS_ARB_RW1_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW1_DR) +#define USBFS_ARB_RW1_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW1_RA) + +#define USBFS_ARB_RW1_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW1_RA_MSB) +#define USBFS_ARB_RW1_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW1_WA) +#define USBFS_ARB_RW1_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW1_WA_MSB) +#define USBFS_ARB_RW1_DR_IND USBFS_USB__ARB_RW1_DR +#define USBFS_ARB_RW1_RA_IND USBFS_USB__ARB_RW1_RA +#define USBFS_ARB_RW1_RA_MSB_IND USBFS_USB__ARB_RW1_RA_MSB +#define USBFS_ARB_RW1_WA_IND USBFS_USB__ARB_RW1_WA +#define USBFS_ARB_RW1_WA_MSB_IND USBFS_USB__ARB_RW1_WA_MSB + +#define USBFS_ARB_RW2_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW2_DR) +#define USBFS_ARB_RW2_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW2_RA) +#define USBFS_ARB_RW2_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW2_RA_MSB) +#define USBFS_ARB_RW2_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW2_WA) +#define USBFS_ARB_RW2_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW2_WA_MSB) + +#define USBFS_ARB_RW3_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW3_DR) +#define USBFS_ARB_RW3_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW3_RA) +#define USBFS_ARB_RW3_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW3_RA_MSB) +#define USBFS_ARB_RW3_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW3_WA) +#define USBFS_ARB_RW3_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW3_WA_MSB) + +#define USBFS_ARB_RW4_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW4_DR) +#define USBFS_ARB_RW4_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW4_RA) +#define USBFS_ARB_RW4_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW4_RA_MSB) +#define USBFS_ARB_RW4_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW4_WA) +#define USBFS_ARB_RW4_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW4_WA_MSB) + +#define USBFS_ARB_RW5_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW5_DR) +#define USBFS_ARB_RW5_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW5_RA) +#define USBFS_ARB_RW5_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW5_RA_MSB) +#define USBFS_ARB_RW5_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW5_WA) +#define USBFS_ARB_RW5_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW5_WA_MSB) + +#define USBFS_ARB_RW6_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW6_DR) +#define USBFS_ARB_RW6_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW6_RA) +#define USBFS_ARB_RW6_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW6_RA_MSB) +#define USBFS_ARB_RW6_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW6_WA) +#define USBFS_ARB_RW6_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW6_WA_MSB) + +#define USBFS_ARB_RW7_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW7_DR) +#define USBFS_ARB_RW7_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW7_RA) +#define USBFS_ARB_RW7_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW7_RA_MSB) +#define USBFS_ARB_RW7_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW7_WA) +#define USBFS_ARB_RW7_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW7_WA_MSB) + +#define USBFS_ARB_RW8_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW8_DR) +#define USBFS_ARB_RW8_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW8_RA) +#define USBFS_ARB_RW8_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW8_RA_MSB) +#define USBFS_ARB_RW8_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW8_WA) +#define USBFS_ARB_RW8_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW8_WA_MSB) + +#define USBFS_BUF_SIZE_PTR ( (reg8 *) USBFS_USB__BUF_SIZE) +#define USBFS_BUF_SIZE_REG (*(reg8 *) USBFS_USB__BUF_SIZE) +#define USBFS_BUS_RST_CNT_PTR ( (reg8 *) USBFS_USB__BUS_RST_CNT) +#define USBFS_BUS_RST_CNT_REG (*(reg8 *) USBFS_USB__BUS_RST_CNT) +#define USBFS_CWA_PTR ( (reg8 *) USBFS_USB__CWA) +#define USBFS_CWA_REG (*(reg8 *) USBFS_USB__CWA) +#define USBFS_CWA_MSB_PTR ( (reg8 *) USBFS_USB__CWA_MSB) +#define USBFS_CWA_MSB_REG (*(reg8 *) USBFS_USB__CWA_MSB) +#define USBFS_CR0_PTR ( (reg8 *) USBFS_USB__CR0) +#define USBFS_CR0_REG (*(reg8 *) USBFS_USB__CR0) +#define USBFS_CR1_PTR ( (reg8 *) USBFS_USB__CR1) +#define USBFS_CR1_REG (*(reg8 *) USBFS_USB__CR1) + +#define USBFS_DMA_THRES_PTR ( (reg8 *) USBFS_USB__DMA_THRES) +#define USBFS_DMA_THRES_REG (*(reg8 *) USBFS_USB__DMA_THRES) +#define USBFS_DMA_THRES_MSB_PTR ( (reg8 *) USBFS_USB__DMA_THRES_MSB) +#define USBFS_DMA_THRES_MSB_REG (*(reg8 *) USBFS_USB__DMA_THRES_MSB) + +#define USBFS_EP_ACTIVE_PTR ( (reg8 *) USBFS_USB__EP_ACTIVE) +#define USBFS_EP_ACTIVE_REG (*(reg8 *) USBFS_USB__EP_ACTIVE) +#define USBFS_EP_TYPE_PTR ( (reg8 *) USBFS_USB__EP_TYPE) +#define USBFS_EP_TYPE_REG (*(reg8 *) USBFS_USB__EP_TYPE) + +#define USBFS_EP0_CNT_PTR ( (reg8 *) USBFS_USB__EP0_CNT) +#define USBFS_EP0_CNT_REG (*(reg8 *) USBFS_USB__EP0_CNT) +#define USBFS_EP0_CR_PTR ( (reg8 *) USBFS_USB__EP0_CR) +#define USBFS_EP0_CR_REG (*(reg8 *) USBFS_USB__EP0_CR) +#define USBFS_EP0_DR0_PTR ( (reg8 *) USBFS_USB__EP0_DR0) +#define USBFS_EP0_DR0_REG (*(reg8 *) USBFS_USB__EP0_DR0) +#define USBFS_EP0_DR1_PTR ( (reg8 *) USBFS_USB__EP0_DR1) +#define USBFS_EP0_DR1_REG (*(reg8 *) USBFS_USB__EP0_DR1) +#define USBFS_EP0_DR2_PTR ( (reg8 *) USBFS_USB__EP0_DR2) +#define USBFS_EP0_DR2_REG (*(reg8 *) USBFS_USB__EP0_DR2) +#define USBFS_EP0_DR3_PTR ( (reg8 *) USBFS_USB__EP0_DR3) +#define USBFS_EP0_DR3_REG (*(reg8 *) USBFS_USB__EP0_DR3) +#define USBFS_EP0_DR4_PTR ( (reg8 *) USBFS_USB__EP0_DR4) +#define USBFS_EP0_DR4_REG (*(reg8 *) USBFS_USB__EP0_DR4) +#define USBFS_EP0_DR5_PTR ( (reg8 *) USBFS_USB__EP0_DR5) +#define USBFS_EP0_DR5_REG (*(reg8 *) USBFS_USB__EP0_DR5) +#define USBFS_EP0_DR6_PTR ( (reg8 *) USBFS_USB__EP0_DR6) +#define USBFS_EP0_DR6_REG (*(reg8 *) USBFS_USB__EP0_DR6) +#define USBFS_EP0_DR7_PTR ( (reg8 *) USBFS_USB__EP0_DR7) +#define USBFS_EP0_DR7_REG (*(reg8 *) USBFS_USB__EP0_DR7) +#define USBFS_EP0_DR0_IND USBFS_USB__EP0_DR0 +#define USBFS_EP0_DR_BASE (*(volatile USBFS_ep0_data_struct CYXDATA *) USBFS_USB__EP0_DR0) + +#define USBFS_OSCLK_DR0_PTR ( (reg8 *) USBFS_USB__OSCLK_DR0) +#define USBFS_OSCLK_DR0_REG (*(reg8 *) USBFS_USB__OSCLK_DR0) +#define USBFS_OSCLK_DR1_PTR ( (reg8 *) USBFS_USB__OSCLK_DR1) +#define USBFS_OSCLK_DR1_REG (*(reg8 *) USBFS_USB__OSCLK_DR1) + +#define USBFS_SIE_EP_INT_EN_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_EN) +#define USBFS_SIE_EP_INT_EN_REG (*(reg8 *) USBFS_USB__SIE_EP_INT_EN) +#define USBFS_SIE_EP_INT_SR_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_SR) +#define USBFS_SIE_EP_INT_SR_REG (*(reg8 *) USBFS_USB__SIE_EP_INT_SR) + +#define USBFS_SIE_EP1_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT0) +#define USBFS_SIE_EP1_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP1_CNT0) +#define USBFS_SIE_EP1_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT1) +#define USBFS_SIE_EP1_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP1_CNT1) +#define USBFS_SIE_EP1_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CR0) +#define USBFS_SIE_EP1_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP1_CR0) +#define USBFS_SIE_EP1_CNT1_IND USBFS_USB__SIE_EP1_CNT1 +#define USBFS_SIE_EP1_CNT0_IND USBFS_USB__SIE_EP1_CNT0 +#define USBFS_SIE_EP1_CR0_IND USBFS_USB__SIE_EP1_CR0 +#define USBFS_SIE_EP_BASE (*(volatile USBFS_sie_eps_struct CYXDATA *) \ + (USBFS_USB__SIE_EP1_CNT0 - sizeof(USBFS_sie_ep_struct))) + +#define USBFS_SIE_EP2_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT0) +#define USBFS_SIE_EP2_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP2_CNT0) +#define USBFS_SIE_EP2_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT1) +#define USBFS_SIE_EP2_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP2_CNT1) +#define USBFS_SIE_EP2_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CR0) +#define USBFS_SIE_EP2_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP2_CR0) + +#define USBFS_SIE_EP3_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT0) +#define USBFS_SIE_EP3_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP3_CNT0) +#define USBFS_SIE_EP3_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT1) +#define USBFS_SIE_EP3_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP3_CNT1) +#define USBFS_SIE_EP3_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CR0) +#define USBFS_SIE_EP3_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP3_CR0) + +#define USBFS_SIE_EP4_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT0) +#define USBFS_SIE_EP4_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP4_CNT0) +#define USBFS_SIE_EP4_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT1) +#define USBFS_SIE_EP4_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP4_CNT1) +#define USBFS_SIE_EP4_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CR0) +#define USBFS_SIE_EP4_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP4_CR0) + +#define USBFS_SIE_EP5_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT0) +#define USBFS_SIE_EP5_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP5_CNT0) +#define USBFS_SIE_EP5_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT1) +#define USBFS_SIE_EP5_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP5_CNT1) +#define USBFS_SIE_EP5_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CR0) +#define USBFS_SIE_EP5_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP5_CR0) + +#define USBFS_SIE_EP6_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT0) +#define USBFS_SIE_EP6_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP6_CNT0) +#define USBFS_SIE_EP6_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT1) +#define USBFS_SIE_EP6_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP6_CNT1) +#define USBFS_SIE_EP6_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CR0) +#define USBFS_SIE_EP6_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP6_CR0) + +#define USBFS_SIE_EP7_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT0) +#define USBFS_SIE_EP7_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP7_CNT0) +#define USBFS_SIE_EP7_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT1) +#define USBFS_SIE_EP7_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP7_CNT1) +#define USBFS_SIE_EP7_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CR0) +#define USBFS_SIE_EP7_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP7_CR0) + +#define USBFS_SIE_EP8_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT0) +#define USBFS_SIE_EP8_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP8_CNT0) +#define USBFS_SIE_EP8_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT1) +#define USBFS_SIE_EP8_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP8_CNT1) +#define USBFS_SIE_EP8_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CR0) +#define USBFS_SIE_EP8_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP8_CR0) + +#define USBFS_SOF0_PTR ( (reg8 *) USBFS_USB__SOF0) +#define USBFS_SOF0_REG (*(reg8 *) USBFS_USB__SOF0) +#define USBFS_SOF1_PTR ( (reg8 *) USBFS_USB__SOF1) +#define USBFS_SOF1_REG (*(reg8 *) USBFS_USB__SOF1) + +#define USBFS_USB_CLK_EN_PTR ( (reg8 *) USBFS_USB__USB_CLK_EN) +#define USBFS_USB_CLK_EN_REG (*(reg8 *) USBFS_USB__USB_CLK_EN) + +#define USBFS_USBIO_CR0_PTR ( (reg8 *) USBFS_USB__USBIO_CR0) +#define USBFS_USBIO_CR0_REG (*(reg8 *) USBFS_USB__USBIO_CR0) +#define USBFS_USBIO_CR1_PTR ( (reg8 *) USBFS_USB__USBIO_CR1) +#define USBFS_USBIO_CR1_REG (*(reg8 *) USBFS_USB__USBIO_CR1) + +#define USBFS_DYN_RECONFIG_PTR ( (reg8 *) USBFS_USB__DYN_RECONFIG) +#define USBFS_DYN_RECONFIG_REG (*(reg8 *) USBFS_USB__DYN_RECONFIG) + +#if (CY_PSOC4) + #define USBFS_ARB_RW1_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_RA16) + #define USBFS_ARB_RW1_RA16_REG (*(reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_RA16) + #define USBFS_ARB_RW1_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_WA16) + #define USBFS_ARB_RW1_WA16_REG (*(reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_WA16) + #define USBFS_ARB_RW1_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_DR16) + #define USBFS_ARB_RW1_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_DR16) + #define USBFS_ARB_EP16_BASE (*(volatile USBFS_arb_eps_reg16_struct CYXDATA *) \ + (USBFS_USB__ARB_RW1_WA16 - sizeof(USBFS_arb_ep_reg16_struct))) + + #define USBFS_ARB_RW2_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW2_DR16) + #define USBFS_ARB_RW2_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW2_RA16) + #define USBFS_ARB_RW2_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW2_WA16) + + #define USBFS_ARB_RW3_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW3_DR16) + #define USBFS_ARB_RW3_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW3_RA16) + #define USBFS_ARB_RW3_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW3_WA16) + + #define USBFS_ARB_RW4_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW4_DR16) + #define USBFS_ARB_RW4_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW4_RA16) + #define USBFS_ARB_RW4_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW4_WA16) + + #define USBFS_ARB_RW5_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW5_DR16) + #define USBFS_ARB_RW5_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW5_RA16) + #define USBFS_ARB_RW5_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW5_WA16) + + #define USBFS_ARB_RW6_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW6_DR16) + #define USBFS_ARB_RW6_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW6_RA16) + #define USBFS_ARB_RW6_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW6_WA16) + + #define USBFS_ARB_RW7_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW7_DR16) + #define USBFS_ARB_RW7_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW7_RA16) + #define USBFS_ARB_RW7_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW7_WA16) + + #define USBFS_ARB_RW8_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW8_DR16) + #define USBFS_ARB_RW8_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW8_RA16) + #define USBFS_ARB_RW8_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW8_WA16) + + #define USBFS_OSCLK_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__OSCLK_DR16) + #define USBFS_OSCLK_DR16_REG (*(reg32 *) USBFS_cy_m0s8_usb__OSCLK_DR16) + + #define USBFS_SOF16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__SOF16) + #define USBFS_SOF16_REG (*(reg32 *) USBFS_cy_m0s8_usb__SOF16) + + #define USBFS_CWA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__CWA16) + #define USBFS_CWA16_REG (*(reg32 *) USBFS_cy_m0s8_usb__CWA16) + + #define USBFS_DMA_THRES16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__DMA_THRES16) + #define USBFS_DMA_THRES16_REG (*(reg32 *) USBFS_cy_m0s8_usb__DMA_THRES16) + + #define USBFS_USB_CLK_EN_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_CLK_EN) + #define USBFS_USB_CLK_EN_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_CLK_EN) + + #define USBFS_USBIO_CR2_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USBIO_CR2) + #define USBFS_USBIO_CR2_REG (*(reg32 *) USBFS_cy_m0s8_usb__USBIO_CR2) + + #define USBFS_USB_MEM ( (reg32 *) USBFS_cy_m0s8_usb__MEM_DATA0) + + #define USBFS_POWER_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_POWER_CTRL) + #define USBFS_POWER_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_POWER_CTRL) + + #define USBFS_CHGDET_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_CHGDET_CTRL) + #define USBFS_CHGDET_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_CHGDET_CTRL) + + #define USBFS_USBIO_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_USBIO_CTRL) + #define USBFS_USBIO_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_USBIO_CTRL) + + #define USBFS_FLOW_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_FLOW_CTRL) + #define USBFS_FLOW_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_FLOW_CTRL) + + #define USBFS_LPM_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_LPM_CTRL) + #define USBFS_LPM_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_LPM_CTRL) + + #define USBFS_LPM_STAT_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_LPM_STAT) + #define USBFS_LPM_STAT_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_LPM_STAT) + + #define USBFS_PHY_CONTROL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_PHY_CONTROL) + #define USBFS_PHY_CONTROL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_PHY_CONTROL) + + #define USBFS_INTR_SIE_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE) + #define USBFS_INTR_SIE_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE) + + #define USBFS_INTR_SIE_SET_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_SET) + #define USBFS_INTR_SIE_SET_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_SET) + + #define USBFS_INTR_SIE_MASK_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASK) + #define USBFS_INTR_SIE_MASK_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASK) + + #define USBFS_INTR_SIE_MASKED_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASKED) + #define USBFS_INTR_SIE_MASKED_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASKED) + + #define USBFS_INTR_LVL_SEL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_LVL_SEL) + #define USBFS_INTR_LVL_SEL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_LVL_SEL) + + #define USBFS_INTR_CAUSE_HI_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_HI) + #define USBFS_INTR_CAUSE_HI_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_HI) + + #define USBFS_INTR_CAUSE_LO_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_LO) + #define USBFS_INTR_CAUSE_LO_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_LO) + + #define USBFS_INTR_CAUSE_MED_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_MED) + #define USBFS_INTR_CAUSE_MED_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_MED) + + #define USBFS_DFT_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_DFT_CTRL) + #define USBFS_DFT_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_DFT_CTRL) + + #if (USBFS_VBUS_MONITORING_ENABLE) + #if (USBFS_VBUS_POWER_PAD_ENABLE) + /* Vbus power pad pin is hard wired to P13[2] */ + #define USBFS_VBUS_STATUS_REG (*(reg32 *) CYREG_GPIO_PRT13_PS) + #define USBFS_VBUS_STATUS_PTR ( (reg32 *) CYREG_GPIO_PRT13_PS) + #define USBFS_VBUS_VALID (0x04u) + #else + /* Vbus valid pin is hard wired to P0[0] */ + #define USBFS_VBUS_STATUS_REG (*(reg32 *) CYREG_GPIO_PRT0_PS) + #define USBFS_VBUS_STATUS_PTR ( (reg32 *) CYREG_GPIO_PRT0_PS) + #define USBFS_VBUS_VALID (0x01u) + #endif + #endif /*(USBFS_VBUS_MONITORING_ENABLE) */ + + #define USBFS_BURSTEND_0_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND0_TR_OUTPUT) + #define USBFS_BURSTEND_1_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND1_TR_OUTPUT) + #define USBFS_BURSTEND_2_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND2_TR_OUTPUT) + #define USBFS_BURSTEND_3_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND3_TR_OUTPUT) + #define USBFS_BURSTEND_4_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND4_TR_OUTPUT) + #define USBFS_BURSTEND_5_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND5_TR_OUTPUT) + #define USBFS_BURSTEND_6_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND6_TR_OUTPUT) + #define USBFS_BURSTEND_7_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND7_TR_OUTPUT) + +#else /* (CY_PSOC3 || CY_PSOC5LP) */ + + /* USBFS_PM_USB_CR0 */ + #define USBFS_PM_USB_CR0_PTR ( (reg8 *) CYREG_PM_USB_CR0) + #define USBFS_PM_USB_CR0_REG (*(reg8 *) CYREG_PM_USB_CR0) + + /* USBFS_PM_ACT/STBY_CFG */ + #define USBFS_PM_ACT_CFG_PTR ( (reg8 *) USBFS_USB__PM_ACT_CFG) + #define USBFS_PM_ACT_CFG_REG (*(reg8 *) USBFS_USB__PM_ACT_CFG) + #define USBFS_PM_STBY_CFG_PTR ( (reg8 *) USBFS_USB__PM_STBY_CFG) + #define USBFS_PM_STBY_CFG_REG (*(reg8 *) USBFS_USB__PM_STBY_CFG) + + #if (!CY_PSOC5LP) + #define USBFS_USBIO_CR2_PTR ( (reg8 *) USBFS_USB__USBIO_CR2) + #define USBFS_USBIO_CR2_REG (* (reg8 *) USBFS_USB__USBIO_CR2) + #endif /* (!CY_PSOC5LP) */ + + /* USBFS_USB_MEM - USB IP memory buffer */ + #define USBFS_USB_MEM ((reg8 *) CYDEV_USB_MEM_BASE) + + #if (USBFS_VBUS_MONITORING_ENABLE) + #if (USBFS_VBUS_MONITORING_INTERNAL) + #define USBFS_VBUS_STATUS_REG (*(reg8 *) USBFS_VBUS__PS) + #define USBFS_VBUS_STATUS_PTR ( (reg8 *) USBFS_VBUS__PS) + #define USBFS_VBUS_VALID (USBFS_VBUS__MASK) + #else + #define USBFS_VBUS_STATUS_REG (*(reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG) + #define USBFS_VBUS_STATUS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG) + #define USBFS_VBUS_VALID (USBFS_Vbus_ps_sts_sts_reg__MASK) + #endif /* (USBFS_VBUS_MONITORING_INTERNAL) */ + #endif /*(USBFS_VBUS_MONITORING_ENABLE) */ +#endif /* (CY_PSOC4) */ + + +/*************************************** +* Interrupt source constants +***************************************/ + +#define USBFS_DP_INTC_PRIORITY USBFS_dp_int__INTC_PRIOR_NUM +#define USBFS_DP_INTC_VECT_NUM USBFS_dp_int__INTC_NUMBER + +#if (CY_PSOC4) + #define USBFS_DMA_AUTO_INTR_PRIO (0u) + + #define USBFS_INTR_HI_PRIORITY USBFS_high_int__INTC_PRIOR_NUM + #define USBFS_INTR_HI_VECT_NUM USBFS_high_int__INTC_NUMBER + + #define USBFS_INTR_MED_PRIORITY USBFS_med_int__INTC_PRIOR_NUM + #define USBFS_INTR_MED_VECT_NUM USBFS_med_int__INTC_NUMBER + + #define USBFS_INTR_LO_PRIORITY USBFS_lo_int__INTC_PRIOR_NUM + #define USBFS_INTR_LO_VECT_NUM USBFS_lo_int__INTC_NUMBER + + /* Interrupt sources in USBFS_isrCallbacks[] table */ + #define USBFS_SOF_INTR_NUM (0u) + #define USBFS_BUS_RESET_INT_NUM (1u) + #define USBFS_EP0_INTR_NUM (2u) + #define USBFS_LPM_INTR_NUM (3u) + #define USBFS_ARB_EP_INTR_NUM (4u) + #define USBFS_EP1_INTR_NUM (5u) + #define USBFS_EP2_INTR_NUM (6u) + #define USBFS_EP3_INTR_NUM (7u) + #define USBFS_EP4_INTR_NUM (8u) + #define USBFS_EP5_INTR_NUM (9u) + #define USBFS_EP6_INTR_NUM (10u) + #define USBFS_EP7_INTR_NUM (11u) + #define USBFS_EP8_INTR_NUM (12u) + +#else + #define USBFS_BUS_RESET_PRIOR USBFS_bus_reset__INTC_PRIOR_NUM + #define USBFS_BUS_RESET_MASK USBFS_bus_reset__INTC_MASK + #define USBFS_BUS_RESET_VECT_NUM USBFS_bus_reset__INTC_NUMBER + + #define USBFS_SOF_PRIOR USBFS_sof_int__INTC_PRIOR_NUM + #define USBFS_SOF_MASK USBFS_sof_int__INTC_MASK + #define USBFS_SOF_VECT_NUM USBFS_sof_int__INTC_NUMBER + + #define USBFS_EP_0_PRIOR USBFS_ep_0__INTC_PRIOR_NUM + #define USBFS_EP_0_MASK USBFS_ep_0__INTC_MASK + #define USBFS_EP_0_VECT_NUM USBFS_ep_0__INTC_NUMBER + + #define USBFS_EP_1_PRIOR USBFS_ep_1__INTC_PRIOR_NUM + #define USBFS_EP_1_MASK USBFS_ep_1__INTC_MASK + #define USBFS_EP_1_VECT_NUM USBFS_ep_1__INTC_NUMBER + + #define USBFS_EP_2_PRIOR USBFS_ep_2__INTC_PRIOR_NUM + #define USBFS_EP_2_MASK USBFS_ep_2__INTC_MASK + #define USBFS_EP_2_VECT_NUM USBFS_ep_2__INTC_NUMBER + + #define USBFS_EP_3_PRIOR USBFS_ep_3__INTC_PRIOR_NUM + #define USBFS_EP_3_MASK USBFS_ep_3__INTC_MASK + #define USBFS_EP_3_VECT_NUM USBFS_ep_3__INTC_NUMBER + + #define USBFS_EP_4_PRIOR USBFS_ep_4__INTC_PRIOR_NUM + #define USBFS_EP_4_MASK USBFS_ep_4__INTC_MASK + #define USBFS_EP_4_VECT_NUM USBFS_ep_4__INTC_NUMBER + + #define USBFS_EP_5_PRIOR USBFS_ep_5__INTC_PRIOR_NUM + #define USBFS_EP_5_MASK USBFS_ep_5__INTC_MASK + #define USBFS_EP_5_VECT_NUM USBFS_ep_5__INTC_NUMBER + + #define USBFS_EP_6_PRIOR USBFS_ep_6__INTC_PRIOR_NUM + #define USBFS_EP_6_MASK USBFS_ep_6__INTC_MASK + #define USBFS_EP_6_VECT_NUM USBFS_ep_6__INTC_NUMBER + + #define USBFS_EP_7_PRIOR USBFS_ep_7__INTC_PRIOR_NUM + #define USBFS_EP_7_MASK USBFS_ep_7__INTC_MASK + #define USBFS_EP_7_VECT_NUM USBFS_ep_7__INTC_NUMBER + + #define USBFS_EP_8_PRIOR USBFS_ep_8__INTC_PRIOR_NUM + #define USBFS_EP_8_MASK USBFS_ep_8__INTC_MASK + #define USBFS_EP_8_VECT_NUM USBFS_ep_8__INTC_NUMBER + + /* Set ARB ISR priority 0 to be highest for all EPX ISRs. */ + #define USBFS_ARB_PRIOR (0u) + #define USBFS_ARB_MASK USBFS_arb_int__INTC_MASK + #define USBFS_ARB_VECT_NUM USBFS_arb_int__INTC_NUMBER +#endif /* (CY_PSOC4) */ + + +/*************************************** +* Endpoint 0 offsets (Table 9-2) +***************************************/ +#define USBFS_bmRequestTypeReg USBFS_EP0_DR_BASE.epData[0u] +#define USBFS_bRequestReg USBFS_EP0_DR_BASE.epData[1u] +#define USBFS_wValueLoReg USBFS_EP0_DR_BASE.epData[2u] +#define USBFS_wValueHiReg USBFS_EP0_DR_BASE.epData[3u] +#define USBFS_wIndexLoReg USBFS_EP0_DR_BASE.epData[4u] +#define USBFS_wIndexHiReg USBFS_EP0_DR_BASE.epData[5u] +#define USBFS_wLengthLoReg USBFS_EP0_DR_BASE.epData[6u] +#define USBFS_wLengthHiReg USBFS_EP0_DR_BASE.epData[7u] + +/* Compatibility defines */ +#define USBFS_lengthLoReg USBFS_EP0_DR_BASE.epData[6u] +#define USBFS_lengthHiReg USBFS_EP0_DR_BASE.epData[7u] + + +/*************************************** +* Register Constants +***************************************/ + +#define USBFS_3500MV (3500u) +#if (CY_PSOC4) + #define USBFS_VDDD_MV (CYDEV_VBUS_MV) +#else + #define USBFS_VDDD_MV (CYDEV_VDDD_MV) +#endif /* (CY_PSOC4) */ + + +/* USBFS_USB_CLK */ +#define USBFS_USB_CLK_CSR_CLK_EN_POS (0u) +#define USBFS_USB_CLK_CSR_CLK_EN ((uint8) ((uint8) 0x1u << USBFS_USB_CLK_CSR_CLK_EN_POS)) +#define USBFS_USB_CLK_ENABLE (USBFS_USB_CLK_CSR_CLK_EN) + +/* USBFS_CR0 */ +#define USBFS_CR0_DEVICE_ADDRESS_POS (0u) +#define USBFS_CR0_ENABLE_POS (7u) +#define USBFS_CR0_DEVICE_ADDRESS_MASK ((uint8) ((uint8) 0x7Fu << USBFS_CR0_DEVICE_ADDRESS_POS)) +#define USBFS_CR0_ENABLE ((uint8) ((uint8) 0x01u << USBFS_CR0_ENABLE_POS)) + + +/* USBFS_CR1 */ +#define USBFS_CR1_REG_ENABLE_POS (0u) +#define USBFS_CR1_ENABLE_LOCK_POS (1u) +#define USBFS_CR1_BUS_ACTIVITY_POS (2u) +#define USBFS_CR1_TRIM_OFFSET_MSB_POS (3u) +#define USBFS_CR1_REG_ENABLE ((uint8) ((uint8) 0x1u << USBFS_CR1_REG_ENABLE_POS)) +#define USBFS_CR1_ENABLE_LOCK ((uint8) ((uint8) 0x1u << USBFS_CR1_ENABLE_LOCK_POS)) +#define USBFS_CR1_BUS_ACTIVITY ((uint8) ((uint8) 0x1u << USBFS_CR1_BUS_ACTIVITY_POS)) +#define USBFS_CR1_TRIM_OFFSET_MSB ((uint8) ((uint8) 0x1u << USBFS_CR1_TRIM_OFFSET_MSB_POS)) + +/* USBFS_EPX_CNT */ +#define USBFS_EP0_CNT_DATA_TOGGLE (0x80u) +#define USBFS_EPX_CNT_DATA_TOGGLE (0x80u) +#define USBFS_EPX_CNT0_MASK (0x0Fu) +#define USBFS_EPX_CNTX_MSB_MASK (0x07u) +#define USBFS_EPX_CNTX_ADDR_SHIFT (0x04u) +#define USBFS_EPX_CNTX_ADDR_OFFSET (0x10u) +#define USBFS_EPX_CNTX_CRC_COUNT (0x02u) +#define USBFS_EPX_DATA_BUF_MAX (512u) + +/* USBFS_USBIO_CR0 */ + +#define USBFS_USBIO_CR0_TEN (0x80u) +#define USBFS_USBIO_CR0_TSE0 (0x40u) +#define USBFS_USBIO_CR0_TD (0x20u) +#define USBFS_USBIO_CR0_RD (0x01u) + +/* USBFS_USBIO_CR1 */ +#define USBFS_USBIO_CR1_DM0_POS (0u) +#define USBFS_USBIO_CR1_DP0_POS (1u) +#define USBFS_USBIO_CR1_USBPUEN_POS (2u) +#define USBFS_USBIO_CR1_IOMODE_POS (5u) +#define USBFS_USBIO_CR1_DM0 ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_DM0_POS)) +#define USBFS_USBIO_CR1_DP0 ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_DP0_POS)) +#define USBFS_USBIO_CR1_USBPUEN ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_USBPUEN_POS)) +#define USBFS_USBIO_CR1_IOMODE ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_IOMODE_POS)) + +/* USBFS_FASTCLK_IMO_CR */ +#define USBFS_FASTCLK_IMO_CR_USBCLK_ON (0x40u) +#define USBFS_FASTCLK_IMO_CR_XCLKEN (0x20u) +#define USBFS_FASTCLK_IMO_CR_FX2ON (0x10u) + +/* USBFS_ARB_EPX_CFG */ +#define USBFS_ARB_EPX_CFG_IN_DATA_RDY_POS (0u) +#define USBFS_ARB_EPX_CFG_DMA_REQ_POS (1u) +#define USBFS_ARB_EPX_CFG_CRC_BYPASS_POS (2u) +#define USBFS_ARB_EPX_CFG_RESET_POS (3u) +#define USBFS_ARB_EPX_CFG_IN_DATA_RDY ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_IN_DATA_RDY_POS)) +#define USBFS_ARB_EPX_CFG_DMA_REQ ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_DMA_REQ_POS)) +#define USBFS_ARB_EPX_CFG_CRC_BYPASS ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_CRC_BYPASS_POS)) +#define USBFS_ARB_EPX_CFG_RESET ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_RESET_POS)) + +/* USBFS_ARB_EPX_INT / SR */ +#define USBFS_ARB_EPX_INT_IN_BUF_FULL_POS (0u) +#define USBFS_ARB_EPX_INT_DMA_GNT_POS (1u) +#define USBFS_ARB_EPX_INT_BUF_OVER_POS (2u) +#define USBFS_ARB_EPX_INT_BUF_UNDER_POS (3u) +#define USBFS_ARB_EPX_INT_ERR_INT_POS (4u) +#define USBFS_ARB_EPX_INT_IN_BUF_FULL ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_IN_BUF_FULL_POS)) +#define USBFS_ARB_EPX_INT_DMA_GNT ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_DMA_GNT_POS)) +#define USBFS_ARB_EPX_INT_BUF_OVER ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_BUF_OVER_POS)) +#define USBFS_ARB_EPX_INT_BUF_UNDER ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_BUF_UNDER_POS)) +#define USBFS_ARB_EPX_INT_ERR_INT ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_ERR_INT_POS)) + +#if (CY_PSOC4) +#define USBFS_ARB_EPX_INT_DMA_TERMIN_POS (5u) +#define USBFS_ARB_EPX_INT_DMA_TERMIN ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_DMA_TERMIN_POS)) +#endif /* (CY_PSOC4) */ + +/* Common arbiter interrupt sources for all PSoC devices. */ +#define USBFS_ARB_EPX_INT_COMMON (USBFS_ARB_EPX_INT_IN_BUF_FULL | \ + USBFS_ARB_EPX_INT_DMA_GNT | \ + USBFS_ARB_EPX_INT_BUF_OVER | \ + USBFS_ARB_EPX_INT_BUF_UNDER | \ + USBFS_ARB_EPX_INT_ERR_INT) + +#if (CY_PSOC4) + #define USBFS_ARB_EPX_INT_ALL (USBFS_ARB_EPX_INT_COMMON | USBFS_ARB_EPX_INT_DMA_TERMIN) +#else + #define USBFS_ARB_EPX_INT_ALL (USBFS_ARB_EPX_INT_COMMON) +#endif /* (CY_PSOC4) */ + +/* USBFS_ARB_CFG */ +#define USBFS_ARB_CFG_AUTO_MEM_POS (4u) +#define USBFS_ARB_CFG_DMA_CFG_POS (5u) +#define USBFS_ARB_CFG_CFG_CMP_POS (7u) +#define USBFS_ARB_CFG_AUTO_MEM ((uint8) ((uint8) 0x1u << USBFS_ARB_CFG_AUTO_MEM_POS)) +#define USBFS_ARB_CFG_DMA_CFG_MASK ((uint8) ((uint8) 0x3u << USBFS_ARB_CFG_DMA_CFG_POS)) +#define USBFS_ARB_CFG_DMA_CFG_NONE ((uint8) ((uint8) 0x0u << USBFS_ARB_CFG_DMA_CFG_POS)) +#define USBFS_ARB_CFG_DMA_CFG_MANUAL ((uint8) ((uint8) 0x1u << USBFS_ARB_CFG_DMA_CFG_POS)) +#define USBFS_ARB_CFG_DMA_CFG_AUTO ((uint8) ((uint8) 0x2u << USBFS_ARB_CFG_DMA_CFG_POS)) +#define USBFS_ARB_CFG_CFG_CMP ((uint8) ((uint8) 0x1u << USBFS_ARB_CFG_CFG_CMP_POS)) + +/* USBFS_DYN_RECONFIG */ +#define USBFS_DYN_RECONFIG_EP_SHIFT (1u) +#define USBFS_DYN_RECONFIG_ENABLE_POS (0u) +#define USBFS_DYN_RECONFIG_EPNO_POS (1u) +#define USBFS_DYN_RECONFIG_RDY_STS_POS (4u) +#define USBFS_DYN_RECONFIG_ENABLE ((uint8) ((uint8) 0x1u << USBFS_DYN_RECONFIG_ENABLE_POS)) +#define USBFS_DYN_RECONFIG_EPNO_MASK ((uint8) ((uint8) 0x7u << USBFS_DYN_RECONFIG_EPNO_POS)) +#define USBFS_DYN_RECONFIG_RDY_STS ((uint8) ((uint8) 0x1u << USBFS_DYN_RECONFIG_RDY_STS_POS)) + +/* USBFS_ARB_INT */ +#define USBFS_ARB_INT_EP1_INTR_POS (0u) /* [0] Interrupt for USB EP1 */ +#define USBFS_ARB_INT_EP2_INTR_POS (1u) /* [1] Interrupt for USB EP2 */ +#define USBFS_ARB_INT_EP3_INTR_POS (2u) /* [2] Interrupt for USB EP3 */ +#define USBFS_ARB_INT_EP4_INTR_POS (3u) /* [3] Interrupt for USB EP4 */ +#define USBFS_ARB_INT_EP5_INTR_POS (4u) /* [4] Interrupt for USB EP5 */ +#define USBFS_ARB_INT_EP6_INTR_POS (5u) /* [5] Interrupt for USB EP6 */ +#define USBFS_ARB_INT_EP7_INTR_POS (6u) /* [6] Interrupt for USB EP7 */ +#define USBFS_ARB_INT_EP8_INTR_POS (7u) /* [7] Interrupt for USB EP8 */ +#define USBFS_ARB_INT_EP1_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP1_INTR_POS)) +#define USBFS_ARB_INT_EP2_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP2_INTR_POS)) +#define USBFS_ARB_INT_EP3_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP3_INTR_POS)) +#define USBFS_ARB_INT_EP4_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP4_INTR_POS)) +#define USBFS_ARB_INT_EP5_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP5_INTR_POS)) +#define USBFS_ARB_INT_EP6_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP6_INTR_POS)) +#define USBFS_ARB_INT_EP7_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP7_INTR_POS)) +#define USBFS_ARB_INT_EP8_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP8_INTR_POS)) + +/* USBFS_SIE_INT */ +#define USBFS_SIE_INT_EP1_INTR_POS (0u) /* [0] Interrupt for USB EP1 */ +#define USBFS_SIE_INT_EP2_INTR_POS (1u) /* [1] Interrupt for USB EP2 */ +#define USBFS_SIE_INT_EP3_INTR_POS (2u) /* [2] Interrupt for USB EP3 */ +#define USBFS_SIE_INT_EP4_INTR_POS (3u) /* [3] Interrupt for USB EP4 */ +#define USBFS_SIE_INT_EP5_INTR_POS (4u) /* [4] Interrupt for USB EP5 */ +#define USBFS_SIE_INT_EP6_INTR_POS (5u) /* [5] Interrupt for USB EP6 */ +#define USBFS_SIE_INT_EP7_INTR_POS (6u) /* [6] Interrupt for USB EP7 */ +#define USBFS_SIE_INT_EP8_INTR_POS (7u) /* [7] Interrupt for USB EP8 */ +#define USBFS_SIE_INT_EP1_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP1_INTR_POS)) +#define USBFS_SIE_INT_EP2_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP2_INTR_POS)) +#define USBFS_SIE_INT_EP3_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP3_INTR_POS)) +#define USBFS_SIE_INT_EP4_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP4_INTR_POS)) +#define USBFS_SIE_INT_EP5_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP5_INTR_POS)) +#define USBFS_SIE_INT_EP6_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP6_INTR_POS)) +#define USBFS_SIE_INT_EP7_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP7_INTR_POS)) +#define USBFS_SIE_INT_EP8_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP8_INTR_POS)) + +#if (CY_PSOC4) + /* USBFS_POWER_CTRL_REG */ + #define USBFS_POWER_CTRL_VBUS_VALID_OVR_POS (0u) /* [0] */ + #define USBFS_POWER_CTRL_SUSPEND_POS (2u) /* [1] */ + #define USBFS_POWER_CTRL_SUSPEND_DEL_POS (3u) /* [3] */ + #define USBFS_POWER_CTRL_ISOLATE_POS (4u) /* [4] */ + #define USBFS_POWER_CTRL_CHDET_PWR_CTL_POS (5u) /* [5] */ + #define USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN_POS (25u) /* [25] */ + #define USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN_POS (26u) /* [26] */ + #define USBFS_POWER_CTRL_ENABLE_RCVR_POS (27u) /* [27] */ + #define USBFS_POWER_CTRL_ENABLE_DPO_POS (28u) /* [28] */ + #define USBFS_POWER_CTRL_ENABLE_DMO_POS (29u) /* [29] */ + #define USBFS_POWER_CTRL_ENABLE_CHGDET_POS (30u) /* [30] */ + #define USBFS_POWER_CTRL_ENABLE_POS (31u) /* [31] */ + #define USBFS_POWER_CTRL_VBUS_VALID_OVR_MASK ((uint32) 0x03u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS) + #define USBFS_POWER_CTRL_VBUS_VALID_OVR_0 ((uint32) 0x00u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS) + #define USBFS_POWER_CTRL_VBUS_VALID_OVR_1 ((uint32) 0x01u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS) + #define USBFS_POWER_CTRL_VBUS_VALID_OVR_GPIO ((uint32) 0x02u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS) + #define USBFS_POWER_CTRL_VBUS_VALID_OVR_PHY ((uint32) 0x03u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS) + #define USBFS_POWER_CTRL_SUSPEND ((uint32) 0x01u << USBFS_POWER_CTRL_SUSPEND_POS) + #define USBFS_POWER_CTRL_SUSPEND_DEL ((uint32) 0x01u << USBFS_POWER_CTRL_SUSPEND_DEL_POS) + #define USBFS_POWER_CTRL_ISOLATE ((uint32) 0x01u << USBFS_POWER_CTRL_ISOLATE_POS) + #define USBFS_POWER_CTRL_CHDET_PWR_CTL_MASK ((uint32) 0x03u << USBFS_POWER_CTRL_CHDET_PWR_CTL_POS) + #define USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN_POS) + #define USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN_POS) + #define USBFS_POWER_CTRL_ENABLE_RCVR ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_RCVR_POS) + #define USBFS_POWER_CTRL_ENABLE_DPO ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_DPO_POS) + #define USBFS_POWER_CTRL_ENABLE_DMO ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_DMO_POS) + #define USBFS_POWER_CTRL_ENABLE_CHGDET ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_CHGDET_POS) + #define USBFS_POWER_CTRL_ENABLE ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_POS) + + /* USBFS_CHGDET_CTRL_REG */ + #define USBFS_CHGDET_CTRL_COMP_DP_POS (0u) /* [0] */ + #define USBFS_CHGDET_CTRL_COMP_DM_POS (1u) /* [1] */ + #define USBFS_CHGDET_CTRL_COMP_EN_POS (2u) /* [2] */ + #define USBFS_CHGDET_CTRL_REF_DP_POS (3u) /* [3] */ + #define USBFS_CHGDET_CTRL_REF_DM_POS (4u) /* [4] */ + #define USBFS_CHGDET_CTRL_REF_EN_POS (5u) /* [5] */ + #define USBFS_CHGDET_CTRL_DCD_SRC_EN_POS (6u) /* [6] */ + #define USBFS_CHGDET_CTRL_ADFT_CTRL_POS (12u) /* [12] */ + #define USBFS_CHGDET_CTRL_COMP_OUT_POS (31u) /* [31] */ + #define USBFS_CHGDET_CTRL_COMP_DP ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_DP_POS) + #define USBFS_CHGDET_CTRL_COMP_DM ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_DM_POS) + #define USBFS_CHGDET_CTRL_COMP_EN ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_EN_POS) + #define USBFS_CHGDET_CTRL_REF_DP ((uint32) 0x01u << USBFS_CHGDET_CTRL_REF_DP_POS) + #define USBFS_CHGDET_CTRL_REF_DM ((uint32) 0x01u << USBFS_CHGDET_CTRL_REF_DM_POS) + #define USBFS_CHGDET_CTRL_REF_EN ((uint32) 0x01u << USBFS_CHGDET_CTRL_REF_EN_POS) + #define USBFS_CHGDET_CTRL_DCD_SRC_EN ((uint32) 0x01u << USBFS_CHGDET_CTRL_DCD_SRC_EN_POS) + #define USBFS_CHGDET_CTRL_ADFT_CTRL_MASK ((uint32) 0x03u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS) + #define USBFS_CHGDET_CTRL_ADFT_CTRL_NORMAL ((uint32) 0x00u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS) + #define USBFS_CHGDET_CTRL_ADFT_CTRL_VBG ((uint32) 0x01u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS) + #define USBFS_CHGDET_CTRL_ADFT_CTRL_DONTUSE ((uint32) 0x02u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS) + #define USBFS_CHGDET_CTRL_ADFT_CTRL_ADFTIN ((uint32) 0x03u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS) + #define USBFS_CHGDET_CTRL_COMP_OUT ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_OUT_POS) + + /* USBFS_LPM_CTRL */ + #define USBFS_LPM_CTRL_LPM_EN_POS (0u) + #define USBFS_LPM_CTRL_LPM_ACK_RESP_POS (1u) + #define USBFS_LPM_CTRL_NYET_EN_POS (2u) + #define USBFS_LPM_CTRL_SUB_RESP_POS (4u) + #define USBFS_LPM_CTRL_LPM_EN ((uint32) 0x01u << USBFS_LPM_CTRL_LPM_EN_POS) + #define USBFS_LPM_CTRL_LPM_ACK_RESP ((uint32) 0x01u << USBFS_LPM_CTRL_LPM_ACK_RESP_POS) + #define USBFS_LPM_CTRL_NYET_EN ((uint32) 0x01u << USBFS_LPM_CTRL_NYET_EN_POS) + #define USBFS_LPM_CTRL_ACK_NYET_MASK ((uint32) 0x03u << USBFS_LPM_CTRL_LPM_ACK_RESP_POS) + #define USBFS_LPM_CTRL_SUB_RESP ((uint32) 0x01u << USBFS_LPM_CTRL_SUB_RESP_POS) + + #define USBFS_LPM_STAT_LPM_BESL_POS (0u) + #define USBFS_LPM_STAT_LPM_REMOTE_WAKE_POS (4u) + #define USBFS_LPM_STAT_LPM_BESL_MASK ((uint32) 0x0Fu << USBFS_LPM_STAT_LPM_BESL_POS) + #define USBFS_LPM_STAT_LPM_REMOTE_WAKE ((uint32) 0x01u << USBFS_LPM_STAT_LPM_REMOTE_WAKE_POS) + + /* USBFS_INTR_SIE */ + #define USBFS_INTR_SIE_SOF_INTR_POS (0u) /* [0] Interrupt for USB SOF */ + #define USBFS_INTR_SIE_BUS_RESET_INTR_POS (1u) /* [1] Interrupt for BUS RESET */ + #define USBFS_INTR_SIE_EP0_INTR_POS (2u) /* [2] Interrupt for EP0 */ + #define USBFS_INTR_SIE_LPM_INTR_POS (3u) /* [3] Interrupt for LPM */ + #define USBFS_INTR_SIE_RESUME_INTR_POS (4u) /* [4] Interrupt for RESUME (not used by component) */ + #define USBFS_INTR_SIE_SOF_INTR ((uint32) 0x01u << USBFS_INTR_SIE_SOF_INTR_POS) + #define USBFS_INTR_SIE_BUS_RESET_INTR ((uint32) 0x01u << USBFS_INTR_SIE_BUS_RESET_INTR_POS) + #define USBFS_INTR_SIE_EP0_INTR ((uint32) 0x01u << USBFS_INTR_SIE_EP0_INTR_POS) + #define USBFS_INTR_SIE_LPM_INTR ((uint32) 0x01u << USBFS_INTR_SIE_LPM_INTR_POS) + #define USBFS_INTR_SIE_RESUME_INTR ((uint32) 0x01u << USBFS_INTR_SIE_RESUME_INTR_POS) + + /* USBFS_INTR_CAUSE_LO, MED and HI */ + #define USBFS_INTR_CAUSE_SOF_INTR_POS (0u) /* [0] Interrupt status for USB SOF */ + #define USBFS_INTR_CAUSE_BUS_RESET_INTR_POS (1u) /* [1] Interrupt status for USB BUS RSET */ + #define USBFS_INTR_CAUSE_EP0_INTR_POS (2u) /* [2] Interrupt status for USB EP0 */ + #define USBFS_INTR_CAUSE_LPM_INTR_POS (3u) /* [3] Interrupt status for USB LPM */ + #define USBFS_INTR_CAUSE_RESUME_INTR_POS (4u) /* [4] Interrupt status for USB RESUME */ + #define USBFS_INTR_CAUSE_ARB_INTR_POS (7u) /* [7] Interrupt status for USB ARB */ + #define USBFS_INTR_CAUSE_EP1_INTR_POS (8u) /* [8] Interrupt status for USB EP1 */ + #define USBFS_INTR_CAUSE_EP2_INTR_POS (9u) /* [9] Interrupt status for USB EP2 */ + #define USBFS_INTR_CAUSE_EP3_INTR_POS (10u) /* [10] Interrupt status for USB EP3 */ + #define USBFS_INTR_CAUSE_EP4_INTR_POS (11u) /* [11] Interrupt status for USB EP4 */ + #define USBFS_INTR_CAUSE_EP5_INTR_POS (12u) /* [12] Interrupt status for USB EP5 */ + #define USBFS_INTR_CAUSE_EP6_INTR_POS (13u) /* [13] Interrupt status for USB EP6 */ + #define USBFS_INTR_CAUSE_EP7_INTR_POS (14u) /* [14] Interrupt status for USB EP7 */ + #define USBFS_INTR_CAUSE_EP8_INTR_POS (15u) /* [15] Interrupt status for USB EP8 */ + #define USBFS_INTR_CAUSE_SOF_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_SOF_INTR_POS) + #define USBFS_INTR_CAUSE_BUS_RESET_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_BUS_RESET_INTR_POS) + #define USBFS_INTR_CAUSE_EP0_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP0_INTR_POS) + #define USBFS_INTR_CAUSE_LPM_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_LPM_INTR_POS) + #define USBFS_INTR_CAUSE_RESUME_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_RESUME_INTR_POS) + #define USBFS_INTR_CAUSE_ARB_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_ARB_INTR_POS) + #define USBFS_INTR_CAUSE_EP1_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP1_INTR_POS) + #define USBFS_INTR_CAUSE_EP2_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP2_INTR_POS) + #define USBFS_INTR_CAUSE_EP3_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP3_INTR_POS) + #define USBFS_INTR_CAUSE_EP4_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP4_INTR_POS) + #define USBFS_INTR_CAUSE_EP5_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP5_INTR_POS) + #define USBFS_INTR_CAUSE_EP6_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP6_INTR_POS) + #define USBFS_INTR_CAUSE_EP7_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP7_INTR_POS) + #define USBFS_INTR_CAUSE_EP8_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP8_INTR_POS) + + #define USBFS_INTR_CAUSE_CTRL_INTR_MASK (USBFS_INTR_CAUSE_SOF_INTR | \ + USBFS_INTR_CAUSE_BUS_RESET_INTR | \ + USBFS_INTR_CAUSE_EP0_INTR | \ + USBFS_INTR_CAUSE_LPM_INTR) + + #define USBFS_INTR_CAUSE_EP1_8_INTR_MASK (USBFS_INTR_CAUSE_EP1_INTR | \ + USBFS_INTR_CAUSE_EP2_INTR | \ + USBFS_INTR_CAUSE_EP3_INTR | \ + USBFS_INTR_CAUSE_EP4_INTR | \ + USBFS_INTR_CAUSE_EP5_INTR | \ + USBFS_INTR_CAUSE_EP6_INTR | \ + USBFS_INTR_CAUSE_EP7_INTR | \ + USBFS_INTR_CAUSE_EP8_INTR) + + #define USBFS_INTR_CAUSE_EP_INTR_SHIFT (USBFS_INTR_CAUSE_ARB_INTR_POS - \ + (USBFS_INTR_CAUSE_LPM_INTR_POS + 1u)) + #define USBFS_INTR_CAUSE_SRC_COUNT (13u) + + #define USBFS_CHGDET_CTRL_PRIMARY (USBFS_CHGDET_CTRL_COMP_EN | \ + USBFS_CHGDET_CTRL_COMP_DM | \ + USBFS_CHGDET_CTRL_REF_EN | \ + USBFS_CHGDET_CTRL_REF_DP) + + #define USBFS_CHGDET_CTRL_SECONDARY (USBFS_CHGDET_CTRL_COMP_EN | \ + USBFS_CHGDET_CTRL_COMP_DP | \ + USBFS_CHGDET_CTRL_REF_EN | \ + USBFS_CHGDET_CTRL_REF_DM) + + #define USBFS_CHGDET_CTRL_DEFAULT (0x00000900u) + + +#else /* (CY_PSOC3 || CY_PSOC5LP) */ + #define USBFS_PM_ACT_EN_FSUSB USBFS_USB__PM_ACT_MSK + #define USBFS_PM_STBY_EN_FSUSB USBFS_USB__PM_STBY_MSK + #define USBFS_PM_AVAIL_EN_FSUSBIO (0x10u) + + #define USBFS_PM_USB_CR0_REF_EN (0x01u) + #define USBFS_PM_USB_CR0_PD_N (0x02u) + #define USBFS_PM_USB_CR0_PD_PULLUP_N (0x04u) +#endif /* (CY_PSOC4) */ + + +/*************************************** +* Macros Definitions +***************************************/ + +#if (CY_PSOC4) + #define USBFS_ClearSieInterruptSource(intMask) \ + do{ \ + USBFS_INTR_SIE_REG = (uint32) (intMask); \ + }while(0) +#else + #define USBFS_ClearSieInterruptSource(intMask) \ + do{ /* Does nothing. */ }while(0) +#endif /* (CY_PSOC4) */ + +#define USBFS_ClearSieEpInterruptSource(intMask) \ + do{ \ + USBFS_SIE_EP_INT_SR_REG = (uint8) (intMask); \ + }while(0) + +#define USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType) (((epType) == USBFS_EP_TYPE_ISOC) ? \ + (USBFS_MODE_ISO_IN) : (USBFS_MODE_ACK_IN)) + +#define USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType) (((epType) == USBFS_EP_TYPE_ISOC) ? \ + (USBFS_MODE_ISO_OUT) : (USBFS_MODE_ACK_OUT)) + +#define USBFS_GET_EP_TYPE(epNumber) (USBFS_EP[epNumber].attrib & USBFS_EP_TYPE_MASK) + +#define USBFS_GET_UINT16(hi, low) (((uint16) ((uint16) (hi) << 8u)) | ((uint16) (low) & 0xFFu)) + + +/*************************************** +* Initialization Register Settings +***************************************/ + +/* Clear device address and enable USB IP respond to USB traffic. */ +#define USBFS_DEFUALT_CR0 (USBFS_CR0_ENABLE) + +/* Arbiter configuration depends on memory management mode. */ +#define USBFS_DEFAULT_ARB_CFG ((USBFS_EP_MANAGEMENT_MANUAL) ? (USBFS_ARB_CFG_DMA_CFG_NONE) : \ + ((USBFS_EP_MANAGEMENT_DMA_MANUAL) ? \ + (USBFS_ARB_CFG_DMA_CFG_MANUAL) : \ + (USBFS_ARB_CFG_AUTO_MEM | USBFS_ARB_CFG_DMA_CFG_AUTO))) + +/* Enable arbiter interrupt for active endpoints only */ +#define USBFS_DEFAULT_ARB_INT_EN \ + ((uint8) ((uint8) USBFS_DMA1_ACTIVE << USBFS_ARB_INT_EP1_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA2_ACTIVE << USBFS_ARB_INT_EP2_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA3_ACTIVE << USBFS_ARB_INT_EP3_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA4_ACTIVE << USBFS_ARB_INT_EP4_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA5_ACTIVE << USBFS_ARB_INT_EP5_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA6_ACTIVE << USBFS_ARB_INT_EP6_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA7_ACTIVE << USBFS_ARB_INT_EP7_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA8_ACTIVE << USBFS_ARB_INT_EP8_INTR_POS)) + +/* Enable all SIE endpoints interrupts */ +#define USBFS_DEFAULT_SIE_EP_INT_EN (USBFS_SIE_INT_EP1_INTR | \ + USBFS_SIE_INT_EP2_INTR | \ + USBFS_SIE_INT_EP3_INTR | \ + USBFS_SIE_INT_EP4_INTR | \ + USBFS_SIE_INT_EP5_INTR | \ + USBFS_SIE_INT_EP6_INTR | \ + USBFS_SIE_INT_EP7_INTR | \ + USBFS_SIE_INT_EP8_INTR) + +#define USBFS_ARB_EPX_CFG_DEFAULT (USBFS_ARB_EPX_CFG_RESET | \ + USBFS_ARB_EPX_CFG_CRC_BYPASS) + +/* Default EP arbiter interrupt source register */ +#define USBFS_ARB_EPX_INT_COMMON_MASK (USBFS_ARB_EPX_INT_IN_BUF_FULL | \ + USBFS_ARB_EPX_INT_BUF_OVER | \ + USBFS_ARB_EPX_INT_BUF_UNDER | \ + USBFS_ARB_EPX_INT_ERR_INT | \ + (USBFS_EP_MANAGEMENT_DMA_MANUAL ? USBFS_ARB_EPX_INT_DMA_GNT : 0u)) + +#define USBFS_CLEAR_REG (0u) + +#if (CY_PSOC4) + /* Set USB lock option when IMO is locked to USB traffic. */ + #define USBFS_DEFUALT_CR1 ((0u != CySysClkImoGetUsbLock()) ? (USBFS_CR1_ENABLE_LOCK) : (0u)) + + /* Recommended value is increased from 3 to 10 due to suppress glitch on + * RSE0 with USB2.0 hubs (LF CLK = 32kHz equal to 350us). */ + #define USBFS_DEFUALT_BUS_RST_CNT (10u) + + /* Select VBUS sources as: valid, PHY of GPIO, and clears isolate bit. */ + /* Application level must ensure that VBUS is valid valid to use. */ + #define USBFS_DEFAULT_POWER_CTRL_VBUS (USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN | \ + ((!USBFS_VBUS_MONITORING_ENABLE) ? \ + (USBFS_POWER_CTRL_VBUS_VALID_OVR_1) : \ + (USBFS_VBUS_POWER_PAD_ENABLE ? \ + (USBFS_POWER_CTRL_VBUS_VALID_OVR_PHY) : \ + (USBFS_POWER_CTRL_VBUS_VALID_OVR_GPIO)))) + /* Enable USB IP. */ + #define USBFS_DEFAULT_POWER_CTRL_PHY (USBFS_POWER_CTRL_SUSPEND | \ + USBFS_POWER_CTRL_SUSPEND_DEL | \ + USBFS_POWER_CTRL_ENABLE_RCVR | \ + USBFS_POWER_CTRL_ENABLE_DPO | \ + USBFS_POWER_CTRL_ENABLE_DMO | \ + USBFS_POWER_CTRL_ENABLE) + + /* Assign interrupt between levels lo, med, hi. */ + #define USBFS_DEFAULT_INTR_LVL_SEL ((uint32) (USBFS_INTR_LVL_SEL)) + + /* Enable interrupt source in the INTR_SIE. The SOF is always disabled and EP0 is enabled. */ + #define USBFS_DEFAULT_INTR_SIE_MASK \ + ((uint32) ((uint32) USBFS_BUS_RESET_ISR_ACTIVE << USBFS_INTR_SIE_BUS_RESET_INTR_POS) | \ + (uint32) ((uint32) USBFS_SOF_ISR_ACTIVE << USBFS_INTR_SIE_SOF_INTR_POS) | \ + (uint32) ((uint32) USBFS_LPM_ACTIVE << USBFS_INTR_SIE_LPM_INTR_POS) | \ + (uint32) ((uint32) USBFS_INTR_SIE_EP0_INTR)) + + /* Arbiter interrupt sources */ + #define USBFS_ARB_EPX_INT_MASK (USBFS_ARB_EPX_INT_COMMON_MASK | \ + (USBFS_EP_MANAGEMENT_DMA_AUTO ? USBFS_ARB_EPX_INT_DMA_TERMIN : 0u)) + + /* Common DMA configuration */ + #define USBFS_DMA_COMMON_CFG (CYDMA_PULSE | CYDMA_ENTIRE_DESCRIPTOR | \ + CYDMA_NON_PREEMPTABLE) + + +#else + #define USBFS_ARB_EPX_INT_MASK (USBFS_ARB_EPX_INT_COMMON_MASK) + + #define USBFS_DEFUALT_CR1 (USBFS_CR1_ENABLE_LOCK) + + /* Recommended value is 3 for LF CLK = 100kHz equal to 100us. */ + #define USBFS_DEFUALT_BUS_RST_CNT (10u) +#endif /* (CY_PSOC4) */ + +/* +* \addtogroup group_deprecated +* @{ +*/ + +/*************************************** +* The following code is DEPRECATED and +* must not be used. +***************************************/ + +/* Renamed type definitions */ +#define USBFS_CODE CYCODE +#define USBFS_FAR CYFAR +#if defined(__C51__) || defined(__CX51__) + #define USBFS_DATA data + #define USBFS_XDATA xdata +#else + #define USBFS_DATA + #define USBFS_XDATA +#endif /* __C51__ */ +#define USBFS_NULL NULL +/** @} deprecated */ +/* Renamed structure fields */ +#define wBuffOffset buffOffset +#define wBufferSize bufferSize +#define bStatus status +#define wLength length +#define wCount count + +/* Renamed global variable */ +#define CurrentTD USBFS_currentTD +#define USBFS_interfaceSetting_last USBFS_interfaceSettingLast + +/* Renamed global constants */ +#define USBFS_DWR_VDDD_OPERATION (USBFS_DWR_POWER_OPERATION) + +/* Renamed functions */ +#define USBFS_bCheckActivity USBFS_CheckActivity +#define USBFS_bGetConfiguration USBFS_GetConfiguration +#define USBFS_bGetInterfaceSetting USBFS_GetInterfaceSetting +#define USBFS_bGetEPState USBFS_GetEPState +#define USBFS_wGetEPCount USBFS_GetEPCount +#define USBFS_bGetEPAckState USBFS_GetEPAckState +#define USBFS_bRWUEnabled USBFS_RWUEnabled +#define USBFS_bVBusPresent USBFS_VBusPresent + +#define USBFS_bConfiguration USBFS_configuration +#define USBFS_bInterfaceSetting USBFS_interfaceSetting +#define USBFS_bDeviceAddress USBFS_deviceAddress +#define USBFS_bDeviceStatus USBFS_deviceStatus +#define USBFS_bDevice USBFS_device +#define USBFS_bTransferState USBFS_transferState +#define USBFS_bLastPacketSize USBFS_lastPacketSize + +#define USBFS_LoadEP USBFS_LoadInEP +#define USBFS_LoadInISOCEP USBFS_LoadInEP +#define USBFS_EnableOutISOCEP USBFS_EnableOutEP + +#define USBFS_SetVector CyIntSetVector +#define USBFS_SetPriority CyIntSetPriority +#define USBFS_EnableInt CyIntEnable + +/* Replace with register access. */ +#define USBFS_bmRequestType USBFS_EP0_DR0_PTR +#define USBFS_bRequest USBFS_EP0_DR1_PTR +#define USBFS_wValue USBFS_EP0_DR2_PTR +#define USBFS_wValueHi USBFS_EP0_DR3_PTR +#define USBFS_wValueLo USBFS_EP0_DR2_PTR +#define USBFS_wIndex USBFS_EP0_DR4_PTR +#define USBFS_wIndexHi USBFS_EP0_DR5_PTR +#define USBFS_wIndexLo USBFS_EP0_DR4_PTR +#define USBFS_length USBFS_EP0_DR6_PTR +#define USBFS_lengthHi USBFS_EP0_DR7_PTR +#define USBFS_lengthLo USBFS_EP0_DR6_PTR + +/* Rename VBUS monitoring registers. */ +#if (CY_PSOC3 || CY_PSOC5LP) + #if (USBFS_VBUS_MONITORING_ENABLE) + #if (USBFS_VBUS_MONITORING_INTERNAL) + #define USBFS_VBUS_DR_PTR ( (reg8 *) USBFS_VBUS__DR) + #define USBFS_VBUS_DR_REG (*(reg8 *) USBFS_VBUS__DR) + #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_VBUS__PS) + #define USBFS_VBUS_PS_REG (*(reg8 *) USBFS_VBUS__PS) + #define USBFS_VBUS_MASK USBFS_VBUS__MASK + #else + #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG) + #define USBFS_VBUS_MASK (0x01u) + #endif /* (USBFS_VBUS_MONITORING_INTERNAL) */ + #endif /*(USBFS_VBUS_MONITORING_ENABLE) */ + + /* Pointer DIE structure in flash (8 bytes): Y and X location, wafer, lot msb, lot lsb, + * work week, fab/year, minor. */ + #define USBFS_DIE_ID CYDEV_FLSHID_CUST_TABLES_BASE + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + #if (USBFS_DMA1_ACTIVE) + #define USBFS_ep1_TD_TERMOUT_EN (USBFS_ep1__TD_TERMOUT_EN) + #else + #define USBFS_ep1_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA1_ACTIVE) */ + + #if (USBFS_DMA2_ACTIVE) + #define USBFS_ep2_TD_TERMOUT_EN (USBFS_ep2__TD_TERMOUT_EN) + #else + #define USBFS_ep2_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA2_ACTIVE) */ + + #if (USBFS_DMA3_ACTIVE) + #define USBFS_ep3_TD_TERMOUT_EN (USBFS_ep3__TD_TERMOUT_EN) + #else + #define USBFS_ep3_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA3_ACTIVE) */ + + #if (USBFS_DMA4_ACTIVE) + #define USBFS_ep4_TD_TERMOUT_EN (USBFS_ep4__TD_TERMOUT_EN) + #else + #define USBFS_ep4_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA4_ACTIVE) */ + + #if (USBFS_DMA5_ACTIVE) + #define USBFS_ep5_TD_TERMOUT_EN (USBFS_ep5__TD_TERMOUT_EN) + #else + #define USBFS_ep5_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA5_ACTIVE) */ + + #if (USBFS_DMA6_ACTIVE) + #define USBFS_ep6_TD_TERMOUT_EN (USBFS_ep6__TD_TERMOUT_EN) + #else + #define USBFS_ep6_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA6_ACTIVE) */ + + #if (USBFS_DMA7_ACTIVE) + #define USBFS_ep7_TD_TERMOUT_EN (USBFS_ep7__TD_TERMOUT_EN) + #else + #define USBFS_ep7_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA7_ACTIVE) */ + + #if (USBFS_DMA8_ACTIVE) + #define USBFS_ep8_TD_TERMOUT_EN (USBFS_ep8__TD_TERMOUT_EN) + #else + #define USBFS_ep8_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA8_ACTIVE) */ + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +/* Rename USB IP registers. */ +#define USBFS_ARB_CFG USBFS_ARB_CFG_PTR + +#define USBFS_ARB_EP1_CFG USBFS_ARB_EP1_CFG_PTR +#define USBFS_ARB_EP1_INT_EN USBFS_ARB_EP1_INT_EN_PTR +#define USBFS_ARB_EP1_SR USBFS_ARB_EP1_SR_PTR + +#define USBFS_ARB_EP2_CFG USBFS_ARB_EP2_CFG_PTR +#define USBFS_ARB_EP2_INT_EN USBFS_ARB_EP2_INT_EN_PTR +#define USBFS_ARB_EP2_SR USBFS_ARB_EP2_SR_PTR + +#define USBFS_ARB_EP3_CFG USBFS_ARB_EP3_CFG_PTR +#define USBFS_ARB_EP3_INT_EN USBFS_ARB_EP3_INT_EN_PTR +#define USBFS_ARB_EP3_SR USBFS_ARB_EP3_SR_PTR + +#define USBFS_ARB_EP4_CFG USBFS_ARB_EP4_CFG_PTR +#define USBFS_ARB_EP4_INT_EN USBFS_ARB_EP4_INT_EN_PTR +#define USBFS_ARB_EP4_SR USBFS_ARB_EP4_SR_PTR + +#define USBFS_ARB_EP5_CFG USBFS_ARB_EP5_CFG_PTR +#define USBFS_ARB_EP5_INT_EN USBFS_ARB_EP5_INT_EN_PTR +#define USBFS_ARB_EP5_SR USBFS_ARB_EP5_SR_PTR + +#define USBFS_ARB_EP6_CFG USBFS_ARB_EP6_CFG_PTR +#define USBFS_ARB_EP6_INT_EN USBFS_ARB_EP6_INT_EN_PTR +#define USBFS_ARB_EP6_SR USBFS_ARB_EP6_SR_PTR + +#define USBFS_ARB_EP7_CFG USBFS_ARB_EP7_CFG_PTR +#define USBFS_ARB_EP7_INT_EN USBFS_ARB_EP7_INT_EN_PTR +#define USBFS_ARB_EP7_SR USBFS_ARB_EP7_SR_PTR + +#define USBFS_ARB_EP8_CFG USBFS_ARB_EP8_CFG_PTR +#define USBFS_ARB_EP8_INT_EN USBFS_ARB_EP8_INT_EN_PTR +#define USBFS_ARB_EP8_SR USBFS_ARB_EP8_SR_PTR + +#define USBFS_ARB_INT_EN USBFS_ARB_INT_EN_PTR +#define USBFS_ARB_INT_SR USBFS_ARB_INT_SR_PTR + +#define USBFS_ARB_RW1_DR USBFS_ARB_RW1_DR_PTR +#define USBFS_ARB_RW1_RA USBFS_ARB_RW1_RA_PTR +#define USBFS_ARB_RW1_RA_MSB USBFS_ARB_RW1_RA_MSB_PTR +#define USBFS_ARB_RW1_WA USBFS_ARB_RW1_WA_PTR +#define USBFS_ARB_RW1_WA_MSB USBFS_ARB_RW1_WA_MSB_PTR + +#define USBFS_ARB_RW2_DR USBFS_ARB_RW2_DR_PTR +#define USBFS_ARB_RW2_RA USBFS_ARB_RW2_RA_PTR +#define USBFS_ARB_RW2_RA_MSB USBFS_ARB_RW2_RA_MSB_PTR +#define USBFS_ARB_RW2_WA USBFS_ARB_RW2_WA_PTR +#define USBFS_ARB_RW2_WA_MSB USBFS_ARB_RW2_WA_MSB_PTR + +#define USBFS_ARB_RW3_DR USBFS_ARB_RW3_DR_PTR +#define USBFS_ARB_RW3_RA USBFS_ARB_RW3_RA_PTR +#define USBFS_ARB_RW3_RA_MSB USBFS_ARB_RW3_RA_MSB_PTR +#define USBFS_ARB_RW3_WA USBFS_ARB_RW3_WA_PTR +#define USBFS_ARB_RW3_WA_MSB USBFS_ARB_RW3_WA_MSB_PTR + +#define USBFS_ARB_RW4_DR USBFS_ARB_RW4_DR_PTR +#define USBFS_ARB_RW4_RA USBFS_ARB_RW4_RA_PTR +#define USBFS_ARB_RW4_RA_MSB USBFS_ARB_RW4_RA_MSB_PTR +#define USBFS_ARB_RW4_WA USBFS_ARB_RW4_WA_PTR +#define USBFS_ARB_RW4_WA_MSB USBFS_ARB_RW4_WA_MSB_PTR + +#define USBFS_ARB_RW5_DR USBFS_ARB_RW5_DR_PTR +#define USBFS_ARB_RW5_RA USBFS_ARB_RW5_RA_PTR +#define USBFS_ARB_RW5_RA_MSB USBFS_ARB_RW5_RA_MSB_PTR +#define USBFS_ARB_RW5_WA USBFS_ARB_RW5_WA_PTR +#define USBFS_ARB_RW5_WA_MSB USBFS_ARB_RW5_WA_MSB_PTR + +#define USBFS_ARB_RW6_DR USBFS_ARB_RW6_DR_PTR +#define USBFS_ARB_RW6_RA USBFS_ARB_RW6_RA_PTR +#define USBFS_ARB_RW6_RA_MSB USBFS_ARB_RW6_RA_MSB_PTR +#define USBFS_ARB_RW6_WA USBFS_ARB_RW6_WA_PTR +#define USBFS_ARB_RW6_WA_MSB USBFS_ARB_RW6_WA_MSB_PTR + +#define USBFS_ARB_RW7_DR USBFS_ARB_RW7_DR_PTR +#define USBFS_ARB_RW7_RA USBFS_ARB_RW7_RA_PTR +#define USBFS_ARB_RW7_RA_MSB USBFS_ARB_RW7_RA_MSB_PTR +#define USBFS_ARB_RW7_WA USBFS_ARB_RW7_WA_PTR +#define USBFS_ARB_RW7_WA_MSB USBFS_ARB_RW7_WA_MSB_PTR + +#define USBFS_ARB_RW8_DR USBFS_ARB_RW8_DR_PTR +#define USBFS_ARB_RW8_RA USBFS_ARB_RW8_RA_PTR +#define USBFS_ARB_RW8_RA_MSB USBFS_ARB_RW8_RA_MSB_PTR +#define USBFS_ARB_RW8_WA USBFS_ARB_RW8_WA_PTR +#define USBFS_ARB_RW8_WA_MSB USBFS_ARB_RW8_WA_MSB_PTR + +#define USBFS_BUF_SIZE USBFS_BUF_SIZE_PTR +#define USBFS_BUS_RST_CNT USBFS_BUS_RST_CNT_PTR +#define USBFS_CR0 USBFS_CR0_PTR +#define USBFS_CR1 USBFS_CR1_PTR +#define USBFS_CWA USBFS_CWA_PTR +#define USBFS_CWA_MSB USBFS_CWA_MSB_PTR + +#define USBFS_DMA_THRES USBFS_DMA_THRES_PTR +#define USBFS_DMA_THRES_MSB USBFS_DMA_THRES_MSB_PTR + +#define USBFS_EP_ACTIVE USBFS_EP_ACTIVE_PTR +#define USBFS_EP_TYPE USBFS_EP_TYPE_PTR + +#define USBFS_EP0_CNT USBFS_EP0_CNT_PTR +#define USBFS_EP0_CR USBFS_EP0_CR_PTR +#define USBFS_EP0_DR0 USBFS_EP0_DR0_PTR +#define USBFS_EP0_DR1 USBFS_EP0_DR1_PTR +#define USBFS_EP0_DR2 USBFS_EP0_DR2_PTR +#define USBFS_EP0_DR3 USBFS_EP0_DR3_PTR +#define USBFS_EP0_DR4 USBFS_EP0_DR4_PTR +#define USBFS_EP0_DR5 USBFS_EP0_DR5_PTR +#define USBFS_EP0_DR6 USBFS_EP0_DR6_PTR +#define USBFS_EP0_DR7 USBFS_EP0_DR7_PTR + +#define USBFS_OSCLK_DR0 USBFS_OSCLK_DR0_PTR +#define USBFS_OSCLK_DR1 USBFS_OSCLK_DR1_PTR + +#define USBFS_PM_ACT_CFG USBFS_PM_ACT_CFG_PTR +#define USBFS_PM_STBY_CFG USBFS_PM_STBY_CFG_PTR + +#define USBFS_SIE_EP_INT_EN USBFS_SIE_EP_INT_EN_PTR +#define USBFS_SIE_EP_INT_SR USBFS_SIE_EP_INT_SR_PTR + +#define USBFS_SIE_EP1_CNT0 USBFS_SIE_EP1_CNT0_PTR +#define USBFS_SIE_EP1_CNT1 USBFS_SIE_EP1_CNT1_PTR +#define USBFS_SIE_EP1_CR0 USBFS_SIE_EP1_CR0_PTR + +#define USBFS_SIE_EP2_CNT0 USBFS_SIE_EP2_CNT0_PTR +#define USBFS_SIE_EP2_CNT1 USBFS_SIE_EP2_CNT1_PTR +#define USBFS_SIE_EP2_CR0 USBFS_SIE_EP2_CR0_PTR + +#define USBFS_SIE_EP3_CNT0 USBFS_SIE_EP3_CNT0_PTR +#define USBFS_SIE_EP3_CNT1 USBFS_SIE_EP3_CNT1_PTR +#define USBFS_SIE_EP3_CR0 USBFS_SIE_EP3_CR0_PTR + +#define USBFS_SIE_EP4_CNT0 USBFS_SIE_EP4_CNT0_PTR +#define USBFS_SIE_EP4_CNT1 USBFS_SIE_EP4_CNT1_PTR +#define USBFS_SIE_EP4_CR0 USBFS_SIE_EP4_CR0_PTR + +#define USBFS_SIE_EP5_CNT0 USBFS_SIE_EP5_CNT0_PTR +#define USBFS_SIE_EP5_CNT1 USBFS_SIE_EP5_CNT1_PTR +#define USBFS_SIE_EP5_CR0 USBFS_SIE_EP5_CR0_PTR + +#define USBFS_SIE_EP6_CNT0 USBFS_SIE_EP6_CNT0_PTR +#define USBFS_SIE_EP6_CNT1 USBFS_SIE_EP6_CNT1_PTR +#define USBFS_SIE_EP6_CR0 USBFS_SIE_EP6_CR0_PTR + +#define USBFS_SIE_EP7_CNT0 USBFS_SIE_EP7_CNT0_PTR +#define USBFS_SIE_EP7_CNT1 USBFS_SIE_EP7_CNT1_PTR +#define USBFS_SIE_EP7_CR0 USBFS_SIE_EP7_CR0_PTR + +#define USBFS_SIE_EP8_CNT0 USBFS_SIE_EP8_CNT0_PTR +#define USBFS_SIE_EP8_CNT1 USBFS_SIE_EP8_CNT1_PTR +#define USBFS_SIE_EP8_CR0 USBFS_SIE_EP8_CR0_PTR + +#define USBFS_SOF0 USBFS_SOF0_PTR +#define USBFS_SOF1 USBFS_SOF1_PTR + +#define USBFS_USB_CLK_EN USBFS_USB_CLK_EN_PTR + +#define USBFS_USBIO_CR0 USBFS_USBIO_CR0_PTR +#define USBFS_USBIO_CR1 USBFS_USBIO_CR1_PTR +#define USBFS_USBIO_CR2 USBFS_USBIO_CR2_PTR + +#define USBFS_DM_INP_DIS_PTR ( (reg8 *) USBFS_Dm__INP_DIS) +#define USBFS_DM_INP_DIS_REG (*(reg8 *) USBFS_Dm__INP_DIS) +#define USBFS_DP_INP_DIS_PTR ( (reg8 *) USBFS_Dp__INP_DIS) +#define USBFS_DP_INP_DIS_REG (*(reg8 *) USBFS_Dp__INP_DIS) +#define USBFS_DP_INTSTAT_PTR ( (reg8 *) USBFS_Dp__INTSTAT) +#define USBFS_DP_INTSTAT_REG (*(reg8 *) USBFS_Dp__INTSTAT) +#define USBFS_DM_MASK USBFS_Dm__0__MASK +#define USBFS_DP_MASK USBFS_Dp__0__MASK + +#define USBFS_SIE_EP_INT_EP1_MASK (0x01u) +#define USBFS_SIE_EP_INT_EP2_MASK (0x02u) +#define USBFS_SIE_EP_INT_EP3_MASK (0x04u) +#define USBFS_SIE_EP_INT_EP4_MASK (0x08u) +#define USBFS_SIE_EP_INT_EP5_MASK (0x10u) +#define USBFS_SIE_EP_INT_EP6_MASK (0x20u) +#define USBFS_SIE_EP_INT_EP7_MASK (0x40u) +#define USBFS_SIE_EP_INT_EP8_MASK (0x80u) + +#define USBFS_ARB_EPX_SR_IN_BUF_FULL (0x01u) +#define USBFS_ARB_EPX_SR_DMA_GNT (0x02u) +#define USBFS_ARB_EPX_SR_BUF_OVER (0x04u) +#define USBFS_ARB_EPX_SR_BUF_UNDER (0x08u) + +#define USBFS_ARB_EPX_INT_EN_ALL USBFS_ARB_EPX_INT_ALL + +#define USBFS_CR1_BUS_ACTIVITY_SHIFT (0x02u) + +#define USBFS_BUS_RST_COUNT USBFS_DEFUALT_BUS_RST_CNT + +#define USBFS_ARB_INT_MASK USBFS_DEFAULT_ARB_INT_EN + +#if (CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_LEOPARD) + /* CY_PSOC3 interrupt registers */ + #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_INTC_PRIOR0) + #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_INTC_SET_EN0) + #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_INTC_CLR_EN0) + #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_INTC_VECT_MBASE) +#elif (CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_PANTHER) + /* CY_PSOC5LP interrupt registers */ + #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_NVIC_PRI_0) + #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0) + #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0) + #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET) +#endif /* CYDEV_CHIP_DIE_EXPECT */ + + +#endif /* (CY_USBFS_USBFS_H) */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_Dp.c b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_Dp.c new file mode 100644 index 0000000000..dc6e9856e8 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_Dp.c @@ -0,0 +1,234 @@ +/******************************************************************************* +* File Name: USBFS_Dp.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "cytypes.h" +#include "USBFS_Dp.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + USBFS_Dp__PORT == 15 && ((USBFS_Dp__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: USBFS_Dp_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_Write +*******************************************************************************/ +void USBFS_Dp_Write(uint8 value) +{ + uint8 staticBits = (USBFS_Dp_DR & (uint8)(~USBFS_Dp_MASK)); + USBFS_Dp_DR = staticBits | ((uint8)(value << USBFS_Dp_SHIFT) & USBFS_Dp_MASK); +} + + +/******************************************************************************* +* Function Name: USBFS_Dp_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_SetDriveMode +*******************************************************************************/ +void USBFS_Dp_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(USBFS_Dp_0, mode); +} + + +/******************************************************************************* +* Function Name: USBFS_Dp_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_Read +*******************************************************************************/ +uint8 USBFS_Dp_Read(void) +{ + return (USBFS_Dp_PS & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; +} + + +/******************************************************************************* +* Function Name: USBFS_Dp_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred USBFS_Dp_Read() API because the +* USBFS_Dp_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_ReadDataReg +*******************************************************************************/ +uint8 USBFS_Dp_ReadDataReg(void) +{ + return (USBFS_Dp_DR & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(USBFS_Dp_INTSTAT) + + /******************************************************************************* + * Function Name: USBFS_Dp_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use USBFS_Dp_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - USBFS_Dp_0_INTR (First pin in the list) + * - USBFS_Dp_1_INTR (Second pin in the list) + * - ... + * - USBFS_Dp_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_SetInterruptMode + *******************************************************************************/ + void USBFS_Dp_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & USBFS_Dp_0_INTR) != 0u) + { + USBFS_Dp_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: USBFS_Dp_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_ClearInterrupt + *******************************************************************************/ + uint8 USBFS_Dp_ClearInterrupt(void) + { + return (USBFS_Dp_INTSTAT & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_Dp.h b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_Dp.h new file mode 100644 index 0000000000..c337910f9f --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_Dp.h @@ -0,0 +1,173 @@ +/******************************************************************************* +* File Name: USBFS_Dp.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_USBFS_Dp_H) /* Pins USBFS_Dp_H */ +#define CY_PINS_USBFS_Dp_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "USBFS_Dp_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + USBFS_Dp__PORT == 15 && ((USBFS_Dp__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void USBFS_Dp_Write(uint8 value); +void USBFS_Dp_SetDriveMode(uint8 mode); +uint8 USBFS_Dp_ReadDataReg(void); +uint8 USBFS_Dp_Read(void); +void USBFS_Dp_SetInterruptMode(uint16 position, uint16 mode); +uint8 USBFS_Dp_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the USBFS_Dp_SetDriveMode() function. + * @{ + */ + #define USBFS_Dp_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define USBFS_Dp_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define USBFS_Dp_DM_RES_UP PIN_DM_RES_UP + #define USBFS_Dp_DM_RES_DWN PIN_DM_RES_DWN + #define USBFS_Dp_DM_OD_LO PIN_DM_OD_LO + #define USBFS_Dp_DM_OD_HI PIN_DM_OD_HI + #define USBFS_Dp_DM_STRONG PIN_DM_STRONG + #define USBFS_Dp_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define USBFS_Dp_MASK USBFS_Dp__MASK +#define USBFS_Dp_SHIFT USBFS_Dp__SHIFT +#define USBFS_Dp_WIDTH 1u + +/* Interrupt constants */ +#if defined(USBFS_Dp__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in USBFS_Dp_SetInterruptMode() function. + * @{ + */ + #define USBFS_Dp_INTR_NONE (uint16)(0x0000u) + #define USBFS_Dp_INTR_RISING (uint16)(0x0001u) + #define USBFS_Dp_INTR_FALLING (uint16)(0x0002u) + #define USBFS_Dp_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define USBFS_Dp_INTR_MASK (0x01u) +#endif /* (USBFS_Dp__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define USBFS_Dp_PS (* (reg8 *) USBFS_Dp__PS) +/* Data Register */ +#define USBFS_Dp_DR (* (reg8 *) USBFS_Dp__DR) +/* Port Number */ +#define USBFS_Dp_PRT_NUM (* (reg8 *) USBFS_Dp__PRT) +/* Connect to Analog Globals */ +#define USBFS_Dp_AG (* (reg8 *) USBFS_Dp__AG) +/* Analog MUX bux enable */ +#define USBFS_Dp_AMUX (* (reg8 *) USBFS_Dp__AMUX) +/* Bidirectional Enable */ +#define USBFS_Dp_BIE (* (reg8 *) USBFS_Dp__BIE) +/* Bit-mask for Aliased Register Access */ +#define USBFS_Dp_BIT_MASK (* (reg8 *) USBFS_Dp__BIT_MASK) +/* Bypass Enable */ +#define USBFS_Dp_BYP (* (reg8 *) USBFS_Dp__BYP) +/* Port wide control signals */ +#define USBFS_Dp_CTL (* (reg8 *) USBFS_Dp__CTL) +/* Drive Modes */ +#define USBFS_Dp_DM0 (* (reg8 *) USBFS_Dp__DM0) +#define USBFS_Dp_DM1 (* (reg8 *) USBFS_Dp__DM1) +#define USBFS_Dp_DM2 (* (reg8 *) USBFS_Dp__DM2) +/* Input Buffer Disable Override */ +#define USBFS_Dp_INP_DIS (* (reg8 *) USBFS_Dp__INP_DIS) +/* LCD Common or Segment Drive */ +#define USBFS_Dp_LCD_COM_SEG (* (reg8 *) USBFS_Dp__LCD_COM_SEG) +/* Enable Segment LCD */ +#define USBFS_Dp_LCD_EN (* (reg8 *) USBFS_Dp__LCD_EN) +/* Slew Rate Control */ +#define USBFS_Dp_SLW (* (reg8 *) USBFS_Dp__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define USBFS_Dp_PRTDSI__CAPS_SEL (* (reg8 *) USBFS_Dp__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define USBFS_Dp_PRTDSI__DBL_SYNC_IN (* (reg8 *) USBFS_Dp__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define USBFS_Dp_PRTDSI__OE_SEL0 (* (reg8 *) USBFS_Dp__PRTDSI__OE_SEL0) +#define USBFS_Dp_PRTDSI__OE_SEL1 (* (reg8 *) USBFS_Dp__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define USBFS_Dp_PRTDSI__OUT_SEL0 (* (reg8 *) USBFS_Dp__PRTDSI__OUT_SEL0) +#define USBFS_Dp_PRTDSI__OUT_SEL1 (* (reg8 *) USBFS_Dp__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define USBFS_Dp_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_Dp__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(USBFS_Dp__SIO_CFG) + #define USBFS_Dp_SIO_HYST_EN (* (reg8 *) USBFS_Dp__SIO_HYST_EN) + #define USBFS_Dp_SIO_REG_HIFREQ (* (reg8 *) USBFS_Dp__SIO_REG_HIFREQ) + #define USBFS_Dp_SIO_CFG (* (reg8 *) USBFS_Dp__SIO_CFG) + #define USBFS_Dp_SIO_DIFF (* (reg8 *) USBFS_Dp__SIO_DIFF) +#endif /* (USBFS_Dp__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(USBFS_Dp__INTSTAT) + #define USBFS_Dp_INTSTAT (* (reg8 *) USBFS_Dp__INTSTAT) + #define USBFS_Dp_SNAP (* (reg8 *) USBFS_Dp__SNAP) + + #define USBFS_Dp_0_INTTYPE_REG (* (reg8 *) USBFS_Dp__0__INTTYPE) +#endif /* (USBFS_Dp__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_USBFS_Dp_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_Dp_aliases.h b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_Dp_aliases.h new file mode 100644 index 0000000000..a4d25267c2 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_Dp_aliases.h @@ -0,0 +1,44 @@ +/******************************************************************************* +* File Name: USBFS_Dp.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_PINS_USBFS_Dp_ALIASES_H) /* Pins USBFS_Dp_ALIASES_H */ +#define CY_PINS_USBFS_Dp_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define USBFS_Dp_0 (USBFS_Dp__0__PC) +#define USBFS_Dp_0_INTR ((uint16)((uint16)0x0001u << USBFS_Dp__0__SHIFT)) + +#define USBFS_Dp_INTR_ALL ((uint16)(USBFS_Dp_0_INTR)) + +#endif /* End Pins USBFS_Dp_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_cdc.c b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_cdc.c new file mode 100644 index 0000000000..d2009b6ef8 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_cdc.c @@ -0,0 +1,1147 @@ +/***************************************************************************//** +* \file USBFS_cdc.c +* \version 3.20 +* +* \brief +* This file contains the USB CDC class request handler. +* +* Related Document: +* Universal Serial Bus Class Definitions for Communication Devices Version 1.1 +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "USBFS_cdc.h" +#include "USBFS_pvt.h" +#include "usbd_PSoC5LP.h" + + +#if defined(USBFS_ENABLE_CDC_CLASS) + +/******************************************************************************* +* CDC Variables +*******************************************************************************/ + +/*PUBLIC*/ +/** Contains the current line coding structure. The host sets it using a + * SET_LINE_CODING request and returns it to the user code using the + * USBFS_GetDTERate(), USBFS_GetCharFormat(), + * USBFS_GetParityType(), and USBFS_GetDataBits() APIs. + * It is an array of 2 elements for COM port 1 and COM port 2 for MultiCOM port + * support. In case of 1 COM port, data is in 0 element.*/ +volatile uint8 USBFS_linesCoding[USBFS_MAX_MULTI_COM_NUM][USBFS_LINE_CODING_SIZE] = +{ + /*COM Port 1*/ + { + 0x00u, 0xC2u, 0x01u, 0x00u, /* Data terminal rate 115200 */ + 0x00u, /* 1 Stop bit */ + 0x00u, /* None parity */ + 0x08u /* 8 data bits */ + }, +// /*COM Port 2*/ +// { +// 0x00u, 0xC2u, 0x01u, 0x00u, /* Data terminal rate 115200 */ +// 0x00u, /* 1 Stop bit */ +// 0x00u, /* None parity */ +// 0x08u /* 8 data bits */ +// } +}; + +/**Used as a flag for the USBFS_IsLineChanged() API, to inform it that the + * host has been sent a request to change line coding or control bitmap. It is + * an array of 2 elements for COM port 1 and COM port 2 for MultiCOM port + * support. In case of 1 COM port, data is in 0 element.*/ +volatile uint8 USBFS_linesChanged[USBFS_MAX_MULTI_COM_NUM]; +/** Contains the current control-signal bitmap. The host sets it using a + * SET_CONTROL_LINE request and returns it to the user code using the + * USBFS_GetLineControl() API. It is an array of 2 elements for COM + * port 1 and COM port 2 for MultiCOM port support. In case of 1 COM port, data + * is in 0 element.*/ +volatile uint16 USBFS_linesControlBitmap[USBFS_MAX_MULTI_COM_NUM]; +/** Contains the 16-bit serial state value that was sent using the + * \ref USBFS_SendSerialState() API. . It is an array of 2 elements + * for COM port 1 and COM port 2 for MultiCOM port support. In case of 1 COM + * port, data is in 0 element.*/ +volatile uint16 USBFS_serialStateBitmap[USBFS_MAX_MULTI_COM_NUM]; +/** Contains the data IN endpoint number. It is initialized after a + * SET_CONFIGURATION request based on a user descriptor. It is used in CDC APIs + * to send data to the PC. It is an array of 2 elements for COM port 1 and COM + * port 2 for MultiCOM port support. In case of 1 COM port, data is in 0 element.*/ +volatile uint8 USBFS_cdcDataInEp[USBFS_MAX_MULTI_COM_NUM]; +/** Contains the data OUT endpoint number. It is initialized after a + * SET_CONFIGURATION request based on user descriptor. It is used in CDC APIs to + * receive data from the PC. It is an array of 2 elements for COM port 1 and COM + * port 2 for MultiCOM port support. In case of 1 COM port, data is in 0 element.*/ +volatile uint8 USBFS_cdcDataOutEp[USBFS_MAX_MULTI_COM_NUM]; +/** Contains the data IN endpoint number for COMMUNICATION interface. It is + * initialized after a SET_CONFIGURATION request based on a user descriptor. It + * is used in CDC APIs to send data to the PC. It is an array of 2 elements for + * COM port 1 and COM port 2 for MultiCOM port support. In case of 1 COM port, + * data is in 0 element.*/ +volatile uint8 USBFS_cdcCommInInterruptEp[USBFS_MAX_MULTI_COM_NUM]; + +/*PRIVATE*/ + +#define USBFS_CDC_IN_EP (0u) +#define USBFS_CDC_OUT_EP (1u) +#define USBFS_CDC_NOTE_EP (2u) + +#define USBFS_CDC_EP_MASK (0x01u) + +#define USBFS_GET_EP_COM_NUM(cdcComNums, epType) (((cdcComNums) >> (epType)) & USBFS_CDC_EP_MASK) + + +/*************************************** +* Static Function Prototypes +***************************************/ +#if (USBFS_ENABLE_CDC_CLASS_API != 0u) + static uint16 USBFS_StrLen(const char8 string[]) ; + static t_USBFS_cdc_notification USBFS_serialStateNotification = + { + + USBFS_SERIAL_STATE_REQUEST_TYPE, /* bRequestType */ + USBFS_SERIAL_STATE, /* bNotification */ + 0u, /* wValue */ + 0u, /* wValueMSB */ + 0u, /* wIndex */ + 0u, /* wIndexMSB */ + USBFS_SERIAL_STATE_LENGTH, /* wLength */ + 0u, /* wLengthMSB */ + 0u, /* wSerialState */ + 0u, /* wSerialStateMSB */ + }; + static uint8 USBFS_activeCom = 0u; +#endif /* (USBFS_ENABLE_CDC_CLASS_API != 0u) */ + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START CDC_CUSTOM_DECLARATIONS` Place your declaration here */ + +#define USBFS_CDC_SEND_BREAK (0x23u) + +volatile bool SetLineCodingReq = false; + +__packed union { + uint16 wValue; /* wValue */ + __packed struct { + uint8 wValueL; + uint8 wValueH; + }; +} Value; + + + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_DispatchCDCClassRqst +****************************************************************************//** +* +* This routine dispatches CDC class requests. +* +* \return +* requestHandled +* +* \globalvars +* USBFS_linesCoding: Contains the current line coding structure. +* It is set by the Host using SET_LINE_CODING request and returned to the +* user code by the USBFS_GetDTERate(), USBFS_GetCharFormat(), +* USBFS_GetParityType(), USBFS_GetDataBits() APIs. +* USBFS_linesControlBitmap: Contains the current control signal +* bitmap. It is set by the Host using SET_CONTROL_LINE request and returned +* to the user code by the USBFS_GetLineControl() API. +* USBFS_linesChanged: This variable is used as a flag for the +* USBFS_IsLineChanged() API, to be aware that Host has been sent request +* for changing Line Coding or Control Bitmap. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchCDCClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + uint8 comPort; + + comPort = USBFS_GetInterfaceComPort((uint8)USBFS_wIndexLoReg); + + /* Check request direction: D2H or H2D. */ + if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H)) + { + /* Handle direction from device to host. */ + + switch (USBFS_bRequestReg) + { + case USBFS_CDC_GET_LINE_CODING: + USBFS_currentTD.count = USBFS_LINE_CODING_SIZE; + USBFS_currentTD.pData = USBFS_linesCoding[comPort]; + requestHandled = USBFS_InitControlRead(); + break; + + /* `#START CDC_READ_REQUESTS` Place other request handler here */ + + /* `#END` */ + + default: + /* Do not handle this request unless callback is defined. */ + #ifdef USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK + requestHandled = USBFS_DispatchCDCClass_CDC_READ_REQUESTS_Callback(); + #endif /* (USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK) */ + break; + } + } + else + { + /* Handle direction from host to device. */ + + switch (USBFS_bRequestReg) + { + case USBFS_CDC_SET_LINE_CODING: + USBFS_currentTD.count = USBFS_LINE_CODING_SIZE; + USBFS_currentTD.pData = USBFS_linesCoding[comPort]; + USBFS_linesChanged[comPort] |= USBFS_LINE_CODING_CHANGED; + + SetLineCodingReq = true; + requestHandled = USBFS_InitControlWrite(); + break; + + case USBFS_CDC_SET_CONTROL_LINE_STATE: + USBFS_linesControlBitmap[comPort] = (uint8) USBFS_wValueLoReg; + USBFS_linesChanged[comPort] |= USBFS_LINE_CONTROL_CHANGED; + + requestHandled = USBFS_InitNoDataControlTransfer(); + break; + + /* `#START CDC_WRITE_REQUESTS` Place other request handler here */ + + case USBFS_CDC_SEND_BREAK: + Value.wValueL = USBFS_wValueLoReg; + Value.wValueH = USBFS_wValueHiReg; + break_value = Value.wValue; + break_req = 1; + requestHandled = USBFS_InitNoDataControlTransfer(); + USBFS_CDCClassRqst_Callback(); + break; + /* `#END` */ + + default: + /* Do not handle this request unless callback is defined. */ + #ifdef USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK + requestHandled = USBFS_DispatchCDCClass_CDC_WRITE_REQUESTS_Callback(); + #endif /* (USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK) */ + break; + } + } + + return(requestHandled); +} + + +/*************************************************************************** +* Function Name: USBFS_GetInterfaceComPort +************************************************************************//** +* \internal +* Internal function which gets number of COM port by specified interface +* number. +* +* \param uint8 interface +* Interface number +* +* \return +* COM port number (0 or 1) or error 0xFF +* +***************************************************************************/ +uint8 USBFS_GetInterfaceComPort(uint8 interface) +{ + uint8 comPort = 0u; + uint8 res = 0xFFu; + uint8 notEp; + + while (comPort < USBFS_MAX_MULTI_COM_NUM) + { + notEp = USBFS_cdcCommInInterruptEp[comPort]; + + if (USBFS_EP[notEp].interface == interface) + { + res = comPort; + comPort = USBFS_MAX_MULTI_COM_NUM; + } + + comPort++; + } + return (res); +} + + +/*************************************** +* Optional CDC APIs +***************************************/ +#if (USBFS_ENABLE_CDC_CLASS_API != 0u) +/*************************************************************************** +* Function Name: USBFS_CDC_Init +************************************************************************//** +* +* This function initializes the CDC interface to be ready to receive data +* from the PC. The API set active communication port to 0 in the case of +* multiple communication port support.This API should be called after the +* device has been started and configured using USBUART_Start() API to +* initialize and start the USBFS component operation. Then call the +* USBUART_GetConfiguration() API to wait until the host has enumerated and +* configured the device. For example: +* +* \snippet /USBFS_sut_02.cydsn/main.c wait for enumeration +* +* \return +* cystatus: +* Return Value Description +* USBFS_SUCCESS CDC interface was initialized correctly +* USBFS_FAILURE CDC interface was not initialized +* +* \globalvars +* USBFS_linesChanged: Initialized to zero. +* USBFS_cdcDataOutEp: Used as an OUT endpoint number. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_CDC_Init(void) +{ + uint8 comPort; + uint8 outEp; + uint8 ret = USBFS_SUCCESS; + + USBFS_activeCom = 0u; + USBFS_linesChanged[USBFS_COM_PORT1] = 0u; +// USBFS_linesChanged[USBFS_COM_PORT2] = 0u; + + for(comPort = 0u; comPort outEp)) + { + USBFS_EnableOutEP(outEp); + } + + } + + /* COM Port 1 should be correct to proceed. */ + if ((0u == USBFS_cdcDataInEp[USBFS_COM_PORT1]) \ + || (0u == USBFS_cdcDataOutEp[USBFS_COM_PORT1]) \ + || (0u == USBFS_cdcCommInInterruptEp[USBFS_COM_PORT1]) + || (USBFS_cdcDataInEp[USBFS_COM_PORT1] >= USBFS_MAX_EP) + || (USBFS_cdcDataOutEp[USBFS_COM_PORT1] >= USBFS_MAX_EP) + || (USBFS_cdcCommInInterruptEp[USBFS_COM_PORT1] >= USBFS_MAX_EP)) + { + ret = USBFS_FAILURE; + } + + return (ret); +} + + +/******************************************************************************* +* Function Name: USBFS_PutData +****************************************************************************//** +* +* This function sends a specified number of bytes from the location specified +* by a pointer to the PC. The USBFS_CDCIsReady() function should be +* called before sending new data, to be sure that the previous data has +* finished sending. +* If the last sent packet is less than maximum packet size the USB transfer +* of this short packet will identify the end of the segment. If the last sent +* packet is exactly maximum packet size, it shall be followed by a zero-length +* packet (which is a short packet) to assure the end of segment is properly +* identified. To send zero-length packet, use USBFS_PutData() API +* with length parameter set to zero. +* +* \param pData: pointer to the buffer containing data to be sent. +* \param length: Specifies the number of bytes to send from the pData +* buffer. Maximum length will be limited by the maximum packet +* size for the endpoint. Data will be lost if length is greater than Max +* Packet Size. +* +* \globalvars +* +* USBFS_cdcDataInEp: CDC IN endpoint number used for sending +* data. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_PutData(const uint8* pData, uint16 length) +{ + uint8 epNumber = USBFS_cdcDataInEp[USBFS_activeCom]; + + /* Limit length to maximum packet size for endpoint. */ + if (length > USBFS_EP[epNumber].bufferSize) + { + /* Caution: Data will be lost if length is greater than Max Packet Size. */ + length = USBFS_EP[epNumber].bufferSize; + + /* Halt CPU in debug mode */ + CYASSERT(0u != 0u); + } + + USBFS_LoadInEP(epNumber, pData, length); +} + + +/******************************************************************************* +* Function Name: USBFS_StrLen +****************************************************************************//** +* +* Calculates length of a null terminated string. +* +* \param string: pointer to the string. +* +* \return +* Length of the string +* +*******************************************************************************/ +static uint16 USBFS_StrLen(const char8 string[]) +{ + uint16 len = 0u; + + while (string[len] != (char8)0) + { + len++; + } + + return ((uint16) len); +} + + +/*************************************************************************** +* Function Name: USBFS_PutString +************************************************************************//** +* +* This function sends a null terminated string to the PC. This function will +* block if there is not enough memory to place the whole string. It will block +* until the entire string has been written to the transmit buffer. +* The USBFS_CDCIsReady() function should be called before +* sending data with a new call to USBFS_PutString(), to be sure +* that the previous data has finished sending. This function sends +* zero-length packet automatically, if the length of the last packet, sent +* by this API, is equal to Max Packet Size +* +* \param string: pointer to the string to be sent to the PC. +* +* \globalvars +* +* USBFS_cdcDataInEp: CDC IN endpoint number used for sending +* data. +* +* \reentrant +* No. +* +***************************************************************************/ +void USBFS_PutString(const char8 string[]) +{ + uint16 strLength; + uint16 sendLength; + uint16 bufIndex = 0u; + + uint8 epNumber = USBFS_cdcDataInEp[USBFS_activeCom]; + + /* Get length string length (it is terminated with zero). */ + strLength = USBFS_StrLen(string); + + do + { + /* Limit length to maximum packet size of endpoint. */ + sendLength = (strLength > USBFS_EP[epNumber].bufferSize) ? + USBFS_EP[epNumber].bufferSize : strLength; + + /* Load IN endpoint and expose it to host. */ + USBFS_LoadInEP(epNumber, (const uint8 *)&string[bufIndex], sendLength); + strLength -= sendLength; + + /* If more data are present to send or full packet was sent */ + if ((strLength > 0u) || (sendLength == USBFS_EP[epNumber].bufferSize)) + { + bufIndex += sendLength; + + /* Wait until host read data from IN endpoint buffer. */ + while (USBFS_IN_BUFFER_FULL == USBFS_EP[epNumber].apiEpState) + { + } + + /* If last packet is exactly maximum packet size, it shall be followed + * by a zero-length packet to assure the end of segment is properly + * identified by the terminal. + */ + if (0u == strLength) + { + USBFS_LoadInEP(epNumber, NULL, 0u); + } + } + } + while (strLength > 0u); +} + + +/*************************************************************************** +* Function Name: USBFS_PutChar +************************************************************************//** +* +* This function writes a single character to the PC at a time. This is an +* inefficient way to send large amounts of data. +* +* \param txDataByte: Character to be sent to the PC. +* +* \globalvars +* +* USBFS_cdcDataInEp: CDC IN endpoint number used for sending +* data. +* +* \reentrant +* No. +* +***************************************************************************/ +void USBFS_PutChar(char8 txDataByte) +{ + uint8 dataByte; + dataByte = (uint8) txDataByte; + + USBFS_LoadInEP(USBFS_cdcDataInEp[USBFS_activeCom], &dataByte, 1u); +} + + +/******************************************************************************* +* Function Name: USBFS_PutCRLF +****************************************************************************//** +* +* This function sends a carriage return (0x0D) and line feed (0x0A) to the +* PC. This APIis provided to mimic API provided by our other UART components +* +* \globalvars +* +* USBFS_cdcDataInEp: CDC IN endpoint number used for sending +* data. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_PutCRLF(void) +{ + const uint8 CYCODE txData[] = {0x0Du, 0x0Au}; + + USBFS_LoadInEP(USBFS_cdcDataInEp[USBFS_activeCom], (const uint8 *)txData, 2u); +} + + +/******************************************************************************* +* Function Name: USBFS_GetCount +****************************************************************************//** +* +* This function returns the number of bytes that were received from the PC. +* The returned length value should be passed to USBFS_GetData() as +* a parameter to read all received data. If all of the received data is not +* read at one time by the USBFS_GetData() API, the unread data will +* be lost. +* +* \return +* Returns the number of received bytes. The maximum amount of received data at +* a time is limited by the maximum packet size for the endpoint. +* +* \globalvars +* USBFS_cdcDataOutEp: CDC OUT endpoint number used. +* +*******************************************************************************/ +uint16 USBFS_GetCount(void) +{ + uint16 bytesCount; + + uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom]; + + if (USBFS_OUT_BUFFER_FULL == USBFS_EP[epNumber].apiEpState) + { + bytesCount = USBFS_GetEPCount(epNumber); + } + else + { + bytesCount = 0u; + } + + return (bytesCount); +} + + +/******************************************************************************* +* Function Name: USBFS_DataIsReady +****************************************************************************//** +* +* This function returns a non-zero value if the component received data or +* received zero-length packet. The USBFS_GetAll() or +* USBFS_GetData() API should be called to read data from the buffer +* and reinitialize the OUT endpoint even when a zero-length packet is +* received. These APIs will return zero value when zero-length packet is +* received. +* +* \return +* If the OUT packet is received, this function returns a non-zero value. +* Otherwise, it returns zero. +* +* \globalvars +* USBFS_cdcDataOutEp: CDC OUT endpoint number used. +* +*******************************************************************************/ +uint8 USBFS_DataIsReady(void) +{ + return (USBFS_GetEPState(USBFS_cdcDataOutEp[USBFS_activeCom])); +} + + +/******************************************************************************* +* Function Name: USBFS_CDCIsReady +****************************************************************************//** +* +* This function returns a non-zero value if the component is ready to send more +* data to the PC; otherwise, it returns zero. The function should be called +* before sending new data when using any of the following APIs: +* USBFS_PutData(),USBFS_PutString(), +* USBFS_PutChar or USBFS_PutCRLF(), +* to be sure that the previous data has finished sending. +* +* \return +* If the buffer can accept new data, this function returns a non-zero value. +* Otherwise, it returns zero. +* +* \globalvars +* USBFS_cdcDataInEp: CDC IN endpoint number used. +* +*******************************************************************************/ +uint8 USBFS_CDCIsReady(void) +{ + return (USBFS_GetEPState(USBFS_cdcDataInEp[USBFS_activeCom])); +} + + +/*************************************************************************** +* Function Name: USBFS_GetData +************************************************************************//** +* +* This function gets a specified number of bytes from the input buffer and +* places them in a data array specified by the passed pointer. +* The USBFS_DataIsReady() API should be called first, to be sure +* that data is received from the host. If all received data will not be read at +* once, the unread data will be lost. The USBFS_GetData() API should +* be called to get the number of bytes that were received. +* +* \param pData: Pointer to the data array where data will be placed. +* \param Length: Number of bytes to read into the data array from the RX buffer. +* Maximum length is limited by the the number of received bytes +* or 64 bytes. +* +* \return +* Number of bytes which function moves from endpoint RAM into the +* data array. The function moves fewer than the requested number +* of bytes if the host sends fewer bytes than requested or sends +* zero-length packet. +* +* \globalvars +* USBFS_cdcDataOutEp: CDC OUT endpoint number used. +* +* \reentrant +* No. +* +***************************************************************************/ +uint16 USBFS_GetData(uint8* pData, uint16 length) +{ + uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom]; + + /* Read data from OUT endpoint buffer. */ + length = USBFS_ReadOutEP(epNumber, pData, length); + +#if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* Wait until DMA complete transferring data from OUT endpoint buffer. */ + while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(epNumber)) + { + } + + /* Enable OUT endpoint to communicate with host. */ + USBFS_EnableOutEP(epNumber); +#endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + return (length); +} + + +/******************************************************************************* +* Function Name: USBFS_GetAll +****************************************************************************//** +* +* This function gets all bytes of received data from the input buffer and +* places them into a specified data array. The +* USBFS_DataIsReady() API should be called first, to be sure +* that data is received from the host. +* +* \param pData: Pointer to the data array where data will be placed. +* +* \return +* Number of bytes received. The maximum amount of the received at a time +* data is 64 bytes. +* +* \globalvars +* - \ref USBFS_cdcDataOutEp: CDC OUT endpoint number used. +* - \ref USBFS_EP[].bufferSize: EP max packet size is used as a +* length to read all data from the EP buffer. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint16 USBFS_GetAll(uint8* pData) +{ + uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom]; + uint16 dataLength; + + /* Read data from OUT endpoint buffer. */ + dataLength = USBFS_ReadOutEP(epNumber, pData, USBFS_EP[epNumber].bufferSize); + +#if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* Wait until DMA complete transferring data from OUT endpoint buffer. */ + while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(epNumber)) + { + } + + /* Enable OUT endpoint to communicate with host. */ + USBFS_EnableOutEP(epNumber); +#endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + return (dataLength); +} + + +/*************************************************************************** +* Function Name: USBFS_GetChar +************************************************************************//** +* +* This function reads one byte of received data from the buffer. If more than +* one byte has been received from the host, the rest of the data will be lost. +* +* \return +* Received one character. +* +* \globalvars +* USBFS_cdcDataOutEp: CDC OUT endpoint number used. +* +* \reentrant +* No. +* +***************************************************************************/ +uint8 USBFS_GetChar(void) +{ + uint8 rxData; + uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom]; + + (void) USBFS_ReadOutEP(epNumber, &rxData, 1u); + +#if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* Wait until DMA complete transferring data from OUT endpoint buffer. */ + while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(epNumber)) + { + } + + /* Enable OUT endpoint to communicate with host. */ + USBFS_EnableOutEP(epNumber); +#endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + return (rxData); +} + + +/******************************************************************************* +* Function Name: USBFS_IsLineChanged +****************************************************************************//** +* +* This function returns clear on read status of the line. It returns not zero +* value when the host sends updated coding or control information to the +* device. The USBFS_GetDTERate(), USBFS_GetCharFormat() +* or USBFS_GetParityType() or USBFS_GetDataBits() API +* should be called to read data coding information. +* The USBFS_GetLineControl() API should be called to read line +* control information. +* +* \return +* If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE requests are received, it +* returns a non-zero value. Otherwise, it returns zero. +* Return Value | Description +* -----------------------------|-------------------------- +* USBUART_LINE_CODING_CHANGED | Line coding changed +* USBUART_LINE_CONTROL_CHANGED | Line control changed +* +* \globalvars +* - \ref USBFS_transferState: it is checked to be sure then OUT +* data phase has been complete, and data written to the lineCoding or +* Control Bitmap buffer. +* - \ref USBFS_linesChanged: used as a flag to be aware that +* Host has been sent request for changing Line Coding or Control Bitmap. +* +*******************************************************************************/ +uint8 USBFS_IsLineChanged(void) +{ + uint8 state = 0u; + + /* transferState is checked to be sure then OUT data phase has been complete */ + if (USBFS_transferState == USBFS_TRANS_STATE_IDLE) + { + if (USBFS_linesChanged[USBFS_activeCom] != 0u) + { + state = USBFS_linesChanged[USBFS_activeCom]; + USBFS_linesChanged[USBFS_activeCom] = 0u; + } + } + + return (state); +} + + +/*************************************************************************** +* Function Name: USBFS_GetDTERate +************************************************************************//** +* +* This function returns the data terminal rate set for this port in bits +* per second. +* +* \return +* Returns a uint32 value of the data rate in bits per second. +* +* \globalvars +* USBFS_linesCoding: First four bytes converted to uint32 +* depend on compiler, and returned as a data rate. +* +*******************************************************************************/ +uint32 USBFS_GetDTERate(void) +{ + uint32 rate; + + rate = USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE + 3u]; + rate = (rate << 8u) | USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE + 2u]; + rate = (rate << 8u) | USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE + 1u]; + rate = (rate << 8u) | USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE]; + + return (rate); +} + + +/******************************************************************************* +* Function Name: USBFS_GetCharFormat +****************************************************************************//** +* +* Returns the number of stop bits. +* +* \return +* Returns the number of stop bits. +* Return |Value Description +* ---------------------|------------------- +* USBUART_1_STOPBIT | 1 stop bit +* USBUART_1_5_STOPBITS | 1,5 stop bits +* USBUART_2_STOPBITS | 2 stop bits +* +* +* \globalvars +* USBFS_linesCoding: used to get a parameter. +* +*******************************************************************************/ +uint8 USBFS_GetCharFormat(void) +{ + return (USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_STOP_BITS]); +} + + +/******************************************************************************* +* Function Name: USBFS_GetParityType +****************************************************************************//** +* +* This function returns the parity type for the CDC port. +* +* \return +* Returns the parity type. +* Return | Value Description +* ----------------------|------------------- +* USBUART_PARITY_NONE | 1 stop bit +* USBUART_PARITY_ODD | 1,5 stop bits +* USBUART_PARITY_EVEN | 2 stop bits +* USBUART_PARITY_MARK | Mark +* USBUART_PARITY_SPACE | Space +* +* \globalvars +* USBFS_linesCoding: used to get a parameter. +* +*******************************************************************************/ +uint8 USBFS_GetParityType(void) +{ + return (USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_PARITY]); +} + + +/*************************************************************************** +* Function Name: USBFS_GetDataBits +************************************************************************//** +* +* This function returns the number of data bits for the CDC port. +* +* \return +* Returns the number of data bits. +* The number of data bits can be 5, 6, 7, 8 or 16. +* +* \globalvars +* USBFS_linesCoding: used to get a parameter. +* +*******************************************************************************/ +uint8 USBFS_GetDataBits(void) +{ + return (USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_DATA_BITS]); +} + + +/*************************************************************************** +* Function Name: USBFS_GetLineControl +************************************************************************//** +* +* This function returns Line control bitmap that the host sends to the +* device. +* +* \return +* Returns Line control bitmap. +* Return |Value Notes +* -------------------------|----------------------------------------------- +* USBUART_LINE_CONTROL_DTR |Indicates that a DTR signal is present. This signal corresponds to V.24 signal 108/2 and RS232 signal DTR. +* USBUART_LINE_CONTROL_RTS |Carrier control for half-duplex modems. This signal corresponds to V.24 signal 105 and RS232 signal RTS. +* RESERVED |The rest of the bits are reserved. +* +* *Note* Some terminal emulation programs do not properly handle these +* control signals. They update information about DTR and RTS state only +* when the RTS signal changes the state. +* +* \globalvars +* USBFS_linesControlBitmap: used to get a parameter. +* +*******************************************************************************/ +uint16 USBFS_GetLineControl(void) +{ + return (USBFS_linesControlBitmap[USBFS_activeCom]); +} + + +/******************************************************************************* +* Function Name: USBFS_SendSerialState +****************************************************************************//** +* +* Sends the serial state notification to the host using the interrupt +* endpoint for the COM port selected using the API SetComPort().The +* USBFS_NotificationIsReady() API must be called to check if the +* Component is ready to send more serial state to the host. The API will +* not send the notification data if the interrupt endpoint Max Packet Size +* is less than the required 10 bytes. +* +* \param uint16 serialState +* 16-bit value that will be sent from the device to the +* host as SERIAL_STATE notification using the IN interrupt endpoint. Refer +* to revision 1.2 of the CDC PSTN Subclass specification for bit field +* definitions of the 16-bit serial state value. +* +*******************************************************************************/ +void USBFS_SendSerialState (uint16 serialState) +{ + uint8 epNumber = USBFS_cdcCommInInterruptEp[USBFS_activeCom]; + + if(USBFS_SERIAL_STATE_SIZE <= USBFS_EP[epNumber].bufferSize) + { + /* Save current SERIAL_STATE bitmap. */ + USBFS_serialStateBitmap[USBFS_activeCom] = serialState; + + /* Add interface number */ + USBFS_serialStateNotification.wIndex = USBFS_EP[epNumber].interface; + + /*Form SERIAL_STATE data*/ + USBFS_serialStateNotification.wSerialState = LO8(USBFS_serialStateBitmap[USBFS_activeCom]); + USBFS_serialStateNotification.wSerialStateMSB = HI8(USBFS_serialStateBitmap[USBFS_activeCom]); + + USBFS_LoadInEP(epNumber, (uint8 *) &USBFS_serialStateNotification, sizeof(USBFS_serialStateNotification)); + } +} + + +/******************************************************************************* +* Function Name: USBFS_GetSerialState +****************************************************************************//** +* +* This function returns the current serial state value for the COM port +* selected using the API SetComPort(). +* +* \return +* 16-bit serial state value. Refer to revision 1.2 of the CDC PSTN Subclass +* specification for bit field definitions of the 16-bit serial state value. +* +*******************************************************************************/ +uint16 USBFS_GetSerialState(void) +{ + return USBFS_serialStateBitmap[USBFS_activeCom]; +} + + +/******************************************************************************* +* Function Name: USBFS_NotificationIsReady +****************************************************************************//** +* +* This function returns a non-zero value if the Component is ready to send +* more notifications to the host; otherwise, it returns zero. The function +* should be called before sending new notifications when using +* USBFS_SendSerialState() to ensure that any previous +* notification data has been already sent to the host. +* +* \return +* If the buffer can accept new data(endpoint buffer not full), this +* function returns a non-zero value. Otherwise, it returns zero. +* +* \globalvars +* USBFS_cdcDataInEp: CDC IN endpoint number used. +* +*******************************************************************************/ +uint8 USBFS_NotificationIsReady(void) +{ + return (USBFS_EP[USBFS_cdcCommInInterruptEp[USBFS_activeCom]].apiEpState); +} + + +/******************************************************************************* +* Function Name: USBFS_SetComPort +****************************************************************************//** +* +* This function allows the user to select from one of the two COM ports +* they wish to address in the instance of having multiple COM ports +* instantiated though the use of a composite device. Once set, all future +* function calls related to the USBUART will be affected. This addressed +* COM port can be changed during run time. +* +* \param comNumber +* Contains the COM interface the user wishes to address. Value can either +* be 0 or 1 since a maximum of only 2 COM ports can be supported. Note that +* this COM port number is not the COM port number assigned on the PC side +* for the UART communication. If a value greater than 1 is passed, the +* function returns without performing any action. +* +*******************************************************************************/ +void USBFS_SetComPort(uint8 comNumber) +{ + if ((USBFS_activeCom != comNumber) && \ + (comNumber < USBFS_MAX_MULTI_COM_NUM )) + { + USBFS_activeCom = comNumber; + } +} + + +/******************************************************************************* +* Function Name: USBFS_GetComPort +****************************************************************************//** +* +* This function returns the current selected COM port that the user is +* currently addressing in the instance of having multiple COM ports +* instantiated though the use of a composite device. +* +* \return +* Returns the currently selected COM port. Value can either be 0 or 1 since +* a maximum of only 2 COM ports can be supported. . Note that this COM port +* number is not the COM port number assigned on the PC side for the UART +* communication. +* +*******************************************************************************/ +uint8 USBFS_GetComPort(void) +{ + return (USBFS_activeCom); +} + + +#endif /* (USBFS_ENABLE_CDC_CLASS_API) */ + + +/*************************************************************************** +* Function Name: USBFS_Cdc_EpInit +************************************************************************//** +* +* \internal +* This routine decide type of endpoint (IN, OUT, Notification) and same to +* appropriate global variables according to COM port number. +* USBFS_cdcDataInEp[], USBFS_cdcCommInInterruptEp[], +* USBFS_cdcDataOutEp[] +* +* \param pEP: Pointer to structure with current EP description. +* \param epNum: EP number +* \param cdcComNums: Bit array of current COM ports for CDC IN, OUT, +* and notification EPs(0 - COM port 1, 1- COM port 2) +* +* \return +* Updated cdcComNums +* +* \reentrant +* No. +* +***************************************************************************/ +uint8 USBFS_Cdc_EpInit(const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP, uint8 epNum, uint8 cdcComNums) +{ + uint8 epType; + + epType = pEP->attributes & USBFS_EP_TYPE_MASK; + + if (0u != (pEP->addr & USBFS_DIR_IN)) + { + if (epType != USBFS_EP_TYPE_INT) + { + USBFS_cdcDataInEp[USBFS_GET_EP_COM_NUM(cdcComNums, USBFS_CDC_IN_EP)] = epNum; + cdcComNums |= (uint8)(USBFS_COM_PORT2 << USBFS_CDC_IN_EP); + } + else + { + + USBFS_cdcCommInInterruptEp[USBFS_GET_EP_COM_NUM(cdcComNums, USBFS_CDC_NOTE_EP)] = epNum; + cdcComNums |= (uint8)(USBFS_COM_PORT2 << USBFS_CDC_NOTE_EP); + } + } + else + { + if (epType != USBFS_EP_TYPE_INT) + { + USBFS_cdcDataOutEp[USBFS_GET_EP_COM_NUM(cdcComNums, USBFS_CDC_OUT_EP)] = epNum; + cdcComNums |= (uint8)(USBFS_COM_PORT2 << USBFS_CDC_OUT_EP); + } + } + return (cdcComNums); +} + + +/******************************************************************************* +* Additional user functions supporting CDC Requests +********************************************************************************/ + +/* `#START CDC_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* (USBFS_ENABLE_CDC_CLASS) */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_cdc.h b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_cdc.h new file mode 100644 index 0000000000..58d724c6e3 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_cdc.h @@ -0,0 +1,149 @@ +/***************************************************************************//** +* \file USBFS_cdc.h +* \version 3.20 +* +* \brief +* This file provides function prototypes and constants for the USBFS component +* CDC class. +* +* Related Document: +* Universal Serial Bus Class Definitions for Communication Devices Version 1.1 +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_USBFS_USBFS_cdc_H) +#define CY_USBFS_USBFS_cdc_H + +#include "USBFS.h" + + +/******************************************************************************* +* Prototypes of the USBFS_cdc API. +*******************************************************************************/ +/** +* \addtogroup group_cdc +* @{ +*/ +#if (USBFS_ENABLE_CDC_CLASS_API != 0u) + uint8 USBFS_CDC_Init(void) ; + void USBFS_PutData(const uint8* pData, uint16 length) ; + void USBFS_PutString(const char8 string[]) ; + void USBFS_PutChar(char8 txDataByte) ; + void USBFS_PutCRLF(void) ; + uint16 USBFS_GetCount(void) ; + uint8 USBFS_CDCIsReady(void) ; + uint8 USBFS_DataIsReady(void) ; + uint16 USBFS_GetData(uint8* pData, uint16 length) ; + uint16 USBFS_GetAll(uint8* pData) ; + uint8 USBFS_GetChar(void) ; + uint8 USBFS_IsLineChanged(void) ; + uint32 USBFS_GetDTERate(void) ; + uint8 USBFS_GetCharFormat(void) ; + uint8 USBFS_GetParityType(void) ; + uint8 USBFS_GetDataBits(void) ; + uint16 USBFS_GetLineControl(void) ; + void USBFS_SendSerialState (uint16 serialState) ; + uint16 USBFS_GetSerialState (void) ; + void USBFS_SetComPort (uint8 comNumber) ; + uint8 USBFS_GetComPort (void) ; + uint8 USBFS_NotificationIsReady(void) ; + +#endif /* (USBFS_ENABLE_CDC_CLASS_API) */ +/** @} cdc */ + +/******************************************************************************* +* Constants for USBFS_cdc API. +*******************************************************************************/ + +/* CDC Class-Specific Request Codes (CDC ver 1.2 Table 19) */ +#define USBFS_CDC_SET_LINE_CODING (0x20u) +#define USBFS_CDC_GET_LINE_CODING (0x21u) +#define USBFS_CDC_SET_CONTROL_LINE_STATE (0x22u) + +/*PSTN Subclass Specific Notifications (CDC ver 1.2 Table 30)*/ +#define USBFS_SERIAL_STATE (0x20u) + +#define USBFS_LINE_CODING_CHANGED (0x01u) +#define USBFS_LINE_CONTROL_CHANGED (0x02u) + +#define USBFS_1_STOPBIT (0x00u) +#define USBFS_1_5_STOPBITS (0x01u) +#define USBFS_2_STOPBITS (0x02u) + +#define USBFS_PARITY_NONE (0x00u) +#define USBFS_PARITY_ODD (0x01u) +#define USBFS_PARITY_EVEN (0x02u) +#define USBFS_PARITY_MARK (0x03u) +#define USBFS_PARITY_SPACE (0x04u) + +#define USBFS_LINE_CODING_SIZE (0x07u) +#define USBFS_LINE_CODING_RATE (0x00u) +#define USBFS_LINE_CODING_STOP_BITS (0x04u) +#define USBFS_LINE_CODING_PARITY (0x05u) +#define USBFS_LINE_CODING_DATA_BITS (0x06u) + +#define USBFS_LINE_CONTROL_DTR (0x01u) +#define USBFS_LINE_CONTROL_RTS (0x02u) + +//#define USBFS_MAX_MULTI_COM_NUM (2u) +#define USBFS_MAX_MULTI_COM_NUM (1u) + +#define USBFS_COM_PORT1 (0u) +#define USBFS_COM_PORT2 (1u) + +#define USBFS_SUCCESS (0u) +#define USBFS_FAILURE (1u) + +#define USBFS_SERIAL_STATE_SIZE (10u) + +/* SerialState constants*/ +#define USBFS_SERIAL_STATE_REQUEST_TYPE (0xA1u) +#define USBFS_SERIAL_STATE_LENGTH (0x2u) + +/******************************************************************************* +* External data references +*******************************************************************************/ +/** +* \addtogroup group_cdc +* @{ +*/ +extern volatile uint8 USBFS_linesCoding[USBFS_MAX_MULTI_COM_NUM][USBFS_LINE_CODING_SIZE]; +extern volatile uint8 USBFS_linesChanged[USBFS_MAX_MULTI_COM_NUM]; +extern volatile uint16 USBFS_linesControlBitmap[USBFS_MAX_MULTI_COM_NUM]; +extern volatile uint16 USBFS_serialStateBitmap[USBFS_MAX_MULTI_COM_NUM]; +extern volatile uint8 USBFS_cdcDataInEp[USBFS_MAX_MULTI_COM_NUM]; +extern volatile uint8 USBFS_cdcDataOutEp[USBFS_MAX_MULTI_COM_NUM]; +extern volatile uint8 USBFS_cdcCommInInterruptEp[USBFS_MAX_MULTI_COM_NUM]; +/** @} cdc */ + +/******************************************************************************* +* The following code is DEPRECATED and +* must not be used. +*******************************************************************************/ + + +#define USBFS_lineCoding USBFS_linesCoding[0] +#define USBFS_lineChanged USBFS_linesChanged[0] +#define USBFS_lineControlBitmap USBFS_linesControlBitmap[0] +#define USBFS_cdc_data_in_ep USBFS_cdcDataInEp[0] +#define USBFS_cdc_data_out_ep USBFS_cdcDataOutEp[0] + +#endif /* (CY_USBFS_USBFS_cdc_H) */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_cls.c b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_cls.c new file mode 100644 index 0000000000..e1084ab85e --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_cls.c @@ -0,0 +1,156 @@ +/***************************************************************************//** +* \file USBFS_cls.c +* \version 3.20 +* +* \brief +* This file contains the USB Class request handler. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "USBFS_pvt.h" + + +#if(USBFS_EXTERN_CLS == USBFS_FALSE) + +/*************************************** +* User Implemented Class Driver Declarations. +***************************************/ +/* `#START USER_DEFINED_CLASS_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_DispatchClassRqst +****************************************************************************//** +* This routine dispatches class specific requests depend on interface class. +* +* \return +* requestHandled. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchClassRqst(void) +{ + uint8 interfaceNumber; + uint8 requestHandled = USBFS_FALSE; + + /* Get interface to which request is intended. */ + switch (USBFS_bmRequestTypeReg & USBFS_RQST_RCPT_MASK) + { + case USBFS_RQST_RCPT_IFC: + /* Class-specific request directed to interface: wIndexLoReg + * contains interface number. + */ + interfaceNumber = (uint8) USBFS_wIndexLoReg; + break; + + case USBFS_RQST_RCPT_EP: + /* Class-specific request directed to endpoint: wIndexLoReg contains + * endpoint number. Find interface related to endpoint. + */ + interfaceNumber = USBFS_EP[USBFS_wIndexLoReg & USBFS_DIR_UNUSED].interface; + break; + + default: + /* Default interface is zero. */ + interfaceNumber = 0u; + break; + } + + /* Check that interface is within acceptable range */ + if (interfaceNumber <= USBFS_MAX_INTERFACES_NUMBER) + { + #if (defined(USBFS_ENABLE_HID_CLASS) || \ + defined(USBFS_ENABLE_AUDIO_CLASS) || \ + defined(USBFS_ENABLE_CDC_CLASS) || \ + USBFS_ENABLE_MSC_CLASS) + + /* Handle class request depends on interface type. */ + switch (USBFS_interfaceClass[interfaceNumber]) + { + #if defined(USBFS_ENABLE_HID_CLASS) + case USBFS_CLASS_HID: + requestHandled = USBFS_DispatchHIDClassRqst(); + break; + #endif /* (USBFS_ENABLE_HID_CLASS) */ + + #if defined(USBFS_ENABLE_AUDIO_CLASS) + case USBFS_CLASS_AUDIO: + requestHandled = USBFS_DispatchAUDIOClassRqst(); + break; + #endif /* (USBFS_CLASS_AUDIO) */ + + #if defined(USBFS_ENABLE_CDC_CLASS) + case USBFS_CLASS_CDC: + requestHandled = USBFS_DispatchCDCClassRqst(); + break; + #endif /* (USBFS_ENABLE_CDC_CLASS) */ + + #if (USBFS_ENABLE_MSC_CLASS) + case USBFS_CLASS_MSD: + #if (USBFS_HANDLE_MSC_REQUESTS) + /* MSC requests are handled by the component. */ + requestHandled = USBFS_DispatchMSCClassRqst(); + #elif defined(USBFS_DISPATCH_MSC_CLASS_RQST_CALLBACK) + /* MSC requests are handled by user defined callbcak. */ + requestHandled = USBFS_DispatchMSCClassRqst_Callback(); + #else + /* MSC requests are not handled. */ + requestHandled = USBFS_FALSE; + #endif /* (USBFS_HANDLE_MSC_REQUESTS) */ + break; + #endif /* (USBFS_ENABLE_MSC_CLASS) */ + + default: + /* Request is not handled: unknown class request type. */ + requestHandled = USBFS_FALSE; + break; + } + #endif /* Class support is enabled */ + } + + /* `#START USER_DEFINED_CLASS_CODE` Place your Class request here */ + + /* `#END` */ + +#ifdef USBFS_DISPATCH_CLASS_RQST_CALLBACK + if (USBFS_FALSE == requestHandled) + { + requestHandled = USBFS_DispatchClassRqst_Callback(interfaceNumber); + } +#endif /* (USBFS_DISPATCH_CLASS_RQST_CALLBACK) */ + + return (requestHandled); +} + + +/******************************************************************************* +* Additional user functions supporting Class Specific Requests +********************************************************************************/ + +/* `#START CLASS_SPECIFIC_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* USBFS_EXTERN_CLS */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_cydmac.h b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_cydmac.h new file mode 100644 index 0000000000..9c691a4cb3 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_cydmac.h @@ -0,0 +1,287 @@ +/***************************************************************************//** +* \file USBFS_cydmac.h +* \version 3.20 +* +* \brief +* This file provides macros implemenation of DMA_P4 functions. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_USBFS_USBFS_cydmac_H) +#define CY_USBFS_USBFS_cydmac_H + +#include "USBFS_pvt.h" + +/******************************************************************************* +* Function Name: USBFS_CyDmaSetConfiguration +****************************************************************************//** +* +* Sets configuration information for the specified descriptor. +* +* \param ch: DMA ch modified by this function. +* \param descr: Descriptor (0 or 1) modified by this function. +* \param cfg: Descriptor control register. +* +* \sideeffect +* The status register associated with the specified descriptor is reset to +* zero after this function call. This function should not be called while +* the descriptor is active. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +#define USBFS_CyDmaSetConfiguration(ch, descr, cfg) \ + do{ \ + CYDMA_DESCR_BASE.descriptor[ch][descr].ctl = (cfg); \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaSetInterruptMask +****************************************************************************//** +* +* Enables the DMA channel interrupt. +* +* \param ch: Channel used by this function. +* +* +*******************************************************************************/ +#define USBFS_CyDmaSetInterruptMask(ch) \ + do{ \ + CYDMA_INTR_MASK_REG |= ((uint32)(1UL << (ch))); \ + }while(0) + + +/******************************************************************************* +* Function Name:USBFS_CyDmaSetDescriptor0Next +****************************************************************************//** +* +* Sets the descriptor 0 that should be run the next time the channel is +* triggered. +* +* \param channel: Channel used by this function. +* +* +*******************************************************************************/ +#define USBFS_CyDmaSetDescriptor0Next(ch) \ + do{ \ + CYDMA_CH_CTL_BASE.ctl[(ch)] &= (uint32) ~CYDMA_DESCRIPTOR; \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaSetNumDataElements +****************************************************************************//** +* +* Sets the number of data elements to transfer for specified descriptor. +* +* \param ch: Channel used by this function. +* \param descr: Descriptor (0 or 1) modified by this function. +* \param numEl: Total number of data elements this descriptor transfers - 1u. +* Valid ranges are 0 to 65535. +* +* +* \sideeffect +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +#define USBFS_CyDmaSetNumDataElements(ch, descr, numEl) \ + do{ \ + CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].ctl = \ + ((CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].ctl & (uint32) ~CYDMA_DATA_NR) | ((uint32) (numEl))); \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaGetSrcAddress +****************************************************************************//** +* +* Returns the source address for the specified descriptor. +* +* \param ch: Channel used by this function. +* \param descr: Specifies descriptor (0 or 1) used by this function. +* +* \return +* Source address written to specified descriptor. +* +*******************************************************************************/ +#define USBFS_CyDmaGetSrcAddress(ch, descr) CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].src + + +/******************************************************************************* +* Function Name: USBFS_CyDmaSetSrcAddress +****************************************************************************//** +* +* Configures the source address for the specified descriptor. +* +* \param ch: Channel used by this function. +* \param descr: Descriptor (0 or 1) modified by this function. +* \param srcAddress: Address of DMA transfer source. +* +* +* \sideeffect +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +#define USBFS_CyDmaSetSrcAddress(ch, descr, srcAddress) \ + do{ \ + CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].src = (srcAddress); \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaGetDstAddress +****************************************************************************//** +* +* Returns the destination address for the specified descriptor, set by +* CyDmaSetDstAddress(). +* +* \param ch: Channel used by this function. +* \param descr: Specifies descriptor (0 or 1) used by this function. +* +* \return +* Destination address written to specified descriptor. +* +*******************************************************************************/ +#define USBFS_CyDmaGetDstAddress(ch, descr) CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].dst + + +/******************************************************************************* +* Function Name: USBFS_CyDmaSetDstAddress +****************************************************************************//** +* +* Configures the destination address for the specified descriptor. +* +* \param ch: Channel used by this function. +* \param descr: Descriptor (0 or 1) modified by this function. +* \param dstAddress: Address of DMA transfer destination. +* +* +* \sideeffect +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +#define USBFS_CyDmaSetDstAddress(ch, descr, dstAddress) \ + do{ \ + CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].dst = (dstAddress); \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaValidateDescriptor +****************************************************************************//** +* +* Validates the specified descriptor after it has been invalidated. +* +* \param ch: Channel used by this function. +* \param descr: Descriptor (0 or 1) modified by this function. +* +* +* \sideeffect +* The status register associated with the specified descriptor is reset to +* zero after this function call. +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +#define USBFS_CyDmaValidateDescriptor(ch, descr) \ + do{ \ + CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].status = CYDMA_VALID; \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaChEnable +****************************************************************************//** +* +* Enables the DMA ch. +* +* \param ch: Channel used by this function. +* +* +* \sideeffect +* If this function is called before DMA is completely configured the operation +* of the DMA is undefined and could result in system data corruption. +* +*******************************************************************************/ +#define USBFS_CyDmaChEnable(ch) \ + do{ \ + CYDMA_CH_CTL_BASE.ctl[(ch)] |= CYDMA_ENABLED; \ + }while(0) + + +/******************************************************************************* +* Function Name: CyDmaChDisable +****************************************************************************//** +* +* Disables the DMA ch. +* +* \param ch: Channel used by this function. +* +* +* \sideeffect +* If this function is called during a DMA transfer the transfer is aborted. +* +*******************************************************************************/ +#define USBFS_CyDmaChDisable(ch) \ + do{ \ + CYDMA_CH_CTL_BASE.ctl[(ch)] &= (uint32) ~CYDMA_ENABLED; \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaTriggerIn +****************************************************************************//** +* +* Triggers the DMA channel to execute a transfer. The tr_in signal is +* triggered. +* +* \param trSel: trigger to be activated. +* +* +*******************************************************************************/ +#define USBFS_DMA_USB_REQ_TR_OUT (0xC0020100U) +#define USBFS_CyDmaTriggerIn(trSel) \ + do{ \ + CYDMA_TR_CTL_REG = USBFS_DMA_USB_REQ_TR_OUT | (uint32)(trSel); \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaTriggerOut +****************************************************************************//** +* +* Triggers the DMA channel to generate a transfer completion signal without +* actual transfer executed. The tr_out signal is triggered. +* +* \param trSel: trigger to be activated. +* +* +*******************************************************************************/ +#define USBFS_DMA_USB_BURST_END_TR_OUT (0xC0020300U) +#define USBFS_CyDmaTriggerOut(trSel) \ + do{ \ + CYDMA_TR_CTL_REG = USBFS_DMA_USB_BURST_END_TR_OUT | (uint32)(trSel); \ + }while(0) + + +#endif /* (CY_USBFS_USBFS_cydmac_H) */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_descr.c b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_descr.c new file mode 100644 index 0000000000..135e8e1438 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_descr.c @@ -0,0 +1,587 @@ +/***************************************************************************//** +* \file USBFS_descr.c +* \version 3.20 +* +* \brief +* This file contains the USB descriptors and storage. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "USBFS_pvt.h" + + +/***************************************************************************** +* User supplied descriptors. If you want to specify your own descriptors, +* define USER_SUPPLIED_DESCRIPTORS below and add your descriptors. +*****************************************************************************/ +/* `#START USER_DESCRIPTORS_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/*************************************** +* USB Customizer Generated Descriptors +***************************************/ + +#if !defined(USER_SUPPLIED_DESCRIPTORS) +/********************************************************************* +* Device Descriptors +*********************************************************************/ +const uint8 CYCODE USBFS_DEVICE0_DESCR[18u] = { +/* Descriptor Length */ 0x12u, +/* DescriptorType: DEVICE */ 0x01u, +/* bcdUSB (ver 2.0) */ 0x00u, 0x02u, +#if defined(DAPLINK_IF) +/* bDeviceClass */ 0xEFu, +/* bDeviceSubClass */ 0x02u, +/* bDeviceProtocol */ 0x01u, +#else +/* bDeviceClass */ 0x00u, +/* bDeviceSubClass */ 0x00u, +/* bDeviceProtocol */ 0x00u, +#endif +/* bMaxPacketSize0 */ 0x08u, +/* idVendor */ 0x28u, 0x0Du, +/* idProduct */ 0x04u, 0x02u, +/* bcdDevice */ 0x00u, 0x01u, +/* iManufacturer */ 0x01u, +/* iProduct */ 0x02u, +/* iSerialNumber */ 0x80u, +/* bNumConfigurations */ 0x01u +}; +/********************************************************************* +* Config Descriptor +*********************************************************************/ +#if defined(DAPLINK_IF) +const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[130u] = { +/* Config Descriptor Length */ 0x09u, +/* DescriptorType: CONFIG */ 0x02u, +/* wTotalLength */ 0x82u, 0x00u, +/* bNumInterfaces */ 0x04u, +/* bConfigurationValue */ 0x01u, +/* iConfiguration */ 0x02u, +/* bmAttributes */ 0x80u, +/* bMaxPower */ 0xC8u, +#else +const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[32u] = { +/* Config Descriptor Length */ 0x09u, +/* DescriptorType: CONFIG */ 0x02u, +/* wTotalLength */ 0x20u, 0x00u, +/* bNumInterfaces */ 0x01u, +/* bConfigurationValue */ 0x01u, +/* iConfiguration */ 0x02u, +/* bmAttributes */ 0x80u, +/* bMaxPower */ 0xC8u, +#endif +/********************************************************************* +* MSC Interface Descriptor +*********************************************************************/ +/* Interface Descriptor Length */ 0x09u, +/* DescriptorType: INTERFACE */ 0x04u, +/* bInterfaceNumber */ 0x00u, +/* bAlternateSetting */ 0x00u, +/* bNumEndpoints */ 0x02u, +/* bInterfaceClass */ 0x08u, +/* bInterfaceSubClass */ 0x06u, +/* bInterfaceProtocol */ 0x50u, +/* iInterface */ 0x05u, +/********************************************************************* +* Endpoint Descriptor +*********************************************************************/ +/* Endpoint Descriptor Length */ 0x07u, +/* DescriptorType: ENDPOINT */ 0x05u, +/* bEndpointAddress */ 0x81u, +/* bmAttributes */ 0x02u, +/* wMaxPacketSize */ 0x40u, 0x00u, +/* bInterval */ 0x00u, +/********************************************************************* +* Endpoint Descriptor +*********************************************************************/ +/* Endpoint Descriptor Length */ 0x07u, +/* DescriptorType: ENDPOINT */ 0x05u, +/* bEndpointAddress */ 0x02u, +/* bmAttributes */ 0x02u, +/* wMaxPacketSize */ 0x40u, 0x00u, +#if defined(DAPLINK_IF) +/* bInterval */ 0x00u, +/********************************************************************* +* Interface Association Descriptor +*********************************************************************/ +/* Interface Association Descriptor Length*/ 0x08u, +/* DescriptorType: INTERFACE ASSOCIATION */ 0x0Bu, +/* bFirstInterface */ 0x01u, +/* bInterfaceCount */ 0x02u, +/* bFunctionClass */ 0x02u, +/* bFunctionSubClass */ 0x02u, +/* bFunctionProtocol */ 0x01u, +/* iFunction */ 0x00u, +/********************************************************************* +* CDC Interface Descriptor +*********************************************************************/ +/* Interface Descriptor Length */ 0x09u, +/* DescriptorType: INTERFACE */ 0x04u, +/* bInterfaceNumber */ 0x01u, +/* bAlternateSetting */ 0x00u, +/* bNumEndpoints */ 0x01u, +/* bInterfaceClass */ 0x02u, +/* bInterfaceSubClass */ 0x02u, +/* bInterfaceProtocol */ 0x01u, +/* iInterface */ 0x07u, +/********************************************************************* +* Header Descriptor +*********************************************************************/ +/* Header Descriptor Length */ 0x05u, +/* DescriptorType: CS_INTERFACE */ 0x24u, +/* bDescriptorSubtype */ 0x00u, +/* bcdADC */ 0x10u, 0x01u, +/********************************************************************* +* Call Management Descriptor +*********************************************************************/ +/* Call Management Descriptor Length */ 0x05u, +/* DescriptorType: CS_INTERFACE */ 0x24u, +/* bDescriptorSubtype */ 0x01u, +/* bmCapabilities */ 0x03u, +/* bDataInterface */ 0x02u, +/********************************************************************* +* Abstract Control Management Descriptor +*********************************************************************/ +/* Abstract Control Management Descriptor Length*/ 0x04u, +/* DescriptorType: CS_INTERFACE */ 0x24u, +/* bDescriptorSubtype */ 0x02u, +/* bmCapabilities */ 0x06u, +/********************************************************************* +* Union Descriptor +*********************************************************************/ +/* Union Descriptor Length */ 0x05u, +/* DescriptorType: CS_INTERFACE */ 0x24u, +/* bDescriptorSubtype */ 0x06u, +/* bControlInterface */ 0x01u, +/* bSubordinateInterface */ 0x02u, +/********************************************************************* +* Endpoint Descriptor +*********************************************************************/ +/* Endpoint Descriptor Length */ 0x07u, +/* DescriptorType: ENDPOINT */ 0x05u, +/* bEndpointAddress */ 0x83u, +/* bmAttributes */ 0x03u, +/* wMaxPacketSize */ 0x10u, 0x00u, +/* bInterval */ 0x20u, +/********************************************************************* +* Data Interface Descriptor +*********************************************************************/ +/* Interface Descriptor Length */ 0x09u, +/* DescriptorType: INTERFACE */ 0x04u, +/* bInterfaceNumber */ 0x02u, +/* bAlternateSetting */ 0x00u, +/* bNumEndpoints */ 0x02u, +/* bInterfaceClass */ 0x0Au, +/* bInterfaceSubClass */ 0x00u, +/* bInterfaceProtocol */ 0x00u, +/* iInterface */ 0x07u, +/********************************************************************* +* Endpoint Descriptor +*********************************************************************/ +/* Endpoint Descriptor Length */ 0x07u, +/* DescriptorType: ENDPOINT */ 0x05u, +/* bEndpointAddress */ 0x04u, +/* bmAttributes */ 0x02u, +/* wMaxPacketSize */ 0x40u, 0x00u, +/* bInterval */ 0x00u, +/********************************************************************* +* Endpoint Descriptor +*********************************************************************/ +/* Endpoint Descriptor Length */ 0x07u, +/* DescriptorType: ENDPOINT */ 0x05u, +/* bEndpointAddress */ 0x85u, +/* bmAttributes */ 0x02u, +/* wMaxPacketSize */ 0x40u, 0x00u, +/* bInterval */ 0x00u, +/********************************************************************* +* Interface Descriptor +*********************************************************************/ +/* Interface Descriptor Length */ 0x09u, +/* DescriptorType: INTERFACE */ 0x04u, +/* bInterfaceNumber */ 0x03u, +/* bAlternateSetting */ 0x00u, +/* bNumEndpoints */ 0x02u, +/* bInterfaceClass */ 0x03u, +/* bInterfaceSubClass */ 0x00u, +/* bInterfaceProtocol */ 0x00u, +/* iInterface */ 0x03u, +/********************************************************************* +* HID Class Descriptor +*********************************************************************/ +/* HID Class Descriptor Length */ 0x09u, +/* DescriptorType: HID_CLASS */ 0x21u, +/* bcdHID */ 0x11u, 0x01u, +/* bCountryCode */ 0x00u, +/* bNumDescriptors */ 0x01u, +/* bDescriptorType */ 0x22u, +/* wDescriptorLength (LSB) */ USBFS_HID_RPT_2_SIZE_LSB, +/* wDescriptorLength (MSB) */ USBFS_HID_RPT_2_SIZE_MSB, +/********************************************************************* +* Endpoint Descriptor +*********************************************************************/ +/* Endpoint Descriptor Length */ 0x07u, +/* DescriptorType: ENDPOINT */ 0x05u, +/* bEndpointAddress */ 0x86u, +/* bmAttributes */ 0x03u, +/* wMaxPacketSize */ 0x40u, 0x00u, +/* bInterval */ 0x01u, +/********************************************************************* +* Endpoint Descriptor +*********************************************************************/ +/* Endpoint Descriptor Length */ 0x07u, +/* DescriptorType: ENDPOINT */ 0x05u, +/* bEndpointAddress */ 0x07u, +/* bmAttributes */ 0x03u, +/* wMaxPacketSize */ 0x40u, 0x00u, +/* bInterval */ 0x01u +#else +/* bInterval */ 0x00u +#endif +}; + +/********************************************************************* +* String Descriptor Table +*********************************************************************/ +const uint8 CYCODE USBFS_STRING_DESCRIPTORS[211u] = { +/********************************************************************* +* Language ID Descriptor +*********************************************************************/ +/* Descriptor Length */ 0x04u, +/* DescriptorType: STRING */ 0x03u, +/* Language Id */ 0x09u, 0x04u, +/********************************************************************* +* String Descriptor: "ARM" +*********************************************************************/ +/* Descriptor Length */ 0x08u, +/* DescriptorType: STRING */ 0x03u, + (uint8)'A', 0u,(uint8)'R', 0u,(uint8)'M', 0u, +/********************************************************************* +* String Descriptor: "DAPLink CMSIS-DAP" +*********************************************************************/ +/* Descriptor Length */ 0x24u, +/* DescriptorType: STRING */ 0x03u, + (uint8)'D', 0u,(uint8)'A', 0u,(uint8)'P', 0u,(uint8)'L', 0u,(uint8)'i', 0u, + (uint8)'n', 0u,(uint8)'k', 0u,(uint8)' ', 0u,(uint8)'C', 0u,(uint8)'M', 0u, + (uint8)'S', 0u,(uint8)'I', 0u,(uint8)'S', 0u,(uint8)'-', 0u,(uint8)'D', 0u, + (uint8)'A', 0u,(uint8)'P', 0u, +/********************************************************************* +* String Descriptor: "CMSIS-DAP" +*********************************************************************/ +/* Descriptor Length */ 0x14u, +/* DescriptorType: STRING */ 0x03u, + (uint8)'C', 0u,(uint8)'M', 0u,(uint8)'S', 0u,(uint8)'I', 0u,(uint8)'S', 0u, + (uint8)'-', 0u,(uint8)'D', 0u,(uint8)'A', 0u,(uint8)'P', 0u, +/********************************************************************* +* String Descriptor: "WebUSB: CMSIS-DAP" +*********************************************************************/ +/* Descriptor Length */ 0x24u, +/* DescriptorType: STRING */ 0x03u, + (uint8)'W', 0u,(uint8)'e', 0u,(uint8)'b', 0u,(uint8)'U', 0u,(uint8)'S', 0u, + (uint8)'B', 0u,(uint8)':', 0u,(uint8)' ', 0u,(uint8)'C', 0u,(uint8)'M', 0u, + (uint8)'S', 0u,(uint8)'I', 0u,(uint8)'S', 0u,(uint8)'-', 0u,(uint8)'D', 0u, + (uint8)'A', 0u,(uint8)'P', 0u, +/********************************************************************* +* String Descriptor: "USB_MSC" +*********************************************************************/ +/* Descriptor Length */ 0x10u, +/* DescriptorType: STRING */ 0x03u, + (uint8)'U', 0u,(uint8)'S', 0u,(uint8)'B', 0u,(uint8)'_', 0u,(uint8)'M', 0u, + (uint8)'S', 0u,(uint8)'C', 0u, +/********************************************************************* +* String Descriptor: "MBED VFS 0.1" +*********************************************************************/ +/* Descriptor Length */ 0x38u, +/* DescriptorType: STRING */ 0x03u, + (uint8)'M', 0u,(uint8)'B', 0u,(uint8)'E', 0u,(uint8)'D', 0u,(uint8)' ', 0u, + (uint8)' ', 0u,(uint8)' ', 0u,(uint8)' ', 0u,(uint8)'V', 0u,(uint8)'F', 0u, + (uint8)'S', 0u,(uint8)' ', 0u,(uint8)' ', 0u,(uint8)' ', 0u,(uint8)' ', 0u, + (uint8)' ', 0u,(uint8)' ', 0u,(uint8)' ', 0u,(uint8)' ', 0u,(uint8)' ', 0u, + (uint8)' ', 0u,(uint8)' ', 0u,(uint8)' ', 0u,(uint8)' ', 0u,(uint8)'0', 0u, + (uint8)'.', 0u,(uint8)'1', 0u, +/********************************************************************* +* String Descriptor: "mbed Serial Port" +*********************************************************************/ +/* Descriptor Length */ 0x22u, +/* DescriptorType: STRING */ 0x03u, + (uint8)'m', 0u,(uint8)'b', 0u,(uint8)'e', 0u,(uint8)'d', 0u,(uint8)' ', 0u, + (uint8)'S', 0u,(uint8)'e', 0u,(uint8)'r', 0u,(uint8)'i', 0u,(uint8)'a', 0u, + (uint8)'l', 0u,(uint8)' ', 0u,(uint8)'P', 0u,(uint8)'o', 0u,(uint8)'r', 0u, + (uint8)'t', 0u, +/*********************************************************************/ +/* Marks the end of the list. */ 0x00u}; +/*********************************************************************/ + +/********************************************************************* +* Serial Number String Descriptor +*********************************************************************/ +const uint8 CYCODE USBFS_SN_STRING_DESCRIPTOR[26] = { +/* Descriptor Length */ 0x1Au, +/* DescriptorType: STRING */ 0x03u, +(uint8)'0', 0u,(uint8)'0', 0u,(uint8)'0', 0u,(uint8)'1', 0u,(uint8)'A', 0u, + (uint8)'0', 0u,(uint8)'0', 0u,(uint8)'0', 0u,(uint8)'0', 0u,(uint8)'0', 0u, + (uint8)'0', 0u,(uint8)'0', 0u +}; + +/********************************************************************* +* HID Report Descriptor: HID Report Descriptor +*********************************************************************/ +const uint8 CYCODE USBFS_HIDREPORT_DESCRIPTOR1[47u] = { +/* Descriptor Size (Not part of descriptor)*/ USBFS_HID_RPT_1_SIZE_LSB, +USBFS_HID_RPT_1_SIZE_MSB, +/* USAGE_PAGE */ 0x06u, 0xA0u, 0xFFu, +/* USAGE */ 0x09u, 0x01u, +/* COLLECTION */ 0xA1u, 0x01u, +/* USAGE */ 0x09u, 0x02u, +/* COLLECTION */ 0xA1u, 0x00u, +/* USAGE_MINIMUM */ 0x19u, 0x03u, +/* USAGE_MAXIMUM */ 0x29u, 0x43u, +/* LOGICAL_MINIMUM */ 0x15u, 0x00u, +/* LOGICAL_MAXIMUM */ 0x26u, 0xFFu, 0x00u, +/* REPORT_SIZE */ 0x75u, 0x08u, +/* REPORT_COUNT */ 0x95u, 0x40u, +/* OUTPUT */ 0x91u, 0x02u, +/* USAGE_MINIMUM */ 0x19u, 0x44u, +/* USAGE_MAXIMUM */ 0x29u, 0x74u, +/* LOGICAL_MINIMUM */ 0x15u, 0x00u, +/* LOGICAL_MAXIMUM */ 0x26u, 0xFFu, 0x00u, +/* REPORT_SIZE */ 0x75u, 0x08u, +/* REPORT_COUNT */ 0x95u, 0x40u, +/* INPUT */ 0x81u, 0x02u, +/* END_COLLECTION */ 0xC0u, +/* END_COLLECTION */ 0xC0u, +/*********************************************************************/ +/* End of the HID Report Descriptor */ 0x00u, 0x00u}; +/*********************************************************************/ +/********************************************************************* +* HID Report Descriptor: CMSIS-DAP HID Report Descriptor +*********************************************************************/ +const uint8 CYCODE USBFS_HIDREPORT_DESCRIPTOR2[37u] = { +/* Descriptor Size (Not part of descriptor)*/ USBFS_HID_RPT_2_SIZE_LSB, +USBFS_HID_RPT_2_SIZE_MSB, +/* USAGE_PAGE */ 0x06u, 0x00u, 0xFFu, +/* USAGE */ 0x09u, 0x01u, +/* COLLECTION */ 0xA1u, 0x01u, +/* LOGICAL_MINIMUM */ 0x15u, 0x00u, +/* LOGICAL_MAXIMUM */ 0x26u, 0xFFu, 0x00u, +/* REPORT_SIZE */ 0x75u, 0x08u, +/* REPORT_COUNT */ 0x95u, 0x40u, +/* USAGE */ 0x09u, 0x01u, +/* INPUT */ 0x81u, 0x02u, +/* REPORT_COUNT */ 0x95u, 0x40u, +/* USAGE */ 0x09u, 0x01u, +/* OUTPUT */ 0x91u, 0x02u, +/* REPORT_COUNT */ 0x95u, 0x01u, +/* USAGE */ 0x09u, 0x01u, +/* FEATURE */ 0xB1u, 0x02u, +/* END_COLLECTION */ 0xC0u, +/*********************************************************************/ +/* End of the HID Report Descriptor */ 0x00u, 0x00u}; +/*********************************************************************/ + +#if defined(DAPLINK_IF) +#if !defined(USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_HID_RPT_STORAGE) +/********************************************************************* +* HID Input Report Storage +*********************************************************************/ +T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_IN_RPT_SCB; +uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_IN_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_IN_BUF_SIZE]; + +/********************************************************************* +* HID Input Report TD Table +*********************************************************************/ +const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_IN_RPT_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_IN_BUF_SIZE, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_IN_BUF[0u], + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_IN_RPT_SCB}, +}; +/********************************************************************* +* HID Output Report Storage +*********************************************************************/ +T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_OUT_RPT_SCB; +uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_OUT_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_OUT_BUF_SIZE]; + +/********************************************************************* +* HID Output Report TD Table +*********************************************************************/ +const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_OUT_RPT_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_OUT_BUF_SIZE, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_OUT_BUF[0u], + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_OUT_RPT_SCB}, +}; +/********************************************************************* +* HID Feature Report Storage +*********************************************************************/ +T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_FEATURE_RPT_SCB; +uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_FEATURE_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_FEATURE_BUF_SIZE]; + +/********************************************************************* +* HID Feature Report TD Table +*********************************************************************/ +const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_FEATURE_RPT_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_FEATURE_BUF_SIZE, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_FEATURE_BUF[0u], + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_FEATURE_RPT_SCB}, +}; +/********************************************************************* +* HID Report Look Up Table This table has four entries: +* IN Report Table +* OUT Report Table +* Feature Report Table +* HID Report Descriptor +* HID Class Descriptor +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_TABLE[5u] = { + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_IN_RPT_TABLE}, + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_OUT_RPT_TABLE}, + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_FEATURE_RPT_TABLE}, + {0x01u, (const void *)&USBFS_HIDREPORT_DESCRIPTOR2[0]}, + {0x01u, (const void *)&USBFS_DEVICE0_CONFIGURATION0_DESCR[107]} +}; +#endif /* USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_HID_RPT_STORAGE */ + +/********************************************************************* +* Interface Dispatch Table -- Points to the Class Dispatch Tables +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_COUNT, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_TABLE} +}; +#endif +/********************************************************************* +* Endpoint Setting Table -- This table contain the endpoint setting +* for each endpoint in the configuration. It +* contains the necessary information to +* configure the endpoint hardware for each +* interface and alternate setting. +*********************************************************************/ +#if defined(DAPLINK_IF) +const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[7u] = { +/* IFC ALT EPAddr bmAttr MaxPktSize Class ********************/ +{0x00u, 0x00u, 0x81u, 0x02u, 0x0040u, 0x08u}, +{0x00u, 0x00u, 0x02u, 0x02u, 0x0040u, 0x08u}, +{0x01u, 0x00u, 0x83u, 0x03u, 0x0010u, 0x02u}, +{0x02u, 0x00u, 0x04u, 0x02u, 0x0040u, 0x0Au}, +{0x02u, 0x00u, 0x85u, 0x02u, 0x0040u, 0x0Au}, +{0x03u, 0x00u, 0x86u, 0x03u, 0x0040u, 0x03u}, +{0x03u, 0x00u, 0x07u, 0x03u, 0x0040u, 0x03u} +}; +const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[4u] = { +0x08u, 0x02u, 0x0Au, 0x03u +}; +#else +const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[2u] = { +/* IFC ALT EPAddr bmAttr MaxPktSize Class ********************/ +{0x00u, 0x00u, 0x81u, 0x02u, 0x0040u, 0x08u}, +{0x00u, 0x00u, 0x02u, 0x02u, 0x0040u, 0x08u} +}; +const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[1u] = { +0x08u +}; +#endif +/********************************************************************* +* Config Dispatch Table -- Points to the Config Descriptor and each of +* and endpoint setup table and to each +* interface table if it specifies a USB Class +*********************************************************************/ +#if defined(DAPLINK_IF) +const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[7u] = { + {0x01u, &USBFS_DEVICE0_CONFIGURATION0_DESCR}, + {0x07u, &USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE}, + {0x00u, NULL}, + {0x00u, NULL}, + {0x00u, NULL}, + {0x01u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_TABLE}, + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS} +}; +#else +const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[4u] = { + {0x01u, &USBFS_DEVICE0_CONFIGURATION0_DESCR}, + {0x02u, &USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE}, + {0x00u, NULL}, + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS} +}; +#endif +/********************************************************************* +* Device Dispatch Table -- Points to the Device Descriptor and each of +* and Configuration Tables for this Device +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[3u] = { + {0x01u, &USBFS_DEVICE0_DESCR}, + {0x00u, NULL}, + {0x01u, &USBFS_DEVICE0_CONFIGURATION0_TABLE} +}; +/********************************************************************* +* Device Table -- Indexed by the device number. +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_TABLE[1u] = { + {0x01u, &USBFS_DEVICE0_TABLE} +}; + +#endif /* USER_SUPPLIED_DESCRIPTORS */ + +#if defined(USBFS_ENABLE_MSOS_STRING) + + /****************************************************************************** + * USB Microsoft OS String Descriptor + * "MSFT" identifies a Microsoft host + * "100" specifies version 1.00 + * USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR becomes the bRequest value + * in a host vendor device/class request + ******************************************************************************/ + + const uint8 CYCODE USBFS_MSOS_DESCRIPTOR[USBFS_MSOS_DESCRIPTOR_LENGTH] = { + /* Descriptor Length */ 0x12u, + /* DescriptorType: STRING */ 0x03u, + /* qwSignature - "MSFT100" */ (uint8)'M', 0u, (uint8)'S', 0u, (uint8)'F', 0u, (uint8)'T', 0u, + (uint8)'1', 0u, (uint8)'0', 0u, (uint8)'0', 0u, + /* bMS_VendorCode: */ USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR, + /* bPad */ 0x00u + }; + + /* Extended Configuration Descriptor */ + + const uint8 CYCODE USBFS_MSOS_CONFIGURATION_DESCR[USBFS_MSOS_CONF_DESCR_LENGTH] = { + /* Length of the descriptor 4 bytes */ 0x28u, 0x00u, 0x00u, 0x00u, + /* Version of the descriptor 2 bytes */ 0x00u, 0x01u, + /* wIndex - Fixed:INDEX_CONFIG_DESCRIPTOR */ 0x04u, 0x00u, + /* bCount - Count of device functions. */ 0x01u, + /* Reserved : 7 bytes */ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + /* bFirstInterfaceNumber */ 0x00u, + /* Reserved */ 0x01u, + /* compatibleID - "CYUSB\0\0" */ (uint8)'C', (uint8)'Y', (uint8)'U', (uint8)'S', (uint8)'B', + 0x00u, 0x00u, 0x00u, + /* subcompatibleID - "00001\0\0" */ (uint8)'0', (uint8)'0', (uint8)'0', (uint8)'0', (uint8)'1', + 0x00u, 0x00u, 0x00u, + /* Reserved : 6 bytes */ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u + }; + +#endif /* USBFS_ENABLE_MSOS_STRING */ + +/* DIE ID string descriptor for 8 bytes ID */ +#if defined(USBFS_ENABLE_IDSN_STRING) + uint8 USBFS_idSerialNumberStringDescriptor[USBFS_IDSN_DESCR_LENGTH]; +#endif /* USBFS_ENABLE_IDSN_STRING */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_drv.c b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_drv.c new file mode 100644 index 0000000000..272e10c99f --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_drv.c @@ -0,0 +1,811 @@ +/***************************************************************************//** +* \file USBFS_drv.c +* \version 3.20 +* +* \brief +* This file contains the Endpoint 0 Driver for the USBFS Component. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "USBFS_pvt.h" + +#include "usbd_PSoC5LP.h" + +/*************************************** +* Global data allocation +***************************************/ + +volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP]; + +/** Contains the current configuration number, which is set by the host using a + * SET_CONFIGURATION request. This variable is initialized to zero in + * USBFS_InitComponent() API and can be read by the USBFS_GetConfiguration() + * API.*/ +volatile uint8 USBFS_configuration; + +/** Contains the current interface number.*/ +volatile uint8 USBFS_interfaceNumber; + +/** This variable is set to one after SET_CONFIGURATION and SET_INTERFACE + *requests. It can be read by the USBFS_IsConfigurationChanged() API */ +volatile uint8 USBFS_configurationChanged; + +/** Contains the current device address.*/ +volatile uint8 USBFS_deviceAddress; + +/** This is a two-bit variable that contains power status in the bit 0 + * (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote wakeup + * status (DEVICE_STATUS_REMOTE_WAKEUP) in the bit 1. This variable is + * initialized to zero in USBFS_InitComponent() API, configured by the + * USBFS_SetPowerStatus() API. The remote wakeup status cannot be set using the + * API SetPowerStatus(). */ +volatile uint8 USBFS_deviceStatus; + +volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER]; +volatile uint8 USBFS_interfaceSetting_last[USBFS_MAX_INTERFACES_NUMBER]; +volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER]; + +/** Contains the started device number. This variable is set by the + * USBFS_Start() or USBFS_InitComponent() APIs.*/ +volatile uint8 USBFS_device; + +/** Initialized class array for each interface. It is used for handling Class + * specific requests depend on interface class. Different classes in multiple + * alternate settings are not supported.*/ +const uint8 CYCODE *USBFS_interfaceClass; + + +/*************************************** +* Local data allocation +***************************************/ + +volatile uint8 USBFS_ep0Toggle; +volatile uint8 USBFS_lastPacketSize; + +/** This variable is used by the communication functions to handle the current +* transfer state. +* Initialized to TRANS_STATE_IDLE in the USBFS_InitComponent() API and after a +* complete transfer in the status stage. +* Changed to the TRANS_STATE_CONTROL_READ or TRANS_STATE_CONTROL_WRITE in setup +* transaction depending on the request type. +*/ +volatile uint8 USBFS_transferState; +volatile T_USBFS_TD USBFS_currentTD; +volatile uint8 USBFS_ep0Mode; +volatile uint8 USBFS_ep0Count; +volatile uint16 USBFS_transferByteCount; + + +/******************************************************************************* +* Function Name: USBFS_ep_0_Interrupt +****************************************************************************//** +* +* This Interrupt Service Routine handles Endpoint 0 (Control Pipe) traffic. +* It dispatches setup requests and handles the data and status stages. +* +* +*******************************************************************************/ +CY_ISR(USBFS_EP_0_ISR) +{ + uint8 tempReg; + uint8 modifyReg; + +#ifdef USBFS_EP_0_ISR_ENTRY_CALLBACK + USBFS_EP_0_ISR_EntryCallback(); +#endif /* (USBFS_EP_0_ISR_ENTRY_CALLBACK) */ + + tempReg = USBFS_EP0_CR_REG; + if ((tempReg & USBFS_MODE_ACKD) != 0u) + { + modifyReg = 1u; + if ((tempReg & USBFS_MODE_SETUP_RCVD) != 0u) + { + if ((tempReg & USBFS_MODE_MASK) != USBFS_MODE_NAK_IN_OUT) + { + /* Mode not equal to NAK_IN_OUT: invalid setup */ + modifyReg = 0u; + } + else + { + USBFS_HandleSetup(); + + if ((USBFS_ep0Mode & USBFS_MODE_SETUP_RCVD) != 0u) + { + /* SETUP bit set: exit without mode modificaiton */ + modifyReg = 0u; + } + } + } + else if ((tempReg & USBFS_MODE_IN_RCVD) != 0u) + { + USBFS_HandleIN(); + } + else if ((tempReg & USBFS_MODE_OUT_RCVD) != 0u) + { + USBFS_HandleOUT(); + } + else + { + modifyReg = 0u; + } + + /* Modify the EP0_CR register */ + if (modifyReg != 0u) + { + + tempReg = USBFS_EP0_CR_REG; + + /* Make sure that SETUP bit is cleared before modification */ + if ((tempReg & USBFS_MODE_SETUP_RCVD) == 0u) + { + /* Update count register */ + tempReg = (uint8) USBFS_ep0Toggle | USBFS_ep0Count; + USBFS_EP0_CNT_REG = tempReg; + + /* Make sure that previous write operaiton was successful */ + if (tempReg == USBFS_EP0_CNT_REG) + { + /* Repeat until next successful write operation */ + do + { + /* Init temporary variable */ + modifyReg = USBFS_ep0Mode; + + /* Unlock register */ + tempReg = (uint8) (USBFS_EP0_CR_REG & USBFS_MODE_SETUP_RCVD); + + /* Check if SETUP bit is not set */ + if (0u == tempReg) + { + /* Set the Mode Register */ + USBFS_EP0_CR_REG = USBFS_ep0Mode; + + /* Writing check */ + modifyReg = USBFS_EP0_CR_REG & USBFS_MODE_MASK; + } + } + while (modifyReg != USBFS_ep0Mode); + } + } + } + } + + USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_EP0_INTR); + +#ifdef USBFS_EP_0_ISR_EXIT_CALLBACK + USBFS_EP_0_ISR_ExitCallback(); +#endif /* (USBFS_EP_0_ISR_EXIT_CALLBACK) */ +} + + +/******************************************************************************* +* Function Name: USBFS_HandleSetup +****************************************************************************//** +* +* This Routine dispatches requests for the four USB request types +* +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_HandleSetup(void) +{ + uint8 requestHandled; + + /* Clear register lock by SIE (read register) and clear setup bit + * (write any value in register). + */ + requestHandled = (uint8) USBFS_EP0_CR_REG; + USBFS_EP0_CR_REG = (uint8) requestHandled; + requestHandled = (uint8) USBFS_EP0_CR_REG; + + if ((requestHandled & USBFS_MODE_SETUP_RCVD) != 0u) + { + /* SETUP bit is set: exit without mode modification. */ + USBFS_ep0Mode = requestHandled; + } + else + { + /* In case the previous transfer did not complete, close it out */ + USBFS_UpdateStatusBlock(USBFS_XFER_PREMATURE); + + /* Check request type. */ + switch (USBFS_bmRequestTypeReg & USBFS_RQST_TYPE_MASK) + { + case USBFS_RQST_TYPE_STD: + requestHandled = USBFS_HandleStandardRqst(); + break; + + case USBFS_RQST_TYPE_CLS: + requestHandled = USBFS_DispatchClassRqst(); + break; + + case USBFS_RQST_TYPE_VND: + requestHandled = USBFS_HandleVendorRqst(); + break; + + default: + requestHandled = USBFS_FALSE; + break; + } + + /* If request is not recognized. Stall endpoint 0 IN and OUT. */ + if (requestHandled == USBFS_FALSE) + { + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; + } + } +} + + +/******************************************************************************* +* Function Name: USBFS_HandleIN +****************************************************************************//** +* +* This routine handles EP0 IN transfers. +* +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_HandleIN(void) +{ + switch (USBFS_transferState) + { + case USBFS_TRANS_STATE_IDLE: + break; + + case USBFS_TRANS_STATE_CONTROL_READ: + USBFS_ControlReadDataStage(); + break; + + case USBFS_TRANS_STATE_CONTROL_WRITE: + USBFS_ControlWriteStatusStage(); + break; + + case USBFS_TRANS_STATE_NO_DATA_CONTROL: + USBFS_NoDataControlStatusStage(); + break; + + default: /* there are no more states */ + break; + } +} + + +/******************************************************************************* +* Function Name: USBFS_HandleOUT +****************************************************************************//** +* +* This routine handles EP0 OUT transfers. +* +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_HandleOUT(void) +{ + switch (USBFS_transferState) + { + case USBFS_TRANS_STATE_IDLE: + break; + + case USBFS_TRANS_STATE_CONTROL_READ: + USBFS_ControlReadStatusStage(); + break; + + case USBFS_TRANS_STATE_CONTROL_WRITE: + USBFS_ControlWriteDataStage(); + break; + + case USBFS_TRANS_STATE_NO_DATA_CONTROL: + /* Update the completion block */ + USBFS_UpdateStatusBlock(USBFS_XFER_ERROR); + + /* We expect no more data, so stall INs and OUTs */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; + break; + + default: + /* There are no more states */ + break; + } +} + + +/******************************************************************************* +* Function Name: USBFS_LoadEP0 +****************************************************************************//** +* +* This routine loads the EP0 data registers for OUT transfers. It uses the +* currentTD (previously initialized by the _InitControlWrite function and +* updated for each OUT transfer, and the bLastPacketSize) to determine how +* many uint8s to transfer on the current OUT. +* +* If the number of uint8s remaining is zero and the last transfer was full, +* we need to send a zero length packet. Otherwise we send the minimum +* of the control endpoint size (8) or remaining number of uint8s for the +* transaction. +* +* +* \globalvars +* USBFS_transferByteCount - Update the transfer byte count from the +* last transaction. +* USBFS_ep0Count - counts the data loaded to the SIE memory in +* current packet. +* USBFS_lastPacketSize - remembers the USBFS_ep0Count value for the +* next packet. +* USBFS_transferByteCount - sum of the previous bytes transferred +* on previous packets(sum of USBFS_lastPacketSize) +* USBFS_ep0Toggle - inverted +* USBFS_ep0Mode - prepare for mode register content. +* USBFS_transferState - set to TRANS_STATE_CONTROL_READ +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_LoadEP0(void) +{ + uint8 ep0Count = 0u; + + /* Update the transfer byte count from the last transaction */ + USBFS_transferByteCount += USBFS_lastPacketSize; + + /* Now load the next transaction */ + while ((USBFS_currentTD.count > 0u) && (ep0Count < 8u)) + { + USBFS_EP0_DR_BASE.epData[ep0Count] = (uint8) *USBFS_currentTD.pData; + USBFS_currentTD.pData = &USBFS_currentTD.pData[1u]; + ep0Count++; + USBFS_currentTD.count--; + } + + /* Support zero-length packet */ + if ((USBFS_lastPacketSize == 8u) || (ep0Count > 0u)) + { + /* Update the data toggle */ + USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE; + /* Set the Mode Register */ + USBFS_ep0Mode = USBFS_MODE_ACK_IN_STATUS_OUT; + /* Update the state (or stay the same) */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + } + else + { + /* Expect Status Stage Out */ + USBFS_ep0Mode = USBFS_MODE_STATUS_OUT_ONLY; + /* Update the state (or stay the same) */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + } + + /* Save the packet size for next time */ + USBFS_ep0Count = (uint8) ep0Count; + USBFS_lastPacketSize = (uint8) ep0Count; +} + + +/******************************************************************************* +* Function Name: USBFS_InitControlRead +****************************************************************************//** +* +* Initialize a control read transaction. It is used to send data to the host. +* The following global variables should be initialized before this function +* called. To send zero length packet use InitZeroLengthControlTransfer +* function. +* +* +* \return +* requestHandled state. +* +* \globalvars +* USBFS_currentTD.count - counts of data to be sent. +* USBFS_currentTD.pData - data pointer. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_InitControlRead(void) +{ + uint16 xferCount; + + if (USBFS_currentTD.count == 0u) + { + (void) USBFS_InitZeroLengthControlTransfer(); + } + else + { + /* Set up the state machine */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + + /* Set the toggle, it gets updated in LoadEP */ + USBFS_ep0Toggle = 0u; + + /* Initialize the Status Block */ + USBFS_InitializeStatusBlock(); + + xferCount = ((uint16)((uint16) USBFS_lengthHiReg << 8u) | ((uint16) USBFS_lengthLoReg)); + + if (USBFS_currentTD.count > xferCount) + { + USBFS_currentTD.count = xferCount; + } + + USBFS_LoadEP0(); + } + + return (USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_InitZeroLengthControlTransfer +****************************************************************************//** +* +* Initialize a zero length data IN transfer. +* +* \return +* requestHandled state. +* +* \globalvars +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* USBFS_ep0Mode - prepare for mode register content. +* USBFS_transferState - set to TRANS_STATE_CONTROL_READ +* USBFS_ep0Count - cleared, means the zero-length packet. +* USBFS_lastPacketSize - cleared. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_InitZeroLengthControlTransfer(void) + +{ + /* Update the state */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + + /* Set the data toggle */ + USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; + + /* Set the Mode Register */ + USBFS_ep0Mode = USBFS_MODE_ACK_IN_STATUS_OUT; + + /* Save the packet size for next time */ + USBFS_lastPacketSize = 0u; + + USBFS_ep0Count = 0u; + + return (USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_ControlReadDataStage +****************************************************************************//** +* +* Handle the Data Stage of a control read transfer. +* +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_ControlReadDataStage(void) + +{ + USBFS_LoadEP0(); +} + + +/******************************************************************************* +* Function Name: USBFS_ControlReadStatusStage +****************************************************************************//** +* +* Handle the Status Stage of a control read transfer. +* +* +* \globalvars +* USBFS_USBFS_transferByteCount - updated with last packet size. +* USBFS_transferState - set to TRANS_STATE_IDLE. +* USBFS_ep0Mode - set to MODE_STALL_IN_OUT. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_ControlReadStatusStage(void) +{ + /* Update the transfer byte count */ + USBFS_transferByteCount += USBFS_lastPacketSize; + + /* Go Idle */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + + /* Update the completion block */ + USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); + + /* We expect no more data, so stall INs and OUTs */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; +} + + +/******************************************************************************* +* Function Name: USBFS_InitControlWrite +****************************************************************************//** +* +* Initialize a control write transaction +* +* \return +* requestHandled state. +* +* \globalvars +* USBFS_USBFS_transferState - set to TRANS_STATE_CONTROL_WRITE +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_InitControlWrite(void) +{ + uint16 xferCount; + + /* Set up the state machine */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_WRITE; + + /* This might not be necessary */ + USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; + + /* Initialize the Status Block */ + USBFS_InitializeStatusBlock(); + + xferCount = ((uint16)((uint16) USBFS_lengthHiReg << 8u) | ((uint16) USBFS_lengthLoReg)); + + if (USBFS_currentTD.count > xferCount) + { + USBFS_currentTD.count = xferCount; + } + + /* Expect Data or Status Stage */ + USBFS_ep0Mode = USBFS_MODE_ACK_OUT_STATUS_IN; + + return(USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_ControlWriteDataStage +****************************************************************************//** +* +* Handle the Data Stage of a control write transfer +* 1. Get the data (We assume the destination was validated previously) +* 2. Update the count and data toggle +* 3. Update the mode register for the next transaction +* +* +* \globalvars +* USBFS_transferByteCount - Update the transfer byte count from the +* last transaction. +* USBFS_ep0Count - counts the data loaded from the SIE memory +* in current packet. +* USBFS_transferByteCount - sum of the previous bytes transferred +* on previous packets(sum of USBFS_lastPacketSize) +* USBFS_ep0Toggle - inverted +* USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_ControlWriteDataStage(void) +{ + uint8 ep0Count; + uint8 regIndex = 0u; + + ep0Count = (USBFS_EP0_CNT_REG & USBFS_EPX_CNT0_MASK) - USBFS_EPX_CNTX_CRC_COUNT; + + USBFS_transferByteCount += (uint8)ep0Count; + + while ((USBFS_currentTD.count > 0u) && (ep0Count > 0u)) + { + *USBFS_currentTD.pData = (uint8) USBFS_EP0_DR_BASE.epData[regIndex]; + USBFS_currentTD.pData = &USBFS_currentTD.pData[1u]; + regIndex++; + ep0Count--; + USBFS_currentTD.count--; + } + + USBFS_ep0Count = (uint8)ep0Count; + + /* Update the data toggle */ + USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE; + + /* Expect Data or Status Stage */ + USBFS_ep0Mode = USBFS_MODE_ACK_OUT_STATUS_IN; +} + + +/******************************************************************************* +* Function Name: USBFS_ControlWriteStatusStage +****************************************************************************//** +* +* Handle the Status Stage of a control write transfer +* +* \globalvars +* USBFS_transferState - set to TRANS_STATE_IDLE. +* USBFS_USBFS_ep0Mode - set to MODE_STALL_IN_OUT. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_ControlWriteStatusStage(void) +{ + /* Go Idle */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + + /* Update the completion block */ + USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); + + /* We expect no more data, so stall INs and OUTs */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; + + if ( SetLineCodingReq ) + { + SetLineCodingReq = false; + USBFS_CDCClassRqst_Callback(); + } +} + + +/******************************************************************************* +* Function Name: USBFS_InitNoDataControlTransfer +****************************************************************************//** +* +* Initialize a no data control transfer +* +* \return +* requestHandled state. +* +* \globalvars +* USBFS_transferState - set to TRANS_STATE_NO_DATA_CONTROL. +* USBFS_ep0Mode - set to MODE_STATUS_IN_ONLY. +* USBFS_ep0Count - cleared. +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_InitNoDataControlTransfer(void) +{ + USBFS_transferState = USBFS_TRANS_STATE_NO_DATA_CONTROL; + USBFS_ep0Mode = USBFS_MODE_STATUS_IN_ONLY; + USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; + USBFS_ep0Count = 0u; + + return (USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_NoDataControlStatusStage +****************************************************************************//** +* Handle the Status Stage of a no data control transfer. +* +* SET_ADDRESS is special, since we need to receive the status stage with +* the old address. +* +* \globalvars +* USBFS_transferState - set to TRANS_STATE_IDLE. +* USBFS_ep0Mode - set to MODE_STALL_IN_OUT. +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* USBFS_deviceAddress - used to set new address and cleared +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_NoDataControlStatusStage(void) +{ + if (0u != USBFS_deviceAddress) + { + /* Update device address if we got new address. */ + USBFS_CR0_REG = (uint8) USBFS_deviceAddress | USBFS_CR0_ENABLE; + USBFS_deviceAddress = 0u; + } + + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + + /* Update the completion block. */ + USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); + + /* Stall IN and OUT, no more data is expected. */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; +} + + +/******************************************************************************* +* Function Name: USBFS_UpdateStatusBlock +****************************************************************************//** +* +* Update the Completion Status Block for a Request. The block is updated +* with the completion code the USBFS_transferByteCount. The +* StatusBlock Pointer is set to NULL. +* +* completionCode - status. +* +* +* \globalvars +* USBFS_currentTD.pStatusBlock->status - updated by the +* completionCode parameter. +* USBFS_currentTD.pStatusBlock->length - updated. +* USBFS_currentTD.pStatusBlock - cleared. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_UpdateStatusBlock(uint8 completionCode) +{ + if (USBFS_currentTD.pStatusBlock != NULL) + { + USBFS_currentTD.pStatusBlock->status = completionCode; + USBFS_currentTD.pStatusBlock->length = USBFS_transferByteCount; + USBFS_currentTD.pStatusBlock = NULL; + } +} + + +/******************************************************************************* +* Function Name: USBFS_InitializeStatusBlock +****************************************************************************//** +* +* Initialize the Completion Status Block for a Request. The completion +* code is set to USB_XFER_IDLE. +* +* Also, initializes USBFS_transferByteCount. Save some space, +* this is the only consumer. +* +* \globalvars +* USBFS_currentTD.pStatusBlock->status - set to XFER_IDLE. +* USBFS_currentTD.pStatusBlock->length - cleared. +* USBFS_transferByteCount - cleared. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_InitializeStatusBlock(void) +{ + USBFS_transferByteCount = 0u; + + if (USBFS_currentTD.pStatusBlock != NULL) + { + USBFS_currentTD.pStatusBlock->status = USBFS_XFER_IDLE; + USBFS_currentTD.pStatusBlock->length = 0u; + } +} + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_episr.c b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_episr.c new file mode 100644 index 0000000000..ce3b5f8817 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_episr.c @@ -0,0 +1,1363 @@ +/***************************************************************************//** +* \file USBFS_episr.c +* \version 3.20 +* +* \brief +* This file contains the Data endpoint Interrupt Service Routines. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "USBFS_pvt.h" +#include "USBFS_cydmac.h" + + + +/*************************************** +* Custom Declarations +***************************************/ +/* `#START CUSTOM_DECLARATIONS` Place your declaration here */ +#include "usbd_PSoC5LP.h" +/* `#END` */ + + +#if (USBFS_EP1_ISR_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP_1_ISR + ***************************************************************************//** + * + * Endpoint 1 Interrupt Service Routine + * + ******************************************************************************/ + CY_ISR(USBFS_EP_1_ISR) + { + + #ifdef USBFS_EP_1_ISR_ENTRY_CALLBACK + USBFS_EP_1_ISR_EntryCallback(); + #endif /* (USBFS_EP_1_ISR_ENTRY_CALLBACK) */ + + /* `#START EP1_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + { + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP1_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to be read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP1].addr & USBFS_DIR_IN)) + #endif /* (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP1].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP1) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP1].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP1].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == USBFS_EP1) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ + + /* `#START EP1_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_1_ISR_EXIT_CALLBACK + USBFS_EP_1_ISR_ExitCallback(); + #endif /* (USBFS_EP_1_ISR_EXIT_CALLBACK) */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + } + +#endif /* (USBFS_EP1_ISR_ACTIVE) */ + + +#if (USBFS_EP2_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_EP_2_ISR + ****************************************************************************//** + * + * Endpoint 2 Interrupt Service Routine. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_2_ISR) + { + #ifdef USBFS_EP_2_ISR_ENTRY_CALLBACK + USBFS_EP_2_ISR_EntryCallback(); + #endif /* (USBFS_EP_2_ISR_ENTRY_CALLBACK) */ + + /* `#START EP2_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + { + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP2_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to be read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP2].addr & USBFS_DIR_IN)) + #endif /* (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP2].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP2) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP2].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP2].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == USBFS_EP2) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ + + /* `#START EP2_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_2_ISR_EXIT_CALLBACK + USBFS_EP_2_ISR_ExitCallback(); + #endif /* (USBFS_EP_2_ISR_EXIT_CALLBACK) */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + } +#endif /* (USBFS_EP2_ISR_ACTIVE) */ + + +#if (USBFS_EP3_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_EP_3_ISR + ****************************************************************************//** + * + * Endpoint 3 Interrupt Service Routine. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_3_ISR) + { + #ifdef USBFS_EP_3_ISR_ENTRY_CALLBACK + USBFS_EP_3_ISR_EntryCallback(); + #endif /* (USBFS_EP_3_ISR_ENTRY_CALLBACK) */ + + /* `#START EP3_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + { + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP3_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to be read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP3].addr & USBFS_DIR_IN)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP3].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP3) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP3].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP3].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == USBFS_EP3) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ + + /* `#START EP3_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_3_ISR_EXIT_CALLBACK + USBFS_EP_3_ISR_ExitCallback(); + #endif /* (USBFS_EP_3_ISR_EXIT_CALLBACK) */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + } +#endif /* (USBFS_EP3_ISR_ACTIVE) */ + + +#if (USBFS_EP4_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_EP_4_ISR + ****************************************************************************//** + * + * Endpoint 4 Interrupt Service Routine. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_4_ISR) + { + #ifdef USBFS_EP_4_ISR_ENTRY_CALLBACK + USBFS_EP_4_ISR_EntryCallback(); + #endif /* (USBFS_EP_4_ISR_ENTRY_CALLBACK) */ + + /* `#START EP4_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + { + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP4_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP4].addr & USBFS_DIR_IN)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP4].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP4) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP4].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP4].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP4) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ + + /* `#START EP4_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_4_ISR_EXIT_CALLBACK + USBFS_EP_4_ISR_ExitCallback(); + #endif /* (USBFS_EP_4_ISR_EXIT_CALLBACK) */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + } +#endif /* (USBFS_EP4_ISR_ACTIVE) */ + + +#if (USBFS_EP5_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_EP_5_ISR + ****************************************************************************//** + * + * Endpoint 5 Interrupt Service Routine + * + * + *******************************************************************************/ + CY_ISR(USBFS_EP_5_ISR) + { + #ifdef USBFS_EP_5_ISR_ENTRY_CALLBACK + USBFS_EP_5_ISR_EntryCallback(); + #endif /* (USBFS_EP_5_ISR_ENTRY_CALLBACK) */ + + /* `#START EP5_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + { + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP5_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP5].addr & USBFS_DIR_IN)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP5].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP5) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP5].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP5].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == USBFS_EP5) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ + + /* `#START EP5_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_5_ISR_EXIT_CALLBACK + USBFS_EP_5_ISR_ExitCallback(); + #endif /* (USBFS_EP_5_ISR_EXIT_CALLBACK) */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + } +#endif /* (USBFS_EP5_ISR_ACTIVE) */ + + +#if (USBFS_EP6_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_EP_6_ISR + ****************************************************************************//** + * + * Endpoint 6 Interrupt Service Routine. + * + * + *******************************************************************************/ + CY_ISR(USBFS_EP_6_ISR) + { + #ifdef USBFS_EP_6_ISR_ENTRY_CALLBACK + USBFS_EP_6_ISR_EntryCallback(); + #endif /* (USBFS_EP_6_ISR_ENTRY_CALLBACK) */ + + /* `#START EP6_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + { + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP6_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP6].addr & USBFS_DIR_IN)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP6].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP6) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP6].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP6].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == USBFS_EP6) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ + + /* `#START EP6_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_6_ISR_EXIT_CALLBACK + USBFS_EP_6_ISR_ExitCallback(); + #endif /* (USBFS_EP_6_ISR_EXIT_CALLBACK) */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + } +#endif /* (USBFS_EP6_ISR_ACTIVE) */ + + +#if (USBFS_EP7_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_EP_7_ISR + ****************************************************************************//** + * + * Endpoint 7 Interrupt Service Routine. + * + * + *******************************************************************************/ + CY_ISR(USBFS_EP_7_ISR) + { + #ifdef USBFS_EP_7_ISR_ENTRY_CALLBACK + USBFS_EP_7_ISR_EntryCallback(); + #endif /* (USBFS_EP_7_ISR_ENTRY_CALLBACK) */ + + /* `#START EP7_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + { + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP7_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP7].addr & USBFS_DIR_IN)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP7].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP7) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP7].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP7].apiEpState = USBFS_EVENT_PENDING; + } + + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP7) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ + + /* `#START EP7_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_7_ISR_EXIT_CALLBACK + USBFS_EP_7_ISR_ExitCallback(); + #endif /* (USBFS_EP_7_ISR_EXIT_CALLBACK) */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + } +#endif /* (USBFS_EP7_ISR_ACTIVE) */ + + +#if (USBFS_EP8_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_EP_8_ISR + ****************************************************************************//** + * + * Endpoint 8 Interrupt Service Routine + * + * + *******************************************************************************/ + CY_ISR(USBFS_EP_8_ISR) + { + #ifdef USBFS_EP_8_ISR_ENTRY_CALLBACK + USBFS_EP_8_ISR_EntryCallback(); + #endif /* (USBFS_EP_8_ISR_ENTRY_CALLBACK) */ + + /* `#START EP8_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + { + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP8_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP8].addr & USBFS_DIR_IN)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP8].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP8) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP8].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP8].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == USBFS_EP8) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ + + /* `#START EP8_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_8_ISR_EXIT_CALLBACK + USBFS_EP_8_ISR_ExitCallback(); + #endif /* (USBFS_EP_8_ISR_EXIT_CALLBACK) */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + } +#endif /* (USBFS_EP8_ISR_ACTIVE) */ + + +#if (USBFS_SOF_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_SOF_ISR + ****************************************************************************//** + * + * Start of Frame Interrupt Service Routine. + * + * + *******************************************************************************/ + CY_ISR(USBFS_SOF_ISR) + { + #ifdef USBFS_SOF_ISR_ENTRY_CALLBACK + USBFS_SOF_ISR_EntryCallback(); + #endif /* (USBFS_SOF_ISR_ENTRY_CALLBACK) */ + + /* `#START SOF_USER_CODE` Place your code here */ + + /* `#END` */ + + USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_SOF_INTR); + + #ifdef USBFS_SOF_ISR_EXIT_CALLBACK + USBFS_SOF_ISR_ExitCallback(); + #endif /* (USBFS_SOF_ISR_EXIT_CALLBACK) */ + } +#endif /* (USBFS_SOF_ISR_ACTIVE) */ + + +#if (USBFS_BUS_RESET_ISR_ACTIVE) +/******************************************************************************* +* Function Name: USBFS_BUS_RESET_ISR +****************************************************************************//** +* +* USB Bus Reset Interrupt Service Routine. Calls _Start with the same +* parameters as the last USER call to _Start +* +* +*******************************************************************************/ +CY_ISR(USBFS_BUS_RESET_ISR) +{ +#ifdef USBFS_BUS_RESET_ISR_ENTRY_CALLBACK + USBFS_BUS_RESET_ISR_EntryCallback(); +#endif /* (USBFS_BUS_RESET_ISR_ENTRY_CALLBACK) */ + + /* `#START BUS_RESET_USER_CODE` Place your code here */ + + /* `#END` */ + + USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_BUS_RESET_INTR); + + USBFS_ReInitComponent(); + +#ifdef USBFS_BUS_RESET_ISR_EXIT_CALLBACK + USBFS_BUS_RESET_ISR_ExitCallback(); +#endif /* (USBFS_BUS_RESET_ISR_EXIT_CALLBACK) */ +} +#endif /* (USBFS_BUS_RESET_ISR_ACTIVE) */ + + +#if (USBFS_LPM_ACTIVE) +/*************************************************************************** +* Function Name: USBFS_INTR_LPM_ISR +************************************************************************//** +* +* Interrupt Service Routine for LPM of the interrupt sources. +* +* +***************************************************************************/ +CY_ISR(USBFS_LPM_ISR) +{ +#ifdef USBFS_LPM_ISR_ENTRY_CALLBACK + USBFS_LPM_ISR_EntryCallback(); +#endif /* (USBFS_LPM_ISR_ENTRY_CALLBACK) */ + + /* `#START LPM_BEGIN_USER_CODE` Place your code here */ + + /* `#END` */ + + USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_LPM_INTR); + + /* `#START LPM_END_USER_CODE` Place your code here */ + + /* `#END` */ + +#ifdef USBFS_LPM_ISR_EXIT_CALLBACK + USBFS_LPM_ISR_ExitCallback(); +#endif /* (USBFS_LPM_ISR_EXIT_CALLBACK) */ +} +#endif /* (USBFS_LPM_ACTIVE) */ + + +#if (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) + /*************************************************************************** + * Function Name: USBFS_ARB_ISR + ************************************************************************//** + * + * Arbiter Interrupt Service Routine. + * + * + ***************************************************************************/ + CY_ISR(USBFS_ARB_ISR) + { + uint8 arbIntrStatus; + uint8 epStatus; + uint8 ep = USBFS_EP1; + + #ifdef USBFS_ARB_ISR_ENTRY_CALLBACK + USBFS_ARB_ISR_EntryCallback(); + #endif /* (USBFS_ARB_ISR_ENTRY_CALLBACK) */ + + /* `#START ARB_BEGIN_USER_CODE` Place your code here */ + + /* `#END` */ + + /* Get pending ARB interrupt sources. */ + arbIntrStatus = USBFS_ARB_INT_SR_REG; + + while (0u != arbIntrStatus) + { + /* Check which EP is interrupt source. */ + if (0u != (arbIntrStatus & 0x01u)) + { + /* Get endpoint enable interrupt sources. */ + epStatus = (USBFS_ARB_EP_BASE.arbEp[ep].epSr & USBFS_ARB_EP_BASE.arbEp[ep].epIntEn); + + /* Handle IN endpoint buffer full event: happens only once when endpoint buffer is loaded. */ + if (0u != (epStatus & USBFS_ARB_EPX_INT_IN_BUF_FULL)) + { + if (0u != (USBFS_EP[ep].addr & USBFS_DIR_IN)) + { + /* Clear data ready status. */ + USBFS_ARB_EP_BASE.arbEp[ep].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_IN_DATA_RDY; + + #if (CY_PSOC3 || CY_PSOC5LP) + #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) + /* Set up common area DMA with rest of data. */ + if(USBFS_inLength[ep] > USBFS_DMA_BYTES_PER_BURST) + { + USBFS_LoadNextInEP(ep, 0u); + } + else + { + USBFS_inBufFull[ep] = 1u; + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + /* Arm IN endpoint. */ + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_EP[ep].epMode; + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN) + if (ep == USBFS_midi_in_ep) + { + /* Clear MIDI input pointer. */ + USBFS_midiInPointer = 0u; + } + #endif /* (USBFS_ENABLE_MIDI_STREAMING) */ + } + } + + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* Handle DMA completion event for OUT endpoints. */ + if (0u != (epStatus & USBFS_ARB_EPX_SR_DMA_GNT)) + { + if (0u == (USBFS_EP[ep].addr & USBFS_DIR_IN)) + { + /* Notify user that data has been copied from endpoint buffer. */ + USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; + + /* DMA done coping data: OUT endpoint has to be re-armed by user. */ + } + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Handle DMA completion event for OUT endpoints. */ + if (0u != (epStatus & USBFS_ARB_EPX_INT_DMA_TERMIN)) + { + uint32 channelNum = USBFS_DmaChan[ep]; + + /* Restore burst counter for endpoint. */ + USBFS_DmaEpBurstCnt[ep] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCntBackup[ep]); + + /* Disable DMA channel to restore descriptor configuration. The on-going transfer is aborted. */ + USBFS_CyDmaChDisable(channelNum); + + /* Generate DMA tr_out signal to notify USB IP that DMA is done. This signal is not generated + * when transfer was aborted (it occurs when host writes less bytes than buffer size). + */ + USBFS_CyDmaTriggerOut(USBFS_DmaBurstEndOut[ep]); + + /* Restore destination address for output endpoint. */ + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[ep])); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[ep] + + USBFS_DMA_BYTES_PER_BURST)); + + /* Restore number of data elements to transfer which was adjusted for last burst. */ + if (0u != (USBFS_DmaEpLastBurstEl[ep] & USBFS_DMA_DESCR_REVERT)) + { + USBFS_CyDmaSetNumDataElements(channelNum, (USBFS_DmaEpLastBurstEl[ep] >> USBFS_DMA_DESCR_SHIFT), + USBFS_DMA_GET_MAX_ELEM_PER_BURST(USBFS_DmaEpLastBurstEl[ep])); + } + + /* Validate descriptor 0 and 1 (also reset current state). Command to start with descriptor 0. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + if (USBFS_DmaEpBurstCntBackup[ep] > 1u) + { + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1); + } + USBFS_CyDmaSetDescriptor0Next(channelNum); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[ep].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(ep) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[ep].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* Notify user that data has been copied from endpoint buffer. */ + USBFS_EP[ep].apiEpState = USBFS_EVENT_PENDING; + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == ep) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + } + #endif /* (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + + /* `#START ARB_USER_CODE` Place your code here for handle Buffer Underflow/Overflow */ + + /* `#END` */ + + #ifdef USBFS_ARB_ISR_CALLBACK + USBFS_ARB_ISR_Callback(ep, epStatus); + #endif /* (USBFS_ARB_ISR_CALLBACK) */ + + /* Clear serviced endpoint interrupt sources. */ + USBFS_ARB_EP_BASE.arbEp[ep].epSr = epStatus; + } + + ++ep; + arbIntrStatus >>= 1u; + } + + /* `#START ARB_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_ARB_ISR_EXIT_CALLBACK + USBFS_ARB_ISR_ExitCallback(); + #endif /* (USBFS_ARB_ISR_EXIT_CALLBACK) */ + } + +#endif /* (USBFS_ARB_ISR_ACTIVE && USBFS_EP_MANAGEMENT_DMA) */ + + +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) +#if (CY_PSOC4) + + /****************************************************************************** + * Function Name: USBFS_EPxDmaDone + ***************************************************************************//** + * + * \internal + * Endpoint DMA Done Interrupt Service Routine basic function . + * + * \param dmaCh + * number of DMA channel + * + * \param ep + * number of USB end point + * + * \param dmaDone + * transfer completion flag + * + * \return + * updated transfer completion flag + * + ******************************************************************************/ + CY_INLINE static void USBFS_EPxDmaDone(uint8 dmaCh, uint8 ep) + { + uint32 nextAddr; + + /* Manage data elements which remain to transfer. */ + if (0u != USBFS_DmaEpBurstCnt[ep]) + { + if(USBFS_DmaEpBurstCnt[ep] <= 2u) + { + /* Adjust length of last burst. */ + USBFS_CyDmaSetNumDataElements(dmaCh, + ((uint32) USBFS_DmaEpLastBurstEl[ep] >> USBFS_DMA_DESCR_SHIFT), + ((uint32) USBFS_DmaEpLastBurstEl[ep] & USBFS_DMA_BURST_BYTES_MASK)); + } + + + /* Advance source for input endpoint or destination for output endpoint. */ + if (0u != (USBFS_EP[ep].addr & USBFS_DIR_IN)) + { + /* Change source for descriptor 0. */ + nextAddr = (uint32) USBFS_CyDmaGetSrcAddress(dmaCh, USBFS_DMA_DESCR0); + nextAddr += (2u * USBFS_DMA_BYTES_PER_BURST); + USBFS_CyDmaSetSrcAddress(dmaCh, USBFS_DMA_DESCR0, (void *) nextAddr); + + /* Change source for descriptor 1. */ + nextAddr += USBFS_DMA_BYTES_PER_BURST; + USBFS_CyDmaSetSrcAddress(dmaCh, USBFS_DMA_DESCR1, (void *) nextAddr); + } + else + { + /* Change destination for descriptor 0. */ + nextAddr = (uint32) USBFS_CyDmaGetDstAddress(dmaCh, USBFS_DMA_DESCR0); + nextAddr += (2u * USBFS_DMA_BYTES_PER_BURST); + USBFS_CyDmaSetDstAddress(dmaCh, USBFS_DMA_DESCR0, (void *) nextAddr); + + /* Change destination for descriptor 1. */ + nextAddr += USBFS_DMA_BYTES_PER_BURST; + USBFS_CyDmaSetDstAddress(dmaCh, USBFS_DMA_DESCR1, (void *) nextAddr); + } + + /* Enable DMA to execute transfer as it was disabled because there were no valid descriptor. */ + USBFS_CyDmaValidateDescriptor(dmaCh, USBFS_DMA_DESCR0); + + --USBFS_DmaEpBurstCnt[ep]; + if (0u != USBFS_DmaEpBurstCnt[ep]) + { + USBFS_CyDmaValidateDescriptor(dmaCh, USBFS_DMA_DESCR1); + --USBFS_DmaEpBurstCnt[ep]; + } + + USBFS_CyDmaChEnable (dmaCh); + USBFS_CyDmaTriggerIn(USBFS_DmaReqOut[ep]); + } + else + { + /* No data to transfer. False DMA trig. Ignore. */ + } + + } + + #if (USBFS_DMA1_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP1_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 1 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP1_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP1_DMA_CH, + USBFS_EP1); + + } + #endif /* (USBFS_DMA1_ACTIVE) */ + + + #if (USBFS_DMA2_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP2_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 2 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP2_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP2_DMA_CH, + USBFS_EP2); + } + #endif /* (USBFS_DMA2_ACTIVE) */ + + + #if (USBFS_DMA3_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP3_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 3 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP3_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP3_DMA_CH, + USBFS_EP3); + } + #endif /* (USBFS_DMA3_ACTIVE) */ + + + #if (USBFS_DMA4_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP4_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 4 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP4_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP4_DMA_CH, + USBFS_EP4); + } + #endif /* (USBFS_DMA4_ACTIVE) */ + + + #if (USBFS_DMA5_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP5_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 5 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP5_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP5_DMA_CH, + USBFS_EP5); + } + #endif /* (USBFS_DMA5_ACTIVE) */ + + + #if (USBFS_DMA6_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP6_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 6 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP6_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP6_DMA_CH, + USBFS_EP6); + } + #endif /* (USBFS_DMA6_ACTIVE) */ + + + #if (USBFS_DMA7_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP7_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 7 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP7_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP7_DMA_CH, + USBFS_EP7); + } + #endif /* (USBFS_DMA7_ACTIVE) */ + + + #if (USBFS_DMA8_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP8_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 8 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP8_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP8_DMA_CH, + USBFS_EP8); + } + #endif /* (USBFS_DMA8_ACTIVE) */ + + +#else + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + /****************************************************************************** + * Function Name: USBFS_EP_DMA_DONE_ISR + ***************************************************************************//** + * + * DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + CY_ISR(USBFS_EP_DMA_DONE_ISR) + { + uint8 int8Status; + uint8 int17Status; + uint8 ep_status; + uint8 ep = USBFS_EP1; + + #ifdef USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK + USBFS_EP_DMA_DONE_ISR_EntryCallback(); + #endif /* (USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK) */ + + /* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */ + + /* `#END` */ + + /* Read clear on read status register with EP source of interrupt. */ + int17Status = USBFS_EP17_DMA_Done_SR_Read() & USBFS_EP17_SR_MASK; + int8Status = USBFS_EP8_DMA_Done_SR_Read() & USBFS_EP8_SR_MASK; + + while (int8Status != 0u) + { + while (int17Status != 0u) + { + if ((int17Status & 1u) != 0u) /* If EpX interrupt present. */ + { + /* Read Endpoint Status Register. */ + ep_status = USBFS_ARB_EP_BASE.arbEp[ep].epSr; + + if ((0u == (ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL)) && + (0u ==USBFS_inBufFull[ep])) + { + /* `#START EP_DMA_DONE_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_DMA_DONE_ISR_CALLBACK + USBFS_EP_DMA_DONE_ISR_Callback(); + #endif /* (USBFS_EP_DMA_DONE_ISR_CALLBACK) */ + + /* Transfer again 2 last bytes into pre-fetch endpoint area. */ + USBFS_ARB_EP_BASE.arbEp[ep].rwWaMsb = 0u; + USBFS_ARB_EP_BASE.arbEp[ep].rwWa = (USBFS_DMA_BYTES_PER_BURST * ep) - USBFS_DMA_BYTES_REPEAT; + USBFS_LoadNextInEP(ep, 1u); + + /* Set Data ready status to generate DMA request. */ + USBFS_ARB_EP_BASE.arbEp[ep].epCfg |= USBFS_ARB_EPX_CFG_IN_DATA_RDY; + } + } + + ep++; + int17Status >>= 1u; + } + + int8Status >>= 1u; + + if (int8Status != 0u) + { + /* Prepare pointer for EP8. */ + ep = USBFS_EP8; + int17Status = int8Status & 0x01u; + } + } + + /* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK + USBFS_EP_DMA_DONE_ISR_ExitCallback(); + #endif /* (USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK) */ + } + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ +#endif /* (CY_PSOC4) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + +#if (CY_PSOC4) + /*************************************************************************** + * Function Name: USBFS_IntrHandler + ************************************************************************//** + * + * Interrupt handler for Hi/Mid/Low ISRs. + * + * regCause - The cause register of interrupt. One of the three variants: + * USBFS_INTR_CAUSE_LO_REG - Low interrupts. + * USBFS_INTR_CAUSE_MED_REG - Med interrupts. + * USBFS_INTR_CAUSE_HI_REG - - High interrupts. + * + * + ***************************************************************************/ + CY_INLINE static void USBFS_IntrHandler(uint32 intrCause) + { + /* Array of pointers to component interrupt handlers. */ + static const cyisraddress USBFS_isrCallbacks[] = + { + + }; + + uint32 cbIdx = 0u; + + /* Check arbiter interrupt source first. */ + if (0u != (intrCause & USBFS_INTR_CAUSE_ARB_INTR)) + { + USBFS_isrCallbacks[USBFS_ARB_EP_INTR_NUM](); + } + + /* Check all other interrupt sources (except arbiter and resume). */ + intrCause = (intrCause & USBFS_INTR_CAUSE_CTRL_INTR_MASK) | + ((intrCause & USBFS_INTR_CAUSE_EP1_8_INTR_MASK) >> + USBFS_INTR_CAUSE_EP_INTR_SHIFT); + + /* Call interrupt handlers for active interrupt sources. */ + while (0u != intrCause) + { + if (0u != (intrCause & 0x1u)) + { + USBFS_isrCallbacks[cbIdx](); + } + + intrCause >>= 1u; + ++cbIdx; + } + } + + + /*************************************************************************** + * Function Name: USBFS_INTR_HI_ISR + ************************************************************************//** + * + * Interrupt Service Routine for the high group of the interrupt sources. + * + * + ***************************************************************************/ + CY_ISR(USBFS_INTR_HI_ISR) + { + USBFS_IntrHandler(USBFS_INTR_CAUSE_HI_REG); + } + + /*************************************************************************** + * Function Name: USBFS_INTR_MED_ISR + ************************************************************************//** + * + * Interrupt Service Routine for the medium group of the interrupt sources. + * + * + ***************************************************************************/ + CY_ISR(USBFS_INTR_MED_ISR) + { + USBFS_IntrHandler(USBFS_INTR_CAUSE_MED_REG); + } + + /*************************************************************************** + * Function Name: USBFS_INTR_LO_ISR + ************************************************************************//** + * + * Interrupt Service Routine for the low group of the interrupt sources. + * + * + ***************************************************************************/ + CY_ISR(USBFS_INTR_LO_ISR) + { + USBFS_IntrHandler(USBFS_INTR_CAUSE_LO_REG); + } +#endif /* (CY_PSOC4) */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_hid.c b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_hid.c new file mode 100644 index 0000000000..994ec384eb --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_hid.c @@ -0,0 +1,460 @@ +/***************************************************************************//** +* \file USBFS_hid.c +* \version 3.20 +* +* \brief +* This file contains the USB HID Class request handler. +* +* Related Document: +* Device Class Definition for Human Interface Devices (HID) Version 1.11 +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "USBFS_hid.h" +#include "USBFS_pvt.h" + + + +#if defined(USBFS_ENABLE_HID_CLASS) + +/*************************************** +* HID Variables +***************************************/ +/** This variable is initialized in the USBFS_InitComponent() API to the + * PROTOCOL_REPORT value. It is controlled by the host using the + * HID_SET_PROTOCOL request. The value is returned to the user code by the + * USBFS_GetProtocol() API.*/ +volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER]; + +/** This variable controls the HID report rate. It is controlled by the host + * using the HID_SET_IDLE request and used by the USBFS_UpdateHIDTimer() API to + * reload timer.*/ +volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER]; + +/** This variable contains the timer counter, which is decremented and reloaded + * by the USBFS_UpdateHIDTimer() API.*/ +volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER]; /* HID device idle rate value */ + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START HID_CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_UpdateHIDTimer +****************************************************************************//** +* +* This function updates the HID Report idle timer and returns the status and +* reloads the timer if it expires. +* +* \param interface Contains the interface number. +* +* \return +* Returns the state of the HID timer. Symbolic names and their associated values are given here: +* Return Value |Notes +* ---------------------------|------------------------------------------------ +* USBFS_IDLE_TIMER_EXPIRED | The timer expired. +* USBFS_IDLE_TIMER_RUNNING | The timer is running. +* USBFS_IDLE_TIMER_IDEFINITE | The report is sent when data or state changes. +* +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_UpdateHIDTimer(uint8 interface) +{ + uint8 stat = USBFS_IDLE_TIMER_INDEFINITE; + + if(USBFS_hidIdleRate[interface] != 0u) + { + if(USBFS_hidIdleTimer[interface] > 0u) + { + USBFS_hidIdleTimer[interface]--; + stat = USBFS_IDLE_TIMER_RUNNING; + } + else + { + USBFS_hidIdleTimer[interface] = USBFS_hidIdleRate[interface]; + stat = USBFS_IDLE_TIMER_EXPIRED; + } + } + + return((uint8)stat); +} + + +/******************************************************************************* +* Function Name: USBFS_GetProtocol +****************************************************************************//** +* +* This function returns the HID protocol value for the selected interface. +* +* \param interface: Contains the interface number. +* +* \return +* Returns the protocol value. +* +*******************************************************************************/ +uint8 USBFS_GetProtocol(uint8 interface) +{ + return(USBFS_hidProtocol[interface]); +} + + +/******************************************************************************* +* Function Name: USBFS_DispatchHIDClassRqst +****************************************************************************//** +* +* This routine dispatches class requests +* +* \return +* Results of HID Class request handling: +* - USBFS_TRUE - request was handled without errors +* - USBFS_FALSE - error occurs during handling of request +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchHIDClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + + uint8 interfaceNumber = (uint8) USBFS_wIndexLoReg; + + /* Check request direction: D2H or H2D. */ + if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H)) + { + /* Handle direction from device to host. */ + + switch (USBFS_bRequestReg) + { + case USBFS_GET_DESCRIPTOR: + if (USBFS_wValueHiReg == USBFS_DESCR_HID_CLASS) + { + USBFS_FindHidClassDecriptor(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlRead(); + } + } + else if (USBFS_wValueHiReg == USBFS_DESCR_HID_REPORT) + { + USBFS_FindReportDescriptor(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlRead(); + } + } + else + { + /* Do not handle this request. */ + } + break; + + case USBFS_HID_GET_REPORT: + USBFS_FindReport(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlRead(); + } + break; + + case USBFS_HID_GET_IDLE: + /* This function does not support multiple reports per interface*/ + /* Validate interfaceNumber and Report ID (should be 0): Do not support Idle per Report ID */ + if ((interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && (USBFS_wValueLoReg == 0u)) + { + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = &USBFS_hidIdleRate[interfaceNumber]; + requestHandled = USBFS_InitControlRead(); + } + break; + + case USBFS_HID_GET_PROTOCOL: + /* Validate interfaceNumber */ + if( interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) + { + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = &USBFS_hidProtocol[interfaceNumber]; + requestHandled = USBFS_InitControlRead(); + } + break; + + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else + { + /* Handle direction from host to device. */ + + switch (USBFS_bRequestReg) + { + case USBFS_HID_SET_REPORT: + USBFS_FindReport(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlWrite(); + } + break; + + case USBFS_HID_SET_IDLE: + /* This function does not support multiple reports per interface */ + /* Validate interfaceNumber and Report ID (should be 0): Do not support Idle per Report ID */ + if ((interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && (USBFS_wValueLoReg == 0u)) + { + USBFS_hidIdleRate[interfaceNumber] = (uint8)USBFS_wValueHiReg; + /* With regards to HID spec: "7.2.4 Set_Idle Request" + * Latency. If the current period has gone past the + * newly proscribed time duration, then a report + * will be generated immediately. + */ + if(USBFS_hidIdleRate[interfaceNumber] < + USBFS_hidIdleTimer[interfaceNumber]) + { + /* Set the timer to zero and let the UpdateHIDTimer() API return IDLE_TIMER_EXPIRED status*/ + USBFS_hidIdleTimer[interfaceNumber] = 0u; + } + /* If the new request is received within 4 milliseconds + * (1 count) of the end of the current period, then the + * new request will have no effect until after the report. + */ + else if(USBFS_hidIdleTimer[interfaceNumber] <= 1u) + { + /* Do nothing. + * Let the UpdateHIDTimer() API continue to work and + * return IDLE_TIMER_EXPIRED status + */ + } + else + { /* Reload the timer*/ + USBFS_hidIdleTimer[interfaceNumber] = + USBFS_hidIdleRate[interfaceNumber]; + } + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + + case USBFS_HID_SET_PROTOCOL: + /* Validate interfaceNumber and protocol (must be 0 or 1) */ + if ((interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && (USBFS_wValueLoReg <= 1u)) + { + USBFS_hidProtocol[interfaceNumber] = (uint8)USBFS_wValueLoReg; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + + default: + /* Unknown class request is not handled. */ + break; + } + } + + return (requestHandled); +} + + +/******************************************************************************* +* Function Name: USB_FindHidClassDescriptor +****************************************************************************//** +* +* This routine find Hid Class Descriptor pointer based on the Interface number +* and Alternate setting then loads the currentTD structure with the address of +* the buffer and the size. +* The HID Class Descriptor resides inside the config descriptor. +* +* \return +* currentTD +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_FindHidClassDecriptor(void) +{ + const T_USBFS_LUT CYCODE *pTmp; + volatile uint8 *pDescr; + uint8 interfaceN; + + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + + interfaceN = (uint8) USBFS_wIndexLoReg; + /* Third entry in the LUT starts the Interface Table pointers */ + /* Now use the request interface number*/ + pTmp = &pTmp[interfaceN + 2u]; + + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + + /* Now use Alternate setting number */ + pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; + + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + + /* Fifth entry in the LUT points to Hid Class Descriptor in Configuration Descriptor */ + pTmp = &pTmp[4u]; + pDescr = (volatile uint8 *)pTmp->p_list; + + /* The first byte contains the descriptor length */ + USBFS_currentTD.count = *pDescr; + USBFS_currentTD.pData = pDescr; +} + + +/******************************************************************************* +* Function Name: USB_FindReportDescriptor +****************************************************************************//** +* +* This routine find Hid Report Descriptor pointer based on the Interface +* number, then loads the currentTD structure with the address of the buffer +* and the size. +* Hid Report Descriptor is located after IN/OUT/FEATURE reports. +* +* \return +* currentTD +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_FindReportDescriptor(void) +{ + const T_USBFS_LUT CYCODE *pTmp; + volatile uint8 *pDescr; + uint8 interfaceN; + + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + interfaceN = (uint8) USBFS_wIndexLoReg; + + /* Third entry in the LUT starts the Interface Table pointers */ + /* Now use the request interface number */ + pTmp = &pTmp[interfaceN + 2u]; + + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + + /* Now use Alternate setting number */ + pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; + + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + + /* Fourth entry in the LUT starts the Hid Report Descriptor */ + pTmp = &pTmp[3u]; + pDescr = (volatile uint8 *)pTmp->p_list; + + /* The 1st and 2nd bytes of descriptor contain its length. LSB is 1st. */ + USBFS_currentTD.count = ((uint16)((uint16) pDescr[1u] << 8u) | pDescr[0u]); + USBFS_currentTD.pData = &pDescr[2u]; +} + + +/******************************************************************************* +* Function Name: USBFS_FindReport +****************************************************************************//** +* +* This routine sets up a transfer based on the Interface number, Report Type +* and Report ID, then loads the currentTD structure with the address of the +* buffer and the size. The caller has to decide if it is a control read or +* control write. +* +* \return +* currentTD +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_FindReport(void) +{ + const T_USBFS_LUT CYCODE *pTmp; + T_USBFS_TD *pTD; + uint8 reportType; + uint8 interfaceN; + + /* `#START HID_FINDREPORT` Place custom handling here */ + + /* `#END` */ + +#ifdef USBFS_FIND_REPORT_CALLBACK + USBFS_FindReport_Callback(); +#endif /* (USBFS_FIND_REPORT_CALLBACK) */ + + USBFS_currentTD.count = 0u; /* Init not supported condition */ + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + reportType = (uint8) USBFS_wValueHiReg; + interfaceN = (uint8) USBFS_wIndexLoReg; + + /* Third entry in the LUT Configuration Table starts the Interface Table pointers */ + /* Now use the request interface number */ + pTmp = &pTmp[interfaceN + 2u]; + + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + if (interfaceN < USBFS_MAX_INTERFACES_NUMBER) + { + /* Now use Alternate setting number */ + pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; + + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + + /* Validate reportType to comply with "7.2.1 Get_Report Request" */ + if ((reportType >= USBFS_HID_GET_REPORT_INPUT) && + (reportType <= USBFS_HID_GET_REPORT_FEATURE)) + { + /* Get the entry proper TD (IN, OUT or Feature Report Table)*/ + pTmp = &pTmp[reportType - 1u]; + + /* Get reportID */ + reportType = (uint8) USBFS_wValueLoReg; + + /* Validate table support by the HID descriptor, compare table count with reportID */ + if (pTmp->c >= reportType) + { + pTD = (T_USBFS_TD *) pTmp->p_list; + pTD = &pTD[reportType]; /* select entry depend on report ID*/ + USBFS_currentTD.pData = pTD->pData; /* Buffer pointer */ + USBFS_currentTD.count = pTD->count; /* Buffer Size */ + USBFS_currentTD.pStatusBlock = pTD->pStatusBlock; + } + } + } +} + + +/******************************************************************************* +* Additional user functions supporting HID Requests +********************************************************************************/ + +/* `#START HID_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* USBFS_ENABLE_HID_CLASS */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_hid.h b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_hid.h new file mode 100644 index 0000000000..131695f458 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_hid.h @@ -0,0 +1,80 @@ +/***************************************************************************//** +* \file USBFS_hid.h +* \version 3.20 +* +* \brief +* This file provides function prototypes and constants for the USBFS component +* HID class. +* +* Related Document: +* Device Class Definition for Human Interface Devices (HID) Version 1.11 +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_USBFS_USBFS_hid_H) +#define CY_USBFS_USBFS_hid_H + +#include "USBFS.h" + +/*************************************** +* Prototypes of the USBFS_hid API. +***************************************/ +/** +* \addtogroup group_hid +* @{ +*/ +uint8 USBFS_UpdateHIDTimer(uint8 interface) ; +uint8 USBFS_GetProtocol(uint8 interface) ; +/** @} hid */ + +/*************************************** +*Renamed Functions for backward compatible +***************************************/ + +#define USBFS_bGetProtocol USBFS_GetProtocol + + +/*************************************** +* Constants for USBFS_hid API. +***************************************/ + +#define USBFS_PROTOCOL_BOOT (0x00u) +#define USBFS_PROTOCOL_REPORT (0x01u) + +/* Request Types (HID Chapter 7.2) */ +#define USBFS_HID_GET_REPORT (0x01u) +#define USBFS_HID_GET_IDLE (0x02u) +#define USBFS_HID_GET_PROTOCOL (0x03u) +#define USBFS_HID_SET_REPORT (0x09u) +#define USBFS_HID_SET_IDLE (0x0Au) +#define USBFS_HID_SET_PROTOCOL (0x0Bu) + +/* Descriptor Types (HID Chapter 7.1) */ +#define USBFS_DESCR_HID_CLASS (0x21u) +#define USBFS_DESCR_HID_REPORT (0x22u) +#define USBFS_DESCR_HID_PHYSICAL (0x23u) + +/* Report Request Types (HID Chapter 7.2.1) */ +#define USBFS_HID_GET_REPORT_INPUT (0x01u) +#define USBFS_HID_GET_REPORT_OUTPUT (0x02u) +#define USBFS_HID_GET_REPORT_FEATURE (0x03u) + +#endif /* CY_USBFS_USBFS_hid_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_msc.c b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_msc.c new file mode 100644 index 0000000000..49eb61eb3a --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_msc.c @@ -0,0 +1,159 @@ +/***************************************************************************//** +* \file USBFS_cdc.c +* \version 3.20 +* +* \brief +* This file contains the USB MSC Class request handler and global API for MSC +* class. +* +* Related Document: +* Universal Serial Bus Class Definitions for Communication Devices Version 1.1 +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "USBFS_msc.h" +#include "USBFS_pvt.h" + + +#if (USBFS_HANDLE_MSC_REQUESTS) + +/*************************************** +* Internal variables +***************************************/ + +static uint8 USBFS_lunCount = USBFS_MSC_LUN_NUMBER; + + +/******************************************************************************* +* Function Name: USBFS_DispatchMSCClassRqst +****************************************************************************//** +* +* \internal +* This routine dispatches MSC class requests. +* +* \return +* Status of request processing: handled or not handled. +* +* \globalvars +* USBFS_lunCount - stores number of LUN (logical units). +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchMSCClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + + /* Get request data. */ + uint16 value = USBFS_GET_UINT16(USBFS_wValueHiReg, USBFS_wValueLoReg); + uint16 dataLength = USBFS_GET_UINT16(USBFS_wLengthHiReg, USBFS_wLengthLoReg); + + /* Check request direction: D2H or H2D. */ + if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H)) + { + /* Handle direction from device to host. */ + + if (USBFS_MSC_GET_MAX_LUN == USBFS_bRequestReg) + { + /* Check request fields. */ + if ((value == USBFS_MSC_GET_MAX_LUN_WVALUE) && + (dataLength == USBFS_MSC_GET_MAX_LUN_WLENGTH)) + { + /* Reply to Get Max LUN request: setup control read. */ + USBFS_currentTD.pData = &USBFS_lunCount; + USBFS_currentTD.count = USBFS_MSC_GET_MAX_LUN_WLENGTH; + + requestHandled = USBFS_InitControlRead(); + } + } + } + else + { + /* Handle direction from host to device. */ + + if (USBFS_MSC_RESET == USBFS_bRequestReg) + { + /* Check request fields. */ + if ((value == USBFS_MSC_RESET_WVALUE) && + (dataLength == USBFS_MSC_RESET_WLENGTH)) + { + /* Handle to Bulk-Only Reset request: no data control transfer. */ + USBFS_currentTD.count = USBFS_MSC_RESET_WLENGTH; + + #ifdef USBFS_DISPATCH_MSC_CLASS_MSC_RESET_RQST_CALLBACK + USBFS_DispatchMSCClass_MSC_RESET_RQST_Callback(); + #endif /* (USBFS_DISPATCH_MSC_CLASS_MSC_RESET_RQST_CALLBACK) */ + + requestHandled = USBFS_InitNoDataControlTransfer(); + } + } + } + + return (requestHandled); +} + + +/******************************************************************************* +* Function Name: USBFS_MSC_SetLunCount +****************************************************************************//** +* +* This function sets the number of logical units supported in the application. +* The default number of logical units is set in the component customizer. +* +* \param lunCount: Count of the logical units. Valid range is between 1 and 16. +* +* +* \globalvars +* USBFS_lunCount - stores number of LUN (logical units). +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_MSC_SetLunCount(uint8 lunCount) +{ + USBFS_lunCount = (lunCount - 1u); +} + + +/******************************************************************************* +* Function Name: USBFS_MSC_GetLunCount +****************************************************************************//** +* +* This function returns the number of logical units. +* +* \return +* Number of the logical units. +* +* \globalvars +* USBFS_lunCount - stores number of LUN (logical units). +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_MSC_GetLunCount(void) +{ + return (USBFS_lunCount + 1u); +} + +#endif /* (USBFS_HANDLE_MSC_REQUESTS) */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_msc.h b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_msc.h new file mode 100644 index 0000000000..80b3ce887c --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_msc.h @@ -0,0 +1,73 @@ +/***************************************************************************//** +* \file USBFS_msc.h +* \version 3.20 +* +* \brief +* This file provides function prototypes and constants for the USBFS component +* MSC class support. +* +* Related Document: +* Device Class Definition for Mass Storage (MSC) Version TDB +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_USBFS_USBFS_msc_H) +#define CY_USBFS_USBFS_msc_H + +#include "USBFS.h" + +/*************************************** +* Initial Parameter Constants +***************************************/ + +#define USBFS_HANDLE_MSC_REQUESTS (0u != (1u)) +#define USBFS_MSC_LUN_NUMBER (1u - 1u) + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_msc +* @{ +*/ +#if (USBFS_HANDLE_MSC_REQUESTS) + void USBFS_MSC_SetLunCount(uint8 lunCount) ; + uint8 USBFS_MSC_GetLunCount(void) ; +#endif /* (USBFS_HANDLE_MSC_REQUESTS) */ +/** @} msc */ + +/*************************************** +* Constants +***************************************/ + +/* MSC Class-Specific requests */ +#define USBFS_MSC_RESET (0xFFu) +#define USBFS_MSC_GET_MAX_LUN (0xFEu) + +/* MSC Class-Specific requests constant fields. */ +#define USBFS_MSC_RESET_WVALUE (0u) +#define USBFS_MSC_RESET_WLENGTH (0u) + +#define USBFS_MSC_GET_MAX_LUN_WVALUE (0u) +#define USBFS_MSC_GET_MAX_LUN_WLENGTH (1u) + +#endif /* CY_USBFS_USBFS_msc_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_pm.c b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_pm.c new file mode 100644 index 0000000000..92855989fc --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_pm.c @@ -0,0 +1,341 @@ +/***************************************************************************//** +* \file USBFS_pm.c +* \version 3.20 +* +* \brief +* This file provides Suspend/Resume APIs implementation. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "USBFS_pvt.h" +#include "USBFS_Dp.h" + + +/*************************************** +* Custom Declarations +***************************************/ +/* `#START PM_CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/*************************************** +* Local data allocation +***************************************/ + +static USBFS_BACKUP_STRUCT USBFS_backup; + +#if (USBFS_DP_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_DP_ISR + ****************************************************************************//** + * + * This Interrupt Service Routine handles DP pin changes for wake-up from + * the sleep mode. + * + *******************************************************************************/ + CY_ISR(USBFS_DP_ISR) + { + #ifdef USBFS_DP_ISR_ENTRY_CALLBACK + USBFS_DP_ISR_EntryCallback(); + #endif /* (USBFS_DP_ISR_ENTRY_CALLBACK) */ + + /* `#START DP_USER_CODE` Place your code here */ + + /* `#END` */ + + (void) USBFS_Dp_ClearInterrupt(); + + #ifdef USBFS_DP_ISR_EXIT_CALLBACK + USBFS_DP_ISR_ExitCallback(); + #endif /* (USBFS_DP_ISR_EXIT_CALLBACK) */ + } +#endif /* (USBFS_DP_ISR_ACTIVE) */ + + +/******************************************************************************* +* Function Name: USBFS_SaveConfig +****************************************************************************//** +* +* Saves the current user configuration. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_SaveConfig(void) +{ + /* Empty function added for the compatibility purpose. */ +} + + +/******************************************************************************* +* Function Name: USBFS_RestoreConfig +****************************************************************************//** +* +* Restores the current user configuration. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_RestoreConfig(void) +{ + if (USBFS_configuration != 0u) + { + USBFS_ConfigReg(); + USBFS_EpStateInit(); + } +} + + +/******************************************************************************* +* Function Name: USBFS_Suspend +****************************************************************************//** +* +* This function prepares the USBFS component to enter low power mode. The +* interrupt on falling edge on Dp pin is configured to wakeup device when the +* host drives resume condition. The pull-up is enabled on the Dp line while +* device is in low power mode. The supported low power modes are Deep Sleep +* (PSoC 4200L) and Sleep (PSoC 3/ PSoC 5LP). +* +* *Note* For PSoC 4200L devices, this function should not be called before +* entering Sleep. +* +* *Note* After enter low power mode, the data which is left in the IN or OUT +* endpoint buffers is not restored after wakeup and lost. Therefore it should +* be stored in the SRAM for OUT endpoint or read by the host for IN endpoint +* before enter low power mode. +* +* \globalvars +* USBFS_backup.enable: modified. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_Suspend(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + if (0u != (USBFS_CR0_REG & USBFS_CR0_ENABLE)) + { + /* USB block is enabled. */ + USBFS_backup.enableState = 1u; + + #if (USBFS_EP_MANAGEMENT_DMA) + USBFS_Stop_DMA(USBFS_MAX_EP); + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + #if (CY_PSOC4) + /* Suspend enter sequence. */ + USBFS_POWER_CTRL_REG |= (USBFS_POWER_CTRL_SUSPEND | + USBFS_POWER_CTRL_SUSPEND_DEL); + + /* Store state of USB regulator and disable it. */ + USBFS_backup.mode = (uint8) (USBFS_CR1_REG & USBFS_CR1_REG_ENABLE); + USBFS_CR1_REG &= (uint32) ~USBFS_CR1_REG_ENABLE; + + /* Store SIE interrupt sources. Valid bits are 0 - 4. */ + USBFS_backup.intrSeiMask = (uint8) USBFS_INTR_SIE_MASK_REG; + + #else + /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled. */ + USBFS_USBIO_CR0_REG &= (uint8) ~USBFS_USBIO_CR0_TEN; + CyDelayUs(USBFS_WAIT_REG_STABILITY_50NS); /*~50ns delay. */ + + /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) and pd_pullup_hv(Inverted) high. */ + USBFS_PM_USB_CR0_REG &= (uint8) ~(USBFS_PM_USB_CR0_PD_N | + USBFS_PM_USB_CR0_PD_PULLUP_N); + + /* Disable the SIE. */ + USBFS_CR0_REG &= (uint8) ~USBFS_CR0_ENABLE; + + CyDelayUs(USBFS_WAIT_REG_STABILITY_50NS); /* ~50ns delay. */ + /* Store mode and disable VRegulator. */ + USBFS_backup.mode = (uint8) (USBFS_CR1_REG & USBFS_CR1_REG_ENABLE); + USBFS_CR1_REG &= (uint8) ~USBFS_CR1_REG_ENABLE; + + CyDelayUs(USBFS_WAIT_REG_STABILITY_1US); /* min 0.5us delay required. */ + + /* Disable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ + USBFS_PM_USB_CR0_REG &= (uint8) ~USBFS_PM_USB_CR0_REF_EN; + + /* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pull-up. */ + USBFS_USBIO_CR1_REG |= USBFS_USBIO_CR1_IOMODE; + + /* Disable USBFS block. */ + /* Clear power active and standby mode templates: disable USB block. */ + USBFS_PM_ACT_CFG_REG &= (uint8) ~USBFS_PM_ACT_EN_FSUSB; + USBFS_PM_STBY_CFG_REG &= (uint8) ~USBFS_PM_STBY_EN_FSUSB; + + CyDelayUs(USBFS_WAIT_REG_STABILITY_1US); /* min 0.5us delay required. */ + #endif /* (CY_PSOC4) */ + } + else + { + USBFS_backup.enableState = 0u; + } + + CyExitCriticalSection(enableInterrupts); + +#if (USBFS_DP_ISR_ACTIVE) + /* Clear active mode Dp interrupt source history. */ + (void) USBFS_Dp_ClearInterrupt(); + CyIntClearPending(USBFS_DP_INTC_VECT_NUM); + + CyIntEnable (USBFS_DP_INTC_VECT_NUM); +#endif /* (USBFS_DP_ISR_ACTIVE). */ +} + + +/******************************************************************************* +* Function Name: USBFS_Resume +****************************************************************************//** +* +* This function prepares the USBFS component for active mode operation after +* exit low power mode. It restores the component active mode configuration such +* as device address assigned previously by the host, endpoints buffer and disables +* interrupt on Dp pin. +* The supported low power modes are Deep Sleep (PSoC 4200L) and Sleep +* (PSoC 3/ PSoC 5LP). +* +* *Note* For PSoC 4200L devices, this function should not be called after +* exiting Sleep. +* +* *Note* To resume communication with the host, the data endpoints must be +* managed: the OUT endpoints must be enabled and IN endpoints must be loaded +* with data. For DMA with Automatic Buffer Management, all endpoints buffers +* must be initialized again before making them available to the host. +* +* +* \globalvars +* USBFS_backup - checked. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_Resume(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + if (0u != USBFS_backup.enableState) + { + #if (USBFS_DP_ISR_ACTIVE) + CyIntDisable(USBFS_DP_INTC_VECT_NUM); + #endif /* (USBFS_DP_ISR_ACTIVE) */ + + #if (CY_PSOC4) + /* Enable clock to USB IP. */ + USBFS_USB_CLK_EN_REG |= USBFS_USB_CLK_CSR_CLK_EN; + + /* Restore arbiter configuration for DMA transfers. */ + #if (USBFS_EP_MANAGEMENT_DMA) + #if (USBFS_ARB_ISR_ACTIVE) + /* Enable ARB EP interrupt sources. */ + USBFS_ARB_INT_EN_REG = USBFS_DEFAULT_ARB_INT_EN; + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + /* Configure arbiter for Manual or Auto DMA operation and clear + * configuration completion. + */ + USBFS_ARB_CFG_REG = USBFS_DEFAULT_ARB_CFG; + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + /* Restore level (hi, lo, med) for each interrupt source. */ + USBFS_INTR_LVL_SEL_REG = USBFS_DEFAULT_INTR_LVL_SEL; + + /* Store SIE interrupt sources. */ + USBFS_INTR_SIE_MASK_REG = (uint32) USBFS_backup.intrSeiMask; + + /* Set EP0.CR: ACK Setup, NAK IN/OUT. */ + USBFS_EP0_CR_REG = USBFS_MODE_NAK_IN_OUT; + + /* Restore data EP1-8 configuration. */ + USBFS_RestoreConfig(); + + /* Restore state of USB regulator and wait until it supples stable power. */ + USBFS_CR1_REG |= USBFS_backup.mode; + CyDelayUs(USBFS_WAIT_VREF_STABILITY); + + /* Suspend exit sequence. */ + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND; + CyDelayUs(USBFS_WAIT_SUSPEND_DEL_DISABLE); + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND_DEL; + + #else + /* Set power active and standby mode templates: enable USB block. */ + USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB; + USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB; + + /* Enable core clock. */ + USBFS_USB_CLK_EN_REG |= USBFS_USB_CLK_ENABLE; + + /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN; + + /* The reference is available ~40us after power restored. */ + CyDelayUs(USBFS_WAIT_VREF_RESTORE); + /* Restore state of USB regulator and wait until it supples stable power. */ + USBFS_CR1_REG |= USBFS_backup.mode; + CyDelayUs(USBFS_WAIT_VREF_STABILITY); /*~50ns delay. */ + + /* Enable USBIO. */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N; + CyDelayUs(USBFS_WAIT_PD_PULLUP_N_ENABLE); + /* Set the USBIO pull-up enable. */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N; + + /* Restore arbiter configuration for DMA transfers. */ + #if (USBFS_EP_MANAGEMENT_DMA) + #if (USBFS_ARB_ISR_ACTIVE) + /* Enable ARB EP interrupt sources. */ + USBFS_ARB_INT_EN_REG = USBFS_DEFAULT_ARB_INT_EN; + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + /* Configure arbiter for Manual or Auto DMA operation and clear + * configuration completion. + */ + USBFS_ARB_CFG_REG = USBFS_DEFAULT_ARB_CFG; + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + /* Set EP0.CR: ACK Setup, STALL IN/OUT. */ + USBFS_EP0_CR_REG = USBFS_MODE_STALL_IN_OUT; + + /* Enable the USB IP to respond to USB traffic with the last address. */ + USBFS_CR0_REG |= USBFS_CR0_ENABLE; + CyDelayCycles(USBFS_WAIT_CR0_REG_STABILITY); + + /* Enable D+ pull-up and keep USB control on IO. */ + USBFS_USBIO_CR1_REG = USBFS_USBIO_CR1_USBPUEN; + + /* Restore data EP1-8 configuration. */ + USBFS_RestoreConfig(); + #endif /* (CY_PSOC4) */ + } + + CyExitCriticalSection(enableInterrupts); +} + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_pvt.h b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_pvt.h new file mode 100644 index 0000000000..7464f2a143 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_pvt.h @@ -0,0 +1,426 @@ +/***************************************************************************//** +* \file .h +* \version 3.20 +* +* \brief +* This file provides private function prototypes and constants for the +* USBFS component. It is not intended to be used in the user project. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_USBFS_USBFS_pvt_H) +#define CY_USBFS_USBFS_pvt_H + +#include "USBFS.h" + +#ifdef USBFS_ENABLE_AUDIO_CLASS + #include "USBFS_audio.h" +#endif /* USBFS_ENABLE_AUDIO_CLASS */ + +#ifdef USBFS_ENABLE_CDC_CLASS + #include "USBFS_cdc.h" +#endif /* USBFS_ENABLE_CDC_CLASS */ + +#if (USBFS_ENABLE_MIDI_CLASS) + #include "USBFS_midi.h" +#endif /* (USBFS_ENABLE_MIDI_CLASS) */ + +#if (USBFS_ENABLE_MSC_CLASS) + #include "USBFS_msc.h" +#endif /* (USBFS_ENABLE_MSC_CLASS) */ + +#if (USBFS_EP_MANAGEMENT_DMA) + #if (CY_PSOC4) + #include + #else + #include + #if ((USBFS_EP_MANAGEMENT_DMA_AUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) + #include "USBFS_EP_DMA_Done_isr.h" + #include "USBFS_EP8_DMA_Done_SR.h" + #include "USBFS_EP17_DMA_Done_SR.h" + #endif /* ((USBFS_EP_MANAGEMENT_DMA_AUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + #endif /* (CY_PSOC4) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + +#if (USBFS_DMA1_ACTIVE) + #include "USBFS_ep1_dma.h" + #define USBFS_EP1_DMA_CH (USBFS_ep1_dma_CHANNEL) +#endif /* (USBFS_DMA1_ACTIVE) */ + +#if (USBFS_DMA2_ACTIVE) + #include "USBFS_ep2_dma.h" + #define USBFS_EP2_DMA_CH (USBFS_ep2_dma_CHANNEL) +#endif /* (USBFS_DMA2_ACTIVE) */ + +#if (USBFS_DMA3_ACTIVE) + #include "USBFS_ep3_dma.h" + #define USBFS_EP3_DMA_CH (USBFS_ep3_dma_CHANNEL) +#endif /* (USBFS_DMA3_ACTIVE) */ + +#if (USBFS_DMA4_ACTIVE) + #include "USBFS_ep4_dma.h" + #define USBFS_EP4_DMA_CH (USBFS_ep4_dma_CHANNEL) +#endif /* (USBFS_DMA4_ACTIVE) */ + +#if (USBFS_DMA5_ACTIVE) + #include "USBFS_ep5_dma.h" + #define USBFS_EP5_DMA_CH (USBFS_ep5_dma_CHANNEL) +#endif /* (USBFS_DMA5_ACTIVE) */ + +#if (USBFS_DMA6_ACTIVE) + #include "USBFS_ep6_dma.h" + #define USBFS_EP6_DMA_CH (USBFS_ep6_dma_CHANNEL) +#endif /* (USBFS_DMA6_ACTIVE) */ + +#if (USBFS_DMA7_ACTIVE) + #include "USBFS_ep7_dma.h" + #define USBFS_EP7_DMA_CH (USBFS_ep7_dma_CHANNEL) +#endif /* (USBFS_DMA7_ACTIVE) */ + +#if (USBFS_DMA8_ACTIVE) + #include "USBFS_ep8_dma.h" + #define USBFS_EP8_DMA_CH (USBFS_ep8_dma_CHANNEL) +#endif /* (USBFS_DMA8_ACTIVE) */ + + +/*************************************** +* Private Variables +***************************************/ + +/* Generated external references for descriptors. */ +extern const uint8 CYCODE USBFS_DEVICE0_DESCR[18u]; +#if defined(DAPLINK_IF) +extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[130u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_TABLE[1u]; +extern const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[7u]; +extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[4u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[7u]; +#else +extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[32u]; +extern const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[2u]; +extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[1u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[4u]; +#endif +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[3u]; +extern const T_USBFS_LUT CYCODE USBFS_TABLE[1u]; +extern const uint8 CYCODE USBFS_SN_STRING_DESCRIPTOR[26]; +extern const uint8 CYCODE USBFS_STRING_DESCRIPTORS[211u]; +#if defined(DAPLINK_IF) +extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_IN_RPT_SCB; +extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_IN_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_IN_BUF_SIZE]; +extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_OUT_RPT_SCB; +extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_OUT_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_OUT_BUF_SIZE]; +extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_FEATURE_RPT_SCB; +extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_FEATURE_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_FEATURE_BUF_SIZE]; +#endif +extern const uint8 CYCODE USBFS_HIDREPORT_DESCRIPTOR1[47u]; +extern const uint8 CYCODE USBFS_HIDREPORT_DESCRIPTOR2[37u]; +#if defined(DAPLINK_IF) +extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_IN_RPT_TABLE[1u]; +extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_OUT_RPT_TABLE[1u]; +extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_FEATURE_RPT_TABLE[1u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE4_ALTERNATE0_HID_TABLE[5u]; +#endif + +extern const uint8 CYCODE USBFS_MSOS_DESCRIPTOR[USBFS_MSOS_DESCRIPTOR_LENGTH]; +extern const uint8 CYCODE USBFS_MSOS_CONFIGURATION_DESCR[USBFS_MSOS_CONF_DESCR_LENGTH]; +#if defined(USBFS_ENABLE_IDSN_STRING) + extern uint8 USBFS_idSerialNumberStringDescriptor[USBFS_IDSN_DESCR_LENGTH]; +#endif /* (USBFS_ENABLE_IDSN_STRING) */ + +extern volatile uint8 USBFS_interfaceNumber; +extern volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER]; +extern volatile uint8 USBFS_interfaceSettingLast[USBFS_MAX_INTERFACES_NUMBER]; +extern volatile uint8 USBFS_deviceAddress; +extern volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER]; +extern const uint8 CYCODE *USBFS_interfaceClass; + +extern volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP]; +extern volatile T_USBFS_TD USBFS_currentTD; + +#if (USBFS_EP_MANAGEMENT_DMA) + #if (CY_PSOC4) + extern const uint8 USBFS_DmaChan[USBFS_MAX_EP]; + #else + extern uint8 USBFS_DmaChan[USBFS_MAX_EP]; + extern uint8 USBFS_DmaTd [USBFS_MAX_EP]; + #endif /* (CY_PSOC4) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) +#if (CY_PSOC4) + extern uint8 USBFS_DmaEpBurstCnt [USBFS_MAX_EP]; + extern uint8 USBFS_DmaEpLastBurstEl[USBFS_MAX_EP]; + + extern uint8 USBFS_DmaEpBurstCntBackup [USBFS_MAX_EP]; + extern uint32 USBFS_DmaEpBufferAddrBackup[USBFS_MAX_EP]; + + extern const uint8 USBFS_DmaReqOut [USBFS_MAX_EP]; + extern const uint8 USBFS_DmaBurstEndOut[USBFS_MAX_EP]; +#else + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + extern uint8 USBFS_DmaNextTd[USBFS_MAX_EP]; + extern volatile uint16 USBFS_inLength [USBFS_MAX_EP]; + extern volatile uint8 USBFS_inBufFull[USBFS_MAX_EP]; + extern const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP]; + extern const uint8 *USBFS_inDataPointer[USBFS_MAX_EP]; + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ +#endif /* CY_PSOC4 */ +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + +extern volatile uint8 USBFS_ep0Toggle; +extern volatile uint8 USBFS_lastPacketSize; +extern volatile uint8 USBFS_ep0Mode; +extern volatile uint8 USBFS_ep0Count; +extern volatile uint16 USBFS_transferByteCount; + + +/*************************************** +* Private Function Prototypes +***************************************/ +void USBFS_ReInitComponent(void) ; +void USBFS_HandleSetup(void) ; +void USBFS_HandleIN(void) ; +void USBFS_HandleOUT(void) ; +void USBFS_LoadEP0(void) ; +uint8 USBFS_InitControlRead(void) ; +uint8 USBFS_InitControlWrite(void) ; +void USBFS_ControlReadDataStage(void) ; +void USBFS_ControlReadStatusStage(void) ; +void USBFS_ControlReadPrematureStatus(void) ; +uint8 USBFS_InitControlWrite(void) ; +uint8 USBFS_InitZeroLengthControlTransfer(void) ; +void USBFS_ControlWriteDataStage(void) ; +void USBFS_ControlWriteStatusStage(void) ; +void USBFS_ControlWritePrematureStatus(void); +uint8 USBFS_InitNoDataControlTransfer(void) ; +void USBFS_NoDataControlStatusStage(void) ; +void USBFS_InitializeStatusBlock(void) ; +void USBFS_UpdateStatusBlock(uint8 completionCode) ; +uint8 USBFS_DispatchClassRqst(void) ; + +void USBFS_Config(uint8 clearAltSetting) ; +void USBFS_ConfigAltChanged(void) ; +void USBFS_ConfigReg(void) ; +void USBFS_EpStateInit(void) ; + + +const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex); +const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void) ; +#if (USBFS_BOS_ENABLE) + const T_USBFS_LUT CYCODE *USBFS_GetBOSPtr(void) ; +#endif /* (USBFS_BOS_ENABLE) */ +const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) ; +uint8 USBFS_ClearEndpointHalt(void) ; +uint8 USBFS_SetEndpointHalt(void) ; +uint8 USBFS_ValidateAlternateSetting(void) ; + +void USBFS_SaveConfig(void) ; +void USBFS_RestoreConfig(void) ; + +#if (CY_PSOC3 || CY_PSOC5LP) + #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) + void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) ; + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +#if defined(USBFS_ENABLE_IDSN_STRING) + void USBFS_ReadDieID(uint8 descr[]) ; +#endif /* USBFS_ENABLE_IDSN_STRING */ + +#if defined(USBFS_ENABLE_HID_CLASS) + uint8 USBFS_DispatchHIDClassRqst(void) ; +#endif /* (USBFS_ENABLE_HID_CLASS) */ + +#if defined(USBFS_ENABLE_AUDIO_CLASS) + uint8 USBFS_DispatchAUDIOClassRqst(void) ; +#endif /* (USBFS_ENABLE_AUDIO_CLASS) */ + +#if defined(USBFS_ENABLE_CDC_CLASS) + uint8 USBFS_DispatchCDCClassRqst(void) ; +#endif /* (USBFS_ENABLE_CDC_CLASS) */ + +#if (USBFS_ENABLE_MSC_CLASS) + #if (USBFS_HANDLE_MSC_REQUESTS) + uint8 USBFS_DispatchMSCClassRqst(void) ; + #endif /* (USBFS_HANDLE_MSC_REQUESTS) */ +#endif /* (USBFS_ENABLE_MSC_CLASS */ + +CY_ISR_PROTO(USBFS_EP_0_ISR); +CY_ISR_PROTO(USBFS_BUS_RESET_ISR); + +#if (USBFS_SOF_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_SOF_ISR); +#endif /* (USBFS_SOF_ISR_ACTIVE) */ + +#if (USBFS_EP1_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_1_ISR); +#endif /* (USBFS_EP1_ISR_ACTIVE) */ + +#if (USBFS_EP2_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_2_ISR); +#endif /* (USBFS_EP2_ISR_ACTIVE) */ + +#if (USBFS_EP3_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_3_ISR); +#endif /* (USBFS_EP3_ISR_ACTIVE) */ + +#if (USBFS_EP4_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_4_ISR); +#endif /* (USBFS_EP4_ISR_ACTIVE) */ + +#if (USBFS_EP5_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_5_ISR); +#endif /* (USBFS_EP5_ISR_ACTIVE) */ + +#if (USBFS_EP6_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_6_ISR); +#endif /* (USBFS_EP6_ISR_ACTIVE) */ + +#if (USBFS_EP7_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_7_ISR); +#endif /* (USBFS_EP7_ISR_ACTIVE) */ + +#if (USBFS_EP8_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_8_ISR); +#endif /* (USBFS_EP8_ISR_ACTIVE) */ + +#if (USBFS_EP_MANAGEMENT_DMA) + CY_ISR_PROTO(USBFS_ARB_ISR); +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + +#if (USBFS_DP_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_DP_ISR); +#endif /* (USBFS_DP_ISR_ACTIVE) */ + +#if (CY_PSOC4) + CY_ISR_PROTO(USBFS_INTR_HI_ISR); + CY_ISR_PROTO(USBFS_INTR_MED_ISR); + CY_ISR_PROTO(USBFS_INTR_LO_ISR); + #if (USBFS_LPM_ACTIVE) + CY_ISR_PROTO(USBFS_LPM_ISR); + #endif /* (USBFS_LPM_ACTIVE) */ +#endif /* (CY_PSOC4) */ + +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) +#if (CY_PSOC4) + #if (USBFS_DMA1_ACTIVE) + void USBFS_EP1_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA1_ACTIVE) */ + + #if (USBFS_DMA2_ACTIVE) + void USBFS_EP2_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA2_ACTIVE) */ + + #if (USBFS_DMA3_ACTIVE) + void USBFS_EP3_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA3_ACTIVE) */ + + #if (USBFS_DMA4_ACTIVE) + void USBFS_EP4_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA4_ACTIVE) */ + + #if (USBFS_DMA5_ACTIVE) + void USBFS_EP5_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA5_ACTIVE) */ + + #if (USBFS_DMA6_ACTIVE) + void USBFS_EP6_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA6_ACTIVE) */ + + #if (USBFS_DMA7_ACTIVE) + void USBFS_EP7_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA7_ACTIVE) */ + + #if (USBFS_DMA8_ACTIVE) + void USBFS_EP8_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA8_ACTIVE) */ + +#else + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + CY_ISR_PROTO(USBFS_EP_DMA_DONE_ISR); + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ +#endif /* (CY_PSOC4) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + +/*************************************** +* Request Handlers +***************************************/ + +uint8 USBFS_HandleStandardRqst(void) ; +uint8 USBFS_DispatchClassRqst(void) ; +uint8 USBFS_HandleVendorRqst(void) ; + + +/*************************************** +* HID Internal references +***************************************/ + +#if defined(USBFS_ENABLE_HID_CLASS) + void USBFS_FindReport(void) ; + void USBFS_FindReportDescriptor(void) ; + void USBFS_FindHidClassDecriptor(void) ; +#endif /* USBFS_ENABLE_HID_CLASS */ + + +/*************************************** +* MIDI Internal references +***************************************/ + +#if defined(USBFS_ENABLE_MIDI_STREAMING) + void USBFS_MIDI_IN_EP_Service(void) ; +#endif /* (USBFS_ENABLE_MIDI_STREAMING) */ + + +/*************************************** +* CDC Internal references +***************************************/ + +#if defined(USBFS_ENABLE_CDC_CLASS) + + typedef struct + { + uint8 bRequestType; + uint8 bNotification; + uint8 wValue; + uint8 wValueMSB; + uint8 wIndex; + uint8 wIndexMSB; + uint8 wLength; + uint8 wLengthMSB; + uint8 wSerialState; + uint8 wSerialStateMSB; + } t_USBFS_cdc_notification; + + uint8 USBFS_GetInterfaceComPort(uint8 interface) ; + uint8 USBFS_Cdc_EpInit( const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP, uint8 epNum, uint8 cdcComNums) ; + + extern volatile uint8 USBFS_cdc_dataInEpList[USBFS_MAX_MULTI_COM_NUM]; + extern volatile uint8 USBFS_cdc_dataOutEpList[USBFS_MAX_MULTI_COM_NUM]; + extern volatile uint8 USBFS_cdc_commInEpList[USBFS_MAX_MULTI_COM_NUM]; +#endif /* (USBFS_ENABLE_CDC_CLASS) */ + + +#endif /* CY_USBFS_USBFS_pvt_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_std.c b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_std.c new file mode 100644 index 0000000000..dc878931ef --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_std.c @@ -0,0 +1,1271 @@ +/***************************************************************************//** +* \file USBFS_std.c +* \version 3.20 +* +* \brief +* This file contains the USB Standard request handler. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "USBFS_pvt.h" + +/*************************************** +* Static data allocation +***************************************/ + +#if defined(USBFS_ENABLE_FWSN_STRING) + static volatile uint8* USBFS_fwSerialNumberStringDescriptor; + static volatile uint8 USBFS_snStringConfirm = USBFS_FALSE; +#endif /* (USBFS_ENABLE_FWSN_STRING) */ + +#if defined(USBFS_ENABLE_FWSN_STRING) + /*************************************************************************** + * Function Name: USBFS_SerialNumString + ************************************************************************//** + * + * This function is available only when the User Call Back option in the + * Serial Number String descriptor properties is selected. Application + * firmware can provide the source of the USB device serial number string + * descriptor during run time. The default string is used if the application + * firmware does not use this function or sets the wrong string descriptor. + * + * \param snString: Pointer to the user-defined string descriptor. The + * string descriptor should meet the Universal Serial Bus Specification + * revision 2.0 chapter 9.6.7 + * Offset|Size|Value|Description + * ------|----|------|--------------------------------- + * 0 |1 |N |Size of this descriptor in bytes + * 1 |1 |0x03 |STRING Descriptor Type + * 2 |N-2 |Number|UNICODE encoded string + * + * *For example:* uint8 snString[16]={0x0E,0x03,'F',0,'W',0,'S',0,'N',0,'0',0,'1',0}; + * + * \reentrant + * No. + * + ***************************************************************************/ + void USBFS_SerialNumString(uint8 snString[]) + { + USBFS_snStringConfirm = USBFS_FALSE; + + if (snString != NULL) + { + /* Check descriptor validation */ + if ((snString[0u] > 1u) && (snString[1u] == USBFS_DESCR_STRING)) + { + USBFS_fwSerialNumberStringDescriptor = snString; + USBFS_snStringConfirm = USBFS_TRUE; + } + } + } +#endif /* USBFS_ENABLE_FWSN_STRING */ + + +/******************************************************************************* +* Function Name: USBFS_HandleStandardRqst +****************************************************************************//** +* +* This Routine dispatches standard requests +* +* +* \return +* TRUE if request handled. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_HandleStandardRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + uint8 interfaceNumber; + uint8 configurationN; + uint8 bmRequestType = USBFS_bmRequestTypeReg; + +#if defined(USBFS_ENABLE_STRINGS) + volatile uint8 *pStr = 0u; + #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS) + uint8 nStr; + uint8 descrLength; + #endif /* (USBFS_ENABLE_DESCRIPTOR_STRINGS) */ +#endif /* (USBFS_ENABLE_STRINGS) */ + + static volatile uint8 USBFS_tBuffer[USBFS_STATUS_LENGTH_MAX]; + const T_USBFS_LUT CYCODE *pTmp; + + USBFS_currentTD.count = 0u; + + if (USBFS_RQST_DIR_D2H == (bmRequestType & USBFS_RQST_DIR_MASK)) + { + /* Control Read */ + switch (USBFS_bRequestReg) + { + case USBFS_GET_DESCRIPTOR: + if (USBFS_DESCR_DEVICE ==USBFS_wValueHiReg) + { + pTmp = USBFS_GetDeviceTablePtr(); + USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; + USBFS_currentTD.count = USBFS_DEVICE_DESCR_LENGTH; + + requestHandled = USBFS_InitControlRead(); + } + else if (USBFS_DESCR_CONFIG == USBFS_wValueHiReg) + { + pTmp = USBFS_GetConfigTablePtr((uint8) USBFS_wValueLoReg); + + /* Verify that requested descriptor exists */ + if (pTmp != NULL) + { + USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; + USBFS_currentTD.count = (uint16)((uint16)(USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \ + (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW]; + requestHandled = USBFS_InitControlRead(); + } + } + + #if(USBFS_BOS_ENABLE) + else if (USBFS_DESCR_BOS == USBFS_wValueHiReg) + { + pTmp = USBFS_GetBOSPtr(); + + /* Verify that requested descriptor exists */ + if (pTmp != NULL) + { + USBFS_currentTD.pData = (volatile uint8 *)pTmp; + USBFS_currentTD.count = ((uint16)((uint16)(USBFS_currentTD.pData)[USBFS_BOS_DESCR_TOTAL_LENGTH_HI] << 8u)) | \ + (USBFS_currentTD.pData)[USBFS_BOS_DESCR_TOTAL_LENGTH_LOW]; + requestHandled = USBFS_InitControlRead(); + } + } + #endif /*(USBFS_BOS_ENABLE)*/ + + #if defined(USBFS_ENABLE_STRINGS) + else if (USBFS_DESCR_STRING == USBFS_wValueHiReg) + { + /* Descriptor Strings */ + #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS) + nStr = 0u; + pStr = (volatile uint8 *) &USBFS_STRING_DESCRIPTORS[0u]; + + while ((USBFS_wValueLoReg > nStr) && (*pStr != 0u)) + { + /* Read descriptor length from 1st byte */ + descrLength = *pStr; + /* Move to next string descriptor */ + pStr = &pStr[descrLength]; + nStr++; + } + #endif /* (USBFS_ENABLE_DESCRIPTOR_STRINGS) */ + + /* Microsoft OS String */ + #if defined(USBFS_ENABLE_MSOS_STRING) + if (USBFS_STRING_MSOS == USBFS_wValueLoReg) + { + pStr = (volatile uint8 *)& USBFS_MSOS_DESCRIPTOR[0u]; + } + #endif /* (USBFS_ENABLE_MSOS_STRING) */ + + /* SN string */ + #if defined(USBFS_ENABLE_SN_STRING) + if ((USBFS_wValueLoReg != 0u) && + (USBFS_wValueLoReg == USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT])) + { + #if defined(USBFS_ENABLE_IDSN_STRING) + /* Read DIE ID and generate string descriptor in RAM */ + USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor); + pStr = USBFS_idSerialNumberStringDescriptor; + #elif defined(USBFS_ENABLE_FWSN_STRING) + + if(USBFS_snStringConfirm != USBFS_FALSE) + { + pStr = USBFS_fwSerialNumberStringDescriptor; + } + else + { + pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u]; + } + #else + pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u]; + #endif /* (USBFS_ENABLE_IDSN_STRING) */ + } + #endif /* (USBFS_ENABLE_SN_STRING) */ + + if (*pStr != 0u) + { + USBFS_currentTD.count = *pStr; + USBFS_currentTD.pData = pStr; + requestHandled = USBFS_InitControlRead(); + } + } + #endif /* USBFS_ENABLE_STRINGS */ + else + { + requestHandled = USBFS_DispatchClassRqst(); + } + break; + + case USBFS_GET_STATUS: + switch (bmRequestType & USBFS_RQST_RCPT_MASK) + { + case USBFS_RQST_RCPT_EP: + USBFS_currentTD.count = USBFS_EP_STATUS_LENGTH; + USBFS_tBuffer[0u] = USBFS_EP[USBFS_wIndexLoReg & USBFS_DIR_UNUSED].hwEpState; + USBFS_tBuffer[1u] = 0u; + USBFS_currentTD.pData = &USBFS_tBuffer[0u]; + + requestHandled = USBFS_InitControlRead(); + break; + case USBFS_RQST_RCPT_DEV: + USBFS_currentTD.count = USBFS_DEVICE_STATUS_LENGTH; + USBFS_tBuffer[0u] = USBFS_deviceStatus; + USBFS_tBuffer[1u] = 0u; + USBFS_currentTD.pData = &USBFS_tBuffer[0u]; + + requestHandled = USBFS_InitControlRead(); + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + break; + + case USBFS_GET_CONFIGURATION: + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = (volatile uint8 *) &USBFS_configuration; + requestHandled = USBFS_InitControlRead(); + break; + + case USBFS_GET_INTERFACE: + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = (volatile uint8 *) &USBFS_interfaceSetting[USBFS_wIndexLoReg]; + requestHandled = USBFS_InitControlRead(); + break; + + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else + { + /* Control Write */ + switch (USBFS_bRequestReg) + { + case USBFS_SET_ADDRESS: + /* Store address to be set in USBFS_NoDataControlStatusStage(). */ + USBFS_deviceAddress = (uint8) USBFS_wValueLoReg; + requestHandled = USBFS_InitNoDataControlTransfer(); + break; + + case USBFS_SET_CONFIGURATION: + configurationN = USBFS_wValueLoReg; + + /* Verify that configuration descriptor exists */ + if(configurationN > 0u) + { + pTmp = USBFS_GetConfigTablePtr((uint8) configurationN - 1u); + } + + /* Responds with a Request Error when configuration number is invalid */ + if (((configurationN > 0u) && (pTmp != NULL)) || (configurationN == 0u)) + { + /* Set new configuration if it has been changed */ + if(configurationN != USBFS_configuration) + { + USBFS_configuration = (uint8) configurationN; + USBFS_configurationChanged = USBFS_TRUE; + USBFS_Config(USBFS_TRUE); + } + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + + case USBFS_SET_INTERFACE: + if (0u != USBFS_ValidateAlternateSetting()) + { + /* Get interface number from the request. */ + interfaceNumber = USBFS_wIndexLoReg; + USBFS_interfaceNumber = (uint8) USBFS_wIndexLoReg; + + /* Check if alternate settings is changed for interface. */ + if (USBFS_interfaceSettingLast[interfaceNumber] != USBFS_interfaceSetting[interfaceNumber]) + { + USBFS_configurationChanged = USBFS_TRUE; + + /* Change alternate setting for the endpoints. */ + #if (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC) + USBFS_Config(USBFS_FALSE); + #else + USBFS_ConfigAltChanged(); + #endif /* (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC) */ + } + + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + + case USBFS_CLEAR_FEATURE: + switch (bmRequestType & USBFS_RQST_RCPT_MASK) + { + case USBFS_RQST_RCPT_EP: + if (USBFS_wValueLoReg == USBFS_ENDPOINT_HALT) + { + requestHandled = USBFS_ClearEndpointHalt(); + } + break; + case USBFS_RQST_RCPT_DEV: + /* Clear device REMOTE_WAKEUP */ + if (USBFS_wValueLoReg == USBFS_DEVICE_REMOTE_WAKEUP) + { + USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_REMOTE_WAKEUP; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + case USBFS_RQST_RCPT_IFC: + /* Validate interfaceNumber */ + if (USBFS_wIndexLoReg < USBFS_MAX_INTERFACES_NUMBER) + { + USBFS_interfaceStatus[USBFS_wIndexLoReg] &= (uint8) ~USBFS_wValueLoReg; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + break; + + case USBFS_SET_FEATURE: + switch (bmRequestType & USBFS_RQST_RCPT_MASK) + { + case USBFS_RQST_RCPT_EP: + if (USBFS_wValueLoReg == USBFS_ENDPOINT_HALT) + { + requestHandled = USBFS_SetEndpointHalt(); + } + break; + + case USBFS_RQST_RCPT_DEV: + /* Set device REMOTE_WAKEUP */ + if (USBFS_wValueLoReg == USBFS_DEVICE_REMOTE_WAKEUP) + { + USBFS_deviceStatus |= USBFS_DEVICE_STATUS_REMOTE_WAKEUP; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + + case USBFS_RQST_RCPT_IFC: + /* Validate interfaceNumber */ + if (USBFS_wIndexLoReg < USBFS_MAX_INTERFACES_NUMBER) + { + USBFS_interfaceStatus[USBFS_wIndexLoReg] &= (uint8) ~USBFS_wValueLoReg; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + + default: /* requestHandled is initialized as FALSE by default */ + break; + } + break; + + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + + return (requestHandled); +} + + +#if defined(USBFS_ENABLE_IDSN_STRING) + /*************************************************************************** + * Function Name: USBFS_ReadDieID + ************************************************************************//** + * + * This routine read Die ID and generate Serial Number string descriptor. + * + * \param descr: pointer on string descriptor. This string size has to be equal or + * greater than USBFS_IDSN_DESCR_LENGTH. + * + * + * \reentrant + * No. + * + ***************************************************************************/ + void USBFS_ReadDieID(uint8 descr[]) + { + const char8 CYCODE hex[] = "0123456789ABCDEF"; + uint8 i; + uint8 j = 0u; + uint8 uniqueId[8u]; + + if (NULL != descr) + { + /* Initialize descriptor header. */ + descr[0u] = USBFS_IDSN_DESCR_LENGTH; + descr[1u] = USBFS_DESCR_STRING; + + /* Unique ID size is 8 bytes. */ + CyGetUniqueId((uint32 *) uniqueId); + + /* Fill descriptor with unique device ID. */ + for (i = 2u; i < USBFS_IDSN_DESCR_LENGTH; i += 4u) + { + descr[i] = (uint8) hex[(uniqueId[j] >> 4u)]; + descr[i + 1u] = 0u; + descr[i + 2u] = (uint8) hex[(uniqueId[j] & 0x0Fu)]; + descr[i + 3u] = 0u; + ++j; + } + } + } +#endif /* (USBFS_ENABLE_IDSN_STRING) */ + + +/******************************************************************************* +* Function Name: USBFS_ConfigReg +****************************************************************************//** +* +* This routine configures hardware registers from the variables. +* It is called from USBFS_Config() function and from RestoreConfig +* after Wakeup. +* +*******************************************************************************/ +void USBFS_ConfigReg(void) +{ + uint8 ep; + +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) + uint8 epType = 0u; +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + /* Go thought all endpoints and set hardware configuration */ + for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ++ep) + { + USBFS_ARB_EP_BASE.arbEp[ep].epCfg = USBFS_ARB_EPX_CFG_DEFAULT; + + #if (USBFS_EP_MANAGEMENT_DMA) + /* Enable arbiter endpoint interrupt sources */ + USBFS_ARB_EP_BASE.arbEp[ep].epIntEn = USBFS_ARB_EPX_INT_MASK; + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + if (USBFS_EP[ep].epMode != USBFS_MODE_DISABLE) + { + if (0u != (USBFS_EP[ep].addr & USBFS_DIR_IN)) + { + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_IN; + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO && CY_PSOC4) + /* Clear DMA_TERMIN for IN endpoint. */ + USBFS_ARB_EP_BASE.arbEp[ep].epIntEn &= (uint32) ~USBFS_ARB_EPX_INT_DMA_TERMIN; + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && CY_PSOC4) */ + } + else + { + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_OUT; + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* (CY_PSOC4): DMA_TERMIN for OUT endpoint is set above. */ + + /* Prepare endpoint type mask. */ + epType |= (uint8) (0x01u << (ep - USBFS_EP1)); + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + } + } + else + { + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_STALL_DATA_EP; + } + + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + #if (CY_PSOC4) + USBFS_ARB_EP16_BASE.arbEp[ep].rwRa16 = (uint32) USBFS_EP[ep].buffOffset; + USBFS_ARB_EP16_BASE.arbEp[ep].rwWa16 = (uint32) USBFS_EP[ep].buffOffset; + #else + USBFS_ARB_EP_BASE.arbEp[ep].rwRa = LO8(USBFS_EP[ep].buffOffset); + USBFS_ARB_EP_BASE.arbEp[ep].rwRaMsb = HI8(USBFS_EP[ep].buffOffset); + USBFS_ARB_EP_BASE.arbEp[ep].rwWa = LO8(USBFS_EP[ep].buffOffset); + USBFS_ARB_EP_BASE.arbEp[ep].rwWaMsb = HI8(USBFS_EP[ep].buffOffset); + #endif /* (CY_PSOC4) */ + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ + } + +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* BUF_SIZE depend on DMA_THRESS value:0x55-32 bytes 0x44-16 bytes 0x33-8 bytes 0x22-4 bytes 0x11-2 bytes */ + USBFS_BUF_SIZE_REG = USBFS_DMA_BUF_SIZE; + + /* Configure DMA burst threshold */ +#if (CY_PSOC4) + USBFS_DMA_THRES16_REG = USBFS_DMA_BYTES_PER_BURST; +#else + USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST; + USBFS_DMA_THRES_MSB_REG = 0u; +#endif /* (CY_PSOC4) */ + USBFS_EP_ACTIVE_REG = USBFS_DEFAULT_ARB_INT_EN; + USBFS_EP_TYPE_REG = epType; + + /* Cfg_cmp bit set to 1 once configuration is complete. */ + /* Lock arbiter configtuation */ + USBFS_ARB_CFG_REG |= (uint8) USBFS_ARB_CFG_CFG_CMP; + /* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */ + USBFS_ARB_CFG_REG &= (uint8) ~USBFS_ARB_CFG_CFG_CMP; + +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + /* Enable interrupt SIE interurpt source from EP0-EP1 */ + USBFS_SIE_EP_INT_EN_REG = (uint8) USBFS_DEFAULT_SIE_EP_INT_EN; +} + + +/******************************************************************************* +* Function Name: USBFS_EpStateInit +****************************************************************************//** +* +* This routine initialize state of Data end points based of its type: +* IN - USBFS_IN_BUFFER_EMPTY (USBFS_EVENT_PENDING) +* OUT - USBFS_OUT_BUFFER_EMPTY (USBFS_NO_EVENT_PENDING) +* +*******************************************************************************/ +void USBFS_EpStateInit(void) +{ + uint8 i; + + for (i = USBFS_EP1; i < USBFS_MAX_EP; i++) + { + if (0u != (USBFS_EP[i].addr & USBFS_DIR_IN)) + { + /* IN Endpoint */ + USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING; + } + else + { + /* OUT Endpoint */ + USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING; + } + } + +} + + +/******************************************************************************* +* Function Name: USBFS_Config +****************************************************************************//** +* +* This routine configures endpoints for the entire configuration by scanning +* the configuration descriptor. +* +* \param clearAltSetting: It configures the bAlternateSetting 0 for each interface. +* +* USBFS_interfaceClass - Initialized class array for each interface. +* It is used for handling Class specific requests depend on interface class. +* Different classes in multiple Alternate settings does not supported. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_Config(uint8 clearAltSetting) +{ + uint8 ep; + uint8 curEp; + uint8 i; + uint8 epType; + const uint8 *pDescr; + + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + uint16 buffCount = 0u; + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + const T_USBFS_LUT CYCODE *pTmp; + const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP; + + /* Clear endpoints settings */ + for (ep = 0u; ep < USBFS_MAX_EP; ++ep) + { + USBFS_EP[ep].attrib = 0u; + USBFS_EP[ep].hwEpState = 0u; + USBFS_EP[ep].epToggle = 0u; + USBFS_EP[ep].bufferSize = 0u; + USBFS_EP[ep].interface = 0u; + USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; + USBFS_EP[ep].epMode = USBFS_MODE_DISABLE; + } + + /* Clear Alternate settings for all interfaces. */ + if (0u != clearAltSetting) + { + for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; ++i) + { + USBFS_interfaceSetting[i] = 0u; + USBFS_interfaceSettingLast[i] = 0u; + } + } + + /* Init Endpoints and Device Status if configured */ + if (USBFS_configuration > 0u) + { + #if defined(USBFS_ENABLE_CDC_CLASS) + uint8 cdcComNums = 0u; + #endif /* (USBFS_ENABLE_CDC_CLASS) */ + + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + + /* Set Power status for current configuration */ + pDescr = (const uint8 *)pTmp->p_list; + if ((pDescr[USBFS_CONFIG_DESCR_ATTRIB] & USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED) != 0u) + { + USBFS_deviceStatus |= (uint8) USBFS_DEVICE_STATUS_SELF_POWERED; + } + else + { + USBFS_deviceStatus &= (uint8) ~USBFS_DEVICE_STATUS_SELF_POWERED; + } + + /* Move to next element */ + pTmp = &pTmp[1u]; + ep = pTmp->c; /* For this table, c is the number of endpoints configurations */ + + #if (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC) + /* Configure for dynamic EP memory allocation */ + /* p_list points the endpoint setting table. */ + pEP = (T_USBFS_EP_SETTINGS_BLOCK *) pTmp->p_list; + + for (i = 0u; i < ep; i++) + { + /* Compare current Alternate setting with EP Alt */ + if (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) + { + curEp = pEP->addr & USBFS_DIR_UNUSED; + epType = pEP->attributes & USBFS_EP_TYPE_MASK; + + USBFS_EP[curEp].addr = pEP->addr; + USBFS_EP[curEp].attrib = pEP->attributes; + USBFS_EP[curEp].bufferSize = pEP->bufferSize; + + if (0u != (pEP->addr & USBFS_DIR_IN)) + { + /* IN Endpoint */ + USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType); + USBFS_EP[curEp].apiEpState = USBFS_EVENT_PENDING; + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_IN_BUFF_SIZE > 0)) + if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_in_ep = curEp; + } + #endif /* (USBFS_ENABLE_MIDI_STREAMING) */ + } + else + { + /* OUT Endpoint */ + USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType); + USBFS_EP[curEp].apiEpState = USBFS_NO_EVENT_PENDING; + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_OUT_BUFF_SIZE > 0)) + if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_out_ep = curEp; + } + #endif /* (USBFS_ENABLE_MIDI_STREAMING) */ + } + + #if(defined (USBFS_ENABLE_CDC_CLASS)) + if((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||(pEP->bMisc == USBFS_CLASS_CDC)) + { + cdcComNums = USBFS_Cdc_EpInit(pEP, curEp, cdcComNums); + } + #endif /* (USBFS_ENABLE_CDC_CLASS) */ + } + + pEP = &pEP[1u]; + } + + #else + for (i = USBFS_EP1; i < USBFS_MAX_EP; ++i) + { + /* p_list points the endpoint setting table. */ + pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; + /* Find max length for each EP and select it (length could be different in different Alt settings) */ + /* but other settings should be correct with regards to Interface alt Setting */ + + for (curEp = 0u; curEp < ep; ++curEp) + { + if (i == (pEP->addr & USBFS_DIR_UNUSED)) + { + /* Compare endpoint buffers size with current size to find greater. */ + if (USBFS_EP[i].bufferSize < pEP->bufferSize) + { + USBFS_EP[i].bufferSize = pEP->bufferSize; + } + + /* Compare current Alternate setting with EP Alt */ + if (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) + { + USBFS_EP[i].addr = pEP->addr; + USBFS_EP[i].attrib = pEP->attributes; + + epType = pEP->attributes & USBFS_EP_TYPE_MASK; + + if (0u != (pEP->addr & USBFS_DIR_IN)) + { + /* IN Endpoint */ + USBFS_EP[i].epMode = USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType); + USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING; + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_IN_BUFF_SIZE > 0)) + if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_in_ep = i; + } + #endif /* (USBFS_ENABLE_MIDI_STREAMING) */ + } + else + { + /* OUT Endpoint */ + USBFS_EP[i].epMode = USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType); + USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING; + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_OUT_BUFF_SIZE > 0)) + if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_out_ep = i; + } + #endif /* (USBFS_ENABLE_MIDI_STREAMING) */ + } + + #if (defined(USBFS_ENABLE_CDC_CLASS)) + if((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||(pEP->bMisc == USBFS_CLASS_CDC)) + { + cdcComNums = USBFS_Cdc_EpInit(pEP, i, cdcComNums); + } + #endif /* (USBFS_ENABLE_CDC_CLASS) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + break; /* Use first EP setting in Auto memory management */ + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + } + } + + pEP = &pEP[1u]; + } + } + #endif /* (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC) */ + + /* Init class array for each interface and interface number for each EP. + * It is used for handling Class specific requests directed to either an + * interface or the endpoint. + */ + /* p_list points the endpoint setting table. */ + pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; + for (i = 0u; i < ep; i++) + { + /* Configure interface number for each EP */ + USBFS_EP[pEP->addr & USBFS_DIR_UNUSED].interface = pEP->interface; + pEP = &pEP[1u]; + } + + /* Init pointer on interface class table */ + USBFS_interfaceClass = USBFS_GetInterfaceClassTablePtr(); + + /* Set the endpoint buffer addresses */ + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + buffCount = 0u; + for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ++ep) + { + USBFS_EP[ep].buffOffset = buffCount; + buffCount += USBFS_EP[ep].bufferSize; + + #if (USBFS_GEN_16BITS_EP_ACCESS) + /* Align EP buffers to be event size to access 16-bits DR register. */ + buffCount += (0u != (buffCount & 0x01u)) ? 1u : 0u; + #endif /* (USBFS_GEN_16BITS_EP_ACCESS) */ + } + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + /* Configure hardware registers */ + USBFS_ConfigReg(); + } +} + + +/******************************************************************************* +* Function Name: USBFS_ConfigAltChanged +****************************************************************************//** +* +* This routine update configuration for the required endpoints only. +* It is called after SET_INTERFACE request when Static memory allocation used. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_ConfigAltChanged(void) +{ + uint8 ep; + uint8 curEp; + uint8 epType; + uint8 i; + uint8 interfaceNum; + + const T_USBFS_LUT CYCODE *pTmp; + const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP; + + /* Init Endpoints and Device Status if configured */ + if (USBFS_configuration > 0u) + { + /* Get number of endpoints configurations (ep). */ + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + pTmp = &pTmp[1u]; + ep = pTmp->c; + + /* Get pointer to endpoints setting table (pEP). */ + pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; + + /* Look through all possible endpoint configurations. Find endpoints + * which belong to current interface and alternate settings for + * re-configuration. + */ + interfaceNum = USBFS_interfaceNumber; + for (i = 0u; i < ep; i++) + { + /* Find endpoints which belong to current interface and alternate settings. */ + if ((interfaceNum == pEP->interface) && + (USBFS_interfaceSetting[interfaceNum] == pEP->altSetting)) + { + curEp = ((uint8) pEP->addr & USBFS_DIR_UNUSED); + epType = ((uint8) pEP->attributes & USBFS_EP_TYPE_MASK); + + /* Change the SIE mode for the selected EP to NAK ALL */ + USBFS_EP[curEp].epToggle = 0u; + USBFS_EP[curEp].addr = pEP->addr; + USBFS_EP[curEp].attrib = pEP->attributes; + USBFS_EP[curEp].bufferSize = pEP->bufferSize; + + if (0u != (pEP->addr & USBFS_DIR_IN)) + { + /* IN Endpoint */ + USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType); + USBFS_EP[curEp].apiEpState = USBFS_EVENT_PENDING; + } + else + { + /* OUT Endpoint */ + USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType); + USBFS_EP[curEp].apiEpState = USBFS_NO_EVENT_PENDING; + } + + /* Make SIE to NAK any endpoint requests */ + USBFS_SIE_EP_BASE.sieEp[curEp].epCr0 = USBFS_MODE_NAK_IN_OUT; + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Clear IN data ready. */ + USBFS_ARB_EP_BASE.arbEp[curEp].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_IN_DATA_RDY; + + /* Select endpoint number of reconfiguration */ + USBFS_DYN_RECONFIG_REG = (uint8) ((curEp - 1u) << USBFS_DYN_RECONFIG_EP_SHIFT); + + /* Request for dynamic re-configuration of endpoint. */ + USBFS_DYN_RECONFIG_REG |= USBFS_DYN_RECONFIG_ENABLE; + + /* Wait until block is ready for re-configuration */ + while (0u == (USBFS_DYN_RECONFIG_REG & USBFS_DYN_RECONFIG_RDY_STS)) + { + } + + /* Once DYN_RECONFIG_RDY_STS bit is set, FW can change the EP configuration. */ + /* Change EP Type with new direction */ + if (0u != (pEP->addr & USBFS_DIR_IN)) + { + /* Set endpoint type: 0 - IN and 1 - OUT. */ + USBFS_EP_TYPE_REG &= (uint8) ~(uint8)((uint8) 0x01u << (curEp - 1u)); + + #if (CY_PSOC4) + /* Clear DMA_TERMIN for IN endpoint */ + USBFS_ARB_EP_BASE.arbEp[curEp].epIntEn &= (uint32) ~USBFS_ARB_EPX_INT_DMA_TERMIN; + #endif /* (CY_PSOC4) */ + } + else + { + /* Set endpoint type: 0 - IN and 1- OUT. */ + USBFS_EP_TYPE_REG |= (uint8) ((uint8) 0x01u << (curEp - 1u)); + + #if (CY_PSOC4) + /* Set DMA_TERMIN for OUT endpoint */ + USBFS_ARB_EP_BASE.arbEp[curEp].epIntEn |= (uint32) USBFS_ARB_EPX_INT_DMA_TERMIN; + #endif /* (CY_PSOC4) */ + } + + /* Complete dynamic re-configuration: all endpoint related status and signals + * are set into the default state. + */ + USBFS_DYN_RECONFIG_REG &= (uint8) ~USBFS_DYN_RECONFIG_ENABLE; + + #else + USBFS_SIE_EP_BASE.sieEp[curEp].epCnt0 = HI8(USBFS_EP[curEp].bufferSize); + USBFS_SIE_EP_BASE.sieEp[curEp].epCnt1 = LO8(USBFS_EP[curEp].bufferSize); + + #if (CY_PSOC4) + USBFS_ARB_EP16_BASE.arbEp[curEp].rwRa16 = (uint32) USBFS_EP[curEp].buffOffset; + USBFS_ARB_EP16_BASE.arbEp[curEp].rwWa16 = (uint32) USBFS_EP[curEp].buffOffset; + #else + USBFS_ARB_EP_BASE.arbEp[curEp].rwRa = LO8(USBFS_EP[curEp].buffOffset); + USBFS_ARB_EP_BASE.arbEp[curEp].rwRaMsb = HI8(USBFS_EP[curEp].buffOffset); + USBFS_ARB_EP_BASE.arbEp[curEp].rwWa = LO8(USBFS_EP[curEp].buffOffset); + USBFS_ARB_EP_BASE.arbEp[curEp].rwWaMsb = HI8(USBFS_EP[curEp].buffOffset); + #endif /* (CY_PSOC4) */ + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + } + + pEP = &pEP[1u]; /* Get next EP element */ + } + + /* The main loop has to re-enable DMA and OUT endpoint */ + } +} + + +/******************************************************************************* +* Function Name: USBFS_GetConfigTablePtr +****************************************************************************//** +* +* This routine returns a pointer a configuration table entry +* +* \param confIndex: Configuration Index +* +* \return +* Device Descriptor pointer or NULL when descriptor does not exist. +* +*******************************************************************************/ +const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex) + +{ + /* Device Table */ + const T_USBFS_LUT CYCODE *pTmp; + + pTmp = (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list; + + /* The first entry points to the Device Descriptor, + * the second entry point to the BOS Descriptor + * the rest configuration entries. + * Set pointer to the first Configuration Descriptor + */ + pTmp = &pTmp[2u]; + /* For this table, c is the number of configuration descriptors */ + if(confIndex >= pTmp->c) /* Verify that required configuration descriptor exists */ + { + pTmp = (const T_USBFS_LUT CYCODE *) NULL; + } + else + { + pTmp = (const T_USBFS_LUT CYCODE *) pTmp[confIndex].p_list; + } + + return (pTmp); +} + + +#if (USBFS_BOS_ENABLE) + /******************************************************************************* + * Function Name: USBFS_GetBOSPtr + ****************************************************************************//** + * + * This routine returns a pointer a BOS table entry + * + * + * + * \return + * BOS Descriptor pointer or NULL when descriptor does not exist. + * + *******************************************************************************/ + const T_USBFS_LUT CYCODE *USBFS_GetBOSPtr(void) + + { + /* Device Table */ + const T_USBFS_LUT CYCODE *pTmp; + + pTmp = (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list; + + /* The first entry points to the Device Descriptor, + * the second entry points to the BOS Descriptor + */ + pTmp = &pTmp[1u]; + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + return (pTmp); + } +#endif /* (USBFS_BOS_ENABLE) */ + + +/******************************************************************************* +* Function Name: USBFS_GetDeviceTablePtr +****************************************************************************//** +* +* This routine returns a pointer to the Device table +* +* \return +* Device Table pointer +* +*******************************************************************************/ +const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void) + +{ + /* Device Table */ + return( (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list ); +} + + +/******************************************************************************* +* Function Name: USB_GetInterfaceClassTablePtr +****************************************************************************//** +* +* This routine returns Interface Class table pointer, which contains +* the relation between interface number and interface class. +* +* \return +* Interface Class table pointer. +* +*******************************************************************************/ +const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) + +{ + const T_USBFS_LUT CYCODE *pTmp; + const uint8 CYCODE *pInterfaceClass; + uint8 currentInterfacesNum; + + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + if (pTmp != NULL) + { + currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES]; + /* Third entry in the LUT starts the Interface Table pointers */ + /* The INTERFACE_CLASS table is located after all interfaces */ + pTmp = &pTmp[currentInterfacesNum + 2u]; + pInterfaceClass = (const uint8 CYCODE *) pTmp->p_list; + } + else + { + pInterfaceClass = (const uint8 CYCODE *) NULL; + } + + return (pInterfaceClass); +} + + +/******************************************************************************* +* Function Name: USBFS_TerminateEP +****************************************************************************//** +* +* This function terminates the specified USBFS endpoint. +* This function should be used before endpoint reconfiguration. +* +* \param ep Contains the data endpoint number. +* +* \reentrant +* No. +* +* \sideeffect +* +* The device responds with a NAK for any transactions on the selected endpoint. +* +*******************************************************************************/ +void USBFS_TerminateEP(uint8 epNumber) +{ + /* Get endpoint number */ + epNumber &= USBFS_DIR_UNUSED; + + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + /* Set the endpoint Halt */ + USBFS_EP[epNumber].hwEpState |= USBFS_ENDPOINT_STATUS_HALT; + + /* Clear the data toggle */ + USBFS_EP[epNumber].epToggle = 0u; + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_ALLOWED; + + if ((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_MODE_NAK_IN; + } + else + { + /* OUT Endpoint */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_MODE_NAK_OUT; + } + } +} + + +/******************************************************************************* +* Function Name: USBFS_SetEndpointHalt +****************************************************************************//** +* +* This routine handles set endpoint halt. +* +* \return +* requestHandled. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_SetEndpointHalt(void) +{ + uint8 requestHandled = USBFS_FALSE; + uint8 ep; + + /* Set endpoint halt */ + ep = USBFS_wIndexLoReg & USBFS_DIR_UNUSED; + + if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) + { + /* Set the endpoint Halt */ + USBFS_EP[ep].hwEpState |= (USBFS_ENDPOINT_STATUS_HALT); + + /* Clear the data toggle */ + USBFS_EP[ep].epToggle = 0u; + USBFS_EP[ep].apiEpState |= USBFS_NO_EVENT_ALLOWED; + + if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = (USBFS_MODE_STALL_DATA_EP | + USBFS_MODE_ACK_IN); + } + else + { + /* OUT Endpoint */ + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = (USBFS_MODE_STALL_DATA_EP | + USBFS_MODE_ACK_OUT); + } + requestHandled = USBFS_InitNoDataControlTransfer(); + } + + return (requestHandled); +} + + +/******************************************************************************* +* Function Name: USBFS_ClearEndpointHalt +****************************************************************************//** +* +* This routine handles clear endpoint halt. +* +* \return +* requestHandled. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_ClearEndpointHalt(void) +{ + uint8 requestHandled = USBFS_FALSE; + uint8 ep; + + /* Clear endpoint halt */ + ep = USBFS_wIndexLoReg & USBFS_DIR_UNUSED; + + if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) + { + /* Clear the endpoint Halt */ + USBFS_EP[ep].hwEpState &= (uint8) ~USBFS_ENDPOINT_STATUS_HALT; + + /* Clear the data toggle */ + USBFS_EP[ep].epToggle = 0u; + + /* Clear toggle bit for already armed packet */ + USBFS_SIE_EP_BASE.sieEp[ep].epCnt0 &= (uint8) ~(uint8)USBFS_EPX_CNT_DATA_TOGGLE; + + /* Return API State as it was defined before */ + USBFS_EP[ep].apiEpState &= (uint8) ~USBFS_NO_EVENT_ALLOWED; + + if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + if(USBFS_EP[ep].apiEpState == USBFS_IN_BUFFER_EMPTY) + { + /* Wait for next packet from application */ + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_IN; + } + else /* Continue armed transfer */ + { + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_ACK_IN; + } + } + else + { + /* OUT Endpoint */ + if (USBFS_EP[ep].apiEpState == USBFS_OUT_BUFFER_FULL) + { + /* Allow application to read full buffer */ + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_OUT; + } + else /* Mark endpoint as empty, so it will be reloaded */ + { + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_ACK_OUT; + } + } + + requestHandled = USBFS_InitNoDataControlTransfer(); + } + + return(requestHandled); +} + + +/******************************************************************************* +* Function Name: USBFS_ValidateAlternateSetting +****************************************************************************//** +* +* Validates (and records) a SET INTERFACE request. +* +* \return +* requestHandled. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_ValidateAlternateSetting(void) +{ + uint8 requestHandled = USBFS_FALSE; + + uint8 interfaceNum; + uint8 curInterfacesNum; + const T_USBFS_LUT CYCODE *pTmp; + + /* Get interface number from the request. */ + interfaceNum = (uint8) USBFS_wIndexLoReg; + + /* Get number of interfaces for current configuration. */ + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + curInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES]; + + /* Validate that interface number is within range. */ + if ((interfaceNum <= curInterfacesNum) || (interfaceNum <= USBFS_MAX_INTERFACES_NUMBER)) + { + /* Save current and new alternate settings (come with request) to make + * desicion about following endpoint re-configuration. + */ + USBFS_interfaceSettingLast[interfaceNum] = USBFS_interfaceSetting[interfaceNum]; + USBFS_interfaceSetting[interfaceNum] = (uint8) USBFS_wValueLoReg; + + requestHandled = USBFS_TRUE; + } + + return (requestHandled); +} + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_vnd.c b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_vnd.c new file mode 100644 index 0000000000..8ec9808291 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/USBFS_vnd.c @@ -0,0 +1,109 @@ +/***************************************************************************//** +* \file USBFS_vnd.c +* \version 3.20 +* +* \brief +* This file contains the USB vendor request handler. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "USBFS_pvt.h" + + +#if(USBFS_EXTERN_VND == USBFS_FALSE) + +/*************************************** +* Vendor Specific Declarations +***************************************/ + +/* `#START VENDOR_SPECIFIC_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_HandleVendorRqst +****************************************************************************//** +* +* This routine provide users with a method to implement vendor specific +* requests. +* +* To implement vendor specific requests, add your code in this function to +* decode and disposition the request. If the request is handled, your code +* must set the variable "requestHandled" to TRUE, indicating that the +* request has been handled. +* +* \return +* requestHandled. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_HandleVendorRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + + /* Check request direction: D2H or H2D. */ + if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H)) + { + /* Handle direction from device to host. */ + + switch (USBFS_bRequestReg) + { + case USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR: + #if defined(USBFS_ENABLE_MSOS_STRING) + USBFS_currentTD.pData = (volatile uint8 *) &USBFS_MSOS_CONFIGURATION_DESCR[0u]; + USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u]; + requestHandled = USBFS_InitControlRead(); + #endif /* (USBFS_ENABLE_MSOS_STRING) */ + break; + + default: + break; + } + } + + /* `#START VENDOR_SPECIFIC_CODE` Place your vendor specific request here */ + + /* `#END` */ + +#ifdef USBFS_HANDLE_VENDOR_RQST_CALLBACK + if (USBFS_FALSE == requestHandled) + { + requestHandled = USBFS_HandleVendorRqst_Callback(); + } +#endif /* (USBFS_HANDLE_VENDOR_RQST_CALLBACK) */ + + return (requestHandled); +} + + +/******************************************************************************* +* Additional user functions supporting Vendor Specific Requests +********************************************************************************/ + +/* `#START VENDOR_SPECIFIC_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + + +#endif /* USBFS_EXTERN_VND */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/core_cm3_psoc5.h b/source/hic_hal/cypress/psoc5lp/PSoC5/core_cm3_psoc5.h new file mode 100644 index 0000000000..d3c1c98dc2 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/core_cm3_psoc5.h @@ -0,0 +1,59 @@ +/******************************************************************************* +* \file core_cm3_psoc5.h +* \version 5.70 +* +* \brief Provides important type information for the PSoC5. This includes types +* necessary for core_cm3.h. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + + +#if !defined(__CORE_CM3_PSOC5_H__) +#define __CORE_CM3_PSOC5_H__ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1 /*!< 15 Cortex-M3 System Tick Interrupt */ +/****** PSoC5 Peripheral Interrupt Numbers *******************************************************/ + /* Not relevant. All peripheral interrupts are defined by the user */ +} IRQn_Type; + +#include + +#define __CHECK_DEVICE_DEFINES + +#define __CM3_REV 0x0201 + +#define __MPU_PRESENT 0 +#define __NVIC_PRIO_BITS 3 +#define __Vendor_SysTickConfig 0 + +#include + + +#endif /* __CORE_CM3_PSOC5_H__ */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/cyPm.c b/source/hic_hal/cypress/psoc5lp/PSoC5/cyPm.c new file mode 100644 index 0000000000..b70bebd3cc --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/cyPm.c @@ -0,0 +1,1876 @@ +/***************************************************************************//** +* \file cyPm.c +* \version 5.70 +* +* \brief Provides an API for the power management. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "cyPm.h" + + + +/******************************************************************* +* Place your includes, defines, and code here. Do not use the merge +* region below unless any component datasheet suggests doing so. +*******************************************************************/ +/* `#START CY_PM_HEADER_INCLUDE` */ + +/* `#END` */ + + +static CY_PM_BACKUP_STRUCT cyPmBackup; +static CY_PM_CLOCK_BACKUP_STRUCT cyPmClockBackup; + +/* Convertion table between register's values and frequency in MHz */ +static const uint8 CYCODE cyPmImoFreqReg2Mhz[7u] = {12u, 6u, 24u, 3u, 48u, 62u, 74u}; + +/* Function Prototypes */ +static void CyPmHibSaveSet(void); +static void CyPmHibRestore(void) ; + +static void CyPmHibSlpSaveSet(void) ; +static void CyPmHibSlpRestore(void) ; + +static void CyPmHviLviSaveDisable(void) ; +static void CyPmHviLviRestore(void) ; + + +/******************************************************************************* +* Function Name: CyPmSaveClocks +****************************************************************************//** +* +* This function is called in preparation for entering sleep or hibernate low +* power modes. Saves all the states of the clocking system that do not persist +* during sleep/hibernate or that need to be altered in preparation for +* sleep/hibernate. Shutdowns all the digital and analog clock dividers for the +* active power mode configuration. +* +* Switches the master clock over to the IMO and shuts down the PLL and MHz +* Crystal. The IMO frequency is set to either 12 MHz or 48 MHz to match the +* Design-Wide Resources System Editor "Enable Fast IMO During Startup" setting. +* The ILO and 32 KHz oscillators are not impacted. The current Flash wait state +* setting is saved and the Flash wait state setting is set for the current IMO +* speed. +* +* Note If the Master Clock source is routed through the DSI inputs, then it +* must be set manually to another source before using the +* CyPmSaveClocks()/CyPmRestoreClocks() functions. +* +* \sideeffect +* All peripheral clocks are going to be off after this API method call. +* +*******************************************************************************/ +void CyPmSaveClocks(void) +{ + /* Digital and analog clocks - save enable state and disable them all */ + cyPmClockBackup.enClkA = CY_PM_ACT_CFG1_REG & CY_PM_ACT_EN_CLK_A_MASK; + cyPmClockBackup.enClkD = CY_PM_ACT_CFG2_REG; + CY_PM_ACT_CFG1_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_A_MASK)); + CY_PM_ACT_CFG2_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_D_MASK)); + + /* Save current flash wait cycles and set the maximum value */ + cyPmClockBackup.flashWaitCycles = CY_PM_CACHE_CR_CYCLES_MASK & CY_PM_CACHE_CR_REG; + CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); + + /* IMO - save current IMO MHz OSC frequency and USB mode is on bit */ + cyPmClockBackup.imoFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; + cyPmClockBackup.imoUsbClk = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_USB; + + /* IMO doubler - save enable state */ + if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON)) + { + /* IMO doubler enabled - save and disable */ + cyPmClockBackup.imo2x = CY_PM_ENABLED; + } + else + { + /* IMO doubler disabled */ + cyPmClockBackup.imo2x = CY_PM_DISABLED; + } + + /* Master clock - save source */ + cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK; + + /* Switch Master clock's source from PLL's output to PLL's source */ + if(CY_MASTER_SOURCE_PLL == cyPmClockBackup.masterClkSrc) + { + switch (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_PLL_SRC_MASK) + { + case CY_PM_CLKDIST_PLL_SRC_IMO: + CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO); + break; + + case CY_PM_CLKDIST_PLL_SRC_XTAL: + CyMasterClk_SetSource(CY_MASTER_SOURCE_XTAL); + break; + + case CY_PM_CLKDIST_PLL_SRC_DSI: + CyMasterClk_SetSource(CY_MASTER_SOURCE_DSI); + break; + + default: + CYASSERT(0u != 0u); + break; + } + } + + /* PLL - check enable state, disable if needed */ + if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE)) + { + /* PLL is enabled - save state and disable */ + cyPmClockBackup.pllEnableState = CY_PM_ENABLED; + CyPLL_OUT_Stop(); + } + else + { + /* PLL is disabled - save state */ + cyPmClockBackup.pllEnableState = CY_PM_DISABLED; + } + + /* IMO - set appropriate frequency for LPM */ + CyIMO_SetFreq(CY_PM_IMO_FREQ_LPM); + + /* IMO - save enable state and enable without wait to settle */ + if(0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)) + { + /* IMO - save enabled state */ + cyPmClockBackup.imoEnable = CY_PM_ENABLED; + } + else + { + /* IMO - save disabled state */ + cyPmClockBackup.imoEnable = CY_PM_DISABLED; + + /* Enable the IMO. Use software delay instead of the FTW-based inside */ + CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE); + + /* Settling time of the IMO is of the order of less than 6us */ + CyDelayUs(6u); + } + + /* IMO - save the current IMOCLK source and set to IMO if not yet */ + if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_XCLKEN)) + { + /* DSI or XTAL CLK */ + cyPmClockBackup.imoClkSrc = + (0u == (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO2X_SRC)) ? CY_IMO_SOURCE_DSI : CY_IMO_SOURCE_XTAL; + + /* IMO - set IMOCLK source to IMO */ + CyIMO_SetSource(CY_IMO_SOURCE_IMO); + } + else + { + /* IMO */ + cyPmClockBackup.imoClkSrc = CY_IMO_SOURCE_IMO; + } + + /* Save clk_imo source */ + cyPmClockBackup.clkImoSrc = CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK; + + /* If IMOCLK2X or SPC OSC is source for clk_imo, set it to IMOCLK */ + if(CY_PM_CLKDIST_IMO_OUT_IMO != cyPmClockBackup.clkImoSrc) + { + /* Set IMOCLK to source for clk_imo */ + CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) | + CY_PM_CLKDIST_IMO_OUT_IMO; + } /* Need to change nothing if IMOCLK is source clk_imo */ + + /* IMO doubler - disable it (saved above) */ + if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON)) + { + CyIMO_DisableDoubler(); + } + + /* Master clock - save divider and set it to divide-by-one (if no yet) */ + cyPmClockBackup.clkSyncDiv = CY_PM_CLKDIST_MSTR0_REG; + if(CY_PM_DIV_BY_ONE != cyPmClockBackup.clkSyncDiv) + { + CyMasterClk_SetDivider(CY_PM_DIV_BY_ONE); + } /* No change if master clock divider is 1 */ + + /* Master clock source - set it to IMO if not yet. */ + if(CY_MASTER_SOURCE_IMO != cyPmClockBackup.masterClkSrc) + { + CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO); + } /* No change if master clock source is IMO */ + + /* Bus clock - save divider and set it, if needed, to divide-by-one */ + cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u); + cyPmClockBackup.clkBusDiv |= CY_PM_CLK_BUS_LSB_DIV_REG; + if(CY_PM_BUS_CLK_DIV_BY_ONE != cyPmClockBackup.clkBusDiv) + { + CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE); + } /* Do nothing if saved and actual values are equal */ + + /* Set number of wait cycles for flash according to CPU frequency in MHz */ + CyFlash_SetWaitCycles((uint8)CY_PM_GET_CPU_FREQ_MHZ); + + /* MHz ECO - check enable state and disable if needed */ + if(0u != (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_ENABLE)) + { + /* MHz ECO is enabled - save state and disable */ + cyPmClockBackup.xmhzEnableState = CY_PM_ENABLED; + CyXTAL_Stop(); + } + else + { + /* MHz ECO is disabled - save state */ + cyPmClockBackup.xmhzEnableState = CY_PM_DISABLED; + } + + + /*************************************************************************** + * Save the enable state of delay between the system bus clock and each of the + * 4 individual analog clocks. This bit non-retention and its value should + * be restored on wakeup. + ***************************************************************************/ + if(0u != (CY_PM_CLKDIST_DELAY_REG & CY_PM_CLKDIST_DELAY_EN)) + { + cyPmClockBackup.clkDistDelay = CY_PM_ENABLED; + } + else + { + cyPmClockBackup.clkDistDelay = CY_PM_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: CyPmRestoreClocks +****************************************************************************//** +* +* Restores any state that was preserved by the last call to CyPmSaveClocks(). +* The Flash wait state setting is also restored. +* +* Note If the Master Clock source is routed through the DSI inputs, then it +* must be set manually to another source before using the +* CyPmSaveClocks()/CyPmRestoreClocks() functions. +* +* PSoC 3 and PSoC 5LP: +* The merge region could be used to process state when the megahertz crystal is +* not ready after a hold-off timeout. +* +* PSoC 5: +* The 130 ms is given for the megahertz crystal to stabilize. Its readiness is +* not verified after a hold-off timeout. +* +*******************************************************************************/ +void CyPmRestoreClocks(void) +{ + cystatus status = CYRET_TIMEOUT; + uint16 i; + uint16 clkBusDivTmp; + + + /* Convertion table between CyIMO_SetFreq() parameters and register's value */ + const uint8 CYCODE cyPmImoFreqMhz2Reg[7u] = { + CY_IMO_FREQ_12MHZ, CY_IMO_FREQ_6MHZ, CY_IMO_FREQ_24MHZ, CY_IMO_FREQ_3MHZ, + CY_IMO_FREQ_48MHZ, 5u, 6u}; + + /* Restore enable state of delay between system bus clock and ACLKs. */ + if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay) + { + /* Delay for both bandgap and delay line to settle out */ + CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) * + CY_PM_GET_CPU_FREQ_MHZ); + + CY_PM_CLKDIST_DELAY_REG |= CY_PM_CLKDIST_DELAY_EN; + } + + /* MHz ECO restore state */ + if(CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) + { + /*********************************************************************** + * Enabling XMHZ XTAL. The actual CyXTAL_Start() with a non zero wait + * period uses FTW for period measurement. This could cause a problem + * if CTW/FTW is used as a wake up time in the low power modes APIs. + * So, the XTAL wait procedure is implemented with a software delay. + ***********************************************************************/ + + /* Enable XMHZ XTAL with no wait */ + (void) CyXTAL_Start(CY_PM_XTAL_MHZ_NO_WAIT); + + /* Read XERR bit to clear it */ + (void) CY_PM_FASTCLK_XMHZ_CSR_REG; + + /* Wait */ + for(i = CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US; i > 0u; i--) + { + /* Make a 200 microseconds delay */ + CyDelayCycles((uint32)CY_PM_WAIT_200_US * CY_PM_GET_CPU_FREQ_MHZ); + + /* High output indicates oscillator failure */ + if(0u == (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_XERR)) + { + status = CYRET_SUCCESS; + break; + } + } + + if(CYRET_TIMEOUT == status) + { + /******************************************************************* + * Process the situation when megahertz crystal is not ready. + * Time to stabilize the value is crystal specific. + *******************************************************************/ + /* `#START_MHZ_ECO_TIMEOUT` */ + + /* `#END` */ + + #ifdef CY_BOOT_CY_PM_RESTORE_CLOCKS_ECO_TIMEOUT_CALLBACK + CyBoot_CyPmRestoreClocks_EcoTimeout_Callback(); + #endif /* CY_BOOT_CY_PM_RESTORE_CLOCKS_ECO_TIMEOUT_CALLBACK */ + } + } /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */ + + + /* Temporary set maximum flash wait cycles */ + CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); + + /* XTAL and DSI clocks are ready to be source for Master clock. */ + if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) || + (CY_PM_MASTER_CLK_SRC_DSI == cyPmClockBackup.masterClkSrc)) + { + /* Restore Master clock's divider */ + if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv) + { + /* Restore Master clock divider */ + CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv); + } + + /* Restore Master clock source */ + CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc); + } + + /* IMO - restore IMO frequency */ + if((0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) && + (CY_IMO_FREQ_24MHZ == cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq])) + { + /* Restore IMO frequency (24 MHz) and trim it for USB */ + CyIMO_SetFreq(CY_IMO_FREQ_USB); + } + else + { + /* Restore IMO frequency */ + CyIMO_SetFreq(cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq]); + + if(0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) + { + CY_PM_FASTCLK_IMO_CR_REG |= CY_PM_FASTCLK_IMO_CR_USB; + } + else + { + CY_PM_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_PM_FASTCLK_IMO_CR_USB)); + } + } + + /* IMO - restore enable state if needed */ + if((CY_PM_ENABLED == cyPmClockBackup.imoEnable) && + (0u == (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))) + { + /* IMO - restore enabled state */ + CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE); + } + + /* IMO - restore IMOCLK source */ + CyIMO_SetSource(cyPmClockBackup.imoClkSrc); + + /* Restore IMO doubler enable state (turned off by CyPmSaveClocks()) */ + if(CY_PM_ENABLED == cyPmClockBackup.imo2x) + { + CyIMO_EnableDoubler(); + } + + /* IMO - restore clk_imo source, if needed */ + if(cyPmClockBackup.clkImoSrc != (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK)) + { + CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) | + cyPmClockBackup.clkImoSrc; + } + + + /* PLL restore state */ + if(CY_PM_ENABLED == cyPmClockBackup.pllEnableState) + { + /*********************************************************************** + * Enable PLL. The actual CyPLL_OUT_Start() without wait period uses FTW + * for period measurement. This could cause a problem if CTW/FTW is used + * as a wakeup time in the low power modes APIs. To omit this issue PLL + * wait procedure is implemented with a software delay. + ***********************************************************************/ + status = CYRET_TIMEOUT; + + /* Enable PLL */ + (void) CyPLL_OUT_Start(CY_PM_PLL_OUT_NO_WAIT); + + /* Read to clear lock status after delay */ + CyDelayUs((uint32)80u); + (void) CY_PM_FASTCLK_PLL_SR_REG; + + /* It should take 250 us lock: 251-80 = 171 */ + for(i = 171u; i > 0u; i--) + { + CyDelayUs((uint32)1u); + + /* Accept PLL is OK after two consecutive polls indicate PLL lock */ + if((0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)) && + (0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED))) + { + status = CYRET_SUCCESS; + break; + } + } + + if(CYRET_TIMEOUT == status) + { + /******************************************************************* + * Process the situation when PLL is not ready. + *******************************************************************/ + /* `#START_PLL_TIMEOUT` */ + + /* `#END` */ + + #ifdef CY_BOOT_CY_PM_RESTORE_CLOCKS_PLL_TIMEOUT_CALLBACK + CyBoot_CyPmRestoreClocks_PllTimeout_Callback(); + #endif /* CY_BOOT_CY_PM_RESTORE_CLOCKS_PLL_TIMEOUT_CALLBACK */ + } + } /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */ + + + /* PLL and IMO is ready to be source for Master clock */ + if((CY_PM_MASTER_CLK_SRC_IMO == cyPmClockBackup.masterClkSrc) || + (CY_PM_MASTER_CLK_SRC_PLL == cyPmClockBackup.masterClkSrc)) + { + /* Restore Master clock divider */ + if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv) + { + CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv); + } + + /* Restore Master clock source */ + CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc); + } + + /* IMO - disable if it was originally disabled */ + if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) && + (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))) + { + CyIMO_Stop(); + } + + /* Bus clock - restore divider, if needed */ + clkBusDivTmp = (uint16) ((uint16)CY_PM_CLK_BUS_MSB_DIV_REG << 8u); + clkBusDivTmp |= CY_PM_CLK_BUS_LSB_DIV_REG; + if(cyPmClockBackup.clkBusDiv != clkBusDivTmp) + { + CyBusClk_SetDivider(cyPmClockBackup.clkBusDiv); + } + + /* Restore flash wait cycles */ + CY_PM_CACHE_CR_REG = ((CY_PM_CACHE_CR_REG & ((uint8)(~CY_PM_CACHE_CR_CYCLES_MASK))) | + cyPmClockBackup.flashWaitCycles); + + /* Digital and analog clocks - restore state */ + CY_PM_ACT_CFG1_REG = cyPmClockBackup.enClkA; + CY_PM_ACT_CFG2_REG = cyPmClockBackup.enClkD; +} + + +/******************************************************************************* +* Function Name: CyPmAltAct +****************************************************************************//** +* +* Puts the part into the Alternate Active (Standby) state. The Alternate Active +* state can allow for any of the capabilities of the device to be active, but +* the operation of this function is dependent on the CPU being disabled during +* the Alternate Active state. The configuration code and the component APIs +* will configure the template for the Alternate Active state to be the same as +* the Active state with the exception that the CPU will be disabled during +* Alternate Active. +* +* Note Before calling this function, you must manually configure the power mode +* of the source clocks for the timer that is used as the wakeup timer. +* +* PSoC 3: +* Before switching to Alternate Active, if a wakeupTime other than NONE is +* specified, then the appropriate timer state is configured as specified with +* the interrupt for that timer disabled. The wakeup source will be the +* combination of the values specified in the wakeupSource and any timer +* specified in the wakeupTime argument. Once the wakeup condition is +* satisfied, then all saved state is restored and the function returns in the +* Active state. +* +* Note that if the wakeupTime is made with a different value, the period before +* the wakeup occurs can be significantly shorter than the specified time. If +* the next call is made with the same wakeupTime value, then the wakeup will +* occur the specified period after the previous wakeup occurred. +* +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. If the CTW, FTW or One PPS is already +* configured for wakeup, for example with the SleepTimer or RTC components, +* then specify NONE for the wakeupTime and include the appropriate source for +* wakeupSource. +* +* PSoC 5LP: +* This function is used to both enter the Alternate Active mode and halt the +* processor. For PSoC 3 these two actions must be paired together. With PSoC +* 5LP the processor can be halted independently with the __WFI() function from +* the CMSIS library that is included in Creator. This function should be used +* instead when the action required is just to halt the processor until an +* enabled interrupt occurs. +* +* The wakeupTime parameter is not used for this device. It must be set to zero +* (PM_ALT_ACT_TIME_NONE). The wake up time configuration can be done by a +* separate component: the CTW wakeup interval should be configured with the +* Sleep Timer component and one second interval should be configured with the +* RTC component. +* +* The wakeup behavior depends on the wakeupSource parameter in the following +* manner: upon function execution the device will be switched from Active to +* Alternate Active mode and then the CPU will be halted. When an enabled wakeup +* event occurs the device will return to Active mode. Similarly when an +* enabled interrupt occurs the CPU will be started. These two actions will +* occur together provided that the event that occurs is an enabled wakeup +* source and also generates an interrupt. If just the wakeup event occurs then +* the device will be in Active mode, but the CPU will remain halted waiting for +* an interrupt. If an interrupt occurs from something other than a wakeup +* source, then the CPU will restart with the device in Alternate Active mode +* until a wakeup event occurs. +* +* For example, if CyPmAltAct(PM_ALT_ACT_TIME_NONE, PM_ALT_ACT_SRC_PICU) is +* called and PICU interrupt occurs, the CPU will be started and device will be +* switched into Active mode. And if CyPmAltAct(PM_ALT_ACT_TIME_NONE, +* PM_ALT_ACT_SRC_NONE) is called and PICU interrupt occurs, the CPU will be +* started while device remains in Alternate Active mode. +* +* \param wakeupTime: Specifies a timer wakeup source and the frequency of that +* source. For PSoC 5LP this parameter is ignored. +* +* Define Time +* PM_ALT_ACT_TIME_NONE None +* \param PM_ALT_ACT_TIME_ONE_PPS One PPS: 1 second +* \param PM_ALT_ACT_TIME_CTW_2MS CTW: 2 ms +* \param PM_ALT_ACT_TIME_CTW_4MS CTW: 4 ms +* \param PM_ALT_ACT_TIME_CTW_8MS CTW: 8 ms +* \param PM_ALT_ACT_TIME_CTW_16MS CTW: 16 ms +* \param PM_ALT_ACT_TIME_CTW_32MS CTW: 32 ms +* \param PM_ALT_ACT_TIME_CTW_64MS CTW: 64 ms +* \param PM_ALT_ACT_TIME_CTW_128MS CTW: 128 ms +* \param PM_ALT_ACT_TIME_CTW_256MS CTW: 256 ms +* \param PM_ALT_ACT_TIME_CTW_512MS CTW: 512 ms +* \param PM_ALT_ACT_TIME_CTW_1024MS CTW: 1024 ms +* \param PM_ALT_ACT_TIME_CTW_2048MS CTW: 2048 ms +* \param PM_ALT_ACT_TIME_CTW_4096MS CTW: 4096 ms +* PM_ALT_ACT_TIME_FTW(1-256)* FTW: 10us to 2.56 ms +* +* \param *Note: PM_ALT_ACT_TIME_FTW() is a macro that takes an argument that +* specifies how many increments of 10 us to delay. + For PSoC 3 silicon the valid range of values is 1 to 256. +* +* \param wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if +* a wakeupTime has been specified, the associated timer will +* be included as a wakeup source. +* +* Define Source +* PM_ALT_ACT_SRC_NONE None +* PM_ALT_ACT_SRC_COMPARATOR0 Comparator 0 +* PM_ALT_ACT_SRC_COMPARATOR1 Comparator 1 +* PM_ALT_ACT_SRC_COMPARATOR2 Comparator 2 +* PM_ALT_ACT_SRC_COMPARATOR3 Comparator 3 +* PM_ALT_ACT_SRC_INTERRUPT Interrupt +* PM_ALT_ACT_SRC_PICU PICU +* PM_ALT_ACT_SRC_I2C I2C +* PM_ALT_ACT_SRC_BOOSTCONVERTER Boost Converter +* PM_ALT_ACT_SRC_FTW Fast Timewheel* +* PM_ALT_ACT_SRC_VD High and Low Voltage Detection (HVI, LVI)* +* PM_ALT_ACT_SRC_CTW Central Timewheel** +* PM_ALT_ACT_SRC_ONE_PPS One PPS** +* PM_ALT_ACT_SRC_LCD LCD +* +* \param *Note : FTW and HVI/LVI wakeup signals are in the same mask bit. +* \param **Note: CTW and One PPS wakeup signals are in the same mask bit. +* +* When specifying a Comparator as the wakeupSource, an instance specific define +* that will track with the specific comparator that the instance +* is placed into should be used. As an example, for a Comparator instance named +* \param MyComp the value to OR into the mask is: MyComp_ctComp__CMP_MASK. +* +* When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus() +* function must be called upon wakeup with a corresponding parameter. Please +* refer to the CyPmReadStatus() API in the System Reference Guide for more +* information. +* +* Reentrant: +* No +* +* \sideeffect +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is +* used as wakeup time) or ILO 100 KHz (if the FTW timer is used as wakeup time) +* will be left started. +* +*******************************************************************************/ +void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) +{ + #if(CY_PSOC5) + + /* Arguments expected to be 0 */ + CYASSERT(PM_ALT_ACT_TIME_NONE == wakeupTime); + + if(0u != wakeupTime) + { + /* To remove unreferenced local variable warning */ + } + + #endif /* (CY_PSOC5) */ + + + #if(CY_PSOC3) + + /* FTW - save current and set new configuration */ + if((wakeupTime >= PM_ALT_ACT_TIME_FTW(1u)) && (wakeupTime <= PM_ALT_ACT_TIME_FTW(256u))) + { + CyPmFtwSetInterval(PM_ALT_ACT_FTW_INTERVAL(wakeupTime)); + + /* Include associated timer to wakeupSource */ + wakeupSource |= PM_ALT_ACT_SRC_FTW; + } + + /* CTW - save current and set new configuration */ + if((wakeupTime >= PM_ALT_ACT_TIME_CTW_2MS) && (wakeupTime <= PM_ALT_ACT_TIME_CTW_4096MS)) + { + /* Save current CTW configuration and set new one */ + CyPmCtwSetInterval((uint8)(wakeupTime - 1u)); + + /* Include associated timer to wakeupSource */ + wakeupSource |= PM_ALT_ACT_SRC_CTW; + } + + /* 1PPS - save current and set new configuration */ + if(PM_ALT_ACT_TIME_ONE_PPS == wakeupTime) + { + /* Save current 1PPS configuration and set new one */ + CyPmOppsSet(); + + /* Include associated timer to wakeupSource */ + wakeupSource |= PM_ALT_ACT_SRC_ONE_PPS; + } + + #endif /* (CY_PSOC3) */ + + + /* Save and set new wake up configuration */ + + /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */ + cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; + CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); + + /* Comparators */ + cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; + CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); + + /* LCD */ + cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; + CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); + + + /* Switch to the Alternate Active mode */ + CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_ALT_ACT); + + /* Recommended readback. */ + (void) CY_PM_MODE_CSR_REG; + + /* Two recommended NOPs to get into the mode. */ + CY_NOP; + CY_NOP; + + /* Execute WFI instruction (for ARM-based devices only) */ + CY_PM_WFI; + + /* Point of return from Alternate Active Mode */ + + /* Restore wake up configuration */ + CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; + CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; + CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; +} + + +/******************************************************************************* +* Function Name: CyPmSleep +****************************************************************************//** +* +* Puts the part into the Sleep state. +* +* Note Before calling this function, you must manually configure the power +* mode of the source clocks for the timer that is used as the wakeup timer. +* +* Note Before calling this function, you must prepare clock tree configuration +* for the low power mode by calling CyPmSaveClocks(). And restore clock +* configuration after CyPmSleep() execution by calling CyPmRestoreClocks(). See +* Power Management section, Clock Configuration subsection of the System +* Reference Guide for more information. +* +* PSoC 3: +* Before switching to Sleep, if a wakeupTime other than NONE is specified, +* then the appropriate timer state is configured as specified with the +* interrupt for that timer disabled. The wakeup source will be a combination +* of the values specified in the wakeupSource and any timer specified in the +* wakeupTime argument. Once the wakeup condition is satisfied, then all saved +* state is restored and the function returns in the Active state. +* +* Note that if the wakeupTime is made with a different value, the period before +* the wakeup occurs can be significantly shorter than the specified time. If +* the next call is made with the same wakeupTime value, then the wakeup will +* occur the specified period after the previous wakeup occurred. +* +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. If the CTW or One PPS is already +* configured for wakeup, for example with the SleepTimer or RTC components, +* then specify NONE for the wakeupTime and include the appropriate source for +* wakeupSource. +* +* PSoC 5LP: +* The wakeupTime parameter is not used and the only NONE can be specified. +* The wakeup time must be configured with the component, SleepTimer for CTW +* intervals and RTC for 1PPS interval. The component must be configured to +* generate interrupt. +* +* \param wakeupTime: Specifies a timer wakeup source and the frequency of that +* source. For PSoC 5LP, this parameter is ignored. +* +* Define Time +* PM_SLEEP_TIME_NONE None +* \param PM_SLEEP_TIME_ONE_PPS One PPS: 1 second +* \param PM_SLEEP_TIME_CTW_2MS CTW: 2 ms +* \param PM_SLEEP_TIME_CTW_4MS CTW: 4 ms +* \param PM_SLEEP_TIME_CTW_8MS CTW: 8 ms +* \param PM_SLEEP_TIME_CTW_16MS CTW: 16 ms +* \param PM_SLEEP_TIME_CTW_32MS CTW: 32 ms +* \param PM_SLEEP_TIME_CTW_64MS CTW: 64 ms +* \param PM_SLEEP_TIME_CTW_128MS CTW: 128 ms +* \param PM_SLEEP_TIME_CTW_256MS CTW: 256 ms +* \param PM_SLEEP_TIME_CTW_512MS CTW: 512 ms +* \param PM_SLEEP_TIME_CTW_1024MS CTW: 1024 ms +* \param PM_SLEEP_TIME_CTW_2048MS CTW: 2048 ms +* \param PM_SLEEP_TIME_CTW_4096MS CTW: 4096 ms +* +* \param wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if +* a wakeupTime has been specified the associated timer will be +* included as a wakeup source. +* +* Define Source +* PM_SLEEP_SRC_NONE None +* PM_SLEEP_SRC_COMPARATOR0 Comparator 0 +* PM_SLEEP_SRC_COMPARATOR1 Comparator 1 +* PM_SLEEP_SRC_COMPARATOR2 Comparator 2 +* PM_SLEEP_SRC_COMPARATOR3 Comparator 3 +* PM_SLEEP_SRC_PICU PICU +* PM_SLEEP_SRC_I2C I2C +* PM_SLEEP_SRC_BOOSTCONVERTER Boost Converter +* PM_SLEEP_SRC_VD High and Low Voltage Detection (HVI, LVI) +* PM_SLEEP_SRC_CTW Central Timewheel* +* PM_SLEEP_SRC_ONE_PPS One PPS* +* PM_SLEEP_SRC_LCD LCD +* +* \param *Note: CTW and One PPS wakeup signals are in the same mask bit. +* +* When specifying a Comparator as the wakeupSource an instance specific define +* should be used that will track with the specific comparator that the instance +* is placed into. As an example for a Comparator instance named MyComp the +* \param value to OR into the mask is: MyComp_ctComp__CMP_MASK. +* +* When CTW or One PPS is used as a wakeup source, the CyPmReadStatus() +* function must be called upon wakeup with corresponding parameter. Please +* refer to the CyPmReadStatus() API in the System Reference Guide for more +* information. +* +* Reentrant: +* No +* +* Side Effects and Restrictions: +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is +* used as wake up time) will be left started. +* +* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to +* measure Hibernate/Sleep regulator settling time after a reset. The holdoff +* delay is measured using rising edges of the 1 kHz ILO. +* +* For PSoC 3 silicon hardware buzz should be disabled before entering a sleep +* power mode. It is disabled by PSoC Creator during startup. +* If a Low Voltage Interrupt (LVI), High Voltage Interrupt (HVI) or Brown Out +* detect (power supply supervising capabilities) are required in a design +* during sleep, use the Central Time Wheel (CTW) to periodically wake the +* device, perform software buzz, and refresh the supervisory services. If LVI, +* HVI, or Brown Out is not required, then CTW is not required. +* Refer to the device errata for more information. +* +*******************************************************************************/ +void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) +{ + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + + /*********************************************************************** + * The Hibernate/Sleep regulator has a settling time after a reset. + * During this time, the system ignores requests to enter Sleep and + * Hibernate modes. The holdoff delay is measured using rising edges of + * the 1 kHz ILO. + ***********************************************************************/ + if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) + { + /* Disable hold off - no action on restore */ + CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; + } + else + { + /* Abort, device is not ready for low power mode entry */ + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); + + return; + } + + + /*********************************************************************** + * PSoC3 < TO6: + * - Hardware buzz must be disabled before the sleep mode entry. + * - Voltage supervision (HVI/LVI) requires hardware buzz, so they must + * be also disabled. + * + * PSoC3 >= TO6: + * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware + * buzz must be enabled before the sleep mode entry and restored on + * the wakeup. + ***********************************************************************/ + #if(CY_PSOC3) + + /* Silicon Revision ID is below TO6 */ + if(CYDEV_CHIP_REV_ACTUAL < 5u) + { + /* Hardware buzz expected to be disabled in Sleep mode */ + CYASSERT(0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ)); + } + + + if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | + CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) + { + if(CYDEV_CHIP_REV_ACTUAL < 5u) + { + /* LVI/HVI requires hardware buzz to be enabled */ + CYASSERT(0u != 0u); + } + else + { + if (0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ)) + { + cyPmBackup.hardwareBuzz = CY_PM_DISABLED; + CY_PM_PWRSYS_WAKE_TR2_REG |= CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ; + } + else + { + cyPmBackup.hardwareBuzz = CY_PM_ENABLED; + } + } + } + + #endif /* (CY_PSOC3) */ + + + /******************************************************************************* + * For ARM-based devices,interrupt is required for the CPU to wake up. The + * Power Management implementation assumes that wakeup time is configured with a + * separate component (component-based wakeup time configuration) for + * interrupt to be issued on terminal count. For more information, refer to the + * Wakeup Time Configuration section of System Reference Guide. + *******************************************************************************/ + #if(CY_PSOC5) + + /* Arguments expected to be 0 */ + CYASSERT(PM_SLEEP_TIME_NONE == wakeupTime); + + if(0u != wakeupTime) + { + /* To remove unreferenced local variable warning */ + } + + #endif /* (CY_PSOC5) */ + + + CyPmHibSlpSaveSet(); + + + #if(CY_PSOC3) + + /* CTW - save current and set new configuration */ + if((wakeupTime >= PM_SLEEP_TIME_CTW_2MS) && (wakeupTime <= PM_SLEEP_TIME_CTW_4096MS)) + { + /* Save current and set new configuration of CTW */ + CyPmCtwSetInterval((uint8)(wakeupTime - 1u)); + + /* Include associated timer to wakeupSource */ + wakeupSource |= PM_SLEEP_SRC_CTW; + } + + /* 1PPS - save current and set new configuration */ + if(PM_SLEEP_TIME_ONE_PPS == wakeupTime) + { + /* Save current and set new configuration of the 1PPS */ + CyPmOppsSet(); + + /* Include associated timer to wakeupSource */ + wakeupSource |= PM_SLEEP_SRC_ONE_PPS; + } + + #endif /* (CY_PSOC3) */ + + + /* Save and set new wake up configuration */ + + /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */ + cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; + CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); + + /* Comparators */ + cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; + CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); + + /* LCD */ + cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; + CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); + + + /******************************************************************* + * Do not use the merge region below unless any component datasheet + * suggests doing so. + *******************************************************************/ + /* `#START CY_PM_JUST_BEFORE_SLEEP` */ + + /* `#END` */ + + #ifdef CY_BOOT_CY_PM_SLEEP_BEFORE_SLEEP_CALLBACK + CyBoot_CyPmSleep_BeforeSleep_Callback(); + #endif /* CY_BOOT_CY_PM_SLEEP_BEFORE_SLEEP_CALLBACK */ + + /* Last moment IMO frequency change */ + if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) + { + /* IMO frequency is 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED; + } + else + { + /* IMO frequency is not 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; + + /* Save IMO frequency */ + cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; + + /* Set IMO frequency to 12 MHz */ + CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); + } + + /* Switch to Sleep mode */ + CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_SLEEP); + + /* Recommended readback. */ + (void) CY_PM_MODE_CSR_REG; + + /* Two recommended NOPs to get into mode. */ + CY_NOP; + CY_NOP; + + /* Execute WFI instruction (for ARM-based devices only) */ + CY_PM_WFI; + + /* Point of return from Sleep Mode */ + + /* Restore last moment IMO frequency change */ + if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz) + { + CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ_MASK))) | + cyPmBackup.imoActFreq; + } + + + /******************************************************************* + * Do not use merge region below unless any component datasheet + * suggest to do so. + *******************************************************************/ + /* `#START CY_PM_JUST_AFTER_WAKEUP_FROM_SLEEP` */ + + /* `#END` */ + + #ifdef CY_BOOT_CY_PM_SLEEP_AFTER_SLEEP_CALLBACK + CyBoot_CyPmSleep_AfterSleep_Callback(); + #endif /* CY_BOOT_CY_PM_SLEEP_AFTER_SLEEP_CALLBACK */ + + /* Restore hardware configuration */ + CyPmHibSlpRestore(); + + + /* Disable hardware buzz, if it was previously enabled */ + #if(CY_PSOC3) + + if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | + CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) + { + if(CYDEV_CHIP_REV_ACTUAL >= 5u) + { + if (CY_PM_DISABLED == cyPmBackup.hardwareBuzz) + { + CY_PM_PWRSYS_WAKE_TR2_REG &= (uint8)(~CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ); + } + } + } + + #endif /* (CY_PSOC3) */ + + + /* Restore current wake up configuration */ + CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; + CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; + CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyPmHibernate +****************************************************************************//** +* +* Puts the part into the Hibernate state. +* +* Before switching to Hibernate, the current status of the PICU wakeup source +* bit is saved and then set. This configures the device to wake up from the +* PICU. Make sure you have at least one pin configured to generate PICU +* interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls +* the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]." +* In the Pins component datasheet, this register is referred to as the IRQ +* option. Once the wakeup occurs, the PICU wakeup source bit is restored and +* the PSoC returns to the Active state. +* +* Reentrant: +* No +* +* \sideeffect +* Applications must wait 20 us before re-entering hibernate or sleep after +* waking up from hibernate. The 20 us allows the sleep regulator time to +* stabilize before the next hibernate / sleep event occurs. The 20 us +* requirement begins when the device wakes up. There is no hardware check that +* this requirement is met. The specified delay should be done on ISR entry. +* +* After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin +* is instance name of the Pins component) function must be called to clear the +* latched pin events to allow the proper Hibernate mode entry and to enable +* detection of future events. +* +* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to +* measure Hibernate/Sleep regulator settling time after a reset. The holdoff +* delay is measured using the rising edges of the 1 kHz ILO. +* +*******************************************************************************/ +void CyPmHibernate(void) +{ + CyPmHibernateEx(CY_PM_HIB_SRC_PICU); +} + + +/******************************************************************************* +* Function Name: CyPmHibernateEx +****************************************************************************//** +* +* Puts the part into the Hibernate state. +* +* The following wake up sources can be configured: PICU interrupt, Comparator0, +* Comparator1, Comparator2, and Comparator3 output. +* +* Before switching to Hibernate, the current status of the PICU wakeup source +* bit is saved and then set. +* +* If using PICU as the wake up source, make sure you have at least one pin +* configured to generate a PICU interrupt. For pin Px.y, the register +* "PICU_INTTYPE_PICUx_INTTYPEy" controls the PICU behavior. In the TRM, this +* register is "PICU[0..15]_INTTYPE[0..7]." In the Pins component datasheet, +* this register is referred to as the IRQ option. Once the wakeup occurs, the +* PICU wakeup source bit is restored and the PSoC returns to the Active state. +* +* If using a comparator as the wake up source, make sure you call this function +* with the 'wakeupSource' parameter set to the appropriate comparator. The part +* is configured for the requested wakeup source by setting the corresponding +* bits in PM_WAKEUP_CFG1 register. +* +* Function call CyPmHibernateEx(CY_PM_HIB_SRC_PICU) will act in the same way as +* CyPmHibernate(). +* +* \param wakeupSource: +* Parameter Value Description +* CY_PM_HIB_SRC_PICU PICU interrupt is set as the wake up source. +* CY_PM_HIB_SRC_COMPARATOR0 Comparator 0 is set as the wake up source. +* CY_PM_HIB_SRC_COMPARATOR1 Comparator 1 is set as the wake up source. +* CY_PM_HIB_SRC_COMPARATOR2 Comparator 2 is set as the wake up source. +* CY_PM_HIB_SRC_COMPARATOR3 Comparator 3 is set as the wake up source. +* +* Reentrant: +* No +* +* \sideeffect +* Applications must wait 20 us before re-entering hibernate or sleep after +* waking up from hibernate. The 20 us allows the sleep regulator time to +* stabilize before the next hibernate / sleep event occurs. The 20 us +* requirement begins when the device wakes up. There is no hardware check that +* this requirement is met. The specified delay should be done on ISR entry. +* +* After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin +* is instance name of the Pins component) function must be called to clear the +* latched pin events to allow the proper Hibernate mode entry and to enable +* detection of future events. +* +* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to +* measure Hibernate/Sleep regulator settling time after a reset. The holdoff +* delay is measured using the rising edges of the 1 kHz ILO. +* +*******************************************************************************/ +void CyPmHibernateEx(uint16 wakeupSource) +{ + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + /*********************************************************************** + * The Hibernate/Sleep regulator has a settling time after a reset. + * During this time, the system ignores requests to enter the Sleep and + * Hibernate modes. The holdoff delay is measured using the rising edges of + * the 1 kHz ILO. + ***********************************************************************/ + if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) + { + /* Disable hold off - no action on restore */ + CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; + } + else + { + /* Abort, device is not ready for low power mode entry */ + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); + + return; + } + + CyPmHibSaveSet(); + + + /* Save and set new wake up configuration */ + + /* Save and enable only wakeup on PICU */ + cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; + CY_PM_WAKEUP_CFG0_REG = ((uint8) (wakeupSource >> 4u) & CY_PM_WAKEUP_PICU); + + /* Comparators */ + cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; + CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); + + cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; + CY_PM_WAKEUP_CFG2_REG = 0x00u; + + + /* Last moment IMO frequency change */ + if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) + { + /* IMO frequency is 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED; + } + else + { + /* IMO frequency is not 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; + + /* Save IMO frequency */ + cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; + + /* Set IMO frequency to 12 MHz */ + CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); + } + + + /* Switch to Hibernate Mode */ + CY_PM_MODE_CSR_REG = (CY_PM_MODE_CSR_REG & ((uint8) (~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_HIBERNATE; + + /* Recommended readback. */ + (void) CY_PM_MODE_CSR_REG; + + /* Two recommended NOPs to get into mode. */ + CY_NOP; + CY_NOP; + + /* Execute WFI instruction (for ARM-based devices only) */ + CY_PM_WFI; + + + /* Point of return from Hibernate mode */ + + + /* Restore last moment IMO frequency change */ + if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz) + { + CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ_MASK))) | + cyPmBackup.imoActFreq; + } + + + /* Restore device for proper Hibernate mode exit*/ + CyPmHibRestore(); + + /* Restore current wake up configuration */ + CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; + CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; + CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyPmReadStatus +****************************************************************************//** +* +* Manages the Power Manager Interrupt Status Register. This register has the +* interrupt status for the one pulse per second, central timewheel and fast +* timewheel timers. This hardware register clears on read. To allow for only +* clearing the bits of interest and preserving the other bits, this function +* uses a shadow register that retains the state. This function reads the +* status register and ORs that value with the shadow register. That is the +* value that is returned. Then the bits in the mask that are set are cleared +* from this value and written back to the shadow register. +* +* Note You must call this function within 1 ms (1 clock cycle of the ILO) +* after a CTW event has occurred. +* +* \param mask: Bits in the shadow register to clear. +* +* Define Source +* CY_PM_FTW_INT Fast Timewheel +* CY_PM_CTW_INT Central Timewheel +* CY_PM_ONEPPS_INT One Pulse Per Second +* +* \return +* Status. Same bits values as the mask parameter. +* +*******************************************************************************/ +uint8 CyPmReadStatus(uint8 mask) +{ + static uint8 interruptStatus; + uint8 interruptState; + uint8 tmpStatus; + + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + /* Save value of register, copy it and clear desired bit */ + interruptStatus |= CY_PM_INT_SR_REG; + tmpStatus = interruptStatus & (CY_PM_FTW_INT | CY_PM_CTW_INT | CY_PM_ONEPPS_INT); + interruptStatus &= ((uint8)(~mask)); + + /* Exit critical section */ + CyExitCriticalSection(interruptState); + + return(tmpStatus); +} + + +/******************************************************************************* +* Function Name: CyPmHibSaveSet +****************************************************************************//** +* +* Prepare device for proper Hibernate low power mode entry: +* - Disables I2C backup regulator +* - Saves ILO power down mode state and enable it +* - Saves state of 1 kHz and 100 kHz ILO and disable them +* - Disables sleep regulator and shorts vccd to vpwrsleep +* - Save LVI/HVI configuration and disable them - CyPmHviLviSaveDisable() +* - CyPmHibSlpSaveSet() function is called +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHibSaveSet(void) +{ + /* I2C backup reg must be off when the sleep regulator is unavailable */ + if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP)) + { + /*********************************************************************** + * If the I2C backup regulator is enabled, all the fixed-function registers + * store their values while the device is in the low power mode, otherwise their + * configuration is lost. The I2C API makes a decision to restore or not + * to restore I2C registers based on this. If this regulator will be + * disabled and then enabled, I2C API will suppose that the I2C block + * registers preserved their values, while this is not true. So, the + * backup regulator is disabled. The I2C sleep APIs is responsible for + * restoration. + ***********************************************************************/ + + /* Disable I2C backup register */ + CY_PM_PWRSYS_CR1_REG &= ((uint8)(~CY_PM_PWRSYS_CR1_I2CREG_BACKUP)); + } + + + /* Save current ILO power mode and ensure low power mode */ + cyPmBackup.iloPowerMode = CyILO_SetPowerMode(CY_PM_POWERDOWN_MODE); + + /* Save current 1kHz ILO enable state. Disabled automatically. */ + cyPmBackup.ilo1kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_1K)) ? + CY_PM_DISABLED : CY_PM_ENABLED; + + /* Save current 100kHz ILO enable state. Disabled automatically. */ + cyPmBackup.ilo100kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_100K)) ? + CY_PM_DISABLED : CY_PM_ENABLED; + + + /* Disable the sleep regulator and shorts vccd to vpwrsleep */ + if(0u == (CY_PM_PWRSYS_SLP_TR_REG & CY_PM_PWRSYS_SLP_TR_BYPASS)) + { + /* Save current bypass state */ + cyPmBackup.slpTrBypass = CY_PM_DISABLED; + CY_PM_PWRSYS_SLP_TR_REG |= CY_PM_PWRSYS_SLP_TR_BYPASS; + } + else + { + cyPmBackup.slpTrBypass = CY_PM_ENABLED; + } + + /* LPCOMPs are always enabled (even when BOTH ext_vccd=1 and ext_vcca=1)*/ + + + /*************************************************************************** + * LVI/HVI must be disabled in Hibernate + ***************************************************************************/ + + /* Save LVI/HVI configuration and disable them */ + CyPmHviLviSaveDisable(); + + + /* Make the same preparations for Hibernate and Sleep modes */ + CyPmHibSlpSaveSet(); + + + /*************************************************************************** + * Save and set the power mode wakeup trim registers + ***************************************************************************/ + cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG; + cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG; + + #if(CY_PSOC5) + cyPmBackup.wakeupTrim3 = CY_PM_PWRSYS_WAKE_TR3_REG; + #endif /* (CY_PSOC5) */ + + CY_PM_PWRSYS_WAKE_TR0_REG = CY_PM_PWRSYS_WAKE_TR0; + CY_PM_PWRSYS_WAKE_TR1_REG = CY_PM_PWRSYS_WAKE_TR1; + + #if(CY_PSOC5) + CY_PM_PWRSYS_WAKE_TR3_REG = CY_PM_PWRSYS_WAKE_TR3; + #endif /* (CY_PSOC5) */ +} + + +/******************************************************************************* +* Function Name: CyPmHibRestore +****************************************************************************//** +* +* Restores the device for the proper Hibernate mode exit: +* - Restores LVI/HVI configuration - calsl CyPmHviLviRestore() +* - CyPmHibSlpSaveRestore() function is called +* - Restores ILO power down mode state and enables it +* - Restores the state of 1 kHz and 100 kHz ILO and disables them +* - Restores the sleep regulator settings +* +*******************************************************************************/ +static void CyPmHibRestore(void) +{ + /* Restore LVI/HVI configuration */ + CyPmHviLviRestore(); + + /* Restore the same configuration for Hibernate and Sleep modes */ + CyPmHibSlpRestore(); + + /* Restore 1kHz ILO enable state */ + if(CY_PM_ENABLED == cyPmBackup.ilo1kEnable) + { + /* Enable 1kHz ILO */ + CyILO_Start1K(); + } + + /* Restore 100kHz ILO enable state */ + if(CY_PM_ENABLED == cyPmBackup.ilo100kEnable) + { + /* Enable 100kHz ILO */ + CyILO_Start100K(); + } + + /* Restore ILO power mode */ + (void) CyILO_SetPowerMode(cyPmBackup.iloPowerMode); + + + if(CY_PM_DISABLED == cyPmBackup.slpTrBypass) + { + /* Enable the sleep regulator */ + CY_PM_PWRSYS_SLP_TR_REG &= ((uint8)(~CY_PM_PWRSYS_SLP_TR_BYPASS)); + } + + + /*************************************************************************** + * Restore the power mode wakeup trim registers + ***************************************************************************/ + CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0; + CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1; + + #if(CY_PSOC5) + CY_PM_PWRSYS_WAKE_TR3_REG = cyPmBackup.wakeupTrim3; + #endif /* (CY_PSOC5) */ +} + + +/******************************************************************************* +* Function Name: CyPmCtwSetInterval +****************************************************************************//** +* +* Performs the CTW configuration: +* - Disables the CTW interrupt +* - Enables 1 kHz ILO +* - Sets a new CTW interval +* +* \param ctwInterval: the CTW interval to be set. +* +* \sideeffect +* Enables ILO 1 KHz clock and leaves it enabled. +* +*******************************************************************************/ +void CyPmCtwSetInterval(uint8 ctwInterval) +{ + /* Disable CTW interrupt enable */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_IE)); + + /* Enable 1kHz ILO (required for CTW operation) */ + CyILO_Start1K(); + + /* Interval could be set only while CTW is disabled */ + if(0u != (CY_PM_TW_CFG2_REG & CY_PM_CTW_EN)) + { + /* Set CTW interval if needed */ + if(CY_PM_TW_CFG1_REG != ctwInterval) + { + /* Disable the CTW, set new CTW interval and enable it again */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_EN)); + CY_PM_TW_CFG1_REG = ctwInterval; + CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; + } /* Required interval is already set */ + } + else + { + /* Set CTW interval if needed */ + if(CY_PM_TW_CFG1_REG != ctwInterval) + { + /* Set new CTW interval. Could be changed if CTW is disabled */ + CY_PM_TW_CFG1_REG = ctwInterval; + } /* Required interval is already set */ + + /* Enable CTW */ + CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; + } +} + + +/******************************************************************************* +* Function Name: CyPmOppsSet +****************************************************************************//** +* +* Performs 1PPS configuration: +* - Starts 32 KHz XTAL +* - Disables 1PPS interrupts +* - Enables 1PPS +* +*******************************************************************************/ +void CyPmOppsSet(void) +{ + /* Enable 32kHz XTAL if needed */ + if(0u == (CY_PM_SLOWCLK_X32_CR_REG & CY_PM_X32_CR_X32EN)) + { + /* Enable 32kHz XTAL */ + CyXTAL_32KHZ_Start(); + } + + /* Disable 1PPS interrupt enable */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_1PPS_IE)); + + /* Enable 1PPS operation */ + CY_PM_TW_CFG2_REG |= CY_PM_1PPS_EN; +} + + +/******************************************************************************* +* Function Name: CyPmFtwSetInterval +****************************************************************************//** +* +* Performs the FTW configuration: +* - Disables the FTW interrupt +* - Enables 100 kHz ILO +* - Sets a new FTW interval. +* +* \param ftwInterval The FTW counter interval. +* +* \sideeffect +* Enables the ILO 100 KHz clock and leaves it enabled. +* +*******************************************************************************/ +void CyPmFtwSetInterval(uint8 ftwInterval) +{ + /* Disable FTW interrupt enable */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_IE)); + + /* Enable 100kHz ILO */ + CyILO_Start100K(); + + /* Interval could be set only while FTW is disabled */ + if(0u != (CY_PM_TW_CFG2_REG & CY_PM_FTW_EN)) + { + /* Disable FTW, set new FTW interval if needed and enable it again */ + if(CY_PM_TW_CFG0_REG != ftwInterval) + { + /* Disable CTW, set new CTW interval and enable it again */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_EN)); + CY_PM_TW_CFG0_REG = ftwInterval; + CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN; + } /* Required interval is already set */ + } + else + { + /* Set new FTW counter interval if needed. FTW is disabled. */ + if(CY_PM_TW_CFG0_REG != ftwInterval) + { + /* Set new CTW interval. Could be changed if CTW is disabled */ + CY_PM_TW_CFG0_REG = ftwInterval; + } /* Required interval is already set */ + + /* Enable FTW */ + CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN; + } +} + + +/******************************************************************************* +* Function Name: CyPmHibSlpSaveSet +****************************************************************************//** +* +* This API is used for preparing the device for the Sleep and Hibernate low +* power modes entry: +* - Saves the COMP, VIDAC, DSM, and SAR routing connections (PSoC 5) +* - Saves the SC/CT routing connections (PSoC 3/5/5LP) +* - Disables the Serial Wire Viewer (SWV) (PSoC 3) +* - Saves the boost reference selection and sets it to internal +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHibSlpSaveSet(void) +{ + /* Save SC/CT routing registers */ + cyPmBackup.scctData[0u] = CY_GET_REG8(CYREG_SC0_SW0 ); + cyPmBackup.scctData[1u] = CY_GET_REG8(CYREG_SC0_SW2 ); + cyPmBackup.scctData[2u] = CY_GET_REG8(CYREG_SC0_SW3 ); + cyPmBackup.scctData[3u] = CY_GET_REG8(CYREG_SC0_SW4 ); + cyPmBackup.scctData[4u] = CY_GET_REG8(CYREG_SC0_SW6 ); + cyPmBackup.scctData[5u] = CY_GET_REG8(CYREG_SC0_SW8 ); + cyPmBackup.scctData[6u] = CY_GET_REG8(CYREG_SC0_SW10); + + cyPmBackup.scctData[7u] = CY_GET_REG8(CYREG_SC1_SW0 ); + cyPmBackup.scctData[8u] = CY_GET_REG8(CYREG_SC1_SW2 ); + cyPmBackup.scctData[9u] = CY_GET_REG8(CYREG_SC1_SW3 ); + cyPmBackup.scctData[10u] = CY_GET_REG8(CYREG_SC1_SW4 ); + cyPmBackup.scctData[11u] = CY_GET_REG8(CYREG_SC1_SW6 ); + cyPmBackup.scctData[12u] = CY_GET_REG8(CYREG_SC1_SW8 ); + cyPmBackup.scctData[13u] = CY_GET_REG8(CYREG_SC1_SW10); + + cyPmBackup.scctData[14u] = CY_GET_REG8(CYREG_SC2_SW0 ); + cyPmBackup.scctData[15u] = CY_GET_REG8(CYREG_SC2_SW2 ); + cyPmBackup.scctData[16u] = CY_GET_REG8(CYREG_SC2_SW3 ); + cyPmBackup.scctData[17u] = CY_GET_REG8(CYREG_SC2_SW4 ); + cyPmBackup.scctData[18u] = CY_GET_REG8(CYREG_SC2_SW6 ); + cyPmBackup.scctData[19u] = CY_GET_REG8(CYREG_SC2_SW8 ); + cyPmBackup.scctData[20u] = CY_GET_REG8(CYREG_SC2_SW10); + + cyPmBackup.scctData[21u] = CY_GET_REG8(CYREG_SC3_SW0 ); + cyPmBackup.scctData[22u] = CY_GET_REG8(CYREG_SC3_SW2 ); + cyPmBackup.scctData[23u] = CY_GET_REG8(CYREG_SC3_SW3 ); + cyPmBackup.scctData[24u] = CY_GET_REG8(CYREG_SC3_SW4 ); + cyPmBackup.scctData[25u] = CY_GET_REG8(CYREG_SC3_SW6 ); + cyPmBackup.scctData[26u] = CY_GET_REG8(CYREG_SC3_SW8 ); + cyPmBackup.scctData[27u] = CY_GET_REG8(CYREG_SC3_SW10); + + CY_SET_REG8(CYREG_SC0_SW0 , 0u); + CY_SET_REG8(CYREG_SC0_SW2 , 0u); + CY_SET_REG8(CYREG_SC0_SW3 , 0u); + CY_SET_REG8(CYREG_SC0_SW4 , 0u); + CY_SET_REG8(CYREG_SC0_SW6 , 0u); + CY_SET_REG8(CYREG_SC0_SW8 , 0u); + CY_SET_REG8(CYREG_SC0_SW10, 0u); + + CY_SET_REG8(CYREG_SC1_SW0 , 0u); + CY_SET_REG8(CYREG_SC1_SW2 , 0u); + CY_SET_REG8(CYREG_SC1_SW3 , 0u); + CY_SET_REG8(CYREG_SC1_SW4 , 0u); + CY_SET_REG8(CYREG_SC1_SW6 , 0u); + CY_SET_REG8(CYREG_SC1_SW8 , 0u); + CY_SET_REG8(CYREG_SC1_SW10, 0u); + + CY_SET_REG8(CYREG_SC2_SW0 , 0u); + CY_SET_REG8(CYREG_SC2_SW2 , 0u); + CY_SET_REG8(CYREG_SC2_SW3 , 0u); + CY_SET_REG8(CYREG_SC2_SW4 , 0u); + CY_SET_REG8(CYREG_SC2_SW6 , 0u); + CY_SET_REG8(CYREG_SC2_SW8 , 0u); + CY_SET_REG8(CYREG_SC2_SW10, 0u); + + CY_SET_REG8(CYREG_SC3_SW0 , 0u); + CY_SET_REG8(CYREG_SC3_SW2 , 0u); + CY_SET_REG8(CYREG_SC3_SW3 , 0u); + CY_SET_REG8(CYREG_SC3_SW4 , 0u); + CY_SET_REG8(CYREG_SC3_SW6 , 0u); + CY_SET_REG8(CYREG_SC3_SW8 , 0u); + CY_SET_REG8(CYREG_SC3_SW10, 0u); + + + #if(CY_PSOC3) + + /* Serial Wire Viewer (SWV) workaround */ + + /* Disable SWV before entering low power mode */ + if(0u != (CY_PM_MLOGIC_DBG_REG & CY_PM_MLOGIC_DBG_SWV_CLK_EN)) + { + /* Save SWV clock enabled state */ + cyPmBackup.swvClkEnabled = CY_PM_ENABLED; + + /* Save current ports drive mode settings */ + cyPmBackup.prt1Dm = CY_PM_PRT1_PC3_REG & ((uint8)(~CY_PM_PRT1_PC3_DM_MASK)); + + /* Set drive mode to strong output */ + CY_PM_PRT1_PC3_REG = (CY_PM_PRT1_PC3_REG & CY_PM_PRT1_PC3_DM_MASK) | + CY_PM_PRT1_PC3_DM_STRONG; + + /* Disable SWV clocks */ + CY_PM_MLOGIC_DBG_REG &= ((uint8)(~CY_PM_MLOGIC_DBG_SWV_CLK_EN)); + } + else + { + /* Save SWV clock disabled state */ + cyPmBackup.swvClkEnabled = CY_PM_DISABLED; + } + + #endif /* (CY_PSOC3) */ + + + /*************************************************************************** + * Save boost reference and set it to boost's internal by clearing the bit. + * External (chip bandgap) reference is not available in Sleep and Hibernate. + ***************************************************************************/ + if(0u != (CY_PM_BOOST_CR2_REG & CY_PM_BOOST_CR2_EREFSEL_EXT)) + { + cyPmBackup.boostRefExt = CY_PM_ENABLED; + CY_PM_BOOST_CR2_REG &= ((uint8)(~CY_PM_BOOST_CR2_EREFSEL_EXT)); + } + else + { + cyPmBackup.boostRefExt = CY_PM_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: CyPmHibSlpRestore +****************************************************************************//** +* +* This API is used for restoring the device configurations after wakeup from +* the Sleep and Hibernate low power modes: +* - Restores the SC/CT routing connections +* - Restores the enable state of the Serial Wire Viewer (SWV) (PSoC 3) +* - Restores the boost reference selection +* +*******************************************************************************/ +static void CyPmHibSlpRestore(void) +{ + /* Restore SC/CT routing registers */ + CY_SET_REG8(CYREG_SC0_SW0 , cyPmBackup.scctData[0u] ); + CY_SET_REG8(CYREG_SC0_SW2 , cyPmBackup.scctData[1u] ); + CY_SET_REG8(CYREG_SC0_SW3 , cyPmBackup.scctData[2u] ); + CY_SET_REG8(CYREG_SC0_SW4 , cyPmBackup.scctData[3u] ); + CY_SET_REG8(CYREG_SC0_SW6 , cyPmBackup.scctData[4u] ); + CY_SET_REG8(CYREG_SC0_SW8 , cyPmBackup.scctData[5u] ); + CY_SET_REG8(CYREG_SC0_SW10, cyPmBackup.scctData[6u] ); + + CY_SET_REG8(CYREG_SC1_SW0 , cyPmBackup.scctData[7u] ); + CY_SET_REG8(CYREG_SC1_SW2 , cyPmBackup.scctData[8u] ); + CY_SET_REG8(CYREG_SC1_SW3 , cyPmBackup.scctData[9u] ); + CY_SET_REG8(CYREG_SC1_SW4 , cyPmBackup.scctData[10u]); + CY_SET_REG8(CYREG_SC1_SW6 , cyPmBackup.scctData[11u]); + CY_SET_REG8(CYREG_SC1_SW8 , cyPmBackup.scctData[12u]); + CY_SET_REG8(CYREG_SC1_SW10, cyPmBackup.scctData[13u]); + + CY_SET_REG8(CYREG_SC2_SW0 , cyPmBackup.scctData[14u]); + CY_SET_REG8(CYREG_SC2_SW2 , cyPmBackup.scctData[15u]); + CY_SET_REG8(CYREG_SC2_SW3 , cyPmBackup.scctData[16u]); + CY_SET_REG8(CYREG_SC2_SW4 , cyPmBackup.scctData[17u]); + CY_SET_REG8(CYREG_SC2_SW6 , cyPmBackup.scctData[18u]); + CY_SET_REG8(CYREG_SC2_SW8 , cyPmBackup.scctData[19u]); + CY_SET_REG8(CYREG_SC2_SW10, cyPmBackup.scctData[20u]); + + CY_SET_REG8(CYREG_SC3_SW0 , cyPmBackup.scctData[21u]); + CY_SET_REG8(CYREG_SC3_SW2 , cyPmBackup.scctData[22u]); + CY_SET_REG8(CYREG_SC3_SW3 , cyPmBackup.scctData[23u]); + CY_SET_REG8(CYREG_SC3_SW4 , cyPmBackup.scctData[24u]); + CY_SET_REG8(CYREG_SC3_SW6 , cyPmBackup.scctData[25u]); + CY_SET_REG8(CYREG_SC3_SW8 , cyPmBackup.scctData[26u]); + CY_SET_REG8(CYREG_SC3_SW10, cyPmBackup.scctData[27u]); + + + #if(CY_PSOC3) + + /* Serial Wire Viewer (SWV) workaround */ + if(CY_PM_ENABLED == cyPmBackup.swvClkEnabled) + { + /* Restore ports drive mode */ + CY_PM_PRT1_PC3_REG = (CY_PM_PRT1_PC3_REG & CY_PM_PRT1_PC3_DM_MASK) | + cyPmBackup.prt1Dm; + + /* Enable SWV clocks */ + CY_PM_MLOGIC_DBG_REG |= CY_PM_MLOGIC_DBG_SWV_CLK_EN; + } + + #endif /* (CY_PSOC3) */ + + + /* Restore boost reference */ + if(CY_PM_ENABLED == cyPmBackup.boostRefExt) + { + CY_PM_BOOST_CR2_REG |= CY_PM_BOOST_CR2_EREFSEL_EXT; + } +} + + +/******************************************************************************* +* Function Name: CyPmHviLviSaveDisable +****************************************************************************//** +* +* Saves analog and digital LVI and HVI configuration and disables them. +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHviLviSaveDisable(void) +{ + if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_LVID_EN)) + { + cyPmBackup.lvidEn = CY_PM_ENABLED; + cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK; + + /* Save state of reset device at specified Vddd threshold */ + cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \ + CY_PM_DISABLED : CY_PM_ENABLED; + + CyVdLvDigitDisable(); + } + else + { + cyPmBackup.lvidEn = CY_PM_DISABLED; + } + + if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_LVIA_EN)) + { + cyPmBackup.lviaEn = CY_PM_ENABLED; + cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u; + + /* Save state of reset device at specified Vdda threshold */ + cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \ + CY_PM_DISABLED : CY_PM_ENABLED; + + CyVdLvAnalogDisable(); + } + else + { + cyPmBackup.lviaEn = CY_PM_DISABLED; + } + + if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_HVIA_EN)) + { + cyPmBackup.hviaEn = CY_PM_ENABLED; + CyVdHvAnalogDisable(); + } + else + { + cyPmBackup.hviaEn = CY_PM_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: CyPmHviLviRestore +****************************************************************************//** +* +* Restores the analog and digital LVI and HVI configuration. +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHviLviRestore(void) +{ + /* Restore LVI/HVI configuration */ + if(CY_PM_ENABLED == cyPmBackup.lvidEn) + { + CyVdLvDigitEnable(cyPmBackup.lvidRst, cyPmBackup.lvidTrip); + } + + if(CY_PM_ENABLED == cyPmBackup.lviaEn) + { + CyVdLvAnalogEnable(cyPmBackup.lviaRst, cyPmBackup.lviaTrip); + } + + if(CY_PM_ENABLED == cyPmBackup.hviaEn) + { + CyVdHvAnalogEnable(); + } +} + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/cyPm.h b/source/hic_hal/cypress/psoc5lp/PSoC5/cyPm.h new file mode 100644 index 0000000000..f1a575529e --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/cyPm.h @@ -0,0 +1,701 @@ +/***************************************************************************//** +* \file cyPm.h +* \version 5.70 +* +* \brief Provides the function definitions for the power management API. +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_BOOT_CYPM_H) +#define CY_BOOT_CYPM_H + +#include "cytypes.h" /* Register access API */ +#include "cydevice_trm.h" /* Registers addresses */ +#include "cyfitter.h" /* Comparators placement */ +#include "CyLib.h" /* Clock API */ +#include "CyFlash.h" /* Flash API - CyFlash_SetWaitCycles() */ + + +/*************************************** +* Function Prototypes +***************************************/ +void CyPmSaveClocks(void) ; +void CyPmRestoreClocks(void) ; +void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) ; +void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) ; +void CyPmHibernate(void) ; +void CyPmHibernateEx(uint16 wakeupSource) ; + +uint8 CyPmReadStatus(uint8 mask) ; + +/* Internal APIs and are not meant to be called directly by the user */ +void CyPmCtwSetInterval(uint8 ctwInterval) ; +void CyPmFtwSetInterval(uint8 ftwInterval) ; +void CyPmOppsSet(void) ; + + +/*************************************** +* API Constants +***************************************/ + +#define PM_SLEEP_SRC_NONE (0x0000u) +#define PM_SLEEP_TIME_NONE (0x00u) +#define PM_ALT_ACT_SRC_NONE (0x0000u) +#define PM_ALT_ACT_TIME_NONE (0x0000u) + +#if(CY_PSOC3) + + /* Wake up time for Sleep mode */ + #define PM_SLEEP_TIME_ONE_PPS (0x01u) + #define PM_SLEEP_TIME_CTW_2MS (0x02u) + #define PM_SLEEP_TIME_CTW_4MS (0x03u) + #define PM_SLEEP_TIME_CTW_8MS (0x04u) + #define PM_SLEEP_TIME_CTW_16MS (0x05u) + #define PM_SLEEP_TIME_CTW_32MS (0x06u) + #define PM_SLEEP_TIME_CTW_64MS (0x07u) + #define PM_SLEEP_TIME_CTW_128MS (0x08u) + #define PM_SLEEP_TIME_CTW_256MS (0x09u) + #define PM_SLEEP_TIME_CTW_512MS (0x0Au) + #define PM_SLEEP_TIME_CTW_1024MS (0x0Bu) + #define PM_SLEEP_TIME_CTW_2048MS (0x0Cu) + #define PM_SLEEP_TIME_CTW_4096MS (0x0Du) + + /* Difference between parameter's value and register's one */ + #define CY_PM_FTW_INTERVAL_SHIFT (0x000Eu) + + /* Wake up time for Alternate Active mode */ + #define PM_ALT_ACT_TIME_ONE_PPS (0x0001u) + #define PM_ALT_ACT_TIME_CTW_2MS (0x0002u) + #define PM_ALT_ACT_TIME_CTW_4MS (0x0003u) + #define PM_ALT_ACT_TIME_CTW_8MS (0x0004u) + #define PM_ALT_ACT_TIME_CTW_16MS (0x0005u) + #define PM_ALT_ACT_TIME_CTW_32MS (0x0006u) + #define PM_ALT_ACT_TIME_CTW_64MS (0x0007u) + #define PM_ALT_ACT_TIME_CTW_128MS (0x0008u) + #define PM_ALT_ACT_TIME_CTW_256MS (0x0009u) + #define PM_ALT_ACT_TIME_CTW_512MS (0x000Au) + #define PM_ALT_ACT_TIME_CTW_1024MS (0x000Bu) + #define PM_ALT_ACT_TIME_CTW_2048MS (0x000Cu) + #define PM_ALT_ACT_TIME_CTW_4096MS (0x000Du) + #define PM_ALT_ACT_TIME_FTW(x) ((x) + CY_PM_FTW_INTERVAL_SHIFT) + +#endif /* (CY_PSOC3) */ + + +/* Wake up sources for Sleep mode */ +#define PM_SLEEP_SRC_COMPARATOR0 (0x0001u) +#define PM_SLEEP_SRC_COMPARATOR1 (0x0002u) +#define PM_SLEEP_SRC_COMPARATOR2 (0x0004u) +#define PM_SLEEP_SRC_COMPARATOR3 (0x0008u) +#define PM_SLEEP_SRC_PICU (0x0040u) +#define PM_SLEEP_SRC_I2C (0x0080u) +#define PM_SLEEP_SRC_BOOSTCONVERTER (0x0200u) +#define PM_SLEEP_SRC_VD (0x0400u) +#define PM_SLEEP_SRC_CTW (0x0800u) +#define PM_SLEEP_SRC_ONE_PPS (0x0800u) +#define PM_SLEEP_SRC_LCD (0x1000u) + +/* Wake up sources for Hibernate mode */ +#define CY_PM_HIB_SRC_PICU (0x0040u) +#define CY_PM_HIB_SRC_COMPARATOR0 (0x0001u) +#define CY_PM_HIB_SRC_COMPARATOR1 (0x0002u) +#define CY_PM_HIB_SRC_COMPARATOR2 (0x0004u) +#define CY_PM_HIB_SRC_COMPARATOR3 (0x0008u) + +/* Wake up sources for Alternate Active mode */ +#define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u) +#define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u) +#define PM_ALT_ACT_SRC_COMPARATOR2 (0x0004u) +#define PM_ALT_ACT_SRC_COMPARATOR3 (0x0008u) +#define PM_ALT_ACT_SRC_INTERRUPT (0x0010u) +#define PM_ALT_ACT_SRC_PICU (0x0040u) +#define PM_ALT_ACT_SRC_I2C (0x0080u) +#define PM_ALT_ACT_SRC_BOOSTCONVERTER (0x0200u) +#define PM_ALT_ACT_SRC_FTW (0x0400u) +#define PM_ALT_ACT_SRC_VD (0x0400u) +#define PM_ALT_ACT_SRC_CTW (0x0800u) +#define PM_ALT_ACT_SRC_ONE_PPS (0x0800u) +#define PM_ALT_ACT_SRC_LCD (0x1000u) + + +#define CY_PM_WAKEUP_PICU (0x04u) +#define CY_PM_IMO_NO_WAIT_TO_SETTLE (0x00u) +#define CY_PM_POWERDOWN_MODE (0x01u) +#define CY_PM_HIGHPOWER_MODE (0x00u) /* Deprecated */ +#define CY_PM_ENABLED (0x01u) +#define CY_PM_DISABLED (0x00u) + +/* No wait for PLL to stabilize, used in CyPLL_OUT_Start() */ +#define CY_PM_PLL_OUT_NO_WAIT (0u) + +/* No wait for MHZ XTAL to stabilize, used in CyXTAL_Start() */ +#define CY_PM_XTAL_MHZ_NO_WAIT (0u) + +#define CY_PM_WAIT_200_US (200u) +#define CY_PM_WAIT_250_US (250u) +#define CY_PM_WAIT_20_US (20u) + +#define CY_PM_FREQ_3MHZ (3u) +#define CY_PM_FREQ_12MHZ (12u) +#define CY_PM_FREQ_48MHZ (48u) + + +#define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (5u) + + +/* Delay line bandgap current settling time starting from wakeup event */ +#define CY_PM_CLK_DELAY_BANDGAP_SETTLE_US (50u) + +/* Delay line internal bias settling */ +#define CY_PM_CLK_DELAY_BIAS_SETTLE_US (25u) + + +/* Max flash wait cycles for each device */ +#if(CY_PSOC3) + #define CY_PM_MAX_FLASH_WAIT_CYCLES (45u) +#endif /* (CY_PSOC3) */ + +#if(CY_PSOC5) + #define CY_PM_MAX_FLASH_WAIT_CYCLES (55u) +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* This marco is used to obtain the CPU frequency in MHz. It should be only used +* when the clock distribution system is prepared for the low power mode entry. +* This macro is silicon dependent as PSoC 5 devices have no CPU clock divider +* and PSoC 3 devices have different placement of the CPU clock divider register +* bitfield. +*******************************************************************************/ +#if(CY_PSOC3) + #define CY_PM_GET_CPU_FREQ_MHZ \ + ((uint32)(cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) / \ + ((uint8)(((CY_PM_CLKDIST_MSTR1_REG & CY_PM_CLKDIST_CPU_DIV_MASK) >> 4u) + 1u))) +#endif /* (CY_PSOC3) */ + +#if(CY_PSOC5) + + /* CPU clock is directly derived from bus clock */ + #define CY_PM_GET_CPU_FREQ_MHZ (cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* The low power mode entry is different for PSoC 3 and PSoC 5 devices. The low +* power modes in PSoC 5 devices are invoked by Wait-For-Interrupt (WFI) +* instruction. The ARM compilers has __wfi() intrinsic that inserts a WFI +* instruction into the instruction stream generated by the compiler. The GCC +* compiler has to execute assembly language instruction. +*******************************************************************************/ +#if(CY_PSOC5) + + #if defined(__ARMCC_VERSION) /* Instristic for Keil compilers */ + #define CY_PM_WFI __wfi() + #else /* ASM for GCC & IAR */ + #define CY_PM_WFI __asm volatile ("WFI \n") + #endif /* (__ARMCC_VERSION) */ + +#else + + #define CY_PM_WFI CY_NOP + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Macro for the wakeupTime argument of the CyPmAltAct() function. The FTW should +* be programmed manually for non PSoC 3 devices. +*******************************************************************************/ +#if(CY_PSOC3) + + #define PM_ALT_ACT_FTW_INTERVAL(x) ((uint8)((x) - CY_PM_FTW_INTERVAL_SHIFT)) + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* This macro defines the IMO frequency that will be set by CyPmSaveClocks() +* function based on Enable Fast IMO during Startup option from the DWR file. +* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering the +* low power mode and restore IMO back to the value set by CyPmSaveClocks() +* immediately on wakeup. +*******************************************************************************/ + +/* Enable Fast IMO during Startup - enabled */ +#if(1u == CYDEV_CONFIGURATION_IMOENABLED) + + /* IMO will be configured to 48 MHz */ + #define CY_PM_IMO_FREQ_LPM (CY_IMO_FREQ_48MHZ) + +#else + + /* IMO will be configured to 12 MHz */ + #define CY_PM_IMO_FREQ_LPM (CY_IMO_FREQ_12MHZ) + +#endif /* (1u == CYDEV_CONFIGURATION_IMOENABLED) */ + + +typedef struct cyPmClockBackupStruct +{ + /* CyPmSaveClocks()/CyPmRestoreClocks() */ + uint8 enClkA; /* Analog clocks enable */ + uint8 enClkD; /* Digital clocks enable */ + uint8 masterClkSrc; /* Master clock source */ + uint8 imoFreq; /* IMO frequency (reg's value) */ + uint8 imoUsbClk; /* IMO USB CLK (reg's value) */ + uint8 flashWaitCycles; /* Flash wait cycles */ + uint8 imoEnable; /* IMO enable in Active mode */ + uint8 imoClkSrc; /* The IMO output */ + uint8 clkImoSrc; + uint8 imo2x; /* IMO doubler enable state */ + uint8 clkSyncDiv; /* Master clk divider */ + uint16 clkBusDiv; /* clk_bus divider */ + uint8 pllEnableState; /* PLL enable state */ + uint8 xmhzEnableState; /* XM HZ enable state */ + uint8 clkDistDelay; /* Delay for clk_bus and ACLKs */ + +} CY_PM_CLOCK_BACKUP_STRUCT; + + +typedef struct cyPmBackupStruct +{ + uint8 iloPowerMode; /* ILO power mode */ + uint8 ilo1kEnable; /* ILO 1K enable state */ + uint8 ilo100kEnable; /* ILO 100K enable state */ + + uint8 slpTrBypass; /* Sleep Trim Bypass */ + + #if(CY_PSOC3) + + uint8 swvClkEnabled; /* SWV clock enable state */ + uint8 prt1Dm; /* Ports drive mode configuration */ + uint8 hardwareBuzz; + + #endif /* (CY_PSOC3) */ + + uint8 wakeupCfg0; /* Wake up configuration 0 */ + uint8 wakeupCfg1; /* Wake up configuration 1 */ + uint8 wakeupCfg2; /* Wake up configuration 2 */ + + uint8 wakeupTrim0; + uint8 wakeupTrim1; + + #if(CY_PSOC5) + + uint8 wakeupTrim3; + + #endif /* (CY_PSOC5) */ + + uint8 scctData[28u]; /* SC/CT routing registers */ + + /* CyPmHviLviSaveDisable()/CyPmHviLviRestore() */ + uint8 lvidEn; + uint8 lvidTrip; + uint8 lviaEn; + uint8 lviaTrip; + uint8 hviaEn; + uint8 lvidRst; + uint8 lviaRst; + + uint8 imoActFreq; /* Last moment IMO change */ + uint8 imoActFreq12Mhz; /* 12 MHz or not */ + + uint8 boostRefExt; /* Boost reference selection */ + +} CY_PM_BACKUP_STRUCT; + + +/*************************************** +* Registers +***************************************/ + +/* Power Mode Wakeup Trim Register 1 */ +#define CY_PM_PWRSYS_WAKE_TR1_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR1 ) +#define CY_PM_PWRSYS_WAKE_TR1_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR1 ) + +#if(CY_PSOC5) + /* Power Mode Wakeup Trim Register 3 */ + #define CY_PM_PWRSYS_WAKE_TR3_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR3 ) + #define CY_PM_PWRSYS_WAKE_TR3_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR3 ) +#endif /* (CY_PSOC5) */ + +/* Master clock Divider Value Register */ +#define CY_PM_CLKDIST_MSTR0_REG (* (reg8 *) CYREG_CLKDIST_MSTR0 ) +#define CY_PM_CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0 ) + +/* Master Clock Configuration Register/CPU Divider Value */ +#define CY_PM_CLKDIST_MSTR1_REG (* (reg8 *) CYREG_CLKDIST_MSTR1 ) +#define CY_PM_CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1 ) + +/* Clock distribution configuration Register */ +#define CY_PM_CLKDIST_CR_REG (* (reg8 *) CYREG_CLKDIST_CR ) +#define CY_PM_CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR ) + +/* CLK_BUS LSB Divider Value Register */ +#define CY_PM_CLK_BUS_LSB_DIV_REG (* (reg8 *) CYREG_CLKDIST_BCFG0 ) +#define CY_PM_CLK_BUS_LSB_DIV_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0 ) + +/* CLK_BUS MSB Divider Value Register */ +#define CY_PM_CLK_BUS_MSB_DIV_REG (* (reg8 *) CYREG_CLKDIST_BCFG1 ) +#define CY_PM_CLK_BUS_MSB_DIV_PTR ( (reg8 *) CYREG_CLKDIST_BCFG1 ) + +/* CLK_BUS Configuration Register */ +#define CLK_BUS_CFG_REG (* (reg8 *) CYREG_CLKDIST_BCFG2 ) +#define CLK_BUS_CFG_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2 ) + +/* Power Mode Control/Status Register */ +#define CY_PM_MODE_CSR_REG (* (reg8 *) CYREG_PM_MODE_CSR ) +#define CY_PM_MODE_CSR_PTR ( (reg8 *) CYREG_PM_MODE_CSR ) + +/* Power System Control Register 1 */ +#define CY_PM_PWRSYS_CR1_REG (* (reg8 *) CYREG_PWRSYS_CR1 ) +#define CY_PM_PWRSYS_CR1_PTR ( (reg8 *) CYREG_PWRSYS_CR1 ) + +/* Power System Control Register 0 */ +#define CY_PM_PWRSYS_CR0_REG (* (reg8 *) CYREG_PWRSYS_CR0 ) +#define CY_PM_PWRSYS_CR0_PTR ( (reg8 *) CYREG_PWRSYS_CR0 ) + +/* Internal Low-speed Oscillator Control Register 0 */ +#define CY_PM_SLOWCLK_ILO_CR0_REG (* (reg8 *) CYREG_SLOWCLK_ILO_CR0 ) +#define CY_PM_SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0 ) + +/* External 32kHz Crystal Oscillator Control Register */ +#define CY_PM_SLOWCLK_X32_CR_REG (* (reg8 *) CYREG_SLOWCLK_X32_CR ) +#define CY_PM_SLOWCLK_X32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR ) + +#if(CY_PSOC3) + + /* MLOGIC Debug Register */ + #define CY_PM_MLOGIC_DBG_REG (* (reg8 *) CYREG_MLOGIC_DEBUG ) + #define CY_PM_MLOGIC_DBG_PTR ( (reg8 *) CYREG_MLOGIC_DEBUG ) + + /* Port Pin Configuration Register */ + #define CY_PM_PRT1_PC3_REG (* (reg8 *) CYREG_PRT1_PC3 ) + #define CY_PM_PRT1_PC3_PTR ( (reg8 *) CYREG_PRT1_PC3 ) + +#endif /* (CY_PSOC3) */ + + +/* Sleep Regulator Trim Register */ +#define CY_PM_PWRSYS_SLP_TR_REG (* (reg8 *) CYREG_PWRSYS_SLP_TR ) +#define CY_PM_PWRSYS_SLP_TR_PTR ( (reg8 *) CYREG_PWRSYS_SLP_TR ) + + +/* Reset System Control Register */ +#define CY_PM_RESET_CR1_REG (* (reg8 *) CYREG_RESET_CR1 ) +#define CY_PM_RESET_CR1_PTR ( (reg8 *) CYREG_RESET_CR1 ) + +/* Power Mode Wakeup Trim Register 0 */ +#define CY_PM_PWRSYS_WAKE_TR0_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR0 ) +#define CY_PM_PWRSYS_WAKE_TR0_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR0 ) + +#if(CY_PSOC3) + + /* Power Mode Wakeup Trim Register 2 */ + #define CY_PM_PWRSYS_WAKE_TR2_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR2 ) + #define CY_PM_PWRSYS_WAKE_TR2_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR2 ) + +#endif /* (CY_PSOC3) */ + +/* Power Manager Interrupt Status Register */ +#define CY_PM_INT_SR_REG (* (reg8 *) CYREG_PM_INT_SR ) +#define CY_PM_INT_SR_PTR ( (reg8 *) CYREG_PM_INT_SR ) + +/* Active Power Mode Configuration Register 0 */ +#define CY_PM_ACT_CFG0_REG (* (reg8 *) CYREG_PM_ACT_CFG0 ) +#define CY_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 ) + +/* Active Power Mode Configuration Register 1 */ +#define CY_PM_ACT_CFG1_REG (* (reg8 *) CYREG_PM_ACT_CFG1 ) +#define CY_PM_ACT_CFG1_PTR ( (reg8 *) CYREG_PM_ACT_CFG1 ) + +/* Active Power Mode Configuration Register 2 */ +#define CY_PM_ACT_CFG2_REG (* (reg8 *) CYREG_PM_ACT_CFG2 ) +#define CY_PM_ACT_CFG2_PTR ( (reg8 *) CYREG_PM_ACT_CFG2 ) + +/* Boost Control 1 */ +#define CY_PM_BOOST_CR1_REG (* (reg8 *) CYREG_BOOST_CR1 ) +#define CY_PM_BOOST_CR1_PTR ( (reg8 *) CYREG_BOOST_CR1 ) + +/* Timewheel Configuration Register 0 */ +#define CY_PM_TW_CFG0_REG (* (reg8 *) CYREG_PM_TW_CFG0 ) +#define CY_PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0 ) + +/* Timewheel Configuration Register 1 */ +#define CY_PM_TW_CFG1_REG (* (reg8 *) CYREG_PM_TW_CFG1 ) +#define CY_PM_TW_CFG1_PTR ( (reg8 *) CYREG_PM_TW_CFG1 ) + +/* Timewheel Configuration Register 2 */ +#define CY_PM_TW_CFG2_REG (* (reg8 *) CYREG_PM_TW_CFG2 ) +#define CY_PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2 ) + +/* PLL Status Register */ +#define CY_PM_FASTCLK_PLL_SR_REG (*(reg8 *) CYREG_FASTCLK_PLL_SR ) +#define CY_PM_FASTCLK_PLL_SR_PTR ( (reg8 *) CYREG_FASTCLK_PLL_SR ) + +/* Internal Main Oscillator Control Register */ +#define CY_PM_FASTCLK_IMO_CR_REG (* (reg8 *) CYREG_FASTCLK_IMO_CR ) +#define CY_PM_FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR ) + +/* PLL Configuration Register */ +#define CY_PM_FASTCLK_PLL_CFG0_REG (* (reg8 *) CYREG_FASTCLK_PLL_CFG0 ) +#define CY_PM_FASTCLK_PLL_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG0 ) + +/* External 4-33 MHz Crystal Oscillator Status and Control Register */ +#define CY_PM_FASTCLK_XMHZ_CSR_REG (* (reg8 *) CYREG_FASTCLK_XMHZ_CSR ) +#define CY_PM_FASTCLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR ) + +/* Delay block Configuration Register */ +#define CY_PM_CLKDIST_DELAY_REG (* (reg8 *) CYREG_CLKDIST_DLY1 ) +#define CY_PM_CLKDIST_DELAY_PTR ( (reg8 *) CYREG_CLKDIST_DLY1 ) + + +#if(CY_PSOC3) + + /* Cache Control Register */ + #define CY_PM_CACHE_CR_REG (* (reg8 *) CYREG_CACHE_CR ) + #define CY_PM_CACHE_CR_PTR ( (reg8 *) CYREG_CACHE_CR ) + +#else /* Device is PSoC 5 */ + + /* Cache Control Register */ + #define CY_PM_CACHE_CR_REG (* (reg8 *) CYREG_CACHE_CC_CTL ) + #define CY_PM_CACHE_CR_PTR ( (reg8 *) CYREG_CACHE_CC_CTL ) + +#endif /* (CY_PSOC3) */ + + +/* Power Mode Wakeup Mask Configuration Register 0 */ +#define CY_PM_WAKEUP_CFG0_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG0 ) +#define CY_PM_WAKEUP_CFG0_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG0 ) + +/* Power Mode Wakeup Mask Configuration Register 1 */ +#define CY_PM_WAKEUP_CFG1_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG1 ) +#define CY_PM_WAKEUP_CFG1_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG1 ) + +/* Power Mode Wakeup Mask Configuration Register 2 */ +#define CY_PM_WAKEUP_CFG2_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG2 ) +#define CY_PM_WAKEUP_CFG2_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG2 ) + +/* Boost Control 2 */ +#define CY_PM_BOOST_CR2_REG (* (reg8 *) CYREG_BOOST_CR2 ) +#define CY_PM_BOOST_CR2_PTR ( (reg8 *) CYREG_BOOST_CR2 ) + +#if(CY_PSOC3) + + /* Interrrupt Controller Configuration and Status Register */ + #define CY_PM_INTC_CSR_EN_REG (* (reg8 *) CYREG_INTC_CSR_EN ) + #define CY_PM_INTC_CSR_EN_PTR ( (reg8 *) CYREG_INTC_CSR_EN ) + +#endif /* (CY_PSOC3) */ + + +/*************************************** +* Register Constants +***************************************/ + +/* Internal Main Oscillator Control Register */ + +#define CY_PM_FASTCLK_IMO_CR_FREQ_MASK (0x07u) /* IMO frequency mask */ +#define CY_PM_FASTCLK_IMO_CR_FREQ_12MHZ (0x00u) /* IMO frequency 12 MHz */ +#define CY_PM_FASTCLK_IMO_CR_F2XON (0x10u) /* IMO doubler enable */ +#define CY_PM_FASTCLK_IMO_CR_USB (0x40u) /* IMO is in USB mode */ + +#define CY_PM_MASTER_CLK_SRC_IMO (0u) +#define CY_PM_MASTER_CLK_SRC_PLL (1u) +#define CY_PM_MASTER_CLK_SRC_XTAL (2u) +#define CY_PM_MASTER_CLK_SRC_DSI (3u) +#define CY_PM_MASTER_CLK_SRC_MASK (3u) + +#define CY_PM_PLL_CFG0_ENABLE (0x01u) /* PLL enable */ +#define CY_PM_PLL_STATUS_LOCK (0x01u) /* PLL Lock Status */ +#define CY_PM_XMHZ_CSR_ENABLE (0x01u) /* Enable X MHz OSC */ +#define CY_PM_XMHZ_CSR_XERR (0x80u) /* High indicates failure */ +#define CY_PM_BOOST_ENABLE (0x08u) /* Boost enable */ +#define CY_PM_ILO_CR0_EN_1K (0x02u) /* Enable 1kHz ILO */ +#define CY_PM_ILO_CR0_EN_100K (0x04u) /* Enable 100kHz ILO */ +#define CY_PM_ILO_CR0_PD_MODE (0x10u) /* Power down mode for ILO*/ +#define CY_PM_X32_CR_X32EN (0x01u) /* Enable 32kHz OSC */ + +#define CY_PM_CTW_IE (0x08u) /* CTW interrupt enable */ +#define CY_PM_CTW_EN (0x04u) /* CTW enable */ +#define CY_PM_FTW_IE (0x02u) /* FTW interrupt enable */ +#define CY_PM_FTW_EN (0x01u) /* FTW enable */ +#define CY_PM_1PPS_EN (0x10u) /* 1PPS enable */ +#define CY_PM_1PPS_IE (0x20u) /* 1PPS interrupt enable */ + + +#define CY_PM_ACT_EN_CLK_A_MASK (0x0Fu) +#define CY_PM_ACT_EN_CLK_D_MASK (0xFFu) + +#define CY_PM_DIV_BY_ONE (0x00u) + +/* Internal Main Oscillator Control Register */ +#define CY_PM_FASTCLK_IMO_CR_XCLKEN (0x20u) + +/* Clock distribution configuration Register */ +#define CY_PM_CLKDIST_IMO_OUT_MASK (0x30u) +#define CY_PM_CLKDIST_IMO_OUT_IMO (0x00u) +#define CY_PM_CLKDIST_IMO2X_SRC (0x40u) + +#define CY_PM_CLKDIST_PLL_SRC_MASK (0x03u) +#define CY_PM_CLKDIST_PLL_SRC_IMO (0x00u) +#define CY_PM_CLKDIST_PLL_SRC_XTAL (0x01u) +#define CY_PM_CLKDIST_PLL_SRC_DSI (0x02u) + +/* Waiting for hibernate/sleep regulator to stabilize */ +#define CY_PM_MODE_CSR_PWRUP_PULSE_Q (0x08u) + +#define CY_PM_MODE_CSR_ACTIVE (0x00u) /* Active power mode */ +#define CY_PM_MODE_CSR_ALT_ACT (0x01u) /* Alternate Active power */ +#define CY_PM_MODE_CSR_SLEEP (0x03u) /* Sleep power mode */ +#define CY_PM_MODE_CSR_HIBERNATE (0x04u) /* Hibernate power mode */ +#define CY_PM_MODE_CSR_MASK (0x07u) + +/* I2C regulator backup enable */ +#define CY_PM_PWRSYS_CR1_I2CREG_BACKUP (0x04u) + +/* When set, prepares system to disable LDO-A */ +#define CY_PM_PWRSYS_CR1_LDOA_ISO (0x01u) + +/* When set, disables analog LDO regulator */ +#define CY_PM_PWRSYS_CR1_LDOA_DIS (0x02u) + +#define CY_PM_PWRSYS_WAKE_TR2_VCCD_CLK_DET (0x04u) + +#define CY_PM_FTW_INT (0x01u) /* FTW event has occured */ +#define CY_PM_CTW_INT (0x02u) /* CTW event has occured */ +#define CY_PM_ONEPPS_INT (0x04u) /* 1PPS event has occured */ + +/* Active Power Mode Configuration Register 0 */ +#define CY_PM_ACT_CFG0_IMO (0x10u) /* IMO enable in Active */ + +/* Cache Control Register (same mask for all device revisions) */ +#define CY_PM_CACHE_CR_CYCLES_MASK (0xC0u) + +/* Bus Clock divider to divide-by-one */ +#define CY_PM_BUS_CLK_DIV_BY_ONE (0x00u) + +/* HVI/LVI feature on external analog and digital supply mask */ +#define CY_PM_RESET_CR1_HVI_LVI_EN_MASK (0x07u) + +/* High-voltage-interrupt feature on external analog supply */ +#define CY_PM_RESET_CR1_HVIA_EN (0x04u) + +/* Low-voltage-interrupt feature on external analog supply */ +#define CY_PM_RESET_CR1_LVIA_EN (0x02u) + +/* Low-voltage-interrupt feature on external digital supply */ +#define CY_PM_RESET_CR1_LVID_EN (0x01u) + +/* Allows system to program delays on clk_sync_d */ +#define CY_PM_CLKDIST_DELAY_EN (0x04u) + + +#define CY_PM_WAKEUP_SRC_CMPS_MASK (0x000Fu) + +/* Holdoff mask sleep trim */ +#define CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK (0x1Fu) + +#if(CY_PSOC3) + + /* CPU clock divider mask */ + #define CY_PM_CLKDIST_CPU_DIV_MASK (0xF0u) + + /* Serial Wire View (SWV) clock enable */ + #define CY_PM_MLOGIC_DBG_SWV_CLK_EN (0x04u) + + /* Port drive mode */ + #define CY_PM_PRT1_PC3_DM_MASK (0xf1u) + + /* Mode 6, stong pull-up, strong pull-down */ + #define CY_PM_PRT1_PC3_DM_STRONG (0x0Cu) + + /* When set, enables buzz wakeups */ + #define CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ (0x01u) + +#endif /* (CY_PSOC3) */ + + +/* Disables sleep regulator and shorts vccd to vpwrsleep */ +#define CY_PM_PWRSYS_SLP_TR_BYPASS (0x10u) + +/* Boost Control 2: Select external precision reference */ +#define CY_PM_BOOST_CR2_EREFSEL_EXT (0x08u) + +#if(CY_PSOC3) + + #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu) + #define CY_PM_PWRSYS_WAKE_TR1 (0x90u) + +#endif /* (CY_PSOC3) */ + +#if(CY_PSOC5) + + #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu) + #define CY_PM_PWRSYS_WAKE_TR1 (0xB0u) + #define CY_PM_PWRSYS_WAKE_TR3 (0xFFu) + +#endif /* (CY_PSOC5) */ + +#if(CY_PSOC3) + + /* Interrrupt Controller Configuration and Status Register */ + #define CY_PM_INTC_CSR_EN_CLK (0x01u) + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Lock Status Flag. If lock is acquired this flag will stay set (regardless of +* whether lock is subsequently lost) until it is read. Upon reading it will +* clear. If lock is still true then the bit will simply set again. If lock +* happens to be false when the clear on read occurs then the bit will stay +* cleared until the next lock event. +*******************************************************************************/ +#define CY_PM_FASTCLK_PLL_LOCKED (0x01u) + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting with cy_boot 3.30 +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#if(CY_PSOC3) + + /* Was removed as redundant */ + #define CY_PM_FTW_INTERVAL_MASK (0xFFu) + +#endif /* (CY_PSOC3) */ + +/* Was removed as redundant */ +#define CY_PM_CTW_INTERVAL_MASK (0x0Fu) + +#endif /* (CY_BOOT_CYPM_H) */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/cydevice.h b/source/hic_hal/cypress/psoc5lp/PSoC5/cydevice.h new file mode 100644 index 0000000000..1a903bd924 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/cydevice.h @@ -0,0 +1,5366 @@ +/******************************************************************************* +* File Name: cydevice.h +* +* Description: +* This file provides all of the address values for the entire PSoC device. +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CYDEVICE_H) +#define CYDEVICE_H +#define CYDEV_FLASH_BASE 0x00000000u +#define CYDEV_FLASH_SIZE 0x00040000u +#define CYDEV_FLASH_DATA_MBASE 0x00000000u +#define CYDEV_FLASH_DATA_MSIZE 0x00040000u +#define CYDEV_SRAM_BASE 0x1fff8000u +#define CYDEV_SRAM_SIZE 0x00010000u +#define CYDEV_SRAM_CODE64K_MBASE 0x1fff8000u +#define CYDEV_SRAM_CODE64K_MSIZE 0x00004000u +#define CYDEV_SRAM_CODE32K_MBASE 0x1fffc000u +#define CYDEV_SRAM_CODE32K_MSIZE 0x00002000u +#define CYDEV_SRAM_CODE16K_MBASE 0x1fffe000u +#define CYDEV_SRAM_CODE16K_MSIZE 0x00001000u +#define CYDEV_SRAM_CODE_MBASE 0x1fff8000u +#define CYDEV_SRAM_CODE_MSIZE 0x00008000u +#define CYDEV_SRAM_DATA_MBASE 0x20000000u +#define CYDEV_SRAM_DATA_MSIZE 0x00008000u +#define CYDEV_SRAM_DATA16K_MBASE 0x20001000u +#define CYDEV_SRAM_DATA16K_MSIZE 0x00001000u +#define CYDEV_SRAM_DATA32K_MBASE 0x20002000u +#define CYDEV_SRAM_DATA32K_MSIZE 0x00002000u +#define CYDEV_SRAM_DATA64K_MBASE 0x20004000u +#define CYDEV_SRAM_DATA64K_MSIZE 0x00004000u +#define CYDEV_DMA_BASE 0x20008000u +#define CYDEV_DMA_SIZE 0x00008000u +#define CYDEV_DMA_SRAM64K_MBASE 0x20008000u +#define CYDEV_DMA_SRAM64K_MSIZE 0x00004000u +#define CYDEV_DMA_SRAM32K_MBASE 0x2000c000u +#define CYDEV_DMA_SRAM32K_MSIZE 0x00002000u +#define CYDEV_DMA_SRAM16K_MBASE 0x2000e000u +#define CYDEV_DMA_SRAM16K_MSIZE 0x00001000u +#define CYDEV_DMA_SRAM_MBASE 0x2000f000u +#define CYDEV_DMA_SRAM_MSIZE 0x00001000u +#define CYDEV_CLKDIST_BASE 0x40004000u +#define CYDEV_CLKDIST_SIZE 0x00000110u +#define CYDEV_CLKDIST_CR 0x40004000u +#define CYDEV_CLKDIST_LD 0x40004001u +#define CYDEV_CLKDIST_WRK0 0x40004002u +#define CYDEV_CLKDIST_WRK1 0x40004003u +#define CYDEV_CLKDIST_MSTR0 0x40004004u +#define CYDEV_CLKDIST_MSTR1 0x40004005u +#define CYDEV_CLKDIST_BCFG0 0x40004006u +#define CYDEV_CLKDIST_BCFG1 0x40004007u +#define CYDEV_CLKDIST_BCFG2 0x40004008u +#define CYDEV_CLKDIST_UCFG 0x40004009u +#define CYDEV_CLKDIST_DLY0 0x4000400au +#define CYDEV_CLKDIST_DLY1 0x4000400bu +#define CYDEV_CLKDIST_DMASK 0x40004010u +#define CYDEV_CLKDIST_AMASK 0x40004014u +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080u +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG0_CFG0 0x40004080u +#define CYDEV_CLKDIST_DCFG0_CFG1 0x40004081u +#define CYDEV_CLKDIST_DCFG0_CFG2 0x40004082u +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084u +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG1_CFG0 0x40004084u +#define CYDEV_CLKDIST_DCFG1_CFG1 0x40004085u +#define CYDEV_CLKDIST_DCFG1_CFG2 0x40004086u +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088u +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG2_CFG0 0x40004088u +#define CYDEV_CLKDIST_DCFG2_CFG1 0x40004089u +#define CYDEV_CLKDIST_DCFG2_CFG2 0x4000408au +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408cu +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG3_CFG0 0x4000408cu +#define CYDEV_CLKDIST_DCFG3_CFG1 0x4000408du +#define CYDEV_CLKDIST_DCFG3_CFG2 0x4000408eu +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090u +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG4_CFG0 0x40004090u +#define CYDEV_CLKDIST_DCFG4_CFG1 0x40004091u +#define CYDEV_CLKDIST_DCFG4_CFG2 0x40004092u +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094u +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG5_CFG0 0x40004094u +#define CYDEV_CLKDIST_DCFG5_CFG1 0x40004095u +#define CYDEV_CLKDIST_DCFG5_CFG2 0x40004096u +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098u +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG6_CFG0 0x40004098u +#define CYDEV_CLKDIST_DCFG6_CFG1 0x40004099u +#define CYDEV_CLKDIST_DCFG6_CFG2 0x4000409au +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409cu +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG7_CFG0 0x4000409cu +#define CYDEV_CLKDIST_DCFG7_CFG1 0x4000409du +#define CYDEV_CLKDIST_DCFG7_CFG2 0x4000409eu +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100u +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG0_CFG0 0x40004100u +#define CYDEV_CLKDIST_ACFG0_CFG1 0x40004101u +#define CYDEV_CLKDIST_ACFG0_CFG2 0x40004102u +#define CYDEV_CLKDIST_ACFG0_CFG3 0x40004103u +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104u +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG1_CFG0 0x40004104u +#define CYDEV_CLKDIST_ACFG1_CFG1 0x40004105u +#define CYDEV_CLKDIST_ACFG1_CFG2 0x40004106u +#define CYDEV_CLKDIST_ACFG1_CFG3 0x40004107u +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108u +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG2_CFG0 0x40004108u +#define CYDEV_CLKDIST_ACFG2_CFG1 0x40004109u +#define CYDEV_CLKDIST_ACFG2_CFG2 0x4000410au +#define CYDEV_CLKDIST_ACFG2_CFG3 0x4000410bu +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410cu +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG3_CFG0 0x4000410cu +#define CYDEV_CLKDIST_ACFG3_CFG1 0x4000410du +#define CYDEV_CLKDIST_ACFG3_CFG2 0x4000410eu +#define CYDEV_CLKDIST_ACFG3_CFG3 0x4000410fu +#define CYDEV_FASTCLK_BASE 0x40004200u +#define CYDEV_FASTCLK_SIZE 0x00000026u +#define CYDEV_FASTCLK_IMO_BASE 0x40004200u +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001u +#define CYDEV_FASTCLK_IMO_CR 0x40004200u +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210u +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004u +#define CYDEV_FASTCLK_XMHZ_CSR 0x40004210u +#define CYDEV_FASTCLK_XMHZ_CFG0 0x40004212u +#define CYDEV_FASTCLK_XMHZ_CFG1 0x40004213u +#define CYDEV_FASTCLK_PLL_BASE 0x40004220u +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006u +#define CYDEV_FASTCLK_PLL_CFG0 0x40004220u +#define CYDEV_FASTCLK_PLL_CFG1 0x40004221u +#define CYDEV_FASTCLK_PLL_P 0x40004222u +#define CYDEV_FASTCLK_PLL_Q 0x40004223u +#define CYDEV_FASTCLK_PLL_SR 0x40004225u +#define CYDEV_SLOWCLK_BASE 0x40004300u +#define CYDEV_SLOWCLK_SIZE 0x0000000bu +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300u +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002u +#define CYDEV_SLOWCLK_ILO_CR0 0x40004300u +#define CYDEV_SLOWCLK_ILO_CR1 0x40004301u +#define CYDEV_SLOWCLK_X32_BASE 0x40004308u +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003u +#define CYDEV_SLOWCLK_X32_CR 0x40004308u +#define CYDEV_SLOWCLK_X32_CFG 0x40004309u +#define CYDEV_SLOWCLK_X32_TST 0x4000430au +#define CYDEV_BOOST_BASE 0x40004320u +#define CYDEV_BOOST_SIZE 0x00000007u +#define CYDEV_BOOST_CR0 0x40004320u +#define CYDEV_BOOST_CR1 0x40004321u +#define CYDEV_BOOST_CR2 0x40004322u +#define CYDEV_BOOST_CR3 0x40004323u +#define CYDEV_BOOST_SR 0x40004324u +#define CYDEV_BOOST_CR4 0x40004325u +#define CYDEV_BOOST_SR2 0x40004326u +#define CYDEV_PWRSYS_BASE 0x40004330u +#define CYDEV_PWRSYS_SIZE 0x00000002u +#define CYDEV_PWRSYS_CR0 0x40004330u +#define CYDEV_PWRSYS_CR1 0x40004331u +#define CYDEV_PM_BASE 0x40004380u +#define CYDEV_PM_SIZE 0x00000057u +#define CYDEV_PM_TW_CFG0 0x40004380u +#define CYDEV_PM_TW_CFG1 0x40004381u +#define CYDEV_PM_TW_CFG2 0x40004382u +#define CYDEV_PM_WDT_CFG 0x40004383u +#define CYDEV_PM_WDT_CR 0x40004384u +#define CYDEV_PM_INT_SR 0x40004390u +#define CYDEV_PM_MODE_CFG0 0x40004391u +#define CYDEV_PM_MODE_CFG1 0x40004392u +#define CYDEV_PM_MODE_CSR 0x40004393u +#define CYDEV_PM_USB_CR0 0x40004394u +#define CYDEV_PM_WAKEUP_CFG0 0x40004398u +#define CYDEV_PM_WAKEUP_CFG1 0x40004399u +#define CYDEV_PM_WAKEUP_CFG2 0x4000439au +#define CYDEV_PM_ACT_BASE 0x400043a0u +#define CYDEV_PM_ACT_SIZE 0x0000000eu +#define CYDEV_PM_ACT_CFG0 0x400043a0u +#define CYDEV_PM_ACT_CFG1 0x400043a1u +#define CYDEV_PM_ACT_CFG2 0x400043a2u +#define CYDEV_PM_ACT_CFG3 0x400043a3u +#define CYDEV_PM_ACT_CFG4 0x400043a4u +#define CYDEV_PM_ACT_CFG5 0x400043a5u +#define CYDEV_PM_ACT_CFG6 0x400043a6u +#define CYDEV_PM_ACT_CFG7 0x400043a7u +#define CYDEV_PM_ACT_CFG8 0x400043a8u +#define CYDEV_PM_ACT_CFG9 0x400043a9u +#define CYDEV_PM_ACT_CFG10 0x400043aau +#define CYDEV_PM_ACT_CFG11 0x400043abu +#define CYDEV_PM_ACT_CFG12 0x400043acu +#define CYDEV_PM_ACT_CFG13 0x400043adu +#define CYDEV_PM_STBY_BASE 0x400043b0u +#define CYDEV_PM_STBY_SIZE 0x0000000eu +#define CYDEV_PM_STBY_CFG0 0x400043b0u +#define CYDEV_PM_STBY_CFG1 0x400043b1u +#define CYDEV_PM_STBY_CFG2 0x400043b2u +#define CYDEV_PM_STBY_CFG3 0x400043b3u +#define CYDEV_PM_STBY_CFG4 0x400043b4u +#define CYDEV_PM_STBY_CFG5 0x400043b5u +#define CYDEV_PM_STBY_CFG6 0x400043b6u +#define CYDEV_PM_STBY_CFG7 0x400043b7u +#define CYDEV_PM_STBY_CFG8 0x400043b8u +#define CYDEV_PM_STBY_CFG9 0x400043b9u +#define CYDEV_PM_STBY_CFG10 0x400043bau +#define CYDEV_PM_STBY_CFG11 0x400043bbu +#define CYDEV_PM_STBY_CFG12 0x400043bcu +#define CYDEV_PM_STBY_CFG13 0x400043bdu +#define CYDEV_PM_AVAIL_BASE 0x400043c0u +#define CYDEV_PM_AVAIL_SIZE 0x00000017u +#define CYDEV_PM_AVAIL_CR0 0x400043c0u +#define CYDEV_PM_AVAIL_CR1 0x400043c1u +#define CYDEV_PM_AVAIL_CR2 0x400043c2u +#define CYDEV_PM_AVAIL_CR3 0x400043c3u +#define CYDEV_PM_AVAIL_CR4 0x400043c4u +#define CYDEV_PM_AVAIL_CR5 0x400043c5u +#define CYDEV_PM_AVAIL_CR6 0x400043c6u +#define CYDEV_PM_AVAIL_SR0 0x400043d0u +#define CYDEV_PM_AVAIL_SR1 0x400043d1u +#define CYDEV_PM_AVAIL_SR2 0x400043d2u +#define CYDEV_PM_AVAIL_SR3 0x400043d3u +#define CYDEV_PM_AVAIL_SR4 0x400043d4u +#define CYDEV_PM_AVAIL_SR5 0x400043d5u +#define CYDEV_PM_AVAIL_SR6 0x400043d6u +#define CYDEV_PICU_BASE 0x40004500u +#define CYDEV_PICU_SIZE 0x000000b0u +#define CYDEV_PICU_INTTYPE_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080u +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 0x40004500u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 0x40004501u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 0x40004502u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 0x40004503u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 0x40004504u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 0x40004505u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 0x40004506u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 0x40004507u +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508u +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 0x40004508u +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 0x40004509u +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 0x4000450au +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 0x4000450bu +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 0x4000450cu +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 0x4000450du +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 0x4000450eu +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 0x4000450fu +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510u +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 0x40004510u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 0x40004511u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 0x40004512u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 0x40004513u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 0x40004514u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 0x40004515u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 0x40004516u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 0x40004517u +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518u +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 0x40004518u +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 0x40004519u +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 0x4000451au +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 0x4000451bu +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 0x4000451cu +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 0x4000451du +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 0x4000451eu +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 0x4000451fu +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520u +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 0x40004520u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 0x40004521u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 0x40004522u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 0x40004523u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 0x40004524u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 0x40004525u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 0x40004526u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 0x40004527u +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528u +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 0x40004528u +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 0x40004529u +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 0x4000452au +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 0x4000452bu +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 0x4000452cu +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 0x4000452du +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 0x4000452eu +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 0x4000452fu +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530u +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 0x40004530u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 0x40004531u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 0x40004532u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 0x40004533u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 0x40004534u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 0x40004535u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 0x40004536u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 0x40004537u +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560u +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 0x40004560u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 0x40004561u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 0x40004562u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 0x40004563u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 0x40004564u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 0x40004565u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 0x40004566u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 0x40004567u +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578u +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 0x40004578u +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 0x40004579u +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 0x4000457au +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 0x4000457bu +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 0x4000457cu +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 0x4000457du +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 0x4000457eu +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 0x4000457fu +#define CYDEV_PICU_STAT_BASE 0x40004580u +#define CYDEV_PICU_STAT_SIZE 0x00000010u +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580u +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU0_INTSTAT 0x40004580u +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581u +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU1_INTSTAT 0x40004581u +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582u +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU2_INTSTAT 0x40004582u +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583u +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU3_INTSTAT 0x40004583u +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584u +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU4_INTSTAT 0x40004584u +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585u +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU5_INTSTAT 0x40004585u +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586u +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU6_INTSTAT 0x40004586u +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458cu +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU12_INTSTAT 0x4000458cu +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458fu +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU15_INTSTAT 0x4000458fu +#define CYDEV_PICU_SNAP_BASE 0x40004590u +#define CYDEV_PICU_SNAP_SIZE 0x00000010u +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590u +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU0_SNAP 0x40004590u +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591u +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU1_SNAP 0x40004591u +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592u +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU2_SNAP 0x40004592u +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593u +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU3_SNAP 0x40004593u +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594u +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU4_SNAP 0x40004594u +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595u +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU5_SNAP 0x40004595u +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596u +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU6_SNAP 0x40004596u +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459cu +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU12_SNAP 0x4000459cu +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459fu +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU_15_SNAP_15 0x4000459fu +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010u +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045afu +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR 0x400045afu +#define CYDEV_MFGCFG_BASE 0x40004600u +#define CYDEV_MFGCFG_SIZE 0x000000edu +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600u +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038u +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC0_TR 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC1_TR 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC2_TR 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC3_TR 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 0x40004612u +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_SAR0_TR0 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616u +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_SAR1_TR0 0x40004616u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 0x40004620u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 0x40004621u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 0x40004622u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 0x40004623u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 0x40004624u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 0x40004625u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 0x40004626u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 0x40004627u +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630u +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP0_TR0 0x40004630u +#define CYDEV_MFGCFG_ANAIF_CMP0_TR1 0x40004631u +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632u +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP1_TR0 0x40004632u +#define CYDEV_MFGCFG_ANAIF_CMP1_TR1 0x40004633u +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634u +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP2_TR0 0x40004634u +#define CYDEV_MFGCFG_ANAIF_CMP2_TR1 0x40004635u +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636u +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP3_TR0 0x40004636u +#define CYDEV_MFGCFG_ANAIF_CMP3_TR1 0x40004637u +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680u +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000bu +#define CYDEV_MFGCFG_PWRSYS_HIB_TR0 0x40004680u +#define CYDEV_MFGCFG_PWRSYS_HIB_TR1 0x40004681u +#define CYDEV_MFGCFG_PWRSYS_I2C_TR 0x40004682u +#define CYDEV_MFGCFG_PWRSYS_SLP_TR 0x40004683u +#define CYDEV_MFGCFG_PWRSYS_BUZZ_TR 0x40004684u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR0 0x40004685u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR1 0x40004686u +#define CYDEV_MFGCFG_PWRSYS_BREF_TR 0x40004687u +#define CYDEV_MFGCFG_PWRSYS_BG_TR 0x40004688u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR2 0x40004689u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR3 0x4000468au +#define CYDEV_MFGCFG_ILO_BASE 0x40004690u +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002u +#define CYDEV_MFGCFG_ILO_TR0 0x40004690u +#define CYDEV_MFGCFG_ILO_TR1 0x40004691u +#define CYDEV_MFGCFG_X32_BASE 0x40004698u +#define CYDEV_MFGCFG_X32_SIZE 0x00000001u +#define CYDEV_MFGCFG_X32_TR 0x40004698u +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0u +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005u +#define CYDEV_MFGCFG_IMO_TR0 0x400046a0u +#define CYDEV_MFGCFG_IMO_TR1 0x400046a1u +#define CYDEV_MFGCFG_IMO_GAIN 0x400046a2u +#define CYDEV_MFGCFG_IMO_C36M 0x400046a3u +#define CYDEV_MFGCFG_IMO_TR2 0x400046a4u +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8u +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001u +#define CYDEV_MFGCFG_XMHZ_TR 0x400046a8u +#define CYDEV_MFGCFG_DLY 0x400046c0u +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0u +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000du +#define CYDEV_MFGCFG_MLOGIC_DMPSTR 0x400046e2u +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4u +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002u +#define CYDEV_MFGCFG_MLOGIC_SEG_CR 0x400046e4u +#define CYDEV_MFGCFG_MLOGIC_SEG_CFG0 0x400046e5u +#define CYDEV_MFGCFG_MLOGIC_DEBUG 0x400046e8u +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046eau +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001u +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR 0x400046eau +#define CYDEV_MFGCFG_MLOGIC_REV_ID 0x400046ecu +#define CYDEV_RESET_BASE 0x400046f0u +#define CYDEV_RESET_SIZE 0x0000000fu +#define CYDEV_RESET_IPOR_CR0 0x400046f0u +#define CYDEV_RESET_IPOR_CR1 0x400046f1u +#define CYDEV_RESET_IPOR_CR2 0x400046f2u +#define CYDEV_RESET_IPOR_CR3 0x400046f3u +#define CYDEV_RESET_CR0 0x400046f4u +#define CYDEV_RESET_CR1 0x400046f5u +#define CYDEV_RESET_CR2 0x400046f6u +#define CYDEV_RESET_CR3 0x400046f7u +#define CYDEV_RESET_CR4 0x400046f8u +#define CYDEV_RESET_CR5 0x400046f9u +#define CYDEV_RESET_SR0 0x400046fau +#define CYDEV_RESET_SR1 0x400046fbu +#define CYDEV_RESET_SR2 0x400046fcu +#define CYDEV_RESET_SR3 0x400046fdu +#define CYDEV_RESET_TR 0x400046feu +#define CYDEV_SPC_BASE 0x40004700u +#define CYDEV_SPC_SIZE 0x00000100u +#define CYDEV_SPC_FM_EE_CR 0x40004700u +#define CYDEV_SPC_FM_EE_WAKE_CNT 0x40004701u +#define CYDEV_SPC_EE_SCR 0x40004702u +#define CYDEV_SPC_EE_ERR 0x40004703u +#define CYDEV_SPC_CPU_DATA 0x40004720u +#define CYDEV_SPC_DMA_DATA 0x40004721u +#define CYDEV_SPC_SR 0x40004722u +#define CYDEV_SPC_CR 0x40004723u +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780u +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080u +#define CYDEV_SPC_DMM_MAP_SRAM_MBASE 0x40004780u +#define CYDEV_SPC_DMM_MAP_SRAM_MSIZE 0x00000080u +#define CYDEV_CACHE_BASE 0x40004800u +#define CYDEV_CACHE_SIZE 0x0000009cu +#define CYDEV_CACHE_CC_CTL 0x40004800u +#define CYDEV_CACHE_ECC_CORR 0x40004880u +#define CYDEV_CACHE_ECC_ERR 0x40004888u +#define CYDEV_CACHE_FLASH_ERR 0x40004890u +#define CYDEV_CACHE_HITMISS 0x40004898u +#define CYDEV_I2C_BASE 0x40004900u +#define CYDEV_I2C_SIZE 0x000000e1u +#define CYDEV_I2C_XCFG 0x400049c8u +#define CYDEV_I2C_ADR 0x400049cau +#define CYDEV_I2C_CFG 0x400049d6u +#define CYDEV_I2C_CSR 0x400049d7u +#define CYDEV_I2C_D 0x400049d8u +#define CYDEV_I2C_MCSR 0x400049d9u +#define CYDEV_I2C_CLK_DIV1 0x400049dbu +#define CYDEV_I2C_CLK_DIV2 0x400049dcu +#define CYDEV_I2C_TMOUT_CSR 0x400049ddu +#define CYDEV_I2C_TMOUT_SR 0x400049deu +#define CYDEV_I2C_TMOUT_CFG0 0x400049dfu +#define CYDEV_I2C_TMOUT_CFG1 0x400049e0u +#define CYDEV_DEC_BASE 0x40004e00u +#define CYDEV_DEC_SIZE 0x00000015u +#define CYDEV_DEC_CR 0x40004e00u +#define CYDEV_DEC_SR 0x40004e01u +#define CYDEV_DEC_SHIFT1 0x40004e02u +#define CYDEV_DEC_SHIFT2 0x40004e03u +#define CYDEV_DEC_DR2 0x40004e04u +#define CYDEV_DEC_DR2H 0x40004e05u +#define CYDEV_DEC_DR1 0x40004e06u +#define CYDEV_DEC_OCOR 0x40004e08u +#define CYDEV_DEC_OCORM 0x40004e09u +#define CYDEV_DEC_OCORH 0x40004e0au +#define CYDEV_DEC_GCOR 0x40004e0cu +#define CYDEV_DEC_GCORH 0x40004e0du +#define CYDEV_DEC_GVAL 0x40004e0eu +#define CYDEV_DEC_OUTSAMP 0x40004e10u +#define CYDEV_DEC_OUTSAMPM 0x40004e11u +#define CYDEV_DEC_OUTSAMPH 0x40004e12u +#define CYDEV_DEC_OUTSAMPS 0x40004e13u +#define CYDEV_DEC_COHER 0x40004e14u +#define CYDEV_TMR0_BASE 0x40004f00u +#define CYDEV_TMR0_SIZE 0x0000000cu +#define CYDEV_TMR0_CFG0 0x40004f00u +#define CYDEV_TMR0_CFG1 0x40004f01u +#define CYDEV_TMR0_CFG2 0x40004f02u +#define CYDEV_TMR0_SR0 0x40004f03u +#define CYDEV_TMR0_PER0 0x40004f04u +#define CYDEV_TMR0_PER1 0x40004f05u +#define CYDEV_TMR0_CNT_CMP0 0x40004f06u +#define CYDEV_TMR0_CNT_CMP1 0x40004f07u +#define CYDEV_TMR0_CAP0 0x40004f08u +#define CYDEV_TMR0_CAP1 0x40004f09u +#define CYDEV_TMR0_RT0 0x40004f0au +#define CYDEV_TMR0_RT1 0x40004f0bu +#define CYDEV_TMR1_BASE 0x40004f0cu +#define CYDEV_TMR1_SIZE 0x0000000cu +#define CYDEV_TMR1_CFG0 0x40004f0cu +#define CYDEV_TMR1_CFG1 0x40004f0du +#define CYDEV_TMR1_CFG2 0x40004f0eu +#define CYDEV_TMR1_SR0 0x40004f0fu +#define CYDEV_TMR1_PER0 0x40004f10u +#define CYDEV_TMR1_PER1 0x40004f11u +#define CYDEV_TMR1_CNT_CMP0 0x40004f12u +#define CYDEV_TMR1_CNT_CMP1 0x40004f13u +#define CYDEV_TMR1_CAP0 0x40004f14u +#define CYDEV_TMR1_CAP1 0x40004f15u +#define CYDEV_TMR1_RT0 0x40004f16u +#define CYDEV_TMR1_RT1 0x40004f17u +#define CYDEV_TMR2_BASE 0x40004f18u +#define CYDEV_TMR2_SIZE 0x0000000cu +#define CYDEV_TMR2_CFG0 0x40004f18u +#define CYDEV_TMR2_CFG1 0x40004f19u +#define CYDEV_TMR2_CFG2 0x40004f1au +#define CYDEV_TMR2_SR0 0x40004f1bu +#define CYDEV_TMR2_PER0 0x40004f1cu +#define CYDEV_TMR2_PER1 0x40004f1du +#define CYDEV_TMR2_CNT_CMP0 0x40004f1eu +#define CYDEV_TMR2_CNT_CMP1 0x40004f1fu +#define CYDEV_TMR2_CAP0 0x40004f20u +#define CYDEV_TMR2_CAP1 0x40004f21u +#define CYDEV_TMR2_RT0 0x40004f22u +#define CYDEV_TMR2_RT1 0x40004f23u +#define CYDEV_TMR3_BASE 0x40004f24u +#define CYDEV_TMR3_SIZE 0x0000000cu +#define CYDEV_TMR3_CFG0 0x40004f24u +#define CYDEV_TMR3_CFG1 0x40004f25u +#define CYDEV_TMR3_CFG2 0x40004f26u +#define CYDEV_TMR3_SR0 0x40004f27u +#define CYDEV_TMR3_PER0 0x40004f28u +#define CYDEV_TMR3_PER1 0x40004f29u +#define CYDEV_TMR3_CNT_CMP0 0x40004f2au +#define CYDEV_TMR3_CNT_CMP1 0x40004f2bu +#define CYDEV_TMR3_CAP0 0x40004f2cu +#define CYDEV_TMR3_CAP1 0x40004f2du +#define CYDEV_TMR3_RT0 0x40004f2eu +#define CYDEV_TMR3_RT1 0x40004f2fu +#define CYDEV_IO_BASE 0x40005000u +#define CYDEV_IO_SIZE 0x00000200u +#define CYDEV_IO_PC_BASE 0x40005000u +#define CYDEV_IO_PC_SIZE 0x00000080u +#define CYDEV_IO_PC_PRT0_BASE 0x40005000u +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT0_PC0 0x40005000u +#define CYDEV_IO_PC_PRT0_PC1 0x40005001u +#define CYDEV_IO_PC_PRT0_PC2 0x40005002u +#define CYDEV_IO_PC_PRT0_PC3 0x40005003u +#define CYDEV_IO_PC_PRT0_PC4 0x40005004u +#define CYDEV_IO_PC_PRT0_PC5 0x40005005u +#define CYDEV_IO_PC_PRT0_PC6 0x40005006u +#define CYDEV_IO_PC_PRT0_PC7 0x40005007u +#define CYDEV_IO_PC_PRT1_BASE 0x40005008u +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT1_PC0 0x40005008u +#define CYDEV_IO_PC_PRT1_PC1 0x40005009u +#define CYDEV_IO_PC_PRT1_PC2 0x4000500au +#define CYDEV_IO_PC_PRT1_PC3 0x4000500bu +#define CYDEV_IO_PC_PRT1_PC4 0x4000500cu +#define CYDEV_IO_PC_PRT1_PC5 0x4000500du +#define CYDEV_IO_PC_PRT1_PC6 0x4000500eu +#define CYDEV_IO_PC_PRT1_PC7 0x4000500fu +#define CYDEV_IO_PC_PRT2_BASE 0x40005010u +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT2_PC0 0x40005010u +#define CYDEV_IO_PC_PRT2_PC1 0x40005011u +#define CYDEV_IO_PC_PRT2_PC2 0x40005012u +#define CYDEV_IO_PC_PRT2_PC3 0x40005013u +#define CYDEV_IO_PC_PRT2_PC4 0x40005014u +#define CYDEV_IO_PC_PRT2_PC5 0x40005015u +#define CYDEV_IO_PC_PRT2_PC6 0x40005016u +#define CYDEV_IO_PC_PRT2_PC7 0x40005017u +#define CYDEV_IO_PC_PRT3_BASE 0x40005018u +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT3_PC0 0x40005018u +#define CYDEV_IO_PC_PRT3_PC1 0x40005019u +#define CYDEV_IO_PC_PRT3_PC2 0x4000501au +#define CYDEV_IO_PC_PRT3_PC3 0x4000501bu +#define CYDEV_IO_PC_PRT3_PC4 0x4000501cu +#define CYDEV_IO_PC_PRT3_PC5 0x4000501du +#define CYDEV_IO_PC_PRT3_PC6 0x4000501eu +#define CYDEV_IO_PC_PRT3_PC7 0x4000501fu +#define CYDEV_IO_PC_PRT4_BASE 0x40005020u +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT4_PC0 0x40005020u +#define CYDEV_IO_PC_PRT4_PC1 0x40005021u +#define CYDEV_IO_PC_PRT4_PC2 0x40005022u +#define CYDEV_IO_PC_PRT4_PC3 0x40005023u +#define CYDEV_IO_PC_PRT4_PC4 0x40005024u +#define CYDEV_IO_PC_PRT4_PC5 0x40005025u +#define CYDEV_IO_PC_PRT4_PC6 0x40005026u +#define CYDEV_IO_PC_PRT4_PC7 0x40005027u +#define CYDEV_IO_PC_PRT5_BASE 0x40005028u +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT5_PC0 0x40005028u +#define CYDEV_IO_PC_PRT5_PC1 0x40005029u +#define CYDEV_IO_PC_PRT5_PC2 0x4000502au +#define CYDEV_IO_PC_PRT5_PC3 0x4000502bu +#define CYDEV_IO_PC_PRT5_PC4 0x4000502cu +#define CYDEV_IO_PC_PRT5_PC5 0x4000502du +#define CYDEV_IO_PC_PRT5_PC6 0x4000502eu +#define CYDEV_IO_PC_PRT5_PC7 0x4000502fu +#define CYDEV_IO_PC_PRT6_BASE 0x40005030u +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT6_PC0 0x40005030u +#define CYDEV_IO_PC_PRT6_PC1 0x40005031u +#define CYDEV_IO_PC_PRT6_PC2 0x40005032u +#define CYDEV_IO_PC_PRT6_PC3 0x40005033u +#define CYDEV_IO_PC_PRT6_PC4 0x40005034u +#define CYDEV_IO_PC_PRT6_PC5 0x40005035u +#define CYDEV_IO_PC_PRT6_PC6 0x40005036u +#define CYDEV_IO_PC_PRT6_PC7 0x40005037u +#define CYDEV_IO_PC_PRT12_BASE 0x40005060u +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT12_PC0 0x40005060u +#define CYDEV_IO_PC_PRT12_PC1 0x40005061u +#define CYDEV_IO_PC_PRT12_PC2 0x40005062u +#define CYDEV_IO_PC_PRT12_PC3 0x40005063u +#define CYDEV_IO_PC_PRT12_PC4 0x40005064u +#define CYDEV_IO_PC_PRT12_PC5 0x40005065u +#define CYDEV_IO_PC_PRT12_PC6 0x40005066u +#define CYDEV_IO_PC_PRT12_PC7 0x40005067u +#define CYDEV_IO_PC_PRT15_BASE 0x40005078u +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006u +#define CYDEV_IO_PC_PRT15_PC0 0x40005078u +#define CYDEV_IO_PC_PRT15_PC1 0x40005079u +#define CYDEV_IO_PC_PRT15_PC2 0x4000507au +#define CYDEV_IO_PC_PRT15_PC3 0x4000507bu +#define CYDEV_IO_PC_PRT15_PC4 0x4000507cu +#define CYDEV_IO_PC_PRT15_PC5 0x4000507du +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507eu +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002u +#define CYDEV_IO_PC_PRT15_7_6_PC0 0x4000507eu +#define CYDEV_IO_PC_PRT15_7_6_PC1 0x4000507fu +#define CYDEV_IO_DR_BASE 0x40005080u +#define CYDEV_IO_DR_SIZE 0x00000010u +#define CYDEV_IO_DR_PRT0_BASE 0x40005080u +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT0_DR_ALIAS 0x40005080u +#define CYDEV_IO_DR_PRT1_BASE 0x40005081u +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT1_DR_ALIAS 0x40005081u +#define CYDEV_IO_DR_PRT2_BASE 0x40005082u +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT2_DR_ALIAS 0x40005082u +#define CYDEV_IO_DR_PRT3_BASE 0x40005083u +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT3_DR_ALIAS 0x40005083u +#define CYDEV_IO_DR_PRT4_BASE 0x40005084u +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT4_DR_ALIAS 0x40005084u +#define CYDEV_IO_DR_PRT5_BASE 0x40005085u +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT5_DR_ALIAS 0x40005085u +#define CYDEV_IO_DR_PRT6_BASE 0x40005086u +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT6_DR_ALIAS 0x40005086u +#define CYDEV_IO_DR_PRT12_BASE 0x4000508cu +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT12_DR_ALIAS 0x4000508cu +#define CYDEV_IO_DR_PRT15_BASE 0x4000508fu +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT15_DR_15_ALIAS 0x4000508fu +#define CYDEV_IO_PS_BASE 0x40005090u +#define CYDEV_IO_PS_SIZE 0x00000010u +#define CYDEV_IO_PS_PRT0_BASE 0x40005090u +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT0_PS_ALIAS 0x40005090u +#define CYDEV_IO_PS_PRT1_BASE 0x40005091u +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT1_PS_ALIAS 0x40005091u +#define CYDEV_IO_PS_PRT2_BASE 0x40005092u +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT2_PS_ALIAS 0x40005092u +#define CYDEV_IO_PS_PRT3_BASE 0x40005093u +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT3_PS_ALIAS 0x40005093u +#define CYDEV_IO_PS_PRT4_BASE 0x40005094u +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT4_PS_ALIAS 0x40005094u +#define CYDEV_IO_PS_PRT5_BASE 0x40005095u +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT5_PS_ALIAS 0x40005095u +#define CYDEV_IO_PS_PRT6_BASE 0x40005096u +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT6_PS_ALIAS 0x40005096u +#define CYDEV_IO_PS_PRT12_BASE 0x4000509cu +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT12_PS_ALIAS 0x4000509cu +#define CYDEV_IO_PS_PRT15_BASE 0x4000509fu +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT15_PS15_ALIAS 0x4000509fu +#define CYDEV_IO_PRT_BASE 0x40005100u +#define CYDEV_IO_PRT_SIZE 0x00000100u +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100u +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT0_DR 0x40005100u +#define CYDEV_IO_PRT_PRT0_PS 0x40005101u +#define CYDEV_IO_PRT_PRT0_DM0 0x40005102u +#define CYDEV_IO_PRT_PRT0_DM1 0x40005103u +#define CYDEV_IO_PRT_PRT0_DM2 0x40005104u +#define CYDEV_IO_PRT_PRT0_SLW 0x40005105u +#define CYDEV_IO_PRT_PRT0_BYP 0x40005106u +#define CYDEV_IO_PRT_PRT0_BIE 0x40005107u +#define CYDEV_IO_PRT_PRT0_INP_DIS 0x40005108u +#define CYDEV_IO_PRT_PRT0_CTL 0x40005109u +#define CYDEV_IO_PRT_PRT0_PRT 0x4000510au +#define CYDEV_IO_PRT_PRT0_BIT_MASK 0x4000510bu +#define CYDEV_IO_PRT_PRT0_AMUX 0x4000510cu +#define CYDEV_IO_PRT_PRT0_AG 0x4000510du +#define CYDEV_IO_PRT_PRT0_LCD_COM_SEG 0x4000510eu +#define CYDEV_IO_PRT_PRT0_LCD_EN 0x4000510fu +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110u +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT1_DR 0x40005110u +#define CYDEV_IO_PRT_PRT1_PS 0x40005111u +#define CYDEV_IO_PRT_PRT1_DM0 0x40005112u +#define CYDEV_IO_PRT_PRT1_DM1 0x40005113u +#define CYDEV_IO_PRT_PRT1_DM2 0x40005114u +#define CYDEV_IO_PRT_PRT1_SLW 0x40005115u +#define CYDEV_IO_PRT_PRT1_BYP 0x40005116u +#define CYDEV_IO_PRT_PRT1_BIE 0x40005117u +#define CYDEV_IO_PRT_PRT1_INP_DIS 0x40005118u +#define CYDEV_IO_PRT_PRT1_CTL 0x40005119u +#define CYDEV_IO_PRT_PRT1_PRT 0x4000511au +#define CYDEV_IO_PRT_PRT1_BIT_MASK 0x4000511bu +#define CYDEV_IO_PRT_PRT1_AMUX 0x4000511cu +#define CYDEV_IO_PRT_PRT1_AG 0x4000511du +#define CYDEV_IO_PRT_PRT1_LCD_COM_SEG 0x4000511eu +#define CYDEV_IO_PRT_PRT1_LCD_EN 0x4000511fu +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120u +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT2_DR 0x40005120u +#define CYDEV_IO_PRT_PRT2_PS 0x40005121u +#define CYDEV_IO_PRT_PRT2_DM0 0x40005122u +#define CYDEV_IO_PRT_PRT2_DM1 0x40005123u +#define CYDEV_IO_PRT_PRT2_DM2 0x40005124u +#define CYDEV_IO_PRT_PRT2_SLW 0x40005125u +#define CYDEV_IO_PRT_PRT2_BYP 0x40005126u +#define CYDEV_IO_PRT_PRT2_BIE 0x40005127u +#define CYDEV_IO_PRT_PRT2_INP_DIS 0x40005128u +#define CYDEV_IO_PRT_PRT2_CTL 0x40005129u +#define CYDEV_IO_PRT_PRT2_PRT 0x4000512au +#define CYDEV_IO_PRT_PRT2_BIT_MASK 0x4000512bu +#define CYDEV_IO_PRT_PRT2_AMUX 0x4000512cu +#define CYDEV_IO_PRT_PRT2_AG 0x4000512du +#define CYDEV_IO_PRT_PRT2_LCD_COM_SEG 0x4000512eu +#define CYDEV_IO_PRT_PRT2_LCD_EN 0x4000512fu +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130u +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT3_DR 0x40005130u +#define CYDEV_IO_PRT_PRT3_PS 0x40005131u +#define CYDEV_IO_PRT_PRT3_DM0 0x40005132u +#define CYDEV_IO_PRT_PRT3_DM1 0x40005133u +#define CYDEV_IO_PRT_PRT3_DM2 0x40005134u +#define CYDEV_IO_PRT_PRT3_SLW 0x40005135u +#define CYDEV_IO_PRT_PRT3_BYP 0x40005136u +#define CYDEV_IO_PRT_PRT3_BIE 0x40005137u +#define CYDEV_IO_PRT_PRT3_INP_DIS 0x40005138u +#define CYDEV_IO_PRT_PRT3_CTL 0x40005139u +#define CYDEV_IO_PRT_PRT3_PRT 0x4000513au +#define CYDEV_IO_PRT_PRT3_BIT_MASK 0x4000513bu +#define CYDEV_IO_PRT_PRT3_AMUX 0x4000513cu +#define CYDEV_IO_PRT_PRT3_AG 0x4000513du +#define CYDEV_IO_PRT_PRT3_LCD_COM_SEG 0x4000513eu +#define CYDEV_IO_PRT_PRT3_LCD_EN 0x4000513fu +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140u +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT4_DR 0x40005140u +#define CYDEV_IO_PRT_PRT4_PS 0x40005141u +#define CYDEV_IO_PRT_PRT4_DM0 0x40005142u +#define CYDEV_IO_PRT_PRT4_DM1 0x40005143u +#define CYDEV_IO_PRT_PRT4_DM2 0x40005144u +#define CYDEV_IO_PRT_PRT4_SLW 0x40005145u +#define CYDEV_IO_PRT_PRT4_BYP 0x40005146u +#define CYDEV_IO_PRT_PRT4_BIE 0x40005147u +#define CYDEV_IO_PRT_PRT4_INP_DIS 0x40005148u +#define CYDEV_IO_PRT_PRT4_CTL 0x40005149u +#define CYDEV_IO_PRT_PRT4_PRT 0x4000514au +#define CYDEV_IO_PRT_PRT4_BIT_MASK 0x4000514bu +#define CYDEV_IO_PRT_PRT4_AMUX 0x4000514cu +#define CYDEV_IO_PRT_PRT4_AG 0x4000514du +#define CYDEV_IO_PRT_PRT4_LCD_COM_SEG 0x4000514eu +#define CYDEV_IO_PRT_PRT4_LCD_EN 0x4000514fu +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150u +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT5_DR 0x40005150u +#define CYDEV_IO_PRT_PRT5_PS 0x40005151u +#define CYDEV_IO_PRT_PRT5_DM0 0x40005152u +#define CYDEV_IO_PRT_PRT5_DM1 0x40005153u +#define CYDEV_IO_PRT_PRT5_DM2 0x40005154u +#define CYDEV_IO_PRT_PRT5_SLW 0x40005155u +#define CYDEV_IO_PRT_PRT5_BYP 0x40005156u +#define CYDEV_IO_PRT_PRT5_BIE 0x40005157u +#define CYDEV_IO_PRT_PRT5_INP_DIS 0x40005158u +#define CYDEV_IO_PRT_PRT5_CTL 0x40005159u +#define CYDEV_IO_PRT_PRT5_PRT 0x4000515au +#define CYDEV_IO_PRT_PRT5_BIT_MASK 0x4000515bu +#define CYDEV_IO_PRT_PRT5_AMUX 0x4000515cu +#define CYDEV_IO_PRT_PRT5_AG 0x4000515du +#define CYDEV_IO_PRT_PRT5_LCD_COM_SEG 0x4000515eu +#define CYDEV_IO_PRT_PRT5_LCD_EN 0x4000515fu +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160u +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT6_DR 0x40005160u +#define CYDEV_IO_PRT_PRT6_PS 0x40005161u +#define CYDEV_IO_PRT_PRT6_DM0 0x40005162u +#define CYDEV_IO_PRT_PRT6_DM1 0x40005163u +#define CYDEV_IO_PRT_PRT6_DM2 0x40005164u +#define CYDEV_IO_PRT_PRT6_SLW 0x40005165u +#define CYDEV_IO_PRT_PRT6_BYP 0x40005166u +#define CYDEV_IO_PRT_PRT6_BIE 0x40005167u +#define CYDEV_IO_PRT_PRT6_INP_DIS 0x40005168u +#define CYDEV_IO_PRT_PRT6_CTL 0x40005169u +#define CYDEV_IO_PRT_PRT6_PRT 0x4000516au +#define CYDEV_IO_PRT_PRT6_BIT_MASK 0x4000516bu +#define CYDEV_IO_PRT_PRT6_AMUX 0x4000516cu +#define CYDEV_IO_PRT_PRT6_AG 0x4000516du +#define CYDEV_IO_PRT_PRT6_LCD_COM_SEG 0x4000516eu +#define CYDEV_IO_PRT_PRT6_LCD_EN 0x4000516fu +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0u +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT12_DR 0x400051c0u +#define CYDEV_IO_PRT_PRT12_PS 0x400051c1u +#define CYDEV_IO_PRT_PRT12_DM0 0x400051c2u +#define CYDEV_IO_PRT_PRT12_DM1 0x400051c3u +#define CYDEV_IO_PRT_PRT12_DM2 0x400051c4u +#define CYDEV_IO_PRT_PRT12_SLW 0x400051c5u +#define CYDEV_IO_PRT_PRT12_BYP 0x400051c6u +#define CYDEV_IO_PRT_PRT12_BIE 0x400051c7u +#define CYDEV_IO_PRT_PRT12_INP_DIS 0x400051c8u +#define CYDEV_IO_PRT_PRT12_SIO_HYST_EN 0x400051c9u +#define CYDEV_IO_PRT_PRT12_PRT 0x400051cau +#define CYDEV_IO_PRT_PRT12_BIT_MASK 0x400051cbu +#define CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ 0x400051ccu +#define CYDEV_IO_PRT_PRT12_AG 0x400051cdu +#define CYDEV_IO_PRT_PRT12_SIO_CFG 0x400051ceu +#define CYDEV_IO_PRT_PRT12_SIO_DIFF 0x400051cfu +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0u +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT15_DR 0x400051f0u +#define CYDEV_IO_PRT_PRT15_PS 0x400051f1u +#define CYDEV_IO_PRT_PRT15_DM0 0x400051f2u +#define CYDEV_IO_PRT_PRT15_DM1 0x400051f3u +#define CYDEV_IO_PRT_PRT15_DM2 0x400051f4u +#define CYDEV_IO_PRT_PRT15_SLW 0x400051f5u +#define CYDEV_IO_PRT_PRT15_BYP 0x400051f6u +#define CYDEV_IO_PRT_PRT15_BIE 0x400051f7u +#define CYDEV_IO_PRT_PRT15_INP_DIS 0x400051f8u +#define CYDEV_IO_PRT_PRT15_CTL 0x400051f9u +#define CYDEV_IO_PRT_PRT15_PRT 0x400051fau +#define CYDEV_IO_PRT_PRT15_BIT_MASK 0x400051fbu +#define CYDEV_IO_PRT_PRT15_AMUX 0x400051fcu +#define CYDEV_IO_PRT_PRT15_AG 0x400051fdu +#define CYDEV_IO_PRT_PRT15_LCD_COM_SEG 0x400051feu +#define CYDEV_IO_PRT_PRT15_LCD_EN 0x400051ffu +#define CYDEV_PRTDSI_BASE 0x40005200u +#define CYDEV_PRTDSI_SIZE 0x0000007fu +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200u +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT0_OUT_SEL0 0x40005200u +#define CYDEV_PRTDSI_PRT0_OUT_SEL1 0x40005201u +#define CYDEV_PRTDSI_PRT0_OE_SEL0 0x40005202u +#define CYDEV_PRTDSI_PRT0_OE_SEL1 0x40005203u +#define CYDEV_PRTDSI_PRT0_DBL_SYNC_IN 0x40005204u +#define CYDEV_PRTDSI_PRT0_SYNC_OUT 0x40005205u +#define CYDEV_PRTDSI_PRT0_CAPS_SEL 0x40005206u +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208u +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT1_OUT_SEL0 0x40005208u +#define CYDEV_PRTDSI_PRT1_OUT_SEL1 0x40005209u +#define CYDEV_PRTDSI_PRT1_OE_SEL0 0x4000520au +#define CYDEV_PRTDSI_PRT1_OE_SEL1 0x4000520bu +#define CYDEV_PRTDSI_PRT1_DBL_SYNC_IN 0x4000520cu +#define CYDEV_PRTDSI_PRT1_SYNC_OUT 0x4000520du +#define CYDEV_PRTDSI_PRT1_CAPS_SEL 0x4000520eu +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210u +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT2_OUT_SEL0 0x40005210u +#define CYDEV_PRTDSI_PRT2_OUT_SEL1 0x40005211u +#define CYDEV_PRTDSI_PRT2_OE_SEL0 0x40005212u +#define CYDEV_PRTDSI_PRT2_OE_SEL1 0x40005213u +#define CYDEV_PRTDSI_PRT2_DBL_SYNC_IN 0x40005214u +#define CYDEV_PRTDSI_PRT2_SYNC_OUT 0x40005215u +#define CYDEV_PRTDSI_PRT2_CAPS_SEL 0x40005216u +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218u +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT3_OUT_SEL0 0x40005218u +#define CYDEV_PRTDSI_PRT3_OUT_SEL1 0x40005219u +#define CYDEV_PRTDSI_PRT3_OE_SEL0 0x4000521au +#define CYDEV_PRTDSI_PRT3_OE_SEL1 0x4000521bu +#define CYDEV_PRTDSI_PRT3_DBL_SYNC_IN 0x4000521cu +#define CYDEV_PRTDSI_PRT3_SYNC_OUT 0x4000521du +#define CYDEV_PRTDSI_PRT3_CAPS_SEL 0x4000521eu +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220u +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT4_OUT_SEL0 0x40005220u +#define CYDEV_PRTDSI_PRT4_OUT_SEL1 0x40005221u +#define CYDEV_PRTDSI_PRT4_OE_SEL0 0x40005222u +#define CYDEV_PRTDSI_PRT4_OE_SEL1 0x40005223u +#define CYDEV_PRTDSI_PRT4_DBL_SYNC_IN 0x40005224u +#define CYDEV_PRTDSI_PRT4_SYNC_OUT 0x40005225u +#define CYDEV_PRTDSI_PRT4_CAPS_SEL 0x40005226u +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228u +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT5_OUT_SEL0 0x40005228u +#define CYDEV_PRTDSI_PRT5_OUT_SEL1 0x40005229u +#define CYDEV_PRTDSI_PRT5_OE_SEL0 0x4000522au +#define CYDEV_PRTDSI_PRT5_OE_SEL1 0x4000522bu +#define CYDEV_PRTDSI_PRT5_DBL_SYNC_IN 0x4000522cu +#define CYDEV_PRTDSI_PRT5_SYNC_OUT 0x4000522du +#define CYDEV_PRTDSI_PRT5_CAPS_SEL 0x4000522eu +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230u +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT6_OUT_SEL0 0x40005230u +#define CYDEV_PRTDSI_PRT6_OUT_SEL1 0x40005231u +#define CYDEV_PRTDSI_PRT6_OE_SEL0 0x40005232u +#define CYDEV_PRTDSI_PRT6_OE_SEL1 0x40005233u +#define CYDEV_PRTDSI_PRT6_DBL_SYNC_IN 0x40005234u +#define CYDEV_PRTDSI_PRT6_SYNC_OUT 0x40005235u +#define CYDEV_PRTDSI_PRT6_CAPS_SEL 0x40005236u +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260u +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006u +#define CYDEV_PRTDSI_PRT12_OUT_SEL0 0x40005260u +#define CYDEV_PRTDSI_PRT12_OUT_SEL1 0x40005261u +#define CYDEV_PRTDSI_PRT12_OE_SEL0 0x40005262u +#define CYDEV_PRTDSI_PRT12_OE_SEL1 0x40005263u +#define CYDEV_PRTDSI_PRT12_DBL_SYNC_IN 0x40005264u +#define CYDEV_PRTDSI_PRT12_SYNC_OUT 0x40005265u +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278u +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT15_OUT_SEL0 0x40005278u +#define CYDEV_PRTDSI_PRT15_OUT_SEL1 0x40005279u +#define CYDEV_PRTDSI_PRT15_OE_SEL0 0x4000527au +#define CYDEV_PRTDSI_PRT15_OE_SEL1 0x4000527bu +#define CYDEV_PRTDSI_PRT15_DBL_SYNC_IN 0x4000527cu +#define CYDEV_PRTDSI_PRT15_SYNC_OUT 0x4000527du +#define CYDEV_PRTDSI_PRT15_CAPS_SEL 0x4000527eu +#define CYDEV_EMIF_BASE 0x40005400u +#define CYDEV_EMIF_SIZE 0x00000007u +#define CYDEV_EMIF_NO_UDB 0x40005400u +#define CYDEV_EMIF_RP_WAIT_STATES 0x40005401u +#define CYDEV_EMIF_MEM_DWN 0x40005402u +#define CYDEV_EMIF_MEMCLK_DIV 0x40005403u +#define CYDEV_EMIF_CLOCK_EN 0x40005404u +#define CYDEV_EMIF_EM_TYPE 0x40005405u +#define CYDEV_EMIF_WP_WAIT_STATES 0x40005406u +#define CYDEV_ANAIF_BASE 0x40005800u +#define CYDEV_ANAIF_SIZE 0x000003a9u +#define CYDEV_ANAIF_CFG_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SIZE 0x0000010fu +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC0_CR0 0x40005800u +#define CYDEV_ANAIF_CFG_SC0_CR1 0x40005801u +#define CYDEV_ANAIF_CFG_SC0_CR2 0x40005802u +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804u +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC1_CR0 0x40005804u +#define CYDEV_ANAIF_CFG_SC1_CR1 0x40005805u +#define CYDEV_ANAIF_CFG_SC1_CR2 0x40005806u +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808u +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC2_CR0 0x40005808u +#define CYDEV_ANAIF_CFG_SC2_CR1 0x40005809u +#define CYDEV_ANAIF_CFG_SC2_CR2 0x4000580au +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580cu +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC3_CR0 0x4000580cu +#define CYDEV_ANAIF_CFG_SC3_CR1 0x4000580du +#define CYDEV_ANAIF_CFG_SC3_CR2 0x4000580eu +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820u +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC0_CR0 0x40005820u +#define CYDEV_ANAIF_CFG_DAC0_CR1 0x40005821u +#define CYDEV_ANAIF_CFG_DAC0_TST 0x40005822u +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824u +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC1_CR0 0x40005824u +#define CYDEV_ANAIF_CFG_DAC1_CR1 0x40005825u +#define CYDEV_ANAIF_CFG_DAC1_TST 0x40005826u +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828u +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC2_CR0 0x40005828u +#define CYDEV_ANAIF_CFG_DAC2_CR1 0x40005829u +#define CYDEV_ANAIF_CFG_DAC2_TST 0x4000582au +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582cu +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC3_CR0 0x4000582cu +#define CYDEV_ANAIF_CFG_DAC3_CR1 0x4000582du +#define CYDEV_ANAIF_CFG_DAC3_TST 0x4000582eu +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840u +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP0_CR 0x40005840u +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841u +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP1_CR 0x40005841u +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842u +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP2_CR 0x40005842u +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843u +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP3_CR 0x40005843u +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848u +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT0_CR 0x40005848u +#define CYDEV_ANAIF_CFG_LUT0_MX 0x40005849u +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584au +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT1_CR 0x4000584au +#define CYDEV_ANAIF_CFG_LUT1_MX 0x4000584bu +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584cu +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT2_CR 0x4000584cu +#define CYDEV_ANAIF_CFG_LUT2_MX 0x4000584du +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584eu +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT3_CR 0x4000584eu +#define CYDEV_ANAIF_CFG_LUT3_MX 0x4000584fu +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858u +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP0_CR 0x40005858u +#define CYDEV_ANAIF_CFG_OPAMP0_RSVD 0x40005859u +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585au +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP1_CR 0x4000585au +#define CYDEV_ANAIF_CFG_OPAMP1_RSVD 0x4000585bu +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585cu +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP2_CR 0x4000585cu +#define CYDEV_ANAIF_CFG_OPAMP2_RSVD 0x4000585du +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585eu +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP3_CR 0x4000585eu +#define CYDEV_ANAIF_CFG_OPAMP3_RSVD 0x4000585fu +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868u +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LCDDAC_CR0 0x40005868u +#define CYDEV_ANAIF_CFG_LCDDAC_CR1 0x40005869u +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586au +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_LCDDRV_CR 0x4000586au +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586bu +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_LCDTMR_CFG 0x4000586bu +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586cu +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004u +#define CYDEV_ANAIF_CFG_BG_CR0 0x4000586cu +#define CYDEV_ANAIF_CFG_BG_RSVD 0x4000586du +#define CYDEV_ANAIF_CFG_BG_DFT0 0x4000586eu +#define CYDEV_ANAIF_CFG_BG_DFT1 0x4000586fu +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870u +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_CAPSL_CFG0 0x40005870u +#define CYDEV_ANAIF_CFG_CAPSL_CFG1 0x40005871u +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872u +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_CAPSR_CFG0 0x40005872u +#define CYDEV_ANAIF_CFG_CAPSR_CFG1 0x40005873u +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876u +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_PUMP_CR0 0x40005876u +#define CYDEV_ANAIF_CFG_PUMP_CR1 0x40005877u +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878u +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LPF0_CR0 0x40005878u +#define CYDEV_ANAIF_CFG_LPF0_RSVD 0x40005879u +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587au +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LPF1_CR0 0x4000587au +#define CYDEV_ANAIF_CFG_LPF1_RSVD 0x4000587bu +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587cu +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_MISC_CR0 0x4000587cu +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880u +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020u +#define CYDEV_ANAIF_CFG_DSM0_CR0 0x40005880u +#define CYDEV_ANAIF_CFG_DSM0_CR1 0x40005881u +#define CYDEV_ANAIF_CFG_DSM0_CR2 0x40005882u +#define CYDEV_ANAIF_CFG_DSM0_CR3 0x40005883u +#define CYDEV_ANAIF_CFG_DSM0_CR4 0x40005884u +#define CYDEV_ANAIF_CFG_DSM0_CR5 0x40005885u +#define CYDEV_ANAIF_CFG_DSM0_CR6 0x40005886u +#define CYDEV_ANAIF_CFG_DSM0_CR7 0x40005887u +#define CYDEV_ANAIF_CFG_DSM0_CR8 0x40005888u +#define CYDEV_ANAIF_CFG_DSM0_CR9 0x40005889u +#define CYDEV_ANAIF_CFG_DSM0_CR10 0x4000588au +#define CYDEV_ANAIF_CFG_DSM0_CR11 0x4000588bu +#define CYDEV_ANAIF_CFG_DSM0_CR12 0x4000588cu +#define CYDEV_ANAIF_CFG_DSM0_CR13 0x4000588du +#define CYDEV_ANAIF_CFG_DSM0_CR14 0x4000588eu +#define CYDEV_ANAIF_CFG_DSM0_CR15 0x4000588fu +#define CYDEV_ANAIF_CFG_DSM0_CR16 0x40005890u +#define CYDEV_ANAIF_CFG_DSM0_CR17 0x40005891u +#define CYDEV_ANAIF_CFG_DSM0_REF0 0x40005892u +#define CYDEV_ANAIF_CFG_DSM0_REF1 0x40005893u +#define CYDEV_ANAIF_CFG_DSM0_REF2 0x40005894u +#define CYDEV_ANAIF_CFG_DSM0_REF3 0x40005895u +#define CYDEV_ANAIF_CFG_DSM0_DEM0 0x40005896u +#define CYDEV_ANAIF_CFG_DSM0_DEM1 0x40005897u +#define CYDEV_ANAIF_CFG_DSM0_TST0 0x40005898u +#define CYDEV_ANAIF_CFG_DSM0_TST1 0x40005899u +#define CYDEV_ANAIF_CFG_DSM0_BUF0 0x4000589au +#define CYDEV_ANAIF_CFG_DSM0_BUF1 0x4000589bu +#define CYDEV_ANAIF_CFG_DSM0_BUF2 0x4000589cu +#define CYDEV_ANAIF_CFG_DSM0_BUF3 0x4000589du +#define CYDEV_ANAIF_CFG_DSM0_MISC 0x4000589eu +#define CYDEV_ANAIF_CFG_DSM0_RSVD1 0x4000589fu +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900u +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007u +#define CYDEV_ANAIF_CFG_SAR0_CSR0 0x40005900u +#define CYDEV_ANAIF_CFG_SAR0_CSR1 0x40005901u +#define CYDEV_ANAIF_CFG_SAR0_CSR2 0x40005902u +#define CYDEV_ANAIF_CFG_SAR0_CSR3 0x40005903u +#define CYDEV_ANAIF_CFG_SAR0_CSR4 0x40005904u +#define CYDEV_ANAIF_CFG_SAR0_CSR5 0x40005905u +#define CYDEV_ANAIF_CFG_SAR0_CSR6 0x40005906u +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908u +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007u +#define CYDEV_ANAIF_CFG_SAR1_CSR0 0x40005908u +#define CYDEV_ANAIF_CFG_SAR1_CSR1 0x40005909u +#define CYDEV_ANAIF_CFG_SAR1_CSR2 0x4000590au +#define CYDEV_ANAIF_CFG_SAR1_CSR3 0x4000590bu +#define CYDEV_ANAIF_CFG_SAR1_CSR4 0x4000590cu +#define CYDEV_ANAIF_CFG_SAR1_CSR5 0x4000590du +#define CYDEV_ANAIF_CFG_SAR1_CSR6 0x4000590eu +#define CYDEV_ANAIF_RT_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SIZE 0x00000162u +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC0_SW0 0x40005a00u +#define CYDEV_ANAIF_RT_SC0_SW2 0x40005a02u +#define CYDEV_ANAIF_RT_SC0_SW3 0x40005a03u +#define CYDEV_ANAIF_RT_SC0_SW4 0x40005a04u +#define CYDEV_ANAIF_RT_SC0_SW6 0x40005a06u +#define CYDEV_ANAIF_RT_SC0_SW7 0x40005a07u +#define CYDEV_ANAIF_RT_SC0_SW8 0x40005a08u +#define CYDEV_ANAIF_RT_SC0_SW10 0x40005a0au +#define CYDEV_ANAIF_RT_SC0_CLK 0x40005a0bu +#define CYDEV_ANAIF_RT_SC0_BST 0x40005a0cu +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10u +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC1_SW0 0x40005a10u +#define CYDEV_ANAIF_RT_SC1_SW2 0x40005a12u +#define CYDEV_ANAIF_RT_SC1_SW3 0x40005a13u +#define CYDEV_ANAIF_RT_SC1_SW4 0x40005a14u +#define CYDEV_ANAIF_RT_SC1_SW6 0x40005a16u +#define CYDEV_ANAIF_RT_SC1_SW7 0x40005a17u +#define CYDEV_ANAIF_RT_SC1_SW8 0x40005a18u +#define CYDEV_ANAIF_RT_SC1_SW10 0x40005a1au +#define CYDEV_ANAIF_RT_SC1_CLK 0x40005a1bu +#define CYDEV_ANAIF_RT_SC1_BST 0x40005a1cu +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20u +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC2_SW0 0x40005a20u +#define CYDEV_ANAIF_RT_SC2_SW2 0x40005a22u +#define CYDEV_ANAIF_RT_SC2_SW3 0x40005a23u +#define CYDEV_ANAIF_RT_SC2_SW4 0x40005a24u +#define CYDEV_ANAIF_RT_SC2_SW6 0x40005a26u +#define CYDEV_ANAIF_RT_SC2_SW7 0x40005a27u +#define CYDEV_ANAIF_RT_SC2_SW8 0x40005a28u +#define CYDEV_ANAIF_RT_SC2_SW10 0x40005a2au +#define CYDEV_ANAIF_RT_SC2_CLK 0x40005a2bu +#define CYDEV_ANAIF_RT_SC2_BST 0x40005a2cu +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30u +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC3_SW0 0x40005a30u +#define CYDEV_ANAIF_RT_SC3_SW2 0x40005a32u +#define CYDEV_ANAIF_RT_SC3_SW3 0x40005a33u +#define CYDEV_ANAIF_RT_SC3_SW4 0x40005a34u +#define CYDEV_ANAIF_RT_SC3_SW6 0x40005a36u +#define CYDEV_ANAIF_RT_SC3_SW7 0x40005a37u +#define CYDEV_ANAIF_RT_SC3_SW8 0x40005a38u +#define CYDEV_ANAIF_RT_SC3_SW10 0x40005a3au +#define CYDEV_ANAIF_RT_SC3_CLK 0x40005a3bu +#define CYDEV_ANAIF_RT_SC3_BST 0x40005a3cu +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80u +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC0_SW0 0x40005a80u +#define CYDEV_ANAIF_RT_DAC0_SW2 0x40005a82u +#define CYDEV_ANAIF_RT_DAC0_SW3 0x40005a83u +#define CYDEV_ANAIF_RT_DAC0_SW4 0x40005a84u +#define CYDEV_ANAIF_RT_DAC0_STROBE 0x40005a87u +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88u +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC1_SW0 0x40005a88u +#define CYDEV_ANAIF_RT_DAC1_SW2 0x40005a8au +#define CYDEV_ANAIF_RT_DAC1_SW3 0x40005a8bu +#define CYDEV_ANAIF_RT_DAC1_SW4 0x40005a8cu +#define CYDEV_ANAIF_RT_DAC1_STROBE 0x40005a8fu +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90u +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC2_SW0 0x40005a90u +#define CYDEV_ANAIF_RT_DAC2_SW2 0x40005a92u +#define CYDEV_ANAIF_RT_DAC2_SW3 0x40005a93u +#define CYDEV_ANAIF_RT_DAC2_SW4 0x40005a94u +#define CYDEV_ANAIF_RT_DAC2_STROBE 0x40005a97u +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98u +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC3_SW0 0x40005a98u +#define CYDEV_ANAIF_RT_DAC3_SW2 0x40005a9au +#define CYDEV_ANAIF_RT_DAC3_SW3 0x40005a9bu +#define CYDEV_ANAIF_RT_DAC3_SW4 0x40005a9cu +#define CYDEV_ANAIF_RT_DAC3_STROBE 0x40005a9fu +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0u +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP0_SW0 0x40005ac0u +#define CYDEV_ANAIF_RT_CMP0_SW2 0x40005ac2u +#define CYDEV_ANAIF_RT_CMP0_SW3 0x40005ac3u +#define CYDEV_ANAIF_RT_CMP0_SW4 0x40005ac4u +#define CYDEV_ANAIF_RT_CMP0_SW6 0x40005ac6u +#define CYDEV_ANAIF_RT_CMP0_CLK 0x40005ac7u +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8u +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP1_SW0 0x40005ac8u +#define CYDEV_ANAIF_RT_CMP1_SW2 0x40005acau +#define CYDEV_ANAIF_RT_CMP1_SW3 0x40005acbu +#define CYDEV_ANAIF_RT_CMP1_SW4 0x40005accu +#define CYDEV_ANAIF_RT_CMP1_SW6 0x40005aceu +#define CYDEV_ANAIF_RT_CMP1_CLK 0x40005acfu +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0u +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP2_SW0 0x40005ad0u +#define CYDEV_ANAIF_RT_CMP2_SW2 0x40005ad2u +#define CYDEV_ANAIF_RT_CMP2_SW3 0x40005ad3u +#define CYDEV_ANAIF_RT_CMP2_SW4 0x40005ad4u +#define CYDEV_ANAIF_RT_CMP2_SW6 0x40005ad6u +#define CYDEV_ANAIF_RT_CMP2_CLK 0x40005ad7u +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8u +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP3_SW0 0x40005ad8u +#define CYDEV_ANAIF_RT_CMP3_SW2 0x40005adau +#define CYDEV_ANAIF_RT_CMP3_SW3 0x40005adbu +#define CYDEV_ANAIF_RT_CMP3_SW4 0x40005adcu +#define CYDEV_ANAIF_RT_CMP3_SW6 0x40005adeu +#define CYDEV_ANAIF_RT_CMP3_CLK 0x40005adfu +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00u +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DSM0_SW0 0x40005b00u +#define CYDEV_ANAIF_RT_DSM0_SW2 0x40005b02u +#define CYDEV_ANAIF_RT_DSM0_SW3 0x40005b03u +#define CYDEV_ANAIF_RT_DSM0_SW4 0x40005b04u +#define CYDEV_ANAIF_RT_DSM0_SW6 0x40005b06u +#define CYDEV_ANAIF_RT_DSM0_CLK 0x40005b07u +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20u +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_SAR0_SW0 0x40005b20u +#define CYDEV_ANAIF_RT_SAR0_SW2 0x40005b22u +#define CYDEV_ANAIF_RT_SAR0_SW3 0x40005b23u +#define CYDEV_ANAIF_RT_SAR0_SW4 0x40005b24u +#define CYDEV_ANAIF_RT_SAR0_SW6 0x40005b26u +#define CYDEV_ANAIF_RT_SAR0_CLK 0x40005b27u +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28u +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_SAR1_SW0 0x40005b28u +#define CYDEV_ANAIF_RT_SAR1_SW2 0x40005b2au +#define CYDEV_ANAIF_RT_SAR1_SW3 0x40005b2bu +#define CYDEV_ANAIF_RT_SAR1_SW4 0x40005b2cu +#define CYDEV_ANAIF_RT_SAR1_SW6 0x40005b2eu +#define CYDEV_ANAIF_RT_SAR1_CLK 0x40005b2fu +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40u +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP0_MX 0x40005b40u +#define CYDEV_ANAIF_RT_OPAMP0_SW 0x40005b41u +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42u +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP1_MX 0x40005b42u +#define CYDEV_ANAIF_RT_OPAMP1_SW 0x40005b43u +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44u +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP2_MX 0x40005b44u +#define CYDEV_ANAIF_RT_OPAMP2_SW 0x40005b45u +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46u +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP3_MX 0x40005b46u +#define CYDEV_ANAIF_RT_OPAMP3_SW 0x40005b47u +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50u +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005u +#define CYDEV_ANAIF_RT_LCDDAC_SW0 0x40005b50u +#define CYDEV_ANAIF_RT_LCDDAC_SW1 0x40005b51u +#define CYDEV_ANAIF_RT_LCDDAC_SW2 0x40005b52u +#define CYDEV_ANAIF_RT_LCDDAC_SW3 0x40005b53u +#define CYDEV_ANAIF_RT_LCDDAC_SW4 0x40005b54u +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56u +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001u +#define CYDEV_ANAIF_RT_SC_MISC 0x40005b56u +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58u +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004u +#define CYDEV_ANAIF_RT_BUS_SW0 0x40005b58u +#define CYDEV_ANAIF_RT_BUS_SW2 0x40005b5au +#define CYDEV_ANAIF_RT_BUS_SW3 0x40005b5bu +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5cu +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006u +#define CYDEV_ANAIF_RT_DFT_CR0 0x40005b5cu +#define CYDEV_ANAIF_RT_DFT_CR1 0x40005b5du +#define CYDEV_ANAIF_RT_DFT_CR2 0x40005b5eu +#define CYDEV_ANAIF_RT_DFT_CR3 0x40005b5fu +#define CYDEV_ANAIF_RT_DFT_CR4 0x40005b60u +#define CYDEV_ANAIF_RT_DFT_CR5 0x40005b61u +#define CYDEV_ANAIF_WRK_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_SIZE 0x00000029u +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC0_D 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC1_D 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC2_D 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83u +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC3_D 0x40005b83u +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88u +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_DSM0_OUT0 0x40005b88u +#define CYDEV_ANAIF_WRK_DSM0_OUT1 0x40005b89u +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90u +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005u +#define CYDEV_ANAIF_WRK_LUT_SR 0x40005b90u +#define CYDEV_ANAIF_WRK_LUT_WRK1 0x40005b91u +#define CYDEV_ANAIF_WRK_LUT_MSK 0x40005b92u +#define CYDEV_ANAIF_WRK_LUT_CLK 0x40005b93u +#define CYDEV_ANAIF_WRK_LUT_CPTR 0x40005b94u +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96u +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_CMP_WRK 0x40005b96u +#define CYDEV_ANAIF_WRK_CMP_TST 0x40005b97u +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98u +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005u +#define CYDEV_ANAIF_WRK_SC_SR 0x40005b98u +#define CYDEV_ANAIF_WRK_SC_WRK1 0x40005b99u +#define CYDEV_ANAIF_WRK_SC_MSK 0x40005b9au +#define CYDEV_ANAIF_WRK_SC_CMPINV 0x40005b9bu +#define CYDEV_ANAIF_WRK_SC_CPTR 0x40005b9cu +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0u +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_SAR0_WRK0 0x40005ba0u +#define CYDEV_ANAIF_WRK_SAR0_WRK1 0x40005ba1u +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2u +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_SAR1_WRK0 0x40005ba2u +#define CYDEV_ANAIF_WRK_SAR1_WRK1 0x40005ba3u +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8u +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_SARS_SOF 0x40005ba8u +#define CYDEV_USB_BASE 0x40006000u +#define CYDEV_USB_SIZE 0x00000300u +#define CYDEV_USB_EP0_DR0 0x40006000u +#define CYDEV_USB_EP0_DR1 0x40006001u +#define CYDEV_USB_EP0_DR2 0x40006002u +#define CYDEV_USB_EP0_DR3 0x40006003u +#define CYDEV_USB_EP0_DR4 0x40006004u +#define CYDEV_USB_EP0_DR5 0x40006005u +#define CYDEV_USB_EP0_DR6 0x40006006u +#define CYDEV_USB_EP0_DR7 0x40006007u +#define CYDEV_USB_CR0 0x40006008u +#define CYDEV_USB_CR1 0x40006009u +#define CYDEV_USB_SIE_EP_INT_EN 0x4000600au +#define CYDEV_USB_SIE_EP_INT_SR 0x4000600bu +#define CYDEV_USB_SIE_EP1_BASE 0x4000600cu +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP1_CNT0 0x4000600cu +#define CYDEV_USB_SIE_EP1_CNT1 0x4000600du +#define CYDEV_USB_SIE_EP1_CR0 0x4000600eu +#define CYDEV_USB_USBIO_CR0 0x40006010u +#define CYDEV_USB_USBIO_CR1 0x40006012u +#define CYDEV_USB_DYN_RECONFIG 0x40006014u +#define CYDEV_USB_SOF0 0x40006018u +#define CYDEV_USB_SOF1 0x40006019u +#define CYDEV_USB_SIE_EP2_BASE 0x4000601cu +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP2_CNT0 0x4000601cu +#define CYDEV_USB_SIE_EP2_CNT1 0x4000601du +#define CYDEV_USB_SIE_EP2_CR0 0x4000601eu +#define CYDEV_USB_EP0_CR 0x40006028u +#define CYDEV_USB_EP0_CNT 0x40006029u +#define CYDEV_USB_SIE_EP3_BASE 0x4000602cu +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP3_CNT0 0x4000602cu +#define CYDEV_USB_SIE_EP3_CNT1 0x4000602du +#define CYDEV_USB_SIE_EP3_CR0 0x4000602eu +#define CYDEV_USB_SIE_EP4_BASE 0x4000603cu +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP4_CNT0 0x4000603cu +#define CYDEV_USB_SIE_EP4_CNT1 0x4000603du +#define CYDEV_USB_SIE_EP4_CR0 0x4000603eu +#define CYDEV_USB_SIE_EP5_BASE 0x4000604cu +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP5_CNT0 0x4000604cu +#define CYDEV_USB_SIE_EP5_CNT1 0x4000604du +#define CYDEV_USB_SIE_EP5_CR0 0x4000604eu +#define CYDEV_USB_SIE_EP6_BASE 0x4000605cu +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP6_CNT0 0x4000605cu +#define CYDEV_USB_SIE_EP6_CNT1 0x4000605du +#define CYDEV_USB_SIE_EP6_CR0 0x4000605eu +#define CYDEV_USB_SIE_EP7_BASE 0x4000606cu +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP7_CNT0 0x4000606cu +#define CYDEV_USB_SIE_EP7_CNT1 0x4000606du +#define CYDEV_USB_SIE_EP7_CR0 0x4000606eu +#define CYDEV_USB_SIE_EP8_BASE 0x4000607cu +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP8_CNT0 0x4000607cu +#define CYDEV_USB_SIE_EP8_CNT1 0x4000607du +#define CYDEV_USB_SIE_EP8_CR0 0x4000607eu +#define CYDEV_USB_ARB_EP1_BASE 0x40006080u +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP1_CFG 0x40006080u +#define CYDEV_USB_ARB_EP1_INT_EN 0x40006081u +#define CYDEV_USB_ARB_EP1_SR 0x40006082u +#define CYDEV_USB_ARB_RW1_BASE 0x40006084u +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW1_WA 0x40006084u +#define CYDEV_USB_ARB_RW1_WA_MSB 0x40006085u +#define CYDEV_USB_ARB_RW1_RA 0x40006086u +#define CYDEV_USB_ARB_RW1_RA_MSB 0x40006087u +#define CYDEV_USB_ARB_RW1_DR 0x40006088u +#define CYDEV_USB_BUF_SIZE 0x4000608cu +#define CYDEV_USB_EP_ACTIVE 0x4000608eu +#define CYDEV_USB_EP_TYPE 0x4000608fu +#define CYDEV_USB_ARB_EP2_BASE 0x40006090u +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP2_CFG 0x40006090u +#define CYDEV_USB_ARB_EP2_INT_EN 0x40006091u +#define CYDEV_USB_ARB_EP2_SR 0x40006092u +#define CYDEV_USB_ARB_RW2_BASE 0x40006094u +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW2_WA 0x40006094u +#define CYDEV_USB_ARB_RW2_WA_MSB 0x40006095u +#define CYDEV_USB_ARB_RW2_RA 0x40006096u +#define CYDEV_USB_ARB_RW2_RA_MSB 0x40006097u +#define CYDEV_USB_ARB_RW2_DR 0x40006098u +#define CYDEV_USB_ARB_CFG 0x4000609cu +#define CYDEV_USB_USB_CLK_EN 0x4000609du +#define CYDEV_USB_ARB_INT_EN 0x4000609eu +#define CYDEV_USB_ARB_INT_SR 0x4000609fu +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0u +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP3_CFG 0x400060a0u +#define CYDEV_USB_ARB_EP3_INT_EN 0x400060a1u +#define CYDEV_USB_ARB_EP3_SR 0x400060a2u +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4u +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW3_WA 0x400060a4u +#define CYDEV_USB_ARB_RW3_WA_MSB 0x400060a5u +#define CYDEV_USB_ARB_RW3_RA 0x400060a6u +#define CYDEV_USB_ARB_RW3_RA_MSB 0x400060a7u +#define CYDEV_USB_ARB_RW3_DR 0x400060a8u +#define CYDEV_USB_CWA 0x400060acu +#define CYDEV_USB_CWA_MSB 0x400060adu +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0u +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP4_CFG 0x400060b0u +#define CYDEV_USB_ARB_EP4_INT_EN 0x400060b1u +#define CYDEV_USB_ARB_EP4_SR 0x400060b2u +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4u +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW4_WA 0x400060b4u +#define CYDEV_USB_ARB_RW4_WA_MSB 0x400060b5u +#define CYDEV_USB_ARB_RW4_RA 0x400060b6u +#define CYDEV_USB_ARB_RW4_RA_MSB 0x400060b7u +#define CYDEV_USB_ARB_RW4_DR 0x400060b8u +#define CYDEV_USB_DMA_THRES 0x400060bcu +#define CYDEV_USB_DMA_THRES_MSB 0x400060bdu +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0u +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP5_CFG 0x400060c0u +#define CYDEV_USB_ARB_EP5_INT_EN 0x400060c1u +#define CYDEV_USB_ARB_EP5_SR 0x400060c2u +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4u +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW5_WA 0x400060c4u +#define CYDEV_USB_ARB_RW5_WA_MSB 0x400060c5u +#define CYDEV_USB_ARB_RW5_RA 0x400060c6u +#define CYDEV_USB_ARB_RW5_RA_MSB 0x400060c7u +#define CYDEV_USB_ARB_RW5_DR 0x400060c8u +#define CYDEV_USB_BUS_RST_CNT 0x400060ccu +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0u +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP6_CFG 0x400060d0u +#define CYDEV_USB_ARB_EP6_INT_EN 0x400060d1u +#define CYDEV_USB_ARB_EP6_SR 0x400060d2u +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4u +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW6_WA 0x400060d4u +#define CYDEV_USB_ARB_RW6_WA_MSB 0x400060d5u +#define CYDEV_USB_ARB_RW6_RA 0x400060d6u +#define CYDEV_USB_ARB_RW6_RA_MSB 0x400060d7u +#define CYDEV_USB_ARB_RW6_DR 0x400060d8u +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0u +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP7_CFG 0x400060e0u +#define CYDEV_USB_ARB_EP7_INT_EN 0x400060e1u +#define CYDEV_USB_ARB_EP7_SR 0x400060e2u +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4u +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW7_WA 0x400060e4u +#define CYDEV_USB_ARB_RW7_WA_MSB 0x400060e5u +#define CYDEV_USB_ARB_RW7_RA 0x400060e6u +#define CYDEV_USB_ARB_RW7_RA_MSB 0x400060e7u +#define CYDEV_USB_ARB_RW7_DR 0x400060e8u +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0u +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP8_CFG 0x400060f0u +#define CYDEV_USB_ARB_EP8_INT_EN 0x400060f1u +#define CYDEV_USB_ARB_EP8_SR 0x400060f2u +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4u +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW8_WA 0x400060f4u +#define CYDEV_USB_ARB_RW8_WA_MSB 0x400060f5u +#define CYDEV_USB_ARB_RW8_RA 0x400060f6u +#define CYDEV_USB_ARB_RW8_RA_MSB 0x400060f7u +#define CYDEV_USB_ARB_RW8_DR 0x400060f8u +#define CYDEV_USB_MEM_BASE 0x40006100u +#define CYDEV_USB_MEM_SIZE 0x00000200u +#define CYDEV_USB_MEM_DATA_MBASE 0x40006100u +#define CYDEV_USB_MEM_DATA_MSIZE 0x00000200u +#define CYDEV_UWRK_BASE 0x40006400u +#define CYDEV_UWRK_SIZE 0x00000b60u +#define CYDEV_UWRK_UWRK8_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0u +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0u +#define CYDEV_UWRK_UWRK8_B0_UDB00_A0 0x40006400u +#define CYDEV_UWRK_UWRK8_B0_UDB01_A0 0x40006401u +#define CYDEV_UWRK_UWRK8_B0_UDB02_A0 0x40006402u +#define CYDEV_UWRK_UWRK8_B0_UDB03_A0 0x40006403u +#define CYDEV_UWRK_UWRK8_B0_UDB04_A0 0x40006404u +#define CYDEV_UWRK_UWRK8_B0_UDB05_A0 0x40006405u +#define CYDEV_UWRK_UWRK8_B0_UDB06_A0 0x40006406u +#define CYDEV_UWRK_UWRK8_B0_UDB07_A0 0x40006407u +#define CYDEV_UWRK_UWRK8_B0_UDB08_A0 0x40006408u +#define CYDEV_UWRK_UWRK8_B0_UDB09_A0 0x40006409u +#define CYDEV_UWRK_UWRK8_B0_UDB10_A0 0x4000640au +#define CYDEV_UWRK_UWRK8_B0_UDB11_A0 0x4000640bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_A0 0x4000640cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_A0 0x4000640du +#define CYDEV_UWRK_UWRK8_B0_UDB14_A0 0x4000640eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_A0 0x4000640fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_A1 0x40006410u +#define CYDEV_UWRK_UWRK8_B0_UDB01_A1 0x40006411u +#define CYDEV_UWRK_UWRK8_B0_UDB02_A1 0x40006412u +#define CYDEV_UWRK_UWRK8_B0_UDB03_A1 0x40006413u +#define CYDEV_UWRK_UWRK8_B0_UDB04_A1 0x40006414u +#define CYDEV_UWRK_UWRK8_B0_UDB05_A1 0x40006415u +#define CYDEV_UWRK_UWRK8_B0_UDB06_A1 0x40006416u +#define CYDEV_UWRK_UWRK8_B0_UDB07_A1 0x40006417u +#define CYDEV_UWRK_UWRK8_B0_UDB08_A1 0x40006418u +#define CYDEV_UWRK_UWRK8_B0_UDB09_A1 0x40006419u +#define CYDEV_UWRK_UWRK8_B0_UDB10_A1 0x4000641au +#define CYDEV_UWRK_UWRK8_B0_UDB11_A1 0x4000641bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_A1 0x4000641cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_A1 0x4000641du +#define CYDEV_UWRK_UWRK8_B0_UDB14_A1 0x4000641eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_A1 0x4000641fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_D0 0x40006420u +#define CYDEV_UWRK_UWRK8_B0_UDB01_D0 0x40006421u +#define CYDEV_UWRK_UWRK8_B0_UDB02_D0 0x40006422u +#define CYDEV_UWRK_UWRK8_B0_UDB03_D0 0x40006423u +#define CYDEV_UWRK_UWRK8_B0_UDB04_D0 0x40006424u +#define CYDEV_UWRK_UWRK8_B0_UDB05_D0 0x40006425u +#define CYDEV_UWRK_UWRK8_B0_UDB06_D0 0x40006426u +#define CYDEV_UWRK_UWRK8_B0_UDB07_D0 0x40006427u +#define CYDEV_UWRK_UWRK8_B0_UDB08_D0 0x40006428u +#define CYDEV_UWRK_UWRK8_B0_UDB09_D0 0x40006429u +#define CYDEV_UWRK_UWRK8_B0_UDB10_D0 0x4000642au +#define CYDEV_UWRK_UWRK8_B0_UDB11_D0 0x4000642bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_D0 0x4000642cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_D0 0x4000642du +#define CYDEV_UWRK_UWRK8_B0_UDB14_D0 0x4000642eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_D0 0x4000642fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_D1 0x40006430u +#define CYDEV_UWRK_UWRK8_B0_UDB01_D1 0x40006431u +#define CYDEV_UWRK_UWRK8_B0_UDB02_D1 0x40006432u +#define CYDEV_UWRK_UWRK8_B0_UDB03_D1 0x40006433u +#define CYDEV_UWRK_UWRK8_B0_UDB04_D1 0x40006434u +#define CYDEV_UWRK_UWRK8_B0_UDB05_D1 0x40006435u +#define CYDEV_UWRK_UWRK8_B0_UDB06_D1 0x40006436u +#define CYDEV_UWRK_UWRK8_B0_UDB07_D1 0x40006437u +#define CYDEV_UWRK_UWRK8_B0_UDB08_D1 0x40006438u +#define CYDEV_UWRK_UWRK8_B0_UDB09_D1 0x40006439u +#define CYDEV_UWRK_UWRK8_B0_UDB10_D1 0x4000643au +#define CYDEV_UWRK_UWRK8_B0_UDB11_D1 0x4000643bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_D1 0x4000643cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_D1 0x4000643du +#define CYDEV_UWRK_UWRK8_B0_UDB14_D1 0x4000643eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_D1 0x4000643fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_F0 0x40006440u +#define CYDEV_UWRK_UWRK8_B0_UDB01_F0 0x40006441u +#define CYDEV_UWRK_UWRK8_B0_UDB02_F0 0x40006442u +#define CYDEV_UWRK_UWRK8_B0_UDB03_F0 0x40006443u +#define CYDEV_UWRK_UWRK8_B0_UDB04_F0 0x40006444u +#define CYDEV_UWRK_UWRK8_B0_UDB05_F0 0x40006445u +#define CYDEV_UWRK_UWRK8_B0_UDB06_F0 0x40006446u +#define CYDEV_UWRK_UWRK8_B0_UDB07_F0 0x40006447u +#define CYDEV_UWRK_UWRK8_B0_UDB08_F0 0x40006448u +#define CYDEV_UWRK_UWRK8_B0_UDB09_F0 0x40006449u +#define CYDEV_UWRK_UWRK8_B0_UDB10_F0 0x4000644au +#define CYDEV_UWRK_UWRK8_B0_UDB11_F0 0x4000644bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_F0 0x4000644cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_F0 0x4000644du +#define CYDEV_UWRK_UWRK8_B0_UDB14_F0 0x4000644eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_F0 0x4000644fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_F1 0x40006450u +#define CYDEV_UWRK_UWRK8_B0_UDB01_F1 0x40006451u +#define CYDEV_UWRK_UWRK8_B0_UDB02_F1 0x40006452u +#define CYDEV_UWRK_UWRK8_B0_UDB03_F1 0x40006453u +#define CYDEV_UWRK_UWRK8_B0_UDB04_F1 0x40006454u +#define CYDEV_UWRK_UWRK8_B0_UDB05_F1 0x40006455u +#define CYDEV_UWRK_UWRK8_B0_UDB06_F1 0x40006456u +#define CYDEV_UWRK_UWRK8_B0_UDB07_F1 0x40006457u +#define CYDEV_UWRK_UWRK8_B0_UDB08_F1 0x40006458u +#define CYDEV_UWRK_UWRK8_B0_UDB09_F1 0x40006459u +#define CYDEV_UWRK_UWRK8_B0_UDB10_F1 0x4000645au +#define CYDEV_UWRK_UWRK8_B0_UDB11_F1 0x4000645bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_F1 0x4000645cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_F1 0x4000645du +#define CYDEV_UWRK_UWRK8_B0_UDB14_F1 0x4000645eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_F1 0x4000645fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_ST 0x40006460u +#define CYDEV_UWRK_UWRK8_B0_UDB01_ST 0x40006461u +#define CYDEV_UWRK_UWRK8_B0_UDB02_ST 0x40006462u +#define CYDEV_UWRK_UWRK8_B0_UDB03_ST 0x40006463u +#define CYDEV_UWRK_UWRK8_B0_UDB04_ST 0x40006464u +#define CYDEV_UWRK_UWRK8_B0_UDB05_ST 0x40006465u +#define CYDEV_UWRK_UWRK8_B0_UDB06_ST 0x40006466u +#define CYDEV_UWRK_UWRK8_B0_UDB07_ST 0x40006467u +#define CYDEV_UWRK_UWRK8_B0_UDB08_ST 0x40006468u +#define CYDEV_UWRK_UWRK8_B0_UDB09_ST 0x40006469u +#define CYDEV_UWRK_UWRK8_B0_UDB10_ST 0x4000646au +#define CYDEV_UWRK_UWRK8_B0_UDB11_ST 0x4000646bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_ST 0x4000646cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_ST 0x4000646du +#define CYDEV_UWRK_UWRK8_B0_UDB14_ST 0x4000646eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_ST 0x4000646fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_CTL 0x40006470u +#define CYDEV_UWRK_UWRK8_B0_UDB01_CTL 0x40006471u +#define CYDEV_UWRK_UWRK8_B0_UDB02_CTL 0x40006472u +#define CYDEV_UWRK_UWRK8_B0_UDB03_CTL 0x40006473u +#define CYDEV_UWRK_UWRK8_B0_UDB04_CTL 0x40006474u +#define CYDEV_UWRK_UWRK8_B0_UDB05_CTL 0x40006475u +#define CYDEV_UWRK_UWRK8_B0_UDB06_CTL 0x40006476u +#define CYDEV_UWRK_UWRK8_B0_UDB07_CTL 0x40006477u +#define CYDEV_UWRK_UWRK8_B0_UDB08_CTL 0x40006478u +#define CYDEV_UWRK_UWRK8_B0_UDB09_CTL 0x40006479u +#define CYDEV_UWRK_UWRK8_B0_UDB10_CTL 0x4000647au +#define CYDEV_UWRK_UWRK8_B0_UDB11_CTL 0x4000647bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_CTL 0x4000647cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_CTL 0x4000647du +#define CYDEV_UWRK_UWRK8_B0_UDB14_CTL 0x4000647eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_CTL 0x4000647fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_MSK 0x40006480u +#define CYDEV_UWRK_UWRK8_B0_UDB01_MSK 0x40006481u +#define CYDEV_UWRK_UWRK8_B0_UDB02_MSK 0x40006482u +#define CYDEV_UWRK_UWRK8_B0_UDB03_MSK 0x40006483u +#define CYDEV_UWRK_UWRK8_B0_UDB04_MSK 0x40006484u +#define CYDEV_UWRK_UWRK8_B0_UDB05_MSK 0x40006485u +#define CYDEV_UWRK_UWRK8_B0_UDB06_MSK 0x40006486u +#define CYDEV_UWRK_UWRK8_B0_UDB07_MSK 0x40006487u +#define CYDEV_UWRK_UWRK8_B0_UDB08_MSK 0x40006488u +#define CYDEV_UWRK_UWRK8_B0_UDB09_MSK 0x40006489u +#define CYDEV_UWRK_UWRK8_B0_UDB10_MSK 0x4000648au +#define CYDEV_UWRK_UWRK8_B0_UDB11_MSK 0x4000648bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_MSK 0x4000648cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_MSK 0x4000648du +#define CYDEV_UWRK_UWRK8_B0_UDB14_MSK 0x4000648eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_MSK 0x4000648fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_ACTL 0x40006490u +#define CYDEV_UWRK_UWRK8_B0_UDB01_ACTL 0x40006491u +#define CYDEV_UWRK_UWRK8_B0_UDB02_ACTL 0x40006492u +#define CYDEV_UWRK_UWRK8_B0_UDB03_ACTL 0x40006493u +#define CYDEV_UWRK_UWRK8_B0_UDB04_ACTL 0x40006494u +#define CYDEV_UWRK_UWRK8_B0_UDB05_ACTL 0x40006495u +#define CYDEV_UWRK_UWRK8_B0_UDB06_ACTL 0x40006496u +#define CYDEV_UWRK_UWRK8_B0_UDB07_ACTL 0x40006497u +#define CYDEV_UWRK_UWRK8_B0_UDB08_ACTL 0x40006498u +#define CYDEV_UWRK_UWRK8_B0_UDB09_ACTL 0x40006499u +#define CYDEV_UWRK_UWRK8_B0_UDB10_ACTL 0x4000649au +#define CYDEV_UWRK_UWRK8_B0_UDB11_ACTL 0x4000649bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_ACTL 0x4000649cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_ACTL 0x4000649du +#define CYDEV_UWRK_UWRK8_B0_UDB14_ACTL 0x4000649eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_ACTL 0x4000649fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_MC 0x400064a0u +#define CYDEV_UWRK_UWRK8_B0_UDB01_MC 0x400064a1u +#define CYDEV_UWRK_UWRK8_B0_UDB02_MC 0x400064a2u +#define CYDEV_UWRK_UWRK8_B0_UDB03_MC 0x400064a3u +#define CYDEV_UWRK_UWRK8_B0_UDB04_MC 0x400064a4u +#define CYDEV_UWRK_UWRK8_B0_UDB05_MC 0x400064a5u +#define CYDEV_UWRK_UWRK8_B0_UDB06_MC 0x400064a6u +#define CYDEV_UWRK_UWRK8_B0_UDB07_MC 0x400064a7u +#define CYDEV_UWRK_UWRK8_B0_UDB08_MC 0x400064a8u +#define CYDEV_UWRK_UWRK8_B0_UDB09_MC 0x400064a9u +#define CYDEV_UWRK_UWRK8_B0_UDB10_MC 0x400064aau +#define CYDEV_UWRK_UWRK8_B0_UDB11_MC 0x400064abu +#define CYDEV_UWRK_UWRK8_B0_UDB12_MC 0x400064acu +#define CYDEV_UWRK_UWRK8_B0_UDB13_MC 0x400064adu +#define CYDEV_UWRK_UWRK8_B0_UDB14_MC 0x400064aeu +#define CYDEV_UWRK_UWRK8_B0_UDB15_MC 0x400064afu +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500u +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0u +#define CYDEV_UWRK_UWRK8_B1_UDB04_A0 0x40006504u +#define CYDEV_UWRK_UWRK8_B1_UDB05_A0 0x40006505u +#define CYDEV_UWRK_UWRK8_B1_UDB06_A0 0x40006506u +#define CYDEV_UWRK_UWRK8_B1_UDB07_A0 0x40006507u +#define CYDEV_UWRK_UWRK8_B1_UDB08_A0 0x40006508u +#define CYDEV_UWRK_UWRK8_B1_UDB09_A0 0x40006509u +#define CYDEV_UWRK_UWRK8_B1_UDB10_A0 0x4000650au +#define CYDEV_UWRK_UWRK8_B1_UDB11_A0 0x4000650bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_A1 0x40006514u +#define CYDEV_UWRK_UWRK8_B1_UDB05_A1 0x40006515u +#define CYDEV_UWRK_UWRK8_B1_UDB06_A1 0x40006516u +#define CYDEV_UWRK_UWRK8_B1_UDB07_A1 0x40006517u +#define CYDEV_UWRK_UWRK8_B1_UDB08_A1 0x40006518u +#define CYDEV_UWRK_UWRK8_B1_UDB09_A1 0x40006519u +#define CYDEV_UWRK_UWRK8_B1_UDB10_A1 0x4000651au +#define CYDEV_UWRK_UWRK8_B1_UDB11_A1 0x4000651bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_D0 0x40006524u +#define CYDEV_UWRK_UWRK8_B1_UDB05_D0 0x40006525u +#define CYDEV_UWRK_UWRK8_B1_UDB06_D0 0x40006526u +#define CYDEV_UWRK_UWRK8_B1_UDB07_D0 0x40006527u +#define CYDEV_UWRK_UWRK8_B1_UDB08_D0 0x40006528u +#define CYDEV_UWRK_UWRK8_B1_UDB09_D0 0x40006529u +#define CYDEV_UWRK_UWRK8_B1_UDB10_D0 0x4000652au +#define CYDEV_UWRK_UWRK8_B1_UDB11_D0 0x4000652bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_D1 0x40006534u +#define CYDEV_UWRK_UWRK8_B1_UDB05_D1 0x40006535u +#define CYDEV_UWRK_UWRK8_B1_UDB06_D1 0x40006536u +#define CYDEV_UWRK_UWRK8_B1_UDB07_D1 0x40006537u +#define CYDEV_UWRK_UWRK8_B1_UDB08_D1 0x40006538u +#define CYDEV_UWRK_UWRK8_B1_UDB09_D1 0x40006539u +#define CYDEV_UWRK_UWRK8_B1_UDB10_D1 0x4000653au +#define CYDEV_UWRK_UWRK8_B1_UDB11_D1 0x4000653bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_F0 0x40006544u +#define CYDEV_UWRK_UWRK8_B1_UDB05_F0 0x40006545u +#define CYDEV_UWRK_UWRK8_B1_UDB06_F0 0x40006546u +#define CYDEV_UWRK_UWRK8_B1_UDB07_F0 0x40006547u +#define CYDEV_UWRK_UWRK8_B1_UDB08_F0 0x40006548u +#define CYDEV_UWRK_UWRK8_B1_UDB09_F0 0x40006549u +#define CYDEV_UWRK_UWRK8_B1_UDB10_F0 0x4000654au +#define CYDEV_UWRK_UWRK8_B1_UDB11_F0 0x4000654bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_F1 0x40006554u +#define CYDEV_UWRK_UWRK8_B1_UDB05_F1 0x40006555u +#define CYDEV_UWRK_UWRK8_B1_UDB06_F1 0x40006556u +#define CYDEV_UWRK_UWRK8_B1_UDB07_F1 0x40006557u +#define CYDEV_UWRK_UWRK8_B1_UDB08_F1 0x40006558u +#define CYDEV_UWRK_UWRK8_B1_UDB09_F1 0x40006559u +#define CYDEV_UWRK_UWRK8_B1_UDB10_F1 0x4000655au +#define CYDEV_UWRK_UWRK8_B1_UDB11_F1 0x4000655bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_ST 0x40006564u +#define CYDEV_UWRK_UWRK8_B1_UDB05_ST 0x40006565u +#define CYDEV_UWRK_UWRK8_B1_UDB06_ST 0x40006566u +#define CYDEV_UWRK_UWRK8_B1_UDB07_ST 0x40006567u +#define CYDEV_UWRK_UWRK8_B1_UDB08_ST 0x40006568u +#define CYDEV_UWRK_UWRK8_B1_UDB09_ST 0x40006569u +#define CYDEV_UWRK_UWRK8_B1_UDB10_ST 0x4000656au +#define CYDEV_UWRK_UWRK8_B1_UDB11_ST 0x4000656bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_CTL 0x40006574u +#define CYDEV_UWRK_UWRK8_B1_UDB05_CTL 0x40006575u +#define CYDEV_UWRK_UWRK8_B1_UDB06_CTL 0x40006576u +#define CYDEV_UWRK_UWRK8_B1_UDB07_CTL 0x40006577u +#define CYDEV_UWRK_UWRK8_B1_UDB08_CTL 0x40006578u +#define CYDEV_UWRK_UWRK8_B1_UDB09_CTL 0x40006579u +#define CYDEV_UWRK_UWRK8_B1_UDB10_CTL 0x4000657au +#define CYDEV_UWRK_UWRK8_B1_UDB11_CTL 0x4000657bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_MSK 0x40006584u +#define CYDEV_UWRK_UWRK8_B1_UDB05_MSK 0x40006585u +#define CYDEV_UWRK_UWRK8_B1_UDB06_MSK 0x40006586u +#define CYDEV_UWRK_UWRK8_B1_UDB07_MSK 0x40006587u +#define CYDEV_UWRK_UWRK8_B1_UDB08_MSK 0x40006588u +#define CYDEV_UWRK_UWRK8_B1_UDB09_MSK 0x40006589u +#define CYDEV_UWRK_UWRK8_B1_UDB10_MSK 0x4000658au +#define CYDEV_UWRK_UWRK8_B1_UDB11_MSK 0x4000658bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_ACTL 0x40006594u +#define CYDEV_UWRK_UWRK8_B1_UDB05_ACTL 0x40006595u +#define CYDEV_UWRK_UWRK8_B1_UDB06_ACTL 0x40006596u +#define CYDEV_UWRK_UWRK8_B1_UDB07_ACTL 0x40006597u +#define CYDEV_UWRK_UWRK8_B1_UDB08_ACTL 0x40006598u +#define CYDEV_UWRK_UWRK8_B1_UDB09_ACTL 0x40006599u +#define CYDEV_UWRK_UWRK8_B1_UDB10_ACTL 0x4000659au +#define CYDEV_UWRK_UWRK8_B1_UDB11_ACTL 0x4000659bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_MC 0x400065a4u +#define CYDEV_UWRK_UWRK8_B1_UDB05_MC 0x400065a5u +#define CYDEV_UWRK_UWRK8_B1_UDB06_MC 0x400065a6u +#define CYDEV_UWRK_UWRK8_B1_UDB07_MC 0x400065a7u +#define CYDEV_UWRK_UWRK8_B1_UDB08_MC 0x400065a8u +#define CYDEV_UWRK_UWRK8_B1_UDB09_MC 0x400065a9u +#define CYDEV_UWRK_UWRK8_B1_UDB10_MC 0x400065aau +#define CYDEV_UWRK_UWRK8_B1_UDB11_MC 0x400065abu +#define CYDEV_UWRK_UWRK16_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 0x40006802u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 0x40006804u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 0x40006806u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 0x40006808u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 0x4000680au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 0x4000680cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 0x4000680eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 0x40006810u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 0x40006812u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 0x40006814u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 0x40006816u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 0x40006818u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 0x4000681au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 0x4000681cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 0x4000681eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 0x40006840u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 0x40006842u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 0x40006844u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 0x40006846u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 0x40006848u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 0x4000684au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 0x4000684cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 0x4000684eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 0x40006850u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 0x40006852u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 0x40006854u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 0x40006856u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 0x40006858u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 0x4000685au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 0x4000685cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 0x4000685eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 0x40006880u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 0x40006882u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 0x40006884u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 0x40006886u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 0x40006888u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 0x4000688au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 0x4000688cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 0x4000688eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 0x40006890u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 0x40006892u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 0x40006894u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 0x40006896u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 0x40006898u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 0x4000689au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 0x4000689cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 0x4000689eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL 0x400068c0u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL 0x400068c2u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL 0x400068c4u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL 0x400068c6u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL 0x400068c8u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL 0x400068cau +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL 0x400068ccu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL 0x400068ceu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL 0x400068d0u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL 0x400068d2u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL 0x400068d4u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL 0x400068d6u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL 0x400068d8u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL 0x400068dau +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL 0x400068dcu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL 0x400068deu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL 0x40006900u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL 0x40006902u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL 0x40006904u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL 0x40006906u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL 0x40006908u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL 0x4000690au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL 0x4000690cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL 0x4000690eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL 0x40006910u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL 0x40006912u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL 0x40006914u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL 0x40006916u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL 0x40006918u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL 0x4000691au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL 0x4000691cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL 0x4000691eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 0x40006940u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 0x40006942u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 0x40006944u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 0x40006946u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 0x40006948u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 0x4000694au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 0x4000694cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 0x4000694eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 0x40006950u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 0x40006952u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 0x40006954u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 0x40006956u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 0x40006958u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 0x4000695au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 0x4000695cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 0x4000695eu +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 0x40006a08u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 0x40006a0au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 0x40006a0cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 0x40006a0eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 0x40006a10u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 0x40006a12u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 0x40006a14u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 0x40006a16u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 0x40006a48u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 0x40006a4au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 0x40006a4cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 0x40006a4eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 0x40006a50u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 0x40006a52u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 0x40006a54u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 0x40006a56u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 0x40006a88u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 0x40006a8au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 0x40006a8cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 0x40006a8eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 0x40006a90u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 0x40006a92u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 0x40006a94u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 0x40006a96u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL 0x40006ac8u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL 0x40006acau +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL 0x40006accu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL 0x40006aceu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL 0x40006ad0u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL 0x40006ad2u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL 0x40006ad4u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL 0x40006ad6u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL 0x40006b08u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL 0x40006b0au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL 0x40006b0cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL 0x40006b0eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL 0x40006b10u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL 0x40006b12u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL 0x40006b14u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL 0x40006b16u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 0x40006b48u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 0x40006b4au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 0x40006b4cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 0x40006b4eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 0x40006b50u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 0x40006b52u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 0x40006b54u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 0x40006b56u +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075eu +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 0x40006802u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 0x40006804u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 0x40006806u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 0x40006808u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 0x4000680au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 0x4000680cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 0x4000680eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 0x40006810u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 0x40006812u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 0x40006814u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 0x40006816u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 0x40006818u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 0x4000681au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 0x4000681cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 0x40006820u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 0x40006822u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 0x40006824u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 0x40006826u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 0x40006828u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 0x4000682au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 0x4000682cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 0x4000682eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 0x40006830u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 0x40006832u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 0x40006834u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 0x40006836u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 0x40006838u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 0x4000683au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 0x4000683cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 0x40006840u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 0x40006842u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 0x40006844u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 0x40006846u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 0x40006848u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 0x4000684au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 0x4000684cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 0x4000684eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 0x40006850u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 0x40006852u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 0x40006854u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 0x40006856u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 0x40006858u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 0x4000685au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 0x4000685cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 0x40006860u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 0x40006862u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 0x40006864u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 0x40006866u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 0x40006868u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 0x4000686au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 0x4000686cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 0x4000686eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 0x40006870u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 0x40006872u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 0x40006874u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 0x40006876u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 0x40006878u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 0x4000687au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 0x4000687cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 0x40006880u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 0x40006882u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 0x40006884u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 0x40006886u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 0x40006888u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 0x4000688au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 0x4000688cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 0x4000688eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 0x40006890u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 0x40006892u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 0x40006894u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 0x40006896u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 0x40006898u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 0x4000689au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 0x4000689cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 0x400068a0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 0x400068a2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 0x400068a4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 0x400068a6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 0x400068a8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 0x400068aau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 0x400068acu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 0x400068aeu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 0x400068b0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 0x400068b2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 0x400068b4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 0x400068b6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 0x400068b8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 0x400068bau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 0x400068bcu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST 0x400068c0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST 0x400068c2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST 0x400068c4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST 0x400068c6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST 0x400068c8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST 0x400068cau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST 0x400068ccu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST 0x400068ceu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST 0x400068d0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST 0x400068d2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST 0x400068d4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST 0x400068d6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST 0x400068d8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST 0x400068dau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST 0x400068dcu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL 0x400068e0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL 0x400068e2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL 0x400068e4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL 0x400068e6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL 0x400068e8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL 0x400068eau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL 0x400068ecu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL 0x400068eeu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL 0x400068f0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL 0x400068f2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL 0x400068f4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL 0x400068f6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL 0x400068f8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL 0x400068fau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL 0x400068fcu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK 0x40006900u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK 0x40006902u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK 0x40006904u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK 0x40006906u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK 0x40006908u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK 0x4000690au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK 0x4000690cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK 0x4000690eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK 0x40006910u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK 0x40006912u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK 0x40006914u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK 0x40006916u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK 0x40006918u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK 0x4000691au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK 0x4000691cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL 0x40006920u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL 0x40006922u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL 0x40006924u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL 0x40006926u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL 0x40006928u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL 0x4000692au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL 0x4000692cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL 0x4000692eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL 0x40006930u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL 0x40006932u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL 0x40006934u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL 0x40006936u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL 0x40006938u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL 0x4000693au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL 0x4000693cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC 0x40006940u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC 0x40006942u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC 0x40006944u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC 0x40006946u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC 0x40006948u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC 0x4000694au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC 0x4000694cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC 0x4000694eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC 0x40006950u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC 0x40006952u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC 0x40006954u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC 0x40006956u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC 0x40006958u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC 0x4000695au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC 0x4000695cu +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 0x40006a08u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 0x40006a0au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 0x40006a0cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 0x40006a0eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 0x40006a10u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 0x40006a12u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 0x40006a14u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 0x40006a16u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 0x40006a28u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 0x40006a2au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 0x40006a2cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 0x40006a2eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 0x40006a30u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 0x40006a32u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 0x40006a34u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 0x40006a36u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 0x40006a48u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 0x40006a4au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 0x40006a4cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 0x40006a4eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 0x40006a50u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 0x40006a52u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 0x40006a54u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 0x40006a56u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 0x40006a68u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 0x40006a6au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 0x40006a6cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 0x40006a6eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 0x40006a70u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 0x40006a72u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 0x40006a74u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 0x40006a76u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 0x40006a88u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 0x40006a8au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 0x40006a8cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 0x40006a8eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 0x40006a90u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 0x40006a92u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 0x40006a94u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 0x40006a96u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 0x40006aa8u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 0x40006aaau +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 0x40006aacu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 0x40006aaeu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 0x40006ab0u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 0x40006ab2u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 0x40006ab4u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 0x40006ab6u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST 0x40006ac8u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST 0x40006acau +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST 0x40006accu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST 0x40006aceu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST 0x40006ad0u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST 0x40006ad2u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST 0x40006ad4u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST 0x40006ad6u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL 0x40006ae8u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL 0x40006aeau +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL 0x40006aecu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL 0x40006aeeu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL 0x40006af0u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL 0x40006af2u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL 0x40006af4u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL 0x40006af6u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK 0x40006b08u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK 0x40006b0au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK 0x40006b0cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK 0x40006b0eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK 0x40006b10u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK 0x40006b12u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK 0x40006b14u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK 0x40006b16u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL 0x40006b28u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL 0x40006b2au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL 0x40006b2cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL 0x40006b2eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL 0x40006b30u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL 0x40006b32u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL 0x40006b34u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL 0x40006b36u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC 0x40006b48u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC 0x40006b4au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC 0x40006b4cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC 0x40006b4eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC 0x40006b50u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC 0x40006b52u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC 0x40006b54u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC 0x40006b56u +#define CYDEV_PHUB_BASE 0x40007000u +#define CYDEV_PHUB_SIZE 0x00000c00u +#define CYDEV_PHUB_CFG 0x40007000u +#define CYDEV_PHUB_ERR 0x40007004u +#define CYDEV_PHUB_ERR_ADR 0x40007008u +#define CYDEV_PHUB_CH0_BASE 0x40007010u +#define CYDEV_PHUB_CH0_SIZE 0x0000000cu +#define CYDEV_PHUB_CH0_BASIC_CFG 0x40007010u +#define CYDEV_PHUB_CH0_ACTION 0x40007014u +#define CYDEV_PHUB_CH0_BASIC_STATUS 0x40007018u +#define CYDEV_PHUB_CH1_BASE 0x40007020u +#define CYDEV_PHUB_CH1_SIZE 0x0000000cu +#define CYDEV_PHUB_CH1_BASIC_CFG 0x40007020u +#define CYDEV_PHUB_CH1_ACTION 0x40007024u +#define CYDEV_PHUB_CH1_BASIC_STATUS 0x40007028u +#define CYDEV_PHUB_CH2_BASE 0x40007030u +#define CYDEV_PHUB_CH2_SIZE 0x0000000cu +#define CYDEV_PHUB_CH2_BASIC_CFG 0x40007030u +#define CYDEV_PHUB_CH2_ACTION 0x40007034u +#define CYDEV_PHUB_CH2_BASIC_STATUS 0x40007038u +#define CYDEV_PHUB_CH3_BASE 0x40007040u +#define CYDEV_PHUB_CH3_SIZE 0x0000000cu +#define CYDEV_PHUB_CH3_BASIC_CFG 0x40007040u +#define CYDEV_PHUB_CH3_ACTION 0x40007044u +#define CYDEV_PHUB_CH3_BASIC_STATUS 0x40007048u +#define CYDEV_PHUB_CH4_BASE 0x40007050u +#define CYDEV_PHUB_CH4_SIZE 0x0000000cu +#define CYDEV_PHUB_CH4_BASIC_CFG 0x40007050u +#define CYDEV_PHUB_CH4_ACTION 0x40007054u +#define CYDEV_PHUB_CH4_BASIC_STATUS 0x40007058u +#define CYDEV_PHUB_CH5_BASE 0x40007060u +#define CYDEV_PHUB_CH5_SIZE 0x0000000cu +#define CYDEV_PHUB_CH5_BASIC_CFG 0x40007060u +#define CYDEV_PHUB_CH5_ACTION 0x40007064u +#define CYDEV_PHUB_CH5_BASIC_STATUS 0x40007068u +#define CYDEV_PHUB_CH6_BASE 0x40007070u +#define CYDEV_PHUB_CH6_SIZE 0x0000000cu +#define CYDEV_PHUB_CH6_BASIC_CFG 0x40007070u +#define CYDEV_PHUB_CH6_ACTION 0x40007074u +#define CYDEV_PHUB_CH6_BASIC_STATUS 0x40007078u +#define CYDEV_PHUB_CH7_BASE 0x40007080u +#define CYDEV_PHUB_CH7_SIZE 0x0000000cu +#define CYDEV_PHUB_CH7_BASIC_CFG 0x40007080u +#define CYDEV_PHUB_CH7_ACTION 0x40007084u +#define CYDEV_PHUB_CH7_BASIC_STATUS 0x40007088u +#define CYDEV_PHUB_CH8_BASE 0x40007090u +#define CYDEV_PHUB_CH8_SIZE 0x0000000cu +#define CYDEV_PHUB_CH8_BASIC_CFG 0x40007090u +#define CYDEV_PHUB_CH8_ACTION 0x40007094u +#define CYDEV_PHUB_CH8_BASIC_STATUS 0x40007098u +#define CYDEV_PHUB_CH9_BASE 0x400070a0u +#define CYDEV_PHUB_CH9_SIZE 0x0000000cu +#define CYDEV_PHUB_CH9_BASIC_CFG 0x400070a0u +#define CYDEV_PHUB_CH9_ACTION 0x400070a4u +#define CYDEV_PHUB_CH9_BASIC_STATUS 0x400070a8u +#define CYDEV_PHUB_CH10_BASE 0x400070b0u +#define CYDEV_PHUB_CH10_SIZE 0x0000000cu +#define CYDEV_PHUB_CH10_BASIC_CFG 0x400070b0u +#define CYDEV_PHUB_CH10_ACTION 0x400070b4u +#define CYDEV_PHUB_CH10_BASIC_STATUS 0x400070b8u +#define CYDEV_PHUB_CH11_BASE 0x400070c0u +#define CYDEV_PHUB_CH11_SIZE 0x0000000cu +#define CYDEV_PHUB_CH11_BASIC_CFG 0x400070c0u +#define CYDEV_PHUB_CH11_ACTION 0x400070c4u +#define CYDEV_PHUB_CH11_BASIC_STATUS 0x400070c8u +#define CYDEV_PHUB_CH12_BASE 0x400070d0u +#define CYDEV_PHUB_CH12_SIZE 0x0000000cu +#define CYDEV_PHUB_CH12_BASIC_CFG 0x400070d0u +#define CYDEV_PHUB_CH12_ACTION 0x400070d4u +#define CYDEV_PHUB_CH12_BASIC_STATUS 0x400070d8u +#define CYDEV_PHUB_CH13_BASE 0x400070e0u +#define CYDEV_PHUB_CH13_SIZE 0x0000000cu +#define CYDEV_PHUB_CH13_BASIC_CFG 0x400070e0u +#define CYDEV_PHUB_CH13_ACTION 0x400070e4u +#define CYDEV_PHUB_CH13_BASIC_STATUS 0x400070e8u +#define CYDEV_PHUB_CH14_BASE 0x400070f0u +#define CYDEV_PHUB_CH14_SIZE 0x0000000cu +#define CYDEV_PHUB_CH14_BASIC_CFG 0x400070f0u +#define CYDEV_PHUB_CH14_ACTION 0x400070f4u +#define CYDEV_PHUB_CH14_BASIC_STATUS 0x400070f8u +#define CYDEV_PHUB_CH15_BASE 0x40007100u +#define CYDEV_PHUB_CH15_SIZE 0x0000000cu +#define CYDEV_PHUB_CH15_BASIC_CFG 0x40007100u +#define CYDEV_PHUB_CH15_ACTION 0x40007104u +#define CYDEV_PHUB_CH15_BASIC_STATUS 0x40007108u +#define CYDEV_PHUB_CH16_BASE 0x40007110u +#define CYDEV_PHUB_CH16_SIZE 0x0000000cu +#define CYDEV_PHUB_CH16_BASIC_CFG 0x40007110u +#define CYDEV_PHUB_CH16_ACTION 0x40007114u +#define CYDEV_PHUB_CH16_BASIC_STATUS 0x40007118u +#define CYDEV_PHUB_CH17_BASE 0x40007120u +#define CYDEV_PHUB_CH17_SIZE 0x0000000cu +#define CYDEV_PHUB_CH17_BASIC_CFG 0x40007120u +#define CYDEV_PHUB_CH17_ACTION 0x40007124u +#define CYDEV_PHUB_CH17_BASIC_STATUS 0x40007128u +#define CYDEV_PHUB_CH18_BASE 0x40007130u +#define CYDEV_PHUB_CH18_SIZE 0x0000000cu +#define CYDEV_PHUB_CH18_BASIC_CFG 0x40007130u +#define CYDEV_PHUB_CH18_ACTION 0x40007134u +#define CYDEV_PHUB_CH18_BASIC_STATUS 0x40007138u +#define CYDEV_PHUB_CH19_BASE 0x40007140u +#define CYDEV_PHUB_CH19_SIZE 0x0000000cu +#define CYDEV_PHUB_CH19_BASIC_CFG 0x40007140u +#define CYDEV_PHUB_CH19_ACTION 0x40007144u +#define CYDEV_PHUB_CH19_BASIC_STATUS 0x40007148u +#define CYDEV_PHUB_CH20_BASE 0x40007150u +#define CYDEV_PHUB_CH20_SIZE 0x0000000cu +#define CYDEV_PHUB_CH20_BASIC_CFG 0x40007150u +#define CYDEV_PHUB_CH20_ACTION 0x40007154u +#define CYDEV_PHUB_CH20_BASIC_STATUS 0x40007158u +#define CYDEV_PHUB_CH21_BASE 0x40007160u +#define CYDEV_PHUB_CH21_SIZE 0x0000000cu +#define CYDEV_PHUB_CH21_BASIC_CFG 0x40007160u +#define CYDEV_PHUB_CH21_ACTION 0x40007164u +#define CYDEV_PHUB_CH21_BASIC_STATUS 0x40007168u +#define CYDEV_PHUB_CH22_BASE 0x40007170u +#define CYDEV_PHUB_CH22_SIZE 0x0000000cu +#define CYDEV_PHUB_CH22_BASIC_CFG 0x40007170u +#define CYDEV_PHUB_CH22_ACTION 0x40007174u +#define CYDEV_PHUB_CH22_BASIC_STATUS 0x40007178u +#define CYDEV_PHUB_CH23_BASE 0x40007180u +#define CYDEV_PHUB_CH23_SIZE 0x0000000cu +#define CYDEV_PHUB_CH23_BASIC_CFG 0x40007180u +#define CYDEV_PHUB_CH23_ACTION 0x40007184u +#define CYDEV_PHUB_CH23_BASIC_STATUS 0x40007188u +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600u +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM0_CFG0 0x40007600u +#define CYDEV_PHUB_CFGMEM0_CFG1 0x40007604u +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608u +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM1_CFG0 0x40007608u +#define CYDEV_PHUB_CFGMEM1_CFG1 0x4000760cu +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610u +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM2_CFG0 0x40007610u +#define CYDEV_PHUB_CFGMEM2_CFG1 0x40007614u +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618u +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM3_CFG0 0x40007618u +#define CYDEV_PHUB_CFGMEM3_CFG1 0x4000761cu +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620u +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM4_CFG0 0x40007620u +#define CYDEV_PHUB_CFGMEM4_CFG1 0x40007624u +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628u +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM5_CFG0 0x40007628u +#define CYDEV_PHUB_CFGMEM5_CFG1 0x4000762cu +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630u +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM6_CFG0 0x40007630u +#define CYDEV_PHUB_CFGMEM6_CFG1 0x40007634u +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638u +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM7_CFG0 0x40007638u +#define CYDEV_PHUB_CFGMEM7_CFG1 0x4000763cu +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640u +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM8_CFG0 0x40007640u +#define CYDEV_PHUB_CFGMEM8_CFG1 0x40007644u +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648u +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM9_CFG0 0x40007648u +#define CYDEV_PHUB_CFGMEM9_CFG1 0x4000764cu +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650u +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM10_CFG0 0x40007650u +#define CYDEV_PHUB_CFGMEM10_CFG1 0x40007654u +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658u +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM11_CFG0 0x40007658u +#define CYDEV_PHUB_CFGMEM11_CFG1 0x4000765cu +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660u +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM12_CFG0 0x40007660u +#define CYDEV_PHUB_CFGMEM12_CFG1 0x40007664u +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668u +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM13_CFG0 0x40007668u +#define CYDEV_PHUB_CFGMEM13_CFG1 0x4000766cu +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670u +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM14_CFG0 0x40007670u +#define CYDEV_PHUB_CFGMEM14_CFG1 0x40007674u +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678u +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM15_CFG0 0x40007678u +#define CYDEV_PHUB_CFGMEM15_CFG1 0x4000767cu +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680u +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM16_CFG0 0x40007680u +#define CYDEV_PHUB_CFGMEM16_CFG1 0x40007684u +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688u +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM17_CFG0 0x40007688u +#define CYDEV_PHUB_CFGMEM17_CFG1 0x4000768cu +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690u +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM18_CFG0 0x40007690u +#define CYDEV_PHUB_CFGMEM18_CFG1 0x40007694u +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698u +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM19_CFG0 0x40007698u +#define CYDEV_PHUB_CFGMEM19_CFG1 0x4000769cu +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0u +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM20_CFG0 0x400076a0u +#define CYDEV_PHUB_CFGMEM20_CFG1 0x400076a4u +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8u +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM21_CFG0 0x400076a8u +#define CYDEV_PHUB_CFGMEM21_CFG1 0x400076acu +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0u +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM22_CFG0 0x400076b0u +#define CYDEV_PHUB_CFGMEM22_CFG1 0x400076b4u +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8u +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM23_CFG0 0x400076b8u +#define CYDEV_PHUB_CFGMEM23_CFG1 0x400076bcu +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800u +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM0_ORIG_TD0 0x40007800u +#define CYDEV_PHUB_TDMEM0_ORIG_TD1 0x40007804u +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808u +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM1_ORIG_TD0 0x40007808u +#define CYDEV_PHUB_TDMEM1_ORIG_TD1 0x4000780cu +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810u +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM2_ORIG_TD0 0x40007810u +#define CYDEV_PHUB_TDMEM2_ORIG_TD1 0x40007814u +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818u +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM3_ORIG_TD0 0x40007818u +#define CYDEV_PHUB_TDMEM3_ORIG_TD1 0x4000781cu +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820u +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM4_ORIG_TD0 0x40007820u +#define CYDEV_PHUB_TDMEM4_ORIG_TD1 0x40007824u +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828u +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM5_ORIG_TD0 0x40007828u +#define CYDEV_PHUB_TDMEM5_ORIG_TD1 0x4000782cu +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830u +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM6_ORIG_TD0 0x40007830u +#define CYDEV_PHUB_TDMEM6_ORIG_TD1 0x40007834u +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838u +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM7_ORIG_TD0 0x40007838u +#define CYDEV_PHUB_TDMEM7_ORIG_TD1 0x4000783cu +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840u +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM8_ORIG_TD0 0x40007840u +#define CYDEV_PHUB_TDMEM8_ORIG_TD1 0x40007844u +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848u +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM9_ORIG_TD0 0x40007848u +#define CYDEV_PHUB_TDMEM9_ORIG_TD1 0x4000784cu +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850u +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM10_ORIG_TD0 0x40007850u +#define CYDEV_PHUB_TDMEM10_ORIG_TD1 0x40007854u +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858u +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM11_ORIG_TD0 0x40007858u +#define CYDEV_PHUB_TDMEM11_ORIG_TD1 0x4000785cu +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860u +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM12_ORIG_TD0 0x40007860u +#define CYDEV_PHUB_TDMEM12_ORIG_TD1 0x40007864u +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868u +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM13_ORIG_TD0 0x40007868u +#define CYDEV_PHUB_TDMEM13_ORIG_TD1 0x4000786cu +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870u +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM14_ORIG_TD0 0x40007870u +#define CYDEV_PHUB_TDMEM14_ORIG_TD1 0x40007874u +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878u +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM15_ORIG_TD0 0x40007878u +#define CYDEV_PHUB_TDMEM15_ORIG_TD1 0x4000787cu +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880u +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM16_ORIG_TD0 0x40007880u +#define CYDEV_PHUB_TDMEM16_ORIG_TD1 0x40007884u +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888u +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM17_ORIG_TD0 0x40007888u +#define CYDEV_PHUB_TDMEM17_ORIG_TD1 0x4000788cu +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890u +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM18_ORIG_TD0 0x40007890u +#define CYDEV_PHUB_TDMEM18_ORIG_TD1 0x40007894u +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898u +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM19_ORIG_TD0 0x40007898u +#define CYDEV_PHUB_TDMEM19_ORIG_TD1 0x4000789cu +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0u +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM20_ORIG_TD0 0x400078a0u +#define CYDEV_PHUB_TDMEM20_ORIG_TD1 0x400078a4u +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8u +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM21_ORIG_TD0 0x400078a8u +#define CYDEV_PHUB_TDMEM21_ORIG_TD1 0x400078acu +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0u +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM22_ORIG_TD0 0x400078b0u +#define CYDEV_PHUB_TDMEM22_ORIG_TD1 0x400078b4u +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8u +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM23_ORIG_TD0 0x400078b8u +#define CYDEV_PHUB_TDMEM23_ORIG_TD1 0x400078bcu +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0u +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM24_ORIG_TD0 0x400078c0u +#define CYDEV_PHUB_TDMEM24_ORIG_TD1 0x400078c4u +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8u +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM25_ORIG_TD0 0x400078c8u +#define CYDEV_PHUB_TDMEM25_ORIG_TD1 0x400078ccu +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0u +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM26_ORIG_TD0 0x400078d0u +#define CYDEV_PHUB_TDMEM26_ORIG_TD1 0x400078d4u +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8u +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM27_ORIG_TD0 0x400078d8u +#define CYDEV_PHUB_TDMEM27_ORIG_TD1 0x400078dcu +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0u +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM28_ORIG_TD0 0x400078e0u +#define CYDEV_PHUB_TDMEM28_ORIG_TD1 0x400078e4u +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8u +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM29_ORIG_TD0 0x400078e8u +#define CYDEV_PHUB_TDMEM29_ORIG_TD1 0x400078ecu +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0u +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM30_ORIG_TD0 0x400078f0u +#define CYDEV_PHUB_TDMEM30_ORIG_TD1 0x400078f4u +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8u +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM31_ORIG_TD0 0x400078f8u +#define CYDEV_PHUB_TDMEM31_ORIG_TD1 0x400078fcu +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900u +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM32_ORIG_TD0 0x40007900u +#define CYDEV_PHUB_TDMEM32_ORIG_TD1 0x40007904u +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908u +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM33_ORIG_TD0 0x40007908u +#define CYDEV_PHUB_TDMEM33_ORIG_TD1 0x4000790cu +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910u +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM34_ORIG_TD0 0x40007910u +#define CYDEV_PHUB_TDMEM34_ORIG_TD1 0x40007914u +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918u +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM35_ORIG_TD0 0x40007918u +#define CYDEV_PHUB_TDMEM35_ORIG_TD1 0x4000791cu +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920u +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM36_ORIG_TD0 0x40007920u +#define CYDEV_PHUB_TDMEM36_ORIG_TD1 0x40007924u +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928u +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM37_ORIG_TD0 0x40007928u +#define CYDEV_PHUB_TDMEM37_ORIG_TD1 0x4000792cu +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930u +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM38_ORIG_TD0 0x40007930u +#define CYDEV_PHUB_TDMEM38_ORIG_TD1 0x40007934u +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938u +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM39_ORIG_TD0 0x40007938u +#define CYDEV_PHUB_TDMEM39_ORIG_TD1 0x4000793cu +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940u +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM40_ORIG_TD0 0x40007940u +#define CYDEV_PHUB_TDMEM40_ORIG_TD1 0x40007944u +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948u +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM41_ORIG_TD0 0x40007948u +#define CYDEV_PHUB_TDMEM41_ORIG_TD1 0x4000794cu +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950u +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM42_ORIG_TD0 0x40007950u +#define CYDEV_PHUB_TDMEM42_ORIG_TD1 0x40007954u +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958u +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM43_ORIG_TD0 0x40007958u +#define CYDEV_PHUB_TDMEM43_ORIG_TD1 0x4000795cu +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960u +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM44_ORIG_TD0 0x40007960u +#define CYDEV_PHUB_TDMEM44_ORIG_TD1 0x40007964u +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968u +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM45_ORIG_TD0 0x40007968u +#define CYDEV_PHUB_TDMEM45_ORIG_TD1 0x4000796cu +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970u +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM46_ORIG_TD0 0x40007970u +#define CYDEV_PHUB_TDMEM46_ORIG_TD1 0x40007974u +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978u +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM47_ORIG_TD0 0x40007978u +#define CYDEV_PHUB_TDMEM47_ORIG_TD1 0x4000797cu +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980u +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM48_ORIG_TD0 0x40007980u +#define CYDEV_PHUB_TDMEM48_ORIG_TD1 0x40007984u +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988u +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM49_ORIG_TD0 0x40007988u +#define CYDEV_PHUB_TDMEM49_ORIG_TD1 0x4000798cu +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990u +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM50_ORIG_TD0 0x40007990u +#define CYDEV_PHUB_TDMEM50_ORIG_TD1 0x40007994u +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998u +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM51_ORIG_TD0 0x40007998u +#define CYDEV_PHUB_TDMEM51_ORIG_TD1 0x4000799cu +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0u +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM52_ORIG_TD0 0x400079a0u +#define CYDEV_PHUB_TDMEM52_ORIG_TD1 0x400079a4u +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8u +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM53_ORIG_TD0 0x400079a8u +#define CYDEV_PHUB_TDMEM53_ORIG_TD1 0x400079acu +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0u +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM54_ORIG_TD0 0x400079b0u +#define CYDEV_PHUB_TDMEM54_ORIG_TD1 0x400079b4u +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8u +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM55_ORIG_TD0 0x400079b8u +#define CYDEV_PHUB_TDMEM55_ORIG_TD1 0x400079bcu +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0u +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM56_ORIG_TD0 0x400079c0u +#define CYDEV_PHUB_TDMEM56_ORIG_TD1 0x400079c4u +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8u +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM57_ORIG_TD0 0x400079c8u +#define CYDEV_PHUB_TDMEM57_ORIG_TD1 0x400079ccu +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0u +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM58_ORIG_TD0 0x400079d0u +#define CYDEV_PHUB_TDMEM58_ORIG_TD1 0x400079d4u +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8u +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM59_ORIG_TD0 0x400079d8u +#define CYDEV_PHUB_TDMEM59_ORIG_TD1 0x400079dcu +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0u +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM60_ORIG_TD0 0x400079e0u +#define CYDEV_PHUB_TDMEM60_ORIG_TD1 0x400079e4u +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8u +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM61_ORIG_TD0 0x400079e8u +#define CYDEV_PHUB_TDMEM61_ORIG_TD1 0x400079ecu +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0u +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM62_ORIG_TD0 0x400079f0u +#define CYDEV_PHUB_TDMEM62_ORIG_TD1 0x400079f4u +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8u +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM63_ORIG_TD0 0x400079f8u +#define CYDEV_PHUB_TDMEM63_ORIG_TD1 0x400079fcu +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00u +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM64_ORIG_TD0 0x40007a00u +#define CYDEV_PHUB_TDMEM64_ORIG_TD1 0x40007a04u +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08u +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM65_ORIG_TD0 0x40007a08u +#define CYDEV_PHUB_TDMEM65_ORIG_TD1 0x40007a0cu +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10u +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM66_ORIG_TD0 0x40007a10u +#define CYDEV_PHUB_TDMEM66_ORIG_TD1 0x40007a14u +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18u +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM67_ORIG_TD0 0x40007a18u +#define CYDEV_PHUB_TDMEM67_ORIG_TD1 0x40007a1cu +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20u +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM68_ORIG_TD0 0x40007a20u +#define CYDEV_PHUB_TDMEM68_ORIG_TD1 0x40007a24u +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28u +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM69_ORIG_TD0 0x40007a28u +#define CYDEV_PHUB_TDMEM69_ORIG_TD1 0x40007a2cu +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30u +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM70_ORIG_TD0 0x40007a30u +#define CYDEV_PHUB_TDMEM70_ORIG_TD1 0x40007a34u +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38u +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM71_ORIG_TD0 0x40007a38u +#define CYDEV_PHUB_TDMEM71_ORIG_TD1 0x40007a3cu +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40u +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM72_ORIG_TD0 0x40007a40u +#define CYDEV_PHUB_TDMEM72_ORIG_TD1 0x40007a44u +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48u +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM73_ORIG_TD0 0x40007a48u +#define CYDEV_PHUB_TDMEM73_ORIG_TD1 0x40007a4cu +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50u +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM74_ORIG_TD0 0x40007a50u +#define CYDEV_PHUB_TDMEM74_ORIG_TD1 0x40007a54u +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58u +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM75_ORIG_TD0 0x40007a58u +#define CYDEV_PHUB_TDMEM75_ORIG_TD1 0x40007a5cu +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60u +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM76_ORIG_TD0 0x40007a60u +#define CYDEV_PHUB_TDMEM76_ORIG_TD1 0x40007a64u +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68u +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM77_ORIG_TD0 0x40007a68u +#define CYDEV_PHUB_TDMEM77_ORIG_TD1 0x40007a6cu +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70u +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM78_ORIG_TD0 0x40007a70u +#define CYDEV_PHUB_TDMEM78_ORIG_TD1 0x40007a74u +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78u +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM79_ORIG_TD0 0x40007a78u +#define CYDEV_PHUB_TDMEM79_ORIG_TD1 0x40007a7cu +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80u +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM80_ORIG_TD0 0x40007a80u +#define CYDEV_PHUB_TDMEM80_ORIG_TD1 0x40007a84u +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88u +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM81_ORIG_TD0 0x40007a88u +#define CYDEV_PHUB_TDMEM81_ORIG_TD1 0x40007a8cu +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90u +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM82_ORIG_TD0 0x40007a90u +#define CYDEV_PHUB_TDMEM82_ORIG_TD1 0x40007a94u +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98u +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM83_ORIG_TD0 0x40007a98u +#define CYDEV_PHUB_TDMEM83_ORIG_TD1 0x40007a9cu +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0u +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM84_ORIG_TD0 0x40007aa0u +#define CYDEV_PHUB_TDMEM84_ORIG_TD1 0x40007aa4u +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8u +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM85_ORIG_TD0 0x40007aa8u +#define CYDEV_PHUB_TDMEM85_ORIG_TD1 0x40007aacu +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0u +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM86_ORIG_TD0 0x40007ab0u +#define CYDEV_PHUB_TDMEM86_ORIG_TD1 0x40007ab4u +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8u +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM87_ORIG_TD0 0x40007ab8u +#define CYDEV_PHUB_TDMEM87_ORIG_TD1 0x40007abcu +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0u +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM88_ORIG_TD0 0x40007ac0u +#define CYDEV_PHUB_TDMEM88_ORIG_TD1 0x40007ac4u +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8u +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM89_ORIG_TD0 0x40007ac8u +#define CYDEV_PHUB_TDMEM89_ORIG_TD1 0x40007accu +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0u +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM90_ORIG_TD0 0x40007ad0u +#define CYDEV_PHUB_TDMEM90_ORIG_TD1 0x40007ad4u +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8u +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM91_ORIG_TD0 0x40007ad8u +#define CYDEV_PHUB_TDMEM91_ORIG_TD1 0x40007adcu +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0u +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM92_ORIG_TD0 0x40007ae0u +#define CYDEV_PHUB_TDMEM92_ORIG_TD1 0x40007ae4u +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8u +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM93_ORIG_TD0 0x40007ae8u +#define CYDEV_PHUB_TDMEM93_ORIG_TD1 0x40007aecu +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0u +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM94_ORIG_TD0 0x40007af0u +#define CYDEV_PHUB_TDMEM94_ORIG_TD1 0x40007af4u +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8u +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM95_ORIG_TD0 0x40007af8u +#define CYDEV_PHUB_TDMEM95_ORIG_TD1 0x40007afcu +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00u +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM96_ORIG_TD0 0x40007b00u +#define CYDEV_PHUB_TDMEM96_ORIG_TD1 0x40007b04u +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08u +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM97_ORIG_TD0 0x40007b08u +#define CYDEV_PHUB_TDMEM97_ORIG_TD1 0x40007b0cu +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10u +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM98_ORIG_TD0 0x40007b10u +#define CYDEV_PHUB_TDMEM98_ORIG_TD1 0x40007b14u +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18u +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM99_ORIG_TD0 0x40007b18u +#define CYDEV_PHUB_TDMEM99_ORIG_TD1 0x40007b1cu +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20u +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM100_ORIG_TD0 0x40007b20u +#define CYDEV_PHUB_TDMEM100_ORIG_TD1 0x40007b24u +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28u +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM101_ORIG_TD0 0x40007b28u +#define CYDEV_PHUB_TDMEM101_ORIG_TD1 0x40007b2cu +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30u +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM102_ORIG_TD0 0x40007b30u +#define CYDEV_PHUB_TDMEM102_ORIG_TD1 0x40007b34u +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38u +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM103_ORIG_TD0 0x40007b38u +#define CYDEV_PHUB_TDMEM103_ORIG_TD1 0x40007b3cu +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40u +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM104_ORIG_TD0 0x40007b40u +#define CYDEV_PHUB_TDMEM104_ORIG_TD1 0x40007b44u +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48u +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM105_ORIG_TD0 0x40007b48u +#define CYDEV_PHUB_TDMEM105_ORIG_TD1 0x40007b4cu +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50u +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM106_ORIG_TD0 0x40007b50u +#define CYDEV_PHUB_TDMEM106_ORIG_TD1 0x40007b54u +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58u +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM107_ORIG_TD0 0x40007b58u +#define CYDEV_PHUB_TDMEM107_ORIG_TD1 0x40007b5cu +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60u +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM108_ORIG_TD0 0x40007b60u +#define CYDEV_PHUB_TDMEM108_ORIG_TD1 0x40007b64u +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68u +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM109_ORIG_TD0 0x40007b68u +#define CYDEV_PHUB_TDMEM109_ORIG_TD1 0x40007b6cu +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70u +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM110_ORIG_TD0 0x40007b70u +#define CYDEV_PHUB_TDMEM110_ORIG_TD1 0x40007b74u +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78u +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM111_ORIG_TD0 0x40007b78u +#define CYDEV_PHUB_TDMEM111_ORIG_TD1 0x40007b7cu +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80u +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM112_ORIG_TD0 0x40007b80u +#define CYDEV_PHUB_TDMEM112_ORIG_TD1 0x40007b84u +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88u +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM113_ORIG_TD0 0x40007b88u +#define CYDEV_PHUB_TDMEM113_ORIG_TD1 0x40007b8cu +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90u +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM114_ORIG_TD0 0x40007b90u +#define CYDEV_PHUB_TDMEM114_ORIG_TD1 0x40007b94u +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98u +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM115_ORIG_TD0 0x40007b98u +#define CYDEV_PHUB_TDMEM115_ORIG_TD1 0x40007b9cu +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0u +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM116_ORIG_TD0 0x40007ba0u +#define CYDEV_PHUB_TDMEM116_ORIG_TD1 0x40007ba4u +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8u +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM117_ORIG_TD0 0x40007ba8u +#define CYDEV_PHUB_TDMEM117_ORIG_TD1 0x40007bacu +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0u +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM118_ORIG_TD0 0x40007bb0u +#define CYDEV_PHUB_TDMEM118_ORIG_TD1 0x40007bb4u +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8u +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM119_ORIG_TD0 0x40007bb8u +#define CYDEV_PHUB_TDMEM119_ORIG_TD1 0x40007bbcu +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0u +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM120_ORIG_TD0 0x40007bc0u +#define CYDEV_PHUB_TDMEM120_ORIG_TD1 0x40007bc4u +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8u +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM121_ORIG_TD0 0x40007bc8u +#define CYDEV_PHUB_TDMEM121_ORIG_TD1 0x40007bccu +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0u +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM122_ORIG_TD0 0x40007bd0u +#define CYDEV_PHUB_TDMEM122_ORIG_TD1 0x40007bd4u +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8u +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM123_ORIG_TD0 0x40007bd8u +#define CYDEV_PHUB_TDMEM123_ORIG_TD1 0x40007bdcu +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0u +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM124_ORIG_TD0 0x40007be0u +#define CYDEV_PHUB_TDMEM124_ORIG_TD1 0x40007be4u +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8u +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM125_ORIG_TD0 0x40007be8u +#define CYDEV_PHUB_TDMEM125_ORIG_TD1 0x40007becu +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0u +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM126_ORIG_TD0 0x40007bf0u +#define CYDEV_PHUB_TDMEM126_ORIG_TD1 0x40007bf4u +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8u +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM127_ORIG_TD0 0x40007bf8u +#define CYDEV_PHUB_TDMEM127_ORIG_TD1 0x40007bfcu +#define CYDEV_EE_BASE 0x40008000u +#define CYDEV_EE_SIZE 0x00000800u +#define CYDEV_EE_DATA_MBASE 0x40008000u +#define CYDEV_EE_DATA_MSIZE 0x00000800u +#define CYDEV_CAN0_BASE 0x4000a000u +#define CYDEV_CAN0_SIZE 0x000002a0u +#define CYDEV_CAN0_CSR_BASE 0x4000a000u +#define CYDEV_CAN0_CSR_SIZE 0x00000018u +#define CYDEV_CAN0_CSR_INT_SR 0x4000a000u +#define CYDEV_CAN0_CSR_INT_EN 0x4000a004u +#define CYDEV_CAN0_CSR_BUF_SR 0x4000a008u +#define CYDEV_CAN0_CSR_ERR_SR 0x4000a00cu +#define CYDEV_CAN0_CSR_CMD 0x4000a010u +#define CYDEV_CAN0_CSR_CFG 0x4000a014u +#define CYDEV_CAN0_TX0_BASE 0x4000a020u +#define CYDEV_CAN0_TX0_SIZE 0x00000010u +#define CYDEV_CAN0_TX0_CMD 0x4000a020u +#define CYDEV_CAN0_TX0_ID 0x4000a024u +#define CYDEV_CAN0_TX0_DH 0x4000a028u +#define CYDEV_CAN0_TX0_DL 0x4000a02cu +#define CYDEV_CAN0_TX1_BASE 0x4000a030u +#define CYDEV_CAN0_TX1_SIZE 0x00000010u +#define CYDEV_CAN0_TX1_CMD 0x4000a030u +#define CYDEV_CAN0_TX1_ID 0x4000a034u +#define CYDEV_CAN0_TX1_DH 0x4000a038u +#define CYDEV_CAN0_TX1_DL 0x4000a03cu +#define CYDEV_CAN0_TX2_BASE 0x4000a040u +#define CYDEV_CAN0_TX2_SIZE 0x00000010u +#define CYDEV_CAN0_TX2_CMD 0x4000a040u +#define CYDEV_CAN0_TX2_ID 0x4000a044u +#define CYDEV_CAN0_TX2_DH 0x4000a048u +#define CYDEV_CAN0_TX2_DL 0x4000a04cu +#define CYDEV_CAN0_TX3_BASE 0x4000a050u +#define CYDEV_CAN0_TX3_SIZE 0x00000010u +#define CYDEV_CAN0_TX3_CMD 0x4000a050u +#define CYDEV_CAN0_TX3_ID 0x4000a054u +#define CYDEV_CAN0_TX3_DH 0x4000a058u +#define CYDEV_CAN0_TX3_DL 0x4000a05cu +#define CYDEV_CAN0_TX4_BASE 0x4000a060u +#define CYDEV_CAN0_TX4_SIZE 0x00000010u +#define CYDEV_CAN0_TX4_CMD 0x4000a060u +#define CYDEV_CAN0_TX4_ID 0x4000a064u +#define CYDEV_CAN0_TX4_DH 0x4000a068u +#define CYDEV_CAN0_TX4_DL 0x4000a06cu +#define CYDEV_CAN0_TX5_BASE 0x4000a070u +#define CYDEV_CAN0_TX5_SIZE 0x00000010u +#define CYDEV_CAN0_TX5_CMD 0x4000a070u +#define CYDEV_CAN0_TX5_ID 0x4000a074u +#define CYDEV_CAN0_TX5_DH 0x4000a078u +#define CYDEV_CAN0_TX5_DL 0x4000a07cu +#define CYDEV_CAN0_TX6_BASE 0x4000a080u +#define CYDEV_CAN0_TX6_SIZE 0x00000010u +#define CYDEV_CAN0_TX6_CMD 0x4000a080u +#define CYDEV_CAN0_TX6_ID 0x4000a084u +#define CYDEV_CAN0_TX6_DH 0x4000a088u +#define CYDEV_CAN0_TX6_DL 0x4000a08cu +#define CYDEV_CAN0_TX7_BASE 0x4000a090u +#define CYDEV_CAN0_TX7_SIZE 0x00000010u +#define CYDEV_CAN0_TX7_CMD 0x4000a090u +#define CYDEV_CAN0_TX7_ID 0x4000a094u +#define CYDEV_CAN0_TX7_DH 0x4000a098u +#define CYDEV_CAN0_TX7_DL 0x4000a09cu +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0u +#define CYDEV_CAN0_RX0_SIZE 0x00000020u +#define CYDEV_CAN0_RX0_CMD 0x4000a0a0u +#define CYDEV_CAN0_RX0_ID 0x4000a0a4u +#define CYDEV_CAN0_RX0_DH 0x4000a0a8u +#define CYDEV_CAN0_RX0_DL 0x4000a0acu +#define CYDEV_CAN0_RX0_AMR 0x4000a0b0u +#define CYDEV_CAN0_RX0_ACR 0x4000a0b4u +#define CYDEV_CAN0_RX0_AMRD 0x4000a0b8u +#define CYDEV_CAN0_RX0_ACRD 0x4000a0bcu +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0u +#define CYDEV_CAN0_RX1_SIZE 0x00000020u +#define CYDEV_CAN0_RX1_CMD 0x4000a0c0u +#define CYDEV_CAN0_RX1_ID 0x4000a0c4u +#define CYDEV_CAN0_RX1_DH 0x4000a0c8u +#define CYDEV_CAN0_RX1_DL 0x4000a0ccu +#define CYDEV_CAN0_RX1_AMR 0x4000a0d0u +#define CYDEV_CAN0_RX1_ACR 0x4000a0d4u +#define CYDEV_CAN0_RX1_AMRD 0x4000a0d8u +#define CYDEV_CAN0_RX1_ACRD 0x4000a0dcu +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0u +#define CYDEV_CAN0_RX2_SIZE 0x00000020u +#define CYDEV_CAN0_RX2_CMD 0x4000a0e0u +#define CYDEV_CAN0_RX2_ID 0x4000a0e4u +#define CYDEV_CAN0_RX2_DH 0x4000a0e8u +#define CYDEV_CAN0_RX2_DL 0x4000a0ecu +#define CYDEV_CAN0_RX2_AMR 0x4000a0f0u +#define CYDEV_CAN0_RX2_ACR 0x4000a0f4u +#define CYDEV_CAN0_RX2_AMRD 0x4000a0f8u +#define CYDEV_CAN0_RX2_ACRD 0x4000a0fcu +#define CYDEV_CAN0_RX3_BASE 0x4000a100u +#define CYDEV_CAN0_RX3_SIZE 0x00000020u +#define CYDEV_CAN0_RX3_CMD 0x4000a100u +#define CYDEV_CAN0_RX3_ID 0x4000a104u +#define CYDEV_CAN0_RX3_DH 0x4000a108u +#define CYDEV_CAN0_RX3_DL 0x4000a10cu +#define CYDEV_CAN0_RX3_AMR 0x4000a110u +#define CYDEV_CAN0_RX3_ACR 0x4000a114u +#define CYDEV_CAN0_RX3_AMRD 0x4000a118u +#define CYDEV_CAN0_RX3_ACRD 0x4000a11cu +#define CYDEV_CAN0_RX4_BASE 0x4000a120u +#define CYDEV_CAN0_RX4_SIZE 0x00000020u +#define CYDEV_CAN0_RX4_CMD 0x4000a120u +#define CYDEV_CAN0_RX4_ID 0x4000a124u +#define CYDEV_CAN0_RX4_DH 0x4000a128u +#define CYDEV_CAN0_RX4_DL 0x4000a12cu +#define CYDEV_CAN0_RX4_AMR 0x4000a130u +#define CYDEV_CAN0_RX4_ACR 0x4000a134u +#define CYDEV_CAN0_RX4_AMRD 0x4000a138u +#define CYDEV_CAN0_RX4_ACRD 0x4000a13cu +#define CYDEV_CAN0_RX5_BASE 0x4000a140u +#define CYDEV_CAN0_RX5_SIZE 0x00000020u +#define CYDEV_CAN0_RX5_CMD 0x4000a140u +#define CYDEV_CAN0_RX5_ID 0x4000a144u +#define CYDEV_CAN0_RX5_DH 0x4000a148u +#define CYDEV_CAN0_RX5_DL 0x4000a14cu +#define CYDEV_CAN0_RX5_AMR 0x4000a150u +#define CYDEV_CAN0_RX5_ACR 0x4000a154u +#define CYDEV_CAN0_RX5_AMRD 0x4000a158u +#define CYDEV_CAN0_RX5_ACRD 0x4000a15cu +#define CYDEV_CAN0_RX6_BASE 0x4000a160u +#define CYDEV_CAN0_RX6_SIZE 0x00000020u +#define CYDEV_CAN0_RX6_CMD 0x4000a160u +#define CYDEV_CAN0_RX6_ID 0x4000a164u +#define CYDEV_CAN0_RX6_DH 0x4000a168u +#define CYDEV_CAN0_RX6_DL 0x4000a16cu +#define CYDEV_CAN0_RX6_AMR 0x4000a170u +#define CYDEV_CAN0_RX6_ACR 0x4000a174u +#define CYDEV_CAN0_RX6_AMRD 0x4000a178u +#define CYDEV_CAN0_RX6_ACRD 0x4000a17cu +#define CYDEV_CAN0_RX7_BASE 0x4000a180u +#define CYDEV_CAN0_RX7_SIZE 0x00000020u +#define CYDEV_CAN0_RX7_CMD 0x4000a180u +#define CYDEV_CAN0_RX7_ID 0x4000a184u +#define CYDEV_CAN0_RX7_DH 0x4000a188u +#define CYDEV_CAN0_RX7_DL 0x4000a18cu +#define CYDEV_CAN0_RX7_AMR 0x4000a190u +#define CYDEV_CAN0_RX7_ACR 0x4000a194u +#define CYDEV_CAN0_RX7_AMRD 0x4000a198u +#define CYDEV_CAN0_RX7_ACRD 0x4000a19cu +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0u +#define CYDEV_CAN0_RX8_SIZE 0x00000020u +#define CYDEV_CAN0_RX8_CMD 0x4000a1a0u +#define CYDEV_CAN0_RX8_ID 0x4000a1a4u +#define CYDEV_CAN0_RX8_DH 0x4000a1a8u +#define CYDEV_CAN0_RX8_DL 0x4000a1acu +#define CYDEV_CAN0_RX8_AMR 0x4000a1b0u +#define CYDEV_CAN0_RX8_ACR 0x4000a1b4u +#define CYDEV_CAN0_RX8_AMRD 0x4000a1b8u +#define CYDEV_CAN0_RX8_ACRD 0x4000a1bcu +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0u +#define CYDEV_CAN0_RX9_SIZE 0x00000020u +#define CYDEV_CAN0_RX9_CMD 0x4000a1c0u +#define CYDEV_CAN0_RX9_ID 0x4000a1c4u +#define CYDEV_CAN0_RX9_DH 0x4000a1c8u +#define CYDEV_CAN0_RX9_DL 0x4000a1ccu +#define CYDEV_CAN0_RX9_AMR 0x4000a1d0u +#define CYDEV_CAN0_RX9_ACR 0x4000a1d4u +#define CYDEV_CAN0_RX9_AMRD 0x4000a1d8u +#define CYDEV_CAN0_RX9_ACRD 0x4000a1dcu +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0u +#define CYDEV_CAN0_RX10_SIZE 0x00000020u +#define CYDEV_CAN0_RX10_CMD 0x4000a1e0u +#define CYDEV_CAN0_RX10_ID 0x4000a1e4u +#define CYDEV_CAN0_RX10_DH 0x4000a1e8u +#define CYDEV_CAN0_RX10_DL 0x4000a1ecu +#define CYDEV_CAN0_RX10_AMR 0x4000a1f0u +#define CYDEV_CAN0_RX10_ACR 0x4000a1f4u +#define CYDEV_CAN0_RX10_AMRD 0x4000a1f8u +#define CYDEV_CAN0_RX10_ACRD 0x4000a1fcu +#define CYDEV_CAN0_RX11_BASE 0x4000a200u +#define CYDEV_CAN0_RX11_SIZE 0x00000020u +#define CYDEV_CAN0_RX11_CMD 0x4000a200u +#define CYDEV_CAN0_RX11_ID 0x4000a204u +#define CYDEV_CAN0_RX11_DH 0x4000a208u +#define CYDEV_CAN0_RX11_DL 0x4000a20cu +#define CYDEV_CAN0_RX11_AMR 0x4000a210u +#define CYDEV_CAN0_RX11_ACR 0x4000a214u +#define CYDEV_CAN0_RX11_AMRD 0x4000a218u +#define CYDEV_CAN0_RX11_ACRD 0x4000a21cu +#define CYDEV_CAN0_RX12_BASE 0x4000a220u +#define CYDEV_CAN0_RX12_SIZE 0x00000020u +#define CYDEV_CAN0_RX12_CMD 0x4000a220u +#define CYDEV_CAN0_RX12_ID 0x4000a224u +#define CYDEV_CAN0_RX12_DH 0x4000a228u +#define CYDEV_CAN0_RX12_DL 0x4000a22cu +#define CYDEV_CAN0_RX12_AMR 0x4000a230u +#define CYDEV_CAN0_RX12_ACR 0x4000a234u +#define CYDEV_CAN0_RX12_AMRD 0x4000a238u +#define CYDEV_CAN0_RX12_ACRD 0x4000a23cu +#define CYDEV_CAN0_RX13_BASE 0x4000a240u +#define CYDEV_CAN0_RX13_SIZE 0x00000020u +#define CYDEV_CAN0_RX13_CMD 0x4000a240u +#define CYDEV_CAN0_RX13_ID 0x4000a244u +#define CYDEV_CAN0_RX13_DH 0x4000a248u +#define CYDEV_CAN0_RX13_DL 0x4000a24cu +#define CYDEV_CAN0_RX13_AMR 0x4000a250u +#define CYDEV_CAN0_RX13_ACR 0x4000a254u +#define CYDEV_CAN0_RX13_AMRD 0x4000a258u +#define CYDEV_CAN0_RX13_ACRD 0x4000a25cu +#define CYDEV_CAN0_RX14_BASE 0x4000a260u +#define CYDEV_CAN0_RX14_SIZE 0x00000020u +#define CYDEV_CAN0_RX14_CMD 0x4000a260u +#define CYDEV_CAN0_RX14_ID 0x4000a264u +#define CYDEV_CAN0_RX14_DH 0x4000a268u +#define CYDEV_CAN0_RX14_DL 0x4000a26cu +#define CYDEV_CAN0_RX14_AMR 0x4000a270u +#define CYDEV_CAN0_RX14_ACR 0x4000a274u +#define CYDEV_CAN0_RX14_AMRD 0x4000a278u +#define CYDEV_CAN0_RX14_ACRD 0x4000a27cu +#define CYDEV_CAN0_RX15_BASE 0x4000a280u +#define CYDEV_CAN0_RX15_SIZE 0x00000020u +#define CYDEV_CAN0_RX15_CMD 0x4000a280u +#define CYDEV_CAN0_RX15_ID 0x4000a284u +#define CYDEV_CAN0_RX15_DH 0x4000a288u +#define CYDEV_CAN0_RX15_DL 0x4000a28cu +#define CYDEV_CAN0_RX15_AMR 0x4000a290u +#define CYDEV_CAN0_RX15_ACR 0x4000a294u +#define CYDEV_CAN0_RX15_AMRD 0x4000a298u +#define CYDEV_CAN0_RX15_ACRD 0x4000a29cu +#define CYDEV_DFB0_BASE 0x4000c000u +#define CYDEV_DFB0_SIZE 0x000007b5u +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000u +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200u +#define CYDEV_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000u +#define CYDEV_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200u +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200u +#define CYDEV_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200u +#define CYDEV_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400u +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100u +#define CYDEV_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400u +#define CYDEV_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500u +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100u +#define CYDEV_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500u +#define CYDEV_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600u +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100u +#define CYDEV_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600u +#define CYDEV_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700u +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040u +#define CYDEV_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700u +#define CYDEV_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040u +#define CYDEV_DFB0_CR 0x4000c780u +#define CYDEV_DFB0_SR 0x4000c784u +#define CYDEV_DFB0_RAM_EN 0x4000c788u +#define CYDEV_DFB0_RAM_DIR 0x4000c78cu +#define CYDEV_DFB0_SEMA 0x4000c790u +#define CYDEV_DFB0_DSI_CTRL 0x4000c794u +#define CYDEV_DFB0_INT_CTRL 0x4000c798u +#define CYDEV_DFB0_DMA_CTRL 0x4000c79cu +#define CYDEV_DFB0_STAGEA 0x4000c7a0u +#define CYDEV_DFB0_STAGEAM 0x4000c7a1u +#define CYDEV_DFB0_STAGEAH 0x4000c7a2u +#define CYDEV_DFB0_STAGEB 0x4000c7a4u +#define CYDEV_DFB0_STAGEBM 0x4000c7a5u +#define CYDEV_DFB0_STAGEBH 0x4000c7a6u +#define CYDEV_DFB0_HOLDA 0x4000c7a8u +#define CYDEV_DFB0_HOLDAM 0x4000c7a9u +#define CYDEV_DFB0_HOLDAH 0x4000c7aau +#define CYDEV_DFB0_HOLDAS 0x4000c7abu +#define CYDEV_DFB0_HOLDB 0x4000c7acu +#define CYDEV_DFB0_HOLDBM 0x4000c7adu +#define CYDEV_DFB0_HOLDBH 0x4000c7aeu +#define CYDEV_DFB0_HOLDBS 0x4000c7afu +#define CYDEV_DFB0_COHER 0x4000c7b0u +#define CYDEV_DFB0_DALIGN 0x4000c7b4u +#define CYDEV_UCFG_BASE 0x40010000u +#define CYDEV_UCFG_SIZE 0x00005040u +#define CYDEV_UCFG_B0_BASE 0x40010000u +#define CYDEV_UCFG_B0_SIZE 0x00000fefu +#define CYDEV_UCFG_B0_P0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT0 0x40010000u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT1 0x40010004u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT2 0x40010008u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT3 0x4001000cu +#define CYDEV_UCFG_B0_P0_U0_PLD_IT4 0x40010010u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT5 0x40010014u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT6 0x40010018u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT7 0x4001001cu +#define CYDEV_UCFG_B0_P0_U0_PLD_IT8 0x40010020u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT9 0x40010024u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT10 0x40010028u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT11 0x4001002cu +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT0 0x40010030u +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT1 0x40010032u +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT2 0x40010034u +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT3 0x40010036u +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038u +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB 0x4001003au +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003cu +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS 0x4001003eu +#define CYDEV_UCFG_B0_P0_U0_CFG0 0x40010040u +#define CYDEV_UCFG_B0_P0_U0_CFG1 0x40010041u +#define CYDEV_UCFG_B0_P0_U0_CFG2 0x40010042u +#define CYDEV_UCFG_B0_P0_U0_CFG3 0x40010043u +#define CYDEV_UCFG_B0_P0_U0_CFG4 0x40010044u +#define CYDEV_UCFG_B0_P0_U0_CFG5 0x40010045u +#define CYDEV_UCFG_B0_P0_U0_CFG6 0x40010046u +#define CYDEV_UCFG_B0_P0_U0_CFG7 0x40010047u +#define CYDEV_UCFG_B0_P0_U0_CFG8 0x40010048u +#define CYDEV_UCFG_B0_P0_U0_CFG9 0x40010049u +#define CYDEV_UCFG_B0_P0_U0_CFG10 0x4001004au +#define CYDEV_UCFG_B0_P0_U0_CFG11 0x4001004bu +#define CYDEV_UCFG_B0_P0_U0_CFG12 0x4001004cu +#define CYDEV_UCFG_B0_P0_U0_CFG13 0x4001004du +#define CYDEV_UCFG_B0_P0_U0_CFG14 0x4001004eu +#define CYDEV_UCFG_B0_P0_U0_CFG15 0x4001004fu +#define CYDEV_UCFG_B0_P0_U0_CFG16 0x40010050u +#define CYDEV_UCFG_B0_P0_U0_CFG17 0x40010051u +#define CYDEV_UCFG_B0_P0_U0_CFG18 0x40010052u +#define CYDEV_UCFG_B0_P0_U0_CFG19 0x40010053u +#define CYDEV_UCFG_B0_P0_U0_CFG20 0x40010054u +#define CYDEV_UCFG_B0_P0_U0_CFG21 0x40010055u +#define CYDEV_UCFG_B0_P0_U0_CFG22 0x40010056u +#define CYDEV_UCFG_B0_P0_U0_CFG23 0x40010057u +#define CYDEV_UCFG_B0_P0_U0_CFG24 0x40010058u +#define CYDEV_UCFG_B0_P0_U0_CFG25 0x40010059u +#define CYDEV_UCFG_B0_P0_U0_CFG26 0x4001005au +#define CYDEV_UCFG_B0_P0_U0_CFG27 0x4001005bu +#define CYDEV_UCFG_B0_P0_U0_CFG28 0x4001005cu +#define CYDEV_UCFG_B0_P0_U0_CFG29 0x4001005du +#define CYDEV_UCFG_B0_P0_U0_CFG30 0x4001005eu +#define CYDEV_UCFG_B0_P0_U0_CFG31 0x4001005fu +#define CYDEV_UCFG_B0_P0_U0_DCFG0 0x40010060u +#define CYDEV_UCFG_B0_P0_U0_DCFG1 0x40010062u +#define CYDEV_UCFG_B0_P0_U0_DCFG2 0x40010064u +#define CYDEV_UCFG_B0_P0_U0_DCFG3 0x40010066u +#define CYDEV_UCFG_B0_P0_U0_DCFG4 0x40010068u +#define CYDEV_UCFG_B0_P0_U0_DCFG5 0x4001006au +#define CYDEV_UCFG_B0_P0_U0_DCFG6 0x4001006cu +#define CYDEV_UCFG_B0_P0_U0_DCFG7 0x4001006eu +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080u +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT0 0x40010080u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT1 0x40010084u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT2 0x40010088u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT3 0x4001008cu +#define CYDEV_UCFG_B0_P0_U1_PLD_IT4 0x40010090u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT5 0x40010094u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT6 0x40010098u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT7 0x4001009cu +#define CYDEV_UCFG_B0_P0_U1_PLD_IT8 0x400100a0u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT9 0x400100a4u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT10 0x400100a8u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT11 0x400100acu +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT0 0x400100b0u +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT1 0x400100b2u +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT2 0x400100b4u +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT3 0x400100b6u +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8u +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB 0x400100bau +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bcu +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS 0x400100beu +#define CYDEV_UCFG_B0_P0_U1_CFG0 0x400100c0u +#define CYDEV_UCFG_B0_P0_U1_CFG1 0x400100c1u +#define CYDEV_UCFG_B0_P0_U1_CFG2 0x400100c2u +#define CYDEV_UCFG_B0_P0_U1_CFG3 0x400100c3u +#define CYDEV_UCFG_B0_P0_U1_CFG4 0x400100c4u +#define CYDEV_UCFG_B0_P0_U1_CFG5 0x400100c5u +#define CYDEV_UCFG_B0_P0_U1_CFG6 0x400100c6u +#define CYDEV_UCFG_B0_P0_U1_CFG7 0x400100c7u +#define CYDEV_UCFG_B0_P0_U1_CFG8 0x400100c8u +#define CYDEV_UCFG_B0_P0_U1_CFG9 0x400100c9u +#define CYDEV_UCFG_B0_P0_U1_CFG10 0x400100cau +#define CYDEV_UCFG_B0_P0_U1_CFG11 0x400100cbu +#define CYDEV_UCFG_B0_P0_U1_CFG12 0x400100ccu +#define CYDEV_UCFG_B0_P0_U1_CFG13 0x400100cdu +#define CYDEV_UCFG_B0_P0_U1_CFG14 0x400100ceu +#define CYDEV_UCFG_B0_P0_U1_CFG15 0x400100cfu +#define CYDEV_UCFG_B0_P0_U1_CFG16 0x400100d0u +#define CYDEV_UCFG_B0_P0_U1_CFG17 0x400100d1u +#define CYDEV_UCFG_B0_P0_U1_CFG18 0x400100d2u +#define CYDEV_UCFG_B0_P0_U1_CFG19 0x400100d3u +#define CYDEV_UCFG_B0_P0_U1_CFG20 0x400100d4u +#define CYDEV_UCFG_B0_P0_U1_CFG21 0x400100d5u +#define CYDEV_UCFG_B0_P0_U1_CFG22 0x400100d6u +#define CYDEV_UCFG_B0_P0_U1_CFG23 0x400100d7u +#define CYDEV_UCFG_B0_P0_U1_CFG24 0x400100d8u +#define CYDEV_UCFG_B0_P0_U1_CFG25 0x400100d9u +#define CYDEV_UCFG_B0_P0_U1_CFG26 0x400100dau +#define CYDEV_UCFG_B0_P0_U1_CFG27 0x400100dbu +#define CYDEV_UCFG_B0_P0_U1_CFG28 0x400100dcu +#define CYDEV_UCFG_B0_P0_U1_CFG29 0x400100ddu +#define CYDEV_UCFG_B0_P0_U1_CFG30 0x400100deu +#define CYDEV_UCFG_B0_P0_U1_CFG31 0x400100dfu +#define CYDEV_UCFG_B0_P0_U1_DCFG0 0x400100e0u +#define CYDEV_UCFG_B0_P0_U1_DCFG1 0x400100e2u +#define CYDEV_UCFG_B0_P0_U1_DCFG2 0x400100e4u +#define CYDEV_UCFG_B0_P0_U1_DCFG3 0x400100e6u +#define CYDEV_UCFG_B0_P0_U1_DCFG4 0x400100e8u +#define CYDEV_UCFG_B0_P0_U1_DCFG5 0x400100eau +#define CYDEV_UCFG_B0_P0_U1_DCFG6 0x400100ecu +#define CYDEV_UCFG_B0_P0_U1_DCFG7 0x400100eeu +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100u +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P1_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT0 0x40010200u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT1 0x40010204u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT2 0x40010208u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT3 0x4001020cu +#define CYDEV_UCFG_B0_P1_U0_PLD_IT4 0x40010210u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT5 0x40010214u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT6 0x40010218u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT7 0x4001021cu +#define CYDEV_UCFG_B0_P1_U0_PLD_IT8 0x40010220u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT9 0x40010224u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT10 0x40010228u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT11 0x4001022cu +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT0 0x40010230u +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT1 0x40010232u +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT2 0x40010234u +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT3 0x40010236u +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238u +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB 0x4001023au +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023cu +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS 0x4001023eu +#define CYDEV_UCFG_B0_P1_U0_CFG0 0x40010240u +#define CYDEV_UCFG_B0_P1_U0_CFG1 0x40010241u +#define CYDEV_UCFG_B0_P1_U0_CFG2 0x40010242u +#define CYDEV_UCFG_B0_P1_U0_CFG3 0x40010243u +#define CYDEV_UCFG_B0_P1_U0_CFG4 0x40010244u +#define CYDEV_UCFG_B0_P1_U0_CFG5 0x40010245u +#define CYDEV_UCFG_B0_P1_U0_CFG6 0x40010246u +#define CYDEV_UCFG_B0_P1_U0_CFG7 0x40010247u +#define CYDEV_UCFG_B0_P1_U0_CFG8 0x40010248u +#define CYDEV_UCFG_B0_P1_U0_CFG9 0x40010249u +#define CYDEV_UCFG_B0_P1_U0_CFG10 0x4001024au +#define CYDEV_UCFG_B0_P1_U0_CFG11 0x4001024bu +#define CYDEV_UCFG_B0_P1_U0_CFG12 0x4001024cu +#define CYDEV_UCFG_B0_P1_U0_CFG13 0x4001024du +#define CYDEV_UCFG_B0_P1_U0_CFG14 0x4001024eu +#define CYDEV_UCFG_B0_P1_U0_CFG15 0x4001024fu +#define CYDEV_UCFG_B0_P1_U0_CFG16 0x40010250u +#define CYDEV_UCFG_B0_P1_U0_CFG17 0x40010251u +#define CYDEV_UCFG_B0_P1_U0_CFG18 0x40010252u +#define CYDEV_UCFG_B0_P1_U0_CFG19 0x40010253u +#define CYDEV_UCFG_B0_P1_U0_CFG20 0x40010254u +#define CYDEV_UCFG_B0_P1_U0_CFG21 0x40010255u +#define CYDEV_UCFG_B0_P1_U0_CFG22 0x40010256u +#define CYDEV_UCFG_B0_P1_U0_CFG23 0x40010257u +#define CYDEV_UCFG_B0_P1_U0_CFG24 0x40010258u +#define CYDEV_UCFG_B0_P1_U0_CFG25 0x40010259u +#define CYDEV_UCFG_B0_P1_U0_CFG26 0x4001025au +#define CYDEV_UCFG_B0_P1_U0_CFG27 0x4001025bu +#define CYDEV_UCFG_B0_P1_U0_CFG28 0x4001025cu +#define CYDEV_UCFG_B0_P1_U0_CFG29 0x4001025du +#define CYDEV_UCFG_B0_P1_U0_CFG30 0x4001025eu +#define CYDEV_UCFG_B0_P1_U0_CFG31 0x4001025fu +#define CYDEV_UCFG_B0_P1_U0_DCFG0 0x40010260u +#define CYDEV_UCFG_B0_P1_U0_DCFG1 0x40010262u +#define CYDEV_UCFG_B0_P1_U0_DCFG2 0x40010264u +#define CYDEV_UCFG_B0_P1_U0_DCFG3 0x40010266u +#define CYDEV_UCFG_B0_P1_U0_DCFG4 0x40010268u +#define CYDEV_UCFG_B0_P1_U0_DCFG5 0x4001026au +#define CYDEV_UCFG_B0_P1_U0_DCFG6 0x4001026cu +#define CYDEV_UCFG_B0_P1_U0_DCFG7 0x4001026eu +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280u +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT0 0x40010280u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT1 0x40010284u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT2 0x40010288u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT3 0x4001028cu +#define CYDEV_UCFG_B0_P1_U1_PLD_IT4 0x40010290u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT5 0x40010294u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT6 0x40010298u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT7 0x4001029cu +#define CYDEV_UCFG_B0_P1_U1_PLD_IT8 0x400102a0u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT9 0x400102a4u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT10 0x400102a8u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT11 0x400102acu +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT0 0x400102b0u +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT1 0x400102b2u +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT2 0x400102b4u +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT3 0x400102b6u +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8u +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB 0x400102bau +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bcu +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS 0x400102beu +#define CYDEV_UCFG_B0_P1_U1_CFG0 0x400102c0u +#define CYDEV_UCFG_B0_P1_U1_CFG1 0x400102c1u +#define CYDEV_UCFG_B0_P1_U1_CFG2 0x400102c2u +#define CYDEV_UCFG_B0_P1_U1_CFG3 0x400102c3u +#define CYDEV_UCFG_B0_P1_U1_CFG4 0x400102c4u +#define CYDEV_UCFG_B0_P1_U1_CFG5 0x400102c5u +#define CYDEV_UCFG_B0_P1_U1_CFG6 0x400102c6u +#define CYDEV_UCFG_B0_P1_U1_CFG7 0x400102c7u +#define CYDEV_UCFG_B0_P1_U1_CFG8 0x400102c8u +#define CYDEV_UCFG_B0_P1_U1_CFG9 0x400102c9u +#define CYDEV_UCFG_B0_P1_U1_CFG10 0x400102cau +#define CYDEV_UCFG_B0_P1_U1_CFG11 0x400102cbu +#define CYDEV_UCFG_B0_P1_U1_CFG12 0x400102ccu +#define CYDEV_UCFG_B0_P1_U1_CFG13 0x400102cdu +#define CYDEV_UCFG_B0_P1_U1_CFG14 0x400102ceu +#define CYDEV_UCFG_B0_P1_U1_CFG15 0x400102cfu +#define CYDEV_UCFG_B0_P1_U1_CFG16 0x400102d0u +#define CYDEV_UCFG_B0_P1_U1_CFG17 0x400102d1u +#define CYDEV_UCFG_B0_P1_U1_CFG18 0x400102d2u +#define CYDEV_UCFG_B0_P1_U1_CFG19 0x400102d3u +#define CYDEV_UCFG_B0_P1_U1_CFG20 0x400102d4u +#define CYDEV_UCFG_B0_P1_U1_CFG21 0x400102d5u +#define CYDEV_UCFG_B0_P1_U1_CFG22 0x400102d6u +#define CYDEV_UCFG_B0_P1_U1_CFG23 0x400102d7u +#define CYDEV_UCFG_B0_P1_U1_CFG24 0x400102d8u +#define CYDEV_UCFG_B0_P1_U1_CFG25 0x400102d9u +#define CYDEV_UCFG_B0_P1_U1_CFG26 0x400102dau +#define CYDEV_UCFG_B0_P1_U1_CFG27 0x400102dbu +#define CYDEV_UCFG_B0_P1_U1_CFG28 0x400102dcu +#define CYDEV_UCFG_B0_P1_U1_CFG29 0x400102ddu +#define CYDEV_UCFG_B0_P1_U1_CFG30 0x400102deu +#define CYDEV_UCFG_B0_P1_U1_CFG31 0x400102dfu +#define CYDEV_UCFG_B0_P1_U1_DCFG0 0x400102e0u +#define CYDEV_UCFG_B0_P1_U1_DCFG1 0x400102e2u +#define CYDEV_UCFG_B0_P1_U1_DCFG2 0x400102e4u +#define CYDEV_UCFG_B0_P1_U1_DCFG3 0x400102e6u +#define CYDEV_UCFG_B0_P1_U1_DCFG4 0x400102e8u +#define CYDEV_UCFG_B0_P1_U1_DCFG5 0x400102eau +#define CYDEV_UCFG_B0_P1_U1_DCFG6 0x400102ecu +#define CYDEV_UCFG_B0_P1_U1_DCFG7 0x400102eeu +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300u +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P2_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT0 0x40010400u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT1 0x40010404u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT2 0x40010408u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT3 0x4001040cu +#define CYDEV_UCFG_B0_P2_U0_PLD_IT4 0x40010410u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT5 0x40010414u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT6 0x40010418u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT7 0x4001041cu +#define CYDEV_UCFG_B0_P2_U0_PLD_IT8 0x40010420u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT9 0x40010424u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT10 0x40010428u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT11 0x4001042cu +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT0 0x40010430u +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT1 0x40010432u +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT2 0x40010434u +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT3 0x40010436u +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438u +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB 0x4001043au +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043cu +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS 0x4001043eu +#define CYDEV_UCFG_B0_P2_U0_CFG0 0x40010440u +#define CYDEV_UCFG_B0_P2_U0_CFG1 0x40010441u +#define CYDEV_UCFG_B0_P2_U0_CFG2 0x40010442u +#define CYDEV_UCFG_B0_P2_U0_CFG3 0x40010443u +#define CYDEV_UCFG_B0_P2_U0_CFG4 0x40010444u +#define CYDEV_UCFG_B0_P2_U0_CFG5 0x40010445u +#define CYDEV_UCFG_B0_P2_U0_CFG6 0x40010446u +#define CYDEV_UCFG_B0_P2_U0_CFG7 0x40010447u +#define CYDEV_UCFG_B0_P2_U0_CFG8 0x40010448u +#define CYDEV_UCFG_B0_P2_U0_CFG9 0x40010449u +#define CYDEV_UCFG_B0_P2_U0_CFG10 0x4001044au +#define CYDEV_UCFG_B0_P2_U0_CFG11 0x4001044bu +#define CYDEV_UCFG_B0_P2_U0_CFG12 0x4001044cu +#define CYDEV_UCFG_B0_P2_U0_CFG13 0x4001044du +#define CYDEV_UCFG_B0_P2_U0_CFG14 0x4001044eu +#define CYDEV_UCFG_B0_P2_U0_CFG15 0x4001044fu +#define CYDEV_UCFG_B0_P2_U0_CFG16 0x40010450u +#define CYDEV_UCFG_B0_P2_U0_CFG17 0x40010451u +#define CYDEV_UCFG_B0_P2_U0_CFG18 0x40010452u +#define CYDEV_UCFG_B0_P2_U0_CFG19 0x40010453u +#define CYDEV_UCFG_B0_P2_U0_CFG20 0x40010454u +#define CYDEV_UCFG_B0_P2_U0_CFG21 0x40010455u +#define CYDEV_UCFG_B0_P2_U0_CFG22 0x40010456u +#define CYDEV_UCFG_B0_P2_U0_CFG23 0x40010457u +#define CYDEV_UCFG_B0_P2_U0_CFG24 0x40010458u +#define CYDEV_UCFG_B0_P2_U0_CFG25 0x40010459u +#define CYDEV_UCFG_B0_P2_U0_CFG26 0x4001045au +#define CYDEV_UCFG_B0_P2_U0_CFG27 0x4001045bu +#define CYDEV_UCFG_B0_P2_U0_CFG28 0x4001045cu +#define CYDEV_UCFG_B0_P2_U0_CFG29 0x4001045du +#define CYDEV_UCFG_B0_P2_U0_CFG30 0x4001045eu +#define CYDEV_UCFG_B0_P2_U0_CFG31 0x4001045fu +#define CYDEV_UCFG_B0_P2_U0_DCFG0 0x40010460u +#define CYDEV_UCFG_B0_P2_U0_DCFG1 0x40010462u +#define CYDEV_UCFG_B0_P2_U0_DCFG2 0x40010464u +#define CYDEV_UCFG_B0_P2_U0_DCFG3 0x40010466u +#define CYDEV_UCFG_B0_P2_U0_DCFG4 0x40010468u +#define CYDEV_UCFG_B0_P2_U0_DCFG5 0x4001046au +#define CYDEV_UCFG_B0_P2_U0_DCFG6 0x4001046cu +#define CYDEV_UCFG_B0_P2_U0_DCFG7 0x4001046eu +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480u +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT0 0x40010480u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT1 0x40010484u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT2 0x40010488u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT3 0x4001048cu +#define CYDEV_UCFG_B0_P2_U1_PLD_IT4 0x40010490u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT5 0x40010494u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT6 0x40010498u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT7 0x4001049cu +#define CYDEV_UCFG_B0_P2_U1_PLD_IT8 0x400104a0u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT9 0x400104a4u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT10 0x400104a8u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT11 0x400104acu +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT0 0x400104b0u +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT1 0x400104b2u +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT2 0x400104b4u +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT3 0x400104b6u +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8u +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB 0x400104bau +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bcu +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS 0x400104beu +#define CYDEV_UCFG_B0_P2_U1_CFG0 0x400104c0u +#define CYDEV_UCFG_B0_P2_U1_CFG1 0x400104c1u +#define CYDEV_UCFG_B0_P2_U1_CFG2 0x400104c2u +#define CYDEV_UCFG_B0_P2_U1_CFG3 0x400104c3u +#define CYDEV_UCFG_B0_P2_U1_CFG4 0x400104c4u +#define CYDEV_UCFG_B0_P2_U1_CFG5 0x400104c5u +#define CYDEV_UCFG_B0_P2_U1_CFG6 0x400104c6u +#define CYDEV_UCFG_B0_P2_U1_CFG7 0x400104c7u +#define CYDEV_UCFG_B0_P2_U1_CFG8 0x400104c8u +#define CYDEV_UCFG_B0_P2_U1_CFG9 0x400104c9u +#define CYDEV_UCFG_B0_P2_U1_CFG10 0x400104cau +#define CYDEV_UCFG_B0_P2_U1_CFG11 0x400104cbu +#define CYDEV_UCFG_B0_P2_U1_CFG12 0x400104ccu +#define CYDEV_UCFG_B0_P2_U1_CFG13 0x400104cdu +#define CYDEV_UCFG_B0_P2_U1_CFG14 0x400104ceu +#define CYDEV_UCFG_B0_P2_U1_CFG15 0x400104cfu +#define CYDEV_UCFG_B0_P2_U1_CFG16 0x400104d0u +#define CYDEV_UCFG_B0_P2_U1_CFG17 0x400104d1u +#define CYDEV_UCFG_B0_P2_U1_CFG18 0x400104d2u +#define CYDEV_UCFG_B0_P2_U1_CFG19 0x400104d3u +#define CYDEV_UCFG_B0_P2_U1_CFG20 0x400104d4u +#define CYDEV_UCFG_B0_P2_U1_CFG21 0x400104d5u +#define CYDEV_UCFG_B0_P2_U1_CFG22 0x400104d6u +#define CYDEV_UCFG_B0_P2_U1_CFG23 0x400104d7u +#define CYDEV_UCFG_B0_P2_U1_CFG24 0x400104d8u +#define CYDEV_UCFG_B0_P2_U1_CFG25 0x400104d9u +#define CYDEV_UCFG_B0_P2_U1_CFG26 0x400104dau +#define CYDEV_UCFG_B0_P2_U1_CFG27 0x400104dbu +#define CYDEV_UCFG_B0_P2_U1_CFG28 0x400104dcu +#define CYDEV_UCFG_B0_P2_U1_CFG29 0x400104ddu +#define CYDEV_UCFG_B0_P2_U1_CFG30 0x400104deu +#define CYDEV_UCFG_B0_P2_U1_CFG31 0x400104dfu +#define CYDEV_UCFG_B0_P2_U1_DCFG0 0x400104e0u +#define CYDEV_UCFG_B0_P2_U1_DCFG1 0x400104e2u +#define CYDEV_UCFG_B0_P2_U1_DCFG2 0x400104e4u +#define CYDEV_UCFG_B0_P2_U1_DCFG3 0x400104e6u +#define CYDEV_UCFG_B0_P2_U1_DCFG4 0x400104e8u +#define CYDEV_UCFG_B0_P2_U1_DCFG5 0x400104eau +#define CYDEV_UCFG_B0_P2_U1_DCFG6 0x400104ecu +#define CYDEV_UCFG_B0_P2_U1_DCFG7 0x400104eeu +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500u +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P3_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT0 0x40010600u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT1 0x40010604u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT2 0x40010608u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT3 0x4001060cu +#define CYDEV_UCFG_B0_P3_U0_PLD_IT4 0x40010610u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT5 0x40010614u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT6 0x40010618u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT7 0x4001061cu +#define CYDEV_UCFG_B0_P3_U0_PLD_IT8 0x40010620u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT9 0x40010624u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT10 0x40010628u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT11 0x4001062cu +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT0 0x40010630u +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT1 0x40010632u +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT2 0x40010634u +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT3 0x40010636u +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638u +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB 0x4001063au +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063cu +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS 0x4001063eu +#define CYDEV_UCFG_B0_P3_U0_CFG0 0x40010640u +#define CYDEV_UCFG_B0_P3_U0_CFG1 0x40010641u +#define CYDEV_UCFG_B0_P3_U0_CFG2 0x40010642u +#define CYDEV_UCFG_B0_P3_U0_CFG3 0x40010643u +#define CYDEV_UCFG_B0_P3_U0_CFG4 0x40010644u +#define CYDEV_UCFG_B0_P3_U0_CFG5 0x40010645u +#define CYDEV_UCFG_B0_P3_U0_CFG6 0x40010646u +#define CYDEV_UCFG_B0_P3_U0_CFG7 0x40010647u +#define CYDEV_UCFG_B0_P3_U0_CFG8 0x40010648u +#define CYDEV_UCFG_B0_P3_U0_CFG9 0x40010649u +#define CYDEV_UCFG_B0_P3_U0_CFG10 0x4001064au +#define CYDEV_UCFG_B0_P3_U0_CFG11 0x4001064bu +#define CYDEV_UCFG_B0_P3_U0_CFG12 0x4001064cu +#define CYDEV_UCFG_B0_P3_U0_CFG13 0x4001064du +#define CYDEV_UCFG_B0_P3_U0_CFG14 0x4001064eu +#define CYDEV_UCFG_B0_P3_U0_CFG15 0x4001064fu +#define CYDEV_UCFG_B0_P3_U0_CFG16 0x40010650u +#define CYDEV_UCFG_B0_P3_U0_CFG17 0x40010651u +#define CYDEV_UCFG_B0_P3_U0_CFG18 0x40010652u +#define CYDEV_UCFG_B0_P3_U0_CFG19 0x40010653u +#define CYDEV_UCFG_B0_P3_U0_CFG20 0x40010654u +#define CYDEV_UCFG_B0_P3_U0_CFG21 0x40010655u +#define CYDEV_UCFG_B0_P3_U0_CFG22 0x40010656u +#define CYDEV_UCFG_B0_P3_U0_CFG23 0x40010657u +#define CYDEV_UCFG_B0_P3_U0_CFG24 0x40010658u +#define CYDEV_UCFG_B0_P3_U0_CFG25 0x40010659u +#define CYDEV_UCFG_B0_P3_U0_CFG26 0x4001065au +#define CYDEV_UCFG_B0_P3_U0_CFG27 0x4001065bu +#define CYDEV_UCFG_B0_P3_U0_CFG28 0x4001065cu +#define CYDEV_UCFG_B0_P3_U0_CFG29 0x4001065du +#define CYDEV_UCFG_B0_P3_U0_CFG30 0x4001065eu +#define CYDEV_UCFG_B0_P3_U0_CFG31 0x4001065fu +#define CYDEV_UCFG_B0_P3_U0_DCFG0 0x40010660u +#define CYDEV_UCFG_B0_P3_U0_DCFG1 0x40010662u +#define CYDEV_UCFG_B0_P3_U0_DCFG2 0x40010664u +#define CYDEV_UCFG_B0_P3_U0_DCFG3 0x40010666u +#define CYDEV_UCFG_B0_P3_U0_DCFG4 0x40010668u +#define CYDEV_UCFG_B0_P3_U0_DCFG5 0x4001066au +#define CYDEV_UCFG_B0_P3_U0_DCFG6 0x4001066cu +#define CYDEV_UCFG_B0_P3_U0_DCFG7 0x4001066eu +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680u +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT0 0x40010680u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT1 0x40010684u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT2 0x40010688u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT3 0x4001068cu +#define CYDEV_UCFG_B0_P3_U1_PLD_IT4 0x40010690u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT5 0x40010694u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT6 0x40010698u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT7 0x4001069cu +#define CYDEV_UCFG_B0_P3_U1_PLD_IT8 0x400106a0u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT9 0x400106a4u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT10 0x400106a8u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT11 0x400106acu +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT0 0x400106b0u +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT1 0x400106b2u +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT2 0x400106b4u +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT3 0x400106b6u +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8u +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB 0x400106bau +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bcu +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS 0x400106beu +#define CYDEV_UCFG_B0_P3_U1_CFG0 0x400106c0u +#define CYDEV_UCFG_B0_P3_U1_CFG1 0x400106c1u +#define CYDEV_UCFG_B0_P3_U1_CFG2 0x400106c2u +#define CYDEV_UCFG_B0_P3_U1_CFG3 0x400106c3u +#define CYDEV_UCFG_B0_P3_U1_CFG4 0x400106c4u +#define CYDEV_UCFG_B0_P3_U1_CFG5 0x400106c5u +#define CYDEV_UCFG_B0_P3_U1_CFG6 0x400106c6u +#define CYDEV_UCFG_B0_P3_U1_CFG7 0x400106c7u +#define CYDEV_UCFG_B0_P3_U1_CFG8 0x400106c8u +#define CYDEV_UCFG_B0_P3_U1_CFG9 0x400106c9u +#define CYDEV_UCFG_B0_P3_U1_CFG10 0x400106cau +#define CYDEV_UCFG_B0_P3_U1_CFG11 0x400106cbu +#define CYDEV_UCFG_B0_P3_U1_CFG12 0x400106ccu +#define CYDEV_UCFG_B0_P3_U1_CFG13 0x400106cdu +#define CYDEV_UCFG_B0_P3_U1_CFG14 0x400106ceu +#define CYDEV_UCFG_B0_P3_U1_CFG15 0x400106cfu +#define CYDEV_UCFG_B0_P3_U1_CFG16 0x400106d0u +#define CYDEV_UCFG_B0_P3_U1_CFG17 0x400106d1u +#define CYDEV_UCFG_B0_P3_U1_CFG18 0x400106d2u +#define CYDEV_UCFG_B0_P3_U1_CFG19 0x400106d3u +#define CYDEV_UCFG_B0_P3_U1_CFG20 0x400106d4u +#define CYDEV_UCFG_B0_P3_U1_CFG21 0x400106d5u +#define CYDEV_UCFG_B0_P3_U1_CFG22 0x400106d6u +#define CYDEV_UCFG_B0_P3_U1_CFG23 0x400106d7u +#define CYDEV_UCFG_B0_P3_U1_CFG24 0x400106d8u +#define CYDEV_UCFG_B0_P3_U1_CFG25 0x400106d9u +#define CYDEV_UCFG_B0_P3_U1_CFG26 0x400106dau +#define CYDEV_UCFG_B0_P3_U1_CFG27 0x400106dbu +#define CYDEV_UCFG_B0_P3_U1_CFG28 0x400106dcu +#define CYDEV_UCFG_B0_P3_U1_CFG29 0x400106ddu +#define CYDEV_UCFG_B0_P3_U1_CFG30 0x400106deu +#define CYDEV_UCFG_B0_P3_U1_CFG31 0x400106dfu +#define CYDEV_UCFG_B0_P3_U1_DCFG0 0x400106e0u +#define CYDEV_UCFG_B0_P3_U1_DCFG1 0x400106e2u +#define CYDEV_UCFG_B0_P3_U1_DCFG2 0x400106e4u +#define CYDEV_UCFG_B0_P3_U1_DCFG3 0x400106e6u +#define CYDEV_UCFG_B0_P3_U1_DCFG4 0x400106e8u +#define CYDEV_UCFG_B0_P3_U1_DCFG5 0x400106eau +#define CYDEV_UCFG_B0_P3_U1_DCFG6 0x400106ecu +#define CYDEV_UCFG_B0_P3_U1_DCFG7 0x400106eeu +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700u +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P4_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT0 0x40010800u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT1 0x40010804u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT2 0x40010808u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT3 0x4001080cu +#define CYDEV_UCFG_B0_P4_U0_PLD_IT4 0x40010810u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT5 0x40010814u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT6 0x40010818u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT7 0x4001081cu +#define CYDEV_UCFG_B0_P4_U0_PLD_IT8 0x40010820u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT9 0x40010824u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT10 0x40010828u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT11 0x4001082cu +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT0 0x40010830u +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT1 0x40010832u +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT2 0x40010834u +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT3 0x40010836u +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838u +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB 0x4001083au +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083cu +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS 0x4001083eu +#define CYDEV_UCFG_B0_P4_U0_CFG0 0x40010840u +#define CYDEV_UCFG_B0_P4_U0_CFG1 0x40010841u +#define CYDEV_UCFG_B0_P4_U0_CFG2 0x40010842u +#define CYDEV_UCFG_B0_P4_U0_CFG3 0x40010843u +#define CYDEV_UCFG_B0_P4_U0_CFG4 0x40010844u +#define CYDEV_UCFG_B0_P4_U0_CFG5 0x40010845u +#define CYDEV_UCFG_B0_P4_U0_CFG6 0x40010846u +#define CYDEV_UCFG_B0_P4_U0_CFG7 0x40010847u +#define CYDEV_UCFG_B0_P4_U0_CFG8 0x40010848u +#define CYDEV_UCFG_B0_P4_U0_CFG9 0x40010849u +#define CYDEV_UCFG_B0_P4_U0_CFG10 0x4001084au +#define CYDEV_UCFG_B0_P4_U0_CFG11 0x4001084bu +#define CYDEV_UCFG_B0_P4_U0_CFG12 0x4001084cu +#define CYDEV_UCFG_B0_P4_U0_CFG13 0x4001084du +#define CYDEV_UCFG_B0_P4_U0_CFG14 0x4001084eu +#define CYDEV_UCFG_B0_P4_U0_CFG15 0x4001084fu +#define CYDEV_UCFG_B0_P4_U0_CFG16 0x40010850u +#define CYDEV_UCFG_B0_P4_U0_CFG17 0x40010851u +#define CYDEV_UCFG_B0_P4_U0_CFG18 0x40010852u +#define CYDEV_UCFG_B0_P4_U0_CFG19 0x40010853u +#define CYDEV_UCFG_B0_P4_U0_CFG20 0x40010854u +#define CYDEV_UCFG_B0_P4_U0_CFG21 0x40010855u +#define CYDEV_UCFG_B0_P4_U0_CFG22 0x40010856u +#define CYDEV_UCFG_B0_P4_U0_CFG23 0x40010857u +#define CYDEV_UCFG_B0_P4_U0_CFG24 0x40010858u +#define CYDEV_UCFG_B0_P4_U0_CFG25 0x40010859u +#define CYDEV_UCFG_B0_P4_U0_CFG26 0x4001085au +#define CYDEV_UCFG_B0_P4_U0_CFG27 0x4001085bu +#define CYDEV_UCFG_B0_P4_U0_CFG28 0x4001085cu +#define CYDEV_UCFG_B0_P4_U0_CFG29 0x4001085du +#define CYDEV_UCFG_B0_P4_U0_CFG30 0x4001085eu +#define CYDEV_UCFG_B0_P4_U0_CFG31 0x4001085fu +#define CYDEV_UCFG_B0_P4_U0_DCFG0 0x40010860u +#define CYDEV_UCFG_B0_P4_U0_DCFG1 0x40010862u +#define CYDEV_UCFG_B0_P4_U0_DCFG2 0x40010864u +#define CYDEV_UCFG_B0_P4_U0_DCFG3 0x40010866u +#define CYDEV_UCFG_B0_P4_U0_DCFG4 0x40010868u +#define CYDEV_UCFG_B0_P4_U0_DCFG5 0x4001086au +#define CYDEV_UCFG_B0_P4_U0_DCFG6 0x4001086cu +#define CYDEV_UCFG_B0_P4_U0_DCFG7 0x4001086eu +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880u +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT0 0x40010880u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT1 0x40010884u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT2 0x40010888u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT3 0x4001088cu +#define CYDEV_UCFG_B0_P4_U1_PLD_IT4 0x40010890u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT5 0x40010894u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT6 0x40010898u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT7 0x4001089cu +#define CYDEV_UCFG_B0_P4_U1_PLD_IT8 0x400108a0u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT9 0x400108a4u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT10 0x400108a8u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT11 0x400108acu +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT0 0x400108b0u +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT1 0x400108b2u +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT2 0x400108b4u +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT3 0x400108b6u +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8u +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB 0x400108bau +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bcu +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS 0x400108beu +#define CYDEV_UCFG_B0_P4_U1_CFG0 0x400108c0u +#define CYDEV_UCFG_B0_P4_U1_CFG1 0x400108c1u +#define CYDEV_UCFG_B0_P4_U1_CFG2 0x400108c2u +#define CYDEV_UCFG_B0_P4_U1_CFG3 0x400108c3u +#define CYDEV_UCFG_B0_P4_U1_CFG4 0x400108c4u +#define CYDEV_UCFG_B0_P4_U1_CFG5 0x400108c5u +#define CYDEV_UCFG_B0_P4_U1_CFG6 0x400108c6u +#define CYDEV_UCFG_B0_P4_U1_CFG7 0x400108c7u +#define CYDEV_UCFG_B0_P4_U1_CFG8 0x400108c8u +#define CYDEV_UCFG_B0_P4_U1_CFG9 0x400108c9u +#define CYDEV_UCFG_B0_P4_U1_CFG10 0x400108cau +#define CYDEV_UCFG_B0_P4_U1_CFG11 0x400108cbu +#define CYDEV_UCFG_B0_P4_U1_CFG12 0x400108ccu +#define CYDEV_UCFG_B0_P4_U1_CFG13 0x400108cdu +#define CYDEV_UCFG_B0_P4_U1_CFG14 0x400108ceu +#define CYDEV_UCFG_B0_P4_U1_CFG15 0x400108cfu +#define CYDEV_UCFG_B0_P4_U1_CFG16 0x400108d0u +#define CYDEV_UCFG_B0_P4_U1_CFG17 0x400108d1u +#define CYDEV_UCFG_B0_P4_U1_CFG18 0x400108d2u +#define CYDEV_UCFG_B0_P4_U1_CFG19 0x400108d3u +#define CYDEV_UCFG_B0_P4_U1_CFG20 0x400108d4u +#define CYDEV_UCFG_B0_P4_U1_CFG21 0x400108d5u +#define CYDEV_UCFG_B0_P4_U1_CFG22 0x400108d6u +#define CYDEV_UCFG_B0_P4_U1_CFG23 0x400108d7u +#define CYDEV_UCFG_B0_P4_U1_CFG24 0x400108d8u +#define CYDEV_UCFG_B0_P4_U1_CFG25 0x400108d9u +#define CYDEV_UCFG_B0_P4_U1_CFG26 0x400108dau +#define CYDEV_UCFG_B0_P4_U1_CFG27 0x400108dbu +#define CYDEV_UCFG_B0_P4_U1_CFG28 0x400108dcu +#define CYDEV_UCFG_B0_P4_U1_CFG29 0x400108ddu +#define CYDEV_UCFG_B0_P4_U1_CFG30 0x400108deu +#define CYDEV_UCFG_B0_P4_U1_CFG31 0x400108dfu +#define CYDEV_UCFG_B0_P4_U1_DCFG0 0x400108e0u +#define CYDEV_UCFG_B0_P4_U1_DCFG1 0x400108e2u +#define CYDEV_UCFG_B0_P4_U1_DCFG2 0x400108e4u +#define CYDEV_UCFG_B0_P4_U1_DCFG3 0x400108e6u +#define CYDEV_UCFG_B0_P4_U1_DCFG4 0x400108e8u +#define CYDEV_UCFG_B0_P4_U1_DCFG5 0x400108eau +#define CYDEV_UCFG_B0_P4_U1_DCFG6 0x400108ecu +#define CYDEV_UCFG_B0_P4_U1_DCFG7 0x400108eeu +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900u +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT0 0x40010a00u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT1 0x40010a04u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT2 0x40010a08u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT3 0x40010a0cu +#define CYDEV_UCFG_B0_P5_U0_PLD_IT4 0x40010a10u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT5 0x40010a14u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT6 0x40010a18u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT7 0x40010a1cu +#define CYDEV_UCFG_B0_P5_U0_PLD_IT8 0x40010a20u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT9 0x40010a24u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT10 0x40010a28u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT11 0x40010a2cu +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT0 0x40010a30u +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT1 0x40010a32u +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT2 0x40010a34u +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT3 0x40010a36u +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38u +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB 0x40010a3au +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3cu +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3eu +#define CYDEV_UCFG_B0_P5_U0_CFG0 0x40010a40u +#define CYDEV_UCFG_B0_P5_U0_CFG1 0x40010a41u +#define CYDEV_UCFG_B0_P5_U0_CFG2 0x40010a42u +#define CYDEV_UCFG_B0_P5_U0_CFG3 0x40010a43u +#define CYDEV_UCFG_B0_P5_U0_CFG4 0x40010a44u +#define CYDEV_UCFG_B0_P5_U0_CFG5 0x40010a45u +#define CYDEV_UCFG_B0_P5_U0_CFG6 0x40010a46u +#define CYDEV_UCFG_B0_P5_U0_CFG7 0x40010a47u +#define CYDEV_UCFG_B0_P5_U0_CFG8 0x40010a48u +#define CYDEV_UCFG_B0_P5_U0_CFG9 0x40010a49u +#define CYDEV_UCFG_B0_P5_U0_CFG10 0x40010a4au +#define CYDEV_UCFG_B0_P5_U0_CFG11 0x40010a4bu +#define CYDEV_UCFG_B0_P5_U0_CFG12 0x40010a4cu +#define CYDEV_UCFG_B0_P5_U0_CFG13 0x40010a4du +#define CYDEV_UCFG_B0_P5_U0_CFG14 0x40010a4eu +#define CYDEV_UCFG_B0_P5_U0_CFG15 0x40010a4fu +#define CYDEV_UCFG_B0_P5_U0_CFG16 0x40010a50u +#define CYDEV_UCFG_B0_P5_U0_CFG17 0x40010a51u +#define CYDEV_UCFG_B0_P5_U0_CFG18 0x40010a52u +#define CYDEV_UCFG_B0_P5_U0_CFG19 0x40010a53u +#define CYDEV_UCFG_B0_P5_U0_CFG20 0x40010a54u +#define CYDEV_UCFG_B0_P5_U0_CFG21 0x40010a55u +#define CYDEV_UCFG_B0_P5_U0_CFG22 0x40010a56u +#define CYDEV_UCFG_B0_P5_U0_CFG23 0x40010a57u +#define CYDEV_UCFG_B0_P5_U0_CFG24 0x40010a58u +#define CYDEV_UCFG_B0_P5_U0_CFG25 0x40010a59u +#define CYDEV_UCFG_B0_P5_U0_CFG26 0x40010a5au +#define CYDEV_UCFG_B0_P5_U0_CFG27 0x40010a5bu +#define CYDEV_UCFG_B0_P5_U0_CFG28 0x40010a5cu +#define CYDEV_UCFG_B0_P5_U0_CFG29 0x40010a5du +#define CYDEV_UCFG_B0_P5_U0_CFG30 0x40010a5eu +#define CYDEV_UCFG_B0_P5_U0_CFG31 0x40010a5fu +#define CYDEV_UCFG_B0_P5_U0_DCFG0 0x40010a60u +#define CYDEV_UCFG_B0_P5_U0_DCFG1 0x40010a62u +#define CYDEV_UCFG_B0_P5_U0_DCFG2 0x40010a64u +#define CYDEV_UCFG_B0_P5_U0_DCFG3 0x40010a66u +#define CYDEV_UCFG_B0_P5_U0_DCFG4 0x40010a68u +#define CYDEV_UCFG_B0_P5_U0_DCFG5 0x40010a6au +#define CYDEV_UCFG_B0_P5_U0_DCFG6 0x40010a6cu +#define CYDEV_UCFG_B0_P5_U0_DCFG7 0x40010a6eu +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80u +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT0 0x40010a80u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT1 0x40010a84u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT2 0x40010a88u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT3 0x40010a8cu +#define CYDEV_UCFG_B0_P5_U1_PLD_IT4 0x40010a90u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT5 0x40010a94u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT6 0x40010a98u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT7 0x40010a9cu +#define CYDEV_UCFG_B0_P5_U1_PLD_IT8 0x40010aa0u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT9 0x40010aa4u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT10 0x40010aa8u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT11 0x40010aacu +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT0 0x40010ab0u +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT1 0x40010ab2u +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT2 0x40010ab4u +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT3 0x40010ab6u +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8u +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB 0x40010abau +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abcu +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS 0x40010abeu +#define CYDEV_UCFG_B0_P5_U1_CFG0 0x40010ac0u +#define CYDEV_UCFG_B0_P5_U1_CFG1 0x40010ac1u +#define CYDEV_UCFG_B0_P5_U1_CFG2 0x40010ac2u +#define CYDEV_UCFG_B0_P5_U1_CFG3 0x40010ac3u +#define CYDEV_UCFG_B0_P5_U1_CFG4 0x40010ac4u +#define CYDEV_UCFG_B0_P5_U1_CFG5 0x40010ac5u +#define CYDEV_UCFG_B0_P5_U1_CFG6 0x40010ac6u +#define CYDEV_UCFG_B0_P5_U1_CFG7 0x40010ac7u +#define CYDEV_UCFG_B0_P5_U1_CFG8 0x40010ac8u +#define CYDEV_UCFG_B0_P5_U1_CFG9 0x40010ac9u +#define CYDEV_UCFG_B0_P5_U1_CFG10 0x40010acau +#define CYDEV_UCFG_B0_P5_U1_CFG11 0x40010acbu +#define CYDEV_UCFG_B0_P5_U1_CFG12 0x40010accu +#define CYDEV_UCFG_B0_P5_U1_CFG13 0x40010acdu +#define CYDEV_UCFG_B0_P5_U1_CFG14 0x40010aceu +#define CYDEV_UCFG_B0_P5_U1_CFG15 0x40010acfu +#define CYDEV_UCFG_B0_P5_U1_CFG16 0x40010ad0u +#define CYDEV_UCFG_B0_P5_U1_CFG17 0x40010ad1u +#define CYDEV_UCFG_B0_P5_U1_CFG18 0x40010ad2u +#define CYDEV_UCFG_B0_P5_U1_CFG19 0x40010ad3u +#define CYDEV_UCFG_B0_P5_U1_CFG20 0x40010ad4u +#define CYDEV_UCFG_B0_P5_U1_CFG21 0x40010ad5u +#define CYDEV_UCFG_B0_P5_U1_CFG22 0x40010ad6u +#define CYDEV_UCFG_B0_P5_U1_CFG23 0x40010ad7u +#define CYDEV_UCFG_B0_P5_U1_CFG24 0x40010ad8u +#define CYDEV_UCFG_B0_P5_U1_CFG25 0x40010ad9u +#define CYDEV_UCFG_B0_P5_U1_CFG26 0x40010adau +#define CYDEV_UCFG_B0_P5_U1_CFG27 0x40010adbu +#define CYDEV_UCFG_B0_P5_U1_CFG28 0x40010adcu +#define CYDEV_UCFG_B0_P5_U1_CFG29 0x40010addu +#define CYDEV_UCFG_B0_P5_U1_CFG30 0x40010adeu +#define CYDEV_UCFG_B0_P5_U1_CFG31 0x40010adfu +#define CYDEV_UCFG_B0_P5_U1_DCFG0 0x40010ae0u +#define CYDEV_UCFG_B0_P5_U1_DCFG1 0x40010ae2u +#define CYDEV_UCFG_B0_P5_U1_DCFG2 0x40010ae4u +#define CYDEV_UCFG_B0_P5_U1_DCFG3 0x40010ae6u +#define CYDEV_UCFG_B0_P5_U1_DCFG4 0x40010ae8u +#define CYDEV_UCFG_B0_P5_U1_DCFG5 0x40010aeau +#define CYDEV_UCFG_B0_P5_U1_DCFG6 0x40010aecu +#define CYDEV_UCFG_B0_P5_U1_DCFG7 0x40010aeeu +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00u +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT0 0x40010c00u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT1 0x40010c04u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT2 0x40010c08u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT3 0x40010c0cu +#define CYDEV_UCFG_B0_P6_U0_PLD_IT4 0x40010c10u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT5 0x40010c14u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT6 0x40010c18u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT7 0x40010c1cu +#define CYDEV_UCFG_B0_P6_U0_PLD_IT8 0x40010c20u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT9 0x40010c24u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT10 0x40010c28u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT11 0x40010c2cu +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT0 0x40010c30u +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT1 0x40010c32u +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT2 0x40010c34u +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT3 0x40010c36u +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38u +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB 0x40010c3au +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3cu +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3eu +#define CYDEV_UCFG_B0_P6_U0_CFG0 0x40010c40u +#define CYDEV_UCFG_B0_P6_U0_CFG1 0x40010c41u +#define CYDEV_UCFG_B0_P6_U0_CFG2 0x40010c42u +#define CYDEV_UCFG_B0_P6_U0_CFG3 0x40010c43u +#define CYDEV_UCFG_B0_P6_U0_CFG4 0x40010c44u +#define CYDEV_UCFG_B0_P6_U0_CFG5 0x40010c45u +#define CYDEV_UCFG_B0_P6_U0_CFG6 0x40010c46u +#define CYDEV_UCFG_B0_P6_U0_CFG7 0x40010c47u +#define CYDEV_UCFG_B0_P6_U0_CFG8 0x40010c48u +#define CYDEV_UCFG_B0_P6_U0_CFG9 0x40010c49u +#define CYDEV_UCFG_B0_P6_U0_CFG10 0x40010c4au +#define CYDEV_UCFG_B0_P6_U0_CFG11 0x40010c4bu +#define CYDEV_UCFG_B0_P6_U0_CFG12 0x40010c4cu +#define CYDEV_UCFG_B0_P6_U0_CFG13 0x40010c4du +#define CYDEV_UCFG_B0_P6_U0_CFG14 0x40010c4eu +#define CYDEV_UCFG_B0_P6_U0_CFG15 0x40010c4fu +#define CYDEV_UCFG_B0_P6_U0_CFG16 0x40010c50u +#define CYDEV_UCFG_B0_P6_U0_CFG17 0x40010c51u +#define CYDEV_UCFG_B0_P6_U0_CFG18 0x40010c52u +#define CYDEV_UCFG_B0_P6_U0_CFG19 0x40010c53u +#define CYDEV_UCFG_B0_P6_U0_CFG20 0x40010c54u +#define CYDEV_UCFG_B0_P6_U0_CFG21 0x40010c55u +#define CYDEV_UCFG_B0_P6_U0_CFG22 0x40010c56u +#define CYDEV_UCFG_B0_P6_U0_CFG23 0x40010c57u +#define CYDEV_UCFG_B0_P6_U0_CFG24 0x40010c58u +#define CYDEV_UCFG_B0_P6_U0_CFG25 0x40010c59u +#define CYDEV_UCFG_B0_P6_U0_CFG26 0x40010c5au +#define CYDEV_UCFG_B0_P6_U0_CFG27 0x40010c5bu +#define CYDEV_UCFG_B0_P6_U0_CFG28 0x40010c5cu +#define CYDEV_UCFG_B0_P6_U0_CFG29 0x40010c5du +#define CYDEV_UCFG_B0_P6_U0_CFG30 0x40010c5eu +#define CYDEV_UCFG_B0_P6_U0_CFG31 0x40010c5fu +#define CYDEV_UCFG_B0_P6_U0_DCFG0 0x40010c60u +#define CYDEV_UCFG_B0_P6_U0_DCFG1 0x40010c62u +#define CYDEV_UCFG_B0_P6_U0_DCFG2 0x40010c64u +#define CYDEV_UCFG_B0_P6_U0_DCFG3 0x40010c66u +#define CYDEV_UCFG_B0_P6_U0_DCFG4 0x40010c68u +#define CYDEV_UCFG_B0_P6_U0_DCFG5 0x40010c6au +#define CYDEV_UCFG_B0_P6_U0_DCFG6 0x40010c6cu +#define CYDEV_UCFG_B0_P6_U0_DCFG7 0x40010c6eu +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80u +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT0 0x40010c80u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT1 0x40010c84u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT2 0x40010c88u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT3 0x40010c8cu +#define CYDEV_UCFG_B0_P6_U1_PLD_IT4 0x40010c90u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT5 0x40010c94u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT6 0x40010c98u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT7 0x40010c9cu +#define CYDEV_UCFG_B0_P6_U1_PLD_IT8 0x40010ca0u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT9 0x40010ca4u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT10 0x40010ca8u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT11 0x40010cacu +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT0 0x40010cb0u +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT1 0x40010cb2u +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT2 0x40010cb4u +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT3 0x40010cb6u +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8u +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB 0x40010cbau +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbcu +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbeu +#define CYDEV_UCFG_B0_P6_U1_CFG0 0x40010cc0u +#define CYDEV_UCFG_B0_P6_U1_CFG1 0x40010cc1u +#define CYDEV_UCFG_B0_P6_U1_CFG2 0x40010cc2u +#define CYDEV_UCFG_B0_P6_U1_CFG3 0x40010cc3u +#define CYDEV_UCFG_B0_P6_U1_CFG4 0x40010cc4u +#define CYDEV_UCFG_B0_P6_U1_CFG5 0x40010cc5u +#define CYDEV_UCFG_B0_P6_U1_CFG6 0x40010cc6u +#define CYDEV_UCFG_B0_P6_U1_CFG7 0x40010cc7u +#define CYDEV_UCFG_B0_P6_U1_CFG8 0x40010cc8u +#define CYDEV_UCFG_B0_P6_U1_CFG9 0x40010cc9u +#define CYDEV_UCFG_B0_P6_U1_CFG10 0x40010ccau +#define CYDEV_UCFG_B0_P6_U1_CFG11 0x40010ccbu +#define CYDEV_UCFG_B0_P6_U1_CFG12 0x40010cccu +#define CYDEV_UCFG_B0_P6_U1_CFG13 0x40010ccdu +#define CYDEV_UCFG_B0_P6_U1_CFG14 0x40010cceu +#define CYDEV_UCFG_B0_P6_U1_CFG15 0x40010ccfu +#define CYDEV_UCFG_B0_P6_U1_CFG16 0x40010cd0u +#define CYDEV_UCFG_B0_P6_U1_CFG17 0x40010cd1u +#define CYDEV_UCFG_B0_P6_U1_CFG18 0x40010cd2u +#define CYDEV_UCFG_B0_P6_U1_CFG19 0x40010cd3u +#define CYDEV_UCFG_B0_P6_U1_CFG20 0x40010cd4u +#define CYDEV_UCFG_B0_P6_U1_CFG21 0x40010cd5u +#define CYDEV_UCFG_B0_P6_U1_CFG22 0x40010cd6u +#define CYDEV_UCFG_B0_P6_U1_CFG23 0x40010cd7u +#define CYDEV_UCFG_B0_P6_U1_CFG24 0x40010cd8u +#define CYDEV_UCFG_B0_P6_U1_CFG25 0x40010cd9u +#define CYDEV_UCFG_B0_P6_U1_CFG26 0x40010cdau +#define CYDEV_UCFG_B0_P6_U1_CFG27 0x40010cdbu +#define CYDEV_UCFG_B0_P6_U1_CFG28 0x40010cdcu +#define CYDEV_UCFG_B0_P6_U1_CFG29 0x40010cddu +#define CYDEV_UCFG_B0_P6_U1_CFG30 0x40010cdeu +#define CYDEV_UCFG_B0_P6_U1_CFG31 0x40010cdfu +#define CYDEV_UCFG_B0_P6_U1_DCFG0 0x40010ce0u +#define CYDEV_UCFG_B0_P6_U1_DCFG1 0x40010ce2u +#define CYDEV_UCFG_B0_P6_U1_DCFG2 0x40010ce4u +#define CYDEV_UCFG_B0_P6_U1_DCFG3 0x40010ce6u +#define CYDEV_UCFG_B0_P6_U1_DCFG4 0x40010ce8u +#define CYDEV_UCFG_B0_P6_U1_DCFG5 0x40010ceau +#define CYDEV_UCFG_B0_P6_U1_DCFG6 0x40010cecu +#define CYDEV_UCFG_B0_P6_U1_DCFG7 0x40010ceeu +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00u +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT0 0x40010e00u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT1 0x40010e04u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT2 0x40010e08u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT3 0x40010e0cu +#define CYDEV_UCFG_B0_P7_U0_PLD_IT4 0x40010e10u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT5 0x40010e14u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT6 0x40010e18u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT7 0x40010e1cu +#define CYDEV_UCFG_B0_P7_U0_PLD_IT8 0x40010e20u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT9 0x40010e24u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT10 0x40010e28u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT11 0x40010e2cu +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT0 0x40010e30u +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT1 0x40010e32u +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT2 0x40010e34u +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT3 0x40010e36u +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38u +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB 0x40010e3au +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3cu +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3eu +#define CYDEV_UCFG_B0_P7_U0_CFG0 0x40010e40u +#define CYDEV_UCFG_B0_P7_U0_CFG1 0x40010e41u +#define CYDEV_UCFG_B0_P7_U0_CFG2 0x40010e42u +#define CYDEV_UCFG_B0_P7_U0_CFG3 0x40010e43u +#define CYDEV_UCFG_B0_P7_U0_CFG4 0x40010e44u +#define CYDEV_UCFG_B0_P7_U0_CFG5 0x40010e45u +#define CYDEV_UCFG_B0_P7_U0_CFG6 0x40010e46u +#define CYDEV_UCFG_B0_P7_U0_CFG7 0x40010e47u +#define CYDEV_UCFG_B0_P7_U0_CFG8 0x40010e48u +#define CYDEV_UCFG_B0_P7_U0_CFG9 0x40010e49u +#define CYDEV_UCFG_B0_P7_U0_CFG10 0x40010e4au +#define CYDEV_UCFG_B0_P7_U0_CFG11 0x40010e4bu +#define CYDEV_UCFG_B0_P7_U0_CFG12 0x40010e4cu +#define CYDEV_UCFG_B0_P7_U0_CFG13 0x40010e4du +#define CYDEV_UCFG_B0_P7_U0_CFG14 0x40010e4eu +#define CYDEV_UCFG_B0_P7_U0_CFG15 0x40010e4fu +#define CYDEV_UCFG_B0_P7_U0_CFG16 0x40010e50u +#define CYDEV_UCFG_B0_P7_U0_CFG17 0x40010e51u +#define CYDEV_UCFG_B0_P7_U0_CFG18 0x40010e52u +#define CYDEV_UCFG_B0_P7_U0_CFG19 0x40010e53u +#define CYDEV_UCFG_B0_P7_U0_CFG20 0x40010e54u +#define CYDEV_UCFG_B0_P7_U0_CFG21 0x40010e55u +#define CYDEV_UCFG_B0_P7_U0_CFG22 0x40010e56u +#define CYDEV_UCFG_B0_P7_U0_CFG23 0x40010e57u +#define CYDEV_UCFG_B0_P7_U0_CFG24 0x40010e58u +#define CYDEV_UCFG_B0_P7_U0_CFG25 0x40010e59u +#define CYDEV_UCFG_B0_P7_U0_CFG26 0x40010e5au +#define CYDEV_UCFG_B0_P7_U0_CFG27 0x40010e5bu +#define CYDEV_UCFG_B0_P7_U0_CFG28 0x40010e5cu +#define CYDEV_UCFG_B0_P7_U0_CFG29 0x40010e5du +#define CYDEV_UCFG_B0_P7_U0_CFG30 0x40010e5eu +#define CYDEV_UCFG_B0_P7_U0_CFG31 0x40010e5fu +#define CYDEV_UCFG_B0_P7_U0_DCFG0 0x40010e60u +#define CYDEV_UCFG_B0_P7_U0_DCFG1 0x40010e62u +#define CYDEV_UCFG_B0_P7_U0_DCFG2 0x40010e64u +#define CYDEV_UCFG_B0_P7_U0_DCFG3 0x40010e66u +#define CYDEV_UCFG_B0_P7_U0_DCFG4 0x40010e68u +#define CYDEV_UCFG_B0_P7_U0_DCFG5 0x40010e6au +#define CYDEV_UCFG_B0_P7_U0_DCFG6 0x40010e6cu +#define CYDEV_UCFG_B0_P7_U0_DCFG7 0x40010e6eu +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80u +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT0 0x40010e80u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT1 0x40010e84u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT2 0x40010e88u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT3 0x40010e8cu +#define CYDEV_UCFG_B0_P7_U1_PLD_IT4 0x40010e90u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT5 0x40010e94u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT6 0x40010e98u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT7 0x40010e9cu +#define CYDEV_UCFG_B0_P7_U1_PLD_IT8 0x40010ea0u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT9 0x40010ea4u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT10 0x40010ea8u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT11 0x40010eacu +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT0 0x40010eb0u +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT1 0x40010eb2u +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT2 0x40010eb4u +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT3 0x40010eb6u +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8u +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB 0x40010ebau +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebcu +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebeu +#define CYDEV_UCFG_B0_P7_U1_CFG0 0x40010ec0u +#define CYDEV_UCFG_B0_P7_U1_CFG1 0x40010ec1u +#define CYDEV_UCFG_B0_P7_U1_CFG2 0x40010ec2u +#define CYDEV_UCFG_B0_P7_U1_CFG3 0x40010ec3u +#define CYDEV_UCFG_B0_P7_U1_CFG4 0x40010ec4u +#define CYDEV_UCFG_B0_P7_U1_CFG5 0x40010ec5u +#define CYDEV_UCFG_B0_P7_U1_CFG6 0x40010ec6u +#define CYDEV_UCFG_B0_P7_U1_CFG7 0x40010ec7u +#define CYDEV_UCFG_B0_P7_U1_CFG8 0x40010ec8u +#define CYDEV_UCFG_B0_P7_U1_CFG9 0x40010ec9u +#define CYDEV_UCFG_B0_P7_U1_CFG10 0x40010ecau +#define CYDEV_UCFG_B0_P7_U1_CFG11 0x40010ecbu +#define CYDEV_UCFG_B0_P7_U1_CFG12 0x40010eccu +#define CYDEV_UCFG_B0_P7_U1_CFG13 0x40010ecdu +#define CYDEV_UCFG_B0_P7_U1_CFG14 0x40010eceu +#define CYDEV_UCFG_B0_P7_U1_CFG15 0x40010ecfu +#define CYDEV_UCFG_B0_P7_U1_CFG16 0x40010ed0u +#define CYDEV_UCFG_B0_P7_U1_CFG17 0x40010ed1u +#define CYDEV_UCFG_B0_P7_U1_CFG18 0x40010ed2u +#define CYDEV_UCFG_B0_P7_U1_CFG19 0x40010ed3u +#define CYDEV_UCFG_B0_P7_U1_CFG20 0x40010ed4u +#define CYDEV_UCFG_B0_P7_U1_CFG21 0x40010ed5u +#define CYDEV_UCFG_B0_P7_U1_CFG22 0x40010ed6u +#define CYDEV_UCFG_B0_P7_U1_CFG23 0x40010ed7u +#define CYDEV_UCFG_B0_P7_U1_CFG24 0x40010ed8u +#define CYDEV_UCFG_B0_P7_U1_CFG25 0x40010ed9u +#define CYDEV_UCFG_B0_P7_U1_CFG26 0x40010edau +#define CYDEV_UCFG_B0_P7_U1_CFG27 0x40010edbu +#define CYDEV_UCFG_B0_P7_U1_CFG28 0x40010edcu +#define CYDEV_UCFG_B0_P7_U1_CFG29 0x40010eddu +#define CYDEV_UCFG_B0_P7_U1_CFG30 0x40010edeu +#define CYDEV_UCFG_B0_P7_U1_CFG31 0x40010edfu +#define CYDEV_UCFG_B0_P7_U1_DCFG0 0x40010ee0u +#define CYDEV_UCFG_B0_P7_U1_DCFG1 0x40010ee2u +#define CYDEV_UCFG_B0_P7_U1_DCFG2 0x40010ee4u +#define CYDEV_UCFG_B0_P7_U1_DCFG3 0x40010ee6u +#define CYDEV_UCFG_B0_P7_U1_DCFG4 0x40010ee8u +#define CYDEV_UCFG_B0_P7_U1_DCFG5 0x40010eeau +#define CYDEV_UCFG_B0_P7_U1_DCFG6 0x40010eecu +#define CYDEV_UCFG_B0_P7_U1_DCFG7 0x40010eeeu +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00u +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_BASE 0x40011000u +#define CYDEV_UCFG_B1_SIZE 0x00000fefu +#define CYDEV_UCFG_B1_P2_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT0 0x40011400u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT1 0x40011404u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT2 0x40011408u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT3 0x4001140cu +#define CYDEV_UCFG_B1_P2_U0_PLD_IT4 0x40011410u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT5 0x40011414u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT6 0x40011418u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT7 0x4001141cu +#define CYDEV_UCFG_B1_P2_U0_PLD_IT8 0x40011420u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT9 0x40011424u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT10 0x40011428u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT11 0x4001142cu +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT0 0x40011430u +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT1 0x40011432u +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT2 0x40011434u +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT3 0x40011436u +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438u +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB 0x4001143au +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143cu +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS 0x4001143eu +#define CYDEV_UCFG_B1_P2_U0_CFG0 0x40011440u +#define CYDEV_UCFG_B1_P2_U0_CFG1 0x40011441u +#define CYDEV_UCFG_B1_P2_U0_CFG2 0x40011442u +#define CYDEV_UCFG_B1_P2_U0_CFG3 0x40011443u +#define CYDEV_UCFG_B1_P2_U0_CFG4 0x40011444u +#define CYDEV_UCFG_B1_P2_U0_CFG5 0x40011445u +#define CYDEV_UCFG_B1_P2_U0_CFG6 0x40011446u +#define CYDEV_UCFG_B1_P2_U0_CFG7 0x40011447u +#define CYDEV_UCFG_B1_P2_U0_CFG8 0x40011448u +#define CYDEV_UCFG_B1_P2_U0_CFG9 0x40011449u +#define CYDEV_UCFG_B1_P2_U0_CFG10 0x4001144au +#define CYDEV_UCFG_B1_P2_U0_CFG11 0x4001144bu +#define CYDEV_UCFG_B1_P2_U0_CFG12 0x4001144cu +#define CYDEV_UCFG_B1_P2_U0_CFG13 0x4001144du +#define CYDEV_UCFG_B1_P2_U0_CFG14 0x4001144eu +#define CYDEV_UCFG_B1_P2_U0_CFG15 0x4001144fu +#define CYDEV_UCFG_B1_P2_U0_CFG16 0x40011450u +#define CYDEV_UCFG_B1_P2_U0_CFG17 0x40011451u +#define CYDEV_UCFG_B1_P2_U0_CFG18 0x40011452u +#define CYDEV_UCFG_B1_P2_U0_CFG19 0x40011453u +#define CYDEV_UCFG_B1_P2_U0_CFG20 0x40011454u +#define CYDEV_UCFG_B1_P2_U0_CFG21 0x40011455u +#define CYDEV_UCFG_B1_P2_U0_CFG22 0x40011456u +#define CYDEV_UCFG_B1_P2_U0_CFG23 0x40011457u +#define CYDEV_UCFG_B1_P2_U0_CFG24 0x40011458u +#define CYDEV_UCFG_B1_P2_U0_CFG25 0x40011459u +#define CYDEV_UCFG_B1_P2_U0_CFG26 0x4001145au +#define CYDEV_UCFG_B1_P2_U0_CFG27 0x4001145bu +#define CYDEV_UCFG_B1_P2_U0_CFG28 0x4001145cu +#define CYDEV_UCFG_B1_P2_U0_CFG29 0x4001145du +#define CYDEV_UCFG_B1_P2_U0_CFG30 0x4001145eu +#define CYDEV_UCFG_B1_P2_U0_CFG31 0x4001145fu +#define CYDEV_UCFG_B1_P2_U0_DCFG0 0x40011460u +#define CYDEV_UCFG_B1_P2_U0_DCFG1 0x40011462u +#define CYDEV_UCFG_B1_P2_U0_DCFG2 0x40011464u +#define CYDEV_UCFG_B1_P2_U0_DCFG3 0x40011466u +#define CYDEV_UCFG_B1_P2_U0_DCFG4 0x40011468u +#define CYDEV_UCFG_B1_P2_U0_DCFG5 0x4001146au +#define CYDEV_UCFG_B1_P2_U0_DCFG6 0x4001146cu +#define CYDEV_UCFG_B1_P2_U0_DCFG7 0x4001146eu +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480u +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT0 0x40011480u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT1 0x40011484u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT2 0x40011488u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT3 0x4001148cu +#define CYDEV_UCFG_B1_P2_U1_PLD_IT4 0x40011490u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT5 0x40011494u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT6 0x40011498u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT7 0x4001149cu +#define CYDEV_UCFG_B1_P2_U1_PLD_IT8 0x400114a0u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT9 0x400114a4u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT10 0x400114a8u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT11 0x400114acu +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT0 0x400114b0u +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT1 0x400114b2u +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT2 0x400114b4u +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT3 0x400114b6u +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8u +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB 0x400114bau +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bcu +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS 0x400114beu +#define CYDEV_UCFG_B1_P2_U1_CFG0 0x400114c0u +#define CYDEV_UCFG_B1_P2_U1_CFG1 0x400114c1u +#define CYDEV_UCFG_B1_P2_U1_CFG2 0x400114c2u +#define CYDEV_UCFG_B1_P2_U1_CFG3 0x400114c3u +#define CYDEV_UCFG_B1_P2_U1_CFG4 0x400114c4u +#define CYDEV_UCFG_B1_P2_U1_CFG5 0x400114c5u +#define CYDEV_UCFG_B1_P2_U1_CFG6 0x400114c6u +#define CYDEV_UCFG_B1_P2_U1_CFG7 0x400114c7u +#define CYDEV_UCFG_B1_P2_U1_CFG8 0x400114c8u +#define CYDEV_UCFG_B1_P2_U1_CFG9 0x400114c9u +#define CYDEV_UCFG_B1_P2_U1_CFG10 0x400114cau +#define CYDEV_UCFG_B1_P2_U1_CFG11 0x400114cbu +#define CYDEV_UCFG_B1_P2_U1_CFG12 0x400114ccu +#define CYDEV_UCFG_B1_P2_U1_CFG13 0x400114cdu +#define CYDEV_UCFG_B1_P2_U1_CFG14 0x400114ceu +#define CYDEV_UCFG_B1_P2_U1_CFG15 0x400114cfu +#define CYDEV_UCFG_B1_P2_U1_CFG16 0x400114d0u +#define CYDEV_UCFG_B1_P2_U1_CFG17 0x400114d1u +#define CYDEV_UCFG_B1_P2_U1_CFG18 0x400114d2u +#define CYDEV_UCFG_B1_P2_U1_CFG19 0x400114d3u +#define CYDEV_UCFG_B1_P2_U1_CFG20 0x400114d4u +#define CYDEV_UCFG_B1_P2_U1_CFG21 0x400114d5u +#define CYDEV_UCFG_B1_P2_U1_CFG22 0x400114d6u +#define CYDEV_UCFG_B1_P2_U1_CFG23 0x400114d7u +#define CYDEV_UCFG_B1_P2_U1_CFG24 0x400114d8u +#define CYDEV_UCFG_B1_P2_U1_CFG25 0x400114d9u +#define CYDEV_UCFG_B1_P2_U1_CFG26 0x400114dau +#define CYDEV_UCFG_B1_P2_U1_CFG27 0x400114dbu +#define CYDEV_UCFG_B1_P2_U1_CFG28 0x400114dcu +#define CYDEV_UCFG_B1_P2_U1_CFG29 0x400114ddu +#define CYDEV_UCFG_B1_P2_U1_CFG30 0x400114deu +#define CYDEV_UCFG_B1_P2_U1_CFG31 0x400114dfu +#define CYDEV_UCFG_B1_P2_U1_DCFG0 0x400114e0u +#define CYDEV_UCFG_B1_P2_U1_DCFG1 0x400114e2u +#define CYDEV_UCFG_B1_P2_U1_DCFG2 0x400114e4u +#define CYDEV_UCFG_B1_P2_U1_DCFG3 0x400114e6u +#define CYDEV_UCFG_B1_P2_U1_DCFG4 0x400114e8u +#define CYDEV_UCFG_B1_P2_U1_DCFG5 0x400114eau +#define CYDEV_UCFG_B1_P2_U1_DCFG6 0x400114ecu +#define CYDEV_UCFG_B1_P2_U1_DCFG7 0x400114eeu +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500u +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P3_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT0 0x40011600u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT1 0x40011604u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT2 0x40011608u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT3 0x4001160cu +#define CYDEV_UCFG_B1_P3_U0_PLD_IT4 0x40011610u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT5 0x40011614u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT6 0x40011618u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT7 0x4001161cu +#define CYDEV_UCFG_B1_P3_U0_PLD_IT8 0x40011620u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT9 0x40011624u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT10 0x40011628u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT11 0x4001162cu +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT0 0x40011630u +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT1 0x40011632u +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT2 0x40011634u +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT3 0x40011636u +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638u +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB 0x4001163au +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163cu +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS 0x4001163eu +#define CYDEV_UCFG_B1_P3_U0_CFG0 0x40011640u +#define CYDEV_UCFG_B1_P3_U0_CFG1 0x40011641u +#define CYDEV_UCFG_B1_P3_U0_CFG2 0x40011642u +#define CYDEV_UCFG_B1_P3_U0_CFG3 0x40011643u +#define CYDEV_UCFG_B1_P3_U0_CFG4 0x40011644u +#define CYDEV_UCFG_B1_P3_U0_CFG5 0x40011645u +#define CYDEV_UCFG_B1_P3_U0_CFG6 0x40011646u +#define CYDEV_UCFG_B1_P3_U0_CFG7 0x40011647u +#define CYDEV_UCFG_B1_P3_U0_CFG8 0x40011648u +#define CYDEV_UCFG_B1_P3_U0_CFG9 0x40011649u +#define CYDEV_UCFG_B1_P3_U0_CFG10 0x4001164au +#define CYDEV_UCFG_B1_P3_U0_CFG11 0x4001164bu +#define CYDEV_UCFG_B1_P3_U0_CFG12 0x4001164cu +#define CYDEV_UCFG_B1_P3_U0_CFG13 0x4001164du +#define CYDEV_UCFG_B1_P3_U0_CFG14 0x4001164eu +#define CYDEV_UCFG_B1_P3_U0_CFG15 0x4001164fu +#define CYDEV_UCFG_B1_P3_U0_CFG16 0x40011650u +#define CYDEV_UCFG_B1_P3_U0_CFG17 0x40011651u +#define CYDEV_UCFG_B1_P3_U0_CFG18 0x40011652u +#define CYDEV_UCFG_B1_P3_U0_CFG19 0x40011653u +#define CYDEV_UCFG_B1_P3_U0_CFG20 0x40011654u +#define CYDEV_UCFG_B1_P3_U0_CFG21 0x40011655u +#define CYDEV_UCFG_B1_P3_U0_CFG22 0x40011656u +#define CYDEV_UCFG_B1_P3_U0_CFG23 0x40011657u +#define CYDEV_UCFG_B1_P3_U0_CFG24 0x40011658u +#define CYDEV_UCFG_B1_P3_U0_CFG25 0x40011659u +#define CYDEV_UCFG_B1_P3_U0_CFG26 0x4001165au +#define CYDEV_UCFG_B1_P3_U0_CFG27 0x4001165bu +#define CYDEV_UCFG_B1_P3_U0_CFG28 0x4001165cu +#define CYDEV_UCFG_B1_P3_U0_CFG29 0x4001165du +#define CYDEV_UCFG_B1_P3_U0_CFG30 0x4001165eu +#define CYDEV_UCFG_B1_P3_U0_CFG31 0x4001165fu +#define CYDEV_UCFG_B1_P3_U0_DCFG0 0x40011660u +#define CYDEV_UCFG_B1_P3_U0_DCFG1 0x40011662u +#define CYDEV_UCFG_B1_P3_U0_DCFG2 0x40011664u +#define CYDEV_UCFG_B1_P3_U0_DCFG3 0x40011666u +#define CYDEV_UCFG_B1_P3_U0_DCFG4 0x40011668u +#define CYDEV_UCFG_B1_P3_U0_DCFG5 0x4001166au +#define CYDEV_UCFG_B1_P3_U0_DCFG6 0x4001166cu +#define CYDEV_UCFG_B1_P3_U0_DCFG7 0x4001166eu +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680u +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT0 0x40011680u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT1 0x40011684u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT2 0x40011688u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT3 0x4001168cu +#define CYDEV_UCFG_B1_P3_U1_PLD_IT4 0x40011690u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT5 0x40011694u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT6 0x40011698u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT7 0x4001169cu +#define CYDEV_UCFG_B1_P3_U1_PLD_IT8 0x400116a0u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT9 0x400116a4u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT10 0x400116a8u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT11 0x400116acu +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT0 0x400116b0u +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT1 0x400116b2u +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT2 0x400116b4u +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT3 0x400116b6u +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8u +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB 0x400116bau +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bcu +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS 0x400116beu +#define CYDEV_UCFG_B1_P3_U1_CFG0 0x400116c0u +#define CYDEV_UCFG_B1_P3_U1_CFG1 0x400116c1u +#define CYDEV_UCFG_B1_P3_U1_CFG2 0x400116c2u +#define CYDEV_UCFG_B1_P3_U1_CFG3 0x400116c3u +#define CYDEV_UCFG_B1_P3_U1_CFG4 0x400116c4u +#define CYDEV_UCFG_B1_P3_U1_CFG5 0x400116c5u +#define CYDEV_UCFG_B1_P3_U1_CFG6 0x400116c6u +#define CYDEV_UCFG_B1_P3_U1_CFG7 0x400116c7u +#define CYDEV_UCFG_B1_P3_U1_CFG8 0x400116c8u +#define CYDEV_UCFG_B1_P3_U1_CFG9 0x400116c9u +#define CYDEV_UCFG_B1_P3_U1_CFG10 0x400116cau +#define CYDEV_UCFG_B1_P3_U1_CFG11 0x400116cbu +#define CYDEV_UCFG_B1_P3_U1_CFG12 0x400116ccu +#define CYDEV_UCFG_B1_P3_U1_CFG13 0x400116cdu +#define CYDEV_UCFG_B1_P3_U1_CFG14 0x400116ceu +#define CYDEV_UCFG_B1_P3_U1_CFG15 0x400116cfu +#define CYDEV_UCFG_B1_P3_U1_CFG16 0x400116d0u +#define CYDEV_UCFG_B1_P3_U1_CFG17 0x400116d1u +#define CYDEV_UCFG_B1_P3_U1_CFG18 0x400116d2u +#define CYDEV_UCFG_B1_P3_U1_CFG19 0x400116d3u +#define CYDEV_UCFG_B1_P3_U1_CFG20 0x400116d4u +#define CYDEV_UCFG_B1_P3_U1_CFG21 0x400116d5u +#define CYDEV_UCFG_B1_P3_U1_CFG22 0x400116d6u +#define CYDEV_UCFG_B1_P3_U1_CFG23 0x400116d7u +#define CYDEV_UCFG_B1_P3_U1_CFG24 0x400116d8u +#define CYDEV_UCFG_B1_P3_U1_CFG25 0x400116d9u +#define CYDEV_UCFG_B1_P3_U1_CFG26 0x400116dau +#define CYDEV_UCFG_B1_P3_U1_CFG27 0x400116dbu +#define CYDEV_UCFG_B1_P3_U1_CFG28 0x400116dcu +#define CYDEV_UCFG_B1_P3_U1_CFG29 0x400116ddu +#define CYDEV_UCFG_B1_P3_U1_CFG30 0x400116deu +#define CYDEV_UCFG_B1_P3_U1_CFG31 0x400116dfu +#define CYDEV_UCFG_B1_P3_U1_DCFG0 0x400116e0u +#define CYDEV_UCFG_B1_P3_U1_DCFG1 0x400116e2u +#define CYDEV_UCFG_B1_P3_U1_DCFG2 0x400116e4u +#define CYDEV_UCFG_B1_P3_U1_DCFG3 0x400116e6u +#define CYDEV_UCFG_B1_P3_U1_DCFG4 0x400116e8u +#define CYDEV_UCFG_B1_P3_U1_DCFG5 0x400116eau +#define CYDEV_UCFG_B1_P3_U1_DCFG6 0x400116ecu +#define CYDEV_UCFG_B1_P3_U1_DCFG7 0x400116eeu +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700u +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P4_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT0 0x40011800u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT1 0x40011804u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT2 0x40011808u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT3 0x4001180cu +#define CYDEV_UCFG_B1_P4_U0_PLD_IT4 0x40011810u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT5 0x40011814u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT6 0x40011818u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT7 0x4001181cu +#define CYDEV_UCFG_B1_P4_U0_PLD_IT8 0x40011820u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT9 0x40011824u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT10 0x40011828u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT11 0x4001182cu +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT0 0x40011830u +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT1 0x40011832u +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT2 0x40011834u +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT3 0x40011836u +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838u +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB 0x4001183au +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183cu +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS 0x4001183eu +#define CYDEV_UCFG_B1_P4_U0_CFG0 0x40011840u +#define CYDEV_UCFG_B1_P4_U0_CFG1 0x40011841u +#define CYDEV_UCFG_B1_P4_U0_CFG2 0x40011842u +#define CYDEV_UCFG_B1_P4_U0_CFG3 0x40011843u +#define CYDEV_UCFG_B1_P4_U0_CFG4 0x40011844u +#define CYDEV_UCFG_B1_P4_U0_CFG5 0x40011845u +#define CYDEV_UCFG_B1_P4_U0_CFG6 0x40011846u +#define CYDEV_UCFG_B1_P4_U0_CFG7 0x40011847u +#define CYDEV_UCFG_B1_P4_U0_CFG8 0x40011848u +#define CYDEV_UCFG_B1_P4_U0_CFG9 0x40011849u +#define CYDEV_UCFG_B1_P4_U0_CFG10 0x4001184au +#define CYDEV_UCFG_B1_P4_U0_CFG11 0x4001184bu +#define CYDEV_UCFG_B1_P4_U0_CFG12 0x4001184cu +#define CYDEV_UCFG_B1_P4_U0_CFG13 0x4001184du +#define CYDEV_UCFG_B1_P4_U0_CFG14 0x4001184eu +#define CYDEV_UCFG_B1_P4_U0_CFG15 0x4001184fu +#define CYDEV_UCFG_B1_P4_U0_CFG16 0x40011850u +#define CYDEV_UCFG_B1_P4_U0_CFG17 0x40011851u +#define CYDEV_UCFG_B1_P4_U0_CFG18 0x40011852u +#define CYDEV_UCFG_B1_P4_U0_CFG19 0x40011853u +#define CYDEV_UCFG_B1_P4_U0_CFG20 0x40011854u +#define CYDEV_UCFG_B1_P4_U0_CFG21 0x40011855u +#define CYDEV_UCFG_B1_P4_U0_CFG22 0x40011856u +#define CYDEV_UCFG_B1_P4_U0_CFG23 0x40011857u +#define CYDEV_UCFG_B1_P4_U0_CFG24 0x40011858u +#define CYDEV_UCFG_B1_P4_U0_CFG25 0x40011859u +#define CYDEV_UCFG_B1_P4_U0_CFG26 0x4001185au +#define CYDEV_UCFG_B1_P4_U0_CFG27 0x4001185bu +#define CYDEV_UCFG_B1_P4_U0_CFG28 0x4001185cu +#define CYDEV_UCFG_B1_P4_U0_CFG29 0x4001185du +#define CYDEV_UCFG_B1_P4_U0_CFG30 0x4001185eu +#define CYDEV_UCFG_B1_P4_U0_CFG31 0x4001185fu +#define CYDEV_UCFG_B1_P4_U0_DCFG0 0x40011860u +#define CYDEV_UCFG_B1_P4_U0_DCFG1 0x40011862u +#define CYDEV_UCFG_B1_P4_U0_DCFG2 0x40011864u +#define CYDEV_UCFG_B1_P4_U0_DCFG3 0x40011866u +#define CYDEV_UCFG_B1_P4_U0_DCFG4 0x40011868u +#define CYDEV_UCFG_B1_P4_U0_DCFG5 0x4001186au +#define CYDEV_UCFG_B1_P4_U0_DCFG6 0x4001186cu +#define CYDEV_UCFG_B1_P4_U0_DCFG7 0x4001186eu +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880u +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT0 0x40011880u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT1 0x40011884u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT2 0x40011888u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT3 0x4001188cu +#define CYDEV_UCFG_B1_P4_U1_PLD_IT4 0x40011890u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT5 0x40011894u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT6 0x40011898u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT7 0x4001189cu +#define CYDEV_UCFG_B1_P4_U1_PLD_IT8 0x400118a0u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT9 0x400118a4u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT10 0x400118a8u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT11 0x400118acu +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT0 0x400118b0u +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT1 0x400118b2u +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT2 0x400118b4u +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT3 0x400118b6u +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8u +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB 0x400118bau +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bcu +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS 0x400118beu +#define CYDEV_UCFG_B1_P4_U1_CFG0 0x400118c0u +#define CYDEV_UCFG_B1_P4_U1_CFG1 0x400118c1u +#define CYDEV_UCFG_B1_P4_U1_CFG2 0x400118c2u +#define CYDEV_UCFG_B1_P4_U1_CFG3 0x400118c3u +#define CYDEV_UCFG_B1_P4_U1_CFG4 0x400118c4u +#define CYDEV_UCFG_B1_P4_U1_CFG5 0x400118c5u +#define CYDEV_UCFG_B1_P4_U1_CFG6 0x400118c6u +#define CYDEV_UCFG_B1_P4_U1_CFG7 0x400118c7u +#define CYDEV_UCFG_B1_P4_U1_CFG8 0x400118c8u +#define CYDEV_UCFG_B1_P4_U1_CFG9 0x400118c9u +#define CYDEV_UCFG_B1_P4_U1_CFG10 0x400118cau +#define CYDEV_UCFG_B1_P4_U1_CFG11 0x400118cbu +#define CYDEV_UCFG_B1_P4_U1_CFG12 0x400118ccu +#define CYDEV_UCFG_B1_P4_U1_CFG13 0x400118cdu +#define CYDEV_UCFG_B1_P4_U1_CFG14 0x400118ceu +#define CYDEV_UCFG_B1_P4_U1_CFG15 0x400118cfu +#define CYDEV_UCFG_B1_P4_U1_CFG16 0x400118d0u +#define CYDEV_UCFG_B1_P4_U1_CFG17 0x400118d1u +#define CYDEV_UCFG_B1_P4_U1_CFG18 0x400118d2u +#define CYDEV_UCFG_B1_P4_U1_CFG19 0x400118d3u +#define CYDEV_UCFG_B1_P4_U1_CFG20 0x400118d4u +#define CYDEV_UCFG_B1_P4_U1_CFG21 0x400118d5u +#define CYDEV_UCFG_B1_P4_U1_CFG22 0x400118d6u +#define CYDEV_UCFG_B1_P4_U1_CFG23 0x400118d7u +#define CYDEV_UCFG_B1_P4_U1_CFG24 0x400118d8u +#define CYDEV_UCFG_B1_P4_U1_CFG25 0x400118d9u +#define CYDEV_UCFG_B1_P4_U1_CFG26 0x400118dau +#define CYDEV_UCFG_B1_P4_U1_CFG27 0x400118dbu +#define CYDEV_UCFG_B1_P4_U1_CFG28 0x400118dcu +#define CYDEV_UCFG_B1_P4_U1_CFG29 0x400118ddu +#define CYDEV_UCFG_B1_P4_U1_CFG30 0x400118deu +#define CYDEV_UCFG_B1_P4_U1_CFG31 0x400118dfu +#define CYDEV_UCFG_B1_P4_U1_DCFG0 0x400118e0u +#define CYDEV_UCFG_B1_P4_U1_DCFG1 0x400118e2u +#define CYDEV_UCFG_B1_P4_U1_DCFG2 0x400118e4u +#define CYDEV_UCFG_B1_P4_U1_DCFG3 0x400118e6u +#define CYDEV_UCFG_B1_P4_U1_DCFG4 0x400118e8u +#define CYDEV_UCFG_B1_P4_U1_DCFG5 0x400118eau +#define CYDEV_UCFG_B1_P4_U1_DCFG6 0x400118ecu +#define CYDEV_UCFG_B1_P4_U1_DCFG7 0x400118eeu +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900u +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT0 0x40011a00u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT1 0x40011a04u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT2 0x40011a08u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT3 0x40011a0cu +#define CYDEV_UCFG_B1_P5_U0_PLD_IT4 0x40011a10u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT5 0x40011a14u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT6 0x40011a18u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT7 0x40011a1cu +#define CYDEV_UCFG_B1_P5_U0_PLD_IT8 0x40011a20u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT9 0x40011a24u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT10 0x40011a28u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT11 0x40011a2cu +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT0 0x40011a30u +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT1 0x40011a32u +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT2 0x40011a34u +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT3 0x40011a36u +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38u +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB 0x40011a3au +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3cu +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3eu +#define CYDEV_UCFG_B1_P5_U0_CFG0 0x40011a40u +#define CYDEV_UCFG_B1_P5_U0_CFG1 0x40011a41u +#define CYDEV_UCFG_B1_P5_U0_CFG2 0x40011a42u +#define CYDEV_UCFG_B1_P5_U0_CFG3 0x40011a43u +#define CYDEV_UCFG_B1_P5_U0_CFG4 0x40011a44u +#define CYDEV_UCFG_B1_P5_U0_CFG5 0x40011a45u +#define CYDEV_UCFG_B1_P5_U0_CFG6 0x40011a46u +#define CYDEV_UCFG_B1_P5_U0_CFG7 0x40011a47u +#define CYDEV_UCFG_B1_P5_U0_CFG8 0x40011a48u +#define CYDEV_UCFG_B1_P5_U0_CFG9 0x40011a49u +#define CYDEV_UCFG_B1_P5_U0_CFG10 0x40011a4au +#define CYDEV_UCFG_B1_P5_U0_CFG11 0x40011a4bu +#define CYDEV_UCFG_B1_P5_U0_CFG12 0x40011a4cu +#define CYDEV_UCFG_B1_P5_U0_CFG13 0x40011a4du +#define CYDEV_UCFG_B1_P5_U0_CFG14 0x40011a4eu +#define CYDEV_UCFG_B1_P5_U0_CFG15 0x40011a4fu +#define CYDEV_UCFG_B1_P5_U0_CFG16 0x40011a50u +#define CYDEV_UCFG_B1_P5_U0_CFG17 0x40011a51u +#define CYDEV_UCFG_B1_P5_U0_CFG18 0x40011a52u +#define CYDEV_UCFG_B1_P5_U0_CFG19 0x40011a53u +#define CYDEV_UCFG_B1_P5_U0_CFG20 0x40011a54u +#define CYDEV_UCFG_B1_P5_U0_CFG21 0x40011a55u +#define CYDEV_UCFG_B1_P5_U0_CFG22 0x40011a56u +#define CYDEV_UCFG_B1_P5_U0_CFG23 0x40011a57u +#define CYDEV_UCFG_B1_P5_U0_CFG24 0x40011a58u +#define CYDEV_UCFG_B1_P5_U0_CFG25 0x40011a59u +#define CYDEV_UCFG_B1_P5_U0_CFG26 0x40011a5au +#define CYDEV_UCFG_B1_P5_U0_CFG27 0x40011a5bu +#define CYDEV_UCFG_B1_P5_U0_CFG28 0x40011a5cu +#define CYDEV_UCFG_B1_P5_U0_CFG29 0x40011a5du +#define CYDEV_UCFG_B1_P5_U0_CFG30 0x40011a5eu +#define CYDEV_UCFG_B1_P5_U0_CFG31 0x40011a5fu +#define CYDEV_UCFG_B1_P5_U0_DCFG0 0x40011a60u +#define CYDEV_UCFG_B1_P5_U0_DCFG1 0x40011a62u +#define CYDEV_UCFG_B1_P5_U0_DCFG2 0x40011a64u +#define CYDEV_UCFG_B1_P5_U0_DCFG3 0x40011a66u +#define CYDEV_UCFG_B1_P5_U0_DCFG4 0x40011a68u +#define CYDEV_UCFG_B1_P5_U0_DCFG5 0x40011a6au +#define CYDEV_UCFG_B1_P5_U0_DCFG6 0x40011a6cu +#define CYDEV_UCFG_B1_P5_U0_DCFG7 0x40011a6eu +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80u +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT0 0x40011a80u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT1 0x40011a84u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT2 0x40011a88u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT3 0x40011a8cu +#define CYDEV_UCFG_B1_P5_U1_PLD_IT4 0x40011a90u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT5 0x40011a94u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT6 0x40011a98u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT7 0x40011a9cu +#define CYDEV_UCFG_B1_P5_U1_PLD_IT8 0x40011aa0u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT9 0x40011aa4u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT10 0x40011aa8u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT11 0x40011aacu +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT0 0x40011ab0u +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT1 0x40011ab2u +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT2 0x40011ab4u +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT3 0x40011ab6u +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8u +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB 0x40011abau +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abcu +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS 0x40011abeu +#define CYDEV_UCFG_B1_P5_U1_CFG0 0x40011ac0u +#define CYDEV_UCFG_B1_P5_U1_CFG1 0x40011ac1u +#define CYDEV_UCFG_B1_P5_U1_CFG2 0x40011ac2u +#define CYDEV_UCFG_B1_P5_U1_CFG3 0x40011ac3u +#define CYDEV_UCFG_B1_P5_U1_CFG4 0x40011ac4u +#define CYDEV_UCFG_B1_P5_U1_CFG5 0x40011ac5u +#define CYDEV_UCFG_B1_P5_U1_CFG6 0x40011ac6u +#define CYDEV_UCFG_B1_P5_U1_CFG7 0x40011ac7u +#define CYDEV_UCFG_B1_P5_U1_CFG8 0x40011ac8u +#define CYDEV_UCFG_B1_P5_U1_CFG9 0x40011ac9u +#define CYDEV_UCFG_B1_P5_U1_CFG10 0x40011acau +#define CYDEV_UCFG_B1_P5_U1_CFG11 0x40011acbu +#define CYDEV_UCFG_B1_P5_U1_CFG12 0x40011accu +#define CYDEV_UCFG_B1_P5_U1_CFG13 0x40011acdu +#define CYDEV_UCFG_B1_P5_U1_CFG14 0x40011aceu +#define CYDEV_UCFG_B1_P5_U1_CFG15 0x40011acfu +#define CYDEV_UCFG_B1_P5_U1_CFG16 0x40011ad0u +#define CYDEV_UCFG_B1_P5_U1_CFG17 0x40011ad1u +#define CYDEV_UCFG_B1_P5_U1_CFG18 0x40011ad2u +#define CYDEV_UCFG_B1_P5_U1_CFG19 0x40011ad3u +#define CYDEV_UCFG_B1_P5_U1_CFG20 0x40011ad4u +#define CYDEV_UCFG_B1_P5_U1_CFG21 0x40011ad5u +#define CYDEV_UCFG_B1_P5_U1_CFG22 0x40011ad6u +#define CYDEV_UCFG_B1_P5_U1_CFG23 0x40011ad7u +#define CYDEV_UCFG_B1_P5_U1_CFG24 0x40011ad8u +#define CYDEV_UCFG_B1_P5_U1_CFG25 0x40011ad9u +#define CYDEV_UCFG_B1_P5_U1_CFG26 0x40011adau +#define CYDEV_UCFG_B1_P5_U1_CFG27 0x40011adbu +#define CYDEV_UCFG_B1_P5_U1_CFG28 0x40011adcu +#define CYDEV_UCFG_B1_P5_U1_CFG29 0x40011addu +#define CYDEV_UCFG_B1_P5_U1_CFG30 0x40011adeu +#define CYDEV_UCFG_B1_P5_U1_CFG31 0x40011adfu +#define CYDEV_UCFG_B1_P5_U1_DCFG0 0x40011ae0u +#define CYDEV_UCFG_B1_P5_U1_DCFG1 0x40011ae2u +#define CYDEV_UCFG_B1_P5_U1_DCFG2 0x40011ae4u +#define CYDEV_UCFG_B1_P5_U1_DCFG3 0x40011ae6u +#define CYDEV_UCFG_B1_P5_U1_DCFG4 0x40011ae8u +#define CYDEV_UCFG_B1_P5_U1_DCFG5 0x40011aeau +#define CYDEV_UCFG_B1_P5_U1_DCFG6 0x40011aecu +#define CYDEV_UCFG_B1_P5_U1_DCFG7 0x40011aeeu +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00u +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_DSI0_BASE 0x40014000u +#define CYDEV_UCFG_DSI0_SIZE 0x000000efu +#define CYDEV_UCFG_DSI1_BASE 0x40014100u +#define CYDEV_UCFG_DSI1_SIZE 0x000000efu +#define CYDEV_UCFG_DSI2_BASE 0x40014200u +#define CYDEV_UCFG_DSI2_SIZE 0x000000efu +#define CYDEV_UCFG_DSI3_BASE 0x40014300u +#define CYDEV_UCFG_DSI3_SIZE 0x000000efu +#define CYDEV_UCFG_DSI4_BASE 0x40014400u +#define CYDEV_UCFG_DSI4_SIZE 0x000000efu +#define CYDEV_UCFG_DSI5_BASE 0x40014500u +#define CYDEV_UCFG_DSI5_SIZE 0x000000efu +#define CYDEV_UCFG_DSI6_BASE 0x40014600u +#define CYDEV_UCFG_DSI6_SIZE 0x000000efu +#define CYDEV_UCFG_DSI7_BASE 0x40014700u +#define CYDEV_UCFG_DSI7_SIZE 0x000000efu +#define CYDEV_UCFG_DSI8_BASE 0x40014800u +#define CYDEV_UCFG_DSI8_SIZE 0x000000efu +#define CYDEV_UCFG_DSI9_BASE 0x40014900u +#define CYDEV_UCFG_DSI9_SIZE 0x000000efu +#define CYDEV_UCFG_DSI12_BASE 0x40014c00u +#define CYDEV_UCFG_DSI12_SIZE 0x000000efu +#define CYDEV_UCFG_DSI13_BASE 0x40014d00u +#define CYDEV_UCFG_DSI13_SIZE 0x000000efu +#define CYDEV_UCFG_BCTL0_BASE 0x40015000u +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010u +#define CYDEV_UCFG_BCTL0_MDCLK_EN 0x40015000u +#define CYDEV_UCFG_BCTL0_MBCLK_EN 0x40015001u +#define CYDEV_UCFG_BCTL0_WAIT_CFG 0x40015002u +#define CYDEV_UCFG_BCTL0_BANK_CTL 0x40015003u +#define CYDEV_UCFG_BCTL0_UDB_TEST_3 0x40015007u +#define CYDEV_UCFG_BCTL0_DCLK_EN0 0x40015008u +#define CYDEV_UCFG_BCTL0_BCLK_EN0 0x40015009u +#define CYDEV_UCFG_BCTL0_DCLK_EN1 0x4001500au +#define CYDEV_UCFG_BCTL0_BCLK_EN1 0x4001500bu +#define CYDEV_UCFG_BCTL0_DCLK_EN2 0x4001500cu +#define CYDEV_UCFG_BCTL0_BCLK_EN2 0x4001500du +#define CYDEV_UCFG_BCTL0_DCLK_EN3 0x4001500eu +#define CYDEV_UCFG_BCTL0_BCLK_EN3 0x4001500fu +#define CYDEV_UCFG_BCTL1_BASE 0x40015010u +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010u +#define CYDEV_UCFG_BCTL1_MDCLK_EN 0x40015010u +#define CYDEV_UCFG_BCTL1_MBCLK_EN 0x40015011u +#define CYDEV_UCFG_BCTL1_WAIT_CFG 0x40015012u +#define CYDEV_UCFG_BCTL1_BANK_CTL 0x40015013u +#define CYDEV_UCFG_BCTL1_UDB_TEST_3 0x40015017u +#define CYDEV_UCFG_BCTL1_DCLK_EN0 0x40015018u +#define CYDEV_UCFG_BCTL1_BCLK_EN0 0x40015019u +#define CYDEV_UCFG_BCTL1_DCLK_EN1 0x4001501au +#define CYDEV_UCFG_BCTL1_BCLK_EN1 0x4001501bu +#define CYDEV_UCFG_BCTL1_DCLK_EN2 0x4001501cu +#define CYDEV_UCFG_BCTL1_BCLK_EN2 0x4001501du +#define CYDEV_UCFG_BCTL1_DCLK_EN3 0x4001501eu +#define CYDEV_UCFG_BCTL1_BCLK_EN3 0x4001501fu +#define CYDEV_IDMUX_BASE 0x40015100u +#define CYDEV_IDMUX_SIZE 0x00000016u +#define CYDEV_IDMUX_IRQ_CTL0 0x40015100u +#define CYDEV_IDMUX_IRQ_CTL1 0x40015101u +#define CYDEV_IDMUX_IRQ_CTL2 0x40015102u +#define CYDEV_IDMUX_IRQ_CTL3 0x40015103u +#define CYDEV_IDMUX_IRQ_CTL4 0x40015104u +#define CYDEV_IDMUX_IRQ_CTL5 0x40015105u +#define CYDEV_IDMUX_IRQ_CTL6 0x40015106u +#define CYDEV_IDMUX_IRQ_CTL7 0x40015107u +#define CYDEV_IDMUX_DRQ_CTL0 0x40015110u +#define CYDEV_IDMUX_DRQ_CTL1 0x40015111u +#define CYDEV_IDMUX_DRQ_CTL2 0x40015112u +#define CYDEV_IDMUX_DRQ_CTL3 0x40015113u +#define CYDEV_IDMUX_DRQ_CTL4 0x40015114u +#define CYDEV_IDMUX_DRQ_CTL5 0x40015115u +#define CYDEV_CACHERAM_BASE 0x40030000u +#define CYDEV_CACHERAM_SIZE 0x00000400u +#define CYDEV_CACHERAM_DATA_MBASE 0x40030000u +#define CYDEV_CACHERAM_DATA_MSIZE 0x00000400u +#define CYDEV_SFR_BASE 0x40050100u +#define CYDEV_SFR_SIZE 0x000000fbu +#define CYDEV_SFR_GPIO0 0x40050180u +#define CYDEV_SFR_GPIRD0 0x40050189u +#define CYDEV_SFR_GPIO0_SEL 0x4005018au +#define CYDEV_SFR_GPIO1 0x40050190u +#define CYDEV_SFR_GPIRD1 0x40050191u +#define CYDEV_SFR_GPIO2 0x40050198u +#define CYDEV_SFR_GPIRD2 0x40050199u +#define CYDEV_SFR_GPIO2_SEL 0x4005019au +#define CYDEV_SFR_GPIO1_SEL 0x400501a2u +#define CYDEV_SFR_GPIO3 0x400501b0u +#define CYDEV_SFR_GPIRD3 0x400501b1u +#define CYDEV_SFR_GPIO3_SEL 0x400501b2u +#define CYDEV_SFR_GPIO4 0x400501c0u +#define CYDEV_SFR_GPIRD4 0x400501c1u +#define CYDEV_SFR_GPIO4_SEL 0x400501c2u +#define CYDEV_SFR_GPIO5 0x400501c8u +#define CYDEV_SFR_GPIRD5 0x400501c9u +#define CYDEV_SFR_GPIO5_SEL 0x400501cau +#define CYDEV_SFR_GPIO6 0x400501d8u +#define CYDEV_SFR_GPIRD6 0x400501d9u +#define CYDEV_SFR_GPIO6_SEL 0x400501dau +#define CYDEV_SFR_GPIO12 0x400501e8u +#define CYDEV_SFR_GPIRD12 0x400501e9u +#define CYDEV_SFR_GPIO12_SEL 0x400501f2u +#define CYDEV_SFR_GPIO15 0x400501f8u +#define CYDEV_SFR_GPIRD15 0x400501f9u +#define CYDEV_SFR_GPIO15_SEL 0x400501fau +#define CYDEV_P3BA_BASE 0x40050300u +#define CYDEV_P3BA_SIZE 0x0000002bu +#define CYDEV_P3BA_Y_START 0x40050300u +#define CYDEV_P3BA_YROLL 0x40050301u +#define CYDEV_P3BA_YCFG 0x40050302u +#define CYDEV_P3BA_X_START1 0x40050303u +#define CYDEV_P3BA_X_START2 0x40050304u +#define CYDEV_P3BA_XROLL1 0x40050305u +#define CYDEV_P3BA_XROLL2 0x40050306u +#define CYDEV_P3BA_XINC 0x40050307u +#define CYDEV_P3BA_XCFG 0x40050308u +#define CYDEV_P3BA_OFFSETADDR1 0x40050309u +#define CYDEV_P3BA_OFFSETADDR2 0x4005030au +#define CYDEV_P3BA_OFFSETADDR3 0x4005030bu +#define CYDEV_P3BA_ABSADDR1 0x4005030cu +#define CYDEV_P3BA_ABSADDR2 0x4005030du +#define CYDEV_P3BA_ABSADDR3 0x4005030eu +#define CYDEV_P3BA_ABSADDR4 0x4005030fu +#define CYDEV_P3BA_DATCFG1 0x40050310u +#define CYDEV_P3BA_DATCFG2 0x40050311u +#define CYDEV_P3BA_CMP_RSLT1 0x40050314u +#define CYDEV_P3BA_CMP_RSLT2 0x40050315u +#define CYDEV_P3BA_CMP_RSLT3 0x40050316u +#define CYDEV_P3BA_CMP_RSLT4 0x40050317u +#define CYDEV_P3BA_DATA_REG1 0x40050318u +#define CYDEV_P3BA_DATA_REG2 0x40050319u +#define CYDEV_P3BA_DATA_REG3 0x4005031au +#define CYDEV_P3BA_DATA_REG4 0x4005031bu +#define CYDEV_P3BA_EXP_DATA1 0x4005031cu +#define CYDEV_P3BA_EXP_DATA2 0x4005031du +#define CYDEV_P3BA_EXP_DATA3 0x4005031eu +#define CYDEV_P3BA_EXP_DATA4 0x4005031fu +#define CYDEV_P3BA_MSTR_HRDATA1 0x40050320u +#define CYDEV_P3BA_MSTR_HRDATA2 0x40050321u +#define CYDEV_P3BA_MSTR_HRDATA3 0x40050322u +#define CYDEV_P3BA_MSTR_HRDATA4 0x40050323u +#define CYDEV_P3BA_BIST_EN 0x40050324u +#define CYDEV_P3BA_PHUB_MASTER_SSR 0x40050325u +#define CYDEV_P3BA_SEQCFG1 0x40050326u +#define CYDEV_P3BA_SEQCFG2 0x40050327u +#define CYDEV_P3BA_Y_CURR 0x40050328u +#define CYDEV_P3BA_X_CURR1 0x40050329u +#define CYDEV_P3BA_X_CURR2 0x4005032au +#define CYDEV_PANTHER_BASE 0x40080000u +#define CYDEV_PANTHER_SIZE 0x00000020u +#define CYDEV_PANTHER_STCALIB_CFG 0x40080000u +#define CYDEV_PANTHER_WAITPIPE 0x40080004u +#define CYDEV_PANTHER_TRACE_CFG 0x40080008u +#define CYDEV_PANTHER_DBG_CFG 0x4008000cu +#define CYDEV_PANTHER_CM3_LCKRST_STAT 0x40080018u +#define CYDEV_PANTHER_DEVICE_ID 0x4008001cu +#define CYDEV_FLSECC_BASE 0x48000000u +#define CYDEV_FLSECC_SIZE 0x00008000u +#define CYDEV_FLSECC_DATA_MBASE 0x48000000u +#define CYDEV_FLSECC_DATA_MSIZE 0x00008000u +#define CYDEV_FLSHID_BASE 0x49000000u +#define CYDEV_FLSHID_SIZE 0x00000200u +#define CYDEV_FLSHID_RSVD_MBASE 0x49000000u +#define CYDEV_FLSHID_RSVD_MSIZE 0x00000080u +#define CYDEV_FLSHID_CUST_MDATA_MBASE 0x49000080u +#define CYDEV_FLSHID_CUST_MDATA_MSIZE 0x00000080u +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100u +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040u +#define CYDEV_FLSHID_CUST_TABLES_Y_LOC 0x49000100u +#define CYDEV_FLSHID_CUST_TABLES_X_LOC 0x49000101u +#define CYDEV_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102u +#define CYDEV_FLSHID_CUST_TABLES_LOT_LSB 0x49000103u +#define CYDEV_FLSHID_CUST_TABLES_LOT_MSB 0x49000104u +#define CYDEV_FLSHID_CUST_TABLES_WRK_WK 0x49000105u +#define CYDEV_FLSHID_CUST_TABLES_FAB_YR 0x49000106u +#define CYDEV_FLSHID_CUST_TABLES_MINOR 0x49000107u +#define CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108u +#define CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109u +#define CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010au +#define CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010bu +#define CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010cu +#define CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010du +#define CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010eu +#define CYDEV_FLSHID_CUST_TABLES_IMO_USB 0x4900010fu +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110u +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111u +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112u +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113u +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114u +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115u +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116u +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117u +#define CYDEV_FLSHID_CUST_TABLES_DEC_M1 0x49000118u +#define CYDEV_FLSHID_CUST_TABLES_DEC_M2 0x49000119u +#define CYDEV_FLSHID_CUST_TABLES_DEC_M3 0x4900011au +#define CYDEV_FLSHID_CUST_TABLES_DEC_M4 0x4900011bu +#define CYDEV_FLSHID_CUST_TABLES_DEC_M5 0x4900011cu +#define CYDEV_FLSHID_CUST_TABLES_DEC_M6 0x4900011du +#define CYDEV_FLSHID_CUST_TABLES_DEC_M7 0x4900011eu +#define CYDEV_FLSHID_CUST_TABLES_DEC_M8 0x4900011fu +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M1 0x49000120u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M2 0x49000121u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M3 0x49000122u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M4 0x49000123u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M5 0x49000124u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M6 0x49000125u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M7 0x49000126u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M8 0x49000127u +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M1 0x49000128u +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M2 0x49000129u +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M3 0x4900012au +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M4 0x4900012bu +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M5 0x4900012cu +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M6 0x4900012du +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M7 0x4900012eu +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M8 0x4900012fu +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M1 0x49000130u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M2 0x49000131u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M3 0x49000132u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M4 0x49000133u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M5 0x49000134u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M6 0x49000135u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M7 0x49000136u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M8 0x49000137u +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M1 0x49000138u +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M2 0x49000139u +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M3 0x4900013au +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M4 0x4900013bu +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M5 0x4900013cu +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M6 0x4900013du +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M7 0x4900013eu +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M8 0x4900013fu +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180u +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080u +#define CYDEV_FLSHID_MFG_CFG_IMO_TR1 0x49000188u +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR0 0x490001acu +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR0 0x490001aeu +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0u +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2u +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4u +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6u +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8u +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR1 0x490001bau +#define CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ceu +#define CYDEV_EXTMEM_BASE 0x60000000u +#define CYDEV_EXTMEM_SIZE 0x00800000u +#define CYDEV_EXTMEM_DATA_MBASE 0x60000000u +#define CYDEV_EXTMEM_DATA_MSIZE 0x00800000u +#define CYDEV_ITM_BASE 0xe0000000u +#define CYDEV_ITM_SIZE 0x00001000u +#define CYDEV_ITM_TRACE_EN 0xe0000e00u +#define CYDEV_ITM_TRACE_PRIVILEGE 0xe0000e40u +#define CYDEV_ITM_TRACE_CTRL 0xe0000e80u +#define CYDEV_ITM_LOCK_ACCESS 0xe0000fb0u +#define CYDEV_ITM_LOCK_STATUS 0xe0000fb4u +#define CYDEV_ITM_PID4 0xe0000fd0u +#define CYDEV_ITM_PID5 0xe0000fd4u +#define CYDEV_ITM_PID6 0xe0000fd8u +#define CYDEV_ITM_PID7 0xe0000fdcu +#define CYDEV_ITM_PID0 0xe0000fe0u +#define CYDEV_ITM_PID1 0xe0000fe4u +#define CYDEV_ITM_PID2 0xe0000fe8u +#define CYDEV_ITM_PID3 0xe0000fecu +#define CYDEV_ITM_CID0 0xe0000ff0u +#define CYDEV_ITM_CID1 0xe0000ff4u +#define CYDEV_ITM_CID2 0xe0000ff8u +#define CYDEV_ITM_CID3 0xe0000ffcu +#define CYDEV_DWT_BASE 0xe0001000u +#define CYDEV_DWT_SIZE 0x0000005cu +#define CYDEV_DWT_CTRL 0xe0001000u +#define CYDEV_DWT_CYCLE_COUNT 0xe0001004u +#define CYDEV_DWT_CPI_COUNT 0xe0001008u +#define CYDEV_DWT_EXC_OVHD_COUNT 0xe000100cu +#define CYDEV_DWT_SLEEP_COUNT 0xe0001010u +#define CYDEV_DWT_LSU_COUNT 0xe0001014u +#define CYDEV_DWT_FOLD_COUNT 0xe0001018u +#define CYDEV_DWT_PC_SAMPLE 0xe000101cu +#define CYDEV_DWT_COMP_0 0xe0001020u +#define CYDEV_DWT_MASK_0 0xe0001024u +#define CYDEV_DWT_FUNCTION_0 0xe0001028u +#define CYDEV_DWT_COMP_1 0xe0001030u +#define CYDEV_DWT_MASK_1 0xe0001034u +#define CYDEV_DWT_FUNCTION_1 0xe0001038u +#define CYDEV_DWT_COMP_2 0xe0001040u +#define CYDEV_DWT_MASK_2 0xe0001044u +#define CYDEV_DWT_FUNCTION_2 0xe0001048u +#define CYDEV_DWT_COMP_3 0xe0001050u +#define CYDEV_DWT_MASK_3 0xe0001054u +#define CYDEV_DWT_FUNCTION_3 0xe0001058u +#define CYDEV_FPB_BASE 0xe0002000u +#define CYDEV_FPB_SIZE 0x00001000u +#define CYDEV_FPB_CTRL 0xe0002000u +#define CYDEV_FPB_REMAP 0xe0002004u +#define CYDEV_FPB_FP_COMP_0 0xe0002008u +#define CYDEV_FPB_FP_COMP_1 0xe000200cu +#define CYDEV_FPB_FP_COMP_2 0xe0002010u +#define CYDEV_FPB_FP_COMP_3 0xe0002014u +#define CYDEV_FPB_FP_COMP_4 0xe0002018u +#define CYDEV_FPB_FP_COMP_5 0xe000201cu +#define CYDEV_FPB_FP_COMP_6 0xe0002020u +#define CYDEV_FPB_FP_COMP_7 0xe0002024u +#define CYDEV_FPB_PID4 0xe0002fd0u +#define CYDEV_FPB_PID5 0xe0002fd4u +#define CYDEV_FPB_PID6 0xe0002fd8u +#define CYDEV_FPB_PID7 0xe0002fdcu +#define CYDEV_FPB_PID0 0xe0002fe0u +#define CYDEV_FPB_PID1 0xe0002fe4u +#define CYDEV_FPB_PID2 0xe0002fe8u +#define CYDEV_FPB_PID3 0xe0002fecu +#define CYDEV_FPB_CID0 0xe0002ff0u +#define CYDEV_FPB_CID1 0xe0002ff4u +#define CYDEV_FPB_CID2 0xe0002ff8u +#define CYDEV_FPB_CID3 0xe0002ffcu +#define CYDEV_NVIC_BASE 0xe000e000u +#define CYDEV_NVIC_SIZE 0x00000d3cu +#define CYDEV_NVIC_INT_CTL_TYPE 0xe000e004u +#define CYDEV_NVIC_SYSTICK_CTL 0xe000e010u +#define CYDEV_NVIC_SYSTICK_RELOAD 0xe000e014u +#define CYDEV_NVIC_SYSTICK_CURRENT 0xe000e018u +#define CYDEV_NVIC_SYSTICK_CAL 0xe000e01cu +#define CYDEV_NVIC_SETENA0 0xe000e100u +#define CYDEV_NVIC_CLRENA0 0xe000e180u +#define CYDEV_NVIC_SETPEND0 0xe000e200u +#define CYDEV_NVIC_CLRPEND0 0xe000e280u +#define CYDEV_NVIC_ACTIVE0 0xe000e300u +#define CYDEV_NVIC_PRI_0 0xe000e400u +#define CYDEV_NVIC_PRI_1 0xe000e401u +#define CYDEV_NVIC_PRI_2 0xe000e402u +#define CYDEV_NVIC_PRI_3 0xe000e403u +#define CYDEV_NVIC_PRI_4 0xe000e404u +#define CYDEV_NVIC_PRI_5 0xe000e405u +#define CYDEV_NVIC_PRI_6 0xe000e406u +#define CYDEV_NVIC_PRI_7 0xe000e407u +#define CYDEV_NVIC_PRI_8 0xe000e408u +#define CYDEV_NVIC_PRI_9 0xe000e409u +#define CYDEV_NVIC_PRI_10 0xe000e40au +#define CYDEV_NVIC_PRI_11 0xe000e40bu +#define CYDEV_NVIC_PRI_12 0xe000e40cu +#define CYDEV_NVIC_PRI_13 0xe000e40du +#define CYDEV_NVIC_PRI_14 0xe000e40eu +#define CYDEV_NVIC_PRI_15 0xe000e40fu +#define CYDEV_NVIC_PRI_16 0xe000e410u +#define CYDEV_NVIC_PRI_17 0xe000e411u +#define CYDEV_NVIC_PRI_18 0xe000e412u +#define CYDEV_NVIC_PRI_19 0xe000e413u +#define CYDEV_NVIC_PRI_20 0xe000e414u +#define CYDEV_NVIC_PRI_21 0xe000e415u +#define CYDEV_NVIC_PRI_22 0xe000e416u +#define CYDEV_NVIC_PRI_23 0xe000e417u +#define CYDEV_NVIC_PRI_24 0xe000e418u +#define CYDEV_NVIC_PRI_25 0xe000e419u +#define CYDEV_NVIC_PRI_26 0xe000e41au +#define CYDEV_NVIC_PRI_27 0xe000e41bu +#define CYDEV_NVIC_PRI_28 0xe000e41cu +#define CYDEV_NVIC_PRI_29 0xe000e41du +#define CYDEV_NVIC_PRI_30 0xe000e41eu +#define CYDEV_NVIC_PRI_31 0xe000e41fu +#define CYDEV_NVIC_CPUID_BASE 0xe000ed00u +#define CYDEV_NVIC_INTR_CTRL_STATE 0xe000ed04u +#define CYDEV_NVIC_VECT_OFFSET 0xe000ed08u +#define CYDEV_NVIC_APPLN_INTR 0xe000ed0cu +#define CYDEV_NVIC_SYSTEM_CONTROL 0xe000ed10u +#define CYDEV_NVIC_CFG_CONTROL 0xe000ed14u +#define CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18u +#define CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1cu +#define CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20u +#define CYDEV_NVIC_SYS_HANDLER_CSR 0xe000ed24u +#define CYDEV_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28u +#define CYDEV_NVIC_BUS_FAULT_STATUS 0xe000ed29u +#define CYDEV_NVIC_USAGE_FAULT_STATUS 0xe000ed2au +#define CYDEV_NVIC_HARD_FAULT_STATUS 0xe000ed2cu +#define CYDEV_NVIC_DEBUG_FAULT_STATUS 0xe000ed30u +#define CYDEV_NVIC_MEMMAN_FAULT_ADD 0xe000ed34u +#define CYDEV_NVIC_BUS_FAULT_ADD 0xe000ed38u +#define CYDEV_CORE_DBG_BASE 0xe000edf0u +#define CYDEV_CORE_DBG_SIZE 0x00000010u +#define CYDEV_CORE_DBG_DBG_HLT_CS 0xe000edf0u +#define CYDEV_CORE_DBG_DBG_REG_SEL 0xe000edf4u +#define CYDEV_CORE_DBG_DBG_REG_DATA 0xe000edf8u +#define CYDEV_CORE_DBG_EXC_MON_CTL 0xe000edfcu +#define CYDEV_TPIU_BASE 0xe0040000u +#define CYDEV_TPIU_SIZE 0x00001000u +#define CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000u +#define CYDEV_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004u +#define CYDEV_TPIU_ASYNC_CLK_PRESCALER 0xe0040010u +#define CYDEV_TPIU_PROTOCOL 0xe00400f0u +#define CYDEV_TPIU_FORM_FLUSH_STAT 0xe0040300u +#define CYDEV_TPIU_FORM_FLUSH_CTRL 0xe0040304u +#define CYDEV_TPIU_TRIGGER 0xe0040ee8u +#define CYDEV_TPIU_ITETMDATA 0xe0040eecu +#define CYDEV_TPIU_ITATBCTR2 0xe0040ef0u +#define CYDEV_TPIU_ITATBCTR0 0xe0040ef8u +#define CYDEV_TPIU_ITITMDATA 0xe0040efcu +#define CYDEV_TPIU_ITCTRL 0xe0040f00u +#define CYDEV_TPIU_DEVID 0xe0040fc8u +#define CYDEV_TPIU_DEVTYPE 0xe0040fccu +#define CYDEV_TPIU_PID4 0xe0040fd0u +#define CYDEV_TPIU_PID5 0xe0040fd4u +#define CYDEV_TPIU_PID6 0xe0040fd8u +#define CYDEV_TPIU_PID7 0xe0040fdcu +#define CYDEV_TPIU_PID0 0xe0040fe0u +#define CYDEV_TPIU_PID1 0xe0040fe4u +#define CYDEV_TPIU_PID2 0xe0040fe8u +#define CYDEV_TPIU_PID3 0xe0040fecu +#define CYDEV_TPIU_CID0 0xe0040ff0u +#define CYDEV_TPIU_CID1 0xe0040ff4u +#define CYDEV_TPIU_CID2 0xe0040ff8u +#define CYDEV_TPIU_CID3 0xe0040ffcu +#define CYDEV_ETM_BASE 0xe0041000u +#define CYDEV_ETM_SIZE 0x00001000u +#define CYDEV_ETM_CTL 0xe0041000u +#define CYDEV_ETM_CFG_CODE 0xe0041004u +#define CYDEV_ETM_TRIG_EVENT 0xe0041008u +#define CYDEV_ETM_STATUS 0xe0041010u +#define CYDEV_ETM_SYS_CFG 0xe0041014u +#define CYDEV_ETM_TRACE_ENB_EVENT 0xe0041020u +#define CYDEV_ETM_TRACE_EN_CTRL1 0xe0041024u +#define CYDEV_ETM_FIFOFULL_LEVEL 0xe004102cu +#define CYDEV_ETM_SYNC_FREQ 0xe00411e0u +#define CYDEV_ETM_ETM_ID 0xe00411e4u +#define CYDEV_ETM_CFG_CODE_EXT 0xe00411e8u +#define CYDEV_ETM_TR_SS_EMBICE_CTRL 0xe00411f0u +#define CYDEV_ETM_CS_TRACE_ID 0xe0041200u +#define CYDEV_ETM_OS_LOCK_ACCESS 0xe0041300u +#define CYDEV_ETM_OS_LOCK_STATUS 0xe0041304u +#define CYDEV_ETM_PDSR 0xe0041314u +#define CYDEV_ETM_ITMISCIN 0xe0041ee0u +#define CYDEV_ETM_ITTRIGOUT 0xe0041ee8u +#define CYDEV_ETM_ITATBCTR2 0xe0041ef0u +#define CYDEV_ETM_ITATBCTR0 0xe0041ef8u +#define CYDEV_ETM_INT_MODE_CTRL 0xe0041f00u +#define CYDEV_ETM_CLM_TAG_SET 0xe0041fa0u +#define CYDEV_ETM_CLM_TAG_CLR 0xe0041fa4u +#define CYDEV_ETM_LOCK_ACCESS 0xe0041fb0u +#define CYDEV_ETM_LOCK_STATUS 0xe0041fb4u +#define CYDEV_ETM_AUTH_STATUS 0xe0041fb8u +#define CYDEV_ETM_DEV_TYPE 0xe0041fccu +#define CYDEV_ETM_PID4 0xe0041fd0u +#define CYDEV_ETM_PID5 0xe0041fd4u +#define CYDEV_ETM_PID6 0xe0041fd8u +#define CYDEV_ETM_PID7 0xe0041fdcu +#define CYDEV_ETM_PID0 0xe0041fe0u +#define CYDEV_ETM_PID1 0xe0041fe4u +#define CYDEV_ETM_PID2 0xe0041fe8u +#define CYDEV_ETM_PID3 0xe0041fecu +#define CYDEV_ETM_CID0 0xe0041ff0u +#define CYDEV_ETM_CID1 0xe0041ff4u +#define CYDEV_ETM_CID2 0xe0041ff8u +#define CYDEV_ETM_CID3 0xe0041ffcu +#define CYDEV_ROM_TABLE_BASE 0xe00ff000u +#define CYDEV_ROM_TABLE_SIZE 0x00001000u +#define CYDEV_ROM_TABLE_NVIC 0xe00ff000u +#define CYDEV_ROM_TABLE_DWT 0xe00ff004u +#define CYDEV_ROM_TABLE_FPB 0xe00ff008u +#define CYDEV_ROM_TABLE_ITM 0xe00ff00cu +#define CYDEV_ROM_TABLE_TPIU 0xe00ff010u +#define CYDEV_ROM_TABLE_ETM 0xe00ff014u +#define CYDEV_ROM_TABLE_END 0xe00ff018u +#define CYDEV_ROM_TABLE_MEMTYPE 0xe00fffccu +#define CYDEV_ROM_TABLE_PID4 0xe00fffd0u +#define CYDEV_ROM_TABLE_PID5 0xe00fffd4u +#define CYDEV_ROM_TABLE_PID6 0xe00fffd8u +#define CYDEV_ROM_TABLE_PID7 0xe00fffdcu +#define CYDEV_ROM_TABLE_PID0 0xe00fffe0u +#define CYDEV_ROM_TABLE_PID1 0xe00fffe4u +#define CYDEV_ROM_TABLE_PID2 0xe00fffe8u +#define CYDEV_ROM_TABLE_PID3 0xe00fffecu +#define CYDEV_ROM_TABLE_CID0 0xe00ffff0u +#define CYDEV_ROM_TABLE_CID1 0xe00ffff4u +#define CYDEV_ROM_TABLE_CID2 0xe00ffff8u +#define CYDEV_ROM_TABLE_CID3 0xe00ffffcu +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000u +#define CYDEV_FLS_ROW_SIZE 0x00000100u +#define CYDEV_ECC_SECTOR_SIZE 0x00002000u +#define CYDEV_ECC_ROW_SIZE 0x00000020u +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u +#define CYDEV_EEPROM_ROW_SIZE 0x00000010u +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004u +#define CYCLK_LD_SYNC_EN 0x00000002u +#define CYCLK_LD_LOAD 0x00000001u +#define CYCLK_PIPE 0x00000080u +#define CYCLK_SSS 0x00000040u +#define CYCLK_EARLY 0x00000020u +#define CYCLK_DUTY 0x00000010u +#define CYCLK_SYNC 0x00000008u +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 +#endif /* CYDEVICE_H */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/cydevice_trm.h b/source/hic_hal/cypress/psoc5lp/PSoC5/cydevice_trm.h new file mode 100644 index 0000000000..a689a53946 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/cydevice_trm.h @@ -0,0 +1,5366 @@ +/******************************************************************************* +* File Name: cydevice_trm.h +* +* Description: +* This file provides all of the address values for the entire PSoC device. +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CYDEVICE_TRM_H) +#define CYDEVICE_TRM_H +#define CYDEV_FLASH_BASE 0x00000000u +#define CYDEV_FLASH_SIZE 0x00040000u +#define CYREG_FLASH_DATA_MBASE 0x00000000u +#define CYREG_FLASH_DATA_MSIZE 0x00040000u +#define CYDEV_SRAM_BASE 0x1fff8000u +#define CYDEV_SRAM_SIZE 0x00010000u +#define CYREG_SRAM_CODE64K_MBASE 0x1fff8000u +#define CYREG_SRAM_CODE64K_MSIZE 0x00004000u +#define CYREG_SRAM_CODE32K_MBASE 0x1fffc000u +#define CYREG_SRAM_CODE32K_MSIZE 0x00002000u +#define CYREG_SRAM_CODE16K_MBASE 0x1fffe000u +#define CYREG_SRAM_CODE16K_MSIZE 0x00001000u +#define CYREG_SRAM_CODE_MBASE 0x1fff8000u +#define CYREG_SRAM_CODE_MSIZE 0x00008000u +#define CYREG_SRAM_DATA_MBASE 0x20000000u +#define CYREG_SRAM_DATA_MSIZE 0x00008000u +#define CYREG_SRAM_DATA16K_MBASE 0x20001000u +#define CYREG_SRAM_DATA16K_MSIZE 0x00001000u +#define CYREG_SRAM_DATA32K_MBASE 0x20002000u +#define CYREG_SRAM_DATA32K_MSIZE 0x00002000u +#define CYREG_SRAM_DATA64K_MBASE 0x20004000u +#define CYREG_SRAM_DATA64K_MSIZE 0x00004000u +#define CYDEV_DMA_BASE 0x20008000u +#define CYDEV_DMA_SIZE 0x00008000u +#define CYREG_DMA_SRAM64K_MBASE 0x20008000u +#define CYREG_DMA_SRAM64K_MSIZE 0x00004000u +#define CYREG_DMA_SRAM32K_MBASE 0x2000c000u +#define CYREG_DMA_SRAM32K_MSIZE 0x00002000u +#define CYREG_DMA_SRAM16K_MBASE 0x2000e000u +#define CYREG_DMA_SRAM16K_MSIZE 0x00001000u +#define CYREG_DMA_SRAM_MBASE 0x2000f000u +#define CYREG_DMA_SRAM_MSIZE 0x00001000u +#define CYDEV_CLKDIST_BASE 0x40004000u +#define CYDEV_CLKDIST_SIZE 0x00000110u +#define CYREG_CLKDIST_CR 0x40004000u +#define CYREG_CLKDIST_LD 0x40004001u +#define CYREG_CLKDIST_WRK0 0x40004002u +#define CYREG_CLKDIST_WRK1 0x40004003u +#define CYREG_CLKDIST_MSTR0 0x40004004u +#define CYREG_CLKDIST_MSTR1 0x40004005u +#define CYREG_CLKDIST_BCFG0 0x40004006u +#define CYREG_CLKDIST_BCFG1 0x40004007u +#define CYREG_CLKDIST_BCFG2 0x40004008u +#define CYREG_CLKDIST_UCFG 0x40004009u +#define CYREG_CLKDIST_DLY0 0x4000400au +#define CYREG_CLKDIST_DLY1 0x4000400bu +#define CYREG_CLKDIST_DMASK 0x40004010u +#define CYREG_CLKDIST_AMASK 0x40004014u +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080u +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG0_CFG0 0x40004080u +#define CYREG_CLKDIST_DCFG0_CFG1 0x40004081u +#define CYREG_CLKDIST_DCFG0_CFG2 0x40004082u +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084u +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG1_CFG0 0x40004084u +#define CYREG_CLKDIST_DCFG1_CFG1 0x40004085u +#define CYREG_CLKDIST_DCFG1_CFG2 0x40004086u +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088u +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG2_CFG0 0x40004088u +#define CYREG_CLKDIST_DCFG2_CFG1 0x40004089u +#define CYREG_CLKDIST_DCFG2_CFG2 0x4000408au +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408cu +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG3_CFG0 0x4000408cu +#define CYREG_CLKDIST_DCFG3_CFG1 0x4000408du +#define CYREG_CLKDIST_DCFG3_CFG2 0x4000408eu +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090u +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG4_CFG0 0x40004090u +#define CYREG_CLKDIST_DCFG4_CFG1 0x40004091u +#define CYREG_CLKDIST_DCFG4_CFG2 0x40004092u +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094u +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG5_CFG0 0x40004094u +#define CYREG_CLKDIST_DCFG5_CFG1 0x40004095u +#define CYREG_CLKDIST_DCFG5_CFG2 0x40004096u +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098u +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG6_CFG0 0x40004098u +#define CYREG_CLKDIST_DCFG6_CFG1 0x40004099u +#define CYREG_CLKDIST_DCFG6_CFG2 0x4000409au +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409cu +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG7_CFG0 0x4000409cu +#define CYREG_CLKDIST_DCFG7_CFG1 0x4000409du +#define CYREG_CLKDIST_DCFG7_CFG2 0x4000409eu +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100u +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG0_CFG0 0x40004100u +#define CYREG_CLKDIST_ACFG0_CFG1 0x40004101u +#define CYREG_CLKDIST_ACFG0_CFG2 0x40004102u +#define CYREG_CLKDIST_ACFG0_CFG3 0x40004103u +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104u +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG1_CFG0 0x40004104u +#define CYREG_CLKDIST_ACFG1_CFG1 0x40004105u +#define CYREG_CLKDIST_ACFG1_CFG2 0x40004106u +#define CYREG_CLKDIST_ACFG1_CFG3 0x40004107u +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108u +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG2_CFG0 0x40004108u +#define CYREG_CLKDIST_ACFG2_CFG1 0x40004109u +#define CYREG_CLKDIST_ACFG2_CFG2 0x4000410au +#define CYREG_CLKDIST_ACFG2_CFG3 0x4000410bu +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410cu +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG3_CFG0 0x4000410cu +#define CYREG_CLKDIST_ACFG3_CFG1 0x4000410du +#define CYREG_CLKDIST_ACFG3_CFG2 0x4000410eu +#define CYREG_CLKDIST_ACFG3_CFG3 0x4000410fu +#define CYDEV_FASTCLK_BASE 0x40004200u +#define CYDEV_FASTCLK_SIZE 0x00000026u +#define CYDEV_FASTCLK_IMO_BASE 0x40004200u +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001u +#define CYREG_FASTCLK_IMO_CR 0x40004200u +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210u +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004u +#define CYREG_FASTCLK_XMHZ_CSR 0x40004210u +#define CYREG_FASTCLK_XMHZ_CFG0 0x40004212u +#define CYREG_FASTCLK_XMHZ_CFG1 0x40004213u +#define CYDEV_FASTCLK_PLL_BASE 0x40004220u +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006u +#define CYREG_FASTCLK_PLL_CFG0 0x40004220u +#define CYREG_FASTCLK_PLL_CFG1 0x40004221u +#define CYREG_FASTCLK_PLL_P 0x40004222u +#define CYREG_FASTCLK_PLL_Q 0x40004223u +#define CYREG_FASTCLK_PLL_SR 0x40004225u +#define CYDEV_SLOWCLK_BASE 0x40004300u +#define CYDEV_SLOWCLK_SIZE 0x0000000bu +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300u +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002u +#define CYREG_SLOWCLK_ILO_CR0 0x40004300u +#define CYREG_SLOWCLK_ILO_CR1 0x40004301u +#define CYDEV_SLOWCLK_X32_BASE 0x40004308u +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003u +#define CYREG_SLOWCLK_X32_CR 0x40004308u +#define CYREG_SLOWCLK_X32_CFG 0x40004309u +#define CYREG_SLOWCLK_X32_TST 0x4000430au +#define CYDEV_BOOST_BASE 0x40004320u +#define CYDEV_BOOST_SIZE 0x00000007u +#define CYREG_BOOST_CR0 0x40004320u +#define CYREG_BOOST_CR1 0x40004321u +#define CYREG_BOOST_CR2 0x40004322u +#define CYREG_BOOST_CR3 0x40004323u +#define CYREG_BOOST_SR 0x40004324u +#define CYREG_BOOST_CR4 0x40004325u +#define CYREG_BOOST_SR2 0x40004326u +#define CYDEV_PWRSYS_BASE 0x40004330u +#define CYDEV_PWRSYS_SIZE 0x00000002u +#define CYREG_PWRSYS_CR0 0x40004330u +#define CYREG_PWRSYS_CR1 0x40004331u +#define CYDEV_PM_BASE 0x40004380u +#define CYDEV_PM_SIZE 0x00000057u +#define CYREG_PM_TW_CFG0 0x40004380u +#define CYREG_PM_TW_CFG1 0x40004381u +#define CYREG_PM_TW_CFG2 0x40004382u +#define CYREG_PM_WDT_CFG 0x40004383u +#define CYREG_PM_WDT_CR 0x40004384u +#define CYREG_PM_INT_SR 0x40004390u +#define CYREG_PM_MODE_CFG0 0x40004391u +#define CYREG_PM_MODE_CFG1 0x40004392u +#define CYREG_PM_MODE_CSR 0x40004393u +#define CYREG_PM_USB_CR0 0x40004394u +#define CYREG_PM_WAKEUP_CFG0 0x40004398u +#define CYREG_PM_WAKEUP_CFG1 0x40004399u +#define CYREG_PM_WAKEUP_CFG2 0x4000439au +#define CYDEV_PM_ACT_BASE 0x400043a0u +#define CYDEV_PM_ACT_SIZE 0x0000000eu +#define CYREG_PM_ACT_CFG0 0x400043a0u +#define CYREG_PM_ACT_CFG1 0x400043a1u +#define CYREG_PM_ACT_CFG2 0x400043a2u +#define CYREG_PM_ACT_CFG3 0x400043a3u +#define CYREG_PM_ACT_CFG4 0x400043a4u +#define CYREG_PM_ACT_CFG5 0x400043a5u +#define CYREG_PM_ACT_CFG6 0x400043a6u +#define CYREG_PM_ACT_CFG7 0x400043a7u +#define CYREG_PM_ACT_CFG8 0x400043a8u +#define CYREG_PM_ACT_CFG9 0x400043a9u +#define CYREG_PM_ACT_CFG10 0x400043aau +#define CYREG_PM_ACT_CFG11 0x400043abu +#define CYREG_PM_ACT_CFG12 0x400043acu +#define CYREG_PM_ACT_CFG13 0x400043adu +#define CYDEV_PM_STBY_BASE 0x400043b0u +#define CYDEV_PM_STBY_SIZE 0x0000000eu +#define CYREG_PM_STBY_CFG0 0x400043b0u +#define CYREG_PM_STBY_CFG1 0x400043b1u +#define CYREG_PM_STBY_CFG2 0x400043b2u +#define CYREG_PM_STBY_CFG3 0x400043b3u +#define CYREG_PM_STBY_CFG4 0x400043b4u +#define CYREG_PM_STBY_CFG5 0x400043b5u +#define CYREG_PM_STBY_CFG6 0x400043b6u +#define CYREG_PM_STBY_CFG7 0x400043b7u +#define CYREG_PM_STBY_CFG8 0x400043b8u +#define CYREG_PM_STBY_CFG9 0x400043b9u +#define CYREG_PM_STBY_CFG10 0x400043bau +#define CYREG_PM_STBY_CFG11 0x400043bbu +#define CYREG_PM_STBY_CFG12 0x400043bcu +#define CYREG_PM_STBY_CFG13 0x400043bdu +#define CYDEV_PM_AVAIL_BASE 0x400043c0u +#define CYDEV_PM_AVAIL_SIZE 0x00000017u +#define CYREG_PM_AVAIL_CR0 0x400043c0u +#define CYREG_PM_AVAIL_CR1 0x400043c1u +#define CYREG_PM_AVAIL_CR2 0x400043c2u +#define CYREG_PM_AVAIL_CR3 0x400043c3u +#define CYREG_PM_AVAIL_CR4 0x400043c4u +#define CYREG_PM_AVAIL_CR5 0x400043c5u +#define CYREG_PM_AVAIL_CR6 0x400043c6u +#define CYREG_PM_AVAIL_SR0 0x400043d0u +#define CYREG_PM_AVAIL_SR1 0x400043d1u +#define CYREG_PM_AVAIL_SR2 0x400043d2u +#define CYREG_PM_AVAIL_SR3 0x400043d3u +#define CYREG_PM_AVAIL_SR4 0x400043d4u +#define CYREG_PM_AVAIL_SR5 0x400043d5u +#define CYREG_PM_AVAIL_SR6 0x400043d6u +#define CYDEV_PICU_BASE 0x40004500u +#define CYDEV_PICU_SIZE 0x000000b0u +#define CYDEV_PICU_INTTYPE_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080u +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008u +#define CYREG_PICU0_INTTYPE0 0x40004500u +#define CYREG_PICU0_INTTYPE1 0x40004501u +#define CYREG_PICU0_INTTYPE2 0x40004502u +#define CYREG_PICU0_INTTYPE3 0x40004503u +#define CYREG_PICU0_INTTYPE4 0x40004504u +#define CYREG_PICU0_INTTYPE5 0x40004505u +#define CYREG_PICU0_INTTYPE6 0x40004506u +#define CYREG_PICU0_INTTYPE7 0x40004507u +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508u +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008u +#define CYREG_PICU1_INTTYPE0 0x40004508u +#define CYREG_PICU1_INTTYPE1 0x40004509u +#define CYREG_PICU1_INTTYPE2 0x4000450au +#define CYREG_PICU1_INTTYPE3 0x4000450bu +#define CYREG_PICU1_INTTYPE4 0x4000450cu +#define CYREG_PICU1_INTTYPE5 0x4000450du +#define CYREG_PICU1_INTTYPE6 0x4000450eu +#define CYREG_PICU1_INTTYPE7 0x4000450fu +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510u +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008u +#define CYREG_PICU2_INTTYPE0 0x40004510u +#define CYREG_PICU2_INTTYPE1 0x40004511u +#define CYREG_PICU2_INTTYPE2 0x40004512u +#define CYREG_PICU2_INTTYPE3 0x40004513u +#define CYREG_PICU2_INTTYPE4 0x40004514u +#define CYREG_PICU2_INTTYPE5 0x40004515u +#define CYREG_PICU2_INTTYPE6 0x40004516u +#define CYREG_PICU2_INTTYPE7 0x40004517u +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518u +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008u +#define CYREG_PICU3_INTTYPE0 0x40004518u +#define CYREG_PICU3_INTTYPE1 0x40004519u +#define CYREG_PICU3_INTTYPE2 0x4000451au +#define CYREG_PICU3_INTTYPE3 0x4000451bu +#define CYREG_PICU3_INTTYPE4 0x4000451cu +#define CYREG_PICU3_INTTYPE5 0x4000451du +#define CYREG_PICU3_INTTYPE6 0x4000451eu +#define CYREG_PICU3_INTTYPE7 0x4000451fu +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520u +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008u +#define CYREG_PICU4_INTTYPE0 0x40004520u +#define CYREG_PICU4_INTTYPE1 0x40004521u +#define CYREG_PICU4_INTTYPE2 0x40004522u +#define CYREG_PICU4_INTTYPE3 0x40004523u +#define CYREG_PICU4_INTTYPE4 0x40004524u +#define CYREG_PICU4_INTTYPE5 0x40004525u +#define CYREG_PICU4_INTTYPE6 0x40004526u +#define CYREG_PICU4_INTTYPE7 0x40004527u +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528u +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008u +#define CYREG_PICU5_INTTYPE0 0x40004528u +#define CYREG_PICU5_INTTYPE1 0x40004529u +#define CYREG_PICU5_INTTYPE2 0x4000452au +#define CYREG_PICU5_INTTYPE3 0x4000452bu +#define CYREG_PICU5_INTTYPE4 0x4000452cu +#define CYREG_PICU5_INTTYPE5 0x4000452du +#define CYREG_PICU5_INTTYPE6 0x4000452eu +#define CYREG_PICU5_INTTYPE7 0x4000452fu +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530u +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008u +#define CYREG_PICU6_INTTYPE0 0x40004530u +#define CYREG_PICU6_INTTYPE1 0x40004531u +#define CYREG_PICU6_INTTYPE2 0x40004532u +#define CYREG_PICU6_INTTYPE3 0x40004533u +#define CYREG_PICU6_INTTYPE4 0x40004534u +#define CYREG_PICU6_INTTYPE5 0x40004535u +#define CYREG_PICU6_INTTYPE6 0x40004536u +#define CYREG_PICU6_INTTYPE7 0x40004537u +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560u +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008u +#define CYREG_PICU12_INTTYPE0 0x40004560u +#define CYREG_PICU12_INTTYPE1 0x40004561u +#define CYREG_PICU12_INTTYPE2 0x40004562u +#define CYREG_PICU12_INTTYPE3 0x40004563u +#define CYREG_PICU12_INTTYPE4 0x40004564u +#define CYREG_PICU12_INTTYPE5 0x40004565u +#define CYREG_PICU12_INTTYPE6 0x40004566u +#define CYREG_PICU12_INTTYPE7 0x40004567u +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578u +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008u +#define CYREG_PICU15_INTTYPE0 0x40004578u +#define CYREG_PICU15_INTTYPE1 0x40004579u +#define CYREG_PICU15_INTTYPE2 0x4000457au +#define CYREG_PICU15_INTTYPE3 0x4000457bu +#define CYREG_PICU15_INTTYPE4 0x4000457cu +#define CYREG_PICU15_INTTYPE5 0x4000457du +#define CYREG_PICU15_INTTYPE6 0x4000457eu +#define CYREG_PICU15_INTTYPE7 0x4000457fu +#define CYDEV_PICU_STAT_BASE 0x40004580u +#define CYDEV_PICU_STAT_SIZE 0x00000010u +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580u +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001u +#define CYREG_PICU0_INTSTAT 0x40004580u +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581u +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001u +#define CYREG_PICU1_INTSTAT 0x40004581u +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582u +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001u +#define CYREG_PICU2_INTSTAT 0x40004582u +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583u +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001u +#define CYREG_PICU3_INTSTAT 0x40004583u +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584u +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001u +#define CYREG_PICU4_INTSTAT 0x40004584u +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585u +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001u +#define CYREG_PICU5_INTSTAT 0x40004585u +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586u +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001u +#define CYREG_PICU6_INTSTAT 0x40004586u +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458cu +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001u +#define CYREG_PICU12_INTSTAT 0x4000458cu +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458fu +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001u +#define CYREG_PICU15_INTSTAT 0x4000458fu +#define CYDEV_PICU_SNAP_BASE 0x40004590u +#define CYDEV_PICU_SNAP_SIZE 0x00000010u +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590u +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001u +#define CYREG_PICU0_SNAP 0x40004590u +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591u +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001u +#define CYREG_PICU1_SNAP 0x40004591u +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592u +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001u +#define CYREG_PICU2_SNAP 0x40004592u +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593u +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001u +#define CYREG_PICU3_SNAP 0x40004593u +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594u +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001u +#define CYREG_PICU4_SNAP 0x40004594u +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595u +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001u +#define CYREG_PICU5_SNAP 0x40004595u +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596u +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001u +#define CYREG_PICU6_SNAP 0x40004596u +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459cu +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001u +#define CYREG_PICU12_SNAP 0x4000459cu +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459fu +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001u +#define CYREG_PICU_15_SNAP_15 0x4000459fu +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010u +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001u +#define CYREG_PICU0_DISABLE_COR 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001u +#define CYREG_PICU1_DISABLE_COR 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001u +#define CYREG_PICU2_DISABLE_COR 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001u +#define CYREG_PICU3_DISABLE_COR 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001u +#define CYREG_PICU4_DISABLE_COR 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001u +#define CYREG_PICU5_DISABLE_COR 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001u +#define CYREG_PICU6_DISABLE_COR 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001u +#define CYREG_PICU12_DISABLE_COR 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045afu +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001u +#define CYREG_PICU15_DISABLE_COR 0x400045afu +#define CYDEV_MFGCFG_BASE 0x40004600u +#define CYDEV_MFGCFG_SIZE 0x000000edu +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600u +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038u +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001u +#define CYREG_DAC0_TR 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001u +#define CYREG_DAC1_TR 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001u +#define CYREG_DAC2_TR 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001u +#define CYREG_DAC3_TR 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001u +#define CYREG_NPUMP_DSM_TR0 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001u +#define CYREG_NPUMP_SC_TR0 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001u +#define CYREG_NPUMP_OPAMP_TR0 0x40004612u +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001u +#define CYREG_SAR0_TR0 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616u +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001u +#define CYREG_SAR1_TR0 0x40004616u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002u +#define CYREG_OPAMP0_TR0 0x40004620u +#define CYREG_OPAMP0_TR1 0x40004621u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002u +#define CYREG_OPAMP1_TR0 0x40004622u +#define CYREG_OPAMP1_TR1 0x40004623u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002u +#define CYREG_OPAMP2_TR0 0x40004624u +#define CYREG_OPAMP2_TR1 0x40004625u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002u +#define CYREG_OPAMP3_TR0 0x40004626u +#define CYREG_OPAMP3_TR1 0x40004627u +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630u +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002u +#define CYREG_CMP0_TR0 0x40004630u +#define CYREG_CMP0_TR1 0x40004631u +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632u +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002u +#define CYREG_CMP1_TR0 0x40004632u +#define CYREG_CMP1_TR1 0x40004633u +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634u +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002u +#define CYREG_CMP2_TR0 0x40004634u +#define CYREG_CMP2_TR1 0x40004635u +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636u +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002u +#define CYREG_CMP3_TR0 0x40004636u +#define CYREG_CMP3_TR1 0x40004637u +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680u +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000bu +#define CYREG_PWRSYS_HIB_TR0 0x40004680u +#define CYREG_PWRSYS_HIB_TR1 0x40004681u +#define CYREG_PWRSYS_I2C_TR 0x40004682u +#define CYREG_PWRSYS_SLP_TR 0x40004683u +#define CYREG_PWRSYS_BUZZ_TR 0x40004684u +#define CYREG_PWRSYS_WAKE_TR0 0x40004685u +#define CYREG_PWRSYS_WAKE_TR1 0x40004686u +#define CYREG_PWRSYS_BREF_TR 0x40004687u +#define CYREG_PWRSYS_BG_TR 0x40004688u +#define CYREG_PWRSYS_WAKE_TR2 0x40004689u +#define CYREG_PWRSYS_WAKE_TR3 0x4000468au +#define CYDEV_MFGCFG_ILO_BASE 0x40004690u +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002u +#define CYREG_ILO_TR0 0x40004690u +#define CYREG_ILO_TR1 0x40004691u +#define CYDEV_MFGCFG_X32_BASE 0x40004698u +#define CYDEV_MFGCFG_X32_SIZE 0x00000001u +#define CYREG_X32_TR 0x40004698u +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0u +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005u +#define CYREG_IMO_TR0 0x400046a0u +#define CYREG_IMO_TR1 0x400046a1u +#define CYREG_IMO_GAIN 0x400046a2u +#define CYREG_IMO_C36M 0x400046a3u +#define CYREG_IMO_TR2 0x400046a4u +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8u +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001u +#define CYREG_XMHZ_TR 0x400046a8u +#define CYREG_MFGCFG_DLY 0x400046c0u +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0u +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000du +#define CYREG_MLOGIC_DMPSTR 0x400046e2u +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4u +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002u +#define CYREG_MLOGIC_SEG_CR 0x400046e4u +#define CYREG_MLOGIC_SEG_CFG0 0x400046e5u +#define CYREG_MLOGIC_DEBUG 0x400046e8u +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046eau +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001u +#define CYREG_MLOGIC_CPU_SCR_CPU_SCR 0x400046eau +#define CYREG_MLOGIC_REV_ID 0x400046ecu +#define CYDEV_RESET_BASE 0x400046f0u +#define CYDEV_RESET_SIZE 0x0000000fu +#define CYREG_RESET_IPOR_CR0 0x400046f0u +#define CYREG_RESET_IPOR_CR1 0x400046f1u +#define CYREG_RESET_IPOR_CR2 0x400046f2u +#define CYREG_RESET_IPOR_CR3 0x400046f3u +#define CYREG_RESET_CR0 0x400046f4u +#define CYREG_RESET_CR1 0x400046f5u +#define CYREG_RESET_CR2 0x400046f6u +#define CYREG_RESET_CR3 0x400046f7u +#define CYREG_RESET_CR4 0x400046f8u +#define CYREG_RESET_CR5 0x400046f9u +#define CYREG_RESET_SR0 0x400046fau +#define CYREG_RESET_SR1 0x400046fbu +#define CYREG_RESET_SR2 0x400046fcu +#define CYREG_RESET_SR3 0x400046fdu +#define CYREG_RESET_TR 0x400046feu +#define CYDEV_SPC_BASE 0x40004700u +#define CYDEV_SPC_SIZE 0x00000100u +#define CYREG_SPC_FM_EE_CR 0x40004700u +#define CYREG_SPC_FM_EE_WAKE_CNT 0x40004701u +#define CYREG_SPC_EE_SCR 0x40004702u +#define CYREG_SPC_EE_ERR 0x40004703u +#define CYREG_SPC_CPU_DATA 0x40004720u +#define CYREG_SPC_DMA_DATA 0x40004721u +#define CYREG_SPC_SR 0x40004722u +#define CYREG_SPC_CR 0x40004723u +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780u +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080u +#define CYREG_SPC_DMM_MAP_SRAM_MBASE 0x40004780u +#define CYREG_SPC_DMM_MAP_SRAM_MSIZE 0x00000080u +#define CYDEV_CACHE_BASE 0x40004800u +#define CYDEV_CACHE_SIZE 0x0000009cu +#define CYREG_CACHE_CC_CTL 0x40004800u +#define CYREG_CACHE_ECC_CORR 0x40004880u +#define CYREG_CACHE_ECC_ERR 0x40004888u +#define CYREG_CACHE_FLASH_ERR 0x40004890u +#define CYREG_CACHE_HITMISS 0x40004898u +#define CYDEV_I2C_BASE 0x40004900u +#define CYDEV_I2C_SIZE 0x000000e1u +#define CYREG_I2C_XCFG 0x400049c8u +#define CYREG_I2C_ADR 0x400049cau +#define CYREG_I2C_CFG 0x400049d6u +#define CYREG_I2C_CSR 0x400049d7u +#define CYREG_I2C_D 0x400049d8u +#define CYREG_I2C_MCSR 0x400049d9u +#define CYREG_I2C_CLK_DIV1 0x400049dbu +#define CYREG_I2C_CLK_DIV2 0x400049dcu +#define CYREG_I2C_TMOUT_CSR 0x400049ddu +#define CYREG_I2C_TMOUT_SR 0x400049deu +#define CYREG_I2C_TMOUT_CFG0 0x400049dfu +#define CYREG_I2C_TMOUT_CFG1 0x400049e0u +#define CYDEV_DEC_BASE 0x40004e00u +#define CYDEV_DEC_SIZE 0x00000015u +#define CYREG_DEC_CR 0x40004e00u +#define CYREG_DEC_SR 0x40004e01u +#define CYREG_DEC_SHIFT1 0x40004e02u +#define CYREG_DEC_SHIFT2 0x40004e03u +#define CYREG_DEC_DR2 0x40004e04u +#define CYREG_DEC_DR2H 0x40004e05u +#define CYREG_DEC_DR1 0x40004e06u +#define CYREG_DEC_OCOR 0x40004e08u +#define CYREG_DEC_OCORM 0x40004e09u +#define CYREG_DEC_OCORH 0x40004e0au +#define CYREG_DEC_GCOR 0x40004e0cu +#define CYREG_DEC_GCORH 0x40004e0du +#define CYREG_DEC_GVAL 0x40004e0eu +#define CYREG_DEC_OUTSAMP 0x40004e10u +#define CYREG_DEC_OUTSAMPM 0x40004e11u +#define CYREG_DEC_OUTSAMPH 0x40004e12u +#define CYREG_DEC_OUTSAMPS 0x40004e13u +#define CYREG_DEC_COHER 0x40004e14u +#define CYDEV_TMR0_BASE 0x40004f00u +#define CYDEV_TMR0_SIZE 0x0000000cu +#define CYREG_TMR0_CFG0 0x40004f00u +#define CYREG_TMR0_CFG1 0x40004f01u +#define CYREG_TMR0_CFG2 0x40004f02u +#define CYREG_TMR0_SR0 0x40004f03u +#define CYREG_TMR0_PER0 0x40004f04u +#define CYREG_TMR0_PER1 0x40004f05u +#define CYREG_TMR0_CNT_CMP0 0x40004f06u +#define CYREG_TMR0_CNT_CMP1 0x40004f07u +#define CYREG_TMR0_CAP0 0x40004f08u +#define CYREG_TMR0_CAP1 0x40004f09u +#define CYREG_TMR0_RT0 0x40004f0au +#define CYREG_TMR0_RT1 0x40004f0bu +#define CYDEV_TMR1_BASE 0x40004f0cu +#define CYDEV_TMR1_SIZE 0x0000000cu +#define CYREG_TMR1_CFG0 0x40004f0cu +#define CYREG_TMR1_CFG1 0x40004f0du +#define CYREG_TMR1_CFG2 0x40004f0eu +#define CYREG_TMR1_SR0 0x40004f0fu +#define CYREG_TMR1_PER0 0x40004f10u +#define CYREG_TMR1_PER1 0x40004f11u +#define CYREG_TMR1_CNT_CMP0 0x40004f12u +#define CYREG_TMR1_CNT_CMP1 0x40004f13u +#define CYREG_TMR1_CAP0 0x40004f14u +#define CYREG_TMR1_CAP1 0x40004f15u +#define CYREG_TMR1_RT0 0x40004f16u +#define CYREG_TMR1_RT1 0x40004f17u +#define CYDEV_TMR2_BASE 0x40004f18u +#define CYDEV_TMR2_SIZE 0x0000000cu +#define CYREG_TMR2_CFG0 0x40004f18u +#define CYREG_TMR2_CFG1 0x40004f19u +#define CYREG_TMR2_CFG2 0x40004f1au +#define CYREG_TMR2_SR0 0x40004f1bu +#define CYREG_TMR2_PER0 0x40004f1cu +#define CYREG_TMR2_PER1 0x40004f1du +#define CYREG_TMR2_CNT_CMP0 0x40004f1eu +#define CYREG_TMR2_CNT_CMP1 0x40004f1fu +#define CYREG_TMR2_CAP0 0x40004f20u +#define CYREG_TMR2_CAP1 0x40004f21u +#define CYREG_TMR2_RT0 0x40004f22u +#define CYREG_TMR2_RT1 0x40004f23u +#define CYDEV_TMR3_BASE 0x40004f24u +#define CYDEV_TMR3_SIZE 0x0000000cu +#define CYREG_TMR3_CFG0 0x40004f24u +#define CYREG_TMR3_CFG1 0x40004f25u +#define CYREG_TMR3_CFG2 0x40004f26u +#define CYREG_TMR3_SR0 0x40004f27u +#define CYREG_TMR3_PER0 0x40004f28u +#define CYREG_TMR3_PER1 0x40004f29u +#define CYREG_TMR3_CNT_CMP0 0x40004f2au +#define CYREG_TMR3_CNT_CMP1 0x40004f2bu +#define CYREG_TMR3_CAP0 0x40004f2cu +#define CYREG_TMR3_CAP1 0x40004f2du +#define CYREG_TMR3_RT0 0x40004f2eu +#define CYREG_TMR3_RT1 0x40004f2fu +#define CYDEV_IO_BASE 0x40005000u +#define CYDEV_IO_SIZE 0x00000200u +#define CYDEV_IO_PC_BASE 0x40005000u +#define CYDEV_IO_PC_SIZE 0x00000080u +#define CYDEV_IO_PC_PRT0_BASE 0x40005000u +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008u +#define CYREG_PRT0_PC0 0x40005000u +#define CYREG_PRT0_PC1 0x40005001u +#define CYREG_PRT0_PC2 0x40005002u +#define CYREG_PRT0_PC3 0x40005003u +#define CYREG_PRT0_PC4 0x40005004u +#define CYREG_PRT0_PC5 0x40005005u +#define CYREG_PRT0_PC6 0x40005006u +#define CYREG_PRT0_PC7 0x40005007u +#define CYDEV_IO_PC_PRT1_BASE 0x40005008u +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008u +#define CYREG_PRT1_PC0 0x40005008u +#define CYREG_PRT1_PC1 0x40005009u +#define CYREG_PRT1_PC2 0x4000500au +#define CYREG_PRT1_PC3 0x4000500bu +#define CYREG_PRT1_PC4 0x4000500cu +#define CYREG_PRT1_PC5 0x4000500du +#define CYREG_PRT1_PC6 0x4000500eu +#define CYREG_PRT1_PC7 0x4000500fu +#define CYDEV_IO_PC_PRT2_BASE 0x40005010u +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008u +#define CYREG_PRT2_PC0 0x40005010u +#define CYREG_PRT2_PC1 0x40005011u +#define CYREG_PRT2_PC2 0x40005012u +#define CYREG_PRT2_PC3 0x40005013u +#define CYREG_PRT2_PC4 0x40005014u +#define CYREG_PRT2_PC5 0x40005015u +#define CYREG_PRT2_PC6 0x40005016u +#define CYREG_PRT2_PC7 0x40005017u +#define CYDEV_IO_PC_PRT3_BASE 0x40005018u +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008u +#define CYREG_PRT3_PC0 0x40005018u +#define CYREG_PRT3_PC1 0x40005019u +#define CYREG_PRT3_PC2 0x4000501au +#define CYREG_PRT3_PC3 0x4000501bu +#define CYREG_PRT3_PC4 0x4000501cu +#define CYREG_PRT3_PC5 0x4000501du +#define CYREG_PRT3_PC6 0x4000501eu +#define CYREG_PRT3_PC7 0x4000501fu +#define CYDEV_IO_PC_PRT4_BASE 0x40005020u +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008u +#define CYREG_PRT4_PC0 0x40005020u +#define CYREG_PRT4_PC1 0x40005021u +#define CYREG_PRT4_PC2 0x40005022u +#define CYREG_PRT4_PC3 0x40005023u +#define CYREG_PRT4_PC4 0x40005024u +#define CYREG_PRT4_PC5 0x40005025u +#define CYREG_PRT4_PC6 0x40005026u +#define CYREG_PRT4_PC7 0x40005027u +#define CYDEV_IO_PC_PRT5_BASE 0x40005028u +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008u +#define CYREG_PRT5_PC0 0x40005028u +#define CYREG_PRT5_PC1 0x40005029u +#define CYREG_PRT5_PC2 0x4000502au +#define CYREG_PRT5_PC3 0x4000502bu +#define CYREG_PRT5_PC4 0x4000502cu +#define CYREG_PRT5_PC5 0x4000502du +#define CYREG_PRT5_PC6 0x4000502eu +#define CYREG_PRT5_PC7 0x4000502fu +#define CYDEV_IO_PC_PRT6_BASE 0x40005030u +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008u +#define CYREG_PRT6_PC0 0x40005030u +#define CYREG_PRT6_PC1 0x40005031u +#define CYREG_PRT6_PC2 0x40005032u +#define CYREG_PRT6_PC3 0x40005033u +#define CYREG_PRT6_PC4 0x40005034u +#define CYREG_PRT6_PC5 0x40005035u +#define CYREG_PRT6_PC6 0x40005036u +#define CYREG_PRT6_PC7 0x40005037u +#define CYDEV_IO_PC_PRT12_BASE 0x40005060u +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008u +#define CYREG_PRT12_PC0 0x40005060u +#define CYREG_PRT12_PC1 0x40005061u +#define CYREG_PRT12_PC2 0x40005062u +#define CYREG_PRT12_PC3 0x40005063u +#define CYREG_PRT12_PC4 0x40005064u +#define CYREG_PRT12_PC5 0x40005065u +#define CYREG_PRT12_PC6 0x40005066u +#define CYREG_PRT12_PC7 0x40005067u +#define CYDEV_IO_PC_PRT15_BASE 0x40005078u +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006u +#define CYREG_IO_PC_PRT15_PC0 0x40005078u +#define CYREG_IO_PC_PRT15_PC1 0x40005079u +#define CYREG_IO_PC_PRT15_PC2 0x4000507au +#define CYREG_IO_PC_PRT15_PC3 0x4000507bu +#define CYREG_IO_PC_PRT15_PC4 0x4000507cu +#define CYREG_IO_PC_PRT15_PC5 0x4000507du +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507eu +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002u +#define CYREG_IO_PC_PRT15_7_6_PC0 0x4000507eu +#define CYREG_IO_PC_PRT15_7_6_PC1 0x4000507fu +#define CYDEV_IO_DR_BASE 0x40005080u +#define CYDEV_IO_DR_SIZE 0x00000010u +#define CYDEV_IO_DR_PRT0_BASE 0x40005080u +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001u +#define CYREG_PRT0_DR_ALIAS 0x40005080u +#define CYDEV_IO_DR_PRT1_BASE 0x40005081u +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001u +#define CYREG_PRT1_DR_ALIAS 0x40005081u +#define CYDEV_IO_DR_PRT2_BASE 0x40005082u +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001u +#define CYREG_PRT2_DR_ALIAS 0x40005082u +#define CYDEV_IO_DR_PRT3_BASE 0x40005083u +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001u +#define CYREG_PRT3_DR_ALIAS 0x40005083u +#define CYDEV_IO_DR_PRT4_BASE 0x40005084u +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001u +#define CYREG_PRT4_DR_ALIAS 0x40005084u +#define CYDEV_IO_DR_PRT5_BASE 0x40005085u +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001u +#define CYREG_PRT5_DR_ALIAS 0x40005085u +#define CYDEV_IO_DR_PRT6_BASE 0x40005086u +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001u +#define CYREG_PRT6_DR_ALIAS 0x40005086u +#define CYDEV_IO_DR_PRT12_BASE 0x4000508cu +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001u +#define CYREG_PRT12_DR_ALIAS 0x4000508cu +#define CYDEV_IO_DR_PRT15_BASE 0x4000508fu +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001u +#define CYREG_PRT15_DR_15_ALIAS 0x4000508fu +#define CYDEV_IO_PS_BASE 0x40005090u +#define CYDEV_IO_PS_SIZE 0x00000010u +#define CYDEV_IO_PS_PRT0_BASE 0x40005090u +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001u +#define CYREG_PRT0_PS_ALIAS 0x40005090u +#define CYDEV_IO_PS_PRT1_BASE 0x40005091u +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001u +#define CYREG_PRT1_PS_ALIAS 0x40005091u +#define CYDEV_IO_PS_PRT2_BASE 0x40005092u +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001u +#define CYREG_PRT2_PS_ALIAS 0x40005092u +#define CYDEV_IO_PS_PRT3_BASE 0x40005093u +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001u +#define CYREG_PRT3_PS_ALIAS 0x40005093u +#define CYDEV_IO_PS_PRT4_BASE 0x40005094u +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001u +#define CYREG_PRT4_PS_ALIAS 0x40005094u +#define CYDEV_IO_PS_PRT5_BASE 0x40005095u +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001u +#define CYREG_PRT5_PS_ALIAS 0x40005095u +#define CYDEV_IO_PS_PRT6_BASE 0x40005096u +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001u +#define CYREG_PRT6_PS_ALIAS 0x40005096u +#define CYDEV_IO_PS_PRT12_BASE 0x4000509cu +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001u +#define CYREG_PRT12_PS_ALIAS 0x4000509cu +#define CYDEV_IO_PS_PRT15_BASE 0x4000509fu +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001u +#define CYREG_PRT15_PS15_ALIAS 0x4000509fu +#define CYDEV_IO_PRT_BASE 0x40005100u +#define CYDEV_IO_PRT_SIZE 0x00000100u +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100u +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010u +#define CYREG_PRT0_DR 0x40005100u +#define CYREG_PRT0_PS 0x40005101u +#define CYREG_PRT0_DM0 0x40005102u +#define CYREG_PRT0_DM1 0x40005103u +#define CYREG_PRT0_DM2 0x40005104u +#define CYREG_PRT0_SLW 0x40005105u +#define CYREG_PRT0_BYP 0x40005106u +#define CYREG_PRT0_BIE 0x40005107u +#define CYREG_PRT0_INP_DIS 0x40005108u +#define CYREG_PRT0_CTL 0x40005109u +#define CYREG_PRT0_PRT 0x4000510au +#define CYREG_PRT0_BIT_MASK 0x4000510bu +#define CYREG_PRT0_AMUX 0x4000510cu +#define CYREG_PRT0_AG 0x4000510du +#define CYREG_PRT0_LCD_COM_SEG 0x4000510eu +#define CYREG_PRT0_LCD_EN 0x4000510fu +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110u +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010u +#define CYREG_PRT1_DR 0x40005110u +#define CYREG_PRT1_PS 0x40005111u +#define CYREG_PRT1_DM0 0x40005112u +#define CYREG_PRT1_DM1 0x40005113u +#define CYREG_PRT1_DM2 0x40005114u +#define CYREG_PRT1_SLW 0x40005115u +#define CYREG_PRT1_BYP 0x40005116u +#define CYREG_PRT1_BIE 0x40005117u +#define CYREG_PRT1_INP_DIS 0x40005118u +#define CYREG_PRT1_CTL 0x40005119u +#define CYREG_PRT1_PRT 0x4000511au +#define CYREG_PRT1_BIT_MASK 0x4000511bu +#define CYREG_PRT1_AMUX 0x4000511cu +#define CYREG_PRT1_AG 0x4000511du +#define CYREG_PRT1_LCD_COM_SEG 0x4000511eu +#define CYREG_PRT1_LCD_EN 0x4000511fu +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120u +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010u +#define CYREG_PRT2_DR 0x40005120u +#define CYREG_PRT2_PS 0x40005121u +#define CYREG_PRT2_DM0 0x40005122u +#define CYREG_PRT2_DM1 0x40005123u +#define CYREG_PRT2_DM2 0x40005124u +#define CYREG_PRT2_SLW 0x40005125u +#define CYREG_PRT2_BYP 0x40005126u +#define CYREG_PRT2_BIE 0x40005127u +#define CYREG_PRT2_INP_DIS 0x40005128u +#define CYREG_PRT2_CTL 0x40005129u +#define CYREG_PRT2_PRT 0x4000512au +#define CYREG_PRT2_BIT_MASK 0x4000512bu +#define CYREG_PRT2_AMUX 0x4000512cu +#define CYREG_PRT2_AG 0x4000512du +#define CYREG_PRT2_LCD_COM_SEG 0x4000512eu +#define CYREG_PRT2_LCD_EN 0x4000512fu +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130u +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010u +#define CYREG_PRT3_DR 0x40005130u +#define CYREG_PRT3_PS 0x40005131u +#define CYREG_PRT3_DM0 0x40005132u +#define CYREG_PRT3_DM1 0x40005133u +#define CYREG_PRT3_DM2 0x40005134u +#define CYREG_PRT3_SLW 0x40005135u +#define CYREG_PRT3_BYP 0x40005136u +#define CYREG_PRT3_BIE 0x40005137u +#define CYREG_PRT3_INP_DIS 0x40005138u +#define CYREG_PRT3_CTL 0x40005139u +#define CYREG_PRT3_PRT 0x4000513au +#define CYREG_PRT3_BIT_MASK 0x4000513bu +#define CYREG_PRT3_AMUX 0x4000513cu +#define CYREG_PRT3_AG 0x4000513du +#define CYREG_PRT3_LCD_COM_SEG 0x4000513eu +#define CYREG_PRT3_LCD_EN 0x4000513fu +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140u +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010u +#define CYREG_PRT4_DR 0x40005140u +#define CYREG_PRT4_PS 0x40005141u +#define CYREG_PRT4_DM0 0x40005142u +#define CYREG_PRT4_DM1 0x40005143u +#define CYREG_PRT4_DM2 0x40005144u +#define CYREG_PRT4_SLW 0x40005145u +#define CYREG_PRT4_BYP 0x40005146u +#define CYREG_PRT4_BIE 0x40005147u +#define CYREG_PRT4_INP_DIS 0x40005148u +#define CYREG_PRT4_CTL 0x40005149u +#define CYREG_PRT4_PRT 0x4000514au +#define CYREG_PRT4_BIT_MASK 0x4000514bu +#define CYREG_PRT4_AMUX 0x4000514cu +#define CYREG_PRT4_AG 0x4000514du +#define CYREG_PRT4_LCD_COM_SEG 0x4000514eu +#define CYREG_PRT4_LCD_EN 0x4000514fu +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150u +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010u +#define CYREG_PRT5_DR 0x40005150u +#define CYREG_PRT5_PS 0x40005151u +#define CYREG_PRT5_DM0 0x40005152u +#define CYREG_PRT5_DM1 0x40005153u +#define CYREG_PRT5_DM2 0x40005154u +#define CYREG_PRT5_SLW 0x40005155u +#define CYREG_PRT5_BYP 0x40005156u +#define CYREG_PRT5_BIE 0x40005157u +#define CYREG_PRT5_INP_DIS 0x40005158u +#define CYREG_PRT5_CTL 0x40005159u +#define CYREG_PRT5_PRT 0x4000515au +#define CYREG_PRT5_BIT_MASK 0x4000515bu +#define CYREG_PRT5_AMUX 0x4000515cu +#define CYREG_PRT5_AG 0x4000515du +#define CYREG_PRT5_LCD_COM_SEG 0x4000515eu +#define CYREG_PRT5_LCD_EN 0x4000515fu +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160u +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010u +#define CYREG_PRT6_DR 0x40005160u +#define CYREG_PRT6_PS 0x40005161u +#define CYREG_PRT6_DM0 0x40005162u +#define CYREG_PRT6_DM1 0x40005163u +#define CYREG_PRT6_DM2 0x40005164u +#define CYREG_PRT6_SLW 0x40005165u +#define CYREG_PRT6_BYP 0x40005166u +#define CYREG_PRT6_BIE 0x40005167u +#define CYREG_PRT6_INP_DIS 0x40005168u +#define CYREG_PRT6_CTL 0x40005169u +#define CYREG_PRT6_PRT 0x4000516au +#define CYREG_PRT6_BIT_MASK 0x4000516bu +#define CYREG_PRT6_AMUX 0x4000516cu +#define CYREG_PRT6_AG 0x4000516du +#define CYREG_PRT6_LCD_COM_SEG 0x4000516eu +#define CYREG_PRT6_LCD_EN 0x4000516fu +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0u +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010u +#define CYREG_PRT12_DR 0x400051c0u +#define CYREG_PRT12_PS 0x400051c1u +#define CYREG_PRT12_DM0 0x400051c2u +#define CYREG_PRT12_DM1 0x400051c3u +#define CYREG_PRT12_DM2 0x400051c4u +#define CYREG_PRT12_SLW 0x400051c5u +#define CYREG_PRT12_BYP 0x400051c6u +#define CYREG_PRT12_BIE 0x400051c7u +#define CYREG_PRT12_INP_DIS 0x400051c8u +#define CYREG_PRT12_SIO_HYST_EN 0x400051c9u +#define CYREG_PRT12_PRT 0x400051cau +#define CYREG_PRT12_BIT_MASK 0x400051cbu +#define CYREG_PRT12_SIO_REG_HIFREQ 0x400051ccu +#define CYREG_PRT12_AG 0x400051cdu +#define CYREG_PRT12_SIO_CFG 0x400051ceu +#define CYREG_PRT12_SIO_DIFF 0x400051cfu +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0u +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010u +#define CYREG_PRT15_DR 0x400051f0u +#define CYREG_PRT15_PS 0x400051f1u +#define CYREG_PRT15_DM0 0x400051f2u +#define CYREG_PRT15_DM1 0x400051f3u +#define CYREG_PRT15_DM2 0x400051f4u +#define CYREG_PRT15_SLW 0x400051f5u +#define CYREG_PRT15_BYP 0x400051f6u +#define CYREG_PRT15_BIE 0x400051f7u +#define CYREG_PRT15_INP_DIS 0x400051f8u +#define CYREG_PRT15_CTL 0x400051f9u +#define CYREG_PRT15_PRT 0x400051fau +#define CYREG_PRT15_BIT_MASK 0x400051fbu +#define CYREG_PRT15_AMUX 0x400051fcu +#define CYREG_PRT15_AG 0x400051fdu +#define CYREG_PRT15_LCD_COM_SEG 0x400051feu +#define CYREG_PRT15_LCD_EN 0x400051ffu +#define CYDEV_PRTDSI_BASE 0x40005200u +#define CYDEV_PRTDSI_SIZE 0x0000007fu +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200u +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007u +#define CYREG_PRT0_OUT_SEL0 0x40005200u +#define CYREG_PRT0_OUT_SEL1 0x40005201u +#define CYREG_PRT0_OE_SEL0 0x40005202u +#define CYREG_PRT0_OE_SEL1 0x40005203u +#define CYREG_PRT0_DBL_SYNC_IN 0x40005204u +#define CYREG_PRT0_SYNC_OUT 0x40005205u +#define CYREG_PRT0_CAPS_SEL 0x40005206u +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208u +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007u +#define CYREG_PRT1_OUT_SEL0 0x40005208u +#define CYREG_PRT1_OUT_SEL1 0x40005209u +#define CYREG_PRT1_OE_SEL0 0x4000520au +#define CYREG_PRT1_OE_SEL1 0x4000520bu +#define CYREG_PRT1_DBL_SYNC_IN 0x4000520cu +#define CYREG_PRT1_SYNC_OUT 0x4000520du +#define CYREG_PRT1_CAPS_SEL 0x4000520eu +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210u +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007u +#define CYREG_PRT2_OUT_SEL0 0x40005210u +#define CYREG_PRT2_OUT_SEL1 0x40005211u +#define CYREG_PRT2_OE_SEL0 0x40005212u +#define CYREG_PRT2_OE_SEL1 0x40005213u +#define CYREG_PRT2_DBL_SYNC_IN 0x40005214u +#define CYREG_PRT2_SYNC_OUT 0x40005215u +#define CYREG_PRT2_CAPS_SEL 0x40005216u +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218u +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007u +#define CYREG_PRT3_OUT_SEL0 0x40005218u +#define CYREG_PRT3_OUT_SEL1 0x40005219u +#define CYREG_PRT3_OE_SEL0 0x4000521au +#define CYREG_PRT3_OE_SEL1 0x4000521bu +#define CYREG_PRT3_DBL_SYNC_IN 0x4000521cu +#define CYREG_PRT3_SYNC_OUT 0x4000521du +#define CYREG_PRT3_CAPS_SEL 0x4000521eu +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220u +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007u +#define CYREG_PRT4_OUT_SEL0 0x40005220u +#define CYREG_PRT4_OUT_SEL1 0x40005221u +#define CYREG_PRT4_OE_SEL0 0x40005222u +#define CYREG_PRT4_OE_SEL1 0x40005223u +#define CYREG_PRT4_DBL_SYNC_IN 0x40005224u +#define CYREG_PRT4_SYNC_OUT 0x40005225u +#define CYREG_PRT4_CAPS_SEL 0x40005226u +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228u +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007u +#define CYREG_PRT5_OUT_SEL0 0x40005228u +#define CYREG_PRT5_OUT_SEL1 0x40005229u +#define CYREG_PRT5_OE_SEL0 0x4000522au +#define CYREG_PRT5_OE_SEL1 0x4000522bu +#define CYREG_PRT5_DBL_SYNC_IN 0x4000522cu +#define CYREG_PRT5_SYNC_OUT 0x4000522du +#define CYREG_PRT5_CAPS_SEL 0x4000522eu +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230u +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007u +#define CYREG_PRT6_OUT_SEL0 0x40005230u +#define CYREG_PRT6_OUT_SEL1 0x40005231u +#define CYREG_PRT6_OE_SEL0 0x40005232u +#define CYREG_PRT6_OE_SEL1 0x40005233u +#define CYREG_PRT6_DBL_SYNC_IN 0x40005234u +#define CYREG_PRT6_SYNC_OUT 0x40005235u +#define CYREG_PRT6_CAPS_SEL 0x40005236u +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260u +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006u +#define CYREG_PRT12_OUT_SEL0 0x40005260u +#define CYREG_PRT12_OUT_SEL1 0x40005261u +#define CYREG_PRT12_OE_SEL0 0x40005262u +#define CYREG_PRT12_OE_SEL1 0x40005263u +#define CYREG_PRT12_DBL_SYNC_IN 0x40005264u +#define CYREG_PRT12_SYNC_OUT 0x40005265u +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278u +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007u +#define CYREG_PRT15_OUT_SEL0 0x40005278u +#define CYREG_PRT15_OUT_SEL1 0x40005279u +#define CYREG_PRT15_OE_SEL0 0x4000527au +#define CYREG_PRT15_OE_SEL1 0x4000527bu +#define CYREG_PRT15_DBL_SYNC_IN 0x4000527cu +#define CYREG_PRT15_SYNC_OUT 0x4000527du +#define CYREG_PRT15_CAPS_SEL 0x4000527eu +#define CYDEV_EMIF_BASE 0x40005400u +#define CYDEV_EMIF_SIZE 0x00000007u +#define CYREG_EMIF_NO_UDB 0x40005400u +#define CYREG_EMIF_RP_WAIT_STATES 0x40005401u +#define CYREG_EMIF_MEM_DWN 0x40005402u +#define CYREG_EMIF_MEMCLK_DIV 0x40005403u +#define CYREG_EMIF_CLOCK_EN 0x40005404u +#define CYREG_EMIF_EM_TYPE 0x40005405u +#define CYREG_EMIF_WP_WAIT_STATES 0x40005406u +#define CYDEV_ANAIF_BASE 0x40005800u +#define CYDEV_ANAIF_SIZE 0x000003a9u +#define CYDEV_ANAIF_CFG_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SIZE 0x0000010fu +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003u +#define CYREG_SC0_CR0 0x40005800u +#define CYREG_SC0_CR1 0x40005801u +#define CYREG_SC0_CR2 0x40005802u +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804u +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003u +#define CYREG_SC1_CR0 0x40005804u +#define CYREG_SC1_CR1 0x40005805u +#define CYREG_SC1_CR2 0x40005806u +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808u +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003u +#define CYREG_SC2_CR0 0x40005808u +#define CYREG_SC2_CR1 0x40005809u +#define CYREG_SC2_CR2 0x4000580au +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580cu +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003u +#define CYREG_SC3_CR0 0x4000580cu +#define CYREG_SC3_CR1 0x4000580du +#define CYREG_SC3_CR2 0x4000580eu +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820u +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003u +#define CYREG_DAC0_CR0 0x40005820u +#define CYREG_DAC0_CR1 0x40005821u +#define CYREG_DAC0_TST 0x40005822u +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824u +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003u +#define CYREG_DAC1_CR0 0x40005824u +#define CYREG_DAC1_CR1 0x40005825u +#define CYREG_DAC1_TST 0x40005826u +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828u +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003u +#define CYREG_DAC2_CR0 0x40005828u +#define CYREG_DAC2_CR1 0x40005829u +#define CYREG_DAC2_TST 0x4000582au +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582cu +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003u +#define CYREG_DAC3_CR0 0x4000582cu +#define CYREG_DAC3_CR1 0x4000582du +#define CYREG_DAC3_TST 0x4000582eu +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840u +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001u +#define CYREG_CMP0_CR 0x40005840u +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841u +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001u +#define CYREG_CMP1_CR 0x40005841u +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842u +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001u +#define CYREG_CMP2_CR 0x40005842u +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843u +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001u +#define CYREG_CMP3_CR 0x40005843u +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848u +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002u +#define CYREG_LUT0_CR 0x40005848u +#define CYREG_LUT0_MX 0x40005849u +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584au +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002u +#define CYREG_LUT1_CR 0x4000584au +#define CYREG_LUT1_MX 0x4000584bu +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584cu +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002u +#define CYREG_LUT2_CR 0x4000584cu +#define CYREG_LUT2_MX 0x4000584du +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584eu +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002u +#define CYREG_LUT3_CR 0x4000584eu +#define CYREG_LUT3_MX 0x4000584fu +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858u +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002u +#define CYREG_OPAMP0_CR 0x40005858u +#define CYREG_OPAMP0_RSVD 0x40005859u +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585au +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002u +#define CYREG_OPAMP1_CR 0x4000585au +#define CYREG_OPAMP1_RSVD 0x4000585bu +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585cu +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002u +#define CYREG_OPAMP2_CR 0x4000585cu +#define CYREG_OPAMP2_RSVD 0x4000585du +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585eu +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002u +#define CYREG_OPAMP3_CR 0x4000585eu +#define CYREG_OPAMP3_RSVD 0x4000585fu +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868u +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002u +#define CYREG_LCDDAC_CR0 0x40005868u +#define CYREG_LCDDAC_CR1 0x40005869u +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586au +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001u +#define CYREG_LCDDRV_CR 0x4000586au +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586bu +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001u +#define CYREG_LCDTMR_CFG 0x4000586bu +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586cu +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004u +#define CYREG_BG_CR0 0x4000586cu +#define CYREG_BG_RSVD 0x4000586du +#define CYREG_BG_DFT0 0x4000586eu +#define CYREG_BG_DFT1 0x4000586fu +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870u +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002u +#define CYREG_CAPSL_CFG0 0x40005870u +#define CYREG_CAPSL_CFG1 0x40005871u +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872u +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002u +#define CYREG_CAPSR_CFG0 0x40005872u +#define CYREG_CAPSR_CFG1 0x40005873u +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876u +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002u +#define CYREG_PUMP_CR0 0x40005876u +#define CYREG_PUMP_CR1 0x40005877u +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878u +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002u +#define CYREG_LPF0_CR0 0x40005878u +#define CYREG_LPF0_RSVD 0x40005879u +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587au +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002u +#define CYREG_LPF1_CR0 0x4000587au +#define CYREG_LPF1_RSVD 0x4000587bu +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587cu +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001u +#define CYREG_ANAIF_CFG_MISC_CR0 0x4000587cu +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880u +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020u +#define CYREG_DSM0_CR0 0x40005880u +#define CYREG_DSM0_CR1 0x40005881u +#define CYREG_DSM0_CR2 0x40005882u +#define CYREG_DSM0_CR3 0x40005883u +#define CYREG_DSM0_CR4 0x40005884u +#define CYREG_DSM0_CR5 0x40005885u +#define CYREG_DSM0_CR6 0x40005886u +#define CYREG_DSM0_CR7 0x40005887u +#define CYREG_DSM0_CR8 0x40005888u +#define CYREG_DSM0_CR9 0x40005889u +#define CYREG_DSM0_CR10 0x4000588au +#define CYREG_DSM0_CR11 0x4000588bu +#define CYREG_DSM0_CR12 0x4000588cu +#define CYREG_DSM0_CR13 0x4000588du +#define CYREG_DSM0_CR14 0x4000588eu +#define CYREG_DSM0_CR15 0x4000588fu +#define CYREG_DSM0_CR16 0x40005890u +#define CYREG_DSM0_CR17 0x40005891u +#define CYREG_DSM0_REF0 0x40005892u +#define CYREG_DSM0_REF1 0x40005893u +#define CYREG_DSM0_REF2 0x40005894u +#define CYREG_DSM0_REF3 0x40005895u +#define CYREG_DSM0_DEM0 0x40005896u +#define CYREG_DSM0_DEM1 0x40005897u +#define CYREG_DSM0_TST0 0x40005898u +#define CYREG_DSM0_TST1 0x40005899u +#define CYREG_DSM0_BUF0 0x4000589au +#define CYREG_DSM0_BUF1 0x4000589bu +#define CYREG_DSM0_BUF2 0x4000589cu +#define CYREG_DSM0_BUF3 0x4000589du +#define CYREG_DSM0_MISC 0x4000589eu +#define CYREG_DSM0_RSVD1 0x4000589fu +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900u +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007u +#define CYREG_SAR0_CSR0 0x40005900u +#define CYREG_SAR0_CSR1 0x40005901u +#define CYREG_SAR0_CSR2 0x40005902u +#define CYREG_SAR0_CSR3 0x40005903u +#define CYREG_SAR0_CSR4 0x40005904u +#define CYREG_SAR0_CSR5 0x40005905u +#define CYREG_SAR0_CSR6 0x40005906u +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908u +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007u +#define CYREG_SAR1_CSR0 0x40005908u +#define CYREG_SAR1_CSR1 0x40005909u +#define CYREG_SAR1_CSR2 0x4000590au +#define CYREG_SAR1_CSR3 0x4000590bu +#define CYREG_SAR1_CSR4 0x4000590cu +#define CYREG_SAR1_CSR5 0x4000590du +#define CYREG_SAR1_CSR6 0x4000590eu +#define CYDEV_ANAIF_RT_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SIZE 0x00000162u +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000du +#define CYREG_SC0_SW0 0x40005a00u +#define CYREG_SC0_SW2 0x40005a02u +#define CYREG_SC0_SW3 0x40005a03u +#define CYREG_SC0_SW4 0x40005a04u +#define CYREG_SC0_SW6 0x40005a06u +#define CYREG_SC0_SW7 0x40005a07u +#define CYREG_SC0_SW8 0x40005a08u +#define CYREG_SC0_SW10 0x40005a0au +#define CYREG_SC0_CLK 0x40005a0bu +#define CYREG_SC0_BST 0x40005a0cu +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10u +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000du +#define CYREG_SC1_SW0 0x40005a10u +#define CYREG_SC1_SW2 0x40005a12u +#define CYREG_SC1_SW3 0x40005a13u +#define CYREG_SC1_SW4 0x40005a14u +#define CYREG_SC1_SW6 0x40005a16u +#define CYREG_SC1_SW7 0x40005a17u +#define CYREG_SC1_SW8 0x40005a18u +#define CYREG_SC1_SW10 0x40005a1au +#define CYREG_SC1_CLK 0x40005a1bu +#define CYREG_SC1_BST 0x40005a1cu +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20u +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000du +#define CYREG_SC2_SW0 0x40005a20u +#define CYREG_SC2_SW2 0x40005a22u +#define CYREG_SC2_SW3 0x40005a23u +#define CYREG_SC2_SW4 0x40005a24u +#define CYREG_SC2_SW6 0x40005a26u +#define CYREG_SC2_SW7 0x40005a27u +#define CYREG_SC2_SW8 0x40005a28u +#define CYREG_SC2_SW10 0x40005a2au +#define CYREG_SC2_CLK 0x40005a2bu +#define CYREG_SC2_BST 0x40005a2cu +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30u +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000du +#define CYREG_SC3_SW0 0x40005a30u +#define CYREG_SC3_SW2 0x40005a32u +#define CYREG_SC3_SW3 0x40005a33u +#define CYREG_SC3_SW4 0x40005a34u +#define CYREG_SC3_SW6 0x40005a36u +#define CYREG_SC3_SW7 0x40005a37u +#define CYREG_SC3_SW8 0x40005a38u +#define CYREG_SC3_SW10 0x40005a3au +#define CYREG_SC3_CLK 0x40005a3bu +#define CYREG_SC3_BST 0x40005a3cu +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80u +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008u +#define CYREG_DAC0_SW0 0x40005a80u +#define CYREG_DAC0_SW2 0x40005a82u +#define CYREG_DAC0_SW3 0x40005a83u +#define CYREG_DAC0_SW4 0x40005a84u +#define CYREG_DAC0_STROBE 0x40005a87u +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88u +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008u +#define CYREG_DAC1_SW0 0x40005a88u +#define CYREG_DAC1_SW2 0x40005a8au +#define CYREG_DAC1_SW3 0x40005a8bu +#define CYREG_DAC1_SW4 0x40005a8cu +#define CYREG_DAC1_STROBE 0x40005a8fu +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90u +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008u +#define CYREG_DAC2_SW0 0x40005a90u +#define CYREG_DAC2_SW2 0x40005a92u +#define CYREG_DAC2_SW3 0x40005a93u +#define CYREG_DAC2_SW4 0x40005a94u +#define CYREG_DAC2_STROBE 0x40005a97u +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98u +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008u +#define CYREG_DAC3_SW0 0x40005a98u +#define CYREG_DAC3_SW2 0x40005a9au +#define CYREG_DAC3_SW3 0x40005a9bu +#define CYREG_DAC3_SW4 0x40005a9cu +#define CYREG_DAC3_STROBE 0x40005a9fu +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0u +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008u +#define CYREG_CMP0_SW0 0x40005ac0u +#define CYREG_CMP0_SW2 0x40005ac2u +#define CYREG_CMP0_SW3 0x40005ac3u +#define CYREG_CMP0_SW4 0x40005ac4u +#define CYREG_CMP0_SW6 0x40005ac6u +#define CYREG_CMP0_CLK 0x40005ac7u +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8u +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008u +#define CYREG_CMP1_SW0 0x40005ac8u +#define CYREG_CMP1_SW2 0x40005acau +#define CYREG_CMP1_SW3 0x40005acbu +#define CYREG_CMP1_SW4 0x40005accu +#define CYREG_CMP1_SW6 0x40005aceu +#define CYREG_CMP1_CLK 0x40005acfu +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0u +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008u +#define CYREG_CMP2_SW0 0x40005ad0u +#define CYREG_CMP2_SW2 0x40005ad2u +#define CYREG_CMP2_SW3 0x40005ad3u +#define CYREG_CMP2_SW4 0x40005ad4u +#define CYREG_CMP2_SW6 0x40005ad6u +#define CYREG_CMP2_CLK 0x40005ad7u +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8u +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008u +#define CYREG_CMP3_SW0 0x40005ad8u +#define CYREG_CMP3_SW2 0x40005adau +#define CYREG_CMP3_SW3 0x40005adbu +#define CYREG_CMP3_SW4 0x40005adcu +#define CYREG_CMP3_SW6 0x40005adeu +#define CYREG_CMP3_CLK 0x40005adfu +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00u +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008u +#define CYREG_DSM0_SW0 0x40005b00u +#define CYREG_DSM0_SW2 0x40005b02u +#define CYREG_DSM0_SW3 0x40005b03u +#define CYREG_DSM0_SW4 0x40005b04u +#define CYREG_DSM0_SW6 0x40005b06u +#define CYREG_DSM0_CLK 0x40005b07u +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20u +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008u +#define CYREG_SAR0_SW0 0x40005b20u +#define CYREG_SAR0_SW2 0x40005b22u +#define CYREG_SAR0_SW3 0x40005b23u +#define CYREG_SAR0_SW4 0x40005b24u +#define CYREG_SAR0_SW6 0x40005b26u +#define CYREG_SAR0_CLK 0x40005b27u +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28u +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008u +#define CYREG_SAR1_SW0 0x40005b28u +#define CYREG_SAR1_SW2 0x40005b2au +#define CYREG_SAR1_SW3 0x40005b2bu +#define CYREG_SAR1_SW4 0x40005b2cu +#define CYREG_SAR1_SW6 0x40005b2eu +#define CYREG_SAR1_CLK 0x40005b2fu +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40u +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002u +#define CYREG_OPAMP0_MX 0x40005b40u +#define CYREG_OPAMP0_SW 0x40005b41u +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42u +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002u +#define CYREG_OPAMP1_MX 0x40005b42u +#define CYREG_OPAMP1_SW 0x40005b43u +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44u +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002u +#define CYREG_OPAMP2_MX 0x40005b44u +#define CYREG_OPAMP2_SW 0x40005b45u +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46u +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002u +#define CYREG_OPAMP3_MX 0x40005b46u +#define CYREG_OPAMP3_SW 0x40005b47u +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50u +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005u +#define CYREG_LCDDAC_SW0 0x40005b50u +#define CYREG_LCDDAC_SW1 0x40005b51u +#define CYREG_LCDDAC_SW2 0x40005b52u +#define CYREG_LCDDAC_SW3 0x40005b53u +#define CYREG_LCDDAC_SW4 0x40005b54u +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56u +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001u +#define CYREG_SC_MISC 0x40005b56u +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58u +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004u +#define CYREG_BUS_SW0 0x40005b58u +#define CYREG_BUS_SW2 0x40005b5au +#define CYREG_BUS_SW3 0x40005b5bu +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5cu +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006u +#define CYREG_DFT_CR0 0x40005b5cu +#define CYREG_DFT_CR1 0x40005b5du +#define CYREG_DFT_CR2 0x40005b5eu +#define CYREG_DFT_CR3 0x40005b5fu +#define CYREG_DFT_CR4 0x40005b60u +#define CYREG_DFT_CR5 0x40005b61u +#define CYDEV_ANAIF_WRK_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_SIZE 0x00000029u +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001u +#define CYREG_DAC0_D 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001u +#define CYREG_DAC1_D 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001u +#define CYREG_DAC2_D 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83u +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001u +#define CYREG_DAC3_D 0x40005b83u +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88u +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002u +#define CYREG_DSM0_OUT0 0x40005b88u +#define CYREG_DSM0_OUT1 0x40005b89u +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90u +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005u +#define CYREG_LUT_SR 0x40005b90u +#define CYREG_LUT_WRK1 0x40005b91u +#define CYREG_LUT_MSK 0x40005b92u +#define CYREG_LUT_CLK 0x40005b93u +#define CYREG_LUT_CPTR 0x40005b94u +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96u +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002u +#define CYREG_CMP_WRK 0x40005b96u +#define CYREG_CMP_TST 0x40005b97u +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98u +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005u +#define CYREG_SC_SR 0x40005b98u +#define CYREG_SC_WRK1 0x40005b99u +#define CYREG_SC_MSK 0x40005b9au +#define CYREG_SC_CMPINV 0x40005b9bu +#define CYREG_SC_CPTR 0x40005b9cu +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0u +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002u +#define CYREG_SAR0_WRK0 0x40005ba0u +#define CYREG_SAR0_WRK1 0x40005ba1u +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2u +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002u +#define CYREG_SAR1_WRK0 0x40005ba2u +#define CYREG_SAR1_WRK1 0x40005ba3u +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8u +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001u +#define CYREG_ANAIF_WRK_SARS_SOF 0x40005ba8u +#define CYDEV_USB_BASE 0x40006000u +#define CYDEV_USB_SIZE 0x00000300u +#define CYREG_USB_EP0_DR0 0x40006000u +#define CYREG_USB_EP0_DR1 0x40006001u +#define CYREG_USB_EP0_DR2 0x40006002u +#define CYREG_USB_EP0_DR3 0x40006003u +#define CYREG_USB_EP0_DR4 0x40006004u +#define CYREG_USB_EP0_DR5 0x40006005u +#define CYREG_USB_EP0_DR6 0x40006006u +#define CYREG_USB_EP0_DR7 0x40006007u +#define CYREG_USB_CR0 0x40006008u +#define CYREG_USB_CR1 0x40006009u +#define CYREG_USB_SIE_EP_INT_EN 0x4000600au +#define CYREG_USB_SIE_EP_INT_SR 0x4000600bu +#define CYDEV_USB_SIE_EP1_BASE 0x4000600cu +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003u +#define CYREG_USB_SIE_EP1_CNT0 0x4000600cu +#define CYREG_USB_SIE_EP1_CNT1 0x4000600du +#define CYREG_USB_SIE_EP1_CR0 0x4000600eu +#define CYREG_USB_USBIO_CR0 0x40006010u +#define CYREG_USB_USBIO_CR1 0x40006012u +#define CYREG_USB_DYN_RECONFIG 0x40006014u +#define CYREG_USB_SOF0 0x40006018u +#define CYREG_USB_SOF1 0x40006019u +#define CYDEV_USB_SIE_EP2_BASE 0x4000601cu +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003u +#define CYREG_USB_SIE_EP2_CNT0 0x4000601cu +#define CYREG_USB_SIE_EP2_CNT1 0x4000601du +#define CYREG_USB_SIE_EP2_CR0 0x4000601eu +#define CYREG_USB_EP0_CR 0x40006028u +#define CYREG_USB_EP0_CNT 0x40006029u +#define CYDEV_USB_SIE_EP3_BASE 0x4000602cu +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003u +#define CYREG_USB_SIE_EP3_CNT0 0x4000602cu +#define CYREG_USB_SIE_EP3_CNT1 0x4000602du +#define CYREG_USB_SIE_EP3_CR0 0x4000602eu +#define CYDEV_USB_SIE_EP4_BASE 0x4000603cu +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003u +#define CYREG_USB_SIE_EP4_CNT0 0x4000603cu +#define CYREG_USB_SIE_EP4_CNT1 0x4000603du +#define CYREG_USB_SIE_EP4_CR0 0x4000603eu +#define CYDEV_USB_SIE_EP5_BASE 0x4000604cu +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003u +#define CYREG_USB_SIE_EP5_CNT0 0x4000604cu +#define CYREG_USB_SIE_EP5_CNT1 0x4000604du +#define CYREG_USB_SIE_EP5_CR0 0x4000604eu +#define CYDEV_USB_SIE_EP6_BASE 0x4000605cu +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003u +#define CYREG_USB_SIE_EP6_CNT0 0x4000605cu +#define CYREG_USB_SIE_EP6_CNT1 0x4000605du +#define CYREG_USB_SIE_EP6_CR0 0x4000605eu +#define CYDEV_USB_SIE_EP7_BASE 0x4000606cu +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003u +#define CYREG_USB_SIE_EP7_CNT0 0x4000606cu +#define CYREG_USB_SIE_EP7_CNT1 0x4000606du +#define CYREG_USB_SIE_EP7_CR0 0x4000606eu +#define CYDEV_USB_SIE_EP8_BASE 0x4000607cu +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003u +#define CYREG_USB_SIE_EP8_CNT0 0x4000607cu +#define CYREG_USB_SIE_EP8_CNT1 0x4000607du +#define CYREG_USB_SIE_EP8_CR0 0x4000607eu +#define CYDEV_USB_ARB_EP1_BASE 0x40006080u +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003u +#define CYREG_USB_ARB_EP1_CFG 0x40006080u +#define CYREG_USB_ARB_EP1_INT_EN 0x40006081u +#define CYREG_USB_ARB_EP1_SR 0x40006082u +#define CYDEV_USB_ARB_RW1_BASE 0x40006084u +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005u +#define CYREG_USB_ARB_RW1_WA 0x40006084u +#define CYREG_USB_ARB_RW1_WA_MSB 0x40006085u +#define CYREG_USB_ARB_RW1_RA 0x40006086u +#define CYREG_USB_ARB_RW1_RA_MSB 0x40006087u +#define CYREG_USB_ARB_RW1_DR 0x40006088u +#define CYREG_USB_BUF_SIZE 0x4000608cu +#define CYREG_USB_EP_ACTIVE 0x4000608eu +#define CYREG_USB_EP_TYPE 0x4000608fu +#define CYDEV_USB_ARB_EP2_BASE 0x40006090u +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003u +#define CYREG_USB_ARB_EP2_CFG 0x40006090u +#define CYREG_USB_ARB_EP2_INT_EN 0x40006091u +#define CYREG_USB_ARB_EP2_SR 0x40006092u +#define CYDEV_USB_ARB_RW2_BASE 0x40006094u +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005u +#define CYREG_USB_ARB_RW2_WA 0x40006094u +#define CYREG_USB_ARB_RW2_WA_MSB 0x40006095u +#define CYREG_USB_ARB_RW2_RA 0x40006096u +#define CYREG_USB_ARB_RW2_RA_MSB 0x40006097u +#define CYREG_USB_ARB_RW2_DR 0x40006098u +#define CYREG_USB_ARB_CFG 0x4000609cu +#define CYREG_USB_USB_CLK_EN 0x4000609du +#define CYREG_USB_ARB_INT_EN 0x4000609eu +#define CYREG_USB_ARB_INT_SR 0x4000609fu +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0u +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003u +#define CYREG_USB_ARB_EP3_CFG 0x400060a0u +#define CYREG_USB_ARB_EP3_INT_EN 0x400060a1u +#define CYREG_USB_ARB_EP3_SR 0x400060a2u +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4u +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005u +#define CYREG_USB_ARB_RW3_WA 0x400060a4u +#define CYREG_USB_ARB_RW3_WA_MSB 0x400060a5u +#define CYREG_USB_ARB_RW3_RA 0x400060a6u +#define CYREG_USB_ARB_RW3_RA_MSB 0x400060a7u +#define CYREG_USB_ARB_RW3_DR 0x400060a8u +#define CYREG_USB_CWA 0x400060acu +#define CYREG_USB_CWA_MSB 0x400060adu +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0u +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003u +#define CYREG_USB_ARB_EP4_CFG 0x400060b0u +#define CYREG_USB_ARB_EP4_INT_EN 0x400060b1u +#define CYREG_USB_ARB_EP4_SR 0x400060b2u +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4u +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005u +#define CYREG_USB_ARB_RW4_WA 0x400060b4u +#define CYREG_USB_ARB_RW4_WA_MSB 0x400060b5u +#define CYREG_USB_ARB_RW4_RA 0x400060b6u +#define CYREG_USB_ARB_RW4_RA_MSB 0x400060b7u +#define CYREG_USB_ARB_RW4_DR 0x400060b8u +#define CYREG_USB_DMA_THRES 0x400060bcu +#define CYREG_USB_DMA_THRES_MSB 0x400060bdu +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0u +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003u +#define CYREG_USB_ARB_EP5_CFG 0x400060c0u +#define CYREG_USB_ARB_EP5_INT_EN 0x400060c1u +#define CYREG_USB_ARB_EP5_SR 0x400060c2u +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4u +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005u +#define CYREG_USB_ARB_RW5_WA 0x400060c4u +#define CYREG_USB_ARB_RW5_WA_MSB 0x400060c5u +#define CYREG_USB_ARB_RW5_RA 0x400060c6u +#define CYREG_USB_ARB_RW5_RA_MSB 0x400060c7u +#define CYREG_USB_ARB_RW5_DR 0x400060c8u +#define CYREG_USB_BUS_RST_CNT 0x400060ccu +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0u +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003u +#define CYREG_USB_ARB_EP6_CFG 0x400060d0u +#define CYREG_USB_ARB_EP6_INT_EN 0x400060d1u +#define CYREG_USB_ARB_EP6_SR 0x400060d2u +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4u +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005u +#define CYREG_USB_ARB_RW6_WA 0x400060d4u +#define CYREG_USB_ARB_RW6_WA_MSB 0x400060d5u +#define CYREG_USB_ARB_RW6_RA 0x400060d6u +#define CYREG_USB_ARB_RW6_RA_MSB 0x400060d7u +#define CYREG_USB_ARB_RW6_DR 0x400060d8u +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0u +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003u +#define CYREG_USB_ARB_EP7_CFG 0x400060e0u +#define CYREG_USB_ARB_EP7_INT_EN 0x400060e1u +#define CYREG_USB_ARB_EP7_SR 0x400060e2u +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4u +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005u +#define CYREG_USB_ARB_RW7_WA 0x400060e4u +#define CYREG_USB_ARB_RW7_WA_MSB 0x400060e5u +#define CYREG_USB_ARB_RW7_RA 0x400060e6u +#define CYREG_USB_ARB_RW7_RA_MSB 0x400060e7u +#define CYREG_USB_ARB_RW7_DR 0x400060e8u +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0u +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003u +#define CYREG_USB_ARB_EP8_CFG 0x400060f0u +#define CYREG_USB_ARB_EP8_INT_EN 0x400060f1u +#define CYREG_USB_ARB_EP8_SR 0x400060f2u +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4u +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005u +#define CYREG_USB_ARB_RW8_WA 0x400060f4u +#define CYREG_USB_ARB_RW8_WA_MSB 0x400060f5u +#define CYREG_USB_ARB_RW8_RA 0x400060f6u +#define CYREG_USB_ARB_RW8_RA_MSB 0x400060f7u +#define CYREG_USB_ARB_RW8_DR 0x400060f8u +#define CYDEV_USB_MEM_BASE 0x40006100u +#define CYDEV_USB_MEM_SIZE 0x00000200u +#define CYREG_USB_MEM_DATA_MBASE 0x40006100u +#define CYREG_USB_MEM_DATA_MSIZE 0x00000200u +#define CYDEV_UWRK_BASE 0x40006400u +#define CYDEV_UWRK_SIZE 0x00000b60u +#define CYDEV_UWRK_UWRK8_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0u +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0u +#define CYREG_B0_UDB00_A0 0x40006400u +#define CYREG_B0_UDB01_A0 0x40006401u +#define CYREG_B0_UDB02_A0 0x40006402u +#define CYREG_B0_UDB03_A0 0x40006403u +#define CYREG_B0_UDB04_A0 0x40006404u +#define CYREG_B0_UDB05_A0 0x40006405u +#define CYREG_B0_UDB06_A0 0x40006406u +#define CYREG_B0_UDB07_A0 0x40006407u +#define CYREG_B0_UDB08_A0 0x40006408u +#define CYREG_B0_UDB09_A0 0x40006409u +#define CYREG_B0_UDB10_A0 0x4000640au +#define CYREG_B0_UDB11_A0 0x4000640bu +#define CYREG_B0_UDB12_A0 0x4000640cu +#define CYREG_B0_UDB13_A0 0x4000640du +#define CYREG_B0_UDB14_A0 0x4000640eu +#define CYREG_B0_UDB15_A0 0x4000640fu +#define CYREG_B0_UDB00_A1 0x40006410u +#define CYREG_B0_UDB01_A1 0x40006411u +#define CYREG_B0_UDB02_A1 0x40006412u +#define CYREG_B0_UDB03_A1 0x40006413u +#define CYREG_B0_UDB04_A1 0x40006414u +#define CYREG_B0_UDB05_A1 0x40006415u +#define CYREG_B0_UDB06_A1 0x40006416u +#define CYREG_B0_UDB07_A1 0x40006417u +#define CYREG_B0_UDB08_A1 0x40006418u +#define CYREG_B0_UDB09_A1 0x40006419u +#define CYREG_B0_UDB10_A1 0x4000641au +#define CYREG_B0_UDB11_A1 0x4000641bu +#define CYREG_B0_UDB12_A1 0x4000641cu +#define CYREG_B0_UDB13_A1 0x4000641du +#define CYREG_B0_UDB14_A1 0x4000641eu +#define CYREG_B0_UDB15_A1 0x4000641fu +#define CYREG_B0_UDB00_D0 0x40006420u +#define CYREG_B0_UDB01_D0 0x40006421u +#define CYREG_B0_UDB02_D0 0x40006422u +#define CYREG_B0_UDB03_D0 0x40006423u +#define CYREG_B0_UDB04_D0 0x40006424u +#define CYREG_B0_UDB05_D0 0x40006425u +#define CYREG_B0_UDB06_D0 0x40006426u +#define CYREG_B0_UDB07_D0 0x40006427u +#define CYREG_B0_UDB08_D0 0x40006428u +#define CYREG_B0_UDB09_D0 0x40006429u +#define CYREG_B0_UDB10_D0 0x4000642au +#define CYREG_B0_UDB11_D0 0x4000642bu +#define CYREG_B0_UDB12_D0 0x4000642cu +#define CYREG_B0_UDB13_D0 0x4000642du +#define CYREG_B0_UDB14_D0 0x4000642eu +#define CYREG_B0_UDB15_D0 0x4000642fu +#define CYREG_B0_UDB00_D1 0x40006430u +#define CYREG_B0_UDB01_D1 0x40006431u +#define CYREG_B0_UDB02_D1 0x40006432u +#define CYREG_B0_UDB03_D1 0x40006433u +#define CYREG_B0_UDB04_D1 0x40006434u +#define CYREG_B0_UDB05_D1 0x40006435u +#define CYREG_B0_UDB06_D1 0x40006436u +#define CYREG_B0_UDB07_D1 0x40006437u +#define CYREG_B0_UDB08_D1 0x40006438u +#define CYREG_B0_UDB09_D1 0x40006439u +#define CYREG_B0_UDB10_D1 0x4000643au +#define CYREG_B0_UDB11_D1 0x4000643bu +#define CYREG_B0_UDB12_D1 0x4000643cu +#define CYREG_B0_UDB13_D1 0x4000643du +#define CYREG_B0_UDB14_D1 0x4000643eu +#define CYREG_B0_UDB15_D1 0x4000643fu +#define CYREG_B0_UDB00_F0 0x40006440u +#define CYREG_B0_UDB01_F0 0x40006441u +#define CYREG_B0_UDB02_F0 0x40006442u +#define CYREG_B0_UDB03_F0 0x40006443u +#define CYREG_B0_UDB04_F0 0x40006444u +#define CYREG_B0_UDB05_F0 0x40006445u +#define CYREG_B0_UDB06_F0 0x40006446u +#define CYREG_B0_UDB07_F0 0x40006447u +#define CYREG_B0_UDB08_F0 0x40006448u +#define CYREG_B0_UDB09_F0 0x40006449u +#define CYREG_B0_UDB10_F0 0x4000644au +#define CYREG_B0_UDB11_F0 0x4000644bu +#define CYREG_B0_UDB12_F0 0x4000644cu +#define CYREG_B0_UDB13_F0 0x4000644du +#define CYREG_B0_UDB14_F0 0x4000644eu +#define CYREG_B0_UDB15_F0 0x4000644fu +#define CYREG_B0_UDB00_F1 0x40006450u +#define CYREG_B0_UDB01_F1 0x40006451u +#define CYREG_B0_UDB02_F1 0x40006452u +#define CYREG_B0_UDB03_F1 0x40006453u +#define CYREG_B0_UDB04_F1 0x40006454u +#define CYREG_B0_UDB05_F1 0x40006455u +#define CYREG_B0_UDB06_F1 0x40006456u +#define CYREG_B0_UDB07_F1 0x40006457u +#define CYREG_B0_UDB08_F1 0x40006458u +#define CYREG_B0_UDB09_F1 0x40006459u +#define CYREG_B0_UDB10_F1 0x4000645au +#define CYREG_B0_UDB11_F1 0x4000645bu +#define CYREG_B0_UDB12_F1 0x4000645cu +#define CYREG_B0_UDB13_F1 0x4000645du +#define CYREG_B0_UDB14_F1 0x4000645eu +#define CYREG_B0_UDB15_F1 0x4000645fu +#define CYREG_B0_UDB00_ST 0x40006460u +#define CYREG_B0_UDB01_ST 0x40006461u +#define CYREG_B0_UDB02_ST 0x40006462u +#define CYREG_B0_UDB03_ST 0x40006463u +#define CYREG_B0_UDB04_ST 0x40006464u +#define CYREG_B0_UDB05_ST 0x40006465u +#define CYREG_B0_UDB06_ST 0x40006466u +#define CYREG_B0_UDB07_ST 0x40006467u +#define CYREG_B0_UDB08_ST 0x40006468u +#define CYREG_B0_UDB09_ST 0x40006469u +#define CYREG_B0_UDB10_ST 0x4000646au +#define CYREG_B0_UDB11_ST 0x4000646bu +#define CYREG_B0_UDB12_ST 0x4000646cu +#define CYREG_B0_UDB13_ST 0x4000646du +#define CYREG_B0_UDB14_ST 0x4000646eu +#define CYREG_B0_UDB15_ST 0x4000646fu +#define CYREG_B0_UDB00_CTL 0x40006470u +#define CYREG_B0_UDB01_CTL 0x40006471u +#define CYREG_B0_UDB02_CTL 0x40006472u +#define CYREG_B0_UDB03_CTL 0x40006473u +#define CYREG_B0_UDB04_CTL 0x40006474u +#define CYREG_B0_UDB05_CTL 0x40006475u +#define CYREG_B0_UDB06_CTL 0x40006476u +#define CYREG_B0_UDB07_CTL 0x40006477u +#define CYREG_B0_UDB08_CTL 0x40006478u +#define CYREG_B0_UDB09_CTL 0x40006479u +#define CYREG_B0_UDB10_CTL 0x4000647au +#define CYREG_B0_UDB11_CTL 0x4000647bu +#define CYREG_B0_UDB12_CTL 0x4000647cu +#define CYREG_B0_UDB13_CTL 0x4000647du +#define CYREG_B0_UDB14_CTL 0x4000647eu +#define CYREG_B0_UDB15_CTL 0x4000647fu +#define CYREG_B0_UDB00_MSK 0x40006480u +#define CYREG_B0_UDB01_MSK 0x40006481u +#define CYREG_B0_UDB02_MSK 0x40006482u +#define CYREG_B0_UDB03_MSK 0x40006483u +#define CYREG_B0_UDB04_MSK 0x40006484u +#define CYREG_B0_UDB05_MSK 0x40006485u +#define CYREG_B0_UDB06_MSK 0x40006486u +#define CYREG_B0_UDB07_MSK 0x40006487u +#define CYREG_B0_UDB08_MSK 0x40006488u +#define CYREG_B0_UDB09_MSK 0x40006489u +#define CYREG_B0_UDB10_MSK 0x4000648au +#define CYREG_B0_UDB11_MSK 0x4000648bu +#define CYREG_B0_UDB12_MSK 0x4000648cu +#define CYREG_B0_UDB13_MSK 0x4000648du +#define CYREG_B0_UDB14_MSK 0x4000648eu +#define CYREG_B0_UDB15_MSK 0x4000648fu +#define CYREG_B0_UDB00_ACTL 0x40006490u +#define CYREG_B0_UDB01_ACTL 0x40006491u +#define CYREG_B0_UDB02_ACTL 0x40006492u +#define CYREG_B0_UDB03_ACTL 0x40006493u +#define CYREG_B0_UDB04_ACTL 0x40006494u +#define CYREG_B0_UDB05_ACTL 0x40006495u +#define CYREG_B0_UDB06_ACTL 0x40006496u +#define CYREG_B0_UDB07_ACTL 0x40006497u +#define CYREG_B0_UDB08_ACTL 0x40006498u +#define CYREG_B0_UDB09_ACTL 0x40006499u +#define CYREG_B0_UDB10_ACTL 0x4000649au +#define CYREG_B0_UDB11_ACTL 0x4000649bu +#define CYREG_B0_UDB12_ACTL 0x4000649cu +#define CYREG_B0_UDB13_ACTL 0x4000649du +#define CYREG_B0_UDB14_ACTL 0x4000649eu +#define CYREG_B0_UDB15_ACTL 0x4000649fu +#define CYREG_B0_UDB00_MC 0x400064a0u +#define CYREG_B0_UDB01_MC 0x400064a1u +#define CYREG_B0_UDB02_MC 0x400064a2u +#define CYREG_B0_UDB03_MC 0x400064a3u +#define CYREG_B0_UDB04_MC 0x400064a4u +#define CYREG_B0_UDB05_MC 0x400064a5u +#define CYREG_B0_UDB06_MC 0x400064a6u +#define CYREG_B0_UDB07_MC 0x400064a7u +#define CYREG_B0_UDB08_MC 0x400064a8u +#define CYREG_B0_UDB09_MC 0x400064a9u +#define CYREG_B0_UDB10_MC 0x400064aau +#define CYREG_B0_UDB11_MC 0x400064abu +#define CYREG_B0_UDB12_MC 0x400064acu +#define CYREG_B0_UDB13_MC 0x400064adu +#define CYREG_B0_UDB14_MC 0x400064aeu +#define CYREG_B0_UDB15_MC 0x400064afu +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500u +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0u +#define CYREG_B1_UDB04_A0 0x40006504u +#define CYREG_B1_UDB05_A0 0x40006505u +#define CYREG_B1_UDB06_A0 0x40006506u +#define CYREG_B1_UDB07_A0 0x40006507u +#define CYREG_B1_UDB08_A0 0x40006508u +#define CYREG_B1_UDB09_A0 0x40006509u +#define CYREG_B1_UDB10_A0 0x4000650au +#define CYREG_B1_UDB11_A0 0x4000650bu +#define CYREG_B1_UDB04_A1 0x40006514u +#define CYREG_B1_UDB05_A1 0x40006515u +#define CYREG_B1_UDB06_A1 0x40006516u +#define CYREG_B1_UDB07_A1 0x40006517u +#define CYREG_B1_UDB08_A1 0x40006518u +#define CYREG_B1_UDB09_A1 0x40006519u +#define CYREG_B1_UDB10_A1 0x4000651au +#define CYREG_B1_UDB11_A1 0x4000651bu +#define CYREG_B1_UDB04_D0 0x40006524u +#define CYREG_B1_UDB05_D0 0x40006525u +#define CYREG_B1_UDB06_D0 0x40006526u +#define CYREG_B1_UDB07_D0 0x40006527u +#define CYREG_B1_UDB08_D0 0x40006528u +#define CYREG_B1_UDB09_D0 0x40006529u +#define CYREG_B1_UDB10_D0 0x4000652au +#define CYREG_B1_UDB11_D0 0x4000652bu +#define CYREG_B1_UDB04_D1 0x40006534u +#define CYREG_B1_UDB05_D1 0x40006535u +#define CYREG_B1_UDB06_D1 0x40006536u +#define CYREG_B1_UDB07_D1 0x40006537u +#define CYREG_B1_UDB08_D1 0x40006538u +#define CYREG_B1_UDB09_D1 0x40006539u +#define CYREG_B1_UDB10_D1 0x4000653au +#define CYREG_B1_UDB11_D1 0x4000653bu +#define CYREG_B1_UDB04_F0 0x40006544u +#define CYREG_B1_UDB05_F0 0x40006545u +#define CYREG_B1_UDB06_F0 0x40006546u +#define CYREG_B1_UDB07_F0 0x40006547u +#define CYREG_B1_UDB08_F0 0x40006548u +#define CYREG_B1_UDB09_F0 0x40006549u +#define CYREG_B1_UDB10_F0 0x4000654au +#define CYREG_B1_UDB11_F0 0x4000654bu +#define CYREG_B1_UDB04_F1 0x40006554u +#define CYREG_B1_UDB05_F1 0x40006555u +#define CYREG_B1_UDB06_F1 0x40006556u +#define CYREG_B1_UDB07_F1 0x40006557u +#define CYREG_B1_UDB08_F1 0x40006558u +#define CYREG_B1_UDB09_F1 0x40006559u +#define CYREG_B1_UDB10_F1 0x4000655au +#define CYREG_B1_UDB11_F1 0x4000655bu +#define CYREG_B1_UDB04_ST 0x40006564u +#define CYREG_B1_UDB05_ST 0x40006565u +#define CYREG_B1_UDB06_ST 0x40006566u +#define CYREG_B1_UDB07_ST 0x40006567u +#define CYREG_B1_UDB08_ST 0x40006568u +#define CYREG_B1_UDB09_ST 0x40006569u +#define CYREG_B1_UDB10_ST 0x4000656au +#define CYREG_B1_UDB11_ST 0x4000656bu +#define CYREG_B1_UDB04_CTL 0x40006574u +#define CYREG_B1_UDB05_CTL 0x40006575u +#define CYREG_B1_UDB06_CTL 0x40006576u +#define CYREG_B1_UDB07_CTL 0x40006577u +#define CYREG_B1_UDB08_CTL 0x40006578u +#define CYREG_B1_UDB09_CTL 0x40006579u +#define CYREG_B1_UDB10_CTL 0x4000657au +#define CYREG_B1_UDB11_CTL 0x4000657bu +#define CYREG_B1_UDB04_MSK 0x40006584u +#define CYREG_B1_UDB05_MSK 0x40006585u +#define CYREG_B1_UDB06_MSK 0x40006586u +#define CYREG_B1_UDB07_MSK 0x40006587u +#define CYREG_B1_UDB08_MSK 0x40006588u +#define CYREG_B1_UDB09_MSK 0x40006589u +#define CYREG_B1_UDB10_MSK 0x4000658au +#define CYREG_B1_UDB11_MSK 0x4000658bu +#define CYREG_B1_UDB04_ACTL 0x40006594u +#define CYREG_B1_UDB05_ACTL 0x40006595u +#define CYREG_B1_UDB06_ACTL 0x40006596u +#define CYREG_B1_UDB07_ACTL 0x40006597u +#define CYREG_B1_UDB08_ACTL 0x40006598u +#define CYREG_B1_UDB09_ACTL 0x40006599u +#define CYREG_B1_UDB10_ACTL 0x4000659au +#define CYREG_B1_UDB11_ACTL 0x4000659bu +#define CYREG_B1_UDB04_MC 0x400065a4u +#define CYREG_B1_UDB05_MC 0x400065a5u +#define CYREG_B1_UDB06_MC 0x400065a6u +#define CYREG_B1_UDB07_MC 0x400065a7u +#define CYREG_B1_UDB08_MC 0x400065a8u +#define CYREG_B1_UDB09_MC 0x400065a9u +#define CYREG_B1_UDB10_MC 0x400065aau +#define CYREG_B1_UDB11_MC 0x400065abu +#define CYDEV_UWRK_UWRK16_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160u +#define CYREG_B0_UDB00_A0_A1 0x40006800u +#define CYREG_B0_UDB01_A0_A1 0x40006802u +#define CYREG_B0_UDB02_A0_A1 0x40006804u +#define CYREG_B0_UDB03_A0_A1 0x40006806u +#define CYREG_B0_UDB04_A0_A1 0x40006808u +#define CYREG_B0_UDB05_A0_A1 0x4000680au +#define CYREG_B0_UDB06_A0_A1 0x4000680cu +#define CYREG_B0_UDB07_A0_A1 0x4000680eu +#define CYREG_B0_UDB08_A0_A1 0x40006810u +#define CYREG_B0_UDB09_A0_A1 0x40006812u +#define CYREG_B0_UDB10_A0_A1 0x40006814u +#define CYREG_B0_UDB11_A0_A1 0x40006816u +#define CYREG_B0_UDB12_A0_A1 0x40006818u +#define CYREG_B0_UDB13_A0_A1 0x4000681au +#define CYREG_B0_UDB14_A0_A1 0x4000681cu +#define CYREG_B0_UDB15_A0_A1 0x4000681eu +#define CYREG_B0_UDB00_D0_D1 0x40006840u +#define CYREG_B0_UDB01_D0_D1 0x40006842u +#define CYREG_B0_UDB02_D0_D1 0x40006844u +#define CYREG_B0_UDB03_D0_D1 0x40006846u +#define CYREG_B0_UDB04_D0_D1 0x40006848u +#define CYREG_B0_UDB05_D0_D1 0x4000684au +#define CYREG_B0_UDB06_D0_D1 0x4000684cu +#define CYREG_B0_UDB07_D0_D1 0x4000684eu +#define CYREG_B0_UDB08_D0_D1 0x40006850u +#define CYREG_B0_UDB09_D0_D1 0x40006852u +#define CYREG_B0_UDB10_D0_D1 0x40006854u +#define CYREG_B0_UDB11_D0_D1 0x40006856u +#define CYREG_B0_UDB12_D0_D1 0x40006858u +#define CYREG_B0_UDB13_D0_D1 0x4000685au +#define CYREG_B0_UDB14_D0_D1 0x4000685cu +#define CYREG_B0_UDB15_D0_D1 0x4000685eu +#define CYREG_B0_UDB00_F0_F1 0x40006880u +#define CYREG_B0_UDB01_F0_F1 0x40006882u +#define CYREG_B0_UDB02_F0_F1 0x40006884u +#define CYREG_B0_UDB03_F0_F1 0x40006886u +#define CYREG_B0_UDB04_F0_F1 0x40006888u +#define CYREG_B0_UDB05_F0_F1 0x4000688au +#define CYREG_B0_UDB06_F0_F1 0x4000688cu +#define CYREG_B0_UDB07_F0_F1 0x4000688eu +#define CYREG_B0_UDB08_F0_F1 0x40006890u +#define CYREG_B0_UDB09_F0_F1 0x40006892u +#define CYREG_B0_UDB10_F0_F1 0x40006894u +#define CYREG_B0_UDB11_F0_F1 0x40006896u +#define CYREG_B0_UDB12_F0_F1 0x40006898u +#define CYREG_B0_UDB13_F0_F1 0x4000689au +#define CYREG_B0_UDB14_F0_F1 0x4000689cu +#define CYREG_B0_UDB15_F0_F1 0x4000689eu +#define CYREG_B0_UDB00_ST_CTL 0x400068c0u +#define CYREG_B0_UDB01_ST_CTL 0x400068c2u +#define CYREG_B0_UDB02_ST_CTL 0x400068c4u +#define CYREG_B0_UDB03_ST_CTL 0x400068c6u +#define CYREG_B0_UDB04_ST_CTL 0x400068c8u +#define CYREG_B0_UDB05_ST_CTL 0x400068cau +#define CYREG_B0_UDB06_ST_CTL 0x400068ccu +#define CYREG_B0_UDB07_ST_CTL 0x400068ceu +#define CYREG_B0_UDB08_ST_CTL 0x400068d0u +#define CYREG_B0_UDB09_ST_CTL 0x400068d2u +#define CYREG_B0_UDB10_ST_CTL 0x400068d4u +#define CYREG_B0_UDB11_ST_CTL 0x400068d6u +#define CYREG_B0_UDB12_ST_CTL 0x400068d8u +#define CYREG_B0_UDB13_ST_CTL 0x400068dau +#define CYREG_B0_UDB14_ST_CTL 0x400068dcu +#define CYREG_B0_UDB15_ST_CTL 0x400068deu +#define CYREG_B0_UDB00_MSK_ACTL 0x40006900u +#define CYREG_B0_UDB01_MSK_ACTL 0x40006902u +#define CYREG_B0_UDB02_MSK_ACTL 0x40006904u +#define CYREG_B0_UDB03_MSK_ACTL 0x40006906u +#define CYREG_B0_UDB04_MSK_ACTL 0x40006908u +#define CYREG_B0_UDB05_MSK_ACTL 0x4000690au +#define CYREG_B0_UDB06_MSK_ACTL 0x4000690cu +#define CYREG_B0_UDB07_MSK_ACTL 0x4000690eu +#define CYREG_B0_UDB08_MSK_ACTL 0x40006910u +#define CYREG_B0_UDB09_MSK_ACTL 0x40006912u +#define CYREG_B0_UDB10_MSK_ACTL 0x40006914u +#define CYREG_B0_UDB11_MSK_ACTL 0x40006916u +#define CYREG_B0_UDB12_MSK_ACTL 0x40006918u +#define CYREG_B0_UDB13_MSK_ACTL 0x4000691au +#define CYREG_B0_UDB14_MSK_ACTL 0x4000691cu +#define CYREG_B0_UDB15_MSK_ACTL 0x4000691eu +#define CYREG_B0_UDB00_MC_00 0x40006940u +#define CYREG_B0_UDB01_MC_00 0x40006942u +#define CYREG_B0_UDB02_MC_00 0x40006944u +#define CYREG_B0_UDB03_MC_00 0x40006946u +#define CYREG_B0_UDB04_MC_00 0x40006948u +#define CYREG_B0_UDB05_MC_00 0x4000694au +#define CYREG_B0_UDB06_MC_00 0x4000694cu +#define CYREG_B0_UDB07_MC_00 0x4000694eu +#define CYREG_B0_UDB08_MC_00 0x40006950u +#define CYREG_B0_UDB09_MC_00 0x40006952u +#define CYREG_B0_UDB10_MC_00 0x40006954u +#define CYREG_B0_UDB11_MC_00 0x40006956u +#define CYREG_B0_UDB12_MC_00 0x40006958u +#define CYREG_B0_UDB13_MC_00 0x4000695au +#define CYREG_B0_UDB14_MC_00 0x4000695cu +#define CYREG_B0_UDB15_MC_00 0x4000695eu +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160u +#define CYREG_B1_UDB04_A0_A1 0x40006a08u +#define CYREG_B1_UDB05_A0_A1 0x40006a0au +#define CYREG_B1_UDB06_A0_A1 0x40006a0cu +#define CYREG_B1_UDB07_A0_A1 0x40006a0eu +#define CYREG_B1_UDB08_A0_A1 0x40006a10u +#define CYREG_B1_UDB09_A0_A1 0x40006a12u +#define CYREG_B1_UDB10_A0_A1 0x40006a14u +#define CYREG_B1_UDB11_A0_A1 0x40006a16u +#define CYREG_B1_UDB04_D0_D1 0x40006a48u +#define CYREG_B1_UDB05_D0_D1 0x40006a4au +#define CYREG_B1_UDB06_D0_D1 0x40006a4cu +#define CYREG_B1_UDB07_D0_D1 0x40006a4eu +#define CYREG_B1_UDB08_D0_D1 0x40006a50u +#define CYREG_B1_UDB09_D0_D1 0x40006a52u +#define CYREG_B1_UDB10_D0_D1 0x40006a54u +#define CYREG_B1_UDB11_D0_D1 0x40006a56u +#define CYREG_B1_UDB04_F0_F1 0x40006a88u +#define CYREG_B1_UDB05_F0_F1 0x40006a8au +#define CYREG_B1_UDB06_F0_F1 0x40006a8cu +#define CYREG_B1_UDB07_F0_F1 0x40006a8eu +#define CYREG_B1_UDB08_F0_F1 0x40006a90u +#define CYREG_B1_UDB09_F0_F1 0x40006a92u +#define CYREG_B1_UDB10_F0_F1 0x40006a94u +#define CYREG_B1_UDB11_F0_F1 0x40006a96u +#define CYREG_B1_UDB04_ST_CTL 0x40006ac8u +#define CYREG_B1_UDB05_ST_CTL 0x40006acau +#define CYREG_B1_UDB06_ST_CTL 0x40006accu +#define CYREG_B1_UDB07_ST_CTL 0x40006aceu +#define CYREG_B1_UDB08_ST_CTL 0x40006ad0u +#define CYREG_B1_UDB09_ST_CTL 0x40006ad2u +#define CYREG_B1_UDB10_ST_CTL 0x40006ad4u +#define CYREG_B1_UDB11_ST_CTL 0x40006ad6u +#define CYREG_B1_UDB04_MSK_ACTL 0x40006b08u +#define CYREG_B1_UDB05_MSK_ACTL 0x40006b0au +#define CYREG_B1_UDB06_MSK_ACTL 0x40006b0cu +#define CYREG_B1_UDB07_MSK_ACTL 0x40006b0eu +#define CYREG_B1_UDB08_MSK_ACTL 0x40006b10u +#define CYREG_B1_UDB09_MSK_ACTL 0x40006b12u +#define CYREG_B1_UDB10_MSK_ACTL 0x40006b14u +#define CYREG_B1_UDB11_MSK_ACTL 0x40006b16u +#define CYREG_B1_UDB04_MC_00 0x40006b48u +#define CYREG_B1_UDB05_MC_00 0x40006b4au +#define CYREG_B1_UDB06_MC_00 0x40006b4cu +#define CYREG_B1_UDB07_MC_00 0x40006b4eu +#define CYREG_B1_UDB08_MC_00 0x40006b50u +#define CYREG_B1_UDB09_MC_00 0x40006b52u +#define CYREG_B1_UDB10_MC_00 0x40006b54u +#define CYREG_B1_UDB11_MC_00 0x40006b56u +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075eu +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015eu +#define CYREG_B0_UDB00_01_A0 0x40006800u +#define CYREG_B0_UDB01_02_A0 0x40006802u +#define CYREG_B0_UDB02_03_A0 0x40006804u +#define CYREG_B0_UDB03_04_A0 0x40006806u +#define CYREG_B0_UDB04_05_A0 0x40006808u +#define CYREG_B0_UDB05_06_A0 0x4000680au +#define CYREG_B0_UDB06_07_A0 0x4000680cu +#define CYREG_B0_UDB07_08_A0 0x4000680eu +#define CYREG_B0_UDB08_09_A0 0x40006810u +#define CYREG_B0_UDB09_10_A0 0x40006812u +#define CYREG_B0_UDB10_11_A0 0x40006814u +#define CYREG_B0_UDB11_12_A0 0x40006816u +#define CYREG_B0_UDB12_13_A0 0x40006818u +#define CYREG_B0_UDB13_14_A0 0x4000681au +#define CYREG_B0_UDB14_15_A0 0x4000681cu +#define CYREG_B0_UDB00_01_A1 0x40006820u +#define CYREG_B0_UDB01_02_A1 0x40006822u +#define CYREG_B0_UDB02_03_A1 0x40006824u +#define CYREG_B0_UDB03_04_A1 0x40006826u +#define CYREG_B0_UDB04_05_A1 0x40006828u +#define CYREG_B0_UDB05_06_A1 0x4000682au +#define CYREG_B0_UDB06_07_A1 0x4000682cu +#define CYREG_B0_UDB07_08_A1 0x4000682eu +#define CYREG_B0_UDB08_09_A1 0x40006830u +#define CYREG_B0_UDB09_10_A1 0x40006832u +#define CYREG_B0_UDB10_11_A1 0x40006834u +#define CYREG_B0_UDB11_12_A1 0x40006836u +#define CYREG_B0_UDB12_13_A1 0x40006838u +#define CYREG_B0_UDB13_14_A1 0x4000683au +#define CYREG_B0_UDB14_15_A1 0x4000683cu +#define CYREG_B0_UDB00_01_D0 0x40006840u +#define CYREG_B0_UDB01_02_D0 0x40006842u +#define CYREG_B0_UDB02_03_D0 0x40006844u +#define CYREG_B0_UDB03_04_D0 0x40006846u +#define CYREG_B0_UDB04_05_D0 0x40006848u +#define CYREG_B0_UDB05_06_D0 0x4000684au +#define CYREG_B0_UDB06_07_D0 0x4000684cu +#define CYREG_B0_UDB07_08_D0 0x4000684eu +#define CYREG_B0_UDB08_09_D0 0x40006850u +#define CYREG_B0_UDB09_10_D0 0x40006852u +#define CYREG_B0_UDB10_11_D0 0x40006854u +#define CYREG_B0_UDB11_12_D0 0x40006856u +#define CYREG_B0_UDB12_13_D0 0x40006858u +#define CYREG_B0_UDB13_14_D0 0x4000685au +#define CYREG_B0_UDB14_15_D0 0x4000685cu +#define CYREG_B0_UDB00_01_D1 0x40006860u +#define CYREG_B0_UDB01_02_D1 0x40006862u +#define CYREG_B0_UDB02_03_D1 0x40006864u +#define CYREG_B0_UDB03_04_D1 0x40006866u +#define CYREG_B0_UDB04_05_D1 0x40006868u +#define CYREG_B0_UDB05_06_D1 0x4000686au +#define CYREG_B0_UDB06_07_D1 0x4000686cu +#define CYREG_B0_UDB07_08_D1 0x4000686eu +#define CYREG_B0_UDB08_09_D1 0x40006870u +#define CYREG_B0_UDB09_10_D1 0x40006872u +#define CYREG_B0_UDB10_11_D1 0x40006874u +#define CYREG_B0_UDB11_12_D1 0x40006876u +#define CYREG_B0_UDB12_13_D1 0x40006878u +#define CYREG_B0_UDB13_14_D1 0x4000687au +#define CYREG_B0_UDB14_15_D1 0x4000687cu +#define CYREG_B0_UDB00_01_F0 0x40006880u +#define CYREG_B0_UDB01_02_F0 0x40006882u +#define CYREG_B0_UDB02_03_F0 0x40006884u +#define CYREG_B0_UDB03_04_F0 0x40006886u +#define CYREG_B0_UDB04_05_F0 0x40006888u +#define CYREG_B0_UDB05_06_F0 0x4000688au +#define CYREG_B0_UDB06_07_F0 0x4000688cu +#define CYREG_B0_UDB07_08_F0 0x4000688eu +#define CYREG_B0_UDB08_09_F0 0x40006890u +#define CYREG_B0_UDB09_10_F0 0x40006892u +#define CYREG_B0_UDB10_11_F0 0x40006894u +#define CYREG_B0_UDB11_12_F0 0x40006896u +#define CYREG_B0_UDB12_13_F0 0x40006898u +#define CYREG_B0_UDB13_14_F0 0x4000689au +#define CYREG_B0_UDB14_15_F0 0x4000689cu +#define CYREG_B0_UDB00_01_F1 0x400068a0u +#define CYREG_B0_UDB01_02_F1 0x400068a2u +#define CYREG_B0_UDB02_03_F1 0x400068a4u +#define CYREG_B0_UDB03_04_F1 0x400068a6u +#define CYREG_B0_UDB04_05_F1 0x400068a8u +#define CYREG_B0_UDB05_06_F1 0x400068aau +#define CYREG_B0_UDB06_07_F1 0x400068acu +#define CYREG_B0_UDB07_08_F1 0x400068aeu +#define CYREG_B0_UDB08_09_F1 0x400068b0u +#define CYREG_B0_UDB09_10_F1 0x400068b2u +#define CYREG_B0_UDB10_11_F1 0x400068b4u +#define CYREG_B0_UDB11_12_F1 0x400068b6u +#define CYREG_B0_UDB12_13_F1 0x400068b8u +#define CYREG_B0_UDB13_14_F1 0x400068bau +#define CYREG_B0_UDB14_15_F1 0x400068bcu +#define CYREG_B0_UDB00_01_ST 0x400068c0u +#define CYREG_B0_UDB01_02_ST 0x400068c2u +#define CYREG_B0_UDB02_03_ST 0x400068c4u +#define CYREG_B0_UDB03_04_ST 0x400068c6u +#define CYREG_B0_UDB04_05_ST 0x400068c8u +#define CYREG_B0_UDB05_06_ST 0x400068cau +#define CYREG_B0_UDB06_07_ST 0x400068ccu +#define CYREG_B0_UDB07_08_ST 0x400068ceu +#define CYREG_B0_UDB08_09_ST 0x400068d0u +#define CYREG_B0_UDB09_10_ST 0x400068d2u +#define CYREG_B0_UDB10_11_ST 0x400068d4u +#define CYREG_B0_UDB11_12_ST 0x400068d6u +#define CYREG_B0_UDB12_13_ST 0x400068d8u +#define CYREG_B0_UDB13_14_ST 0x400068dau +#define CYREG_B0_UDB14_15_ST 0x400068dcu +#define CYREG_B0_UDB00_01_CTL 0x400068e0u +#define CYREG_B0_UDB01_02_CTL 0x400068e2u +#define CYREG_B0_UDB02_03_CTL 0x400068e4u +#define CYREG_B0_UDB03_04_CTL 0x400068e6u +#define CYREG_B0_UDB04_05_CTL 0x400068e8u +#define CYREG_B0_UDB05_06_CTL 0x400068eau +#define CYREG_B0_UDB06_07_CTL 0x400068ecu +#define CYREG_B0_UDB07_08_CTL 0x400068eeu +#define CYREG_B0_UDB08_09_CTL 0x400068f0u +#define CYREG_B0_UDB09_10_CTL 0x400068f2u +#define CYREG_B0_UDB10_11_CTL 0x400068f4u +#define CYREG_B0_UDB11_12_CTL 0x400068f6u +#define CYREG_B0_UDB12_13_CTL 0x400068f8u +#define CYREG_B0_UDB13_14_CTL 0x400068fau +#define CYREG_B0_UDB14_15_CTL 0x400068fcu +#define CYREG_B0_UDB00_01_MSK 0x40006900u +#define CYREG_B0_UDB01_02_MSK 0x40006902u +#define CYREG_B0_UDB02_03_MSK 0x40006904u +#define CYREG_B0_UDB03_04_MSK 0x40006906u +#define CYREG_B0_UDB04_05_MSK 0x40006908u +#define CYREG_B0_UDB05_06_MSK 0x4000690au +#define CYREG_B0_UDB06_07_MSK 0x4000690cu +#define CYREG_B0_UDB07_08_MSK 0x4000690eu +#define CYREG_B0_UDB08_09_MSK 0x40006910u +#define CYREG_B0_UDB09_10_MSK 0x40006912u +#define CYREG_B0_UDB10_11_MSK 0x40006914u +#define CYREG_B0_UDB11_12_MSK 0x40006916u +#define CYREG_B0_UDB12_13_MSK 0x40006918u +#define CYREG_B0_UDB13_14_MSK 0x4000691au +#define CYREG_B0_UDB14_15_MSK 0x4000691cu +#define CYREG_B0_UDB00_01_ACTL 0x40006920u +#define CYREG_B0_UDB01_02_ACTL 0x40006922u +#define CYREG_B0_UDB02_03_ACTL 0x40006924u +#define CYREG_B0_UDB03_04_ACTL 0x40006926u +#define CYREG_B0_UDB04_05_ACTL 0x40006928u +#define CYREG_B0_UDB05_06_ACTL 0x4000692au +#define CYREG_B0_UDB06_07_ACTL 0x4000692cu +#define CYREG_B0_UDB07_08_ACTL 0x4000692eu +#define CYREG_B0_UDB08_09_ACTL 0x40006930u +#define CYREG_B0_UDB09_10_ACTL 0x40006932u +#define CYREG_B0_UDB10_11_ACTL 0x40006934u +#define CYREG_B0_UDB11_12_ACTL 0x40006936u +#define CYREG_B0_UDB12_13_ACTL 0x40006938u +#define CYREG_B0_UDB13_14_ACTL 0x4000693au +#define CYREG_B0_UDB14_15_ACTL 0x4000693cu +#define CYREG_B0_UDB00_01_MC 0x40006940u +#define CYREG_B0_UDB01_02_MC 0x40006942u +#define CYREG_B0_UDB02_03_MC 0x40006944u +#define CYREG_B0_UDB03_04_MC 0x40006946u +#define CYREG_B0_UDB04_05_MC 0x40006948u +#define CYREG_B0_UDB05_06_MC 0x4000694au +#define CYREG_B0_UDB06_07_MC 0x4000694cu +#define CYREG_B0_UDB07_08_MC 0x4000694eu +#define CYREG_B0_UDB08_09_MC 0x40006950u +#define CYREG_B0_UDB09_10_MC 0x40006952u +#define CYREG_B0_UDB10_11_MC 0x40006954u +#define CYREG_B0_UDB11_12_MC 0x40006956u +#define CYREG_B0_UDB12_13_MC 0x40006958u +#define CYREG_B0_UDB13_14_MC 0x4000695au +#define CYREG_B0_UDB14_15_MC 0x4000695cu +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015eu +#define CYREG_B1_UDB04_05_A0 0x40006a08u +#define CYREG_B1_UDB05_06_A0 0x40006a0au +#define CYREG_B1_UDB06_07_A0 0x40006a0cu +#define CYREG_B1_UDB07_08_A0 0x40006a0eu +#define CYREG_B1_UDB08_09_A0 0x40006a10u +#define CYREG_B1_UDB09_10_A0 0x40006a12u +#define CYREG_B1_UDB10_11_A0 0x40006a14u +#define CYREG_B1_UDB11_12_A0 0x40006a16u +#define CYREG_B1_UDB04_05_A1 0x40006a28u +#define CYREG_B1_UDB05_06_A1 0x40006a2au +#define CYREG_B1_UDB06_07_A1 0x40006a2cu +#define CYREG_B1_UDB07_08_A1 0x40006a2eu +#define CYREG_B1_UDB08_09_A1 0x40006a30u +#define CYREG_B1_UDB09_10_A1 0x40006a32u +#define CYREG_B1_UDB10_11_A1 0x40006a34u +#define CYREG_B1_UDB11_12_A1 0x40006a36u +#define CYREG_B1_UDB04_05_D0 0x40006a48u +#define CYREG_B1_UDB05_06_D0 0x40006a4au +#define CYREG_B1_UDB06_07_D0 0x40006a4cu +#define CYREG_B1_UDB07_08_D0 0x40006a4eu +#define CYREG_B1_UDB08_09_D0 0x40006a50u +#define CYREG_B1_UDB09_10_D0 0x40006a52u +#define CYREG_B1_UDB10_11_D0 0x40006a54u +#define CYREG_B1_UDB11_12_D0 0x40006a56u +#define CYREG_B1_UDB04_05_D1 0x40006a68u +#define CYREG_B1_UDB05_06_D1 0x40006a6au +#define CYREG_B1_UDB06_07_D1 0x40006a6cu +#define CYREG_B1_UDB07_08_D1 0x40006a6eu +#define CYREG_B1_UDB08_09_D1 0x40006a70u +#define CYREG_B1_UDB09_10_D1 0x40006a72u +#define CYREG_B1_UDB10_11_D1 0x40006a74u +#define CYREG_B1_UDB11_12_D1 0x40006a76u +#define CYREG_B1_UDB04_05_F0 0x40006a88u +#define CYREG_B1_UDB05_06_F0 0x40006a8au +#define CYREG_B1_UDB06_07_F0 0x40006a8cu +#define CYREG_B1_UDB07_08_F0 0x40006a8eu +#define CYREG_B1_UDB08_09_F0 0x40006a90u +#define CYREG_B1_UDB09_10_F0 0x40006a92u +#define CYREG_B1_UDB10_11_F0 0x40006a94u +#define CYREG_B1_UDB11_12_F0 0x40006a96u +#define CYREG_B1_UDB04_05_F1 0x40006aa8u +#define CYREG_B1_UDB05_06_F1 0x40006aaau +#define CYREG_B1_UDB06_07_F1 0x40006aacu +#define CYREG_B1_UDB07_08_F1 0x40006aaeu +#define CYREG_B1_UDB08_09_F1 0x40006ab0u +#define CYREG_B1_UDB09_10_F1 0x40006ab2u +#define CYREG_B1_UDB10_11_F1 0x40006ab4u +#define CYREG_B1_UDB11_12_F1 0x40006ab6u +#define CYREG_B1_UDB04_05_ST 0x40006ac8u +#define CYREG_B1_UDB05_06_ST 0x40006acau +#define CYREG_B1_UDB06_07_ST 0x40006accu +#define CYREG_B1_UDB07_08_ST 0x40006aceu +#define CYREG_B1_UDB08_09_ST 0x40006ad0u +#define CYREG_B1_UDB09_10_ST 0x40006ad2u +#define CYREG_B1_UDB10_11_ST 0x40006ad4u +#define CYREG_B1_UDB11_12_ST 0x40006ad6u +#define CYREG_B1_UDB04_05_CTL 0x40006ae8u +#define CYREG_B1_UDB05_06_CTL 0x40006aeau +#define CYREG_B1_UDB06_07_CTL 0x40006aecu +#define CYREG_B1_UDB07_08_CTL 0x40006aeeu +#define CYREG_B1_UDB08_09_CTL 0x40006af0u +#define CYREG_B1_UDB09_10_CTL 0x40006af2u +#define CYREG_B1_UDB10_11_CTL 0x40006af4u +#define CYREG_B1_UDB11_12_CTL 0x40006af6u +#define CYREG_B1_UDB04_05_MSK 0x40006b08u +#define CYREG_B1_UDB05_06_MSK 0x40006b0au +#define CYREG_B1_UDB06_07_MSK 0x40006b0cu +#define CYREG_B1_UDB07_08_MSK 0x40006b0eu +#define CYREG_B1_UDB08_09_MSK 0x40006b10u +#define CYREG_B1_UDB09_10_MSK 0x40006b12u +#define CYREG_B1_UDB10_11_MSK 0x40006b14u +#define CYREG_B1_UDB11_12_MSK 0x40006b16u +#define CYREG_B1_UDB04_05_ACTL 0x40006b28u +#define CYREG_B1_UDB05_06_ACTL 0x40006b2au +#define CYREG_B1_UDB06_07_ACTL 0x40006b2cu +#define CYREG_B1_UDB07_08_ACTL 0x40006b2eu +#define CYREG_B1_UDB08_09_ACTL 0x40006b30u +#define CYREG_B1_UDB09_10_ACTL 0x40006b32u +#define CYREG_B1_UDB10_11_ACTL 0x40006b34u +#define CYREG_B1_UDB11_12_ACTL 0x40006b36u +#define CYREG_B1_UDB04_05_MC 0x40006b48u +#define CYREG_B1_UDB05_06_MC 0x40006b4au +#define CYREG_B1_UDB06_07_MC 0x40006b4cu +#define CYREG_B1_UDB07_08_MC 0x40006b4eu +#define CYREG_B1_UDB08_09_MC 0x40006b50u +#define CYREG_B1_UDB09_10_MC 0x40006b52u +#define CYREG_B1_UDB10_11_MC 0x40006b54u +#define CYREG_B1_UDB11_12_MC 0x40006b56u +#define CYDEV_PHUB_BASE 0x40007000u +#define CYDEV_PHUB_SIZE 0x00000c00u +#define CYREG_PHUB_CFG 0x40007000u +#define CYREG_PHUB_ERR 0x40007004u +#define CYREG_PHUB_ERR_ADR 0x40007008u +#define CYDEV_PHUB_CH0_BASE 0x40007010u +#define CYDEV_PHUB_CH0_SIZE 0x0000000cu +#define CYREG_PHUB_CH0_BASIC_CFG 0x40007010u +#define CYREG_PHUB_CH0_ACTION 0x40007014u +#define CYREG_PHUB_CH0_BASIC_STATUS 0x40007018u +#define CYDEV_PHUB_CH1_BASE 0x40007020u +#define CYDEV_PHUB_CH1_SIZE 0x0000000cu +#define CYREG_PHUB_CH1_BASIC_CFG 0x40007020u +#define CYREG_PHUB_CH1_ACTION 0x40007024u +#define CYREG_PHUB_CH1_BASIC_STATUS 0x40007028u +#define CYDEV_PHUB_CH2_BASE 0x40007030u +#define CYDEV_PHUB_CH2_SIZE 0x0000000cu +#define CYREG_PHUB_CH2_BASIC_CFG 0x40007030u +#define CYREG_PHUB_CH2_ACTION 0x40007034u +#define CYREG_PHUB_CH2_BASIC_STATUS 0x40007038u +#define CYDEV_PHUB_CH3_BASE 0x40007040u +#define CYDEV_PHUB_CH3_SIZE 0x0000000cu +#define CYREG_PHUB_CH3_BASIC_CFG 0x40007040u +#define CYREG_PHUB_CH3_ACTION 0x40007044u +#define CYREG_PHUB_CH3_BASIC_STATUS 0x40007048u +#define CYDEV_PHUB_CH4_BASE 0x40007050u +#define CYDEV_PHUB_CH4_SIZE 0x0000000cu +#define CYREG_PHUB_CH4_BASIC_CFG 0x40007050u +#define CYREG_PHUB_CH4_ACTION 0x40007054u +#define CYREG_PHUB_CH4_BASIC_STATUS 0x40007058u +#define CYDEV_PHUB_CH5_BASE 0x40007060u +#define CYDEV_PHUB_CH5_SIZE 0x0000000cu +#define CYREG_PHUB_CH5_BASIC_CFG 0x40007060u +#define CYREG_PHUB_CH5_ACTION 0x40007064u +#define CYREG_PHUB_CH5_BASIC_STATUS 0x40007068u +#define CYDEV_PHUB_CH6_BASE 0x40007070u +#define CYDEV_PHUB_CH6_SIZE 0x0000000cu +#define CYREG_PHUB_CH6_BASIC_CFG 0x40007070u +#define CYREG_PHUB_CH6_ACTION 0x40007074u +#define CYREG_PHUB_CH6_BASIC_STATUS 0x40007078u +#define CYDEV_PHUB_CH7_BASE 0x40007080u +#define CYDEV_PHUB_CH7_SIZE 0x0000000cu +#define CYREG_PHUB_CH7_BASIC_CFG 0x40007080u +#define CYREG_PHUB_CH7_ACTION 0x40007084u +#define CYREG_PHUB_CH7_BASIC_STATUS 0x40007088u +#define CYDEV_PHUB_CH8_BASE 0x40007090u +#define CYDEV_PHUB_CH8_SIZE 0x0000000cu +#define CYREG_PHUB_CH8_BASIC_CFG 0x40007090u +#define CYREG_PHUB_CH8_ACTION 0x40007094u +#define CYREG_PHUB_CH8_BASIC_STATUS 0x40007098u +#define CYDEV_PHUB_CH9_BASE 0x400070a0u +#define CYDEV_PHUB_CH9_SIZE 0x0000000cu +#define CYREG_PHUB_CH9_BASIC_CFG 0x400070a0u +#define CYREG_PHUB_CH9_ACTION 0x400070a4u +#define CYREG_PHUB_CH9_BASIC_STATUS 0x400070a8u +#define CYDEV_PHUB_CH10_BASE 0x400070b0u +#define CYDEV_PHUB_CH10_SIZE 0x0000000cu +#define CYREG_PHUB_CH10_BASIC_CFG 0x400070b0u +#define CYREG_PHUB_CH10_ACTION 0x400070b4u +#define CYREG_PHUB_CH10_BASIC_STATUS 0x400070b8u +#define CYDEV_PHUB_CH11_BASE 0x400070c0u +#define CYDEV_PHUB_CH11_SIZE 0x0000000cu +#define CYREG_PHUB_CH11_BASIC_CFG 0x400070c0u +#define CYREG_PHUB_CH11_ACTION 0x400070c4u +#define CYREG_PHUB_CH11_BASIC_STATUS 0x400070c8u +#define CYDEV_PHUB_CH12_BASE 0x400070d0u +#define CYDEV_PHUB_CH12_SIZE 0x0000000cu +#define CYREG_PHUB_CH12_BASIC_CFG 0x400070d0u +#define CYREG_PHUB_CH12_ACTION 0x400070d4u +#define CYREG_PHUB_CH12_BASIC_STATUS 0x400070d8u +#define CYDEV_PHUB_CH13_BASE 0x400070e0u +#define CYDEV_PHUB_CH13_SIZE 0x0000000cu +#define CYREG_PHUB_CH13_BASIC_CFG 0x400070e0u +#define CYREG_PHUB_CH13_ACTION 0x400070e4u +#define CYREG_PHUB_CH13_BASIC_STATUS 0x400070e8u +#define CYDEV_PHUB_CH14_BASE 0x400070f0u +#define CYDEV_PHUB_CH14_SIZE 0x0000000cu +#define CYREG_PHUB_CH14_BASIC_CFG 0x400070f0u +#define CYREG_PHUB_CH14_ACTION 0x400070f4u +#define CYREG_PHUB_CH14_BASIC_STATUS 0x400070f8u +#define CYDEV_PHUB_CH15_BASE 0x40007100u +#define CYDEV_PHUB_CH15_SIZE 0x0000000cu +#define CYREG_PHUB_CH15_BASIC_CFG 0x40007100u +#define CYREG_PHUB_CH15_ACTION 0x40007104u +#define CYREG_PHUB_CH15_BASIC_STATUS 0x40007108u +#define CYDEV_PHUB_CH16_BASE 0x40007110u +#define CYDEV_PHUB_CH16_SIZE 0x0000000cu +#define CYREG_PHUB_CH16_BASIC_CFG 0x40007110u +#define CYREG_PHUB_CH16_ACTION 0x40007114u +#define CYREG_PHUB_CH16_BASIC_STATUS 0x40007118u +#define CYDEV_PHUB_CH17_BASE 0x40007120u +#define CYDEV_PHUB_CH17_SIZE 0x0000000cu +#define CYREG_PHUB_CH17_BASIC_CFG 0x40007120u +#define CYREG_PHUB_CH17_ACTION 0x40007124u +#define CYREG_PHUB_CH17_BASIC_STATUS 0x40007128u +#define CYDEV_PHUB_CH18_BASE 0x40007130u +#define CYDEV_PHUB_CH18_SIZE 0x0000000cu +#define CYREG_PHUB_CH18_BASIC_CFG 0x40007130u +#define CYREG_PHUB_CH18_ACTION 0x40007134u +#define CYREG_PHUB_CH18_BASIC_STATUS 0x40007138u +#define CYDEV_PHUB_CH19_BASE 0x40007140u +#define CYDEV_PHUB_CH19_SIZE 0x0000000cu +#define CYREG_PHUB_CH19_BASIC_CFG 0x40007140u +#define CYREG_PHUB_CH19_ACTION 0x40007144u +#define CYREG_PHUB_CH19_BASIC_STATUS 0x40007148u +#define CYDEV_PHUB_CH20_BASE 0x40007150u +#define CYDEV_PHUB_CH20_SIZE 0x0000000cu +#define CYREG_PHUB_CH20_BASIC_CFG 0x40007150u +#define CYREG_PHUB_CH20_ACTION 0x40007154u +#define CYREG_PHUB_CH20_BASIC_STATUS 0x40007158u +#define CYDEV_PHUB_CH21_BASE 0x40007160u +#define CYDEV_PHUB_CH21_SIZE 0x0000000cu +#define CYREG_PHUB_CH21_BASIC_CFG 0x40007160u +#define CYREG_PHUB_CH21_ACTION 0x40007164u +#define CYREG_PHUB_CH21_BASIC_STATUS 0x40007168u +#define CYDEV_PHUB_CH22_BASE 0x40007170u +#define CYDEV_PHUB_CH22_SIZE 0x0000000cu +#define CYREG_PHUB_CH22_BASIC_CFG 0x40007170u +#define CYREG_PHUB_CH22_ACTION 0x40007174u +#define CYREG_PHUB_CH22_BASIC_STATUS 0x40007178u +#define CYDEV_PHUB_CH23_BASE 0x40007180u +#define CYDEV_PHUB_CH23_SIZE 0x0000000cu +#define CYREG_PHUB_CH23_BASIC_CFG 0x40007180u +#define CYREG_PHUB_CH23_ACTION 0x40007184u +#define CYREG_PHUB_CH23_BASIC_STATUS 0x40007188u +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600u +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM0_CFG0 0x40007600u +#define CYREG_PHUB_CFGMEM0_CFG1 0x40007604u +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608u +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM1_CFG0 0x40007608u +#define CYREG_PHUB_CFGMEM1_CFG1 0x4000760cu +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610u +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM2_CFG0 0x40007610u +#define CYREG_PHUB_CFGMEM2_CFG1 0x40007614u +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618u +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM3_CFG0 0x40007618u +#define CYREG_PHUB_CFGMEM3_CFG1 0x4000761cu +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620u +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM4_CFG0 0x40007620u +#define CYREG_PHUB_CFGMEM4_CFG1 0x40007624u +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628u +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM5_CFG0 0x40007628u +#define CYREG_PHUB_CFGMEM5_CFG1 0x4000762cu +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630u +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM6_CFG0 0x40007630u +#define CYREG_PHUB_CFGMEM6_CFG1 0x40007634u +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638u +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM7_CFG0 0x40007638u +#define CYREG_PHUB_CFGMEM7_CFG1 0x4000763cu +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640u +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM8_CFG0 0x40007640u +#define CYREG_PHUB_CFGMEM8_CFG1 0x40007644u +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648u +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM9_CFG0 0x40007648u +#define CYREG_PHUB_CFGMEM9_CFG1 0x4000764cu +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650u +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM10_CFG0 0x40007650u +#define CYREG_PHUB_CFGMEM10_CFG1 0x40007654u +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658u +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM11_CFG0 0x40007658u +#define CYREG_PHUB_CFGMEM11_CFG1 0x4000765cu +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660u +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM12_CFG0 0x40007660u +#define CYREG_PHUB_CFGMEM12_CFG1 0x40007664u +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668u +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM13_CFG0 0x40007668u +#define CYREG_PHUB_CFGMEM13_CFG1 0x4000766cu +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670u +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM14_CFG0 0x40007670u +#define CYREG_PHUB_CFGMEM14_CFG1 0x40007674u +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678u +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM15_CFG0 0x40007678u +#define CYREG_PHUB_CFGMEM15_CFG1 0x4000767cu +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680u +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM16_CFG0 0x40007680u +#define CYREG_PHUB_CFGMEM16_CFG1 0x40007684u +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688u +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM17_CFG0 0x40007688u +#define CYREG_PHUB_CFGMEM17_CFG1 0x4000768cu +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690u +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM18_CFG0 0x40007690u +#define CYREG_PHUB_CFGMEM18_CFG1 0x40007694u +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698u +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM19_CFG0 0x40007698u +#define CYREG_PHUB_CFGMEM19_CFG1 0x4000769cu +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0u +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM20_CFG0 0x400076a0u +#define CYREG_PHUB_CFGMEM20_CFG1 0x400076a4u +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8u +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM21_CFG0 0x400076a8u +#define CYREG_PHUB_CFGMEM21_CFG1 0x400076acu +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0u +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM22_CFG0 0x400076b0u +#define CYREG_PHUB_CFGMEM22_CFG1 0x400076b4u +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8u +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM23_CFG0 0x400076b8u +#define CYREG_PHUB_CFGMEM23_CFG1 0x400076bcu +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800u +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM0_ORIG_TD0 0x40007800u +#define CYREG_PHUB_TDMEM0_ORIG_TD1 0x40007804u +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808u +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM1_ORIG_TD0 0x40007808u +#define CYREG_PHUB_TDMEM1_ORIG_TD1 0x4000780cu +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810u +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM2_ORIG_TD0 0x40007810u +#define CYREG_PHUB_TDMEM2_ORIG_TD1 0x40007814u +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818u +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM3_ORIG_TD0 0x40007818u +#define CYREG_PHUB_TDMEM3_ORIG_TD1 0x4000781cu +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820u +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM4_ORIG_TD0 0x40007820u +#define CYREG_PHUB_TDMEM4_ORIG_TD1 0x40007824u +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828u +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM5_ORIG_TD0 0x40007828u +#define CYREG_PHUB_TDMEM5_ORIG_TD1 0x4000782cu +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830u +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM6_ORIG_TD0 0x40007830u +#define CYREG_PHUB_TDMEM6_ORIG_TD1 0x40007834u +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838u +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM7_ORIG_TD0 0x40007838u +#define CYREG_PHUB_TDMEM7_ORIG_TD1 0x4000783cu +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840u +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM8_ORIG_TD0 0x40007840u +#define CYREG_PHUB_TDMEM8_ORIG_TD1 0x40007844u +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848u +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM9_ORIG_TD0 0x40007848u +#define CYREG_PHUB_TDMEM9_ORIG_TD1 0x4000784cu +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850u +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM10_ORIG_TD0 0x40007850u +#define CYREG_PHUB_TDMEM10_ORIG_TD1 0x40007854u +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858u +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM11_ORIG_TD0 0x40007858u +#define CYREG_PHUB_TDMEM11_ORIG_TD1 0x4000785cu +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860u +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM12_ORIG_TD0 0x40007860u +#define CYREG_PHUB_TDMEM12_ORIG_TD1 0x40007864u +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868u +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM13_ORIG_TD0 0x40007868u +#define CYREG_PHUB_TDMEM13_ORIG_TD1 0x4000786cu +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870u +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM14_ORIG_TD0 0x40007870u +#define CYREG_PHUB_TDMEM14_ORIG_TD1 0x40007874u +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878u +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM15_ORIG_TD0 0x40007878u +#define CYREG_PHUB_TDMEM15_ORIG_TD1 0x4000787cu +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880u +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM16_ORIG_TD0 0x40007880u +#define CYREG_PHUB_TDMEM16_ORIG_TD1 0x40007884u +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888u +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM17_ORIG_TD0 0x40007888u +#define CYREG_PHUB_TDMEM17_ORIG_TD1 0x4000788cu +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890u +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM18_ORIG_TD0 0x40007890u +#define CYREG_PHUB_TDMEM18_ORIG_TD1 0x40007894u +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898u +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM19_ORIG_TD0 0x40007898u +#define CYREG_PHUB_TDMEM19_ORIG_TD1 0x4000789cu +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0u +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM20_ORIG_TD0 0x400078a0u +#define CYREG_PHUB_TDMEM20_ORIG_TD1 0x400078a4u +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8u +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM21_ORIG_TD0 0x400078a8u +#define CYREG_PHUB_TDMEM21_ORIG_TD1 0x400078acu +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0u +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM22_ORIG_TD0 0x400078b0u +#define CYREG_PHUB_TDMEM22_ORIG_TD1 0x400078b4u +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8u +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM23_ORIG_TD0 0x400078b8u +#define CYREG_PHUB_TDMEM23_ORIG_TD1 0x400078bcu +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0u +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM24_ORIG_TD0 0x400078c0u +#define CYREG_PHUB_TDMEM24_ORIG_TD1 0x400078c4u +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8u +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM25_ORIG_TD0 0x400078c8u +#define CYREG_PHUB_TDMEM25_ORIG_TD1 0x400078ccu +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0u +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM26_ORIG_TD0 0x400078d0u +#define CYREG_PHUB_TDMEM26_ORIG_TD1 0x400078d4u +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8u +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM27_ORIG_TD0 0x400078d8u +#define CYREG_PHUB_TDMEM27_ORIG_TD1 0x400078dcu +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0u +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM28_ORIG_TD0 0x400078e0u +#define CYREG_PHUB_TDMEM28_ORIG_TD1 0x400078e4u +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8u +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM29_ORIG_TD0 0x400078e8u +#define CYREG_PHUB_TDMEM29_ORIG_TD1 0x400078ecu +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0u +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM30_ORIG_TD0 0x400078f0u +#define CYREG_PHUB_TDMEM30_ORIG_TD1 0x400078f4u +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8u +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM31_ORIG_TD0 0x400078f8u +#define CYREG_PHUB_TDMEM31_ORIG_TD1 0x400078fcu +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900u +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM32_ORIG_TD0 0x40007900u +#define CYREG_PHUB_TDMEM32_ORIG_TD1 0x40007904u +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908u +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM33_ORIG_TD0 0x40007908u +#define CYREG_PHUB_TDMEM33_ORIG_TD1 0x4000790cu +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910u +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM34_ORIG_TD0 0x40007910u +#define CYREG_PHUB_TDMEM34_ORIG_TD1 0x40007914u +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918u +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM35_ORIG_TD0 0x40007918u +#define CYREG_PHUB_TDMEM35_ORIG_TD1 0x4000791cu +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920u +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM36_ORIG_TD0 0x40007920u +#define CYREG_PHUB_TDMEM36_ORIG_TD1 0x40007924u +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928u +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM37_ORIG_TD0 0x40007928u +#define CYREG_PHUB_TDMEM37_ORIG_TD1 0x4000792cu +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930u +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM38_ORIG_TD0 0x40007930u +#define CYREG_PHUB_TDMEM38_ORIG_TD1 0x40007934u +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938u +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM39_ORIG_TD0 0x40007938u +#define CYREG_PHUB_TDMEM39_ORIG_TD1 0x4000793cu +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940u +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM40_ORIG_TD0 0x40007940u +#define CYREG_PHUB_TDMEM40_ORIG_TD1 0x40007944u +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948u +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM41_ORIG_TD0 0x40007948u +#define CYREG_PHUB_TDMEM41_ORIG_TD1 0x4000794cu +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950u +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM42_ORIG_TD0 0x40007950u +#define CYREG_PHUB_TDMEM42_ORIG_TD1 0x40007954u +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958u +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM43_ORIG_TD0 0x40007958u +#define CYREG_PHUB_TDMEM43_ORIG_TD1 0x4000795cu +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960u +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM44_ORIG_TD0 0x40007960u +#define CYREG_PHUB_TDMEM44_ORIG_TD1 0x40007964u +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968u +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM45_ORIG_TD0 0x40007968u +#define CYREG_PHUB_TDMEM45_ORIG_TD1 0x4000796cu +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970u +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM46_ORIG_TD0 0x40007970u +#define CYREG_PHUB_TDMEM46_ORIG_TD1 0x40007974u +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978u +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM47_ORIG_TD0 0x40007978u +#define CYREG_PHUB_TDMEM47_ORIG_TD1 0x4000797cu +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980u +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM48_ORIG_TD0 0x40007980u +#define CYREG_PHUB_TDMEM48_ORIG_TD1 0x40007984u +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988u +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM49_ORIG_TD0 0x40007988u +#define CYREG_PHUB_TDMEM49_ORIG_TD1 0x4000798cu +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990u +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM50_ORIG_TD0 0x40007990u +#define CYREG_PHUB_TDMEM50_ORIG_TD1 0x40007994u +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998u +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM51_ORIG_TD0 0x40007998u +#define CYREG_PHUB_TDMEM51_ORIG_TD1 0x4000799cu +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0u +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM52_ORIG_TD0 0x400079a0u +#define CYREG_PHUB_TDMEM52_ORIG_TD1 0x400079a4u +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8u +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM53_ORIG_TD0 0x400079a8u +#define CYREG_PHUB_TDMEM53_ORIG_TD1 0x400079acu +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0u +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM54_ORIG_TD0 0x400079b0u +#define CYREG_PHUB_TDMEM54_ORIG_TD1 0x400079b4u +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8u +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM55_ORIG_TD0 0x400079b8u +#define CYREG_PHUB_TDMEM55_ORIG_TD1 0x400079bcu +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0u +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM56_ORIG_TD0 0x400079c0u +#define CYREG_PHUB_TDMEM56_ORIG_TD1 0x400079c4u +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8u +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM57_ORIG_TD0 0x400079c8u +#define CYREG_PHUB_TDMEM57_ORIG_TD1 0x400079ccu +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0u +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM58_ORIG_TD0 0x400079d0u +#define CYREG_PHUB_TDMEM58_ORIG_TD1 0x400079d4u +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8u +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM59_ORIG_TD0 0x400079d8u +#define CYREG_PHUB_TDMEM59_ORIG_TD1 0x400079dcu +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0u +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM60_ORIG_TD0 0x400079e0u +#define CYREG_PHUB_TDMEM60_ORIG_TD1 0x400079e4u +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8u +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM61_ORIG_TD0 0x400079e8u +#define CYREG_PHUB_TDMEM61_ORIG_TD1 0x400079ecu +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0u +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM62_ORIG_TD0 0x400079f0u +#define CYREG_PHUB_TDMEM62_ORIG_TD1 0x400079f4u +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8u +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM63_ORIG_TD0 0x400079f8u +#define CYREG_PHUB_TDMEM63_ORIG_TD1 0x400079fcu +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00u +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM64_ORIG_TD0 0x40007a00u +#define CYREG_PHUB_TDMEM64_ORIG_TD1 0x40007a04u +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08u +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM65_ORIG_TD0 0x40007a08u +#define CYREG_PHUB_TDMEM65_ORIG_TD1 0x40007a0cu +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10u +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM66_ORIG_TD0 0x40007a10u +#define CYREG_PHUB_TDMEM66_ORIG_TD1 0x40007a14u +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18u +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM67_ORIG_TD0 0x40007a18u +#define CYREG_PHUB_TDMEM67_ORIG_TD1 0x40007a1cu +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20u +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM68_ORIG_TD0 0x40007a20u +#define CYREG_PHUB_TDMEM68_ORIG_TD1 0x40007a24u +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28u +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM69_ORIG_TD0 0x40007a28u +#define CYREG_PHUB_TDMEM69_ORIG_TD1 0x40007a2cu +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30u +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM70_ORIG_TD0 0x40007a30u +#define CYREG_PHUB_TDMEM70_ORIG_TD1 0x40007a34u +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38u +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM71_ORIG_TD0 0x40007a38u +#define CYREG_PHUB_TDMEM71_ORIG_TD1 0x40007a3cu +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40u +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM72_ORIG_TD0 0x40007a40u +#define CYREG_PHUB_TDMEM72_ORIG_TD1 0x40007a44u +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48u +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM73_ORIG_TD0 0x40007a48u +#define CYREG_PHUB_TDMEM73_ORIG_TD1 0x40007a4cu +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50u +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM74_ORIG_TD0 0x40007a50u +#define CYREG_PHUB_TDMEM74_ORIG_TD1 0x40007a54u +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58u +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM75_ORIG_TD0 0x40007a58u +#define CYREG_PHUB_TDMEM75_ORIG_TD1 0x40007a5cu +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60u +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM76_ORIG_TD0 0x40007a60u +#define CYREG_PHUB_TDMEM76_ORIG_TD1 0x40007a64u +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68u +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM77_ORIG_TD0 0x40007a68u +#define CYREG_PHUB_TDMEM77_ORIG_TD1 0x40007a6cu +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70u +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM78_ORIG_TD0 0x40007a70u +#define CYREG_PHUB_TDMEM78_ORIG_TD1 0x40007a74u +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78u +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM79_ORIG_TD0 0x40007a78u +#define CYREG_PHUB_TDMEM79_ORIG_TD1 0x40007a7cu +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80u +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM80_ORIG_TD0 0x40007a80u +#define CYREG_PHUB_TDMEM80_ORIG_TD1 0x40007a84u +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88u +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM81_ORIG_TD0 0x40007a88u +#define CYREG_PHUB_TDMEM81_ORIG_TD1 0x40007a8cu +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90u +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM82_ORIG_TD0 0x40007a90u +#define CYREG_PHUB_TDMEM82_ORIG_TD1 0x40007a94u +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98u +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM83_ORIG_TD0 0x40007a98u +#define CYREG_PHUB_TDMEM83_ORIG_TD1 0x40007a9cu +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0u +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM84_ORIG_TD0 0x40007aa0u +#define CYREG_PHUB_TDMEM84_ORIG_TD1 0x40007aa4u +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8u +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM85_ORIG_TD0 0x40007aa8u +#define CYREG_PHUB_TDMEM85_ORIG_TD1 0x40007aacu +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0u +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM86_ORIG_TD0 0x40007ab0u +#define CYREG_PHUB_TDMEM86_ORIG_TD1 0x40007ab4u +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8u +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM87_ORIG_TD0 0x40007ab8u +#define CYREG_PHUB_TDMEM87_ORIG_TD1 0x40007abcu +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0u +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM88_ORIG_TD0 0x40007ac0u +#define CYREG_PHUB_TDMEM88_ORIG_TD1 0x40007ac4u +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8u +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM89_ORIG_TD0 0x40007ac8u +#define CYREG_PHUB_TDMEM89_ORIG_TD1 0x40007accu +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0u +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM90_ORIG_TD0 0x40007ad0u +#define CYREG_PHUB_TDMEM90_ORIG_TD1 0x40007ad4u +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8u +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM91_ORIG_TD0 0x40007ad8u +#define CYREG_PHUB_TDMEM91_ORIG_TD1 0x40007adcu +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0u +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM92_ORIG_TD0 0x40007ae0u +#define CYREG_PHUB_TDMEM92_ORIG_TD1 0x40007ae4u +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8u +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM93_ORIG_TD0 0x40007ae8u +#define CYREG_PHUB_TDMEM93_ORIG_TD1 0x40007aecu +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0u +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM94_ORIG_TD0 0x40007af0u +#define CYREG_PHUB_TDMEM94_ORIG_TD1 0x40007af4u +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8u +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM95_ORIG_TD0 0x40007af8u +#define CYREG_PHUB_TDMEM95_ORIG_TD1 0x40007afcu +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00u +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM96_ORIG_TD0 0x40007b00u +#define CYREG_PHUB_TDMEM96_ORIG_TD1 0x40007b04u +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08u +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM97_ORIG_TD0 0x40007b08u +#define CYREG_PHUB_TDMEM97_ORIG_TD1 0x40007b0cu +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10u +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM98_ORIG_TD0 0x40007b10u +#define CYREG_PHUB_TDMEM98_ORIG_TD1 0x40007b14u +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18u +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM99_ORIG_TD0 0x40007b18u +#define CYREG_PHUB_TDMEM99_ORIG_TD1 0x40007b1cu +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20u +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM100_ORIG_TD0 0x40007b20u +#define CYREG_PHUB_TDMEM100_ORIG_TD1 0x40007b24u +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28u +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM101_ORIG_TD0 0x40007b28u +#define CYREG_PHUB_TDMEM101_ORIG_TD1 0x40007b2cu +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30u +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM102_ORIG_TD0 0x40007b30u +#define CYREG_PHUB_TDMEM102_ORIG_TD1 0x40007b34u +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38u +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM103_ORIG_TD0 0x40007b38u +#define CYREG_PHUB_TDMEM103_ORIG_TD1 0x40007b3cu +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40u +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM104_ORIG_TD0 0x40007b40u +#define CYREG_PHUB_TDMEM104_ORIG_TD1 0x40007b44u +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48u +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM105_ORIG_TD0 0x40007b48u +#define CYREG_PHUB_TDMEM105_ORIG_TD1 0x40007b4cu +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50u +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM106_ORIG_TD0 0x40007b50u +#define CYREG_PHUB_TDMEM106_ORIG_TD1 0x40007b54u +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58u +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM107_ORIG_TD0 0x40007b58u +#define CYREG_PHUB_TDMEM107_ORIG_TD1 0x40007b5cu +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60u +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM108_ORIG_TD0 0x40007b60u +#define CYREG_PHUB_TDMEM108_ORIG_TD1 0x40007b64u +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68u +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM109_ORIG_TD0 0x40007b68u +#define CYREG_PHUB_TDMEM109_ORIG_TD1 0x40007b6cu +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70u +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM110_ORIG_TD0 0x40007b70u +#define CYREG_PHUB_TDMEM110_ORIG_TD1 0x40007b74u +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78u +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM111_ORIG_TD0 0x40007b78u +#define CYREG_PHUB_TDMEM111_ORIG_TD1 0x40007b7cu +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80u +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM112_ORIG_TD0 0x40007b80u +#define CYREG_PHUB_TDMEM112_ORIG_TD1 0x40007b84u +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88u +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM113_ORIG_TD0 0x40007b88u +#define CYREG_PHUB_TDMEM113_ORIG_TD1 0x40007b8cu +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90u +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM114_ORIG_TD0 0x40007b90u +#define CYREG_PHUB_TDMEM114_ORIG_TD1 0x40007b94u +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98u +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM115_ORIG_TD0 0x40007b98u +#define CYREG_PHUB_TDMEM115_ORIG_TD1 0x40007b9cu +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0u +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM116_ORIG_TD0 0x40007ba0u +#define CYREG_PHUB_TDMEM116_ORIG_TD1 0x40007ba4u +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8u +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM117_ORIG_TD0 0x40007ba8u +#define CYREG_PHUB_TDMEM117_ORIG_TD1 0x40007bacu +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0u +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM118_ORIG_TD0 0x40007bb0u +#define CYREG_PHUB_TDMEM118_ORIG_TD1 0x40007bb4u +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8u +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM119_ORIG_TD0 0x40007bb8u +#define CYREG_PHUB_TDMEM119_ORIG_TD1 0x40007bbcu +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0u +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM120_ORIG_TD0 0x40007bc0u +#define CYREG_PHUB_TDMEM120_ORIG_TD1 0x40007bc4u +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8u +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM121_ORIG_TD0 0x40007bc8u +#define CYREG_PHUB_TDMEM121_ORIG_TD1 0x40007bccu +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0u +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM122_ORIG_TD0 0x40007bd0u +#define CYREG_PHUB_TDMEM122_ORIG_TD1 0x40007bd4u +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8u +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM123_ORIG_TD0 0x40007bd8u +#define CYREG_PHUB_TDMEM123_ORIG_TD1 0x40007bdcu +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0u +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM124_ORIG_TD0 0x40007be0u +#define CYREG_PHUB_TDMEM124_ORIG_TD1 0x40007be4u +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8u +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM125_ORIG_TD0 0x40007be8u +#define CYREG_PHUB_TDMEM125_ORIG_TD1 0x40007becu +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0u +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM126_ORIG_TD0 0x40007bf0u +#define CYREG_PHUB_TDMEM126_ORIG_TD1 0x40007bf4u +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8u +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM127_ORIG_TD0 0x40007bf8u +#define CYREG_PHUB_TDMEM127_ORIG_TD1 0x40007bfcu +#define CYDEV_EE_BASE 0x40008000u +#define CYDEV_EE_SIZE 0x00000800u +#define CYREG_EE_DATA_MBASE 0x40008000u +#define CYREG_EE_DATA_MSIZE 0x00000800u +#define CYDEV_CAN0_BASE 0x4000a000u +#define CYDEV_CAN0_SIZE 0x000002a0u +#define CYDEV_CAN0_CSR_BASE 0x4000a000u +#define CYDEV_CAN0_CSR_SIZE 0x00000018u +#define CYREG_CAN0_CSR_INT_SR 0x4000a000u +#define CYREG_CAN0_CSR_INT_EN 0x4000a004u +#define CYREG_CAN0_CSR_BUF_SR 0x4000a008u +#define CYREG_CAN0_CSR_ERR_SR 0x4000a00cu +#define CYREG_CAN0_CSR_CMD 0x4000a010u +#define CYREG_CAN0_CSR_CFG 0x4000a014u +#define CYDEV_CAN0_TX0_BASE 0x4000a020u +#define CYDEV_CAN0_TX0_SIZE 0x00000010u +#define CYREG_CAN0_TX0_CMD 0x4000a020u +#define CYREG_CAN0_TX0_ID 0x4000a024u +#define CYREG_CAN0_TX0_DH 0x4000a028u +#define CYREG_CAN0_TX0_DL 0x4000a02cu +#define CYDEV_CAN0_TX1_BASE 0x4000a030u +#define CYDEV_CAN0_TX1_SIZE 0x00000010u +#define CYREG_CAN0_TX1_CMD 0x4000a030u +#define CYREG_CAN0_TX1_ID 0x4000a034u +#define CYREG_CAN0_TX1_DH 0x4000a038u +#define CYREG_CAN0_TX1_DL 0x4000a03cu +#define CYDEV_CAN0_TX2_BASE 0x4000a040u +#define CYDEV_CAN0_TX2_SIZE 0x00000010u +#define CYREG_CAN0_TX2_CMD 0x4000a040u +#define CYREG_CAN0_TX2_ID 0x4000a044u +#define CYREG_CAN0_TX2_DH 0x4000a048u +#define CYREG_CAN0_TX2_DL 0x4000a04cu +#define CYDEV_CAN0_TX3_BASE 0x4000a050u +#define CYDEV_CAN0_TX3_SIZE 0x00000010u +#define CYREG_CAN0_TX3_CMD 0x4000a050u +#define CYREG_CAN0_TX3_ID 0x4000a054u +#define CYREG_CAN0_TX3_DH 0x4000a058u +#define CYREG_CAN0_TX3_DL 0x4000a05cu +#define CYDEV_CAN0_TX4_BASE 0x4000a060u +#define CYDEV_CAN0_TX4_SIZE 0x00000010u +#define CYREG_CAN0_TX4_CMD 0x4000a060u +#define CYREG_CAN0_TX4_ID 0x4000a064u +#define CYREG_CAN0_TX4_DH 0x4000a068u +#define CYREG_CAN0_TX4_DL 0x4000a06cu +#define CYDEV_CAN0_TX5_BASE 0x4000a070u +#define CYDEV_CAN0_TX5_SIZE 0x00000010u +#define CYREG_CAN0_TX5_CMD 0x4000a070u +#define CYREG_CAN0_TX5_ID 0x4000a074u +#define CYREG_CAN0_TX5_DH 0x4000a078u +#define CYREG_CAN0_TX5_DL 0x4000a07cu +#define CYDEV_CAN0_TX6_BASE 0x4000a080u +#define CYDEV_CAN0_TX6_SIZE 0x00000010u +#define CYREG_CAN0_TX6_CMD 0x4000a080u +#define CYREG_CAN0_TX6_ID 0x4000a084u +#define CYREG_CAN0_TX6_DH 0x4000a088u +#define CYREG_CAN0_TX6_DL 0x4000a08cu +#define CYDEV_CAN0_TX7_BASE 0x4000a090u +#define CYDEV_CAN0_TX7_SIZE 0x00000010u +#define CYREG_CAN0_TX7_CMD 0x4000a090u +#define CYREG_CAN0_TX7_ID 0x4000a094u +#define CYREG_CAN0_TX7_DH 0x4000a098u +#define CYREG_CAN0_TX7_DL 0x4000a09cu +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0u +#define CYDEV_CAN0_RX0_SIZE 0x00000020u +#define CYREG_CAN0_RX0_CMD 0x4000a0a0u +#define CYREG_CAN0_RX0_ID 0x4000a0a4u +#define CYREG_CAN0_RX0_DH 0x4000a0a8u +#define CYREG_CAN0_RX0_DL 0x4000a0acu +#define CYREG_CAN0_RX0_AMR 0x4000a0b0u +#define CYREG_CAN0_RX0_ACR 0x4000a0b4u +#define CYREG_CAN0_RX0_AMRD 0x4000a0b8u +#define CYREG_CAN0_RX0_ACRD 0x4000a0bcu +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0u +#define CYDEV_CAN0_RX1_SIZE 0x00000020u +#define CYREG_CAN0_RX1_CMD 0x4000a0c0u +#define CYREG_CAN0_RX1_ID 0x4000a0c4u +#define CYREG_CAN0_RX1_DH 0x4000a0c8u +#define CYREG_CAN0_RX1_DL 0x4000a0ccu +#define CYREG_CAN0_RX1_AMR 0x4000a0d0u +#define CYREG_CAN0_RX1_ACR 0x4000a0d4u +#define CYREG_CAN0_RX1_AMRD 0x4000a0d8u +#define CYREG_CAN0_RX1_ACRD 0x4000a0dcu +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0u +#define CYDEV_CAN0_RX2_SIZE 0x00000020u +#define CYREG_CAN0_RX2_CMD 0x4000a0e0u +#define CYREG_CAN0_RX2_ID 0x4000a0e4u +#define CYREG_CAN0_RX2_DH 0x4000a0e8u +#define CYREG_CAN0_RX2_DL 0x4000a0ecu +#define CYREG_CAN0_RX2_AMR 0x4000a0f0u +#define CYREG_CAN0_RX2_ACR 0x4000a0f4u +#define CYREG_CAN0_RX2_AMRD 0x4000a0f8u +#define CYREG_CAN0_RX2_ACRD 0x4000a0fcu +#define CYDEV_CAN0_RX3_BASE 0x4000a100u +#define CYDEV_CAN0_RX3_SIZE 0x00000020u +#define CYREG_CAN0_RX3_CMD 0x4000a100u +#define CYREG_CAN0_RX3_ID 0x4000a104u +#define CYREG_CAN0_RX3_DH 0x4000a108u +#define CYREG_CAN0_RX3_DL 0x4000a10cu +#define CYREG_CAN0_RX3_AMR 0x4000a110u +#define CYREG_CAN0_RX3_ACR 0x4000a114u +#define CYREG_CAN0_RX3_AMRD 0x4000a118u +#define CYREG_CAN0_RX3_ACRD 0x4000a11cu +#define CYDEV_CAN0_RX4_BASE 0x4000a120u +#define CYDEV_CAN0_RX4_SIZE 0x00000020u +#define CYREG_CAN0_RX4_CMD 0x4000a120u +#define CYREG_CAN0_RX4_ID 0x4000a124u +#define CYREG_CAN0_RX4_DH 0x4000a128u +#define CYREG_CAN0_RX4_DL 0x4000a12cu +#define CYREG_CAN0_RX4_AMR 0x4000a130u +#define CYREG_CAN0_RX4_ACR 0x4000a134u +#define CYREG_CAN0_RX4_AMRD 0x4000a138u +#define CYREG_CAN0_RX4_ACRD 0x4000a13cu +#define CYDEV_CAN0_RX5_BASE 0x4000a140u +#define CYDEV_CAN0_RX5_SIZE 0x00000020u +#define CYREG_CAN0_RX5_CMD 0x4000a140u +#define CYREG_CAN0_RX5_ID 0x4000a144u +#define CYREG_CAN0_RX5_DH 0x4000a148u +#define CYREG_CAN0_RX5_DL 0x4000a14cu +#define CYREG_CAN0_RX5_AMR 0x4000a150u +#define CYREG_CAN0_RX5_ACR 0x4000a154u +#define CYREG_CAN0_RX5_AMRD 0x4000a158u +#define CYREG_CAN0_RX5_ACRD 0x4000a15cu +#define CYDEV_CAN0_RX6_BASE 0x4000a160u +#define CYDEV_CAN0_RX6_SIZE 0x00000020u +#define CYREG_CAN0_RX6_CMD 0x4000a160u +#define CYREG_CAN0_RX6_ID 0x4000a164u +#define CYREG_CAN0_RX6_DH 0x4000a168u +#define CYREG_CAN0_RX6_DL 0x4000a16cu +#define CYREG_CAN0_RX6_AMR 0x4000a170u +#define CYREG_CAN0_RX6_ACR 0x4000a174u +#define CYREG_CAN0_RX6_AMRD 0x4000a178u +#define CYREG_CAN0_RX6_ACRD 0x4000a17cu +#define CYDEV_CAN0_RX7_BASE 0x4000a180u +#define CYDEV_CAN0_RX7_SIZE 0x00000020u +#define CYREG_CAN0_RX7_CMD 0x4000a180u +#define CYREG_CAN0_RX7_ID 0x4000a184u +#define CYREG_CAN0_RX7_DH 0x4000a188u +#define CYREG_CAN0_RX7_DL 0x4000a18cu +#define CYREG_CAN0_RX7_AMR 0x4000a190u +#define CYREG_CAN0_RX7_ACR 0x4000a194u +#define CYREG_CAN0_RX7_AMRD 0x4000a198u +#define CYREG_CAN0_RX7_ACRD 0x4000a19cu +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0u +#define CYDEV_CAN0_RX8_SIZE 0x00000020u +#define CYREG_CAN0_RX8_CMD 0x4000a1a0u +#define CYREG_CAN0_RX8_ID 0x4000a1a4u +#define CYREG_CAN0_RX8_DH 0x4000a1a8u +#define CYREG_CAN0_RX8_DL 0x4000a1acu +#define CYREG_CAN0_RX8_AMR 0x4000a1b0u +#define CYREG_CAN0_RX8_ACR 0x4000a1b4u +#define CYREG_CAN0_RX8_AMRD 0x4000a1b8u +#define CYREG_CAN0_RX8_ACRD 0x4000a1bcu +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0u +#define CYDEV_CAN0_RX9_SIZE 0x00000020u +#define CYREG_CAN0_RX9_CMD 0x4000a1c0u +#define CYREG_CAN0_RX9_ID 0x4000a1c4u +#define CYREG_CAN0_RX9_DH 0x4000a1c8u +#define CYREG_CAN0_RX9_DL 0x4000a1ccu +#define CYREG_CAN0_RX9_AMR 0x4000a1d0u +#define CYREG_CAN0_RX9_ACR 0x4000a1d4u +#define CYREG_CAN0_RX9_AMRD 0x4000a1d8u +#define CYREG_CAN0_RX9_ACRD 0x4000a1dcu +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0u +#define CYDEV_CAN0_RX10_SIZE 0x00000020u +#define CYREG_CAN0_RX10_CMD 0x4000a1e0u +#define CYREG_CAN0_RX10_ID 0x4000a1e4u +#define CYREG_CAN0_RX10_DH 0x4000a1e8u +#define CYREG_CAN0_RX10_DL 0x4000a1ecu +#define CYREG_CAN0_RX10_AMR 0x4000a1f0u +#define CYREG_CAN0_RX10_ACR 0x4000a1f4u +#define CYREG_CAN0_RX10_AMRD 0x4000a1f8u +#define CYREG_CAN0_RX10_ACRD 0x4000a1fcu +#define CYDEV_CAN0_RX11_BASE 0x4000a200u +#define CYDEV_CAN0_RX11_SIZE 0x00000020u +#define CYREG_CAN0_RX11_CMD 0x4000a200u +#define CYREG_CAN0_RX11_ID 0x4000a204u +#define CYREG_CAN0_RX11_DH 0x4000a208u +#define CYREG_CAN0_RX11_DL 0x4000a20cu +#define CYREG_CAN0_RX11_AMR 0x4000a210u +#define CYREG_CAN0_RX11_ACR 0x4000a214u +#define CYREG_CAN0_RX11_AMRD 0x4000a218u +#define CYREG_CAN0_RX11_ACRD 0x4000a21cu +#define CYDEV_CAN0_RX12_BASE 0x4000a220u +#define CYDEV_CAN0_RX12_SIZE 0x00000020u +#define CYREG_CAN0_RX12_CMD 0x4000a220u +#define CYREG_CAN0_RX12_ID 0x4000a224u +#define CYREG_CAN0_RX12_DH 0x4000a228u +#define CYREG_CAN0_RX12_DL 0x4000a22cu +#define CYREG_CAN0_RX12_AMR 0x4000a230u +#define CYREG_CAN0_RX12_ACR 0x4000a234u +#define CYREG_CAN0_RX12_AMRD 0x4000a238u +#define CYREG_CAN0_RX12_ACRD 0x4000a23cu +#define CYDEV_CAN0_RX13_BASE 0x4000a240u +#define CYDEV_CAN0_RX13_SIZE 0x00000020u +#define CYREG_CAN0_RX13_CMD 0x4000a240u +#define CYREG_CAN0_RX13_ID 0x4000a244u +#define CYREG_CAN0_RX13_DH 0x4000a248u +#define CYREG_CAN0_RX13_DL 0x4000a24cu +#define CYREG_CAN0_RX13_AMR 0x4000a250u +#define CYREG_CAN0_RX13_ACR 0x4000a254u +#define CYREG_CAN0_RX13_AMRD 0x4000a258u +#define CYREG_CAN0_RX13_ACRD 0x4000a25cu +#define CYDEV_CAN0_RX14_BASE 0x4000a260u +#define CYDEV_CAN0_RX14_SIZE 0x00000020u +#define CYREG_CAN0_RX14_CMD 0x4000a260u +#define CYREG_CAN0_RX14_ID 0x4000a264u +#define CYREG_CAN0_RX14_DH 0x4000a268u +#define CYREG_CAN0_RX14_DL 0x4000a26cu +#define CYREG_CAN0_RX14_AMR 0x4000a270u +#define CYREG_CAN0_RX14_ACR 0x4000a274u +#define CYREG_CAN0_RX14_AMRD 0x4000a278u +#define CYREG_CAN0_RX14_ACRD 0x4000a27cu +#define CYDEV_CAN0_RX15_BASE 0x4000a280u +#define CYDEV_CAN0_RX15_SIZE 0x00000020u +#define CYREG_CAN0_RX15_CMD 0x4000a280u +#define CYREG_CAN0_RX15_ID 0x4000a284u +#define CYREG_CAN0_RX15_DH 0x4000a288u +#define CYREG_CAN0_RX15_DL 0x4000a28cu +#define CYREG_CAN0_RX15_AMR 0x4000a290u +#define CYREG_CAN0_RX15_ACR 0x4000a294u +#define CYREG_CAN0_RX15_AMRD 0x4000a298u +#define CYREG_CAN0_RX15_ACRD 0x4000a29cu +#define CYDEV_DFB0_BASE 0x4000c000u +#define CYDEV_DFB0_SIZE 0x000007b5u +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000u +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200u +#define CYREG_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000u +#define CYREG_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200u +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200u +#define CYREG_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200u +#define CYREG_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400u +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100u +#define CYREG_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400u +#define CYREG_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500u +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100u +#define CYREG_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500u +#define CYREG_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600u +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100u +#define CYREG_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600u +#define CYREG_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700u +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040u +#define CYREG_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700u +#define CYREG_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040u +#define CYREG_DFB0_CR 0x4000c780u +#define CYREG_DFB0_SR 0x4000c784u +#define CYREG_DFB0_RAM_EN 0x4000c788u +#define CYREG_DFB0_RAM_DIR 0x4000c78cu +#define CYREG_DFB0_SEMA 0x4000c790u +#define CYREG_DFB0_DSI_CTRL 0x4000c794u +#define CYREG_DFB0_INT_CTRL 0x4000c798u +#define CYREG_DFB0_DMA_CTRL 0x4000c79cu +#define CYREG_DFB0_STAGEA 0x4000c7a0u +#define CYREG_DFB0_STAGEAM 0x4000c7a1u +#define CYREG_DFB0_STAGEAH 0x4000c7a2u +#define CYREG_DFB0_STAGEB 0x4000c7a4u +#define CYREG_DFB0_STAGEBM 0x4000c7a5u +#define CYREG_DFB0_STAGEBH 0x4000c7a6u +#define CYREG_DFB0_HOLDA 0x4000c7a8u +#define CYREG_DFB0_HOLDAM 0x4000c7a9u +#define CYREG_DFB0_HOLDAH 0x4000c7aau +#define CYREG_DFB0_HOLDAS 0x4000c7abu +#define CYREG_DFB0_HOLDB 0x4000c7acu +#define CYREG_DFB0_HOLDBM 0x4000c7adu +#define CYREG_DFB0_HOLDBH 0x4000c7aeu +#define CYREG_DFB0_HOLDBS 0x4000c7afu +#define CYREG_DFB0_COHER 0x4000c7b0u +#define CYREG_DFB0_DALIGN 0x4000c7b4u +#define CYDEV_UCFG_BASE 0x40010000u +#define CYDEV_UCFG_SIZE 0x00005040u +#define CYDEV_UCFG_B0_BASE 0x40010000u +#define CYDEV_UCFG_B0_SIZE 0x00000fefu +#define CYDEV_UCFG_B0_P0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070u +#define CYREG_B0_P0_U0_PLD_IT0 0x40010000u +#define CYREG_B0_P0_U0_PLD_IT1 0x40010004u +#define CYREG_B0_P0_U0_PLD_IT2 0x40010008u +#define CYREG_B0_P0_U0_PLD_IT3 0x4001000cu +#define CYREG_B0_P0_U0_PLD_IT4 0x40010010u +#define CYREG_B0_P0_U0_PLD_IT5 0x40010014u +#define CYREG_B0_P0_U0_PLD_IT6 0x40010018u +#define CYREG_B0_P0_U0_PLD_IT7 0x4001001cu +#define CYREG_B0_P0_U0_PLD_IT8 0x40010020u +#define CYREG_B0_P0_U0_PLD_IT9 0x40010024u +#define CYREG_B0_P0_U0_PLD_IT10 0x40010028u +#define CYREG_B0_P0_U0_PLD_IT11 0x4001002cu +#define CYREG_B0_P0_U0_PLD_ORT0 0x40010030u +#define CYREG_B0_P0_U0_PLD_ORT1 0x40010032u +#define CYREG_B0_P0_U0_PLD_ORT2 0x40010034u +#define CYREG_B0_P0_U0_PLD_ORT3 0x40010036u +#define CYREG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038u +#define CYREG_B0_P0_U0_MC_CFG_XORFB 0x4001003au +#define CYREG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003cu +#define CYREG_B0_P0_U0_MC_CFG_BYPASS 0x4001003eu +#define CYREG_B0_P0_U0_CFG0 0x40010040u +#define CYREG_B0_P0_U0_CFG1 0x40010041u +#define CYREG_B0_P0_U0_CFG2 0x40010042u +#define CYREG_B0_P0_U0_CFG3 0x40010043u +#define CYREG_B0_P0_U0_CFG4 0x40010044u +#define CYREG_B0_P0_U0_CFG5 0x40010045u +#define CYREG_B0_P0_U0_CFG6 0x40010046u +#define CYREG_B0_P0_U0_CFG7 0x40010047u +#define CYREG_B0_P0_U0_CFG8 0x40010048u +#define CYREG_B0_P0_U0_CFG9 0x40010049u +#define CYREG_B0_P0_U0_CFG10 0x4001004au +#define CYREG_B0_P0_U0_CFG11 0x4001004bu +#define CYREG_B0_P0_U0_CFG12 0x4001004cu +#define CYREG_B0_P0_U0_CFG13 0x4001004du +#define CYREG_B0_P0_U0_CFG14 0x4001004eu +#define CYREG_B0_P0_U0_CFG15 0x4001004fu +#define CYREG_B0_P0_U0_CFG16 0x40010050u +#define CYREG_B0_P0_U0_CFG17 0x40010051u +#define CYREG_B0_P0_U0_CFG18 0x40010052u +#define CYREG_B0_P0_U0_CFG19 0x40010053u +#define CYREG_B0_P0_U0_CFG20 0x40010054u +#define CYREG_B0_P0_U0_CFG21 0x40010055u +#define CYREG_B0_P0_U0_CFG22 0x40010056u +#define CYREG_B0_P0_U0_CFG23 0x40010057u +#define CYREG_B0_P0_U0_CFG24 0x40010058u +#define CYREG_B0_P0_U0_CFG25 0x40010059u +#define CYREG_B0_P0_U0_CFG26 0x4001005au +#define CYREG_B0_P0_U0_CFG27 0x4001005bu +#define CYREG_B0_P0_U0_CFG28 0x4001005cu +#define CYREG_B0_P0_U0_CFG29 0x4001005du +#define CYREG_B0_P0_U0_CFG30 0x4001005eu +#define CYREG_B0_P0_U0_CFG31 0x4001005fu +#define CYREG_B0_P0_U0_DCFG0 0x40010060u +#define CYREG_B0_P0_U0_DCFG1 0x40010062u +#define CYREG_B0_P0_U0_DCFG2 0x40010064u +#define CYREG_B0_P0_U0_DCFG3 0x40010066u +#define CYREG_B0_P0_U0_DCFG4 0x40010068u +#define CYREG_B0_P0_U0_DCFG5 0x4001006au +#define CYREG_B0_P0_U0_DCFG6 0x4001006cu +#define CYREG_B0_P0_U0_DCFG7 0x4001006eu +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080u +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070u +#define CYREG_B0_P0_U1_PLD_IT0 0x40010080u +#define CYREG_B0_P0_U1_PLD_IT1 0x40010084u +#define CYREG_B0_P0_U1_PLD_IT2 0x40010088u +#define CYREG_B0_P0_U1_PLD_IT3 0x4001008cu +#define CYREG_B0_P0_U1_PLD_IT4 0x40010090u +#define CYREG_B0_P0_U1_PLD_IT5 0x40010094u +#define CYREG_B0_P0_U1_PLD_IT6 0x40010098u +#define CYREG_B0_P0_U1_PLD_IT7 0x4001009cu +#define CYREG_B0_P0_U1_PLD_IT8 0x400100a0u +#define CYREG_B0_P0_U1_PLD_IT9 0x400100a4u +#define CYREG_B0_P0_U1_PLD_IT10 0x400100a8u +#define CYREG_B0_P0_U1_PLD_IT11 0x400100acu +#define CYREG_B0_P0_U1_PLD_ORT0 0x400100b0u +#define CYREG_B0_P0_U1_PLD_ORT1 0x400100b2u +#define CYREG_B0_P0_U1_PLD_ORT2 0x400100b4u +#define CYREG_B0_P0_U1_PLD_ORT3 0x400100b6u +#define CYREG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8u +#define CYREG_B0_P0_U1_MC_CFG_XORFB 0x400100bau +#define CYREG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bcu +#define CYREG_B0_P0_U1_MC_CFG_BYPASS 0x400100beu +#define CYREG_B0_P0_U1_CFG0 0x400100c0u +#define CYREG_B0_P0_U1_CFG1 0x400100c1u +#define CYREG_B0_P0_U1_CFG2 0x400100c2u +#define CYREG_B0_P0_U1_CFG3 0x400100c3u +#define CYREG_B0_P0_U1_CFG4 0x400100c4u +#define CYREG_B0_P0_U1_CFG5 0x400100c5u +#define CYREG_B0_P0_U1_CFG6 0x400100c6u +#define CYREG_B0_P0_U1_CFG7 0x400100c7u +#define CYREG_B0_P0_U1_CFG8 0x400100c8u +#define CYREG_B0_P0_U1_CFG9 0x400100c9u +#define CYREG_B0_P0_U1_CFG10 0x400100cau +#define CYREG_B0_P0_U1_CFG11 0x400100cbu +#define CYREG_B0_P0_U1_CFG12 0x400100ccu +#define CYREG_B0_P0_U1_CFG13 0x400100cdu +#define CYREG_B0_P0_U1_CFG14 0x400100ceu +#define CYREG_B0_P0_U1_CFG15 0x400100cfu +#define CYREG_B0_P0_U1_CFG16 0x400100d0u +#define CYREG_B0_P0_U1_CFG17 0x400100d1u +#define CYREG_B0_P0_U1_CFG18 0x400100d2u +#define CYREG_B0_P0_U1_CFG19 0x400100d3u +#define CYREG_B0_P0_U1_CFG20 0x400100d4u +#define CYREG_B0_P0_U1_CFG21 0x400100d5u +#define CYREG_B0_P0_U1_CFG22 0x400100d6u +#define CYREG_B0_P0_U1_CFG23 0x400100d7u +#define CYREG_B0_P0_U1_CFG24 0x400100d8u +#define CYREG_B0_P0_U1_CFG25 0x400100d9u +#define CYREG_B0_P0_U1_CFG26 0x400100dau +#define CYREG_B0_P0_U1_CFG27 0x400100dbu +#define CYREG_B0_P0_U1_CFG28 0x400100dcu +#define CYREG_B0_P0_U1_CFG29 0x400100ddu +#define CYREG_B0_P0_U1_CFG30 0x400100deu +#define CYREG_B0_P0_U1_CFG31 0x400100dfu +#define CYREG_B0_P0_U1_DCFG0 0x400100e0u +#define CYREG_B0_P0_U1_DCFG1 0x400100e2u +#define CYREG_B0_P0_U1_DCFG2 0x400100e4u +#define CYREG_B0_P0_U1_DCFG3 0x400100e6u +#define CYREG_B0_P0_U1_DCFG4 0x400100e8u +#define CYREG_B0_P0_U1_DCFG5 0x400100eau +#define CYREG_B0_P0_U1_DCFG6 0x400100ecu +#define CYREG_B0_P0_U1_DCFG7 0x400100eeu +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100u +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P1_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070u +#define CYREG_B0_P1_U0_PLD_IT0 0x40010200u +#define CYREG_B0_P1_U0_PLD_IT1 0x40010204u +#define CYREG_B0_P1_U0_PLD_IT2 0x40010208u +#define CYREG_B0_P1_U0_PLD_IT3 0x4001020cu +#define CYREG_B0_P1_U0_PLD_IT4 0x40010210u +#define CYREG_B0_P1_U0_PLD_IT5 0x40010214u +#define CYREG_B0_P1_U0_PLD_IT6 0x40010218u +#define CYREG_B0_P1_U0_PLD_IT7 0x4001021cu +#define CYREG_B0_P1_U0_PLD_IT8 0x40010220u +#define CYREG_B0_P1_U0_PLD_IT9 0x40010224u +#define CYREG_B0_P1_U0_PLD_IT10 0x40010228u +#define CYREG_B0_P1_U0_PLD_IT11 0x4001022cu +#define CYREG_B0_P1_U0_PLD_ORT0 0x40010230u +#define CYREG_B0_P1_U0_PLD_ORT1 0x40010232u +#define CYREG_B0_P1_U0_PLD_ORT2 0x40010234u +#define CYREG_B0_P1_U0_PLD_ORT3 0x40010236u +#define CYREG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238u +#define CYREG_B0_P1_U0_MC_CFG_XORFB 0x4001023au +#define CYREG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023cu +#define CYREG_B0_P1_U0_MC_CFG_BYPASS 0x4001023eu +#define CYREG_B0_P1_U0_CFG0 0x40010240u +#define CYREG_B0_P1_U0_CFG1 0x40010241u +#define CYREG_B0_P1_U0_CFG2 0x40010242u +#define CYREG_B0_P1_U0_CFG3 0x40010243u +#define CYREG_B0_P1_U0_CFG4 0x40010244u +#define CYREG_B0_P1_U0_CFG5 0x40010245u +#define CYREG_B0_P1_U0_CFG6 0x40010246u +#define CYREG_B0_P1_U0_CFG7 0x40010247u +#define CYREG_B0_P1_U0_CFG8 0x40010248u +#define CYREG_B0_P1_U0_CFG9 0x40010249u +#define CYREG_B0_P1_U0_CFG10 0x4001024au +#define CYREG_B0_P1_U0_CFG11 0x4001024bu +#define CYREG_B0_P1_U0_CFG12 0x4001024cu +#define CYREG_B0_P1_U0_CFG13 0x4001024du +#define CYREG_B0_P1_U0_CFG14 0x4001024eu +#define CYREG_B0_P1_U0_CFG15 0x4001024fu +#define CYREG_B0_P1_U0_CFG16 0x40010250u +#define CYREG_B0_P1_U0_CFG17 0x40010251u +#define CYREG_B0_P1_U0_CFG18 0x40010252u +#define CYREG_B0_P1_U0_CFG19 0x40010253u +#define CYREG_B0_P1_U0_CFG20 0x40010254u +#define CYREG_B0_P1_U0_CFG21 0x40010255u +#define CYREG_B0_P1_U0_CFG22 0x40010256u +#define CYREG_B0_P1_U0_CFG23 0x40010257u +#define CYREG_B0_P1_U0_CFG24 0x40010258u +#define CYREG_B0_P1_U0_CFG25 0x40010259u +#define CYREG_B0_P1_U0_CFG26 0x4001025au +#define CYREG_B0_P1_U0_CFG27 0x4001025bu +#define CYREG_B0_P1_U0_CFG28 0x4001025cu +#define CYREG_B0_P1_U0_CFG29 0x4001025du +#define CYREG_B0_P1_U0_CFG30 0x4001025eu +#define CYREG_B0_P1_U0_CFG31 0x4001025fu +#define CYREG_B0_P1_U0_DCFG0 0x40010260u +#define CYREG_B0_P1_U0_DCFG1 0x40010262u +#define CYREG_B0_P1_U0_DCFG2 0x40010264u +#define CYREG_B0_P1_U0_DCFG3 0x40010266u +#define CYREG_B0_P1_U0_DCFG4 0x40010268u +#define CYREG_B0_P1_U0_DCFG5 0x4001026au +#define CYREG_B0_P1_U0_DCFG6 0x4001026cu +#define CYREG_B0_P1_U0_DCFG7 0x4001026eu +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280u +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070u +#define CYREG_B0_P1_U1_PLD_IT0 0x40010280u +#define CYREG_B0_P1_U1_PLD_IT1 0x40010284u +#define CYREG_B0_P1_U1_PLD_IT2 0x40010288u +#define CYREG_B0_P1_U1_PLD_IT3 0x4001028cu +#define CYREG_B0_P1_U1_PLD_IT4 0x40010290u +#define CYREG_B0_P1_U1_PLD_IT5 0x40010294u +#define CYREG_B0_P1_U1_PLD_IT6 0x40010298u +#define CYREG_B0_P1_U1_PLD_IT7 0x4001029cu +#define CYREG_B0_P1_U1_PLD_IT8 0x400102a0u +#define CYREG_B0_P1_U1_PLD_IT9 0x400102a4u +#define CYREG_B0_P1_U1_PLD_IT10 0x400102a8u +#define CYREG_B0_P1_U1_PLD_IT11 0x400102acu +#define CYREG_B0_P1_U1_PLD_ORT0 0x400102b0u +#define CYREG_B0_P1_U1_PLD_ORT1 0x400102b2u +#define CYREG_B0_P1_U1_PLD_ORT2 0x400102b4u +#define CYREG_B0_P1_U1_PLD_ORT3 0x400102b6u +#define CYREG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8u +#define CYREG_B0_P1_U1_MC_CFG_XORFB 0x400102bau +#define CYREG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bcu +#define CYREG_B0_P1_U1_MC_CFG_BYPASS 0x400102beu +#define CYREG_B0_P1_U1_CFG0 0x400102c0u +#define CYREG_B0_P1_U1_CFG1 0x400102c1u +#define CYREG_B0_P1_U1_CFG2 0x400102c2u +#define CYREG_B0_P1_U1_CFG3 0x400102c3u +#define CYREG_B0_P1_U1_CFG4 0x400102c4u +#define CYREG_B0_P1_U1_CFG5 0x400102c5u +#define CYREG_B0_P1_U1_CFG6 0x400102c6u +#define CYREG_B0_P1_U1_CFG7 0x400102c7u +#define CYREG_B0_P1_U1_CFG8 0x400102c8u +#define CYREG_B0_P1_U1_CFG9 0x400102c9u +#define CYREG_B0_P1_U1_CFG10 0x400102cau +#define CYREG_B0_P1_U1_CFG11 0x400102cbu +#define CYREG_B0_P1_U1_CFG12 0x400102ccu +#define CYREG_B0_P1_U1_CFG13 0x400102cdu +#define CYREG_B0_P1_U1_CFG14 0x400102ceu +#define CYREG_B0_P1_U1_CFG15 0x400102cfu +#define CYREG_B0_P1_U1_CFG16 0x400102d0u +#define CYREG_B0_P1_U1_CFG17 0x400102d1u +#define CYREG_B0_P1_U1_CFG18 0x400102d2u +#define CYREG_B0_P1_U1_CFG19 0x400102d3u +#define CYREG_B0_P1_U1_CFG20 0x400102d4u +#define CYREG_B0_P1_U1_CFG21 0x400102d5u +#define CYREG_B0_P1_U1_CFG22 0x400102d6u +#define CYREG_B0_P1_U1_CFG23 0x400102d7u +#define CYREG_B0_P1_U1_CFG24 0x400102d8u +#define CYREG_B0_P1_U1_CFG25 0x400102d9u +#define CYREG_B0_P1_U1_CFG26 0x400102dau +#define CYREG_B0_P1_U1_CFG27 0x400102dbu +#define CYREG_B0_P1_U1_CFG28 0x400102dcu +#define CYREG_B0_P1_U1_CFG29 0x400102ddu +#define CYREG_B0_P1_U1_CFG30 0x400102deu +#define CYREG_B0_P1_U1_CFG31 0x400102dfu +#define CYREG_B0_P1_U1_DCFG0 0x400102e0u +#define CYREG_B0_P1_U1_DCFG1 0x400102e2u +#define CYREG_B0_P1_U1_DCFG2 0x400102e4u +#define CYREG_B0_P1_U1_DCFG3 0x400102e6u +#define CYREG_B0_P1_U1_DCFG4 0x400102e8u +#define CYREG_B0_P1_U1_DCFG5 0x400102eau +#define CYREG_B0_P1_U1_DCFG6 0x400102ecu +#define CYREG_B0_P1_U1_DCFG7 0x400102eeu +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300u +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P2_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070u +#define CYREG_B0_P2_U0_PLD_IT0 0x40010400u +#define CYREG_B0_P2_U0_PLD_IT1 0x40010404u +#define CYREG_B0_P2_U0_PLD_IT2 0x40010408u +#define CYREG_B0_P2_U0_PLD_IT3 0x4001040cu +#define CYREG_B0_P2_U0_PLD_IT4 0x40010410u +#define CYREG_B0_P2_U0_PLD_IT5 0x40010414u +#define CYREG_B0_P2_U0_PLD_IT6 0x40010418u +#define CYREG_B0_P2_U0_PLD_IT7 0x4001041cu +#define CYREG_B0_P2_U0_PLD_IT8 0x40010420u +#define CYREG_B0_P2_U0_PLD_IT9 0x40010424u +#define CYREG_B0_P2_U0_PLD_IT10 0x40010428u +#define CYREG_B0_P2_U0_PLD_IT11 0x4001042cu +#define CYREG_B0_P2_U0_PLD_ORT0 0x40010430u +#define CYREG_B0_P2_U0_PLD_ORT1 0x40010432u +#define CYREG_B0_P2_U0_PLD_ORT2 0x40010434u +#define CYREG_B0_P2_U0_PLD_ORT3 0x40010436u +#define CYREG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438u +#define CYREG_B0_P2_U0_MC_CFG_XORFB 0x4001043au +#define CYREG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043cu +#define CYREG_B0_P2_U0_MC_CFG_BYPASS 0x4001043eu +#define CYREG_B0_P2_U0_CFG0 0x40010440u +#define CYREG_B0_P2_U0_CFG1 0x40010441u +#define CYREG_B0_P2_U0_CFG2 0x40010442u +#define CYREG_B0_P2_U0_CFG3 0x40010443u +#define CYREG_B0_P2_U0_CFG4 0x40010444u +#define CYREG_B0_P2_U0_CFG5 0x40010445u +#define CYREG_B0_P2_U0_CFG6 0x40010446u +#define CYREG_B0_P2_U0_CFG7 0x40010447u +#define CYREG_B0_P2_U0_CFG8 0x40010448u +#define CYREG_B0_P2_U0_CFG9 0x40010449u +#define CYREG_B0_P2_U0_CFG10 0x4001044au +#define CYREG_B0_P2_U0_CFG11 0x4001044bu +#define CYREG_B0_P2_U0_CFG12 0x4001044cu +#define CYREG_B0_P2_U0_CFG13 0x4001044du +#define CYREG_B0_P2_U0_CFG14 0x4001044eu +#define CYREG_B0_P2_U0_CFG15 0x4001044fu +#define CYREG_B0_P2_U0_CFG16 0x40010450u +#define CYREG_B0_P2_U0_CFG17 0x40010451u +#define CYREG_B0_P2_U0_CFG18 0x40010452u +#define CYREG_B0_P2_U0_CFG19 0x40010453u +#define CYREG_B0_P2_U0_CFG20 0x40010454u +#define CYREG_B0_P2_U0_CFG21 0x40010455u +#define CYREG_B0_P2_U0_CFG22 0x40010456u +#define CYREG_B0_P2_U0_CFG23 0x40010457u +#define CYREG_B0_P2_U0_CFG24 0x40010458u +#define CYREG_B0_P2_U0_CFG25 0x40010459u +#define CYREG_B0_P2_U0_CFG26 0x4001045au +#define CYREG_B0_P2_U0_CFG27 0x4001045bu +#define CYREG_B0_P2_U0_CFG28 0x4001045cu +#define CYREG_B0_P2_U0_CFG29 0x4001045du +#define CYREG_B0_P2_U0_CFG30 0x4001045eu +#define CYREG_B0_P2_U0_CFG31 0x4001045fu +#define CYREG_B0_P2_U0_DCFG0 0x40010460u +#define CYREG_B0_P2_U0_DCFG1 0x40010462u +#define CYREG_B0_P2_U0_DCFG2 0x40010464u +#define CYREG_B0_P2_U0_DCFG3 0x40010466u +#define CYREG_B0_P2_U0_DCFG4 0x40010468u +#define CYREG_B0_P2_U0_DCFG5 0x4001046au +#define CYREG_B0_P2_U0_DCFG6 0x4001046cu +#define CYREG_B0_P2_U0_DCFG7 0x4001046eu +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480u +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070u +#define CYREG_B0_P2_U1_PLD_IT0 0x40010480u +#define CYREG_B0_P2_U1_PLD_IT1 0x40010484u +#define CYREG_B0_P2_U1_PLD_IT2 0x40010488u +#define CYREG_B0_P2_U1_PLD_IT3 0x4001048cu +#define CYREG_B0_P2_U1_PLD_IT4 0x40010490u +#define CYREG_B0_P2_U1_PLD_IT5 0x40010494u +#define CYREG_B0_P2_U1_PLD_IT6 0x40010498u +#define CYREG_B0_P2_U1_PLD_IT7 0x4001049cu +#define CYREG_B0_P2_U1_PLD_IT8 0x400104a0u +#define CYREG_B0_P2_U1_PLD_IT9 0x400104a4u +#define CYREG_B0_P2_U1_PLD_IT10 0x400104a8u +#define CYREG_B0_P2_U1_PLD_IT11 0x400104acu +#define CYREG_B0_P2_U1_PLD_ORT0 0x400104b0u +#define CYREG_B0_P2_U1_PLD_ORT1 0x400104b2u +#define CYREG_B0_P2_U1_PLD_ORT2 0x400104b4u +#define CYREG_B0_P2_U1_PLD_ORT3 0x400104b6u +#define CYREG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8u +#define CYREG_B0_P2_U1_MC_CFG_XORFB 0x400104bau +#define CYREG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bcu +#define CYREG_B0_P2_U1_MC_CFG_BYPASS 0x400104beu +#define CYREG_B0_P2_U1_CFG0 0x400104c0u +#define CYREG_B0_P2_U1_CFG1 0x400104c1u +#define CYREG_B0_P2_U1_CFG2 0x400104c2u +#define CYREG_B0_P2_U1_CFG3 0x400104c3u +#define CYREG_B0_P2_U1_CFG4 0x400104c4u +#define CYREG_B0_P2_U1_CFG5 0x400104c5u +#define CYREG_B0_P2_U1_CFG6 0x400104c6u +#define CYREG_B0_P2_U1_CFG7 0x400104c7u +#define CYREG_B0_P2_U1_CFG8 0x400104c8u +#define CYREG_B0_P2_U1_CFG9 0x400104c9u +#define CYREG_B0_P2_U1_CFG10 0x400104cau +#define CYREG_B0_P2_U1_CFG11 0x400104cbu +#define CYREG_B0_P2_U1_CFG12 0x400104ccu +#define CYREG_B0_P2_U1_CFG13 0x400104cdu +#define CYREG_B0_P2_U1_CFG14 0x400104ceu +#define CYREG_B0_P2_U1_CFG15 0x400104cfu +#define CYREG_B0_P2_U1_CFG16 0x400104d0u +#define CYREG_B0_P2_U1_CFG17 0x400104d1u +#define CYREG_B0_P2_U1_CFG18 0x400104d2u +#define CYREG_B0_P2_U1_CFG19 0x400104d3u +#define CYREG_B0_P2_U1_CFG20 0x400104d4u +#define CYREG_B0_P2_U1_CFG21 0x400104d5u +#define CYREG_B0_P2_U1_CFG22 0x400104d6u +#define CYREG_B0_P2_U1_CFG23 0x400104d7u +#define CYREG_B0_P2_U1_CFG24 0x400104d8u +#define CYREG_B0_P2_U1_CFG25 0x400104d9u +#define CYREG_B0_P2_U1_CFG26 0x400104dau +#define CYREG_B0_P2_U1_CFG27 0x400104dbu +#define CYREG_B0_P2_U1_CFG28 0x400104dcu +#define CYREG_B0_P2_U1_CFG29 0x400104ddu +#define CYREG_B0_P2_U1_CFG30 0x400104deu +#define CYREG_B0_P2_U1_CFG31 0x400104dfu +#define CYREG_B0_P2_U1_DCFG0 0x400104e0u +#define CYREG_B0_P2_U1_DCFG1 0x400104e2u +#define CYREG_B0_P2_U1_DCFG2 0x400104e4u +#define CYREG_B0_P2_U1_DCFG3 0x400104e6u +#define CYREG_B0_P2_U1_DCFG4 0x400104e8u +#define CYREG_B0_P2_U1_DCFG5 0x400104eau +#define CYREG_B0_P2_U1_DCFG6 0x400104ecu +#define CYREG_B0_P2_U1_DCFG7 0x400104eeu +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500u +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P3_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070u +#define CYREG_B0_P3_U0_PLD_IT0 0x40010600u +#define CYREG_B0_P3_U0_PLD_IT1 0x40010604u +#define CYREG_B0_P3_U0_PLD_IT2 0x40010608u +#define CYREG_B0_P3_U0_PLD_IT3 0x4001060cu +#define CYREG_B0_P3_U0_PLD_IT4 0x40010610u +#define CYREG_B0_P3_U0_PLD_IT5 0x40010614u +#define CYREG_B0_P3_U0_PLD_IT6 0x40010618u +#define CYREG_B0_P3_U0_PLD_IT7 0x4001061cu +#define CYREG_B0_P3_U0_PLD_IT8 0x40010620u +#define CYREG_B0_P3_U0_PLD_IT9 0x40010624u +#define CYREG_B0_P3_U0_PLD_IT10 0x40010628u +#define CYREG_B0_P3_U0_PLD_IT11 0x4001062cu +#define CYREG_B0_P3_U0_PLD_ORT0 0x40010630u +#define CYREG_B0_P3_U0_PLD_ORT1 0x40010632u +#define CYREG_B0_P3_U0_PLD_ORT2 0x40010634u +#define CYREG_B0_P3_U0_PLD_ORT3 0x40010636u +#define CYREG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638u +#define CYREG_B0_P3_U0_MC_CFG_XORFB 0x4001063au +#define CYREG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063cu +#define CYREG_B0_P3_U0_MC_CFG_BYPASS 0x4001063eu +#define CYREG_B0_P3_U0_CFG0 0x40010640u +#define CYREG_B0_P3_U0_CFG1 0x40010641u +#define CYREG_B0_P3_U0_CFG2 0x40010642u +#define CYREG_B0_P3_U0_CFG3 0x40010643u +#define CYREG_B0_P3_U0_CFG4 0x40010644u +#define CYREG_B0_P3_U0_CFG5 0x40010645u +#define CYREG_B0_P3_U0_CFG6 0x40010646u +#define CYREG_B0_P3_U0_CFG7 0x40010647u +#define CYREG_B0_P3_U0_CFG8 0x40010648u +#define CYREG_B0_P3_U0_CFG9 0x40010649u +#define CYREG_B0_P3_U0_CFG10 0x4001064au +#define CYREG_B0_P3_U0_CFG11 0x4001064bu +#define CYREG_B0_P3_U0_CFG12 0x4001064cu +#define CYREG_B0_P3_U0_CFG13 0x4001064du +#define CYREG_B0_P3_U0_CFG14 0x4001064eu +#define CYREG_B0_P3_U0_CFG15 0x4001064fu +#define CYREG_B0_P3_U0_CFG16 0x40010650u +#define CYREG_B0_P3_U0_CFG17 0x40010651u +#define CYREG_B0_P3_U0_CFG18 0x40010652u +#define CYREG_B0_P3_U0_CFG19 0x40010653u +#define CYREG_B0_P3_U0_CFG20 0x40010654u +#define CYREG_B0_P3_U0_CFG21 0x40010655u +#define CYREG_B0_P3_U0_CFG22 0x40010656u +#define CYREG_B0_P3_U0_CFG23 0x40010657u +#define CYREG_B0_P3_U0_CFG24 0x40010658u +#define CYREG_B0_P3_U0_CFG25 0x40010659u +#define CYREG_B0_P3_U0_CFG26 0x4001065au +#define CYREG_B0_P3_U0_CFG27 0x4001065bu +#define CYREG_B0_P3_U0_CFG28 0x4001065cu +#define CYREG_B0_P3_U0_CFG29 0x4001065du +#define CYREG_B0_P3_U0_CFG30 0x4001065eu +#define CYREG_B0_P3_U0_CFG31 0x4001065fu +#define CYREG_B0_P3_U0_DCFG0 0x40010660u +#define CYREG_B0_P3_U0_DCFG1 0x40010662u +#define CYREG_B0_P3_U0_DCFG2 0x40010664u +#define CYREG_B0_P3_U0_DCFG3 0x40010666u +#define CYREG_B0_P3_U0_DCFG4 0x40010668u +#define CYREG_B0_P3_U0_DCFG5 0x4001066au +#define CYREG_B0_P3_U0_DCFG6 0x4001066cu +#define CYREG_B0_P3_U0_DCFG7 0x4001066eu +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680u +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070u +#define CYREG_B0_P3_U1_PLD_IT0 0x40010680u +#define CYREG_B0_P3_U1_PLD_IT1 0x40010684u +#define CYREG_B0_P3_U1_PLD_IT2 0x40010688u +#define CYREG_B0_P3_U1_PLD_IT3 0x4001068cu +#define CYREG_B0_P3_U1_PLD_IT4 0x40010690u +#define CYREG_B0_P3_U1_PLD_IT5 0x40010694u +#define CYREG_B0_P3_U1_PLD_IT6 0x40010698u +#define CYREG_B0_P3_U1_PLD_IT7 0x4001069cu +#define CYREG_B0_P3_U1_PLD_IT8 0x400106a0u +#define CYREG_B0_P3_U1_PLD_IT9 0x400106a4u +#define CYREG_B0_P3_U1_PLD_IT10 0x400106a8u +#define CYREG_B0_P3_U1_PLD_IT11 0x400106acu +#define CYREG_B0_P3_U1_PLD_ORT0 0x400106b0u +#define CYREG_B0_P3_U1_PLD_ORT1 0x400106b2u +#define CYREG_B0_P3_U1_PLD_ORT2 0x400106b4u +#define CYREG_B0_P3_U1_PLD_ORT3 0x400106b6u +#define CYREG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8u +#define CYREG_B0_P3_U1_MC_CFG_XORFB 0x400106bau +#define CYREG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bcu +#define CYREG_B0_P3_U1_MC_CFG_BYPASS 0x400106beu +#define CYREG_B0_P3_U1_CFG0 0x400106c0u +#define CYREG_B0_P3_U1_CFG1 0x400106c1u +#define CYREG_B0_P3_U1_CFG2 0x400106c2u +#define CYREG_B0_P3_U1_CFG3 0x400106c3u +#define CYREG_B0_P3_U1_CFG4 0x400106c4u +#define CYREG_B0_P3_U1_CFG5 0x400106c5u +#define CYREG_B0_P3_U1_CFG6 0x400106c6u +#define CYREG_B0_P3_U1_CFG7 0x400106c7u +#define CYREG_B0_P3_U1_CFG8 0x400106c8u +#define CYREG_B0_P3_U1_CFG9 0x400106c9u +#define CYREG_B0_P3_U1_CFG10 0x400106cau +#define CYREG_B0_P3_U1_CFG11 0x400106cbu +#define CYREG_B0_P3_U1_CFG12 0x400106ccu +#define CYREG_B0_P3_U1_CFG13 0x400106cdu +#define CYREG_B0_P3_U1_CFG14 0x400106ceu +#define CYREG_B0_P3_U1_CFG15 0x400106cfu +#define CYREG_B0_P3_U1_CFG16 0x400106d0u +#define CYREG_B0_P3_U1_CFG17 0x400106d1u +#define CYREG_B0_P3_U1_CFG18 0x400106d2u +#define CYREG_B0_P3_U1_CFG19 0x400106d3u +#define CYREG_B0_P3_U1_CFG20 0x400106d4u +#define CYREG_B0_P3_U1_CFG21 0x400106d5u +#define CYREG_B0_P3_U1_CFG22 0x400106d6u +#define CYREG_B0_P3_U1_CFG23 0x400106d7u +#define CYREG_B0_P3_U1_CFG24 0x400106d8u +#define CYREG_B0_P3_U1_CFG25 0x400106d9u +#define CYREG_B0_P3_U1_CFG26 0x400106dau +#define CYREG_B0_P3_U1_CFG27 0x400106dbu +#define CYREG_B0_P3_U1_CFG28 0x400106dcu +#define CYREG_B0_P3_U1_CFG29 0x400106ddu +#define CYREG_B0_P3_U1_CFG30 0x400106deu +#define CYREG_B0_P3_U1_CFG31 0x400106dfu +#define CYREG_B0_P3_U1_DCFG0 0x400106e0u +#define CYREG_B0_P3_U1_DCFG1 0x400106e2u +#define CYREG_B0_P3_U1_DCFG2 0x400106e4u +#define CYREG_B0_P3_U1_DCFG3 0x400106e6u +#define CYREG_B0_P3_U1_DCFG4 0x400106e8u +#define CYREG_B0_P3_U1_DCFG5 0x400106eau +#define CYREG_B0_P3_U1_DCFG6 0x400106ecu +#define CYREG_B0_P3_U1_DCFG7 0x400106eeu +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700u +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P4_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070u +#define CYREG_B0_P4_U0_PLD_IT0 0x40010800u +#define CYREG_B0_P4_U0_PLD_IT1 0x40010804u +#define CYREG_B0_P4_U0_PLD_IT2 0x40010808u +#define CYREG_B0_P4_U0_PLD_IT3 0x4001080cu +#define CYREG_B0_P4_U0_PLD_IT4 0x40010810u +#define CYREG_B0_P4_U0_PLD_IT5 0x40010814u +#define CYREG_B0_P4_U0_PLD_IT6 0x40010818u +#define CYREG_B0_P4_U0_PLD_IT7 0x4001081cu +#define CYREG_B0_P4_U0_PLD_IT8 0x40010820u +#define CYREG_B0_P4_U0_PLD_IT9 0x40010824u +#define CYREG_B0_P4_U0_PLD_IT10 0x40010828u +#define CYREG_B0_P4_U0_PLD_IT11 0x4001082cu +#define CYREG_B0_P4_U0_PLD_ORT0 0x40010830u +#define CYREG_B0_P4_U0_PLD_ORT1 0x40010832u +#define CYREG_B0_P4_U0_PLD_ORT2 0x40010834u +#define CYREG_B0_P4_U0_PLD_ORT3 0x40010836u +#define CYREG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838u +#define CYREG_B0_P4_U0_MC_CFG_XORFB 0x4001083au +#define CYREG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083cu +#define CYREG_B0_P4_U0_MC_CFG_BYPASS 0x4001083eu +#define CYREG_B0_P4_U0_CFG0 0x40010840u +#define CYREG_B0_P4_U0_CFG1 0x40010841u +#define CYREG_B0_P4_U0_CFG2 0x40010842u +#define CYREG_B0_P4_U0_CFG3 0x40010843u +#define CYREG_B0_P4_U0_CFG4 0x40010844u +#define CYREG_B0_P4_U0_CFG5 0x40010845u +#define CYREG_B0_P4_U0_CFG6 0x40010846u +#define CYREG_B0_P4_U0_CFG7 0x40010847u +#define CYREG_B0_P4_U0_CFG8 0x40010848u +#define CYREG_B0_P4_U0_CFG9 0x40010849u +#define CYREG_B0_P4_U0_CFG10 0x4001084au +#define CYREG_B0_P4_U0_CFG11 0x4001084bu +#define CYREG_B0_P4_U0_CFG12 0x4001084cu +#define CYREG_B0_P4_U0_CFG13 0x4001084du +#define CYREG_B0_P4_U0_CFG14 0x4001084eu +#define CYREG_B0_P4_U0_CFG15 0x4001084fu +#define CYREG_B0_P4_U0_CFG16 0x40010850u +#define CYREG_B0_P4_U0_CFG17 0x40010851u +#define CYREG_B0_P4_U0_CFG18 0x40010852u +#define CYREG_B0_P4_U0_CFG19 0x40010853u +#define CYREG_B0_P4_U0_CFG20 0x40010854u +#define CYREG_B0_P4_U0_CFG21 0x40010855u +#define CYREG_B0_P4_U0_CFG22 0x40010856u +#define CYREG_B0_P4_U0_CFG23 0x40010857u +#define CYREG_B0_P4_U0_CFG24 0x40010858u +#define CYREG_B0_P4_U0_CFG25 0x40010859u +#define CYREG_B0_P4_U0_CFG26 0x4001085au +#define CYREG_B0_P4_U0_CFG27 0x4001085bu +#define CYREG_B0_P4_U0_CFG28 0x4001085cu +#define CYREG_B0_P4_U0_CFG29 0x4001085du +#define CYREG_B0_P4_U0_CFG30 0x4001085eu +#define CYREG_B0_P4_U0_CFG31 0x4001085fu +#define CYREG_B0_P4_U0_DCFG0 0x40010860u +#define CYREG_B0_P4_U0_DCFG1 0x40010862u +#define CYREG_B0_P4_U0_DCFG2 0x40010864u +#define CYREG_B0_P4_U0_DCFG3 0x40010866u +#define CYREG_B0_P4_U0_DCFG4 0x40010868u +#define CYREG_B0_P4_U0_DCFG5 0x4001086au +#define CYREG_B0_P4_U0_DCFG6 0x4001086cu +#define CYREG_B0_P4_U0_DCFG7 0x4001086eu +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880u +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070u +#define CYREG_B0_P4_U1_PLD_IT0 0x40010880u +#define CYREG_B0_P4_U1_PLD_IT1 0x40010884u +#define CYREG_B0_P4_U1_PLD_IT2 0x40010888u +#define CYREG_B0_P4_U1_PLD_IT3 0x4001088cu +#define CYREG_B0_P4_U1_PLD_IT4 0x40010890u +#define CYREG_B0_P4_U1_PLD_IT5 0x40010894u +#define CYREG_B0_P4_U1_PLD_IT6 0x40010898u +#define CYREG_B0_P4_U1_PLD_IT7 0x4001089cu +#define CYREG_B0_P4_U1_PLD_IT8 0x400108a0u +#define CYREG_B0_P4_U1_PLD_IT9 0x400108a4u +#define CYREG_B0_P4_U1_PLD_IT10 0x400108a8u +#define CYREG_B0_P4_U1_PLD_IT11 0x400108acu +#define CYREG_B0_P4_U1_PLD_ORT0 0x400108b0u +#define CYREG_B0_P4_U1_PLD_ORT1 0x400108b2u +#define CYREG_B0_P4_U1_PLD_ORT2 0x400108b4u +#define CYREG_B0_P4_U1_PLD_ORT3 0x400108b6u +#define CYREG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8u +#define CYREG_B0_P4_U1_MC_CFG_XORFB 0x400108bau +#define CYREG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bcu +#define CYREG_B0_P4_U1_MC_CFG_BYPASS 0x400108beu +#define CYREG_B0_P4_U1_CFG0 0x400108c0u +#define CYREG_B0_P4_U1_CFG1 0x400108c1u +#define CYREG_B0_P4_U1_CFG2 0x400108c2u +#define CYREG_B0_P4_U1_CFG3 0x400108c3u +#define CYREG_B0_P4_U1_CFG4 0x400108c4u +#define CYREG_B0_P4_U1_CFG5 0x400108c5u +#define CYREG_B0_P4_U1_CFG6 0x400108c6u +#define CYREG_B0_P4_U1_CFG7 0x400108c7u +#define CYREG_B0_P4_U1_CFG8 0x400108c8u +#define CYREG_B0_P4_U1_CFG9 0x400108c9u +#define CYREG_B0_P4_U1_CFG10 0x400108cau +#define CYREG_B0_P4_U1_CFG11 0x400108cbu +#define CYREG_B0_P4_U1_CFG12 0x400108ccu +#define CYREG_B0_P4_U1_CFG13 0x400108cdu +#define CYREG_B0_P4_U1_CFG14 0x400108ceu +#define CYREG_B0_P4_U1_CFG15 0x400108cfu +#define CYREG_B0_P4_U1_CFG16 0x400108d0u +#define CYREG_B0_P4_U1_CFG17 0x400108d1u +#define CYREG_B0_P4_U1_CFG18 0x400108d2u +#define CYREG_B0_P4_U1_CFG19 0x400108d3u +#define CYREG_B0_P4_U1_CFG20 0x400108d4u +#define CYREG_B0_P4_U1_CFG21 0x400108d5u +#define CYREG_B0_P4_U1_CFG22 0x400108d6u +#define CYREG_B0_P4_U1_CFG23 0x400108d7u +#define CYREG_B0_P4_U1_CFG24 0x400108d8u +#define CYREG_B0_P4_U1_CFG25 0x400108d9u +#define CYREG_B0_P4_U1_CFG26 0x400108dau +#define CYREG_B0_P4_U1_CFG27 0x400108dbu +#define CYREG_B0_P4_U1_CFG28 0x400108dcu +#define CYREG_B0_P4_U1_CFG29 0x400108ddu +#define CYREG_B0_P4_U1_CFG30 0x400108deu +#define CYREG_B0_P4_U1_CFG31 0x400108dfu +#define CYREG_B0_P4_U1_DCFG0 0x400108e0u +#define CYREG_B0_P4_U1_DCFG1 0x400108e2u +#define CYREG_B0_P4_U1_DCFG2 0x400108e4u +#define CYREG_B0_P4_U1_DCFG3 0x400108e6u +#define CYREG_B0_P4_U1_DCFG4 0x400108e8u +#define CYREG_B0_P4_U1_DCFG5 0x400108eau +#define CYREG_B0_P4_U1_DCFG6 0x400108ecu +#define CYREG_B0_P4_U1_DCFG7 0x400108eeu +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900u +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070u +#define CYREG_B0_P5_U0_PLD_IT0 0x40010a00u +#define CYREG_B0_P5_U0_PLD_IT1 0x40010a04u +#define CYREG_B0_P5_U0_PLD_IT2 0x40010a08u +#define CYREG_B0_P5_U0_PLD_IT3 0x40010a0cu +#define CYREG_B0_P5_U0_PLD_IT4 0x40010a10u +#define CYREG_B0_P5_U0_PLD_IT5 0x40010a14u +#define CYREG_B0_P5_U0_PLD_IT6 0x40010a18u +#define CYREG_B0_P5_U0_PLD_IT7 0x40010a1cu +#define CYREG_B0_P5_U0_PLD_IT8 0x40010a20u +#define CYREG_B0_P5_U0_PLD_IT9 0x40010a24u +#define CYREG_B0_P5_U0_PLD_IT10 0x40010a28u +#define CYREG_B0_P5_U0_PLD_IT11 0x40010a2cu +#define CYREG_B0_P5_U0_PLD_ORT0 0x40010a30u +#define CYREG_B0_P5_U0_PLD_ORT1 0x40010a32u +#define CYREG_B0_P5_U0_PLD_ORT2 0x40010a34u +#define CYREG_B0_P5_U0_PLD_ORT3 0x40010a36u +#define CYREG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38u +#define CYREG_B0_P5_U0_MC_CFG_XORFB 0x40010a3au +#define CYREG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3cu +#define CYREG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3eu +#define CYREG_B0_P5_U0_CFG0 0x40010a40u +#define CYREG_B0_P5_U0_CFG1 0x40010a41u +#define CYREG_B0_P5_U0_CFG2 0x40010a42u +#define CYREG_B0_P5_U0_CFG3 0x40010a43u +#define CYREG_B0_P5_U0_CFG4 0x40010a44u +#define CYREG_B0_P5_U0_CFG5 0x40010a45u +#define CYREG_B0_P5_U0_CFG6 0x40010a46u +#define CYREG_B0_P5_U0_CFG7 0x40010a47u +#define CYREG_B0_P5_U0_CFG8 0x40010a48u +#define CYREG_B0_P5_U0_CFG9 0x40010a49u +#define CYREG_B0_P5_U0_CFG10 0x40010a4au +#define CYREG_B0_P5_U0_CFG11 0x40010a4bu +#define CYREG_B0_P5_U0_CFG12 0x40010a4cu +#define CYREG_B0_P5_U0_CFG13 0x40010a4du +#define CYREG_B0_P5_U0_CFG14 0x40010a4eu +#define CYREG_B0_P5_U0_CFG15 0x40010a4fu +#define CYREG_B0_P5_U0_CFG16 0x40010a50u +#define CYREG_B0_P5_U0_CFG17 0x40010a51u +#define CYREG_B0_P5_U0_CFG18 0x40010a52u +#define CYREG_B0_P5_U0_CFG19 0x40010a53u +#define CYREG_B0_P5_U0_CFG20 0x40010a54u +#define CYREG_B0_P5_U0_CFG21 0x40010a55u +#define CYREG_B0_P5_U0_CFG22 0x40010a56u +#define CYREG_B0_P5_U0_CFG23 0x40010a57u +#define CYREG_B0_P5_U0_CFG24 0x40010a58u +#define CYREG_B0_P5_U0_CFG25 0x40010a59u +#define CYREG_B0_P5_U0_CFG26 0x40010a5au +#define CYREG_B0_P5_U0_CFG27 0x40010a5bu +#define CYREG_B0_P5_U0_CFG28 0x40010a5cu +#define CYREG_B0_P5_U0_CFG29 0x40010a5du +#define CYREG_B0_P5_U0_CFG30 0x40010a5eu +#define CYREG_B0_P5_U0_CFG31 0x40010a5fu +#define CYREG_B0_P5_U0_DCFG0 0x40010a60u +#define CYREG_B0_P5_U0_DCFG1 0x40010a62u +#define CYREG_B0_P5_U0_DCFG2 0x40010a64u +#define CYREG_B0_P5_U0_DCFG3 0x40010a66u +#define CYREG_B0_P5_U0_DCFG4 0x40010a68u +#define CYREG_B0_P5_U0_DCFG5 0x40010a6au +#define CYREG_B0_P5_U0_DCFG6 0x40010a6cu +#define CYREG_B0_P5_U0_DCFG7 0x40010a6eu +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80u +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070u +#define CYREG_B0_P5_U1_PLD_IT0 0x40010a80u +#define CYREG_B0_P5_U1_PLD_IT1 0x40010a84u +#define CYREG_B0_P5_U1_PLD_IT2 0x40010a88u +#define CYREG_B0_P5_U1_PLD_IT3 0x40010a8cu +#define CYREG_B0_P5_U1_PLD_IT4 0x40010a90u +#define CYREG_B0_P5_U1_PLD_IT5 0x40010a94u +#define CYREG_B0_P5_U1_PLD_IT6 0x40010a98u +#define CYREG_B0_P5_U1_PLD_IT7 0x40010a9cu +#define CYREG_B0_P5_U1_PLD_IT8 0x40010aa0u +#define CYREG_B0_P5_U1_PLD_IT9 0x40010aa4u +#define CYREG_B0_P5_U1_PLD_IT10 0x40010aa8u +#define CYREG_B0_P5_U1_PLD_IT11 0x40010aacu +#define CYREG_B0_P5_U1_PLD_ORT0 0x40010ab0u +#define CYREG_B0_P5_U1_PLD_ORT1 0x40010ab2u +#define CYREG_B0_P5_U1_PLD_ORT2 0x40010ab4u +#define CYREG_B0_P5_U1_PLD_ORT3 0x40010ab6u +#define CYREG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8u +#define CYREG_B0_P5_U1_MC_CFG_XORFB 0x40010abau +#define CYREG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abcu +#define CYREG_B0_P5_U1_MC_CFG_BYPASS 0x40010abeu +#define CYREG_B0_P5_U1_CFG0 0x40010ac0u +#define CYREG_B0_P5_U1_CFG1 0x40010ac1u +#define CYREG_B0_P5_U1_CFG2 0x40010ac2u +#define CYREG_B0_P5_U1_CFG3 0x40010ac3u +#define CYREG_B0_P5_U1_CFG4 0x40010ac4u +#define CYREG_B0_P5_U1_CFG5 0x40010ac5u +#define CYREG_B0_P5_U1_CFG6 0x40010ac6u +#define CYREG_B0_P5_U1_CFG7 0x40010ac7u +#define CYREG_B0_P5_U1_CFG8 0x40010ac8u +#define CYREG_B0_P5_U1_CFG9 0x40010ac9u +#define CYREG_B0_P5_U1_CFG10 0x40010acau +#define CYREG_B0_P5_U1_CFG11 0x40010acbu +#define CYREG_B0_P5_U1_CFG12 0x40010accu +#define CYREG_B0_P5_U1_CFG13 0x40010acdu +#define CYREG_B0_P5_U1_CFG14 0x40010aceu +#define CYREG_B0_P5_U1_CFG15 0x40010acfu +#define CYREG_B0_P5_U1_CFG16 0x40010ad0u +#define CYREG_B0_P5_U1_CFG17 0x40010ad1u +#define CYREG_B0_P5_U1_CFG18 0x40010ad2u +#define CYREG_B0_P5_U1_CFG19 0x40010ad3u +#define CYREG_B0_P5_U1_CFG20 0x40010ad4u +#define CYREG_B0_P5_U1_CFG21 0x40010ad5u +#define CYREG_B0_P5_U1_CFG22 0x40010ad6u +#define CYREG_B0_P5_U1_CFG23 0x40010ad7u +#define CYREG_B0_P5_U1_CFG24 0x40010ad8u +#define CYREG_B0_P5_U1_CFG25 0x40010ad9u +#define CYREG_B0_P5_U1_CFG26 0x40010adau +#define CYREG_B0_P5_U1_CFG27 0x40010adbu +#define CYREG_B0_P5_U1_CFG28 0x40010adcu +#define CYREG_B0_P5_U1_CFG29 0x40010addu +#define CYREG_B0_P5_U1_CFG30 0x40010adeu +#define CYREG_B0_P5_U1_CFG31 0x40010adfu +#define CYREG_B0_P5_U1_DCFG0 0x40010ae0u +#define CYREG_B0_P5_U1_DCFG1 0x40010ae2u +#define CYREG_B0_P5_U1_DCFG2 0x40010ae4u +#define CYREG_B0_P5_U1_DCFG3 0x40010ae6u +#define CYREG_B0_P5_U1_DCFG4 0x40010ae8u +#define CYREG_B0_P5_U1_DCFG5 0x40010aeau +#define CYREG_B0_P5_U1_DCFG6 0x40010aecu +#define CYREG_B0_P5_U1_DCFG7 0x40010aeeu +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00u +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070u +#define CYREG_B0_P6_U0_PLD_IT0 0x40010c00u +#define CYREG_B0_P6_U0_PLD_IT1 0x40010c04u +#define CYREG_B0_P6_U0_PLD_IT2 0x40010c08u +#define CYREG_B0_P6_U0_PLD_IT3 0x40010c0cu +#define CYREG_B0_P6_U0_PLD_IT4 0x40010c10u +#define CYREG_B0_P6_U0_PLD_IT5 0x40010c14u +#define CYREG_B0_P6_U0_PLD_IT6 0x40010c18u +#define CYREG_B0_P6_U0_PLD_IT7 0x40010c1cu +#define CYREG_B0_P6_U0_PLD_IT8 0x40010c20u +#define CYREG_B0_P6_U0_PLD_IT9 0x40010c24u +#define CYREG_B0_P6_U0_PLD_IT10 0x40010c28u +#define CYREG_B0_P6_U0_PLD_IT11 0x40010c2cu +#define CYREG_B0_P6_U0_PLD_ORT0 0x40010c30u +#define CYREG_B0_P6_U0_PLD_ORT1 0x40010c32u +#define CYREG_B0_P6_U0_PLD_ORT2 0x40010c34u +#define CYREG_B0_P6_U0_PLD_ORT3 0x40010c36u +#define CYREG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38u +#define CYREG_B0_P6_U0_MC_CFG_XORFB 0x40010c3au +#define CYREG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3cu +#define CYREG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3eu +#define CYREG_B0_P6_U0_CFG0 0x40010c40u +#define CYREG_B0_P6_U0_CFG1 0x40010c41u +#define CYREG_B0_P6_U0_CFG2 0x40010c42u +#define CYREG_B0_P6_U0_CFG3 0x40010c43u +#define CYREG_B0_P6_U0_CFG4 0x40010c44u +#define CYREG_B0_P6_U0_CFG5 0x40010c45u +#define CYREG_B0_P6_U0_CFG6 0x40010c46u +#define CYREG_B0_P6_U0_CFG7 0x40010c47u +#define CYREG_B0_P6_U0_CFG8 0x40010c48u +#define CYREG_B0_P6_U0_CFG9 0x40010c49u +#define CYREG_B0_P6_U0_CFG10 0x40010c4au +#define CYREG_B0_P6_U0_CFG11 0x40010c4bu +#define CYREG_B0_P6_U0_CFG12 0x40010c4cu +#define CYREG_B0_P6_U0_CFG13 0x40010c4du +#define CYREG_B0_P6_U0_CFG14 0x40010c4eu +#define CYREG_B0_P6_U0_CFG15 0x40010c4fu +#define CYREG_B0_P6_U0_CFG16 0x40010c50u +#define CYREG_B0_P6_U0_CFG17 0x40010c51u +#define CYREG_B0_P6_U0_CFG18 0x40010c52u +#define CYREG_B0_P6_U0_CFG19 0x40010c53u +#define CYREG_B0_P6_U0_CFG20 0x40010c54u +#define CYREG_B0_P6_U0_CFG21 0x40010c55u +#define CYREG_B0_P6_U0_CFG22 0x40010c56u +#define CYREG_B0_P6_U0_CFG23 0x40010c57u +#define CYREG_B0_P6_U0_CFG24 0x40010c58u +#define CYREG_B0_P6_U0_CFG25 0x40010c59u +#define CYREG_B0_P6_U0_CFG26 0x40010c5au +#define CYREG_B0_P6_U0_CFG27 0x40010c5bu +#define CYREG_B0_P6_U0_CFG28 0x40010c5cu +#define CYREG_B0_P6_U0_CFG29 0x40010c5du +#define CYREG_B0_P6_U0_CFG30 0x40010c5eu +#define CYREG_B0_P6_U0_CFG31 0x40010c5fu +#define CYREG_B0_P6_U0_DCFG0 0x40010c60u +#define CYREG_B0_P6_U0_DCFG1 0x40010c62u +#define CYREG_B0_P6_U0_DCFG2 0x40010c64u +#define CYREG_B0_P6_U0_DCFG3 0x40010c66u +#define CYREG_B0_P6_U0_DCFG4 0x40010c68u +#define CYREG_B0_P6_U0_DCFG5 0x40010c6au +#define CYREG_B0_P6_U0_DCFG6 0x40010c6cu +#define CYREG_B0_P6_U0_DCFG7 0x40010c6eu +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80u +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070u +#define CYREG_B0_P6_U1_PLD_IT0 0x40010c80u +#define CYREG_B0_P6_U1_PLD_IT1 0x40010c84u +#define CYREG_B0_P6_U1_PLD_IT2 0x40010c88u +#define CYREG_B0_P6_U1_PLD_IT3 0x40010c8cu +#define CYREG_B0_P6_U1_PLD_IT4 0x40010c90u +#define CYREG_B0_P6_U1_PLD_IT5 0x40010c94u +#define CYREG_B0_P6_U1_PLD_IT6 0x40010c98u +#define CYREG_B0_P6_U1_PLD_IT7 0x40010c9cu +#define CYREG_B0_P6_U1_PLD_IT8 0x40010ca0u +#define CYREG_B0_P6_U1_PLD_IT9 0x40010ca4u +#define CYREG_B0_P6_U1_PLD_IT10 0x40010ca8u +#define CYREG_B0_P6_U1_PLD_IT11 0x40010cacu +#define CYREG_B0_P6_U1_PLD_ORT0 0x40010cb0u +#define CYREG_B0_P6_U1_PLD_ORT1 0x40010cb2u +#define CYREG_B0_P6_U1_PLD_ORT2 0x40010cb4u +#define CYREG_B0_P6_U1_PLD_ORT3 0x40010cb6u +#define CYREG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8u +#define CYREG_B0_P6_U1_MC_CFG_XORFB 0x40010cbau +#define CYREG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbcu +#define CYREG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbeu +#define CYREG_B0_P6_U1_CFG0 0x40010cc0u +#define CYREG_B0_P6_U1_CFG1 0x40010cc1u +#define CYREG_B0_P6_U1_CFG2 0x40010cc2u +#define CYREG_B0_P6_U1_CFG3 0x40010cc3u +#define CYREG_B0_P6_U1_CFG4 0x40010cc4u +#define CYREG_B0_P6_U1_CFG5 0x40010cc5u +#define CYREG_B0_P6_U1_CFG6 0x40010cc6u +#define CYREG_B0_P6_U1_CFG7 0x40010cc7u +#define CYREG_B0_P6_U1_CFG8 0x40010cc8u +#define CYREG_B0_P6_U1_CFG9 0x40010cc9u +#define CYREG_B0_P6_U1_CFG10 0x40010ccau +#define CYREG_B0_P6_U1_CFG11 0x40010ccbu +#define CYREG_B0_P6_U1_CFG12 0x40010cccu +#define CYREG_B0_P6_U1_CFG13 0x40010ccdu +#define CYREG_B0_P6_U1_CFG14 0x40010cceu +#define CYREG_B0_P6_U1_CFG15 0x40010ccfu +#define CYREG_B0_P6_U1_CFG16 0x40010cd0u +#define CYREG_B0_P6_U1_CFG17 0x40010cd1u +#define CYREG_B0_P6_U1_CFG18 0x40010cd2u +#define CYREG_B0_P6_U1_CFG19 0x40010cd3u +#define CYREG_B0_P6_U1_CFG20 0x40010cd4u +#define CYREG_B0_P6_U1_CFG21 0x40010cd5u +#define CYREG_B0_P6_U1_CFG22 0x40010cd6u +#define CYREG_B0_P6_U1_CFG23 0x40010cd7u +#define CYREG_B0_P6_U1_CFG24 0x40010cd8u +#define CYREG_B0_P6_U1_CFG25 0x40010cd9u +#define CYREG_B0_P6_U1_CFG26 0x40010cdau +#define CYREG_B0_P6_U1_CFG27 0x40010cdbu +#define CYREG_B0_P6_U1_CFG28 0x40010cdcu +#define CYREG_B0_P6_U1_CFG29 0x40010cddu +#define CYREG_B0_P6_U1_CFG30 0x40010cdeu +#define CYREG_B0_P6_U1_CFG31 0x40010cdfu +#define CYREG_B0_P6_U1_DCFG0 0x40010ce0u +#define CYREG_B0_P6_U1_DCFG1 0x40010ce2u +#define CYREG_B0_P6_U1_DCFG2 0x40010ce4u +#define CYREG_B0_P6_U1_DCFG3 0x40010ce6u +#define CYREG_B0_P6_U1_DCFG4 0x40010ce8u +#define CYREG_B0_P6_U1_DCFG5 0x40010ceau +#define CYREG_B0_P6_U1_DCFG6 0x40010cecu +#define CYREG_B0_P6_U1_DCFG7 0x40010ceeu +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00u +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070u +#define CYREG_B0_P7_U0_PLD_IT0 0x40010e00u +#define CYREG_B0_P7_U0_PLD_IT1 0x40010e04u +#define CYREG_B0_P7_U0_PLD_IT2 0x40010e08u +#define CYREG_B0_P7_U0_PLD_IT3 0x40010e0cu +#define CYREG_B0_P7_U0_PLD_IT4 0x40010e10u +#define CYREG_B0_P7_U0_PLD_IT5 0x40010e14u +#define CYREG_B0_P7_U0_PLD_IT6 0x40010e18u +#define CYREG_B0_P7_U0_PLD_IT7 0x40010e1cu +#define CYREG_B0_P7_U0_PLD_IT8 0x40010e20u +#define CYREG_B0_P7_U0_PLD_IT9 0x40010e24u +#define CYREG_B0_P7_U0_PLD_IT10 0x40010e28u +#define CYREG_B0_P7_U0_PLD_IT11 0x40010e2cu +#define CYREG_B0_P7_U0_PLD_ORT0 0x40010e30u +#define CYREG_B0_P7_U0_PLD_ORT1 0x40010e32u +#define CYREG_B0_P7_U0_PLD_ORT2 0x40010e34u +#define CYREG_B0_P7_U0_PLD_ORT3 0x40010e36u +#define CYREG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38u +#define CYREG_B0_P7_U0_MC_CFG_XORFB 0x40010e3au +#define CYREG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3cu +#define CYREG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3eu +#define CYREG_B0_P7_U0_CFG0 0x40010e40u +#define CYREG_B0_P7_U0_CFG1 0x40010e41u +#define CYREG_B0_P7_U0_CFG2 0x40010e42u +#define CYREG_B0_P7_U0_CFG3 0x40010e43u +#define CYREG_B0_P7_U0_CFG4 0x40010e44u +#define CYREG_B0_P7_U0_CFG5 0x40010e45u +#define CYREG_B0_P7_U0_CFG6 0x40010e46u +#define CYREG_B0_P7_U0_CFG7 0x40010e47u +#define CYREG_B0_P7_U0_CFG8 0x40010e48u +#define CYREG_B0_P7_U0_CFG9 0x40010e49u +#define CYREG_B0_P7_U0_CFG10 0x40010e4au +#define CYREG_B0_P7_U0_CFG11 0x40010e4bu +#define CYREG_B0_P7_U0_CFG12 0x40010e4cu +#define CYREG_B0_P7_U0_CFG13 0x40010e4du +#define CYREG_B0_P7_U0_CFG14 0x40010e4eu +#define CYREG_B0_P7_U0_CFG15 0x40010e4fu +#define CYREG_B0_P7_U0_CFG16 0x40010e50u +#define CYREG_B0_P7_U0_CFG17 0x40010e51u +#define CYREG_B0_P7_U0_CFG18 0x40010e52u +#define CYREG_B0_P7_U0_CFG19 0x40010e53u +#define CYREG_B0_P7_U0_CFG20 0x40010e54u +#define CYREG_B0_P7_U0_CFG21 0x40010e55u +#define CYREG_B0_P7_U0_CFG22 0x40010e56u +#define CYREG_B0_P7_U0_CFG23 0x40010e57u +#define CYREG_B0_P7_U0_CFG24 0x40010e58u +#define CYREG_B0_P7_U0_CFG25 0x40010e59u +#define CYREG_B0_P7_U0_CFG26 0x40010e5au +#define CYREG_B0_P7_U0_CFG27 0x40010e5bu +#define CYREG_B0_P7_U0_CFG28 0x40010e5cu +#define CYREG_B0_P7_U0_CFG29 0x40010e5du +#define CYREG_B0_P7_U0_CFG30 0x40010e5eu +#define CYREG_B0_P7_U0_CFG31 0x40010e5fu +#define CYREG_B0_P7_U0_DCFG0 0x40010e60u +#define CYREG_B0_P7_U0_DCFG1 0x40010e62u +#define CYREG_B0_P7_U0_DCFG2 0x40010e64u +#define CYREG_B0_P7_U0_DCFG3 0x40010e66u +#define CYREG_B0_P7_U0_DCFG4 0x40010e68u +#define CYREG_B0_P7_U0_DCFG5 0x40010e6au +#define CYREG_B0_P7_U0_DCFG6 0x40010e6cu +#define CYREG_B0_P7_U0_DCFG7 0x40010e6eu +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80u +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070u +#define CYREG_B0_P7_U1_PLD_IT0 0x40010e80u +#define CYREG_B0_P7_U1_PLD_IT1 0x40010e84u +#define CYREG_B0_P7_U1_PLD_IT2 0x40010e88u +#define CYREG_B0_P7_U1_PLD_IT3 0x40010e8cu +#define CYREG_B0_P7_U1_PLD_IT4 0x40010e90u +#define CYREG_B0_P7_U1_PLD_IT5 0x40010e94u +#define CYREG_B0_P7_U1_PLD_IT6 0x40010e98u +#define CYREG_B0_P7_U1_PLD_IT7 0x40010e9cu +#define CYREG_B0_P7_U1_PLD_IT8 0x40010ea0u +#define CYREG_B0_P7_U1_PLD_IT9 0x40010ea4u +#define CYREG_B0_P7_U1_PLD_IT10 0x40010ea8u +#define CYREG_B0_P7_U1_PLD_IT11 0x40010eacu +#define CYREG_B0_P7_U1_PLD_ORT0 0x40010eb0u +#define CYREG_B0_P7_U1_PLD_ORT1 0x40010eb2u +#define CYREG_B0_P7_U1_PLD_ORT2 0x40010eb4u +#define CYREG_B0_P7_U1_PLD_ORT3 0x40010eb6u +#define CYREG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8u +#define CYREG_B0_P7_U1_MC_CFG_XORFB 0x40010ebau +#define CYREG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebcu +#define CYREG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebeu +#define CYREG_B0_P7_U1_CFG0 0x40010ec0u +#define CYREG_B0_P7_U1_CFG1 0x40010ec1u +#define CYREG_B0_P7_U1_CFG2 0x40010ec2u +#define CYREG_B0_P7_U1_CFG3 0x40010ec3u +#define CYREG_B0_P7_U1_CFG4 0x40010ec4u +#define CYREG_B0_P7_U1_CFG5 0x40010ec5u +#define CYREG_B0_P7_U1_CFG6 0x40010ec6u +#define CYREG_B0_P7_U1_CFG7 0x40010ec7u +#define CYREG_B0_P7_U1_CFG8 0x40010ec8u +#define CYREG_B0_P7_U1_CFG9 0x40010ec9u +#define CYREG_B0_P7_U1_CFG10 0x40010ecau +#define CYREG_B0_P7_U1_CFG11 0x40010ecbu +#define CYREG_B0_P7_U1_CFG12 0x40010eccu +#define CYREG_B0_P7_U1_CFG13 0x40010ecdu +#define CYREG_B0_P7_U1_CFG14 0x40010eceu +#define CYREG_B0_P7_U1_CFG15 0x40010ecfu +#define CYREG_B0_P7_U1_CFG16 0x40010ed0u +#define CYREG_B0_P7_U1_CFG17 0x40010ed1u +#define CYREG_B0_P7_U1_CFG18 0x40010ed2u +#define CYREG_B0_P7_U1_CFG19 0x40010ed3u +#define CYREG_B0_P7_U1_CFG20 0x40010ed4u +#define CYREG_B0_P7_U1_CFG21 0x40010ed5u +#define CYREG_B0_P7_U1_CFG22 0x40010ed6u +#define CYREG_B0_P7_U1_CFG23 0x40010ed7u +#define CYREG_B0_P7_U1_CFG24 0x40010ed8u +#define CYREG_B0_P7_U1_CFG25 0x40010ed9u +#define CYREG_B0_P7_U1_CFG26 0x40010edau +#define CYREG_B0_P7_U1_CFG27 0x40010edbu +#define CYREG_B0_P7_U1_CFG28 0x40010edcu +#define CYREG_B0_P7_U1_CFG29 0x40010eddu +#define CYREG_B0_P7_U1_CFG30 0x40010edeu +#define CYREG_B0_P7_U1_CFG31 0x40010edfu +#define CYREG_B0_P7_U1_DCFG0 0x40010ee0u +#define CYREG_B0_P7_U1_DCFG1 0x40010ee2u +#define CYREG_B0_P7_U1_DCFG2 0x40010ee4u +#define CYREG_B0_P7_U1_DCFG3 0x40010ee6u +#define CYREG_B0_P7_U1_DCFG4 0x40010ee8u +#define CYREG_B0_P7_U1_DCFG5 0x40010eeau +#define CYREG_B0_P7_U1_DCFG6 0x40010eecu +#define CYREG_B0_P7_U1_DCFG7 0x40010eeeu +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00u +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_BASE 0x40011000u +#define CYDEV_UCFG_B1_SIZE 0x00000fefu +#define CYDEV_UCFG_B1_P2_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070u +#define CYREG_B1_P2_U0_PLD_IT0 0x40011400u +#define CYREG_B1_P2_U0_PLD_IT1 0x40011404u +#define CYREG_B1_P2_U0_PLD_IT2 0x40011408u +#define CYREG_B1_P2_U0_PLD_IT3 0x4001140cu +#define CYREG_B1_P2_U0_PLD_IT4 0x40011410u +#define CYREG_B1_P2_U0_PLD_IT5 0x40011414u +#define CYREG_B1_P2_U0_PLD_IT6 0x40011418u +#define CYREG_B1_P2_U0_PLD_IT7 0x4001141cu +#define CYREG_B1_P2_U0_PLD_IT8 0x40011420u +#define CYREG_B1_P2_U0_PLD_IT9 0x40011424u +#define CYREG_B1_P2_U0_PLD_IT10 0x40011428u +#define CYREG_B1_P2_U0_PLD_IT11 0x4001142cu +#define CYREG_B1_P2_U0_PLD_ORT0 0x40011430u +#define CYREG_B1_P2_U0_PLD_ORT1 0x40011432u +#define CYREG_B1_P2_U0_PLD_ORT2 0x40011434u +#define CYREG_B1_P2_U0_PLD_ORT3 0x40011436u +#define CYREG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438u +#define CYREG_B1_P2_U0_MC_CFG_XORFB 0x4001143au +#define CYREG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143cu +#define CYREG_B1_P2_U0_MC_CFG_BYPASS 0x4001143eu +#define CYREG_B1_P2_U0_CFG0 0x40011440u +#define CYREG_B1_P2_U0_CFG1 0x40011441u +#define CYREG_B1_P2_U0_CFG2 0x40011442u +#define CYREG_B1_P2_U0_CFG3 0x40011443u +#define CYREG_B1_P2_U0_CFG4 0x40011444u +#define CYREG_B1_P2_U0_CFG5 0x40011445u +#define CYREG_B1_P2_U0_CFG6 0x40011446u +#define CYREG_B1_P2_U0_CFG7 0x40011447u +#define CYREG_B1_P2_U0_CFG8 0x40011448u +#define CYREG_B1_P2_U0_CFG9 0x40011449u +#define CYREG_B1_P2_U0_CFG10 0x4001144au +#define CYREG_B1_P2_U0_CFG11 0x4001144bu +#define CYREG_B1_P2_U0_CFG12 0x4001144cu +#define CYREG_B1_P2_U0_CFG13 0x4001144du +#define CYREG_B1_P2_U0_CFG14 0x4001144eu +#define CYREG_B1_P2_U0_CFG15 0x4001144fu +#define CYREG_B1_P2_U0_CFG16 0x40011450u +#define CYREG_B1_P2_U0_CFG17 0x40011451u +#define CYREG_B1_P2_U0_CFG18 0x40011452u +#define CYREG_B1_P2_U0_CFG19 0x40011453u +#define CYREG_B1_P2_U0_CFG20 0x40011454u +#define CYREG_B1_P2_U0_CFG21 0x40011455u +#define CYREG_B1_P2_U0_CFG22 0x40011456u +#define CYREG_B1_P2_U0_CFG23 0x40011457u +#define CYREG_B1_P2_U0_CFG24 0x40011458u +#define CYREG_B1_P2_U0_CFG25 0x40011459u +#define CYREG_B1_P2_U0_CFG26 0x4001145au +#define CYREG_B1_P2_U0_CFG27 0x4001145bu +#define CYREG_B1_P2_U0_CFG28 0x4001145cu +#define CYREG_B1_P2_U0_CFG29 0x4001145du +#define CYREG_B1_P2_U0_CFG30 0x4001145eu +#define CYREG_B1_P2_U0_CFG31 0x4001145fu +#define CYREG_B1_P2_U0_DCFG0 0x40011460u +#define CYREG_B1_P2_U0_DCFG1 0x40011462u +#define CYREG_B1_P2_U0_DCFG2 0x40011464u +#define CYREG_B1_P2_U0_DCFG3 0x40011466u +#define CYREG_B1_P2_U0_DCFG4 0x40011468u +#define CYREG_B1_P2_U0_DCFG5 0x4001146au +#define CYREG_B1_P2_U0_DCFG6 0x4001146cu +#define CYREG_B1_P2_U0_DCFG7 0x4001146eu +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480u +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070u +#define CYREG_B1_P2_U1_PLD_IT0 0x40011480u +#define CYREG_B1_P2_U1_PLD_IT1 0x40011484u +#define CYREG_B1_P2_U1_PLD_IT2 0x40011488u +#define CYREG_B1_P2_U1_PLD_IT3 0x4001148cu +#define CYREG_B1_P2_U1_PLD_IT4 0x40011490u +#define CYREG_B1_P2_U1_PLD_IT5 0x40011494u +#define CYREG_B1_P2_U1_PLD_IT6 0x40011498u +#define CYREG_B1_P2_U1_PLD_IT7 0x4001149cu +#define CYREG_B1_P2_U1_PLD_IT8 0x400114a0u +#define CYREG_B1_P2_U1_PLD_IT9 0x400114a4u +#define CYREG_B1_P2_U1_PLD_IT10 0x400114a8u +#define CYREG_B1_P2_U1_PLD_IT11 0x400114acu +#define CYREG_B1_P2_U1_PLD_ORT0 0x400114b0u +#define CYREG_B1_P2_U1_PLD_ORT1 0x400114b2u +#define CYREG_B1_P2_U1_PLD_ORT2 0x400114b4u +#define CYREG_B1_P2_U1_PLD_ORT3 0x400114b6u +#define CYREG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8u +#define CYREG_B1_P2_U1_MC_CFG_XORFB 0x400114bau +#define CYREG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bcu +#define CYREG_B1_P2_U1_MC_CFG_BYPASS 0x400114beu +#define CYREG_B1_P2_U1_CFG0 0x400114c0u +#define CYREG_B1_P2_U1_CFG1 0x400114c1u +#define CYREG_B1_P2_U1_CFG2 0x400114c2u +#define CYREG_B1_P2_U1_CFG3 0x400114c3u +#define CYREG_B1_P2_U1_CFG4 0x400114c4u +#define CYREG_B1_P2_U1_CFG5 0x400114c5u +#define CYREG_B1_P2_U1_CFG6 0x400114c6u +#define CYREG_B1_P2_U1_CFG7 0x400114c7u +#define CYREG_B1_P2_U1_CFG8 0x400114c8u +#define CYREG_B1_P2_U1_CFG9 0x400114c9u +#define CYREG_B1_P2_U1_CFG10 0x400114cau +#define CYREG_B1_P2_U1_CFG11 0x400114cbu +#define CYREG_B1_P2_U1_CFG12 0x400114ccu +#define CYREG_B1_P2_U1_CFG13 0x400114cdu +#define CYREG_B1_P2_U1_CFG14 0x400114ceu +#define CYREG_B1_P2_U1_CFG15 0x400114cfu +#define CYREG_B1_P2_U1_CFG16 0x400114d0u +#define CYREG_B1_P2_U1_CFG17 0x400114d1u +#define CYREG_B1_P2_U1_CFG18 0x400114d2u +#define CYREG_B1_P2_U1_CFG19 0x400114d3u +#define CYREG_B1_P2_U1_CFG20 0x400114d4u +#define CYREG_B1_P2_U1_CFG21 0x400114d5u +#define CYREG_B1_P2_U1_CFG22 0x400114d6u +#define CYREG_B1_P2_U1_CFG23 0x400114d7u +#define CYREG_B1_P2_U1_CFG24 0x400114d8u +#define CYREG_B1_P2_U1_CFG25 0x400114d9u +#define CYREG_B1_P2_U1_CFG26 0x400114dau +#define CYREG_B1_P2_U1_CFG27 0x400114dbu +#define CYREG_B1_P2_U1_CFG28 0x400114dcu +#define CYREG_B1_P2_U1_CFG29 0x400114ddu +#define CYREG_B1_P2_U1_CFG30 0x400114deu +#define CYREG_B1_P2_U1_CFG31 0x400114dfu +#define CYREG_B1_P2_U1_DCFG0 0x400114e0u +#define CYREG_B1_P2_U1_DCFG1 0x400114e2u +#define CYREG_B1_P2_U1_DCFG2 0x400114e4u +#define CYREG_B1_P2_U1_DCFG3 0x400114e6u +#define CYREG_B1_P2_U1_DCFG4 0x400114e8u +#define CYREG_B1_P2_U1_DCFG5 0x400114eau +#define CYREG_B1_P2_U1_DCFG6 0x400114ecu +#define CYREG_B1_P2_U1_DCFG7 0x400114eeu +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500u +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P3_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070u +#define CYREG_B1_P3_U0_PLD_IT0 0x40011600u +#define CYREG_B1_P3_U0_PLD_IT1 0x40011604u +#define CYREG_B1_P3_U0_PLD_IT2 0x40011608u +#define CYREG_B1_P3_U0_PLD_IT3 0x4001160cu +#define CYREG_B1_P3_U0_PLD_IT4 0x40011610u +#define CYREG_B1_P3_U0_PLD_IT5 0x40011614u +#define CYREG_B1_P3_U0_PLD_IT6 0x40011618u +#define CYREG_B1_P3_U0_PLD_IT7 0x4001161cu +#define CYREG_B1_P3_U0_PLD_IT8 0x40011620u +#define CYREG_B1_P3_U0_PLD_IT9 0x40011624u +#define CYREG_B1_P3_U0_PLD_IT10 0x40011628u +#define CYREG_B1_P3_U0_PLD_IT11 0x4001162cu +#define CYREG_B1_P3_U0_PLD_ORT0 0x40011630u +#define CYREG_B1_P3_U0_PLD_ORT1 0x40011632u +#define CYREG_B1_P3_U0_PLD_ORT2 0x40011634u +#define CYREG_B1_P3_U0_PLD_ORT3 0x40011636u +#define CYREG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638u +#define CYREG_B1_P3_U0_MC_CFG_XORFB 0x4001163au +#define CYREG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163cu +#define CYREG_B1_P3_U0_MC_CFG_BYPASS 0x4001163eu +#define CYREG_B1_P3_U0_CFG0 0x40011640u +#define CYREG_B1_P3_U0_CFG1 0x40011641u +#define CYREG_B1_P3_U0_CFG2 0x40011642u +#define CYREG_B1_P3_U0_CFG3 0x40011643u +#define CYREG_B1_P3_U0_CFG4 0x40011644u +#define CYREG_B1_P3_U0_CFG5 0x40011645u +#define CYREG_B1_P3_U0_CFG6 0x40011646u +#define CYREG_B1_P3_U0_CFG7 0x40011647u +#define CYREG_B1_P3_U0_CFG8 0x40011648u +#define CYREG_B1_P3_U0_CFG9 0x40011649u +#define CYREG_B1_P3_U0_CFG10 0x4001164au +#define CYREG_B1_P3_U0_CFG11 0x4001164bu +#define CYREG_B1_P3_U0_CFG12 0x4001164cu +#define CYREG_B1_P3_U0_CFG13 0x4001164du +#define CYREG_B1_P3_U0_CFG14 0x4001164eu +#define CYREG_B1_P3_U0_CFG15 0x4001164fu +#define CYREG_B1_P3_U0_CFG16 0x40011650u +#define CYREG_B1_P3_U0_CFG17 0x40011651u +#define CYREG_B1_P3_U0_CFG18 0x40011652u +#define CYREG_B1_P3_U0_CFG19 0x40011653u +#define CYREG_B1_P3_U0_CFG20 0x40011654u +#define CYREG_B1_P3_U0_CFG21 0x40011655u +#define CYREG_B1_P3_U0_CFG22 0x40011656u +#define CYREG_B1_P3_U0_CFG23 0x40011657u +#define CYREG_B1_P3_U0_CFG24 0x40011658u +#define CYREG_B1_P3_U0_CFG25 0x40011659u +#define CYREG_B1_P3_U0_CFG26 0x4001165au +#define CYREG_B1_P3_U0_CFG27 0x4001165bu +#define CYREG_B1_P3_U0_CFG28 0x4001165cu +#define CYREG_B1_P3_U0_CFG29 0x4001165du +#define CYREG_B1_P3_U0_CFG30 0x4001165eu +#define CYREG_B1_P3_U0_CFG31 0x4001165fu +#define CYREG_B1_P3_U0_DCFG0 0x40011660u +#define CYREG_B1_P3_U0_DCFG1 0x40011662u +#define CYREG_B1_P3_U0_DCFG2 0x40011664u +#define CYREG_B1_P3_U0_DCFG3 0x40011666u +#define CYREG_B1_P3_U0_DCFG4 0x40011668u +#define CYREG_B1_P3_U0_DCFG5 0x4001166au +#define CYREG_B1_P3_U0_DCFG6 0x4001166cu +#define CYREG_B1_P3_U0_DCFG7 0x4001166eu +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680u +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070u +#define CYREG_B1_P3_U1_PLD_IT0 0x40011680u +#define CYREG_B1_P3_U1_PLD_IT1 0x40011684u +#define CYREG_B1_P3_U1_PLD_IT2 0x40011688u +#define CYREG_B1_P3_U1_PLD_IT3 0x4001168cu +#define CYREG_B1_P3_U1_PLD_IT4 0x40011690u +#define CYREG_B1_P3_U1_PLD_IT5 0x40011694u +#define CYREG_B1_P3_U1_PLD_IT6 0x40011698u +#define CYREG_B1_P3_U1_PLD_IT7 0x4001169cu +#define CYREG_B1_P3_U1_PLD_IT8 0x400116a0u +#define CYREG_B1_P3_U1_PLD_IT9 0x400116a4u +#define CYREG_B1_P3_U1_PLD_IT10 0x400116a8u +#define CYREG_B1_P3_U1_PLD_IT11 0x400116acu +#define CYREG_B1_P3_U1_PLD_ORT0 0x400116b0u +#define CYREG_B1_P3_U1_PLD_ORT1 0x400116b2u +#define CYREG_B1_P3_U1_PLD_ORT2 0x400116b4u +#define CYREG_B1_P3_U1_PLD_ORT3 0x400116b6u +#define CYREG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8u +#define CYREG_B1_P3_U1_MC_CFG_XORFB 0x400116bau +#define CYREG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bcu +#define CYREG_B1_P3_U1_MC_CFG_BYPASS 0x400116beu +#define CYREG_B1_P3_U1_CFG0 0x400116c0u +#define CYREG_B1_P3_U1_CFG1 0x400116c1u +#define CYREG_B1_P3_U1_CFG2 0x400116c2u +#define CYREG_B1_P3_U1_CFG3 0x400116c3u +#define CYREG_B1_P3_U1_CFG4 0x400116c4u +#define CYREG_B1_P3_U1_CFG5 0x400116c5u +#define CYREG_B1_P3_U1_CFG6 0x400116c6u +#define CYREG_B1_P3_U1_CFG7 0x400116c7u +#define CYREG_B1_P3_U1_CFG8 0x400116c8u +#define CYREG_B1_P3_U1_CFG9 0x400116c9u +#define CYREG_B1_P3_U1_CFG10 0x400116cau +#define CYREG_B1_P3_U1_CFG11 0x400116cbu +#define CYREG_B1_P3_U1_CFG12 0x400116ccu +#define CYREG_B1_P3_U1_CFG13 0x400116cdu +#define CYREG_B1_P3_U1_CFG14 0x400116ceu +#define CYREG_B1_P3_U1_CFG15 0x400116cfu +#define CYREG_B1_P3_U1_CFG16 0x400116d0u +#define CYREG_B1_P3_U1_CFG17 0x400116d1u +#define CYREG_B1_P3_U1_CFG18 0x400116d2u +#define CYREG_B1_P3_U1_CFG19 0x400116d3u +#define CYREG_B1_P3_U1_CFG20 0x400116d4u +#define CYREG_B1_P3_U1_CFG21 0x400116d5u +#define CYREG_B1_P3_U1_CFG22 0x400116d6u +#define CYREG_B1_P3_U1_CFG23 0x400116d7u +#define CYREG_B1_P3_U1_CFG24 0x400116d8u +#define CYREG_B1_P3_U1_CFG25 0x400116d9u +#define CYREG_B1_P3_U1_CFG26 0x400116dau +#define CYREG_B1_P3_U1_CFG27 0x400116dbu +#define CYREG_B1_P3_U1_CFG28 0x400116dcu +#define CYREG_B1_P3_U1_CFG29 0x400116ddu +#define CYREG_B1_P3_U1_CFG30 0x400116deu +#define CYREG_B1_P3_U1_CFG31 0x400116dfu +#define CYREG_B1_P3_U1_DCFG0 0x400116e0u +#define CYREG_B1_P3_U1_DCFG1 0x400116e2u +#define CYREG_B1_P3_U1_DCFG2 0x400116e4u +#define CYREG_B1_P3_U1_DCFG3 0x400116e6u +#define CYREG_B1_P3_U1_DCFG4 0x400116e8u +#define CYREG_B1_P3_U1_DCFG5 0x400116eau +#define CYREG_B1_P3_U1_DCFG6 0x400116ecu +#define CYREG_B1_P3_U1_DCFG7 0x400116eeu +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700u +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P4_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070u +#define CYREG_B1_P4_U0_PLD_IT0 0x40011800u +#define CYREG_B1_P4_U0_PLD_IT1 0x40011804u +#define CYREG_B1_P4_U0_PLD_IT2 0x40011808u +#define CYREG_B1_P4_U0_PLD_IT3 0x4001180cu +#define CYREG_B1_P4_U0_PLD_IT4 0x40011810u +#define CYREG_B1_P4_U0_PLD_IT5 0x40011814u +#define CYREG_B1_P4_U0_PLD_IT6 0x40011818u +#define CYREG_B1_P4_U0_PLD_IT7 0x4001181cu +#define CYREG_B1_P4_U0_PLD_IT8 0x40011820u +#define CYREG_B1_P4_U0_PLD_IT9 0x40011824u +#define CYREG_B1_P4_U0_PLD_IT10 0x40011828u +#define CYREG_B1_P4_U0_PLD_IT11 0x4001182cu +#define CYREG_B1_P4_U0_PLD_ORT0 0x40011830u +#define CYREG_B1_P4_U0_PLD_ORT1 0x40011832u +#define CYREG_B1_P4_U0_PLD_ORT2 0x40011834u +#define CYREG_B1_P4_U0_PLD_ORT3 0x40011836u +#define CYREG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838u +#define CYREG_B1_P4_U0_MC_CFG_XORFB 0x4001183au +#define CYREG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183cu +#define CYREG_B1_P4_U0_MC_CFG_BYPASS 0x4001183eu +#define CYREG_B1_P4_U0_CFG0 0x40011840u +#define CYREG_B1_P4_U0_CFG1 0x40011841u +#define CYREG_B1_P4_U0_CFG2 0x40011842u +#define CYREG_B1_P4_U0_CFG3 0x40011843u +#define CYREG_B1_P4_U0_CFG4 0x40011844u +#define CYREG_B1_P4_U0_CFG5 0x40011845u +#define CYREG_B1_P4_U0_CFG6 0x40011846u +#define CYREG_B1_P4_U0_CFG7 0x40011847u +#define CYREG_B1_P4_U0_CFG8 0x40011848u +#define CYREG_B1_P4_U0_CFG9 0x40011849u +#define CYREG_B1_P4_U0_CFG10 0x4001184au +#define CYREG_B1_P4_U0_CFG11 0x4001184bu +#define CYREG_B1_P4_U0_CFG12 0x4001184cu +#define CYREG_B1_P4_U0_CFG13 0x4001184du +#define CYREG_B1_P4_U0_CFG14 0x4001184eu +#define CYREG_B1_P4_U0_CFG15 0x4001184fu +#define CYREG_B1_P4_U0_CFG16 0x40011850u +#define CYREG_B1_P4_U0_CFG17 0x40011851u +#define CYREG_B1_P4_U0_CFG18 0x40011852u +#define CYREG_B1_P4_U0_CFG19 0x40011853u +#define CYREG_B1_P4_U0_CFG20 0x40011854u +#define CYREG_B1_P4_U0_CFG21 0x40011855u +#define CYREG_B1_P4_U0_CFG22 0x40011856u +#define CYREG_B1_P4_U0_CFG23 0x40011857u +#define CYREG_B1_P4_U0_CFG24 0x40011858u +#define CYREG_B1_P4_U0_CFG25 0x40011859u +#define CYREG_B1_P4_U0_CFG26 0x4001185au +#define CYREG_B1_P4_U0_CFG27 0x4001185bu +#define CYREG_B1_P4_U0_CFG28 0x4001185cu +#define CYREG_B1_P4_U0_CFG29 0x4001185du +#define CYREG_B1_P4_U0_CFG30 0x4001185eu +#define CYREG_B1_P4_U0_CFG31 0x4001185fu +#define CYREG_B1_P4_U0_DCFG0 0x40011860u +#define CYREG_B1_P4_U0_DCFG1 0x40011862u +#define CYREG_B1_P4_U0_DCFG2 0x40011864u +#define CYREG_B1_P4_U0_DCFG3 0x40011866u +#define CYREG_B1_P4_U0_DCFG4 0x40011868u +#define CYREG_B1_P4_U0_DCFG5 0x4001186au +#define CYREG_B1_P4_U0_DCFG6 0x4001186cu +#define CYREG_B1_P4_U0_DCFG7 0x4001186eu +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880u +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070u +#define CYREG_B1_P4_U1_PLD_IT0 0x40011880u +#define CYREG_B1_P4_U1_PLD_IT1 0x40011884u +#define CYREG_B1_P4_U1_PLD_IT2 0x40011888u +#define CYREG_B1_P4_U1_PLD_IT3 0x4001188cu +#define CYREG_B1_P4_U1_PLD_IT4 0x40011890u +#define CYREG_B1_P4_U1_PLD_IT5 0x40011894u +#define CYREG_B1_P4_U1_PLD_IT6 0x40011898u +#define CYREG_B1_P4_U1_PLD_IT7 0x4001189cu +#define CYREG_B1_P4_U1_PLD_IT8 0x400118a0u +#define CYREG_B1_P4_U1_PLD_IT9 0x400118a4u +#define CYREG_B1_P4_U1_PLD_IT10 0x400118a8u +#define CYREG_B1_P4_U1_PLD_IT11 0x400118acu +#define CYREG_B1_P4_U1_PLD_ORT0 0x400118b0u +#define CYREG_B1_P4_U1_PLD_ORT1 0x400118b2u +#define CYREG_B1_P4_U1_PLD_ORT2 0x400118b4u +#define CYREG_B1_P4_U1_PLD_ORT3 0x400118b6u +#define CYREG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8u +#define CYREG_B1_P4_U1_MC_CFG_XORFB 0x400118bau +#define CYREG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bcu +#define CYREG_B1_P4_U1_MC_CFG_BYPASS 0x400118beu +#define CYREG_B1_P4_U1_CFG0 0x400118c0u +#define CYREG_B1_P4_U1_CFG1 0x400118c1u +#define CYREG_B1_P4_U1_CFG2 0x400118c2u +#define CYREG_B1_P4_U1_CFG3 0x400118c3u +#define CYREG_B1_P4_U1_CFG4 0x400118c4u +#define CYREG_B1_P4_U1_CFG5 0x400118c5u +#define CYREG_B1_P4_U1_CFG6 0x400118c6u +#define CYREG_B1_P4_U1_CFG7 0x400118c7u +#define CYREG_B1_P4_U1_CFG8 0x400118c8u +#define CYREG_B1_P4_U1_CFG9 0x400118c9u +#define CYREG_B1_P4_U1_CFG10 0x400118cau +#define CYREG_B1_P4_U1_CFG11 0x400118cbu +#define CYREG_B1_P4_U1_CFG12 0x400118ccu +#define CYREG_B1_P4_U1_CFG13 0x400118cdu +#define CYREG_B1_P4_U1_CFG14 0x400118ceu +#define CYREG_B1_P4_U1_CFG15 0x400118cfu +#define CYREG_B1_P4_U1_CFG16 0x400118d0u +#define CYREG_B1_P4_U1_CFG17 0x400118d1u +#define CYREG_B1_P4_U1_CFG18 0x400118d2u +#define CYREG_B1_P4_U1_CFG19 0x400118d3u +#define CYREG_B1_P4_U1_CFG20 0x400118d4u +#define CYREG_B1_P4_U1_CFG21 0x400118d5u +#define CYREG_B1_P4_U1_CFG22 0x400118d6u +#define CYREG_B1_P4_U1_CFG23 0x400118d7u +#define CYREG_B1_P4_U1_CFG24 0x400118d8u +#define CYREG_B1_P4_U1_CFG25 0x400118d9u +#define CYREG_B1_P4_U1_CFG26 0x400118dau +#define CYREG_B1_P4_U1_CFG27 0x400118dbu +#define CYREG_B1_P4_U1_CFG28 0x400118dcu +#define CYREG_B1_P4_U1_CFG29 0x400118ddu +#define CYREG_B1_P4_U1_CFG30 0x400118deu +#define CYREG_B1_P4_U1_CFG31 0x400118dfu +#define CYREG_B1_P4_U1_DCFG0 0x400118e0u +#define CYREG_B1_P4_U1_DCFG1 0x400118e2u +#define CYREG_B1_P4_U1_DCFG2 0x400118e4u +#define CYREG_B1_P4_U1_DCFG3 0x400118e6u +#define CYREG_B1_P4_U1_DCFG4 0x400118e8u +#define CYREG_B1_P4_U1_DCFG5 0x400118eau +#define CYREG_B1_P4_U1_DCFG6 0x400118ecu +#define CYREG_B1_P4_U1_DCFG7 0x400118eeu +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900u +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070u +#define CYREG_B1_P5_U0_PLD_IT0 0x40011a00u +#define CYREG_B1_P5_U0_PLD_IT1 0x40011a04u +#define CYREG_B1_P5_U0_PLD_IT2 0x40011a08u +#define CYREG_B1_P5_U0_PLD_IT3 0x40011a0cu +#define CYREG_B1_P5_U0_PLD_IT4 0x40011a10u +#define CYREG_B1_P5_U0_PLD_IT5 0x40011a14u +#define CYREG_B1_P5_U0_PLD_IT6 0x40011a18u +#define CYREG_B1_P5_U0_PLD_IT7 0x40011a1cu +#define CYREG_B1_P5_U0_PLD_IT8 0x40011a20u +#define CYREG_B1_P5_U0_PLD_IT9 0x40011a24u +#define CYREG_B1_P5_U0_PLD_IT10 0x40011a28u +#define CYREG_B1_P5_U0_PLD_IT11 0x40011a2cu +#define CYREG_B1_P5_U0_PLD_ORT0 0x40011a30u +#define CYREG_B1_P5_U0_PLD_ORT1 0x40011a32u +#define CYREG_B1_P5_U0_PLD_ORT2 0x40011a34u +#define CYREG_B1_P5_U0_PLD_ORT3 0x40011a36u +#define CYREG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38u +#define CYREG_B1_P5_U0_MC_CFG_XORFB 0x40011a3au +#define CYREG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3cu +#define CYREG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3eu +#define CYREG_B1_P5_U0_CFG0 0x40011a40u +#define CYREG_B1_P5_U0_CFG1 0x40011a41u +#define CYREG_B1_P5_U0_CFG2 0x40011a42u +#define CYREG_B1_P5_U0_CFG3 0x40011a43u +#define CYREG_B1_P5_U0_CFG4 0x40011a44u +#define CYREG_B1_P5_U0_CFG5 0x40011a45u +#define CYREG_B1_P5_U0_CFG6 0x40011a46u +#define CYREG_B1_P5_U0_CFG7 0x40011a47u +#define CYREG_B1_P5_U0_CFG8 0x40011a48u +#define CYREG_B1_P5_U0_CFG9 0x40011a49u +#define CYREG_B1_P5_U0_CFG10 0x40011a4au +#define CYREG_B1_P5_U0_CFG11 0x40011a4bu +#define CYREG_B1_P5_U0_CFG12 0x40011a4cu +#define CYREG_B1_P5_U0_CFG13 0x40011a4du +#define CYREG_B1_P5_U0_CFG14 0x40011a4eu +#define CYREG_B1_P5_U0_CFG15 0x40011a4fu +#define CYREG_B1_P5_U0_CFG16 0x40011a50u +#define CYREG_B1_P5_U0_CFG17 0x40011a51u +#define CYREG_B1_P5_U0_CFG18 0x40011a52u +#define CYREG_B1_P5_U0_CFG19 0x40011a53u +#define CYREG_B1_P5_U0_CFG20 0x40011a54u +#define CYREG_B1_P5_U0_CFG21 0x40011a55u +#define CYREG_B1_P5_U0_CFG22 0x40011a56u +#define CYREG_B1_P5_U0_CFG23 0x40011a57u +#define CYREG_B1_P5_U0_CFG24 0x40011a58u +#define CYREG_B1_P5_U0_CFG25 0x40011a59u +#define CYREG_B1_P5_U0_CFG26 0x40011a5au +#define CYREG_B1_P5_U0_CFG27 0x40011a5bu +#define CYREG_B1_P5_U0_CFG28 0x40011a5cu +#define CYREG_B1_P5_U0_CFG29 0x40011a5du +#define CYREG_B1_P5_U0_CFG30 0x40011a5eu +#define CYREG_B1_P5_U0_CFG31 0x40011a5fu +#define CYREG_B1_P5_U0_DCFG0 0x40011a60u +#define CYREG_B1_P5_U0_DCFG1 0x40011a62u +#define CYREG_B1_P5_U0_DCFG2 0x40011a64u +#define CYREG_B1_P5_U0_DCFG3 0x40011a66u +#define CYREG_B1_P5_U0_DCFG4 0x40011a68u +#define CYREG_B1_P5_U0_DCFG5 0x40011a6au +#define CYREG_B1_P5_U0_DCFG6 0x40011a6cu +#define CYREG_B1_P5_U0_DCFG7 0x40011a6eu +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80u +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070u +#define CYREG_B1_P5_U1_PLD_IT0 0x40011a80u +#define CYREG_B1_P5_U1_PLD_IT1 0x40011a84u +#define CYREG_B1_P5_U1_PLD_IT2 0x40011a88u +#define CYREG_B1_P5_U1_PLD_IT3 0x40011a8cu +#define CYREG_B1_P5_U1_PLD_IT4 0x40011a90u +#define CYREG_B1_P5_U1_PLD_IT5 0x40011a94u +#define CYREG_B1_P5_U1_PLD_IT6 0x40011a98u +#define CYREG_B1_P5_U1_PLD_IT7 0x40011a9cu +#define CYREG_B1_P5_U1_PLD_IT8 0x40011aa0u +#define CYREG_B1_P5_U1_PLD_IT9 0x40011aa4u +#define CYREG_B1_P5_U1_PLD_IT10 0x40011aa8u +#define CYREG_B1_P5_U1_PLD_IT11 0x40011aacu +#define CYREG_B1_P5_U1_PLD_ORT0 0x40011ab0u +#define CYREG_B1_P5_U1_PLD_ORT1 0x40011ab2u +#define CYREG_B1_P5_U1_PLD_ORT2 0x40011ab4u +#define CYREG_B1_P5_U1_PLD_ORT3 0x40011ab6u +#define CYREG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8u +#define CYREG_B1_P5_U1_MC_CFG_XORFB 0x40011abau +#define CYREG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abcu +#define CYREG_B1_P5_U1_MC_CFG_BYPASS 0x40011abeu +#define CYREG_B1_P5_U1_CFG0 0x40011ac0u +#define CYREG_B1_P5_U1_CFG1 0x40011ac1u +#define CYREG_B1_P5_U1_CFG2 0x40011ac2u +#define CYREG_B1_P5_U1_CFG3 0x40011ac3u +#define CYREG_B1_P5_U1_CFG4 0x40011ac4u +#define CYREG_B1_P5_U1_CFG5 0x40011ac5u +#define CYREG_B1_P5_U1_CFG6 0x40011ac6u +#define CYREG_B1_P5_U1_CFG7 0x40011ac7u +#define CYREG_B1_P5_U1_CFG8 0x40011ac8u +#define CYREG_B1_P5_U1_CFG9 0x40011ac9u +#define CYREG_B1_P5_U1_CFG10 0x40011acau +#define CYREG_B1_P5_U1_CFG11 0x40011acbu +#define CYREG_B1_P5_U1_CFG12 0x40011accu +#define CYREG_B1_P5_U1_CFG13 0x40011acdu +#define CYREG_B1_P5_U1_CFG14 0x40011aceu +#define CYREG_B1_P5_U1_CFG15 0x40011acfu +#define CYREG_B1_P5_U1_CFG16 0x40011ad0u +#define CYREG_B1_P5_U1_CFG17 0x40011ad1u +#define CYREG_B1_P5_U1_CFG18 0x40011ad2u +#define CYREG_B1_P5_U1_CFG19 0x40011ad3u +#define CYREG_B1_P5_U1_CFG20 0x40011ad4u +#define CYREG_B1_P5_U1_CFG21 0x40011ad5u +#define CYREG_B1_P5_U1_CFG22 0x40011ad6u +#define CYREG_B1_P5_U1_CFG23 0x40011ad7u +#define CYREG_B1_P5_U1_CFG24 0x40011ad8u +#define CYREG_B1_P5_U1_CFG25 0x40011ad9u +#define CYREG_B1_P5_U1_CFG26 0x40011adau +#define CYREG_B1_P5_U1_CFG27 0x40011adbu +#define CYREG_B1_P5_U1_CFG28 0x40011adcu +#define CYREG_B1_P5_U1_CFG29 0x40011addu +#define CYREG_B1_P5_U1_CFG30 0x40011adeu +#define CYREG_B1_P5_U1_CFG31 0x40011adfu +#define CYREG_B1_P5_U1_DCFG0 0x40011ae0u +#define CYREG_B1_P5_U1_DCFG1 0x40011ae2u +#define CYREG_B1_P5_U1_DCFG2 0x40011ae4u +#define CYREG_B1_P5_U1_DCFG3 0x40011ae6u +#define CYREG_B1_P5_U1_DCFG4 0x40011ae8u +#define CYREG_B1_P5_U1_DCFG5 0x40011aeau +#define CYREG_B1_P5_U1_DCFG6 0x40011aecu +#define CYREG_B1_P5_U1_DCFG7 0x40011aeeu +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00u +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_DSI0_BASE 0x40014000u +#define CYDEV_UCFG_DSI0_SIZE 0x000000efu +#define CYDEV_UCFG_DSI1_BASE 0x40014100u +#define CYDEV_UCFG_DSI1_SIZE 0x000000efu +#define CYDEV_UCFG_DSI2_BASE 0x40014200u +#define CYDEV_UCFG_DSI2_SIZE 0x000000efu +#define CYDEV_UCFG_DSI3_BASE 0x40014300u +#define CYDEV_UCFG_DSI3_SIZE 0x000000efu +#define CYDEV_UCFG_DSI4_BASE 0x40014400u +#define CYDEV_UCFG_DSI4_SIZE 0x000000efu +#define CYDEV_UCFG_DSI5_BASE 0x40014500u +#define CYDEV_UCFG_DSI5_SIZE 0x000000efu +#define CYDEV_UCFG_DSI6_BASE 0x40014600u +#define CYDEV_UCFG_DSI6_SIZE 0x000000efu +#define CYDEV_UCFG_DSI7_BASE 0x40014700u +#define CYDEV_UCFG_DSI7_SIZE 0x000000efu +#define CYDEV_UCFG_DSI8_BASE 0x40014800u +#define CYDEV_UCFG_DSI8_SIZE 0x000000efu +#define CYDEV_UCFG_DSI9_BASE 0x40014900u +#define CYDEV_UCFG_DSI9_SIZE 0x000000efu +#define CYDEV_UCFG_DSI12_BASE 0x40014c00u +#define CYDEV_UCFG_DSI12_SIZE 0x000000efu +#define CYDEV_UCFG_DSI13_BASE 0x40014d00u +#define CYDEV_UCFG_DSI13_SIZE 0x000000efu +#define CYDEV_UCFG_BCTL0_BASE 0x40015000u +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010u +#define CYREG_BCTL0_MDCLK_EN 0x40015000u +#define CYREG_BCTL0_MBCLK_EN 0x40015001u +#define CYREG_BCTL0_WAIT_CFG 0x40015002u +#define CYREG_BCTL0_BANK_CTL 0x40015003u +#define CYREG_BCTL0_UDB_TEST_3 0x40015007u +#define CYREG_BCTL0_DCLK_EN0 0x40015008u +#define CYREG_BCTL0_BCLK_EN0 0x40015009u +#define CYREG_BCTL0_DCLK_EN1 0x4001500au +#define CYREG_BCTL0_BCLK_EN1 0x4001500bu +#define CYREG_BCTL0_DCLK_EN2 0x4001500cu +#define CYREG_BCTL0_BCLK_EN2 0x4001500du +#define CYREG_BCTL0_DCLK_EN3 0x4001500eu +#define CYREG_BCTL0_BCLK_EN3 0x4001500fu +#define CYDEV_UCFG_BCTL1_BASE 0x40015010u +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010u +#define CYREG_BCTL1_MDCLK_EN 0x40015010u +#define CYREG_BCTL1_MBCLK_EN 0x40015011u +#define CYREG_BCTL1_WAIT_CFG 0x40015012u +#define CYREG_BCTL1_BANK_CTL 0x40015013u +#define CYREG_BCTL1_UDB_TEST_3 0x40015017u +#define CYREG_BCTL1_DCLK_EN0 0x40015018u +#define CYREG_BCTL1_BCLK_EN0 0x40015019u +#define CYREG_BCTL1_DCLK_EN1 0x4001501au +#define CYREG_BCTL1_BCLK_EN1 0x4001501bu +#define CYREG_BCTL1_DCLK_EN2 0x4001501cu +#define CYREG_BCTL1_BCLK_EN2 0x4001501du +#define CYREG_BCTL1_DCLK_EN3 0x4001501eu +#define CYREG_BCTL1_BCLK_EN3 0x4001501fu +#define CYDEV_IDMUX_BASE 0x40015100u +#define CYDEV_IDMUX_SIZE 0x00000016u +#define CYREG_IDMUX_IRQ_CTL0 0x40015100u +#define CYREG_IDMUX_IRQ_CTL1 0x40015101u +#define CYREG_IDMUX_IRQ_CTL2 0x40015102u +#define CYREG_IDMUX_IRQ_CTL3 0x40015103u +#define CYREG_IDMUX_IRQ_CTL4 0x40015104u +#define CYREG_IDMUX_IRQ_CTL5 0x40015105u +#define CYREG_IDMUX_IRQ_CTL6 0x40015106u +#define CYREG_IDMUX_IRQ_CTL7 0x40015107u +#define CYREG_IDMUX_DRQ_CTL0 0x40015110u +#define CYREG_IDMUX_DRQ_CTL1 0x40015111u +#define CYREG_IDMUX_DRQ_CTL2 0x40015112u +#define CYREG_IDMUX_DRQ_CTL3 0x40015113u +#define CYREG_IDMUX_DRQ_CTL4 0x40015114u +#define CYREG_IDMUX_DRQ_CTL5 0x40015115u +#define CYDEV_CACHERAM_BASE 0x40030000u +#define CYDEV_CACHERAM_SIZE 0x00000400u +#define CYREG_CACHERAM_DATA_MBASE 0x40030000u +#define CYREG_CACHERAM_DATA_MSIZE 0x00000400u +#define CYDEV_SFR_BASE 0x40050100u +#define CYDEV_SFR_SIZE 0x000000fbu +#define CYREG_SFR_GPIO0 0x40050180u +#define CYREG_SFR_GPIRD0 0x40050189u +#define CYREG_SFR_GPIO0_SEL 0x4005018au +#define CYREG_SFR_GPIO1 0x40050190u +#define CYREG_SFR_GPIRD1 0x40050191u +#define CYREG_SFR_GPIO2 0x40050198u +#define CYREG_SFR_GPIRD2 0x40050199u +#define CYREG_SFR_GPIO2_SEL 0x4005019au +#define CYREG_SFR_GPIO1_SEL 0x400501a2u +#define CYREG_SFR_GPIO3 0x400501b0u +#define CYREG_SFR_GPIRD3 0x400501b1u +#define CYREG_SFR_GPIO3_SEL 0x400501b2u +#define CYREG_SFR_GPIO4 0x400501c0u +#define CYREG_SFR_GPIRD4 0x400501c1u +#define CYREG_SFR_GPIO4_SEL 0x400501c2u +#define CYREG_SFR_GPIO5 0x400501c8u +#define CYREG_SFR_GPIRD5 0x400501c9u +#define CYREG_SFR_GPIO5_SEL 0x400501cau +#define CYREG_SFR_GPIO6 0x400501d8u +#define CYREG_SFR_GPIRD6 0x400501d9u +#define CYREG_SFR_GPIO6_SEL 0x400501dau +#define CYREG_SFR_GPIO12 0x400501e8u +#define CYREG_SFR_GPIRD12 0x400501e9u +#define CYREG_SFR_GPIO12_SEL 0x400501f2u +#define CYREG_SFR_GPIO15 0x400501f8u +#define CYREG_SFR_GPIRD15 0x400501f9u +#define CYREG_SFR_GPIO15_SEL 0x400501fau +#define CYDEV_P3BA_BASE 0x40050300u +#define CYDEV_P3BA_SIZE 0x0000002bu +#define CYREG_P3BA_Y_START 0x40050300u +#define CYREG_P3BA_YROLL 0x40050301u +#define CYREG_P3BA_YCFG 0x40050302u +#define CYREG_P3BA_X_START1 0x40050303u +#define CYREG_P3BA_X_START2 0x40050304u +#define CYREG_P3BA_XROLL1 0x40050305u +#define CYREG_P3BA_XROLL2 0x40050306u +#define CYREG_P3BA_XINC 0x40050307u +#define CYREG_P3BA_XCFG 0x40050308u +#define CYREG_P3BA_OFFSETADDR1 0x40050309u +#define CYREG_P3BA_OFFSETADDR2 0x4005030au +#define CYREG_P3BA_OFFSETADDR3 0x4005030bu +#define CYREG_P3BA_ABSADDR1 0x4005030cu +#define CYREG_P3BA_ABSADDR2 0x4005030du +#define CYREG_P3BA_ABSADDR3 0x4005030eu +#define CYREG_P3BA_ABSADDR4 0x4005030fu +#define CYREG_P3BA_DATCFG1 0x40050310u +#define CYREG_P3BA_DATCFG2 0x40050311u +#define CYREG_P3BA_CMP_RSLT1 0x40050314u +#define CYREG_P3BA_CMP_RSLT2 0x40050315u +#define CYREG_P3BA_CMP_RSLT3 0x40050316u +#define CYREG_P3BA_CMP_RSLT4 0x40050317u +#define CYREG_P3BA_DATA_REG1 0x40050318u +#define CYREG_P3BA_DATA_REG2 0x40050319u +#define CYREG_P3BA_DATA_REG3 0x4005031au +#define CYREG_P3BA_DATA_REG4 0x4005031bu +#define CYREG_P3BA_EXP_DATA1 0x4005031cu +#define CYREG_P3BA_EXP_DATA2 0x4005031du +#define CYREG_P3BA_EXP_DATA3 0x4005031eu +#define CYREG_P3BA_EXP_DATA4 0x4005031fu +#define CYREG_P3BA_MSTR_HRDATA1 0x40050320u +#define CYREG_P3BA_MSTR_HRDATA2 0x40050321u +#define CYREG_P3BA_MSTR_HRDATA3 0x40050322u +#define CYREG_P3BA_MSTR_HRDATA4 0x40050323u +#define CYREG_P3BA_BIST_EN 0x40050324u +#define CYREG_P3BA_PHUB_MASTER_SSR 0x40050325u +#define CYREG_P3BA_SEQCFG1 0x40050326u +#define CYREG_P3BA_SEQCFG2 0x40050327u +#define CYREG_P3BA_Y_CURR 0x40050328u +#define CYREG_P3BA_X_CURR1 0x40050329u +#define CYREG_P3BA_X_CURR2 0x4005032au +#define CYDEV_PANTHER_BASE 0x40080000u +#define CYDEV_PANTHER_SIZE 0x00000020u +#define CYREG_PANTHER_STCALIB_CFG 0x40080000u +#define CYREG_PANTHER_WAITPIPE 0x40080004u +#define CYREG_PANTHER_TRACE_CFG 0x40080008u +#define CYREG_PANTHER_DBG_CFG 0x4008000cu +#define CYREG_PANTHER_CM3_LCKRST_STAT 0x40080018u +#define CYREG_PANTHER_DEVICE_ID 0x4008001cu +#define CYDEV_FLSECC_BASE 0x48000000u +#define CYDEV_FLSECC_SIZE 0x00008000u +#define CYREG_FLSECC_DATA_MBASE 0x48000000u +#define CYREG_FLSECC_DATA_MSIZE 0x00008000u +#define CYDEV_FLSHID_BASE 0x49000000u +#define CYDEV_FLSHID_SIZE 0x00000200u +#define CYREG_FLSHID_RSVD_MBASE 0x49000000u +#define CYREG_FLSHID_RSVD_MSIZE 0x00000080u +#define CYREG_FLSHID_CUST_MDATA_MBASE 0x49000080u +#define CYREG_FLSHID_CUST_MDATA_MSIZE 0x00000080u +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100u +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040u +#define CYREG_FLSHID_CUST_TABLES_Y_LOC 0x49000100u +#define CYREG_FLSHID_CUST_TABLES_X_LOC 0x49000101u +#define CYREG_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102u +#define CYREG_FLSHID_CUST_TABLES_LOT_LSB 0x49000103u +#define CYREG_FLSHID_CUST_TABLES_LOT_MSB 0x49000104u +#define CYREG_FLSHID_CUST_TABLES_WRK_WK 0x49000105u +#define CYREG_FLSHID_CUST_TABLES_FAB_YR 0x49000106u +#define CYREG_FLSHID_CUST_TABLES_MINOR 0x49000107u +#define CYREG_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108u +#define CYREG_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109u +#define CYREG_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010au +#define CYREG_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010bu +#define CYREG_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010cu +#define CYREG_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010du +#define CYREG_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010eu +#define CYREG_FLSHID_CUST_TABLES_IMO_USB 0x4900010fu +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110u +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111u +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112u +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113u +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114u +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115u +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116u +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117u +#define CYREG_FLSHID_CUST_TABLES_DEC_M1 0x49000118u +#define CYREG_FLSHID_CUST_TABLES_DEC_M2 0x49000119u +#define CYREG_FLSHID_CUST_TABLES_DEC_M3 0x4900011au +#define CYREG_FLSHID_CUST_TABLES_DEC_M4 0x4900011bu +#define CYREG_FLSHID_CUST_TABLES_DEC_M5 0x4900011cu +#define CYREG_FLSHID_CUST_TABLES_DEC_M6 0x4900011du +#define CYREG_FLSHID_CUST_TABLES_DEC_M7 0x4900011eu +#define CYREG_FLSHID_CUST_TABLES_DEC_M8 0x4900011fu +#define CYREG_FLSHID_CUST_TABLES_DAC0_M1 0x49000120u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M2 0x49000121u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M3 0x49000122u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M4 0x49000123u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M5 0x49000124u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M6 0x49000125u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M7 0x49000126u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M8 0x49000127u +#define CYREG_FLSHID_CUST_TABLES_DAC2_M1 0x49000128u +#define CYREG_FLSHID_CUST_TABLES_DAC2_M2 0x49000129u +#define CYREG_FLSHID_CUST_TABLES_DAC2_M3 0x4900012au +#define CYREG_FLSHID_CUST_TABLES_DAC2_M4 0x4900012bu +#define CYREG_FLSHID_CUST_TABLES_DAC2_M5 0x4900012cu +#define CYREG_FLSHID_CUST_TABLES_DAC2_M6 0x4900012du +#define CYREG_FLSHID_CUST_TABLES_DAC2_M7 0x4900012eu +#define CYREG_FLSHID_CUST_TABLES_DAC2_M8 0x4900012fu +#define CYREG_FLSHID_CUST_TABLES_DAC1_M1 0x49000130u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M2 0x49000131u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M3 0x49000132u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M4 0x49000133u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M5 0x49000134u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M6 0x49000135u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M7 0x49000136u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M8 0x49000137u +#define CYREG_FLSHID_CUST_TABLES_DAC3_M1 0x49000138u +#define CYREG_FLSHID_CUST_TABLES_DAC3_M2 0x49000139u +#define CYREG_FLSHID_CUST_TABLES_DAC3_M3 0x4900013au +#define CYREG_FLSHID_CUST_TABLES_DAC3_M4 0x4900013bu +#define CYREG_FLSHID_CUST_TABLES_DAC3_M5 0x4900013cu +#define CYREG_FLSHID_CUST_TABLES_DAC3_M6 0x4900013du +#define CYREG_FLSHID_CUST_TABLES_DAC3_M7 0x4900013eu +#define CYREG_FLSHID_CUST_TABLES_DAC3_M8 0x4900013fu +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180u +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080u +#define CYREG_FLSHID_MFG_CFG_IMO_TR1 0x49000188u +#define CYREG_FLSHID_MFG_CFG_CMP0_TR0 0x490001acu +#define CYREG_FLSHID_MFG_CFG_CMP1_TR0 0x490001aeu +#define CYREG_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0u +#define CYREG_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2u +#define CYREG_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4u +#define CYREG_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6u +#define CYREG_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8u +#define CYREG_FLSHID_MFG_CFG_CMP3_TR1 0x490001bau +#define CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ceu +#define CYDEV_EXTMEM_BASE 0x60000000u +#define CYDEV_EXTMEM_SIZE 0x00800000u +#define CYREG_EXTMEM_DATA_MBASE 0x60000000u +#define CYREG_EXTMEM_DATA_MSIZE 0x00800000u +#define CYDEV_ITM_BASE 0xe0000000u +#define CYDEV_ITM_SIZE 0x00001000u +#define CYREG_ITM_TRACE_EN 0xe0000e00u +#define CYREG_ITM_TRACE_PRIVILEGE 0xe0000e40u +#define CYREG_ITM_TRACE_CTRL 0xe0000e80u +#define CYREG_ITM_LOCK_ACCESS 0xe0000fb0u +#define CYREG_ITM_LOCK_STATUS 0xe0000fb4u +#define CYREG_ITM_PID4 0xe0000fd0u +#define CYREG_ITM_PID5 0xe0000fd4u +#define CYREG_ITM_PID6 0xe0000fd8u +#define CYREG_ITM_PID7 0xe0000fdcu +#define CYREG_ITM_PID0 0xe0000fe0u +#define CYREG_ITM_PID1 0xe0000fe4u +#define CYREG_ITM_PID2 0xe0000fe8u +#define CYREG_ITM_PID3 0xe0000fecu +#define CYREG_ITM_CID0 0xe0000ff0u +#define CYREG_ITM_CID1 0xe0000ff4u +#define CYREG_ITM_CID2 0xe0000ff8u +#define CYREG_ITM_CID3 0xe0000ffcu +#define CYDEV_DWT_BASE 0xe0001000u +#define CYDEV_DWT_SIZE 0x0000005cu +#define CYREG_DWT_CTRL 0xe0001000u +#define CYREG_DWT_CYCLE_COUNT 0xe0001004u +#define CYREG_DWT_CPI_COUNT 0xe0001008u +#define CYREG_DWT_EXC_OVHD_COUNT 0xe000100cu +#define CYREG_DWT_SLEEP_COUNT 0xe0001010u +#define CYREG_DWT_LSU_COUNT 0xe0001014u +#define CYREG_DWT_FOLD_COUNT 0xe0001018u +#define CYREG_DWT_PC_SAMPLE 0xe000101cu +#define CYREG_DWT_COMP_0 0xe0001020u +#define CYREG_DWT_MASK_0 0xe0001024u +#define CYREG_DWT_FUNCTION_0 0xe0001028u +#define CYREG_DWT_COMP_1 0xe0001030u +#define CYREG_DWT_MASK_1 0xe0001034u +#define CYREG_DWT_FUNCTION_1 0xe0001038u +#define CYREG_DWT_COMP_2 0xe0001040u +#define CYREG_DWT_MASK_2 0xe0001044u +#define CYREG_DWT_FUNCTION_2 0xe0001048u +#define CYREG_DWT_COMP_3 0xe0001050u +#define CYREG_DWT_MASK_3 0xe0001054u +#define CYREG_DWT_FUNCTION_3 0xe0001058u +#define CYDEV_FPB_BASE 0xe0002000u +#define CYDEV_FPB_SIZE 0x00001000u +#define CYREG_FPB_CTRL 0xe0002000u +#define CYREG_FPB_REMAP 0xe0002004u +#define CYREG_FPB_FP_COMP_0 0xe0002008u +#define CYREG_FPB_FP_COMP_1 0xe000200cu +#define CYREG_FPB_FP_COMP_2 0xe0002010u +#define CYREG_FPB_FP_COMP_3 0xe0002014u +#define CYREG_FPB_FP_COMP_4 0xe0002018u +#define CYREG_FPB_FP_COMP_5 0xe000201cu +#define CYREG_FPB_FP_COMP_6 0xe0002020u +#define CYREG_FPB_FP_COMP_7 0xe0002024u +#define CYREG_FPB_PID4 0xe0002fd0u +#define CYREG_FPB_PID5 0xe0002fd4u +#define CYREG_FPB_PID6 0xe0002fd8u +#define CYREG_FPB_PID7 0xe0002fdcu +#define CYREG_FPB_PID0 0xe0002fe0u +#define CYREG_FPB_PID1 0xe0002fe4u +#define CYREG_FPB_PID2 0xe0002fe8u +#define CYREG_FPB_PID3 0xe0002fecu +#define CYREG_FPB_CID0 0xe0002ff0u +#define CYREG_FPB_CID1 0xe0002ff4u +#define CYREG_FPB_CID2 0xe0002ff8u +#define CYREG_FPB_CID3 0xe0002ffcu +#define CYDEV_NVIC_BASE 0xe000e000u +#define CYDEV_NVIC_SIZE 0x00000d3cu +#define CYREG_NVIC_INT_CTL_TYPE 0xe000e004u +#define CYREG_NVIC_SYSTICK_CTL 0xe000e010u +#define CYREG_NVIC_SYSTICK_RELOAD 0xe000e014u +#define CYREG_NVIC_SYSTICK_CURRENT 0xe000e018u +#define CYREG_NVIC_SYSTICK_CAL 0xe000e01cu +#define CYREG_NVIC_SETENA0 0xe000e100u +#define CYREG_NVIC_CLRENA0 0xe000e180u +#define CYREG_NVIC_SETPEND0 0xe000e200u +#define CYREG_NVIC_CLRPEND0 0xe000e280u +#define CYREG_NVIC_ACTIVE0 0xe000e300u +#define CYREG_NVIC_PRI_0 0xe000e400u +#define CYREG_NVIC_PRI_1 0xe000e401u +#define CYREG_NVIC_PRI_2 0xe000e402u +#define CYREG_NVIC_PRI_3 0xe000e403u +#define CYREG_NVIC_PRI_4 0xe000e404u +#define CYREG_NVIC_PRI_5 0xe000e405u +#define CYREG_NVIC_PRI_6 0xe000e406u +#define CYREG_NVIC_PRI_7 0xe000e407u +#define CYREG_NVIC_PRI_8 0xe000e408u +#define CYREG_NVIC_PRI_9 0xe000e409u +#define CYREG_NVIC_PRI_10 0xe000e40au +#define CYREG_NVIC_PRI_11 0xe000e40bu +#define CYREG_NVIC_PRI_12 0xe000e40cu +#define CYREG_NVIC_PRI_13 0xe000e40du +#define CYREG_NVIC_PRI_14 0xe000e40eu +#define CYREG_NVIC_PRI_15 0xe000e40fu +#define CYREG_NVIC_PRI_16 0xe000e410u +#define CYREG_NVIC_PRI_17 0xe000e411u +#define CYREG_NVIC_PRI_18 0xe000e412u +#define CYREG_NVIC_PRI_19 0xe000e413u +#define CYREG_NVIC_PRI_20 0xe000e414u +#define CYREG_NVIC_PRI_21 0xe000e415u +#define CYREG_NVIC_PRI_22 0xe000e416u +#define CYREG_NVIC_PRI_23 0xe000e417u +#define CYREG_NVIC_PRI_24 0xe000e418u +#define CYREG_NVIC_PRI_25 0xe000e419u +#define CYREG_NVIC_PRI_26 0xe000e41au +#define CYREG_NVIC_PRI_27 0xe000e41bu +#define CYREG_NVIC_PRI_28 0xe000e41cu +#define CYREG_NVIC_PRI_29 0xe000e41du +#define CYREG_NVIC_PRI_30 0xe000e41eu +#define CYREG_NVIC_PRI_31 0xe000e41fu +#define CYREG_NVIC_CPUID_BASE 0xe000ed00u +#define CYREG_NVIC_INTR_CTRL_STATE 0xe000ed04u +#define CYREG_NVIC_VECT_OFFSET 0xe000ed08u +#define CYREG_NVIC_APPLN_INTR 0xe000ed0cu +#define CYREG_NVIC_SYSTEM_CONTROL 0xe000ed10u +#define CYREG_NVIC_CFG_CONTROL 0xe000ed14u +#define CYREG_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18u +#define CYREG_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1cu +#define CYREG_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20u +#define CYREG_NVIC_SYS_HANDLER_CSR 0xe000ed24u +#define CYREG_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28u +#define CYREG_NVIC_BUS_FAULT_STATUS 0xe000ed29u +#define CYREG_NVIC_USAGE_FAULT_STATUS 0xe000ed2au +#define CYREG_NVIC_HARD_FAULT_STATUS 0xe000ed2cu +#define CYREG_NVIC_DEBUG_FAULT_STATUS 0xe000ed30u +#define CYREG_NVIC_MEMMAN_FAULT_ADD 0xe000ed34u +#define CYREG_NVIC_BUS_FAULT_ADD 0xe000ed38u +#define CYDEV_CORE_DBG_BASE 0xe000edf0u +#define CYDEV_CORE_DBG_SIZE 0x00000010u +#define CYREG_CORE_DBG_DBG_HLT_CS 0xe000edf0u +#define CYREG_CORE_DBG_DBG_REG_SEL 0xe000edf4u +#define CYREG_CORE_DBG_DBG_REG_DATA 0xe000edf8u +#define CYREG_CORE_DBG_EXC_MON_CTL 0xe000edfcu +#define CYDEV_TPIU_BASE 0xe0040000u +#define CYDEV_TPIU_SIZE 0x00001000u +#define CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000u +#define CYREG_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004u +#define CYREG_TPIU_ASYNC_CLK_PRESCALER 0xe0040010u +#define CYREG_TPIU_PROTOCOL 0xe00400f0u +#define CYREG_TPIU_FORM_FLUSH_STAT 0xe0040300u +#define CYREG_TPIU_FORM_FLUSH_CTRL 0xe0040304u +#define CYREG_TPIU_TRIGGER 0xe0040ee8u +#define CYREG_TPIU_ITETMDATA 0xe0040eecu +#define CYREG_TPIU_ITATBCTR2 0xe0040ef0u +#define CYREG_TPIU_ITATBCTR0 0xe0040ef8u +#define CYREG_TPIU_ITITMDATA 0xe0040efcu +#define CYREG_TPIU_ITCTRL 0xe0040f00u +#define CYREG_TPIU_DEVID 0xe0040fc8u +#define CYREG_TPIU_DEVTYPE 0xe0040fccu +#define CYREG_TPIU_PID4 0xe0040fd0u +#define CYREG_TPIU_PID5 0xe0040fd4u +#define CYREG_TPIU_PID6 0xe0040fd8u +#define CYREG_TPIU_PID7 0xe0040fdcu +#define CYREG_TPIU_PID0 0xe0040fe0u +#define CYREG_TPIU_PID1 0xe0040fe4u +#define CYREG_TPIU_PID2 0xe0040fe8u +#define CYREG_TPIU_PID3 0xe0040fecu +#define CYREG_TPIU_CID0 0xe0040ff0u +#define CYREG_TPIU_CID1 0xe0040ff4u +#define CYREG_TPIU_CID2 0xe0040ff8u +#define CYREG_TPIU_CID3 0xe0040ffcu +#define CYDEV_ETM_BASE 0xe0041000u +#define CYDEV_ETM_SIZE 0x00001000u +#define CYREG_ETM_CTL 0xe0041000u +#define CYREG_ETM_CFG_CODE 0xe0041004u +#define CYREG_ETM_TRIG_EVENT 0xe0041008u +#define CYREG_ETM_STATUS 0xe0041010u +#define CYREG_ETM_SYS_CFG 0xe0041014u +#define CYREG_ETM_TRACE_ENB_EVENT 0xe0041020u +#define CYREG_ETM_TRACE_EN_CTRL1 0xe0041024u +#define CYREG_ETM_FIFOFULL_LEVEL 0xe004102cu +#define CYREG_ETM_SYNC_FREQ 0xe00411e0u +#define CYREG_ETM_ETM_ID 0xe00411e4u +#define CYREG_ETM_CFG_CODE_EXT 0xe00411e8u +#define CYREG_ETM_TR_SS_EMBICE_CTRL 0xe00411f0u +#define CYREG_ETM_CS_TRACE_ID 0xe0041200u +#define CYREG_ETM_OS_LOCK_ACCESS 0xe0041300u +#define CYREG_ETM_OS_LOCK_STATUS 0xe0041304u +#define CYREG_ETM_PDSR 0xe0041314u +#define CYREG_ETM_ITMISCIN 0xe0041ee0u +#define CYREG_ETM_ITTRIGOUT 0xe0041ee8u +#define CYREG_ETM_ITATBCTR2 0xe0041ef0u +#define CYREG_ETM_ITATBCTR0 0xe0041ef8u +#define CYREG_ETM_INT_MODE_CTRL 0xe0041f00u +#define CYREG_ETM_CLM_TAG_SET 0xe0041fa0u +#define CYREG_ETM_CLM_TAG_CLR 0xe0041fa4u +#define CYREG_ETM_LOCK_ACCESS 0xe0041fb0u +#define CYREG_ETM_LOCK_STATUS 0xe0041fb4u +#define CYREG_ETM_AUTH_STATUS 0xe0041fb8u +#define CYREG_ETM_DEV_TYPE 0xe0041fccu +#define CYREG_ETM_PID4 0xe0041fd0u +#define CYREG_ETM_PID5 0xe0041fd4u +#define CYREG_ETM_PID6 0xe0041fd8u +#define CYREG_ETM_PID7 0xe0041fdcu +#define CYREG_ETM_PID0 0xe0041fe0u +#define CYREG_ETM_PID1 0xe0041fe4u +#define CYREG_ETM_PID2 0xe0041fe8u +#define CYREG_ETM_PID3 0xe0041fecu +#define CYREG_ETM_CID0 0xe0041ff0u +#define CYREG_ETM_CID1 0xe0041ff4u +#define CYREG_ETM_CID2 0xe0041ff8u +#define CYREG_ETM_CID3 0xe0041ffcu +#define CYDEV_ROM_TABLE_BASE 0xe00ff000u +#define CYDEV_ROM_TABLE_SIZE 0x00001000u +#define CYREG_ROM_TABLE_NVIC 0xe00ff000u +#define CYREG_ROM_TABLE_DWT 0xe00ff004u +#define CYREG_ROM_TABLE_FPB 0xe00ff008u +#define CYREG_ROM_TABLE_ITM 0xe00ff00cu +#define CYREG_ROM_TABLE_TPIU 0xe00ff010u +#define CYREG_ROM_TABLE_ETM 0xe00ff014u +#define CYREG_ROM_TABLE_END 0xe00ff018u +#define CYREG_ROM_TABLE_MEMTYPE 0xe00fffccu +#define CYREG_ROM_TABLE_PID4 0xe00fffd0u +#define CYREG_ROM_TABLE_PID5 0xe00fffd4u +#define CYREG_ROM_TABLE_PID6 0xe00fffd8u +#define CYREG_ROM_TABLE_PID7 0xe00fffdcu +#define CYREG_ROM_TABLE_PID0 0xe00fffe0u +#define CYREG_ROM_TABLE_PID1 0xe00fffe4u +#define CYREG_ROM_TABLE_PID2 0xe00fffe8u +#define CYREG_ROM_TABLE_PID3 0xe00fffecu +#define CYREG_ROM_TABLE_CID0 0xe00ffff0u +#define CYREG_ROM_TABLE_CID1 0xe00ffff4u +#define CYREG_ROM_TABLE_CID2 0xe00ffff8u +#define CYREG_ROM_TABLE_CID3 0xe00ffffcu +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000u +#define CYDEV_FLS_ROW_SIZE 0x00000100u +#define CYDEV_ECC_SECTOR_SIZE 0x00002000u +#define CYDEV_ECC_ROW_SIZE 0x00000020u +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u +#define CYDEV_EEPROM_ROW_SIZE 0x00000010u +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004u +#define CYCLK_LD_SYNC_EN 0x00000002u +#define CYCLK_LD_LOAD 0x00000001u +#define CYCLK_PIPE 0x00000080u +#define CYCLK_SSS 0x00000040u +#define CYCLK_EARLY 0x00000020u +#define CYCLK_DUTY 0x00000010u +#define CYCLK_SYNC 0x00000008u +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 +#endif /* CYDEVICE_TRM_H */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/cyfitter.h b/source/hic_hal/cypress/psoc5lp/PSoC5/cyfitter.h new file mode 100644 index 0000000000..6b1124eb9b --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/cyfitter.h @@ -0,0 +1,2507 @@ +/******************************************************************************* +* File Name: cyfitter.h +* +* PSoC Creator 4.2 +* +* Description: +* +* This file provides basic startup and mux configuration settings +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#ifndef INCLUDED_CYFITTER_H +#define INCLUDED_CYFITTER_H +#include "cydevice.h" +#include "cydevice_trm.h" + +/* Pin_3 */ +#define Pin_3__0__INTTYPE CYREG_PICU0_INTTYPE6 +#define Pin_3__0__MASK 0x40u +#define Pin_3__0__PC CYREG_PRT0_PC6 +#define Pin_3__0__PORT 0u +#define Pin_3__0__SHIFT 6u +#define Pin_3__AG CYREG_PRT0_AG +#define Pin_3__AMUX CYREG_PRT0_AMUX +#define Pin_3__BIE CYREG_PRT0_BIE +#define Pin_3__BIT_MASK CYREG_PRT0_BIT_MASK +#define Pin_3__BYP CYREG_PRT0_BYP +#define Pin_3__CTL CYREG_PRT0_CTL +#define Pin_3__DM0 CYREG_PRT0_DM0 +#define Pin_3__DM1 CYREG_PRT0_DM1 +#define Pin_3__DM2 CYREG_PRT0_DM2 +#define Pin_3__DR CYREG_PRT0_DR +#define Pin_3__INP_DIS CYREG_PRT0_INP_DIS +#define Pin_3__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE +#define Pin_3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define Pin_3__LCD_EN CYREG_PRT0_LCD_EN +#define Pin_3__MASK 0x40u +#define Pin_3__PORT 0u +#define Pin_3__PRT CYREG_PRT0_PRT +#define Pin_3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define Pin_3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define Pin_3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define Pin_3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define Pin_3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define Pin_3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define Pin_3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define Pin_3__PS CYREG_PRT0_PS +#define Pin_3__SHIFT 6u +#define Pin_3__SLW CYREG_PRT0_SLW + +/* Pin_4 */ +#define Pin_4__0__INTTYPE CYREG_PICU3_INTTYPE7 +#define Pin_4__0__MASK 0x80u +#define Pin_4__0__PC CYREG_PRT3_PC7 +#define Pin_4__0__PORT 3u +#define Pin_4__0__SHIFT 7u +#define Pin_4__AG CYREG_PRT3_AG +#define Pin_4__AMUX CYREG_PRT3_AMUX +#define Pin_4__BIE CYREG_PRT3_BIE +#define Pin_4__BIT_MASK CYREG_PRT3_BIT_MASK +#define Pin_4__BYP CYREG_PRT3_BYP +#define Pin_4__CTL CYREG_PRT3_CTL +#define Pin_4__DM0 CYREG_PRT3_DM0 +#define Pin_4__DM1 CYREG_PRT3_DM1 +#define Pin_4__DM2 CYREG_PRT3_DM2 +#define Pin_4__DR CYREG_PRT3_DR +#define Pin_4__INP_DIS CYREG_PRT3_INP_DIS +#define Pin_4__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define Pin_4__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define Pin_4__LCD_EN CYREG_PRT3_LCD_EN +#define Pin_4__MASK 0x80u +#define Pin_4__PORT 3u +#define Pin_4__PRT CYREG_PRT3_PRT +#define Pin_4__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define Pin_4__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define Pin_4__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define Pin_4__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define Pin_4__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define Pin_4__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define Pin_4__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define Pin_4__PS CYREG_PRT3_PS +#define Pin_4__SHIFT 7u +#define Pin_4__SLW CYREG_PRT3_SLW + +/* Pin_5 */ +#define Pin_5__0__INTTYPE CYREG_PICU0_INTTYPE0 +#define Pin_5__0__MASK 0x01u +#define Pin_5__0__PC CYREG_PRT0_PC0 +#define Pin_5__0__PORT 0u +#define Pin_5__0__SHIFT 0u +#define Pin_5__AG CYREG_PRT0_AG +#define Pin_5__AMUX CYREG_PRT0_AMUX +#define Pin_5__BIE CYREG_PRT0_BIE +#define Pin_5__BIT_MASK CYREG_PRT0_BIT_MASK +#define Pin_5__BYP CYREG_PRT0_BYP +#define Pin_5__CTL CYREG_PRT0_CTL +#define Pin_5__DM0 CYREG_PRT0_DM0 +#define Pin_5__DM1 CYREG_PRT0_DM1 +#define Pin_5__DM2 CYREG_PRT0_DM2 +#define Pin_5__DR CYREG_PRT0_DR +#define Pin_5__INP_DIS CYREG_PRT0_INP_DIS +#define Pin_5__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE +#define Pin_5__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define Pin_5__LCD_EN CYREG_PRT0_LCD_EN +#define Pin_5__MASK 0x01u +#define Pin_5__PORT 0u +#define Pin_5__PRT CYREG_PRT0_PRT +#define Pin_5__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define Pin_5__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define Pin_5__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define Pin_5__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define Pin_5__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define Pin_5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define Pin_5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define Pin_5__PS CYREG_PRT0_PS +#define Pin_5__SHIFT 0u +#define Pin_5__SLW CYREG_PRT0_SLW + +/* SWDIO */ +#define SWDIO__0__INTTYPE CYREG_PICU12_INTTYPE2 +#define SWDIO__0__MASK 0x04u +#define SWDIO__0__PC CYREG_PRT12_PC2 +#define SWDIO__0__PORT 12u +#define SWDIO__0__SHIFT 2u +#define SWDIO__AG CYREG_PRT12_AG +#define SWDIO__BIE CYREG_PRT12_BIE +#define SWDIO__BIT_MASK CYREG_PRT12_BIT_MASK +#define SWDIO__BYP CYREG_PRT12_BYP +#define SWDIO__DM0 CYREG_PRT12_DM0 +#define SWDIO__DM1 CYREG_PRT12_DM1 +#define SWDIO__DM2 CYREG_PRT12_DM2 +#define SWDIO__DR CYREG_PRT12_DR +#define SWDIO__INP_DIS CYREG_PRT12_INP_DIS +#define SWDIO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE +#define SWDIO__MASK 0x04u +#define SWDIO__PORT 12u +#define SWDIO__PRT CYREG_PRT12_PRT +#define SWDIO__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SWDIO__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SWDIO__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SWDIO__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SWDIO__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SWDIO__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SWDIO__PS CYREG_PRT12_PS +#define SWDIO__SHIFT 2u +#define SWDIO__SIO_CFG CYREG_PRT12_SIO_CFG +#define SWDIO__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SWDIO__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SWDIO__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SWDIO__SLW CYREG_PRT12_SLW + +/* USBFS */ +#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_arb_int__INTC_MASK 0x400000u +#define USBFS_arb_int__INTC_NUMBER 22u +#define USBFS_arb_int__INTC_PRIOR_NUM 6u +#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22 +#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_bus_reset__INTC_MASK 0x800000u +#define USBFS_bus_reset__INTC_NUMBER 23u +#define USBFS_bus_reset__INTC_PRIOR_NUM 6u +#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23 +#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7 +#define USBFS_Dm__0__MASK 0x80u +#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 +#define USBFS_Dm__0__PORT 15u +#define USBFS_Dm__0__SHIFT 7u +#define USBFS_Dm__AG CYREG_PRT15_AG +#define USBFS_Dm__AMUX CYREG_PRT15_AMUX +#define USBFS_Dm__BIE CYREG_PRT15_BIE +#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dm__BYP CYREG_PRT15_BYP +#define USBFS_Dm__CTL CYREG_PRT15_CTL +#define USBFS_Dm__DM0 CYREG_PRT15_DM0 +#define USBFS_Dm__DM1 CYREG_PRT15_DM1 +#define USBFS_Dm__DM2 CYREG_PRT15_DM2 +#define USBFS_Dm__DR CYREG_PRT15_DR +#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dm__MASK 0x80u +#define USBFS_Dm__PORT 15u +#define USBFS_Dm__PRT CYREG_PRT15_PRT +#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dm__PS CYREG_PRT15_PS +#define USBFS_Dm__SHIFT 7u +#define USBFS_Dm__SLW CYREG_PRT15_SLW +#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6 +#define USBFS_Dp__0__MASK 0x40u +#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0 +#define USBFS_Dp__0__PORT 15u +#define USBFS_Dp__0__SHIFT 6u +#define USBFS_Dp__AG CYREG_PRT15_AG +#define USBFS_Dp__AMUX CYREG_PRT15_AMUX +#define USBFS_Dp__BIE CYREG_PRT15_BIE +#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dp__BYP CYREG_PRT15_BYP +#define USBFS_Dp__CTL CYREG_PRT15_CTL +#define USBFS_Dp__DM0 CYREG_PRT15_DM0 +#define USBFS_Dp__DM1 CYREG_PRT15_DM1 +#define USBFS_Dp__DM2 CYREG_PRT15_DM2 +#define USBFS_Dp__DR CYREG_PRT15_DR +#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT +#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dp__MASK 0x40u +#define USBFS_Dp__PORT 15u +#define USBFS_Dp__PRT CYREG_PRT15_PRT +#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dp__PS CYREG_PRT15_PS +#define USBFS_Dp__SHIFT 6u +#define USBFS_Dp__SLW CYREG_PRT15_SLW +#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15 +#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_dp_int__INTC_MASK 0x1000u +#define USBFS_dp_int__INTC_NUMBER 12u +#define USBFS_dp_int__INTC_PRIOR_NUM 6u +#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12 +#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_0__INTC_MASK 0x1000000u +#define USBFS_ep_0__INTC_NUMBER 24u +#define USBFS_ep_0__INTC_PRIOR_NUM 6u +#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24 +#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_1__INTC_MASK 0x20u +#define USBFS_ep_1__INTC_NUMBER 5u +#define USBFS_ep_1__INTC_PRIOR_NUM 6u +#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_5 +#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_2__INTC_MASK 0x40u +#define USBFS_ep_2__INTC_NUMBER 6u +#define USBFS_ep_2__INTC_PRIOR_NUM 6u +#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_6 +#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_3__INTC_MASK 0x80u +#define USBFS_ep_3__INTC_NUMBER 7u +#define USBFS_ep_3__INTC_PRIOR_NUM 6u +#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_7 +#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_4__INTC_MASK 0x100u +#define USBFS_ep_4__INTC_NUMBER 8u +#define USBFS_ep_4__INTC_PRIOR_NUM 6u +#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_8 +#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_5__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_5__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_5__INTC_MASK 0x200u +#define USBFS_ep_5__INTC_NUMBER 9u +#define USBFS_ep_5__INTC_PRIOR_NUM 7u +#define USBFS_ep_5__INTC_PRIOR_REG CYREG_NVIC_PRI_9 +#define USBFS_ep_5__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_5__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_6__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_6__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_6__INTC_MASK 0x400u +#define USBFS_ep_6__INTC_NUMBER 10u +#define USBFS_ep_6__INTC_PRIOR_NUM 6u +#define USBFS_ep_6__INTC_PRIOR_REG CYREG_NVIC_PRI_10 +#define USBFS_ep_6__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_6__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_7__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_7__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_7__INTC_MASK 0x800u +#define USBFS_ep_7__INTC_NUMBER 11u +#define USBFS_ep_7__INTC_PRIOR_NUM 6u +#define USBFS_ep_7__INTC_PRIOR_REG CYREG_NVIC_PRI_11 +#define USBFS_ep_7__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_7__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ord_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ord_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ord_int__INTC_MASK 0x2000000u +#define USBFS_ord_int__INTC_NUMBER 25u +#define USBFS_ord_int__INTC_PRIOR_NUM 6u +#define USBFS_ord_int__INTC_PRIOR_REG CYREG_NVIC_PRI_25 +#define USBFS_ord_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ord_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_sof_int__INTC_MASK 0x200000u +#define USBFS_sof_int__INTC_NUMBER 21u +#define USBFS_sof_int__INTC_PRIOR_NUM 6u +#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21 +#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG +#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG +#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN +#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR +#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG +#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN +#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR +#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG +#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN +#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR +#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG +#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN +#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR +#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG +#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN +#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR +#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG +#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN +#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR +#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG +#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN +#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR +#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG +#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN +#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR +#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN +#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR +#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR +#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA +#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB +#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA +#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB +#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR +#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA +#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB +#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA +#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB +#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR +#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA +#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB +#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA +#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB +#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR +#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA +#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB +#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA +#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB +#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR +#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA +#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB +#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA +#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB +#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR +#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA +#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB +#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA +#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB +#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR +#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA +#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB +#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA +#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB +#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR +#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA +#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB +#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA +#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB +#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE +#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT +#define USBFS_USB__CR0 CYREG_USB_CR0 +#define USBFS_USB__CR1 CYREG_USB_CR1 +#define USBFS_USB__CWA CYREG_USB_CWA +#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB +#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES +#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB +#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG +#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE +#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE +#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT +#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR +#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0 +#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1 +#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2 +#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3 +#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4 +#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5 +#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6 +#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7 +#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE +#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5 +#define USBFS_USB__PM_ACT_MSK 0x01u +#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5 +#define USBFS_USB__PM_STBY_MSK 0x01u +#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN +#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR +#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0 +#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1 +#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0 +#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0 +#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1 +#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0 +#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0 +#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1 +#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0 +#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0 +#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1 +#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0 +#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0 +#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1 +#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0 +#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0 +#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1 +#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0 +#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0 +#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1 +#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0 +#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0 +#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1 +#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0 +#define USBFS_USB__SOF0 CYREG_USB_SOF0 +#define USBFS_USB__SOF1 CYREG_USB_SOF1 +#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN +#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0 +#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 +#define USBFS_VBUS__0__INTTYPE CYREG_PICU1_INTTYPE7 +#define USBFS_VBUS__0__MASK 0x80u +#define USBFS_VBUS__0__PC CYREG_PRT1_PC7 +#define USBFS_VBUS__0__PORT 1u +#define USBFS_VBUS__0__SHIFT 7u +#define USBFS_VBUS__AG CYREG_PRT1_AG +#define USBFS_VBUS__AMUX CYREG_PRT1_AMUX +#define USBFS_VBUS__BIE CYREG_PRT1_BIE +#define USBFS_VBUS__BIT_MASK CYREG_PRT1_BIT_MASK +#define USBFS_VBUS__BYP CYREG_PRT1_BYP +#define USBFS_VBUS__CTL CYREG_PRT1_CTL +#define USBFS_VBUS__DM0 CYREG_PRT1_DM0 +#define USBFS_VBUS__DM1 CYREG_PRT1_DM1 +#define USBFS_VBUS__DM2 CYREG_PRT1_DM2 +#define USBFS_VBUS__DR CYREG_PRT1_DR +#define USBFS_VBUS__INP_DIS CYREG_PRT1_INP_DIS +#define USBFS_VBUS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU1_BASE +#define USBFS_VBUS__LCD_COM_SEG CYREG_PRT1_LCD_COM_SEG +#define USBFS_VBUS__LCD_EN CYREG_PRT1_LCD_EN +#define USBFS_VBUS__MASK 0x80u +#define USBFS_VBUS__PORT 1u +#define USBFS_VBUS__PRT CYREG_PRT1_PRT +#define USBFS_VBUS__PRTDSI__CAPS_SEL CYREG_PRT1_CAPS_SEL +#define USBFS_VBUS__PRTDSI__DBL_SYNC_IN CYREG_PRT1_DBL_SYNC_IN +#define USBFS_VBUS__PRTDSI__OE_SEL0 CYREG_PRT1_OE_SEL0 +#define USBFS_VBUS__PRTDSI__OE_SEL1 CYREG_PRT1_OE_SEL1 +#define USBFS_VBUS__PRTDSI__OUT_SEL0 CYREG_PRT1_OUT_SEL0 +#define USBFS_VBUS__PRTDSI__OUT_SEL1 CYREG_PRT1_OUT_SEL1 +#define USBFS_VBUS__PRTDSI__SYNC_OUT CYREG_PRT1_SYNC_OUT +#define USBFS_VBUS__PS CYREG_PRT1_PS +#define USBFS_VBUS__SHIFT 7u +#define USBFS_VBUS__SLW CYREG_PRT1_SLW + +/* SWDCLK */ +#define SWDCLK__0__INTTYPE CYREG_PICU12_INTTYPE3 +#define SWDCLK__0__MASK 0x08u +#define SWDCLK__0__PC CYREG_PRT12_PC3 +#define SWDCLK__0__PORT 12u +#define SWDCLK__0__SHIFT 3u +#define SWDCLK__AG CYREG_PRT12_AG +#define SWDCLK__BIE CYREG_PRT12_BIE +#define SWDCLK__BIT_MASK CYREG_PRT12_BIT_MASK +#define SWDCLK__BYP CYREG_PRT12_BYP +#define SWDCLK__DM0 CYREG_PRT12_DM0 +#define SWDCLK__DM1 CYREG_PRT12_DM1 +#define SWDCLK__DM2 CYREG_PRT12_DM2 +#define SWDCLK__DR CYREG_PRT12_DR +#define SWDCLK__INP_DIS CYREG_PRT12_INP_DIS +#define SWDCLK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE +#define SWDCLK__MASK 0x08u +#define SWDCLK__PORT 12u +#define SWDCLK__PRT CYREG_PRT12_PRT +#define SWDCLK__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SWDCLK__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SWDCLK__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SWDCLK__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SWDCLK__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SWDCLK__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SWDCLK__PS CYREG_PRT12_PS +#define SWDCLK__SHIFT 3u +#define SWDCLK__SIO_CFG CYREG_PRT12_SIO_CFG +#define SWDCLK__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SWDCLK__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SWDCLK__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SWDCLK__SLW CYREG_PRT12_SLW + +/* I2C_POT */ +#define I2C_POT_I2C_FF__ADR CYREG_I2C_ADR +#define I2C_POT_I2C_FF__CFG CYREG_I2C_CFG +#define I2C_POT_I2C_FF__CLK_DIV1 CYREG_I2C_CLK_DIV1 +#define I2C_POT_I2C_FF__CLK_DIV2 CYREG_I2C_CLK_DIV2 +#define I2C_POT_I2C_FF__CSR CYREG_I2C_CSR +#define I2C_POT_I2C_FF__D CYREG_I2C_D +#define I2C_POT_I2C_FF__MCSR CYREG_I2C_MCSR +#define I2C_POT_I2C_FF__PM_ACT_CFG CYREG_PM_ACT_CFG5 +#define I2C_POT_I2C_FF__PM_ACT_MSK 0x04u +#define I2C_POT_I2C_FF__PM_STBY_CFG CYREG_PM_STBY_CFG5 +#define I2C_POT_I2C_FF__PM_STBY_MSK 0x04u +#define I2C_POT_I2C_FF__TMOUT_CFG0 CYREG_I2C_TMOUT_CFG0 +#define I2C_POT_I2C_FF__TMOUT_CFG1 CYREG_I2C_TMOUT_CFG1 +#define I2C_POT_I2C_FF__TMOUT_CSR CYREG_I2C_TMOUT_CSR +#define I2C_POT_I2C_FF__TMOUT_SR CYREG_I2C_TMOUT_SR +#define I2C_POT_I2C_FF__XCFG CYREG_I2C_XCFG +#define I2C_POT_I2C_IRQ__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define I2C_POT_I2C_IRQ__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define I2C_POT_I2C_IRQ__INTC_MASK 0x8000u +#define I2C_POT_I2C_IRQ__INTC_NUMBER 15u +#define I2C_POT_I2C_IRQ__INTC_PRIOR_NUM 7u +#define I2C_POT_I2C_IRQ__INTC_PRIOR_REG CYREG_NVIC_PRI_15 +#define I2C_POT_I2C_IRQ__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define I2C_POT_I2C_IRQ__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* I2C_UDB */ +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__16BIT_A0_REG CYREG_B0_UDB11_12_A0 +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__16BIT_A1_REG CYREG_B0_UDB11_12_A1 +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__16BIT_D0_REG CYREG_B0_UDB11_12_D0 +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__16BIT_D1_REG CYREG_B0_UDB11_12_D1 +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__16BIT_F0_REG CYREG_B0_UDB11_12_F0 +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__16BIT_F1_REG CYREG_B0_UDB11_12_F1 +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__A0_A1_REG CYREG_B0_UDB11_A0_A1 +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__A0_REG CYREG_B0_UDB11_A0 +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__A1_REG CYREG_B0_UDB11_A1 +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__D0_D1_REG CYREG_B0_UDB11_D0_D1 +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__D0_REG CYREG_B0_UDB11_D0 +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__D1_REG CYREG_B0_UDB11_D1 +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__DP_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__F0_F1_REG CYREG_B0_UDB11_F0_F1 +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__F0_REG CYREG_B0_UDB11_F0 +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__F1_REG CYREG_B0_UDB11_F1 +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define I2C_UDB_bI2C_UDB_Master_ClkGen_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define I2C_UDB_bI2C_UDB_Shifter_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 +#define I2C_UDB_bI2C_UDB_Shifter_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 +#define I2C_UDB_bI2C_UDB_Shifter_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 +#define I2C_UDB_bI2C_UDB_Shifter_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1 +#define I2C_UDB_bI2C_UDB_Shifter_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define I2C_UDB_bI2C_UDB_Shifter_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0 +#define I2C_UDB_bI2C_UDB_Shifter_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1 +#define I2C_UDB_bI2C_UDB_Shifter_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1 +#define I2C_UDB_bI2C_UDB_Shifter_u0__A0_REG CYREG_B1_UDB04_A0 +#define I2C_UDB_bI2C_UDB_Shifter_u0__A1_REG CYREG_B1_UDB04_A1 +#define I2C_UDB_bI2C_UDB_Shifter_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1 +#define I2C_UDB_bI2C_UDB_Shifter_u0__D0_REG CYREG_B1_UDB04_D0 +#define I2C_UDB_bI2C_UDB_Shifter_u0__D1_REG CYREG_B1_UDB04_D1 +#define I2C_UDB_bI2C_UDB_Shifter_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define I2C_UDB_bI2C_UDB_Shifter_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 +#define I2C_UDB_bI2C_UDB_Shifter_u0__F0_REG CYREG_B1_UDB04_F0 +#define I2C_UDB_bI2C_UDB_Shifter_u0__F1_REG CYREG_B1_UDB04_F1 +#define I2C_UDB_bI2C_UDB_StsReg__0__MASK 0x01u +#define I2C_UDB_bI2C_UDB_StsReg__0__POS 0 +#define I2C_UDB_bI2C_UDB_StsReg__1__MASK 0x02u +#define I2C_UDB_bI2C_UDB_StsReg__1__POS 1 +#define I2C_UDB_bI2C_UDB_StsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define I2C_UDB_bI2C_UDB_StsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST +#define I2C_UDB_bI2C_UDB_StsReg__2__MASK 0x04u +#define I2C_UDB_bI2C_UDB_StsReg__2__POS 2 +#define I2C_UDB_bI2C_UDB_StsReg__3__MASK 0x08u +#define I2C_UDB_bI2C_UDB_StsReg__3__POS 3 +#define I2C_UDB_bI2C_UDB_StsReg__4__MASK 0x10u +#define I2C_UDB_bI2C_UDB_StsReg__4__POS 4 +#define I2C_UDB_bI2C_UDB_StsReg__5__MASK 0x20u +#define I2C_UDB_bI2C_UDB_StsReg__5__POS 5 +#define I2C_UDB_bI2C_UDB_StsReg__6__MASK 0x40u +#define I2C_UDB_bI2C_UDB_StsReg__6__POS 6 +#define I2C_UDB_bI2C_UDB_StsReg__MASK 0x7Fu +#define I2C_UDB_bI2C_UDB_StsReg__MASK_REG CYREG_B1_UDB07_MSK +#define I2C_UDB_bI2C_UDB_StsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define I2C_UDB_bI2C_UDB_StsReg__STATUS_REG CYREG_B1_UDB07_ST +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__1__MASK 0x02u +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__1__POS 1 +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__2__MASK 0x04u +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__2__POS 2 +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__4__MASK 0x10u +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__4__POS 4 +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__5__MASK 0x20u +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__5__POS 5 +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__6__MASK 0x40u +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__6__POS 6 +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__7__MASK 0x80u +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__7__POS 7 +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__CONTROL_REG CYREG_B0_UDB07_CTL +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__COUNT_REG CYREG_B0_UDB07_CTL +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__MASK 0xF6u +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__PERIOD_REG CYREG_B0_UDB07_MSK +#define I2C_UDB_I2C_IRQ__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define I2C_UDB_I2C_IRQ__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define I2C_UDB_I2C_IRQ__INTC_MASK 0x01u +#define I2C_UDB_I2C_IRQ__INTC_NUMBER 0u +#define I2C_UDB_I2C_IRQ__INTC_PRIOR_NUM 5u +#define I2C_UDB_I2C_IRQ__INTC_PRIOR_REG CYREG_NVIC_PRI_0 +#define I2C_UDB_I2C_IRQ__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define I2C_UDB_I2C_IRQ__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* LED_8Hz */ +#define LED_8Hz__CFG0 CYREG_CLKDIST_DCFG7_CFG0 +#define LED_8Hz__CFG1 CYREG_CLKDIST_DCFG7_CFG1 +#define LED_8Hz__CFG2 CYREG_CLKDIST_DCFG7_CFG2 +#define LED_8Hz__CFG2_SRC_SEL_MASK 0x07u +#define LED_8Hz__INDEX 0x07u +#define LED_8Hz__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define LED_8Hz__PM_ACT_MSK 0x80u +#define LED_8Hz__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define LED_8Hz__PM_STBY_MSK 0x80u + +/* LED_Red */ +#define LED_Red__0__INTTYPE CYREG_PICU1_INTTYPE3 +#define LED_Red__0__MASK 0x08u +#define LED_Red__0__PC CYREG_PRT1_PC3 +#define LED_Red__0__PORT 1u +#define LED_Red__0__SHIFT 3u +#define LED_Red__AG CYREG_PRT1_AG +#define LED_Red__AMUX CYREG_PRT1_AMUX +#define LED_Red__BIE CYREG_PRT1_BIE +#define LED_Red__BIT_MASK CYREG_PRT1_BIT_MASK +#define LED_Red__BYP CYREG_PRT1_BYP +#define LED_Red__CTL CYREG_PRT1_CTL +#define LED_Red__DM0 CYREG_PRT1_DM0 +#define LED_Red__DM1 CYREG_PRT1_DM1 +#define LED_Red__DM2 CYREG_PRT1_DM2 +#define LED_Red__DR CYREG_PRT1_DR +#define LED_Red__INP_DIS CYREG_PRT1_INP_DIS +#define LED_Red__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU1_BASE +#define LED_Red__LCD_COM_SEG CYREG_PRT1_LCD_COM_SEG +#define LED_Red__LCD_EN CYREG_PRT1_LCD_EN +#define LED_Red__MASK 0x08u +#define LED_Red__PORT 1u +#define LED_Red__PRT CYREG_PRT1_PRT +#define LED_Red__PRTDSI__CAPS_SEL CYREG_PRT1_CAPS_SEL +#define LED_Red__PRTDSI__DBL_SYNC_IN CYREG_PRT1_DBL_SYNC_IN +#define LED_Red__PRTDSI__OE_SEL0 CYREG_PRT1_OE_SEL0 +#define LED_Red__PRTDSI__OE_SEL1 CYREG_PRT1_OE_SEL1 +#define LED_Red__PRTDSI__OUT_SEL0 CYREG_PRT1_OUT_SEL0 +#define LED_Red__PRTDSI__OUT_SEL1 CYREG_PRT1_OUT_SEL1 +#define LED_Red__PRTDSI__SYNC_OUT CYREG_PRT1_SYNC_OUT +#define LED_Red__PS CYREG_PRT1_PS +#define LED_Red__SHIFT 3u +#define LED_Red__SLW CYREG_PRT1_SLW + +/* SPIM_HW */ +#define SPIM_HW_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SPIM_HW_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL +#define SPIM_HW_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL +#define SPIM_HW_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL +#define SPIM_HW_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL +#define SPIM_HW_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK +#define SPIM_HW_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK +#define SPIM_HW_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK +#define SPIM_HW_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK +#define SPIM_HW_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SPIM_HW_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB05_CTL +#define SPIM_HW_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL +#define SPIM_HW_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB05_CTL +#define SPIM_HW_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL +#define SPIM_HW_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SPIM_HW_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SPIM_HW_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB05_MSK +#define SPIM_HW_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SPIM_HW_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST +#define SPIM_HW_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB05_MSK +#define SPIM_HW_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SPIM_HW_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SPIM_HW_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SPIM_HW_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL +#define SPIM_HW_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL +#define SPIM_HW_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB05_ST +#define SPIM_HW_BSPIM_CtrlReg__1__MASK 0x02u +#define SPIM_HW_BSPIM_CtrlReg__1__POS 1 +#define SPIM_HW_BSPIM_CtrlReg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SPIM_HW_BSPIM_CtrlReg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL +#define SPIM_HW_BSPIM_CtrlReg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL +#define SPIM_HW_BSPIM_CtrlReg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL +#define SPIM_HW_BSPIM_CtrlReg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL +#define SPIM_HW_BSPIM_CtrlReg__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK +#define SPIM_HW_BSPIM_CtrlReg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK +#define SPIM_HW_BSPIM_CtrlReg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK +#define SPIM_HW_BSPIM_CtrlReg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK +#define SPIM_HW_BSPIM_CtrlReg__2__MASK 0x04u +#define SPIM_HW_BSPIM_CtrlReg__2__POS 2 +#define SPIM_HW_BSPIM_CtrlReg__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SPIM_HW_BSPIM_CtrlReg__CONTROL_REG CYREG_B1_UDB06_CTL +#define SPIM_HW_BSPIM_CtrlReg__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL +#define SPIM_HW_BSPIM_CtrlReg__COUNT_REG CYREG_B1_UDB06_CTL +#define SPIM_HW_BSPIM_CtrlReg__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL +#define SPIM_HW_BSPIM_CtrlReg__MASK 0x06u +#define SPIM_HW_BSPIM_CtrlReg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SPIM_HW_BSPIM_CtrlReg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SPIM_HW_BSPIM_CtrlReg__PERIOD_REG CYREG_B1_UDB06_MSK +#define SPIM_HW_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL +#define SPIM_HW_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST +#define SPIM_HW_BSPIM_RxStsReg__4__MASK 0x10u +#define SPIM_HW_BSPIM_RxStsReg__4__POS 4 +#define SPIM_HW_BSPIM_RxStsReg__5__MASK 0x20u +#define SPIM_HW_BSPIM_RxStsReg__5__POS 5 +#define SPIM_HW_BSPIM_RxStsReg__6__MASK 0x40u +#define SPIM_HW_BSPIM_RxStsReg__6__POS 6 +#define SPIM_HW_BSPIM_RxStsReg__MASK 0x70u +#define SPIM_HW_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB02_MSK +#define SPIM_HW_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL +#define SPIM_HW_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB02_ST +#define SPIM_HW_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB03_04_A0 +#define SPIM_HW_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB03_04_A1 +#define SPIM_HW_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB03_04_D0 +#define SPIM_HW_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB03_04_D1 +#define SPIM_HW_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL +#define SPIM_HW_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB03_04_F0 +#define SPIM_HW_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB03_04_F1 +#define SPIM_HW_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB03_A0_A1 +#define SPIM_HW_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB03_A0 +#define SPIM_HW_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB03_A1 +#define SPIM_HW_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB03_D0_D1 +#define SPIM_HW_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB03_D0 +#define SPIM_HW_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB03_D1 +#define SPIM_HW_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL +#define SPIM_HW_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB03_F0_F1 +#define SPIM_HW_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB03_F0 +#define SPIM_HW_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB03_F1 +#define SPIM_HW_BSPIM_TxStsReg__0__MASK 0x01u +#define SPIM_HW_BSPIM_TxStsReg__0__POS 0 +#define SPIM_HW_BSPIM_TxStsReg__1__MASK 0x02u +#define SPIM_HW_BSPIM_TxStsReg__1__POS 1 +#define SPIM_HW_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define SPIM_HW_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST +#define SPIM_HW_BSPIM_TxStsReg__2__MASK 0x04u +#define SPIM_HW_BSPIM_TxStsReg__2__POS 2 +#define SPIM_HW_BSPIM_TxStsReg__3__MASK 0x08u +#define SPIM_HW_BSPIM_TxStsReg__3__POS 3 +#define SPIM_HW_BSPIM_TxStsReg__4__MASK 0x10u +#define SPIM_HW_BSPIM_TxStsReg__4__POS 4 +#define SPIM_HW_BSPIM_TxStsReg__MASK 0x1Fu +#define SPIM_HW_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB04_MSK +#define SPIM_HW_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define SPIM_HW_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB04_ST + +/* SWDXRES */ +#define SWDXRES__0__INTTYPE CYREG_PICU12_INTTYPE4 +#define SWDXRES__0__MASK 0x10u +#define SWDXRES__0__PC CYREG_PRT12_PC4 +#define SWDXRES__0__PORT 12u +#define SWDXRES__0__SHIFT 4u +#define SWDXRES__AG CYREG_PRT12_AG +#define SWDXRES__BIE CYREG_PRT12_BIE +#define SWDXRES__BIT_MASK CYREG_PRT12_BIT_MASK +#define SWDXRES__BYP CYREG_PRT12_BYP +#define SWDXRES__DM0 CYREG_PRT12_DM0 +#define SWDXRES__DM1 CYREG_PRT12_DM1 +#define SWDXRES__DM2 CYREG_PRT12_DM2 +#define SWDXRES__DR CYREG_PRT12_DR +#define SWDXRES__INP_DIS CYREG_PRT12_INP_DIS +#define SWDXRES__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE +#define SWDXRES__MASK 0x10u +#define SWDXRES__PORT 12u +#define SWDXRES__PRT CYREG_PRT12_PRT +#define SWDXRES__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SWDXRES__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SWDXRES__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SWDXRES__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SWDXRES__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SWDXRES__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SWDXRES__PS CYREG_PRT12_PS +#define SWDXRES__SHIFT 4u +#define SWDXRES__SIO_CFG CYREG_PRT12_SIO_CFG +#define SWDXRES__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SWDXRES__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SWDXRES__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SWDXRES__SLW CYREG_PRT12_SLW + +/* SPI_MISO */ +#define SPI_MISO__0__INTTYPE CYREG_PICU12_INTTYPE5 +#define SPI_MISO__0__MASK 0x20u +#define SPI_MISO__0__PC CYREG_PRT12_PC5 +#define SPI_MISO__0__PORT 12u +#define SPI_MISO__0__SHIFT 5u +#define SPI_MISO__AG CYREG_PRT12_AG +#define SPI_MISO__BIE CYREG_PRT12_BIE +#define SPI_MISO__BIT_MASK CYREG_PRT12_BIT_MASK +#define SPI_MISO__BYP CYREG_PRT12_BYP +#define SPI_MISO__DM0 CYREG_PRT12_DM0 +#define SPI_MISO__DM1 CYREG_PRT12_DM1 +#define SPI_MISO__DM2 CYREG_PRT12_DM2 +#define SPI_MISO__DR CYREG_PRT12_DR +#define SPI_MISO__INP_DIS CYREG_PRT12_INP_DIS +#define SPI_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE +#define SPI_MISO__MASK 0x20u +#define SPI_MISO__PORT 12u +#define SPI_MISO__PRT CYREG_PRT12_PRT +#define SPI_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SPI_MISO__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SPI_MISO__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SPI_MISO__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SPI_MISO__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SPI_MISO__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SPI_MISO__PS CYREG_PRT12_PS +#define SPI_MISO__SHIFT 5u +#define SPI_MISO__SIO_CFG CYREG_PRT12_SIO_CFG +#define SPI_MISO__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SPI_MISO__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SPI_MISO__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SPI_MISO__SLW CYREG_PRT12_SLW + +/* SPI_MOSI */ +#define SPI_MOSI__0__INTTYPE CYREG_PICU15_INTTYPE1 +#define SPI_MOSI__0__MASK 0x02u +#define SPI_MOSI__0__PC CYREG_IO_PC_PRT15_PC1 +#define SPI_MOSI__0__PORT 15u +#define SPI_MOSI__0__SHIFT 1u +#define SPI_MOSI__AG CYREG_PRT15_AG +#define SPI_MOSI__AMUX CYREG_PRT15_AMUX +#define SPI_MOSI__BIE CYREG_PRT15_BIE +#define SPI_MOSI__BIT_MASK CYREG_PRT15_BIT_MASK +#define SPI_MOSI__BYP CYREG_PRT15_BYP +#define SPI_MOSI__CTL CYREG_PRT15_CTL +#define SPI_MOSI__DM0 CYREG_PRT15_DM0 +#define SPI_MOSI__DM1 CYREG_PRT15_DM1 +#define SPI_MOSI__DM2 CYREG_PRT15_DM2 +#define SPI_MOSI__DR CYREG_PRT15_DR +#define SPI_MOSI__INP_DIS CYREG_PRT15_INP_DIS +#define SPI_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define SPI_MOSI__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define SPI_MOSI__LCD_EN CYREG_PRT15_LCD_EN +#define SPI_MOSI__MASK 0x02u +#define SPI_MOSI__PORT 15u +#define SPI_MOSI__PRT CYREG_PRT15_PRT +#define SPI_MOSI__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define SPI_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define SPI_MOSI__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define SPI_MOSI__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define SPI_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define SPI_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define SPI_MOSI__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define SPI_MOSI__PS CYREG_PRT15_PS +#define SPI_MOSI__SHIFT 1u +#define SPI_MOSI__SLW CYREG_PRT15_SLW + +/* SPI_SCLK */ +#define SPI_SCLK__0__INTTYPE CYREG_PICU15_INTTYPE2 +#define SPI_SCLK__0__MASK 0x04u +#define SPI_SCLK__0__PC CYREG_IO_PC_PRT15_PC2 +#define SPI_SCLK__0__PORT 15u +#define SPI_SCLK__0__SHIFT 2u +#define SPI_SCLK__AG CYREG_PRT15_AG +#define SPI_SCLK__AMUX CYREG_PRT15_AMUX +#define SPI_SCLK__BIE CYREG_PRT15_BIE +#define SPI_SCLK__BIT_MASK CYREG_PRT15_BIT_MASK +#define SPI_SCLK__BYP CYREG_PRT15_BYP +#define SPI_SCLK__CTL CYREG_PRT15_CTL +#define SPI_SCLK__DM0 CYREG_PRT15_DM0 +#define SPI_SCLK__DM1 CYREG_PRT15_DM1 +#define SPI_SCLK__DM2 CYREG_PRT15_DM2 +#define SPI_SCLK__DR CYREG_PRT15_DR +#define SPI_SCLK__INP_DIS CYREG_PRT15_INP_DIS +#define SPI_SCLK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define SPI_SCLK__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define SPI_SCLK__LCD_EN CYREG_PRT15_LCD_EN +#define SPI_SCLK__MASK 0x04u +#define SPI_SCLK__PORT 15u +#define SPI_SCLK__PRT CYREG_PRT15_PRT +#define SPI_SCLK__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define SPI_SCLK__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define SPI_SCLK__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define SPI_SCLK__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define SPI_SCLK__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define SPI_SCLK__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define SPI_SCLK__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define SPI_SCLK__PS CYREG_PRT15_PS +#define SPI_SCLK__SHIFT 2u +#define SPI_SCLK__SLW CYREG_PRT15_SLW + +/* SPI_SS_0 */ +#define SPI_SS_0__0__INTTYPE CYREG_PICU15_INTTYPE3 +#define SPI_SS_0__0__MASK 0x08u +#define SPI_SS_0__0__PC CYREG_IO_PC_PRT15_PC3 +#define SPI_SS_0__0__PORT 15u +#define SPI_SS_0__0__SHIFT 3u +#define SPI_SS_0__AG CYREG_PRT15_AG +#define SPI_SS_0__AMUX CYREG_PRT15_AMUX +#define SPI_SS_0__BIE CYREG_PRT15_BIE +#define SPI_SS_0__BIT_MASK CYREG_PRT15_BIT_MASK +#define SPI_SS_0__BYP CYREG_PRT15_BYP +#define SPI_SS_0__CTL CYREG_PRT15_CTL +#define SPI_SS_0__DM0 CYREG_PRT15_DM0 +#define SPI_SS_0__DM1 CYREG_PRT15_DM1 +#define SPI_SS_0__DM2 CYREG_PRT15_DM2 +#define SPI_SS_0__DR CYREG_PRT15_DR +#define SPI_SS_0__INP_DIS CYREG_PRT15_INP_DIS +#define SPI_SS_0__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define SPI_SS_0__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define SPI_SS_0__LCD_EN CYREG_PRT15_LCD_EN +#define SPI_SS_0__MASK 0x08u +#define SPI_SS_0__PORT 15u +#define SPI_SS_0__PRT CYREG_PRT15_PRT +#define SPI_SS_0__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define SPI_SS_0__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define SPI_SS_0__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define SPI_SS_0__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define SPI_SS_0__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define SPI_SS_0__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define SPI_SS_0__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define SPI_SS_0__PS CYREG_PRT15_PS +#define SPI_SS_0__SHIFT 3u +#define SPI_SS_0__SLW CYREG_PRT15_SLW + +/* SPI_SS_1 */ +#define SPI_SS_1__0__INTTYPE CYREG_PICU3_INTTYPE4 +#define SPI_SS_1__0__MASK 0x10u +#define SPI_SS_1__0__PC CYREG_PRT3_PC4 +#define SPI_SS_1__0__PORT 3u +#define SPI_SS_1__0__SHIFT 4u +#define SPI_SS_1__AG CYREG_PRT3_AG +#define SPI_SS_1__AMUX CYREG_PRT3_AMUX +#define SPI_SS_1__BIE CYREG_PRT3_BIE +#define SPI_SS_1__BIT_MASK CYREG_PRT3_BIT_MASK +#define SPI_SS_1__BYP CYREG_PRT3_BYP +#define SPI_SS_1__CTL CYREG_PRT3_CTL +#define SPI_SS_1__DM0 CYREG_PRT3_DM0 +#define SPI_SS_1__DM1 CYREG_PRT3_DM1 +#define SPI_SS_1__DM2 CYREG_PRT3_DM2 +#define SPI_SS_1__DR CYREG_PRT3_DR +#define SPI_SS_1__INP_DIS CYREG_PRT3_INP_DIS +#define SPI_SS_1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SPI_SS_1__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SPI_SS_1__LCD_EN CYREG_PRT3_LCD_EN +#define SPI_SS_1__MASK 0x10u +#define SPI_SS_1__PORT 3u +#define SPI_SS_1__PRT CYREG_PRT3_PRT +#define SPI_SS_1__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SPI_SS_1__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SPI_SS_1__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SPI_SS_1__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SPI_SS_1__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SPI_SS_1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SPI_SS_1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SPI_SS_1__PS CYREG_PRT3_PS +#define SPI_SS_1__SHIFT 4u +#define SPI_SS_1__SLW CYREG_PRT3_SLW + +/* SPI_SS_2 */ +#define SPI_SS_2__0__INTTYPE CYREG_PICU3_INTTYPE6 +#define SPI_SS_2__0__MASK 0x40u +#define SPI_SS_2__0__PC CYREG_PRT3_PC6 +#define SPI_SS_2__0__PORT 3u +#define SPI_SS_2__0__SHIFT 6u +#define SPI_SS_2__AG CYREG_PRT3_AG +#define SPI_SS_2__AMUX CYREG_PRT3_AMUX +#define SPI_SS_2__BIE CYREG_PRT3_BIE +#define SPI_SS_2__BIT_MASK CYREG_PRT3_BIT_MASK +#define SPI_SS_2__BYP CYREG_PRT3_BYP +#define SPI_SS_2__CTL CYREG_PRT3_CTL +#define SPI_SS_2__DM0 CYREG_PRT3_DM0 +#define SPI_SS_2__DM1 CYREG_PRT3_DM1 +#define SPI_SS_2__DM2 CYREG_PRT3_DM2 +#define SPI_SS_2__DR CYREG_PRT3_DR +#define SPI_SS_2__INP_DIS CYREG_PRT3_INP_DIS +#define SPI_SS_2__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SPI_SS_2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SPI_SS_2__LCD_EN CYREG_PRT3_LCD_EN +#define SPI_SS_2__MASK 0x40u +#define SPI_SS_2__PORT 3u +#define SPI_SS_2__PRT CYREG_PRT3_PRT +#define SPI_SS_2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SPI_SS_2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SPI_SS_2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SPI_SS_2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SPI_SS_2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SPI_SS_2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SPI_SS_2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SPI_SS_2__PS CYREG_PRT3_PS +#define SPI_SS_2__SHIFT 6u +#define SPI_SS_2__SLW CYREG_PRT3_SLW + +/* UART_CTS */ +#define UART_CTS__0__INTTYPE CYREG_PICU15_INTTYPE5 +#define UART_CTS__0__MASK 0x20u +#define UART_CTS__0__PC CYREG_IO_PC_PRT15_PC5 +#define UART_CTS__0__PORT 15u +#define UART_CTS__0__SHIFT 5u +#define UART_CTS__AG CYREG_PRT15_AG +#define UART_CTS__AMUX CYREG_PRT15_AMUX +#define UART_CTS__BIE CYREG_PRT15_BIE +#define UART_CTS__BIT_MASK CYREG_PRT15_BIT_MASK +#define UART_CTS__BYP CYREG_PRT15_BYP +#define UART_CTS__CTL CYREG_PRT15_CTL +#define UART_CTS__DM0 CYREG_PRT15_DM0 +#define UART_CTS__DM1 CYREG_PRT15_DM1 +#define UART_CTS__DM2 CYREG_PRT15_DM2 +#define UART_CTS__DR CYREG_PRT15_DR +#define UART_CTS__INP_DIS CYREG_PRT15_INP_DIS +#define UART_CTS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define UART_CTS__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define UART_CTS__LCD_EN CYREG_PRT15_LCD_EN +#define UART_CTS__MASK 0x20u +#define UART_CTS__PORT 15u +#define UART_CTS__PRT CYREG_PRT15_PRT +#define UART_CTS__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define UART_CTS__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define UART_CTS__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define UART_CTS__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define UART_CTS__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define UART_CTS__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define UART_CTS__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define UART_CTS__PS CYREG_PRT15_PS +#define UART_CTS__SHIFT 5u +#define UART_CTS__SLW CYREG_PRT15_SLW +#define UART_CTS_2__0__INTTYPE CYREG_PICU0_INTTYPE1 +#define UART_CTS_2__0__MASK 0x02u +#define UART_CTS_2__0__PC CYREG_PRT0_PC1 +#define UART_CTS_2__0__PORT 0u +#define UART_CTS_2__0__SHIFT 1u +#define UART_CTS_2__AG CYREG_PRT0_AG +#define UART_CTS_2__AMUX CYREG_PRT0_AMUX +#define UART_CTS_2__BIE CYREG_PRT0_BIE +#define UART_CTS_2__BIT_MASK CYREG_PRT0_BIT_MASK +#define UART_CTS_2__BYP CYREG_PRT0_BYP +#define UART_CTS_2__CTL CYREG_PRT0_CTL +#define UART_CTS_2__DM0 CYREG_PRT0_DM0 +#define UART_CTS_2__DM1 CYREG_PRT0_DM1 +#define UART_CTS_2__DM2 CYREG_PRT0_DM2 +#define UART_CTS_2__DR CYREG_PRT0_DR +#define UART_CTS_2__INP_DIS CYREG_PRT0_INP_DIS +#define UART_CTS_2__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE +#define UART_CTS_2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define UART_CTS_2__LCD_EN CYREG_PRT0_LCD_EN +#define UART_CTS_2__MASK 0x02u +#define UART_CTS_2__PORT 0u +#define UART_CTS_2__PRT CYREG_PRT0_PRT +#define UART_CTS_2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define UART_CTS_2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define UART_CTS_2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define UART_CTS_2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define UART_CTS_2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define UART_CTS_2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define UART_CTS_2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define UART_CTS_2__PS CYREG_PRT0_PS +#define UART_CTS_2__SHIFT 1u +#define UART_CTS_2__SLW CYREG_PRT0_SLW + +/* UART_RTS */ +#define UART_RTS__0__INTTYPE CYREG_PICU1_INTTYPE6 +#define UART_RTS__0__MASK 0x40u +#define UART_RTS__0__PC CYREG_PRT1_PC6 +#define UART_RTS__0__PORT 1u +#define UART_RTS__0__SHIFT 6u +#define UART_RTS__AG CYREG_PRT1_AG +#define UART_RTS__AMUX CYREG_PRT1_AMUX +#define UART_RTS__BIE CYREG_PRT1_BIE +#define UART_RTS__BIT_MASK CYREG_PRT1_BIT_MASK +#define UART_RTS__BYP CYREG_PRT1_BYP +#define UART_RTS__CTL CYREG_PRT1_CTL +#define UART_RTS__DM0 CYREG_PRT1_DM0 +#define UART_RTS__DM1 CYREG_PRT1_DM1 +#define UART_RTS__DM2 CYREG_PRT1_DM2 +#define UART_RTS__DR CYREG_PRT1_DR +#define UART_RTS__INP_DIS CYREG_PRT1_INP_DIS +#define UART_RTS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU1_BASE +#define UART_RTS__LCD_COM_SEG CYREG_PRT1_LCD_COM_SEG +#define UART_RTS__LCD_EN CYREG_PRT1_LCD_EN +#define UART_RTS__MASK 0x40u +#define UART_RTS__PORT 1u +#define UART_RTS__PRT CYREG_PRT1_PRT +#define UART_RTS__PRTDSI__CAPS_SEL CYREG_PRT1_CAPS_SEL +#define UART_RTS__PRTDSI__DBL_SYNC_IN CYREG_PRT1_DBL_SYNC_IN +#define UART_RTS__PRTDSI__OE_SEL0 CYREG_PRT1_OE_SEL0 +#define UART_RTS__PRTDSI__OE_SEL1 CYREG_PRT1_OE_SEL1 +#define UART_RTS__PRTDSI__OUT_SEL0 CYREG_PRT1_OUT_SEL0 +#define UART_RTS__PRTDSI__OUT_SEL1 CYREG_PRT1_OUT_SEL1 +#define UART_RTS__PRTDSI__SYNC_OUT CYREG_PRT1_SYNC_OUT +#define UART_RTS__PS CYREG_PRT1_PS +#define UART_RTS__SHIFT 6u +#define UART_RTS__SLW CYREG_PRT1_SLW +#define UART_RTS_2__0__INTTYPE CYREG_PICU0_INTTYPE7 +#define UART_RTS_2__0__MASK 0x80u +#define UART_RTS_2__0__PC CYREG_PRT0_PC7 +#define UART_RTS_2__0__PORT 0u +#define UART_RTS_2__0__SHIFT 7u +#define UART_RTS_2__AG CYREG_PRT0_AG +#define UART_RTS_2__AMUX CYREG_PRT0_AMUX +#define UART_RTS_2__BIE CYREG_PRT0_BIE +#define UART_RTS_2__BIT_MASK CYREG_PRT0_BIT_MASK +#define UART_RTS_2__BYP CYREG_PRT0_BYP +#define UART_RTS_2__CTL CYREG_PRT0_CTL +#define UART_RTS_2__DM0 CYREG_PRT0_DM0 +#define UART_RTS_2__DM1 CYREG_PRT0_DM1 +#define UART_RTS_2__DM2 CYREG_PRT0_DM2 +#define UART_RTS_2__DR CYREG_PRT0_DR +#define UART_RTS_2__INP_DIS CYREG_PRT0_INP_DIS +#define UART_RTS_2__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE +#define UART_RTS_2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define UART_RTS_2__LCD_EN CYREG_PRT0_LCD_EN +#define UART_RTS_2__MASK 0x80u +#define UART_RTS_2__PORT 0u +#define UART_RTS_2__PRT CYREG_PRT0_PRT +#define UART_RTS_2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define UART_RTS_2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define UART_RTS_2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define UART_RTS_2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define UART_RTS_2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define UART_RTS_2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define UART_RTS_2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define UART_RTS_2__PS CYREG_PRT0_PS +#define UART_RTS_2__SHIFT 7u +#define UART_RTS_2__SLW CYREG_PRT0_SLW + +/* Clk_Brea1 */ +#define Clk_Brea1__CFG0 CYREG_CLKDIST_DCFG6_CFG0 +#define Clk_Brea1__CFG1 CYREG_CLKDIST_DCFG6_CFG1 +#define Clk_Brea1__CFG2 CYREG_CLKDIST_DCFG6_CFG2 +#define Clk_Brea1__CFG2_SRC_SEL_MASK 0x07u +#define Clk_Brea1__INDEX 0x06u +#define Clk_Brea1__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define Clk_Brea1__PM_ACT_MSK 0x40u +#define Clk_Brea1__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define Clk_Brea1__PM_STBY_MSK 0x40u + +/* Clk_Brea2 */ +#define Clk_Brea2__CFG0 CYREG_CLKDIST_DCFG5_CFG0 +#define Clk_Brea2__CFG1 CYREG_CLKDIST_DCFG5_CFG1 +#define Clk_Brea2__CFG2 CYREG_CLKDIST_DCFG5_CFG2 +#define Clk_Brea2__CFG2_SRC_SEL_MASK 0x07u +#define Clk_Brea2__INDEX 0x05u +#define Clk_Brea2__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define Clk_Brea2__PM_ACT_MSK 0x20u +#define Clk_Brea2__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define Clk_Brea2__PM_STBY_MSK 0x20u + +/* Clock_I2C */ +#define Clock_I2C__CFG0 CYREG_CLKDIST_DCFG0_CFG0 +#define Clock_I2C__CFG1 CYREG_CLKDIST_DCFG0_CFG1 +#define Clock_I2C__CFG2 CYREG_CLKDIST_DCFG0_CFG2 +#define Clock_I2C__CFG2_SRC_SEL_MASK 0x07u +#define Clock_I2C__INDEX 0x00u +#define Clock_I2C__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define Clock_I2C__PM_ACT_MSK 0x01u +#define Clock_I2C__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define Clock_I2C__PM_STBY_MSK 0x01u + +/* Clock_SPI */ +#define Clock_SPI__CFG0 CYREG_CLKDIST_DCFG1_CFG0 +#define Clock_SPI__CFG1 CYREG_CLKDIST_DCFG1_CFG1 +#define Clock_SPI__CFG2 CYREG_CLKDIST_DCFG1_CFG2 +#define Clock_SPI__CFG2_SRC_SEL_MASK 0x07u +#define Clock_SPI__INDEX 0x01u +#define Clock_SPI__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define Clock_SPI__PM_ACT_MSK 0x02u +#define Clock_SPI__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define Clock_SPI__PM_STBY_MSK 0x02u + +/* LED_Amber */ +#define LED_Amber__0__INTTYPE CYREG_PICU1_INTTYPE4 +#define LED_Amber__0__MASK 0x10u +#define LED_Amber__0__PC CYREG_PRT1_PC4 +#define LED_Amber__0__PORT 1u +#define LED_Amber__0__SHIFT 4u +#define LED_Amber__AG CYREG_PRT1_AG +#define LED_Amber__AMUX CYREG_PRT1_AMUX +#define LED_Amber__BIE CYREG_PRT1_BIE +#define LED_Amber__BIT_MASK CYREG_PRT1_BIT_MASK +#define LED_Amber__BYP CYREG_PRT1_BYP +#define LED_Amber__CTL CYREG_PRT1_CTL +#define LED_Amber__DM0 CYREG_PRT1_DM0 +#define LED_Amber__DM1 CYREG_PRT1_DM1 +#define LED_Amber__DM2 CYREG_PRT1_DM2 +#define LED_Amber__DR CYREG_PRT1_DR +#define LED_Amber__INP_DIS CYREG_PRT1_INP_DIS +#define LED_Amber__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU1_BASE +#define LED_Amber__LCD_COM_SEG CYREG_PRT1_LCD_COM_SEG +#define LED_Amber__LCD_EN CYREG_PRT1_LCD_EN +#define LED_Amber__MASK 0x10u +#define LED_Amber__PORT 1u +#define LED_Amber__PRT CYREG_PRT1_PRT +#define LED_Amber__PRTDSI__CAPS_SEL CYREG_PRT1_CAPS_SEL +#define LED_Amber__PRTDSI__DBL_SYNC_IN CYREG_PRT1_DBL_SYNC_IN +#define LED_Amber__PRTDSI__OE_SEL0 CYREG_PRT1_OE_SEL0 +#define LED_Amber__PRTDSI__OE_SEL1 CYREG_PRT1_OE_SEL1 +#define LED_Amber__PRTDSI__OUT_SEL0 CYREG_PRT1_OUT_SEL0 +#define LED_Amber__PRTDSI__OUT_SEL1 CYREG_PRT1_OUT_SEL1 +#define LED_Amber__PRTDSI__SYNC_OUT CYREG_PRT1_SYNC_OUT +#define LED_Amber__PS CYREG_PRT1_PS +#define LED_Amber__SHIFT 4u +#define LED_Amber__SLW CYREG_PRT1_SLW + +/* LED_Green */ +#define LED_Green__0__INTTYPE CYREG_PICU1_INTTYPE5 +#define LED_Green__0__MASK 0x20u +#define LED_Green__0__PC CYREG_PRT1_PC5 +#define LED_Green__0__PORT 1u +#define LED_Green__0__SHIFT 5u +#define LED_Green__AG CYREG_PRT1_AG +#define LED_Green__AMUX CYREG_PRT1_AMUX +#define LED_Green__BIE CYREG_PRT1_BIE +#define LED_Green__BIT_MASK CYREG_PRT1_BIT_MASK +#define LED_Green__BYP CYREG_PRT1_BYP +#define LED_Green__CTL CYREG_PRT1_CTL +#define LED_Green__DM0 CYREG_PRT1_DM0 +#define LED_Green__DM1 CYREG_PRT1_DM1 +#define LED_Green__DM2 CYREG_PRT1_DM2 +#define LED_Green__DR CYREG_PRT1_DR +#define LED_Green__INP_DIS CYREG_PRT1_INP_DIS +#define LED_Green__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU1_BASE +#define LED_Green__LCD_COM_SEG CYREG_PRT1_LCD_COM_SEG +#define LED_Green__LCD_EN CYREG_PRT1_LCD_EN +#define LED_Green__MASK 0x20u +#define LED_Green__PORT 1u +#define LED_Green__PRT CYREG_PRT1_PRT +#define LED_Green__PRTDSI__CAPS_SEL CYREG_PRT1_CAPS_SEL +#define LED_Green__PRTDSI__DBL_SYNC_IN CYREG_PRT1_DBL_SYNC_IN +#define LED_Green__PRTDSI__OE_SEL0 CYREG_PRT1_OE_SEL0 +#define LED_Green__PRTDSI__OE_SEL1 CYREG_PRT1_OE_SEL1 +#define LED_Green__PRTDSI__OUT_SEL0 CYREG_PRT1_OUT_SEL0 +#define LED_Green__PRTDSI__OUT_SEL1 CYREG_PRT1_OUT_SEL1 +#define LED_Green__PRTDSI__SYNC_OUT CYREG_PRT1_SYNC_OUT +#define LED_Green__PS CYREG_PRT1_PS +#define LED_Green__SHIFT 5u +#define LED_Green__SLW CYREG_PRT1_SLW + +/* UART_RX_2 */ +#define UART_RX_2__0__INTTYPE CYREG_PICU3_INTTYPE0 +#define UART_RX_2__0__MASK 0x01u +#define UART_RX_2__0__PC CYREG_PRT3_PC0 +#define UART_RX_2__0__PORT 3u +#define UART_RX_2__0__SHIFT 0u +#define UART_RX_2__AG CYREG_PRT3_AG +#define UART_RX_2__AMUX CYREG_PRT3_AMUX +#define UART_RX_2__BIE CYREG_PRT3_BIE +#define UART_RX_2__BIT_MASK CYREG_PRT3_BIT_MASK +#define UART_RX_2__BYP CYREG_PRT3_BYP +#define UART_RX_2__CTL CYREG_PRT3_CTL +#define UART_RX_2__DM0 CYREG_PRT3_DM0 +#define UART_RX_2__DM1 CYREG_PRT3_DM1 +#define UART_RX_2__DM2 CYREG_PRT3_DM2 +#define UART_RX_2__DR CYREG_PRT3_DR +#define UART_RX_2__INP_DIS CYREG_PRT3_INP_DIS +#define UART_RX_2__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define UART_RX_2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define UART_RX_2__LCD_EN CYREG_PRT3_LCD_EN +#define UART_RX_2__MASK 0x01u +#define UART_RX_2__PORT 3u +#define UART_RX_2__PRT CYREG_PRT3_PRT +#define UART_RX_2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define UART_RX_2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define UART_RX_2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define UART_RX_2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define UART_RX_2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define UART_RX_2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define UART_RX_2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define UART_RX_2__PS CYREG_PRT3_PS +#define UART_RX_2__SHIFT 0u +#define UART_RX_2__SLW CYREG_PRT3_SLW + +/* UART_TX_2 */ +#define UART_TX_2__0__INTTYPE CYREG_PICU0_INTTYPE3 +#define UART_TX_2__0__MASK 0x08u +#define UART_TX_2__0__PC CYREG_PRT0_PC3 +#define UART_TX_2__0__PORT 0u +#define UART_TX_2__0__SHIFT 3u +#define UART_TX_2__AG CYREG_PRT0_AG +#define UART_TX_2__AMUX CYREG_PRT0_AMUX +#define UART_TX_2__BIE CYREG_PRT0_BIE +#define UART_TX_2__BIT_MASK CYREG_PRT0_BIT_MASK +#define UART_TX_2__BYP CYREG_PRT0_BYP +#define UART_TX_2__CTL CYREG_PRT0_CTL +#define UART_TX_2__DM0 CYREG_PRT0_DM0 +#define UART_TX_2__DM1 CYREG_PRT0_DM1 +#define UART_TX_2__DM2 CYREG_PRT0_DM2 +#define UART_TX_2__DR CYREG_PRT0_DR +#define UART_TX_2__INP_DIS CYREG_PRT0_INP_DIS +#define UART_TX_2__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE +#define UART_TX_2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define UART_TX_2__LCD_EN CYREG_PRT0_LCD_EN +#define UART_TX_2__MASK 0x08u +#define UART_TX_2__PORT 0u +#define UART_TX_2__PRT CYREG_PRT0_PRT +#define UART_TX_2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define UART_TX_2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define UART_TX_2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define UART_TX_2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define UART_TX_2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define UART_TX_2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define UART_TX_2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define UART_TX_2__PS CYREG_PRT0_PS +#define UART_TX_2__SHIFT 3u +#define UART_TX_2__SLW CYREG_PRT0_SLW + +/* ADC_DelSig */ +#define ADC_DelSig_DEC__COHER CYREG_DEC_COHER +#define ADC_DelSig_DEC__CR CYREG_DEC_CR +#define ADC_DelSig_DEC__DR1 CYREG_DEC_DR1 +#define ADC_DelSig_DEC__DR2 CYREG_DEC_DR2 +#define ADC_DelSig_DEC__DR2H CYREG_DEC_DR2H +#define ADC_DelSig_DEC__GCOR CYREG_DEC_GCOR +#define ADC_DelSig_DEC__GCORH CYREG_DEC_GCORH +#define ADC_DelSig_DEC__GVAL CYREG_DEC_GVAL +#define ADC_DelSig_DEC__OCOR CYREG_DEC_OCOR +#define ADC_DelSig_DEC__OCORH CYREG_DEC_OCORH +#define ADC_DelSig_DEC__OCORM CYREG_DEC_OCORM +#define ADC_DelSig_DEC__OUTSAMP CYREG_DEC_OUTSAMP +#define ADC_DelSig_DEC__OUTSAMPH CYREG_DEC_OUTSAMPH +#define ADC_DelSig_DEC__OUTSAMPM CYREG_DEC_OUTSAMPM +#define ADC_DelSig_DEC__OUTSAMPS CYREG_DEC_OUTSAMPS +#define ADC_DelSig_DEC__PM_ACT_CFG CYREG_PM_ACT_CFG10 +#define ADC_DelSig_DEC__PM_ACT_MSK 0x01u +#define ADC_DelSig_DEC__PM_STBY_CFG CYREG_PM_STBY_CFG10 +#define ADC_DelSig_DEC__PM_STBY_MSK 0x01u +#define ADC_DelSig_DEC__SHIFT1 CYREG_DEC_SHIFT1 +#define ADC_DelSig_DEC__SHIFT2 CYREG_DEC_SHIFT2 +#define ADC_DelSig_DEC__SR CYREG_DEC_SR +#define ADC_DelSig_DEC__TRIM__M1 CYREG_FLSHID_CUST_TABLES_DEC_M1 +#define ADC_DelSig_DEC__TRIM__M2 CYREG_FLSHID_CUST_TABLES_DEC_M2 +#define ADC_DelSig_DEC__TRIM__M3 CYREG_FLSHID_CUST_TABLES_DEC_M3 +#define ADC_DelSig_DEC__TRIM__M4 CYREG_FLSHID_CUST_TABLES_DEC_M4 +#define ADC_DelSig_DEC__TRIM__M5 CYREG_FLSHID_CUST_TABLES_DEC_M5 +#define ADC_DelSig_DEC__TRIM__M6 CYREG_FLSHID_CUST_TABLES_DEC_M6 +#define ADC_DelSig_DEC__TRIM__M7 CYREG_FLSHID_CUST_TABLES_DEC_M7 +#define ADC_DelSig_DEC__TRIM__M8 CYREG_FLSHID_CUST_TABLES_DEC_M8 +#define ADC_DelSig_DSM__BUF0 CYREG_DSM0_BUF0 +#define ADC_DelSig_DSM__BUF1 CYREG_DSM0_BUF1 +#define ADC_DelSig_DSM__BUF2 CYREG_DSM0_BUF2 +#define ADC_DelSig_DSM__BUF3 CYREG_DSM0_BUF3 +#define ADC_DelSig_DSM__CLK CYREG_DSM0_CLK +#define ADC_DelSig_DSM__CR0 CYREG_DSM0_CR0 +#define ADC_DelSig_DSM__CR1 CYREG_DSM0_CR1 +#define ADC_DelSig_DSM__CR10 CYREG_DSM0_CR10 +#define ADC_DelSig_DSM__CR11 CYREG_DSM0_CR11 +#define ADC_DelSig_DSM__CR12 CYREG_DSM0_CR12 +#define ADC_DelSig_DSM__CR13 CYREG_DSM0_CR13 +#define ADC_DelSig_DSM__CR14 CYREG_DSM0_CR14 +#define ADC_DelSig_DSM__CR15 CYREG_DSM0_CR15 +#define ADC_DelSig_DSM__CR16 CYREG_DSM0_CR16 +#define ADC_DelSig_DSM__CR17 CYREG_DSM0_CR17 +#define ADC_DelSig_DSM__CR2 CYREG_DSM0_CR2 +#define ADC_DelSig_DSM__CR3 CYREG_DSM0_CR3 +#define ADC_DelSig_DSM__CR4 CYREG_DSM0_CR4 +#define ADC_DelSig_DSM__CR5 CYREG_DSM0_CR5 +#define ADC_DelSig_DSM__CR6 CYREG_DSM0_CR6 +#define ADC_DelSig_DSM__CR7 CYREG_DSM0_CR7 +#define ADC_DelSig_DSM__CR8 CYREG_DSM0_CR8 +#define ADC_DelSig_DSM__CR9 CYREG_DSM0_CR9 +#define ADC_DelSig_DSM__DEM0 CYREG_DSM0_DEM0 +#define ADC_DelSig_DSM__DEM1 CYREG_DSM0_DEM1 +#define ADC_DelSig_DSM__MISC CYREG_DSM0_MISC +#define ADC_DelSig_DSM__OUT0 CYREG_DSM0_OUT0 +#define ADC_DelSig_DSM__OUT1 CYREG_DSM0_OUT1 +#define ADC_DelSig_DSM__REF0 CYREG_DSM0_REF0 +#define ADC_DelSig_DSM__REF1 CYREG_DSM0_REF1 +#define ADC_DelSig_DSM__REF2 CYREG_DSM0_REF2 +#define ADC_DelSig_DSM__REF3 CYREG_DSM0_REF3 +#define ADC_DelSig_DSM__RSVD1 CYREG_DSM0_RSVD1 +#define ADC_DelSig_DSM__SW0 CYREG_DSM0_SW0 +#define ADC_DelSig_DSM__SW2 CYREG_DSM0_SW2 +#define ADC_DelSig_DSM__SW3 CYREG_DSM0_SW3 +#define ADC_DelSig_DSM__SW4 CYREG_DSM0_SW4 +#define ADC_DelSig_DSM__SW6 CYREG_DSM0_SW6 +#define ADC_DelSig_DSM__TR0 CYREG_NPUMP_DSM_TR0 +#define ADC_DelSig_DSM__TST0 CYREG_DSM0_TST0 +#define ADC_DelSig_DSM__TST1 CYREG_DSM0_TST1 +#define ADC_DelSig_Ext_CP_Clk__CFG0 CYREG_CLKDIST_DCFG4_CFG0 +#define ADC_DelSig_Ext_CP_Clk__CFG1 CYREG_CLKDIST_DCFG4_CFG1 +#define ADC_DelSig_Ext_CP_Clk__CFG2 CYREG_CLKDIST_DCFG4_CFG2 +#define ADC_DelSig_Ext_CP_Clk__CFG2_SRC_SEL_MASK 0x07u +#define ADC_DelSig_Ext_CP_Clk__INDEX 0x04u +#define ADC_DelSig_Ext_CP_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define ADC_DelSig_Ext_CP_Clk__PM_ACT_MSK 0x10u +#define ADC_DelSig_Ext_CP_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define ADC_DelSig_Ext_CP_Clk__PM_STBY_MSK 0x10u +#define ADC_DelSig_IRQ__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define ADC_DelSig_IRQ__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define ADC_DelSig_IRQ__INTC_MASK 0x20000000u +#define ADC_DelSig_IRQ__INTC_NUMBER 29u +#define ADC_DelSig_IRQ__INTC_PRIOR_NUM 6u +#define ADC_DelSig_IRQ__INTC_PRIOR_REG CYREG_NVIC_PRI_29 +#define ADC_DelSig_IRQ__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define ADC_DelSig_IRQ__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define ADC_DelSig_theACLK__CFG0 CYREG_CLKDIST_ACFG0_CFG0 +#define ADC_DelSig_theACLK__CFG1 CYREG_CLKDIST_ACFG0_CFG1 +#define ADC_DelSig_theACLK__CFG2 CYREG_CLKDIST_ACFG0_CFG2 +#define ADC_DelSig_theACLK__CFG2_SRC_SEL_MASK 0x07u +#define ADC_DelSig_theACLK__CFG3 CYREG_CLKDIST_ACFG0_CFG3 +#define ADC_DelSig_theACLK__CFG3_PHASE_DLY_MASK 0x0Fu +#define ADC_DelSig_theACLK__INDEX 0x00u +#define ADC_DelSig_theACLK__PM_ACT_CFG CYREG_PM_ACT_CFG1 +#define ADC_DelSig_theACLK__PM_ACT_MSK 0x01u +#define ADC_DelSig_theACLK__PM_STBY_CFG CYREG_PM_STBY_CFG1 +#define ADC_DelSig_theACLK__PM_STBY_MSK 0x01u + +/* Clock_UART */ +#define Clock_UART__CFG0 CYREG_CLKDIST_DCFG3_CFG0 +#define Clock_UART__CFG1 CYREG_CLKDIST_DCFG3_CFG1 +#define Clock_UART__CFG2 CYREG_CLKDIST_DCFG3_CFG2 +#define Clock_UART__CFG2_SRC_SEL_MASK 0x07u +#define Clock_UART__INDEX 0x03u +#define Clock_UART__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define Clock_UART__PM_ACT_MSK 0x08u +#define Clock_UART__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define Clock_UART__PM_STBY_MSK 0x08u +#define Clock_UART_2__CFG0 CYREG_CLKDIST_DCFG2_CFG0 +#define Clock_UART_2__CFG1 CYREG_CLKDIST_DCFG2_CFG1 +#define Clock_UART_2__CFG2 CYREG_CLKDIST_DCFG2_CFG2 +#define Clock_UART_2__CFG2_SRC_SEL_MASK 0x07u +#define Clock_UART_2__INDEX 0x02u +#define Clock_UART_2__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define Clock_UART_2__PM_ACT_MSK 0x04u +#define Clock_UART_2__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define Clock_UART_2__PM_STBY_MSK 0x04u + +/* DIGPOT_SCL */ +#define DIGPOT_SCL__0__INTTYPE CYREG_PICU2_INTTYPE5 +#define DIGPOT_SCL__0__MASK 0x20u +#define DIGPOT_SCL__0__PC CYREG_PRT2_PC5 +#define DIGPOT_SCL__0__PORT 2u +#define DIGPOT_SCL__0__SHIFT 5u +#define DIGPOT_SCL__AG CYREG_PRT2_AG +#define DIGPOT_SCL__AMUX CYREG_PRT2_AMUX +#define DIGPOT_SCL__BIE CYREG_PRT2_BIE +#define DIGPOT_SCL__BIT_MASK CYREG_PRT2_BIT_MASK +#define DIGPOT_SCL__BYP CYREG_PRT2_BYP +#define DIGPOT_SCL__CTL CYREG_PRT2_CTL +#define DIGPOT_SCL__DM0 CYREG_PRT2_DM0 +#define DIGPOT_SCL__DM1 CYREG_PRT2_DM1 +#define DIGPOT_SCL__DM2 CYREG_PRT2_DM2 +#define DIGPOT_SCL__DR CYREG_PRT2_DR +#define DIGPOT_SCL__INP_DIS CYREG_PRT2_INP_DIS +#define DIGPOT_SCL__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU2_BASE +#define DIGPOT_SCL__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define DIGPOT_SCL__LCD_EN CYREG_PRT2_LCD_EN +#define DIGPOT_SCL__MASK 0x20u +#define DIGPOT_SCL__PORT 2u +#define DIGPOT_SCL__PRT CYREG_PRT2_PRT +#define DIGPOT_SCL__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define DIGPOT_SCL__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define DIGPOT_SCL__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define DIGPOT_SCL__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define DIGPOT_SCL__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define DIGPOT_SCL__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define DIGPOT_SCL__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define DIGPOT_SCL__PS CYREG_PRT2_PS +#define DIGPOT_SCL__SHIFT 5u +#define DIGPOT_SCL__SLW CYREG_PRT2_SLW + +/* DIGPOT_SDA */ +#define DIGPOT_SDA__0__INTTYPE CYREG_PICU2_INTTYPE6 +#define DIGPOT_SDA__0__MASK 0x40u +#define DIGPOT_SDA__0__PC CYREG_PRT2_PC6 +#define DIGPOT_SDA__0__PORT 2u +#define DIGPOT_SDA__0__SHIFT 6u +#define DIGPOT_SDA__AG CYREG_PRT2_AG +#define DIGPOT_SDA__AMUX CYREG_PRT2_AMUX +#define DIGPOT_SDA__BIE CYREG_PRT2_BIE +#define DIGPOT_SDA__BIT_MASK CYREG_PRT2_BIT_MASK +#define DIGPOT_SDA__BYP CYREG_PRT2_BYP +#define DIGPOT_SDA__CTL CYREG_PRT2_CTL +#define DIGPOT_SDA__DM0 CYREG_PRT2_DM0 +#define DIGPOT_SDA__DM1 CYREG_PRT2_DM1 +#define DIGPOT_SDA__DM2 CYREG_PRT2_DM2 +#define DIGPOT_SDA__DR CYREG_PRT2_DR +#define DIGPOT_SDA__INP_DIS CYREG_PRT2_INP_DIS +#define DIGPOT_SDA__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU2_BASE +#define DIGPOT_SDA__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define DIGPOT_SDA__LCD_EN CYREG_PRT2_LCD_EN +#define DIGPOT_SDA__MASK 0x40u +#define DIGPOT_SDA__PORT 2u +#define DIGPOT_SDA__PRT CYREG_PRT2_PRT +#define DIGPOT_SDA__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define DIGPOT_SDA__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define DIGPOT_SDA__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define DIGPOT_SDA__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define DIGPOT_SDA__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define DIGPOT_SDA__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define DIGPOT_SDA__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define DIGPOT_SDA__PS CYREG_PRT2_PS +#define DIGPOT_SDA__SHIFT 6u +#define DIGPOT_SDA__SLW CYREG_PRT2_SLW + +/* ModeButton */ +#define ModeButton__0__INTTYPE CYREG_PICU1_INTTYPE2 +#define ModeButton__0__MASK 0x04u +#define ModeButton__0__PC CYREG_PRT1_PC2 +#define ModeButton__0__PORT 1u +#define ModeButton__0__SHIFT 2u +#define ModeButton__AG CYREG_PRT1_AG +#define ModeButton__AMUX CYREG_PRT1_AMUX +#define ModeButton__BIE CYREG_PRT1_BIE +#define ModeButton__BIT_MASK CYREG_PRT1_BIT_MASK +#define ModeButton__BYP CYREG_PRT1_BYP +#define ModeButton__CTL CYREG_PRT1_CTL +#define ModeButton__DM0 CYREG_PRT1_DM0 +#define ModeButton__DM1 CYREG_PRT1_DM1 +#define ModeButton__DM2 CYREG_PRT1_DM2 +#define ModeButton__DR CYREG_PRT1_DR +#define ModeButton__INP_DIS CYREG_PRT1_INP_DIS +#define ModeButton__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU1_BASE +#define ModeButton__LCD_COM_SEG CYREG_PRT1_LCD_COM_SEG +#define ModeButton__LCD_EN CYREG_PRT1_LCD_EN +#define ModeButton__MASK 0x04u +#define ModeButton__PORT 1u +#define ModeButton__PRT CYREG_PRT1_PRT +#define ModeButton__PRTDSI__CAPS_SEL CYREG_PRT1_CAPS_SEL +#define ModeButton__PRTDSI__DBL_SYNC_IN CYREG_PRT1_DBL_SYNC_IN +#define ModeButton__PRTDSI__OE_SEL0 CYREG_PRT1_OE_SEL0 +#define ModeButton__PRTDSI__OE_SEL1 CYREG_PRT1_OE_SEL1 +#define ModeButton__PRTDSI__OUT_SEL0 CYREG_PRT1_OUT_SEL0 +#define ModeButton__PRTDSI__OUT_SEL1 CYREG_PRT1_OUT_SEL1 +#define ModeButton__PRTDSI__SYNC_OUT CYREG_PRT1_SYNC_OUT +#define ModeButton__PS CYREG_PRT1_PS +#define ModeButton__SHIFT 2u +#define ModeButton__SLW CYREG_PRT1_SLW + +/* Pin_I2C_SCL */ +#define Pin_I2C_SCL__0__INTTYPE CYREG_PICU12_INTTYPE0 +#define Pin_I2C_SCL__0__MASK 0x01u +#define Pin_I2C_SCL__0__PC CYREG_PRT12_PC0 +#define Pin_I2C_SCL__0__PORT 12u +#define Pin_I2C_SCL__0__SHIFT 0u +#define Pin_I2C_SCL__AG CYREG_PRT12_AG +#define Pin_I2C_SCL__BIE CYREG_PRT12_BIE +#define Pin_I2C_SCL__BIT_MASK CYREG_PRT12_BIT_MASK +#define Pin_I2C_SCL__BYP CYREG_PRT12_BYP +#define Pin_I2C_SCL__DM0 CYREG_PRT12_DM0 +#define Pin_I2C_SCL__DM1 CYREG_PRT12_DM1 +#define Pin_I2C_SCL__DM2 CYREG_PRT12_DM2 +#define Pin_I2C_SCL__DR CYREG_PRT12_DR +#define Pin_I2C_SCL__INP_DIS CYREG_PRT12_INP_DIS +#define Pin_I2C_SCL__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE +#define Pin_I2C_SCL__MASK 0x01u +#define Pin_I2C_SCL__PORT 12u +#define Pin_I2C_SCL__PRT CYREG_PRT12_PRT +#define Pin_I2C_SCL__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define Pin_I2C_SCL__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define Pin_I2C_SCL__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define Pin_I2C_SCL__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define Pin_I2C_SCL__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define Pin_I2C_SCL__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define Pin_I2C_SCL__PS CYREG_PRT12_PS +#define Pin_I2C_SCL__SHIFT 0u +#define Pin_I2C_SCL__SIO_CFG CYREG_PRT12_SIO_CFG +#define Pin_I2C_SCL__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define Pin_I2C_SCL__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define Pin_I2C_SCL__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define Pin_I2C_SCL__SLW CYREG_PRT12_SLW + +/* Pin_I2C_SDA */ +#define Pin_I2C_SDA__0__INTTYPE CYREG_PICU12_INTTYPE1 +#define Pin_I2C_SDA__0__MASK 0x02u +#define Pin_I2C_SDA__0__PC CYREG_PRT12_PC1 +#define Pin_I2C_SDA__0__PORT 12u +#define Pin_I2C_SDA__0__SHIFT 1u +#define Pin_I2C_SDA__AG CYREG_PRT12_AG +#define Pin_I2C_SDA__BIE CYREG_PRT12_BIE +#define Pin_I2C_SDA__BIT_MASK CYREG_PRT12_BIT_MASK +#define Pin_I2C_SDA__BYP CYREG_PRT12_BYP +#define Pin_I2C_SDA__DM0 CYREG_PRT12_DM0 +#define Pin_I2C_SDA__DM1 CYREG_PRT12_DM1 +#define Pin_I2C_SDA__DM2 CYREG_PRT12_DM2 +#define Pin_I2C_SDA__DR CYREG_PRT12_DR +#define Pin_I2C_SDA__INP_DIS CYREG_PRT12_INP_DIS +#define Pin_I2C_SDA__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE +#define Pin_I2C_SDA__MASK 0x02u +#define Pin_I2C_SDA__PORT 12u +#define Pin_I2C_SDA__PRT CYREG_PRT12_PRT +#define Pin_I2C_SDA__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define Pin_I2C_SDA__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define Pin_I2C_SDA__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define Pin_I2C_SDA__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define Pin_I2C_SDA__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define Pin_I2C_SDA__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define Pin_I2C_SDA__PS CYREG_PRT12_PS +#define Pin_I2C_SDA__SHIFT 1u +#define Pin_I2C_SDA__SIO_CFG CYREG_PRT12_SIO_CFG +#define Pin_I2C_SDA__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define Pin_I2C_SDA__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define Pin_I2C_SDA__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define Pin_I2C_SDA__SLW CYREG_PRT12_SLW + +/* Pin_UART_Rx */ +#define Pin_UART_Rx__0__INTTYPE CYREG_PICU12_INTTYPE7 +#define Pin_UART_Rx__0__MASK 0x80u +#define Pin_UART_Rx__0__PC CYREG_PRT12_PC7 +#define Pin_UART_Rx__0__PORT 12u +#define Pin_UART_Rx__0__SHIFT 7u +#define Pin_UART_Rx__AG CYREG_PRT12_AG +#define Pin_UART_Rx__BIE CYREG_PRT12_BIE +#define Pin_UART_Rx__BIT_MASK CYREG_PRT12_BIT_MASK +#define Pin_UART_Rx__BYP CYREG_PRT12_BYP +#define Pin_UART_Rx__DM0 CYREG_PRT12_DM0 +#define Pin_UART_Rx__DM1 CYREG_PRT12_DM1 +#define Pin_UART_Rx__DM2 CYREG_PRT12_DM2 +#define Pin_UART_Rx__DR CYREG_PRT12_DR +#define Pin_UART_Rx__INP_DIS CYREG_PRT12_INP_DIS +#define Pin_UART_Rx__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE +#define Pin_UART_Rx__MASK 0x80u +#define Pin_UART_Rx__PORT 12u +#define Pin_UART_Rx__PRT CYREG_PRT12_PRT +#define Pin_UART_Rx__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define Pin_UART_Rx__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define Pin_UART_Rx__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define Pin_UART_Rx__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define Pin_UART_Rx__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define Pin_UART_Rx__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define Pin_UART_Rx__PS CYREG_PRT12_PS +#define Pin_UART_Rx__SHIFT 7u +#define Pin_UART_Rx__SIO_CFG CYREG_PRT12_SIO_CFG +#define Pin_UART_Rx__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define Pin_UART_Rx__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define Pin_UART_Rx__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define Pin_UART_Rx__SLW CYREG_PRT12_SLW + +/* Pin_UART_Tx */ +#define Pin_UART_Tx__0__INTTYPE CYREG_PICU12_INTTYPE6 +#define Pin_UART_Tx__0__MASK 0x40u +#define Pin_UART_Tx__0__PC CYREG_PRT12_PC6 +#define Pin_UART_Tx__0__PORT 12u +#define Pin_UART_Tx__0__SHIFT 6u +#define Pin_UART_Tx__AG CYREG_PRT12_AG +#define Pin_UART_Tx__BIE CYREG_PRT12_BIE +#define Pin_UART_Tx__BIT_MASK CYREG_PRT12_BIT_MASK +#define Pin_UART_Tx__BYP CYREG_PRT12_BYP +#define Pin_UART_Tx__DM0 CYREG_PRT12_DM0 +#define Pin_UART_Tx__DM1 CYREG_PRT12_DM1 +#define Pin_UART_Tx__DM2 CYREG_PRT12_DM2 +#define Pin_UART_Tx__DR CYREG_PRT12_DR +#define Pin_UART_Tx__INP_DIS CYREG_PRT12_INP_DIS +#define Pin_UART_Tx__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE +#define Pin_UART_Tx__MASK 0x40u +#define Pin_UART_Tx__PORT 12u +#define Pin_UART_Tx__PRT CYREG_PRT12_PRT +#define Pin_UART_Tx__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define Pin_UART_Tx__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define Pin_UART_Tx__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define Pin_UART_Tx__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define Pin_UART_Tx__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define Pin_UART_Tx__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define Pin_UART_Tx__PS CYREG_PRT12_PS +#define Pin_UART_Tx__SHIFT 6u +#define Pin_UART_Tx__SIO_CFG CYREG_PRT12_SIO_CFG +#define Pin_UART_Tx__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define Pin_UART_Tx__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define Pin_UART_Tx__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define Pin_UART_Tx__SLW CYREG_PRT12_SLW + +/* Pin_VTarget */ +#define Pin_VTarget__0__INTTYPE CYREG_PICU3_INTTYPE3 +#define Pin_VTarget__0__MASK 0x08u +#define Pin_VTarget__0__PC CYREG_PRT3_PC3 +#define Pin_VTarget__0__PORT 3u +#define Pin_VTarget__0__SHIFT 3u +#define Pin_VTarget__AG CYREG_PRT3_AG +#define Pin_VTarget__AMUX CYREG_PRT3_AMUX +#define Pin_VTarget__BIE CYREG_PRT3_BIE +#define Pin_VTarget__BIT_MASK CYREG_PRT3_BIT_MASK +#define Pin_VTarget__BYP CYREG_PRT3_BYP +#define Pin_VTarget__CTL CYREG_PRT3_CTL +#define Pin_VTarget__DM0 CYREG_PRT3_DM0 +#define Pin_VTarget__DM1 CYREG_PRT3_DM1 +#define Pin_VTarget__DM2 CYREG_PRT3_DM2 +#define Pin_VTarget__DR CYREG_PRT3_DR +#define Pin_VTarget__INP_DIS CYREG_PRT3_INP_DIS +#define Pin_VTarget__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define Pin_VTarget__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define Pin_VTarget__LCD_EN CYREG_PRT3_LCD_EN +#define Pin_VTarget__MASK 0x08u +#define Pin_VTarget__PORT 3u +#define Pin_VTarget__PRT CYREG_PRT3_PRT +#define Pin_VTarget__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define Pin_VTarget__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define Pin_VTarget__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define Pin_VTarget__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define Pin_VTarget__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define Pin_VTarget__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define Pin_VTarget__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define Pin_VTarget__PS CYREG_PRT3_PS +#define Pin_VTarget__SHIFT 3u +#define Pin_VTarget__SLW CYREG_PRT3_SLW + +/* SPI_SS_CTRL */ +#define SPI_SS_CTRL_Sync_ctrl_reg__0__MASK 0x01u +#define SPI_SS_CTRL_Sync_ctrl_reg__0__POS 0 +#define SPI_SS_CTRL_Sync_ctrl_reg__1__MASK 0x02u +#define SPI_SS_CTRL_Sync_ctrl_reg__1__POS 1 +#define SPI_SS_CTRL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL +#define SPI_SS_CTRL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL +#define SPI_SS_CTRL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL +#define SPI_SS_CTRL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL +#define SPI_SS_CTRL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL +#define SPI_SS_CTRL_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK +#define SPI_SS_CTRL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK +#define SPI_SS_CTRL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK +#define SPI_SS_CTRL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK +#define SPI_SS_CTRL_Sync_ctrl_reg__2__MASK 0x04u +#define SPI_SS_CTRL_Sync_ctrl_reg__2__POS 2 +#define SPI_SS_CTRL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL +#define SPI_SS_CTRL_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB05_CTL +#define SPI_SS_CTRL_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL +#define SPI_SS_CTRL_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB05_CTL +#define SPI_SS_CTRL_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL +#define SPI_SS_CTRL_Sync_ctrl_reg__MASK 0x07u +#define SPI_SS_CTRL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SPI_SS_CTRL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SPI_SS_CTRL_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB05_MSK + +/* UART_Bridge */ +#define UART_Bridge_2_BUART_sRX_RxBitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL +#define UART_Bridge_2_BUART_sRX_RxBitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB08_09_CTL +#define UART_Bridge_2_BUART_sRX_RxBitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB08_09_CTL +#define UART_Bridge_2_BUART_sRX_RxBitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB08_09_CTL +#define UART_Bridge_2_BUART_sRX_RxBitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB08_09_CTL +#define UART_Bridge_2_BUART_sRX_RxBitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB08_09_MSK +#define UART_Bridge_2_BUART_sRX_RxBitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB08_09_MSK +#define UART_Bridge_2_BUART_sRX_RxBitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB08_09_MSK +#define UART_Bridge_2_BUART_sRX_RxBitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB08_09_MSK +#define UART_Bridge_2_BUART_sRX_RxBitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB08_ACTL +#define UART_Bridge_2_BUART_sRX_RxBitCounter__CONTROL_REG CYREG_B1_UDB08_CTL +#define UART_Bridge_2_BUART_sRX_RxBitCounter__CONTROL_ST_REG CYREG_B1_UDB08_ST_CTL +#define UART_Bridge_2_BUART_sRX_RxBitCounter__COUNT_REG CYREG_B1_UDB08_CTL +#define UART_Bridge_2_BUART_sRX_RxBitCounter__COUNT_ST_REG CYREG_B1_UDB08_ST_CTL +#define UART_Bridge_2_BUART_sRX_RxBitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL +#define UART_Bridge_2_BUART_sRX_RxBitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL +#define UART_Bridge_2_BUART_sRX_RxBitCounter__PERIOD_REG CYREG_B1_UDB08_MSK +#define UART_Bridge_2_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL +#define UART_Bridge_2_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST +#define UART_Bridge_2_BUART_sRX_RxBitCounter_ST__MASK_REG CYREG_B1_UDB08_MSK +#define UART_Bridge_2_BUART_sRX_RxBitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL +#define UART_Bridge_2_BUART_sRX_RxBitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL +#define UART_Bridge_2_BUART_sRX_RxBitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL +#define UART_Bridge_2_BUART_sRX_RxBitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB08_ST_CTL +#define UART_Bridge_2_BUART_sRX_RxBitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB08_ST_CTL +#define UART_Bridge_2_BUART_sRX_RxBitCounter_ST__STATUS_REG CYREG_B1_UDB08_ST +#define UART_Bridge_2_BUART_sRX_RxShifter_u0__16BIT_A0_REG CYREG_B1_UDB10_11_A0 +#define UART_Bridge_2_BUART_sRX_RxShifter_u0__16BIT_A1_REG CYREG_B1_UDB10_11_A1 +#define UART_Bridge_2_BUART_sRX_RxShifter_u0__16BIT_D0_REG CYREG_B1_UDB10_11_D0 +#define UART_Bridge_2_BUART_sRX_RxShifter_u0__16BIT_D1_REG CYREG_B1_UDB10_11_D1 +#define UART_Bridge_2_BUART_sRX_RxShifter_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL +#define UART_Bridge_2_BUART_sRX_RxShifter_u0__16BIT_F0_REG CYREG_B1_UDB10_11_F0 +#define UART_Bridge_2_BUART_sRX_RxShifter_u0__16BIT_F1_REG CYREG_B1_UDB10_11_F1 +#define UART_Bridge_2_BUART_sRX_RxShifter_u0__A0_A1_REG CYREG_B1_UDB10_A0_A1 +#define UART_Bridge_2_BUART_sRX_RxShifter_u0__A0_REG CYREG_B1_UDB10_A0 +#define UART_Bridge_2_BUART_sRX_RxShifter_u0__A1_REG CYREG_B1_UDB10_A1 +#define UART_Bridge_2_BUART_sRX_RxShifter_u0__D0_D1_REG CYREG_B1_UDB10_D0_D1 +#define UART_Bridge_2_BUART_sRX_RxShifter_u0__D0_REG CYREG_B1_UDB10_D0 +#define UART_Bridge_2_BUART_sRX_RxShifter_u0__D1_REG CYREG_B1_UDB10_D1 +#define UART_Bridge_2_BUART_sRX_RxShifter_u0__DP_AUX_CTL_REG CYREG_B1_UDB10_ACTL +#define UART_Bridge_2_BUART_sRX_RxShifter_u0__F0_F1_REG CYREG_B1_UDB10_F0_F1 +#define UART_Bridge_2_BUART_sRX_RxShifter_u0__F0_REG CYREG_B1_UDB10_F0 +#define UART_Bridge_2_BUART_sRX_RxShifter_u0__F1_REG CYREG_B1_UDB10_F1 +#define UART_Bridge_2_BUART_sRX_RxSts__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL +#define UART_Bridge_2_BUART_sRX_RxSts__16BIT_STATUS_REG CYREG_B1_UDB10_11_ST +#define UART_Bridge_2_BUART_sRX_RxSts__3__MASK 0x08u +#define UART_Bridge_2_BUART_sRX_RxSts__3__POS 3 +#define UART_Bridge_2_BUART_sRX_RxSts__4__MASK 0x10u +#define UART_Bridge_2_BUART_sRX_RxSts__4__POS 4 +#define UART_Bridge_2_BUART_sRX_RxSts__5__MASK 0x20u +#define UART_Bridge_2_BUART_sRX_RxSts__5__POS 5 +#define UART_Bridge_2_BUART_sRX_RxSts__MASK 0x38u +#define UART_Bridge_2_BUART_sRX_RxSts__MASK_REG CYREG_B1_UDB10_MSK +#define UART_Bridge_2_BUART_sRX_RxSts__STATUS_AUX_CTL_REG CYREG_B1_UDB10_ACTL +#define UART_Bridge_2_BUART_sRX_RxSts__STATUS_REG CYREG_B1_UDB10_ST +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG CYREG_B1_UDB08_09_A0 +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG CYREG_B1_UDB08_09_A1 +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG CYREG_B1_UDB08_09_D0 +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG CYREG_B1_UDB08_09_D1 +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG CYREG_B1_UDB08_09_F0 +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG CYREG_B1_UDB08_09_F1 +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG CYREG_B1_UDB08_A0_A1 +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG CYREG_B1_UDB08_A0 +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG CYREG_B1_UDB08_A1 +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG CYREG_B1_UDB08_D0_D1 +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG CYREG_B1_UDB08_D0 +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG CYREG_B1_UDB08_D1 +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG CYREG_B1_UDB08_ACTL +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG CYREG_B1_UDB08_F0_F1 +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG CYREG_B1_UDB08_F0 +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG CYREG_B1_UDB08_F1 +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__MSK_DP_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL +#define UART_Bridge_2_BUART_sTX_sCLOCK_TxBitClkGen__PER_DP_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL +#define UART_Bridge_2_BUART_sTX_TxShifter_u0__16BIT_A0_REG CYREG_B0_UDB08_09_A0 +#define UART_Bridge_2_BUART_sTX_TxShifter_u0__16BIT_A1_REG CYREG_B0_UDB08_09_A1 +#define UART_Bridge_2_BUART_sTX_TxShifter_u0__16BIT_D0_REG CYREG_B0_UDB08_09_D0 +#define UART_Bridge_2_BUART_sTX_TxShifter_u0__16BIT_D1_REG CYREG_B0_UDB08_09_D1 +#define UART_Bridge_2_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL +#define UART_Bridge_2_BUART_sTX_TxShifter_u0__16BIT_F0_REG CYREG_B0_UDB08_09_F0 +#define UART_Bridge_2_BUART_sTX_TxShifter_u0__16BIT_F1_REG CYREG_B0_UDB08_09_F1 +#define UART_Bridge_2_BUART_sTX_TxShifter_u0__A0_A1_REG CYREG_B0_UDB08_A0_A1 +#define UART_Bridge_2_BUART_sTX_TxShifter_u0__A0_REG CYREG_B0_UDB08_A0 +#define UART_Bridge_2_BUART_sTX_TxShifter_u0__A1_REG CYREG_B0_UDB08_A1 +#define UART_Bridge_2_BUART_sTX_TxShifter_u0__D0_D1_REG CYREG_B0_UDB08_D0_D1 +#define UART_Bridge_2_BUART_sTX_TxShifter_u0__D0_REG CYREG_B0_UDB08_D0 +#define UART_Bridge_2_BUART_sTX_TxShifter_u0__D1_REG CYREG_B0_UDB08_D1 +#define UART_Bridge_2_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG CYREG_B0_UDB08_ACTL +#define UART_Bridge_2_BUART_sTX_TxShifter_u0__F0_F1_REG CYREG_B0_UDB08_F0_F1 +#define UART_Bridge_2_BUART_sTX_TxShifter_u0__F0_REG CYREG_B0_UDB08_F0 +#define UART_Bridge_2_BUART_sTX_TxShifter_u0__F1_REG CYREG_B0_UDB08_F1 +#define UART_Bridge_2_BUART_sTX_TxSts__0__MASK 0x01u +#define UART_Bridge_2_BUART_sTX_TxSts__0__POS 0 +#define UART_Bridge_2_BUART_sTX_TxSts__1__MASK 0x02u +#define UART_Bridge_2_BUART_sTX_TxSts__1__POS 1 +#define UART_Bridge_2_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL +#define UART_Bridge_2_BUART_sTX_TxSts__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST +#define UART_Bridge_2_BUART_sTX_TxSts__2__MASK 0x04u +#define UART_Bridge_2_BUART_sTX_TxSts__2__POS 2 +#define UART_Bridge_2_BUART_sTX_TxSts__3__MASK 0x08u +#define UART_Bridge_2_BUART_sTX_TxSts__3__POS 3 +#define UART_Bridge_2_BUART_sTX_TxSts__MASK 0x0Fu +#define UART_Bridge_2_BUART_sTX_TxSts__MASK_REG CYREG_B0_UDB09_MSK +#define UART_Bridge_2_BUART_sTX_TxSts__MASK_ST_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL +#define UART_Bridge_2_BUART_sTX_TxSts__PER_ST_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL +#define UART_Bridge_2_BUART_sTX_TxSts__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL +#define UART_Bridge_2_BUART_sTX_TxSts__STATUS_CNT_REG CYREG_B0_UDB09_ST_CTL +#define UART_Bridge_2_BUART_sTX_TxSts__STATUS_CONTROL_REG CYREG_B0_UDB09_ST_CTL +#define UART_Bridge_2_BUART_sTX_TxSts__STATUS_REG CYREG_B0_UDB09_ST +#define UART_Bridge_2_RXInternalInterrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define UART_Bridge_2_RXInternalInterrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define UART_Bridge_2_RXInternalInterrupt__INTC_MASK 0x08u +#define UART_Bridge_2_RXInternalInterrupt__INTC_NUMBER 3u +#define UART_Bridge_2_RXInternalInterrupt__INTC_PRIOR_NUM 7u +#define UART_Bridge_2_RXInternalInterrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_3 +#define UART_Bridge_2_RXInternalInterrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define UART_Bridge_2_RXInternalInterrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define UART_Bridge_2_TXInternalInterrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define UART_Bridge_2_TXInternalInterrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define UART_Bridge_2_TXInternalInterrupt__INTC_MASK 0x10u +#define UART_Bridge_2_TXInternalInterrupt__INTC_NUMBER 4u +#define UART_Bridge_2_TXInternalInterrupt__INTC_PRIOR_NUM 7u +#define UART_Bridge_2_TXInternalInterrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_4 +#define UART_Bridge_2_TXInternalInterrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define UART_Bridge_2_TXInternalInterrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define UART_Bridge_BUART_sRX_RxBitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL +#define UART_Bridge_BUART_sRX_RxBitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL +#define UART_Bridge_BUART_sRX_RxBitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL +#define UART_Bridge_BUART_sRX_RxBitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL +#define UART_Bridge_BUART_sRX_RxBitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL +#define UART_Bridge_BUART_sRX_RxBitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK +#define UART_Bridge_BUART_sRX_RxBitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK +#define UART_Bridge_BUART_sRX_RxBitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK +#define UART_Bridge_BUART_sRX_RxBitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK +#define UART_Bridge_BUART_sRX_RxBitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL +#define UART_Bridge_BUART_sRX_RxBitCounter__CONTROL_REG CYREG_B0_UDB13_CTL +#define UART_Bridge_BUART_sRX_RxBitCounter__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL +#define UART_Bridge_BUART_sRX_RxBitCounter__COUNT_REG CYREG_B0_UDB13_CTL +#define UART_Bridge_BUART_sRX_RxBitCounter__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL +#define UART_Bridge_BUART_sRX_RxBitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define UART_Bridge_BUART_sRX_RxBitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define UART_Bridge_BUART_sRX_RxBitCounter__PERIOD_REG CYREG_B0_UDB13_MSK +#define UART_Bridge_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL +#define UART_Bridge_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST +#define UART_Bridge_BUART_sRX_RxBitCounter_ST__MASK_REG CYREG_B0_UDB13_MSK +#define UART_Bridge_BUART_sRX_RxBitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define UART_Bridge_BUART_sRX_RxBitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define UART_Bridge_BUART_sRX_RxBitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL +#define UART_Bridge_BUART_sRX_RxBitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB13_ST_CTL +#define UART_Bridge_BUART_sRX_RxBitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB13_ST_CTL +#define UART_Bridge_BUART_sRX_RxBitCounter_ST__STATUS_REG CYREG_B0_UDB13_ST +#define UART_Bridge_BUART_sRX_RxShifter_u0__16BIT_A0_REG CYREG_B0_UDB14_15_A0 +#define UART_Bridge_BUART_sRX_RxShifter_u0__16BIT_A1_REG CYREG_B0_UDB14_15_A1 +#define UART_Bridge_BUART_sRX_RxShifter_u0__16BIT_D0_REG CYREG_B0_UDB14_15_D0 +#define UART_Bridge_BUART_sRX_RxShifter_u0__16BIT_D1_REG CYREG_B0_UDB14_15_D1 +#define UART_Bridge_BUART_sRX_RxShifter_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL +#define UART_Bridge_BUART_sRX_RxShifter_u0__16BIT_F0_REG CYREG_B0_UDB14_15_F0 +#define UART_Bridge_BUART_sRX_RxShifter_u0__16BIT_F1_REG CYREG_B0_UDB14_15_F1 +#define UART_Bridge_BUART_sRX_RxShifter_u0__A0_A1_REG CYREG_B0_UDB14_A0_A1 +#define UART_Bridge_BUART_sRX_RxShifter_u0__A0_REG CYREG_B0_UDB14_A0 +#define UART_Bridge_BUART_sRX_RxShifter_u0__A1_REG CYREG_B0_UDB14_A1 +#define UART_Bridge_BUART_sRX_RxShifter_u0__D0_D1_REG CYREG_B0_UDB14_D0_D1 +#define UART_Bridge_BUART_sRX_RxShifter_u0__D0_REG CYREG_B0_UDB14_D0 +#define UART_Bridge_BUART_sRX_RxShifter_u0__D1_REG CYREG_B0_UDB14_D1 +#define UART_Bridge_BUART_sRX_RxShifter_u0__DP_AUX_CTL_REG CYREG_B0_UDB14_ACTL +#define UART_Bridge_BUART_sRX_RxShifter_u0__F0_F1_REG CYREG_B0_UDB14_F0_F1 +#define UART_Bridge_BUART_sRX_RxShifter_u0__F0_REG CYREG_B0_UDB14_F0 +#define UART_Bridge_BUART_sRX_RxShifter_u0__F1_REG CYREG_B0_UDB14_F1 +#define UART_Bridge_BUART_sRX_RxSts__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL +#define UART_Bridge_BUART_sRX_RxSts__16BIT_STATUS_REG CYREG_B0_UDB10_11_ST +#define UART_Bridge_BUART_sRX_RxSts__3__MASK 0x08u +#define UART_Bridge_BUART_sRX_RxSts__3__POS 3 +#define UART_Bridge_BUART_sRX_RxSts__4__MASK 0x10u +#define UART_Bridge_BUART_sRX_RxSts__4__POS 4 +#define UART_Bridge_BUART_sRX_RxSts__5__MASK 0x20u +#define UART_Bridge_BUART_sRX_RxSts__5__POS 5 +#define UART_Bridge_BUART_sRX_RxSts__MASK 0x38u +#define UART_Bridge_BUART_sRX_RxSts__MASK_REG CYREG_B0_UDB10_MSK +#define UART_Bridge_BUART_sRX_RxSts__STATUS_AUX_CTL_REG CYREG_B0_UDB10_ACTL +#define UART_Bridge_BUART_sRX_RxSts__STATUS_REG CYREG_B0_UDB10_ST +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG CYREG_B0_UDB13_14_A0 +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG CYREG_B0_UDB13_14_A1 +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG CYREG_B0_UDB13_14_D0 +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG CYREG_B0_UDB13_14_D1 +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG CYREG_B0_UDB13_14_F0 +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG CYREG_B0_UDB13_14_F1 +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG CYREG_B0_UDB13_A0_A1 +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG CYREG_B0_UDB13_A0 +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG CYREG_B0_UDB13_A1 +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG CYREG_B0_UDB13_D0_D1 +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG CYREG_B0_UDB13_D0 +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG CYREG_B0_UDB13_D1 +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG CYREG_B0_UDB13_ACTL +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG CYREG_B0_UDB13_F0_F1 +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG CYREG_B0_UDB13_F0 +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG CYREG_B0_UDB13_F1 +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__MSK_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__PER_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define UART_Bridge_BUART_sTX_TxShifter_u0__A0_A1_REG CYREG_B0_UDB15_A0_A1 +#define UART_Bridge_BUART_sTX_TxShifter_u0__A0_REG CYREG_B0_UDB15_A0 +#define UART_Bridge_BUART_sTX_TxShifter_u0__A1_REG CYREG_B0_UDB15_A1 +#define UART_Bridge_BUART_sTX_TxShifter_u0__D0_D1_REG CYREG_B0_UDB15_D0_D1 +#define UART_Bridge_BUART_sTX_TxShifter_u0__D0_REG CYREG_B0_UDB15_D0 +#define UART_Bridge_BUART_sTX_TxShifter_u0__D1_REG CYREG_B0_UDB15_D1 +#define UART_Bridge_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG CYREG_B0_UDB15_ACTL +#define UART_Bridge_BUART_sTX_TxShifter_u0__F0_F1_REG CYREG_B0_UDB15_F0_F1 +#define UART_Bridge_BUART_sTX_TxShifter_u0__F0_REG CYREG_B0_UDB15_F0 +#define UART_Bridge_BUART_sTX_TxShifter_u0__F1_REG CYREG_B0_UDB15_F1 +#define UART_Bridge_BUART_sTX_TxSts__0__MASK 0x01u +#define UART_Bridge_BUART_sTX_TxSts__0__POS 0 +#define UART_Bridge_BUART_sTX_TxSts__1__MASK 0x02u +#define UART_Bridge_BUART_sTX_TxSts__1__POS 1 +#define UART_Bridge_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL +#define UART_Bridge_BUART_sTX_TxSts__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST +#define UART_Bridge_BUART_sTX_TxSts__2__MASK 0x04u +#define UART_Bridge_BUART_sTX_TxSts__2__POS 2 +#define UART_Bridge_BUART_sTX_TxSts__3__MASK 0x08u +#define UART_Bridge_BUART_sTX_TxSts__3__POS 3 +#define UART_Bridge_BUART_sTX_TxSts__MASK 0x0Fu +#define UART_Bridge_BUART_sTX_TxSts__MASK_REG CYREG_B0_UDB00_MSK +#define UART_Bridge_BUART_sTX_TxSts__MASK_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define UART_Bridge_BUART_sTX_TxSts__PER_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define UART_Bridge_BUART_sTX_TxSts__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL +#define UART_Bridge_BUART_sTX_TxSts__STATUS_CNT_REG CYREG_B0_UDB00_ST_CTL +#define UART_Bridge_BUART_sTX_TxSts__STATUS_CONTROL_REG CYREG_B0_UDB00_ST_CTL +#define UART_Bridge_BUART_sTX_TxSts__STATUS_REG CYREG_B0_UDB00_ST +#define UART_Bridge_RXInternalInterrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define UART_Bridge_RXInternalInterrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define UART_Bridge_RXInternalInterrupt__INTC_MASK 0x02u +#define UART_Bridge_RXInternalInterrupt__INTC_NUMBER 1u +#define UART_Bridge_RXInternalInterrupt__INTC_PRIOR_NUM 4u +#define UART_Bridge_RXInternalInterrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1 +#define UART_Bridge_RXInternalInterrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define UART_Bridge_RXInternalInterrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define UART_Bridge_TXInternalInterrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define UART_Bridge_TXInternalInterrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define UART_Bridge_TXInternalInterrupt__INTC_MASK 0x04u +#define UART_Bridge_TXInternalInterrupt__INTC_NUMBER 2u +#define UART_Bridge_TXInternalInterrupt__INTC_PRIOR_NUM 4u +#define UART_Bridge_TXInternalInterrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_2 +#define UART_Bridge_TXInternalInterrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define UART_Bridge_TXInternalInterrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* Timer_CSTick */ +#define Timer_CSTick_TimerHW__CAP0 CYREG_TMR0_CAP0 +#define Timer_CSTick_TimerHW__CAP1 CYREG_TMR0_CAP1 +#define Timer_CSTick_TimerHW__CFG0 CYREG_TMR0_CFG0 +#define Timer_CSTick_TimerHW__CFG1 CYREG_TMR0_CFG1 +#define Timer_CSTick_TimerHW__CFG2 CYREG_TMR0_CFG2 +#define Timer_CSTick_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0 +#define Timer_CSTick_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1 +#define Timer_CSTick_TimerHW__PER0 CYREG_TMR0_PER0 +#define Timer_CSTick_TimerHW__PER1 CYREG_TMR0_PER1 +#define Timer_CSTick_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3 +#define Timer_CSTick_TimerHW__PM_ACT_MSK 0x01u +#define Timer_CSTick_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3 +#define Timer_CSTick_TimerHW__PM_STBY_MSK 0x01u +#define Timer_CSTick_TimerHW__RT0 CYREG_TMR0_RT0 +#define Timer_CSTick_TimerHW__RT1 CYREG_TMR0_RT1 +#define Timer_CSTick_TimerHW__SR0 CYREG_TMR0_SR0 + +/* LedControlReg */ +#define LedControlReg_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL +#define LedControlReg_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB09_10_CTL +#define LedControlReg_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB09_10_CTL +#define LedControlReg_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB09_10_CTL +#define LedControlReg_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB09_10_CTL +#define LedControlReg_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB09_10_MSK +#define LedControlReg_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB09_10_MSK +#define LedControlReg_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB09_10_MSK +#define LedControlReg_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB09_10_MSK +#define LedControlReg_Sync_ctrl_reg__2__MASK 0x04u +#define LedControlReg_Sync_ctrl_reg__2__POS 2 +#define LedControlReg_Sync_ctrl_reg__3__MASK 0x08u +#define LedControlReg_Sync_ctrl_reg__3__POS 3 +#define LedControlReg_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB09_ACTL +#define LedControlReg_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB09_CTL +#define LedControlReg_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB09_ST_CTL +#define LedControlReg_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB09_CTL +#define LedControlReg_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB09_ST_CTL +#define LedControlReg_Sync_ctrl_reg__MASK 0x0Cu +#define LedControlReg_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL +#define LedControlReg_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL +#define LedControlReg_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB09_MSK + +/* Pin_BLE_Sleep */ +#define Pin_BLE_Sleep__0__INTTYPE CYREG_PICU15_INTTYPE4 +#define Pin_BLE_Sleep__0__MASK 0x10u +#define Pin_BLE_Sleep__0__PC CYREG_IO_PC_PRT15_PC4 +#define Pin_BLE_Sleep__0__PORT 15u +#define Pin_BLE_Sleep__0__SHIFT 4u +#define Pin_BLE_Sleep__AG CYREG_PRT15_AG +#define Pin_BLE_Sleep__AMUX CYREG_PRT15_AMUX +#define Pin_BLE_Sleep__BIE CYREG_PRT15_BIE +#define Pin_BLE_Sleep__BIT_MASK CYREG_PRT15_BIT_MASK +#define Pin_BLE_Sleep__BYP CYREG_PRT15_BYP +#define Pin_BLE_Sleep__CTL CYREG_PRT15_CTL +#define Pin_BLE_Sleep__DM0 CYREG_PRT15_DM0 +#define Pin_BLE_Sleep__DM1 CYREG_PRT15_DM1 +#define Pin_BLE_Sleep__DM2 CYREG_PRT15_DM2 +#define Pin_BLE_Sleep__DR CYREG_PRT15_DR +#define Pin_BLE_Sleep__INP_DIS CYREG_PRT15_INP_DIS +#define Pin_BLE_Sleep__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define Pin_BLE_Sleep__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define Pin_BLE_Sleep__LCD_EN CYREG_PRT15_LCD_EN +#define Pin_BLE_Sleep__MASK 0x10u +#define Pin_BLE_Sleep__PORT 15u +#define Pin_BLE_Sleep__PRT CYREG_PRT15_PRT +#define Pin_BLE_Sleep__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define Pin_BLE_Sleep__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define Pin_BLE_Sleep__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define Pin_BLE_Sleep__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define Pin_BLE_Sleep__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define Pin_BLE_Sleep__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define Pin_BLE_Sleep__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define Pin_BLE_Sleep__PS CYREG_PRT15_PS +#define Pin_BLE_Sleep__SHIFT 4u +#define Pin_BLE_Sleep__SLW CYREG_PRT15_SLW + +/* Pin_HWVersion */ +#define Pin_HWVersion__0__INTTYPE CYREG_PICU2_INTTYPE0 +#define Pin_HWVersion__0__MASK 0x01u +#define Pin_HWVersion__0__PC CYREG_PRT2_PC0 +#define Pin_HWVersion__0__PORT 2u +#define Pin_HWVersion__0__SHIFT 0u +#define Pin_HWVersion__1__INTTYPE CYREG_PICU2_INTTYPE1 +#define Pin_HWVersion__1__MASK 0x02u +#define Pin_HWVersion__1__PC CYREG_PRT2_PC1 +#define Pin_HWVersion__1__PORT 2u +#define Pin_HWVersion__1__SHIFT 1u +#define Pin_HWVersion__2__INTTYPE CYREG_PICU2_INTTYPE2 +#define Pin_HWVersion__2__MASK 0x04u +#define Pin_HWVersion__2__PC CYREG_PRT2_PC2 +#define Pin_HWVersion__2__PORT 2u +#define Pin_HWVersion__2__SHIFT 2u +#define Pin_HWVersion__3__INTTYPE CYREG_PICU2_INTTYPE3 +#define Pin_HWVersion__3__MASK 0x08u +#define Pin_HWVersion__3__PC CYREG_PRT2_PC3 +#define Pin_HWVersion__3__PORT 2u +#define Pin_HWVersion__3__SHIFT 3u +#define Pin_HWVersion__4__INTTYPE CYREG_PICU2_INTTYPE4 +#define Pin_HWVersion__4__MASK 0x10u +#define Pin_HWVersion__4__PC CYREG_PRT2_PC4 +#define Pin_HWVersion__4__PORT 2u +#define Pin_HWVersion__4__SHIFT 4u +#define Pin_HWVersion__AG CYREG_PRT2_AG +#define Pin_HWVersion__AMUX CYREG_PRT2_AMUX +#define Pin_HWVersion__BIE CYREG_PRT2_BIE +#define Pin_HWVersion__BIT_MASK CYREG_PRT2_BIT_MASK +#define Pin_HWVersion__BYP CYREG_PRT2_BYP +#define Pin_HWVersion__CTL CYREG_PRT2_CTL +#define Pin_HWVersion__DM0 CYREG_PRT2_DM0 +#define Pin_HWVersion__DM1 CYREG_PRT2_DM1 +#define Pin_HWVersion__DM2 CYREG_PRT2_DM2 +#define Pin_HWVersion__DR CYREG_PRT2_DR +#define Pin_HWVersion__INP_DIS CYREG_PRT2_INP_DIS +#define Pin_HWVersion__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU2_BASE +#define Pin_HWVersion__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define Pin_HWVersion__LCD_EN CYREG_PRT2_LCD_EN +#define Pin_HWVersion__MASK 0x1Fu +#define Pin_HWVersion__PORT 2u +#define Pin_HWVersion__PRT CYREG_PRT2_PRT +#define Pin_HWVersion__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define Pin_HWVersion__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define Pin_HWVersion__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define Pin_HWVersion__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define Pin_HWVersion__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define Pin_HWVersion__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define Pin_HWVersion__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define Pin_HWVersion__PS CYREG_PRT2_PS +#define Pin_HWVersion__SHIFT 0u +#define Pin_HWVersion__SLW CYREG_PRT2_SLW + +/* Pin_VoltageEn */ +#define Pin_VoltageEn__0__INTTYPE CYREG_PICU2_INTTYPE7 +#define Pin_VoltageEn__0__MASK 0x80u +#define Pin_VoltageEn__0__PC CYREG_PRT2_PC7 +#define Pin_VoltageEn__0__PORT 2u +#define Pin_VoltageEn__0__SHIFT 7u +#define Pin_VoltageEn__AG CYREG_PRT2_AG +#define Pin_VoltageEn__AMUX CYREG_PRT2_AMUX +#define Pin_VoltageEn__BIE CYREG_PRT2_BIE +#define Pin_VoltageEn__BIT_MASK CYREG_PRT2_BIT_MASK +#define Pin_VoltageEn__BYP CYREG_PRT2_BYP +#define Pin_VoltageEn__CTL CYREG_PRT2_CTL +#define Pin_VoltageEn__DM0 CYREG_PRT2_DM0 +#define Pin_VoltageEn__DM1 CYREG_PRT2_DM1 +#define Pin_VoltageEn__DM2 CYREG_PRT2_DM2 +#define Pin_VoltageEn__DR CYREG_PRT2_DR +#define Pin_VoltageEn__INP_DIS CYREG_PRT2_INP_DIS +#define Pin_VoltageEn__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU2_BASE +#define Pin_VoltageEn__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define Pin_VoltageEn__LCD_EN CYREG_PRT2_LCD_EN +#define Pin_VoltageEn__MASK 0x80u +#define Pin_VoltageEn__PORT 2u +#define Pin_VoltageEn__PRT CYREG_PRT2_PRT +#define Pin_VoltageEn__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define Pin_VoltageEn__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define Pin_VoltageEn__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define Pin_VoltageEn__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define Pin_VoltageEn__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define Pin_VoltageEn__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define Pin_VoltageEn__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define Pin_VoltageEn__PS CYREG_PRT2_PS +#define Pin_VoltageEn__SHIFT 7u +#define Pin_VoltageEn__SLW CYREG_PRT2_SLW + +/* Control_Flow_En */ +#define Control_Flow_En_2_Sync_ctrl_reg__0__MASK 0x01u +#define Control_Flow_En_2_Sync_ctrl_reg__0__POS 0 +#define Control_Flow_En_2_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define Control_Flow_En_2_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define Control_Flow_En_2_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL +#define Control_Flow_En_2_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define Control_Flow_En_2_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL +#define Control_Flow_En_2_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK +#define Control_Flow_En_2_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define Control_Flow_En_2_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK +#define Control_Flow_En_2_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define Control_Flow_En_2_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define Control_Flow_En_2_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL +#define Control_Flow_En_2_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL +#define Control_Flow_En_2_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL +#define Control_Flow_En_2_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL +#define Control_Flow_En_2_Sync_ctrl_reg__MASK 0x01u +#define Control_Flow_En_2_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define Control_Flow_En_2_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define Control_Flow_En_2_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK +#define Control_Flow_En_Sync_ctrl_reg__0__MASK 0x01u +#define Control_Flow_En_Sync_ctrl_reg__0__POS 0 +#define Control_Flow_En_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL +#define Control_Flow_En_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL +#define Control_Flow_En_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL +#define Control_Flow_En_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL +#define Control_Flow_En_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL +#define Control_Flow_En_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK +#define Control_Flow_En_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK +#define Control_Flow_En_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK +#define Control_Flow_En_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK +#define Control_Flow_En_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL +#define Control_Flow_En_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB00_CTL +#define Control_Flow_En_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL +#define Control_Flow_En_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB00_CTL +#define Control_Flow_En_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL +#define Control_Flow_En_Sync_ctrl_reg__MASK 0x01u +#define Control_Flow_En_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define Control_Flow_En_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define Control_Flow_En_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB00_MSK + +/* ApplicationButton */ +#define ApplicationButton__0__INTTYPE CYREG_PICU15_INTTYPE0 +#define ApplicationButton__0__MASK 0x01u +#define ApplicationButton__0__PC CYREG_IO_PC_PRT15_PC0 +#define ApplicationButton__0__PORT 15u +#define ApplicationButton__0__SHIFT 0u +#define ApplicationButton__AG CYREG_PRT15_AG +#define ApplicationButton__AMUX CYREG_PRT15_AMUX +#define ApplicationButton__BIE CYREG_PRT15_BIE +#define ApplicationButton__BIT_MASK CYREG_PRT15_BIT_MASK +#define ApplicationButton__BYP CYREG_PRT15_BYP +#define ApplicationButton__CTL CYREG_PRT15_CTL +#define ApplicationButton__DM0 CYREG_PRT15_DM0 +#define ApplicationButton__DM1 CYREG_PRT15_DM1 +#define ApplicationButton__DM2 CYREG_PRT15_DM2 +#define ApplicationButton__DR CYREG_PRT15_DR +#define ApplicationButton__INP_DIS CYREG_PRT15_INP_DIS +#define ApplicationButton__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define ApplicationButton__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define ApplicationButton__LCD_EN CYREG_PRT15_LCD_EN +#define ApplicationButton__MASK 0x01u +#define ApplicationButton__PORT 15u +#define ApplicationButton__PRT CYREG_PRT15_PRT +#define ApplicationButton__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define ApplicationButton__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define ApplicationButton__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define ApplicationButton__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define ApplicationButton__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define ApplicationButton__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define ApplicationButton__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define ApplicationButton__PS CYREG_PRT15_PS +#define ApplicationButton__SHIFT 0u +#define ApplicationButton__SLW CYREG_PRT15_SLW + +/* Pin_I2cPullUpEnable */ +#define Pin_I2cPullUpEnable__0__INTTYPE CYREG_PICU0_INTTYPE2 +#define Pin_I2cPullUpEnable__0__MASK 0x04u +#define Pin_I2cPullUpEnable__0__PC CYREG_PRT0_PC2 +#define Pin_I2cPullUpEnable__0__PORT 0u +#define Pin_I2cPullUpEnable__0__SHIFT 2u +#define Pin_I2cPullUpEnable__AG CYREG_PRT0_AG +#define Pin_I2cPullUpEnable__AMUX CYREG_PRT0_AMUX +#define Pin_I2cPullUpEnable__BIE CYREG_PRT0_BIE +#define Pin_I2cPullUpEnable__BIT_MASK CYREG_PRT0_BIT_MASK +#define Pin_I2cPullUpEnable__BYP CYREG_PRT0_BYP +#define Pin_I2cPullUpEnable__CTL CYREG_PRT0_CTL +#define Pin_I2cPullUpEnable__DM0 CYREG_PRT0_DM0 +#define Pin_I2cPullUpEnable__DM1 CYREG_PRT0_DM1 +#define Pin_I2cPullUpEnable__DM2 CYREG_PRT0_DM2 +#define Pin_I2cPullUpEnable__DR CYREG_PRT0_DR +#define Pin_I2cPullUpEnable__INP_DIS CYREG_PRT0_INP_DIS +#define Pin_I2cPullUpEnable__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE +#define Pin_I2cPullUpEnable__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define Pin_I2cPullUpEnable__LCD_EN CYREG_PRT0_LCD_EN +#define Pin_I2cPullUpEnable__MASK 0x04u +#define Pin_I2cPullUpEnable__PORT 0u +#define Pin_I2cPullUpEnable__PRT CYREG_PRT0_PRT +#define Pin_I2cPullUpEnable__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define Pin_I2cPullUpEnable__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define Pin_I2cPullUpEnable__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define Pin_I2cPullUpEnable__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define Pin_I2cPullUpEnable__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define Pin_I2cPullUpEnable__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define Pin_I2cPullUpEnable__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define Pin_I2cPullUpEnable__PS CYREG_PRT0_PS +#define Pin_I2cPullUpEnable__SHIFT 2u +#define Pin_I2cPullUpEnable__SLW CYREG_PRT0_SLW + +/* Miscellaneous */ +#define autoVrefComparator_0__CLK CYREG_CMP3_CLK +#define autoVrefComparator_0__CMP_MASK 0x08u +#define autoVrefComparator_0__CMP_NUMBER 3u +#define autoVrefComparator_0__CR CYREG_CMP3_CR +#define autoVrefComparator_0__LUT__CR CYREG_LUT3_CR +#define autoVrefComparator_0__LUT__MSK CYREG_LUT_MSK +#define autoVrefComparator_0__LUT__MSK_MASK 0x08u +#define autoVrefComparator_0__LUT__MSK_SHIFT 3u +#define autoVrefComparator_0__LUT__MX CYREG_LUT3_MX +#define autoVrefComparator_0__LUT__SR CYREG_LUT_SR +#define autoVrefComparator_0__LUT__SR_MASK 0x08u +#define autoVrefComparator_0__LUT__SR_SHIFT 3u +#define autoVrefComparator_0__PM_ACT_CFG CYREG_PM_ACT_CFG7 +#define autoVrefComparator_0__PM_ACT_MSK 0x08u +#define autoVrefComparator_0__PM_STBY_CFG CYREG_PM_STBY_CFG7 +#define autoVrefComparator_0__PM_STBY_MSK 0x08u +#define autoVrefComparator_0__SW0 CYREG_CMP3_SW0 +#define autoVrefComparator_0__SW2 CYREG_CMP3_SW2 +#define autoVrefComparator_0__SW3 CYREG_CMP3_SW3 +#define autoVrefComparator_0__SW4 CYREG_CMP3_SW4 +#define autoVrefComparator_0__SW6 CYREG_CMP3_SW6 +#define autoVrefComparator_0__TR0 CYREG_CMP3_TR0 +#define autoVrefComparator_0__TR1 CYREG_CMP3_TR1 +#define autoVrefComparator_0__TRIM__TR0 CYREG_FLSHID_MFG_CFG_CMP3_TR0 +#define autoVrefComparator_0__TRIM__TR0_HS CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS +#define autoVrefComparator_0__TRIM__TR1 CYREG_FLSHID_MFG_CFG_CMP3_TR1 +#define autoVrefComparator_0__TRIM__TR1_HS CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS +#define autoVrefComparator_0__WRK CYREG_CMP_WRK +#define autoVrefComparator_0__WRK_MASK 0x08u +#define autoVrefComparator_0__WRK_SHIFT 3u +#define BCLK__BUS_CLK__HZ 64000000U +#define BCLK__BUS_CLK__KHZ 64000U +#define BCLK__BUS_CLK__MHZ 64U +#define CY_PROJECT_NAME "KitProg3" +#define CY_VERSION "PSoC Creator 4.2" +#define CYDEV_CHIP_DIE_LEOPARD 1u +#define CYDEV_CHIP_DIE_PSOC4A 18u +#define CYDEV_CHIP_DIE_PSOC5LP 2u +#define CYDEV_CHIP_DIE_PSOC5TM 3u +#define CYDEV_CHIP_DIE_TMA4 4u +#define CYDEV_CHIP_DIE_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_FM0P 5u +#define CYDEV_CHIP_FAMILY_FM3 6u +#define CYDEV_CHIP_FAMILY_FM4 7u +#define CYDEV_CHIP_FAMILY_PSOC3 1u +#define CYDEV_CHIP_FAMILY_PSOC4 2u +#define CYDEV_CHIP_FAMILY_PSOC5 3u +#define CYDEV_CHIP_FAMILY_PSOC6 4u +#define CYDEV_CHIP_FAMILY_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5 +#define CYDEV_CHIP_JTAG_ID 0x2E127069u +#define CYDEV_CHIP_MEMBER_3A 1u +#define CYDEV_CHIP_MEMBER_4A 18u +#define CYDEV_CHIP_MEMBER_4D 13u +#define CYDEV_CHIP_MEMBER_4E 6u +#define CYDEV_CHIP_MEMBER_4F 19u +#define CYDEV_CHIP_MEMBER_4G 4u +#define CYDEV_CHIP_MEMBER_4H 17u +#define CYDEV_CHIP_MEMBER_4I 23u +#define CYDEV_CHIP_MEMBER_4J 14u +#define CYDEV_CHIP_MEMBER_4K 15u +#define CYDEV_CHIP_MEMBER_4L 22u +#define CYDEV_CHIP_MEMBER_4M 21u +#define CYDEV_CHIP_MEMBER_4N 10u +#define CYDEV_CHIP_MEMBER_4O 7u +#define CYDEV_CHIP_MEMBER_4P 20u +#define CYDEV_CHIP_MEMBER_4Q 12u +#define CYDEV_CHIP_MEMBER_4R 8u +#define CYDEV_CHIP_MEMBER_4S 11u +#define CYDEV_CHIP_MEMBER_4T 9u +#define CYDEV_CHIP_MEMBER_4U 5u +#define CYDEV_CHIP_MEMBER_4V 16u +#define CYDEV_CHIP_MEMBER_5A 3u +#define CYDEV_CHIP_MEMBER_5B 2u +#define CYDEV_CHIP_MEMBER_6A 24u +#define CYDEV_CHIP_MEMBER_FM3 28u +#define CYDEV_CHIP_MEMBER_FM4 29u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 25u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 26u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 27u +#define CYDEV_CHIP_MEMBER_UNKNOWN 0u +#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B +#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED +#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT +#define CYDEV_CHIP_REV_LEOPARD_ES1 0u +#define CYDEV_CHIP_REV_LEOPARD_ES2 1u +#define CYDEV_CHIP_REV_LEOPARD_ES3 3u +#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u +#define CYDEV_CHIP_REV_PSOC4A_ES0 17u +#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u +#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u +#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u +#define CYDEV_CHIP_REV_PSOC5TM_ES0 0u +#define CYDEV_CHIP_REV_PSOC5TM_ES1 1u +#define CYDEV_CHIP_REV_PSOC5TM_PRODUCTION 1u +#define CYDEV_CHIP_REV_TMA4_ES 17u +#define CYDEV_CHIP_REV_TMA4_ES2 33u +#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_3A_ES1 0u +#define CYDEV_CHIP_REVISION_3A_ES2 1u +#define CYDEV_CHIP_REVISION_3A_ES3 3u +#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u +#define CYDEV_CHIP_REVISION_4A_ES0 17u +#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD 0u +#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u +#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u +#define CYDEV_CHIP_REVISION_4G_ES 17u +#define CYDEV_CHIP_REVISION_4G_ES2 33u +#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4I_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4J_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4K_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4T_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4V_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_5A_ES0 0u +#define CYDEV_CHIP_REVISION_5A_ES1 1u +#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u +#define CYDEV_CHIP_REVISION_5B_ES0 0u +#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_6A_ES 17u +#define CYDEV_CHIP_REVISION_6A_NO_UDB 33u +#define CYDEV_CHIP_REVISION_6A_PRODUCTION 33u +#define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION +#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED +#define CYDEV_CONFIG_FASTBOOT_ENABLED 1 +#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0 +#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1 +#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2 +#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_Disallowed +#define CYDEV_CONFIGURATION_COMPRESSED 1 +#define CYDEV_CONFIGURATION_DMA 0 +#define CYDEV_CONFIGURATION_ECC 0 +#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED +#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0 +#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED +#define CYDEV_CONFIGURATION_MODE_DMA 2 +#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1 +#define CYDEV_DEBUG_ENABLE_MASK 0x20u +#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG +#define CYDEV_DEBUGGING_DPS_Disable 3 +#define CYDEV_DEBUGGING_DPS_JTAG_4 1 +#define CYDEV_DEBUGGING_DPS_JTAG_5 0 +#define CYDEV_DEBUGGING_DPS_SWD 2 +#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD +#define CYDEV_DEBUGGING_DPS_SWD_SWV 6 +#define CYDEV_DEBUGGING_ENABLE 1 +#define CYDEV_DEBUGGING_XRES 0 +#define CYDEV_DMA_CHANNELS_AVAILABLE 24u +#define CYDEV_ECC_ENABLE 0 +#define CYDEV_HEAP_SIZE 0x1000 +#define CYDEV_INSTRUCT_CACHE_ENABLED 1 +#define CYDEV_INTR_RISING 0x0000801Fu +#define CYDEV_IS_EXPORTING_CODE 0 +#define CYDEV_IS_IMPORTING_CODE 0 +#define CYDEV_PROJ_TYPE 2 +#define CYDEV_PROJ_TYPE_BOOTLOADER 1 +#define CYDEV_PROJ_TYPE_LAUNCHER 5 +#define CYDEV_PROJ_TYPE_LOADABLE 2 +#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4 +#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3 +#define CYDEV_PROJ_TYPE_STANDARD 0 +#define CYDEV_PROTECTION_ENABLE 0 +#define CYDEV_STACK_SIZE 0x4000 +#define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP +#define CYDEV_USE_BUNDLED_CMSIS 1 +#define CYDEV_VARIABLE_VDDA 0 +#define CYDEV_VDDA 5.0 +#define CYDEV_VDDA_MV 5000 +#define CYDEV_VDDD 5.0 +#define CYDEV_VDDD_MV 5000 +#define CYDEV_VDDIO0 5.0 +#define CYDEV_VDDIO0_MV 5000 +#define CYDEV_VDDIO1 5.0 +#define CYDEV_VDDIO1_MV 5000 +#define CYDEV_VDDIO2 5.0 +#define CYDEV_VDDIO2_MV 5000 +#define CYDEV_VDDIO3 5.0 +#define CYDEV_VDDIO3_MV 5000 +#define CYDEV_VIO0 5.0 +#define CYDEV_VIO0_MV 5000 +#define CYDEV_VIO1 5.0 +#define CYDEV_VIO1_MV 5000 +#define CYDEV_VIO2 5.0 +#define CYDEV_VIO2_MV 5000 +#define CYDEV_VIO3 5.0 +#define CYDEV_VIO3_MV 5000 +#define CYIPBLOCK_ARM_CM3_VERSION 0 +#define CYIPBLOCK_P3_ANAIF_VERSION 0 +#define CYIPBLOCK_P3_CAN_VERSION 0 +#define CYIPBLOCK_P3_CAPSENSE_VERSION 0 +#define CYIPBLOCK_P3_COMP_VERSION 0 +#define CYIPBLOCK_P3_DECIMATOR_VERSION 0 +#define CYIPBLOCK_P3_DFB_VERSION 0 +#define CYIPBLOCK_P3_DMA_VERSION 0 +#define CYIPBLOCK_P3_DRQ_VERSION 0 +#define CYIPBLOCK_P3_DSM_VERSION 0 +#define CYIPBLOCK_P3_EMIF_VERSION 0 +#define CYIPBLOCK_P3_I2C_VERSION 0 +#define CYIPBLOCK_P3_LCD_VERSION 0 +#define CYIPBLOCK_P3_LPF_VERSION 0 +#define CYIPBLOCK_P3_OPAMP_VERSION 0 +#define CYIPBLOCK_P3_PM_VERSION 0 +#define CYIPBLOCK_P3_SCCT_VERSION 0 +#define CYIPBLOCK_P3_TIMER_VERSION 0 +#define CYIPBLOCK_P3_USB_VERSION 0 +#define CYIPBLOCK_P3_VIDAC_VERSION 0 +#define CYIPBLOCK_P3_VREF_VERSION 0 +#define CYIPBLOCK_S8_GPIO_VERSION 0 +#define CYIPBLOCK_S8_IRQ_VERSION 0 +#define CYIPBLOCK_S8_SAR_VERSION 0 +#define CYIPBLOCK_S8_SIO_VERSION 0 +#define CYIPBLOCK_S8_UDB_VERSION 0 +#define DMA_CHANNELS_USED__MASK0 0x00000000u +#define CYDEV_BOOTLOADER_ENABLE 0 + +#endif /* INCLUDED_CYFITTER_H */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/cyfitter_cfg.c b/source/hic_hal/cypress/psoc5lp/PSoC5/cyfitter_cfg.c new file mode 100644 index 0000000000..5ef23bf6d4 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/cyfitter_cfg.c @@ -0,0 +1,3009 @@ +/******************************************************************************* +* File Name: cyfitter_cfg.c +* +* Description: +* This file contains device initialization code. +* Except for the user defined sections in CyClockStartupError(), this file should not be modified. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include +#include "cytypes.h" +#include "cydevice_trm.h" +#include "cyfitter.h" +#include "CyLib.h" +#include "cyfitter_cfg.h" + +#define CY_NEED_CYCLOCKSTARTUPERROR 1 + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) + #define CYPACKED + #define CYPACKED_ATTR __attribute__ ((packed)) + #define CYALIGNED __attribute__ ((aligned)) + #define CY_CFG_UNUSED __attribute__ ((unused)) + #ifndef CY_CFG_SECTION + #define CY_CFG_SECTION __attribute__ ((section(".psocinit"))) + #endif + + #if defined(__ARMCC_VERSION) + #define CY_CFG_MEMORY_BARRIER() __memory_changed() + #else + #define CY_CFG_MEMORY_BARRIER() __sync_synchronize() + #endif + +#elif defined(__ICCARM__) + #include + + #define CYPACKED __packed + #define CYPACKED_ATTR + #define CYALIGNED _Pragma("data_alignment=4") + #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") + #define CY_CFG_SECTION _Pragma("location=\".psocinit\"") + + #define CY_CFG_MEMORY_BARRIER() __DMB() + +#else + #error Unsupported toolchain +#endif + +#ifndef CYCODE + #define CYCODE +#endif +#ifndef CYDATA + #define CYDATA +#endif +#ifndef CYFAR + #define CYFAR +#endif +#ifndef CYXDATA + #define CYXDATA +#endif + + +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n); +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n) +{ + (void)memset(s, 0, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} + + + + +/* Clock startup error codes */ +#define CYCLOCKSTART_NO_ERROR 0u +#define CYCLOCKSTART_XTAL_ERROR 1u +#define CYCLOCKSTART_32KHZ_ERROR 2u +#define CYCLOCKSTART_PLL_ERROR 3u +#define CYCLOCKSTART_FLL_ERROR 4u +#define CYCLOCKSTART_WCO_ERROR 5u + + +#ifdef CY_NEED_CYCLOCKSTARTUPERROR +/******************************************************************************* +* Function Name: CyClockStartupError +******************************************************************************** +* Summary: +* If an error is encountered during clock configuration (crystal startup error, +* PLL lock error, etc.), the system will end up here. Unless reimplemented by +* the customer, this function will stop in an infinite loop. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +CY_CFG_UNUSED +static void CyClockStartupError(uint8 errorCode); +CY_CFG_UNUSED +static void CyClockStartupError(uint8 errorCode) +{ + /* To remove the compiler warning if errorCode not used. */ + errorCode = errorCode; + + /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ + /* we will end up here to allow the customer to implement something to */ + /* deal with the clock condition. */ + +#ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK + CY_CFG_Clock_Startup_ErrorCallback(); +#else + /* If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */ + /* `#START CyClockStartupError` */ + + + + /* `#END` */ + + while(1) {} +#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ +} +#endif + +#define CY_CFG_BASE_ADDR_COUNT 42u +CYPACKED typedef struct +{ + uint8 offset; + uint8 value; +} CYPACKED_ATTR cy_cfg_addrvalue_t; + + + +/******************************************************************************* +* Function Name: cfg_write_bytes32 +******************************************************************************** +* Summary: +* This function is used for setting up the chip configuration areas that +* contain relatively sparse data. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]); +static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]) +{ + /* For 32-bit little-endian architectures */ + uint32 i, j = 0u; + for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) + { + uint32 baseAddr = addr_table[i]; + uint8 count = (uint8)baseAddr; + baseAddr &= 0xFFFFFF00u; + while (count != 0u) + { + CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value); + j++; + count--; + } + } +} + +/******************************************************************************* +* Function Name: ClockSetup +******************************************************************************** +* +* Summary: +* Performs the initialization of all of the clocks in the device based on the +* settings in the Clock tab of the DWR. This includes enabling the requested +* clocks and setting the necessary dividers to produce the desired frequency. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void ClockSetup(void); +static void ClockSetup(void) +{ + /* CYDEV_CLKDIST_ACFG0_CFG0 Address: CYREG_CLKDIST_ACFG0_CFG0 Size (bytes): 4 */ + static const uint8 CYCODE BS_CYDEV_CLKDIST_ACFG0_CFG0_VAL[] = { + 0x71u, 0x00u, 0x18u, 0x01u}; + + uint32 timeout; + uint8 pllLock; + + + /* Configure Digital Clocks based on settings from Clock DWR */ + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0003u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x18u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x19u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0340u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x18u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0), 0x0340u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0 + 0x2u), 0x18u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG4_CFG0), 0x0000u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG4_CFG0 + 0x2u), 0x50u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG5_CFG0), 0xF97Fu); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG5_CFG0 + 0x2u), 0x18u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG6_CFG0), 0xF9FFu); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG6_CFG0 + 0x2u), 0x18u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG7_CFG0), 0x30D3u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG7_CFG0 + 0x2u), 0x1Bu); + + /* Configure Analog Clocks based on settings from Clock DWR */ + CYCONFIGCPYCODE((void CYFAR *)(CYREG_CLKDIST_ACFG0_CFG0), (const void CYCODE *)(BS_CYDEV_CLKDIST_ACFG0_CFG0_VAL), 4u); + + /* Configure ILO based on settings from Clock DWR */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u); + + /* Configure IMO based on settings from Clock DWR */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB))); + + /* Configure PLL based on settings from Clock DWR */ + CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0818u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u); + /* Wait up to 250us for the PLL to lock */ + pllLock = 0u; + for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--) + { + pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0)); + CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */ + } + /* If we ran out of time the PLL didn't lock so go to the error function */ + if (timeout == 0u) + { + CyClockStartupError(CYCLOCKSTART_PLL_ERROR); + } + + /* Configure Bus/Master Clock based on settings from Clock DWR */ + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u); + + /* Configure USB Clock based on settings from Clock DWR */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DLY1), 0x04u); + + CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x9Fu))); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG1), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG1) | 0x01u))); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG0), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x80u))); +} + + +/* Analog API Functions */ + + +/******************************************************************************* +* Function Name: AnalogSetDefault +******************************************************************************** +* +* Summary: +* Sets up the analog portions of the chip to default values based on chip +* configuration options from the project. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void AnalogSetDefault(void); +static void AnalogSetDefault(void) +{ + uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u)); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u)); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu)); + CY_SET_XTND_REG8((void CYFAR *)CYREG_CMP3_CR, 0x02u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG7, 0x08u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_PRT0_AG, 0x01u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_PRT12_AG, 0x5Au); + CY_SET_XTND_REG8((void CYFAR *)CYREG_DAC2_SW0, 0x30u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_CMP1_SW0, 0x21u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_CMP3_SW3, 0x20u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_BUS_SW0, 0xA1u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u); +} + + +/******************************************************************************* +* Function Name: SetAnalogRoutingPumps +******************************************************************************** +* +* Summary: +* Enables or disables the analog pumps feeding analog routing switches. +* Intended to be called at startup, based on the Vdda system configuration; +* may be called during operation when the user informs us that the Vdda voltage +* crossed the pump threshold. +* +* Parameters: +* enabled - 1 to enable the pumps, 0 to disable the pumps +* +* Return: +* void +* +*******************************************************************************/ +void SetAnalogRoutingPumps(uint8 enabled) +{ + uint8 regValue = CY_GET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0); + if (enabled != 0u) + { + regValue |= 0x22u; + } + else + { + regValue &= (uint8)~0x22u; + } + CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue); +} + + +#define CY_AMUX_UNUSED CYREG_BOOST_SR +static uint8 CYXDATA * const CYCODE AdcMux__outerAddr[2] = { + (uint8 CYXDATA *)CYREG_CMP3_SW4, + (uint8 CYXDATA *)CYREG_PRT3_AG, +}; + +static const uint8 CYCODE AdcMux__outerMask[2] = { + 0x80u, + 0x08u, +}; + +static uint8 CYXDATA * const CYCODE AdcMux__innerAddr[1] = { + (uint8 CYXDATA *)CYREG_DSM0_SW0, +}; + +static const uint8 CYCODE AdcMux__innerMask[1] = { + 0x80u, +}; + +static const uint8 CYCODE AdcMux__innerMap[2] = { + 0u, + 0u, +}; + +static uint8 AdcMux__armsEnabled = 0u; +static uint8 AdcMux__refCnt[] = {0u}; + +/******************************************************************************* +* Function Name: AdcMux_Set +******************************************************************************** +* Summary: +* This function is used to set a particular channel as active on the AMux. +* +* Parameters: +* channel - The mux channel input to set as active +* +* Return: +* void +* +*******************************************************************************/ +void AdcMux_Set(uint8 channel) +{ + uint8 i; + uint8 channelMask = (1UL << channel); + if ((channel < 2u) && ((AdcMux__armsEnabled & channelMask) == ((uint32)0u))) + { + AdcMux__armsEnabled |= channelMask; + *AdcMux__outerAddr[channel] |= AdcMux__outerMask[channel]; + i = AdcMux__innerMap[channel]; + if (AdcMux__refCnt[i] == 0u) + { + *AdcMux__innerAddr[i] |= AdcMux__innerMask[i]; + } + AdcMux__refCnt[i]++; + } +} + +/******************************************************************************* +* Function Name: AdcMux_Unset +******************************************************************************** +* Summary: +* This function is used to clear a particular channel from being active on the +* AMux. +* +* Parameters: +* channel - The mux channel input to mark inactive +* +* Return: +* void +* +*******************************************************************************/ +void AdcMux_Unset(uint8 channel) +{ + uint8 i; + uint8 channelMask = (1UL << channel); + if ((channel < 2u) && ((AdcMux__armsEnabled & channelMask) != ((uint32)0u))) + { + AdcMux__armsEnabled &= (uint8)~channelMask; + *AdcMux__outerAddr[channel] &= (uint8)~AdcMux__outerMask[channel]; + i = AdcMux__innerMap[channel]; + AdcMux__refCnt[i]--; + if (AdcMux__refCnt[i] == 0) + { + *AdcMux__innerAddr[i] &= (uint8)~AdcMux__innerMask[i]; + } + } +} + +/* This is an implementation detail of the AMux. Code that depends on it may be + incompatible with other versions of PSoC Creator. */ +uint8 CYXDATA * const CYCODE ADC_DelSig_AMux__addrTable[2] = { + (uint8 CYXDATA *)CYREG_DSM0_SW3, + (uint8 CYXDATA *)CY_AMUX_UNUSED, +}; + +/* This is an implementation detail of the AMux. Code that depends on it may be + incompatible with other versions of PSoC Creator. */ +const uint8 CYCODE ADC_DelSig_AMux__maskTable[2] = { + 0x40u, + 0x00u, +}; + +/******************************************************************************* +* Function Name: ADC_DelSig_AMux_Set +******************************************************************************** +* Summary: +* This function is used to set a particular channel as active on the AMux. +* +* Parameters: +* channel - The mux channel input to set as active +* +* Return: +* void +* +*******************************************************************************/ +void ADC_DelSig_AMux_Set(uint8 channel) +{ + if (channel < 2) + { + *ADC_DelSig_AMux__addrTable[channel] |= ADC_DelSig_AMux__maskTable[channel]; + } +} + +/******************************************************************************* +* Function Name: ADC_DelSig_AMux_Unset +******************************************************************************** +* Summary: +* This function is used to clear a particular channel from being active on the +* AMux. +* +* Parameters: +* channel - The mux channel input to mark inactive +* +* Return: +* void +* +*******************************************************************************/ +void ADC_DelSig_AMux_Unset(uint8 channel) +{ + if (channel < 2) + { + *ADC_DelSig_AMux__addrTable[channel] &= (uint8)~ADC_DelSig_AMux__maskTable[channel]; + } +} + + + +/******************************************************************************* +* Function Name: cyfitter_cfg +******************************************************************************** +* Summary: +* This function is called by the start-up code for the selected device. It +* performs all of the necessary device configuration based on the design +* settings. This includes settings from the Design Wide Resources (DWR) such +* as Clocks and Pins as well as any component configuration that is necessary. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ + +void cyfitter_cfg(void) +{ + /* IOPINS0_0 Address: CYREG_PRT0_DR Size (bytes): 10 */ + static const uint8 CYCODE BS_IOPINS0_0_VAL[] = { + 0x04u, 0x00u, 0x06u, 0x88u, 0x88u, 0x00u, 0x88u, 0x00u, 0x41u, 0x00u}; + + /* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */ + static const uint8 CYCODE BS_IOPINS0_7_VAL[] = { + 0x10u, 0x00u, 0xBCu, 0x40u, 0x43u, 0x00u, 0x43u, 0x00u, 0x00u, 0x40u}; + + /* IOPINS1_7 Address: CYREG_PRT12_DR + 0x0000000Bu Size (bytes): 5 */ + static const uint8 CYCODE BS_IOPINS1_7_VAL[] = { + 0x00u, 0xAAu, 0x00u, 0xFFu, 0xAAu}; + + /* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */ + static const uint8 CYCODE BS_IOPINS0_8_VAL[] = { + 0x51u, 0x00u, 0x20u, 0x1Fu, 0x1Eu, 0x00u, 0x0Eu, 0x00u, 0xC0u, 0x00u}; + + /* IOPINS0_1 Address: CYREG_PRT1_DR Size (bytes): 10 */ + static const uint8 CYCODE BS_IOPINS0_1_VAL[] = { + 0x04u, 0x00u, 0xB8u, 0x44u, 0x78u, 0x00u, 0x50u, 0x00u, 0x00u, 0x00u}; + + /* IOPINS0_2 Address: CYREG_PRT2_DR Size (bytes): 10 */ + static const uint8 CYCODE BS_IOPINS0_2_VAL[] = { + 0x1Fu, 0x00u, 0x00u, 0xFFu, 0x80u, 0x00u, 0x60u, 0x00u, 0x00u, 0x00u}; + + /* IOPINS0_3 Address: CYREG_PRT3_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_3_VAL[] = { + 0x01u, 0x50u, 0x50u, 0x00u, 0x50u, 0x00u, 0x88u, 0x00u}; + +#ifdef CYGlobalIntDisable + /* Disable interrupts by default. Let user enable if/when they want. */ + CYGlobalIntDisable +#endif + + + /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x61u : 0x60u)); + /* Setup clocks based on selections from Clock DWR */ + ClockSetup(); + /* Set Flash Cycles based on newly configured 64.00MHz Bus Clock. */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u)); + { + static const uint32 CYCODE cy_cfg_addr_table[] = { + 0x40004501u, /* Base address: 0x40004500 Count: 1 */ + 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ + 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */ + 0x40006407u, /* Base address: 0x40006400 Count: 7 */ + 0x40006504u, /* Base address: 0x40006500 Count: 4 */ + 0x4001005Au, /* Base address: 0x40010000 Count: 90 */ + 0x4001013Du, /* Base address: 0x40010100 Count: 61 */ + 0x40010266u, /* Base address: 0x40010200 Count: 102 */ + 0x40010355u, /* Base address: 0x40010300 Count: 85 */ + 0x4001045Au, /* Base address: 0x40010400 Count: 90 */ + 0x40010560u, /* Base address: 0x40010500 Count: 96 */ + 0x40010655u, /* Base address: 0x40010600 Count: 85 */ + 0x4001075Cu, /* Base address: 0x40010700 Count: 92 */ + 0x4001085Cu, /* Base address: 0x40010800 Count: 92 */ + 0x40010960u, /* Base address: 0x40010900 Count: 96 */ + 0x40010A61u, /* Base address: 0x40010A00 Count: 97 */ + 0x40010B57u, /* Base address: 0x40010B00 Count: 87 */ + 0x40010C65u, /* Base address: 0x40010C00 Count: 101 */ + 0x40010D55u, /* Base address: 0x40010D00 Count: 85 */ + 0x40010E24u, /* Base address: 0x40010E00 Count: 36 */ + 0x40010F3Cu, /* Base address: 0x40010F00 Count: 60 */ + 0x4001145Bu, /* Base address: 0x40011400 Count: 91 */ + 0x4001155Au, /* Base address: 0x40011500 Count: 90 */ + 0x4001164Fu, /* Base address: 0x40011600 Count: 79 */ + 0x40011758u, /* Base address: 0x40011700 Count: 88 */ + 0x40011853u, /* Base address: 0x40011800 Count: 83 */ + 0x4001195Cu, /* Base address: 0x40011900 Count: 92 */ + 0x40011A5Fu, /* Base address: 0x40011A00 Count: 95 */ + 0x40011B56u, /* Base address: 0x40011B00 Count: 86 */ + 0x40014009u, /* Base address: 0x40014000 Count: 9 */ + 0x40014115u, /* Base address: 0x40014100 Count: 21 */ + 0x40014216u, /* Base address: 0x40014200 Count: 22 */ + 0x40014313u, /* Base address: 0x40014300 Count: 19 */ + 0x40014407u, /* Base address: 0x40014400 Count: 7 */ + 0x40014511u, /* Base address: 0x40014500 Count: 17 */ + 0x4001460Cu, /* Base address: 0x40014600 Count: 12 */ + 0x40014713u, /* Base address: 0x40014700 Count: 19 */ + 0x40014814u, /* Base address: 0x40014800 Count: 20 */ + 0x4001491Cu, /* Base address: 0x40014900 Count: 28 */ + 0x40014C15u, /* Base address: 0x40014C00 Count: 21 */ + 0x40014D05u, /* Base address: 0x40014D00 Count: 5 */ + 0x40015005u, /* Base address: 0x40015000 Count: 5 */ + }; + + static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { + {0x7Eu, 0x02u}, + {0x01u, 0x70u}, + {0x0Au, 0x4Bu}, + {0x01u, 0x88u}, + {0x04u, 0x04u}, + {0x08u, 0x50u}, + {0x09u, 0x40u}, + {0x0Cu, 0x84u}, + {0x10u, 0x40u}, + {0x11u, 0x40u}, + {0x14u, 0x1Fu}, + {0x18u, 0x40u}, + {0x78u, 0x02u}, + {0x79u, 0x04u}, + {0x7Cu, 0x41u}, + {0x2Bu, 0x0Fu}, + {0x3Bu, 0x08u}, + {0x80u, 0x0Fu}, + {0x85u, 0x0Fu}, + {0x89u, 0x0Fu}, + {0x8Au, 0x38u}, + {0x8Du, 0x72u}, + {0x24u, 0x04u}, + {0x75u, 0x07u}, + {0x88u, 0x72u}, + {0x8Au, 0x38u}, + {0x00u, 0x03u}, + {0x01u, 0x3Fu}, + {0x04u, 0xFCu}, + {0x05u, 0x3Fu}, + {0x09u, 0x06u}, + {0x0Au, 0xFFu}, + {0x0Cu, 0x83u}, + {0x0Du, 0x01u}, + {0x0Eu, 0x04u}, + {0x10u, 0x83u}, + {0x11u, 0x08u}, + {0x12u, 0x08u}, + {0x14u, 0x7Du}, + {0x16u, 0x02u}, + {0x1Au, 0x81u}, + {0x1Cu, 0x02u}, + {0x1Du, 0x20u}, + {0x1Eu, 0x80u}, + {0x1Fu, 0x40u}, + {0x21u, 0x80u}, + {0x22u, 0x7Eu}, + {0x24u, 0x83u}, + {0x25u, 0x0Du}, + {0x26u, 0x10u}, + {0x27u, 0x30u}, + {0x28u, 0x83u}, + {0x29u, 0x10u}, + {0x2Au, 0x20u}, + {0x2Bu, 0x01u}, + {0x2Cu, 0x42u}, + {0x2Du, 0x03u}, + {0x2Eu, 0x81u}, + {0x31u, 0x3Fu}, + {0x33u, 0x80u}, + {0x35u, 0x3Fu}, + {0x36u, 0xFFu}, + {0x37u, 0x40u}, + {0x39u, 0x22u}, + {0x3Eu, 0x40u}, + {0x3Fu, 0x04u}, + {0x54u, 0x01u}, + {0x56u, 0x04u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x10u}, + {0x5Du, 0x30u}, + {0x5Fu, 0x01u}, + {0x80u, 0x0Du}, + {0x83u, 0x20u}, + {0x84u, 0x0Du}, + {0x85u, 0xF0u}, + {0x87u, 0x07u}, + {0x88u, 0x12u}, + {0x8Au, 0x04u}, + {0x8Bu, 0x40u}, + {0x8Cu, 0x0Du}, + {0x8Du, 0x08u}, + {0x90u, 0x02u}, + {0x91u, 0x03u}, + {0x92u, 0x0Du}, + {0x93u, 0x0Cu}, + {0x95u, 0x0Fu}, + {0x96u, 0x20u}, + {0x97u, 0xF0u}, + {0x98u, 0x01u}, + {0x9Au, 0x12u}, + {0x9Bu, 0xF6u}, + {0x9Cu, 0x10u}, + {0x9Fu, 0x10u}, + {0xA0u, 0x0Du}, + {0xA3u, 0x09u}, + {0xA4u, 0x0Du}, + {0xA8u, 0x02u}, + {0xA9u, 0x05u}, + {0xAAu, 0x18u}, + {0xABu, 0x0Au}, + {0xACu, 0x40u}, + {0xAFu, 0x80u}, + {0xB0u, 0x0Fu}, + {0xB2u, 0x70u}, + {0xB5u, 0xFFu}, + {0xB8u, 0x08u}, + {0xBAu, 0x02u}, + {0xBEu, 0x04u}, + {0xBFu, 0x10u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDCu, 0x01u}, + {0xDFu, 0x01u}, + {0x00u, 0x28u}, + {0x01u, 0x82u}, + {0x05u, 0xA0u}, + {0x06u, 0x80u}, + {0x07u, 0x20u}, + {0x08u, 0x08u}, + {0x09u, 0x61u}, + {0x0Bu, 0x10u}, + {0x0Du, 0x08u}, + {0x0Eu, 0x42u}, + {0x0Fu, 0x08u}, + {0x10u, 0x80u}, + {0x11u, 0x58u}, + {0x13u, 0x20u}, + {0x14u, 0x08u}, + {0x15u, 0x01u}, + {0x17u, 0x48u}, + {0x18u, 0x02u}, + {0x1Eu, 0x40u}, + {0x1Fu, 0x04u}, + {0x21u, 0x22u}, + {0x22u, 0x24u}, + {0x23u, 0x01u}, + {0x24u, 0x08u}, + {0x28u, 0x01u}, + {0x29u, 0x01u}, + {0x2Au, 0x29u}, + {0x2Cu, 0x80u}, + {0x2Du, 0x60u}, + {0x2Eu, 0xA0u}, + {0x30u, 0x80u}, + {0x31u, 0x02u}, + {0x34u, 0x09u}, + {0x35u, 0x82u}, + {0x36u, 0x21u}, + {0x38u, 0x4Au}, + {0x3Bu, 0x10u}, + {0x3Cu, 0x48u}, + {0x3Du, 0x83u}, + {0x3Eu, 0x18u}, + {0x3Fu, 0x08u}, + {0x40u, 0x20u}, + {0x43u, 0x08u}, + {0x58u, 0x20u}, + {0x59u, 0x01u}, + {0x5Au, 0x88u}, + {0x62u, 0x02u}, + {0x69u, 0x80u}, + {0x86u, 0x02u}, + {0x8Bu, 0x04u}, + {0x8Eu, 0x01u}, + {0x8Fu, 0x10u}, + {0xC0u, 0xFFu}, + {0xC2u, 0xFFu}, + {0xC4u, 0xFFu}, + {0xCAu, 0xBFu}, + {0xCCu, 0xF9u}, + {0xCEu, 0xFFu}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x01u}, + {0xE2u, 0x80u}, + {0x02u, 0x20u}, + {0x03u, 0x10u}, + {0x04u, 0x24u}, + {0x05u, 0x34u}, + {0x07u, 0xC8u}, + {0x08u, 0x0Eu}, + {0x0Au, 0x11u}, + {0x0Cu, 0x01u}, + {0x0Eu, 0x06u}, + {0x10u, 0x03u}, + {0x11u, 0x03u}, + {0x12u, 0x1Cu}, + {0x13u, 0x0Cu}, + {0x14u, 0x24u}, + {0x15u, 0x22u}, + {0x17u, 0x94u}, + {0x18u, 0x0Du}, + {0x1Au, 0x12u}, + {0x1Eu, 0x04u}, + {0x1Fu, 0x63u}, + {0x20u, 0x24u}, + {0x23u, 0x8Cu}, + {0x24u, 0x24u}, + {0x28u, 0x1Au}, + {0x29u, 0x45u}, + {0x2Au, 0x01u}, + {0x2Bu, 0x98u}, + {0x2Eu, 0x24u}, + {0x31u, 0xFFu}, + {0x32u, 0x20u}, + {0x36u, 0x1Fu}, + {0x3Au, 0x80u}, + {0x3Eu, 0x04u}, + {0x54u, 0x40u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x11u}, + {0x5Du, 0x10u}, + {0x5Fu, 0x01u}, + {0x81u, 0x08u}, + {0x83u, 0x86u}, + {0x88u, 0x01u}, + {0x8Bu, 0x40u}, + {0x8Cu, 0x04u}, + {0x8Eu, 0x08u}, + {0x8Fu, 0x24u}, + {0x90u, 0x04u}, + {0x91u, 0xB9u}, + {0x92u, 0x08u}, + {0x93u, 0x40u}, + {0x98u, 0x02u}, + {0x9Bu, 0x24u}, + {0x9Du, 0x80u}, + {0x9Fu, 0x07u}, + {0xA1u, 0x40u}, + {0xA3u, 0x8Eu}, + {0xA4u, 0x02u}, + {0xABu, 0x92u}, + {0xB0u, 0x0Eu}, + {0xB1u, 0x7Fu}, + {0xB2u, 0x01u}, + {0xB7u, 0x80u}, + {0xB8u, 0x22u}, + {0xB9u, 0x02u}, + {0xBEu, 0x11u}, + {0xBFu, 0x40u}, + {0xC0u, 0x32u}, + {0xC1u, 0x06u}, + {0xC2u, 0x40u}, + {0xC4u, 0x01u}, + {0xC5u, 0xBEu}, + {0xC6u, 0xFDu}, + {0xC7u, 0x0Cu}, + {0xC8u, 0x1Fu}, + {0xC9u, 0xFFu}, + {0xCAu, 0xFFu}, + {0xCBu, 0xFFu}, + {0xCCu, 0x22u}, + {0xCEu, 0xF0u}, + {0xCFu, 0x0Cu}, + {0xD0u, 0x04u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDAu, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x30u}, + {0xDDu, 0x91u}, + {0xDFu, 0x01u}, + {0xE2u, 0xC0u}, + {0xE4u, 0x40u}, + {0xE5u, 0x01u}, + {0xE6u, 0x10u}, + {0xE7u, 0x11u}, + {0xE8u, 0xC0u}, + {0xE9u, 0x01u}, + {0xEBu, 0x11u}, + {0xECu, 0x40u}, + {0xEDu, 0x01u}, + {0xEEu, 0x40u}, + {0xEFu, 0x01u}, + {0x00u, 0x40u}, + {0x03u, 0x04u}, + {0x04u, 0x08u}, + {0x05u, 0x10u}, + {0x06u, 0x40u}, + {0x07u, 0x02u}, + {0x09u, 0x04u}, + {0x0Au, 0x18u}, + {0x0Bu, 0x40u}, + {0x0Cu, 0x02u}, + {0x0Eu, 0x25u}, + {0x13u, 0x04u}, + {0x14u, 0x04u}, + {0x15u, 0x40u}, + {0x17u, 0x09u}, + {0x1Au, 0x60u}, + {0x1Bu, 0x14u}, + {0x1Du, 0x04u}, + {0x1Fu, 0x40u}, + {0x21u, 0x02u}, + {0x22u, 0x40u}, + {0x27u, 0x40u}, + {0x29u, 0x02u}, + {0x2Bu, 0x08u}, + {0x2Cu, 0x84u}, + {0x2Eu, 0x20u}, + {0x31u, 0xA2u}, + {0x34u, 0x08u}, + {0x36u, 0x01u}, + {0x37u, 0x42u}, + {0x39u, 0x80u}, + {0x3Au, 0x01u}, + {0x3Bu, 0x10u}, + {0x3Cu, 0x08u}, + {0x3Fu, 0x01u}, + {0x40u, 0x8Au}, + {0x42u, 0x24u}, + {0x48u, 0x86u}, + {0x49u, 0x18u}, + {0x4Bu, 0x80u}, + {0x51u, 0x04u}, + {0x52u, 0x50u}, + {0x53u, 0x04u}, + {0x5Bu, 0x90u}, + {0x60u, 0x02u}, + {0x61u, 0x20u}, + {0x65u, 0x04u}, + {0x66u, 0x50u}, + {0x80u, 0x80u}, + {0x82u, 0x01u}, + {0x86u, 0x20u}, + {0x87u, 0x04u}, + {0x88u, 0x08u}, + {0x8Bu, 0x80u}, + {0x8Du, 0x80u}, + {0x91u, 0x80u}, + {0x93u, 0x01u}, + {0x95u, 0x50u}, + {0x96u, 0x90u}, + {0x9Cu, 0x08u}, + {0x9Du, 0x80u}, + {0x9Eu, 0x20u}, + {0x9Fu, 0x48u}, + {0xA3u, 0x08u}, + {0xA4u, 0x84u}, + {0xA5u, 0x4Du}, + {0xA6u, 0x01u}, + {0xA7u, 0x50u}, + {0xABu, 0x40u}, + {0xACu, 0x10u}, + {0xB7u, 0x08u}, + {0xC0u, 0xF3u}, + {0xC2u, 0xFAu}, + {0xC4u, 0xF4u}, + {0xCAu, 0xA5u}, + {0xCCu, 0xDDu}, + {0xCEu, 0xCDu}, + {0xD0u, 0x0Fu}, + {0xD2u, 0x04u}, + {0xD6u, 0x0Cu}, + {0xD8u, 0x7Cu}, + {0xE2u, 0x4Eu}, + {0xE4u, 0x08u}, + {0xE6u, 0x41u}, + {0xEAu, 0x08u}, + {0x01u, 0x20u}, + {0x03u, 0x07u}, + {0x04u, 0x01u}, + {0x05u, 0x10u}, + {0x06u, 0x0Eu}, + {0x07u, 0x07u}, + {0x09u, 0x01u}, + {0x0Au, 0x40u}, + {0x0Du, 0x72u}, + {0x0Fu, 0x04u}, + {0x10u, 0x07u}, + {0x11u, 0x08u}, + {0x12u, 0x30u}, + {0x13u, 0x07u}, + {0x14u, 0x31u}, + {0x15u, 0x01u}, + {0x16u, 0x08u}, + {0x19u, 0x01u}, + {0x1Au, 0x20u}, + {0x1Cu, 0x36u}, + {0x1Du, 0x05u}, + {0x1Eu, 0x01u}, + {0x1Fu, 0x78u}, + {0x20u, 0x10u}, + {0x21u, 0x03u}, + {0x24u, 0x32u}, + {0x25u, 0x42u}, + {0x26u, 0x05u}, + {0x27u, 0x05u}, + {0x28u, 0x33u}, + {0x29u, 0x7Fu}, + {0x2Au, 0x04u}, + {0x2Cu, 0x07u}, + {0x2Du, 0x03u}, + {0x30u, 0x70u}, + {0x33u, 0x7Fu}, + {0x34u, 0x0Fu}, + {0x3Au, 0x20u}, + {0x3Fu, 0x04u}, + {0x54u, 0x09u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Du, 0x10u}, + {0x5Fu, 0x01u}, + {0x80u, 0x03u}, + {0x82u, 0xCCu}, + {0x84u, 0x90u}, + {0x85u, 0x4Fu}, + {0x86u, 0x6Fu}, + {0x87u, 0xA0u}, + {0x88u, 0x54u}, + {0x89u, 0xD1u}, + {0x8Au, 0xA0u}, + {0x8Bu, 0x24u}, + {0x8Cu, 0x4Fu}, + {0x8Du, 0x24u}, + {0x8Fu, 0xDAu}, + {0x90u, 0x4Bu}, + {0x91u, 0x02u}, + {0x92u, 0x04u}, + {0x93u, 0x1Du}, + {0x94u, 0x0Au}, + {0x95u, 0x78u}, + {0x96u, 0x40u}, + {0x97u, 0x87u}, + {0x98u, 0x05u}, + {0x9Au, 0x4Au}, + {0x9Cu, 0x40u}, + {0x9Eu, 0x84u}, + {0x9Fu, 0x01u}, + {0xA0u, 0x4Fu}, + {0xA4u, 0x4Cu}, + {0xA6u, 0x03u}, + {0xA8u, 0x04u}, + {0xAAu, 0xFBu}, + {0xACu, 0x01u}, + {0xB2u, 0xC0u}, + {0xB3u, 0xFFu}, + {0xB4u, 0x3Fu}, + {0xBAu, 0x08u}, + {0xBFu, 0x04u}, + {0xD6u, 0x02u}, + {0xD7u, 0x2Cu}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x01u}, + {0xDDu, 0x10u}, + {0xDFu, 0x01u}, + {0x00u, 0x04u}, + {0x02u, 0x0Bu}, + {0x05u, 0x02u}, + {0x06u, 0x28u}, + {0x07u, 0x01u}, + {0x09u, 0x20u}, + {0x0Au, 0xA0u}, + {0x0Bu, 0x02u}, + {0x0Cu, 0x02u}, + {0x0Du, 0x04u}, + {0x0Eu, 0x19u}, + {0x10u, 0x10u}, + {0x12u, 0x04u}, + {0x13u, 0x41u}, + {0x14u, 0x29u}, + {0x15u, 0x01u}, + {0x18u, 0x44u}, + {0x1Au, 0x84u}, + {0x1Bu, 0x01u}, + {0x1Cu, 0x28u}, + {0x1Fu, 0x10u}, + {0x22u, 0x08u}, + {0x27u, 0x20u}, + {0x28u, 0x02u}, + {0x29u, 0x05u}, + {0x2Bu, 0x04u}, + {0x30u, 0x24u}, + {0x32u, 0x42u}, + {0x34u, 0x08u}, + {0x35u, 0x02u}, + {0x36u, 0x81u}, + {0x38u, 0x20u}, + {0x3Au, 0x04u}, + {0x3Bu, 0x42u}, + {0x3Cu, 0x08u}, + {0x3Du, 0x20u}, + {0x3Eu, 0xA8u}, + {0x58u, 0x40u}, + {0x59u, 0x08u}, + {0x5Au, 0x12u}, + {0x61u, 0x80u}, + {0x67u, 0x80u}, + {0x6Cu, 0x42u}, + {0x6Du, 0x5Bu}, + {0x6Eu, 0x28u}, + {0x75u, 0x80u}, + {0x77u, 0x01u}, + {0x81u, 0xC0u}, + {0x84u, 0x40u}, + {0x86u, 0x01u}, + {0x87u, 0x10u}, + {0x88u, 0x24u}, + {0x8Au, 0x10u}, + {0x8Cu, 0x40u}, + {0x8Du, 0x44u}, + {0x8Fu, 0x18u}, + {0x91u, 0x88u}, + {0x92u, 0x61u}, + {0x93u, 0x80u}, + {0x94u, 0x40u}, + {0x95u, 0x50u}, + {0x96u, 0x08u}, + {0x97u, 0x54u}, + {0x98u, 0x09u}, + {0x99u, 0x08u}, + {0x9Au, 0x20u}, + {0x9Du, 0x80u}, + {0x9Fu, 0x0Du}, + {0xA3u, 0x14u}, + {0xA4u, 0x14u}, + {0xA5u, 0x0Du}, + {0xA6u, 0x11u}, + {0xA7u, 0x40u}, + {0xA9u, 0x02u}, + {0xAAu, 0x01u}, + {0xABu, 0x10u}, + {0xACu, 0x01u}, + {0xADu, 0x40u}, + {0xB0u, 0x10u}, + {0xB2u, 0x01u}, + {0xB4u, 0x04u}, + {0xB5u, 0x03u}, + {0xC0u, 0xF6u}, + {0xC2u, 0xFFu}, + {0xC4u, 0xFFu}, + {0xCAu, 0x0Fu}, + {0xCCu, 0xDFu}, + {0xCEu, 0x7Fu}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x88u}, + {0xE0u, 0x01u}, + {0xE2u, 0x1Au}, + {0xE6u, 0x0Bu}, + {0xEAu, 0x06u}, + {0xECu, 0x01u}, + {0xEEu, 0x04u}, + {0x00u, 0x06u}, + {0x05u, 0x30u}, + {0x07u, 0x40u}, + {0x08u, 0x12u}, + {0x09u, 0x70u}, + {0x0Au, 0x08u}, + {0x0Bu, 0x05u}, + {0x0Cu, 0x01u}, + {0x0Eu, 0x1Eu}, + {0x0Fu, 0x01u}, + {0x10u, 0x18u}, + {0x11u, 0x16u}, + {0x12u, 0x06u}, + {0x14u, 0x01u}, + {0x15u, 0x26u}, + {0x17u, 0x51u}, + {0x18u, 0x02u}, + {0x1Au, 0x18u}, + {0x1Bu, 0x08u}, + {0x1Cu, 0x02u}, + {0x20u, 0x1Cu}, + {0x22u, 0x02u}, + {0x24u, 0x0Au}, + {0x25u, 0x60u}, + {0x26u, 0x10u}, + {0x27u, 0x13u}, + {0x28u, 0x1Fu}, + {0x2Cu, 0x04u}, + {0x2Du, 0x06u}, + {0x33u, 0x70u}, + {0x36u, 0x1Fu}, + {0x37u, 0x0Fu}, + {0x38u, 0x80u}, + {0x3Bu, 0x08u}, + {0x56u, 0x08u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x10u}, + {0x5Du, 0x10u}, + {0x5Fu, 0x01u}, + {0x80u, 0x02u}, + {0x83u, 0x02u}, + {0x84u, 0xA2u}, + {0x85u, 0x20u}, + {0x86u, 0x09u}, + {0x87u, 0x95u}, + {0x88u, 0x02u}, + {0x89u, 0x01u}, + {0x8Cu, 0x90u}, + {0x8Du, 0x35u}, + {0x8Eu, 0x2Eu}, + {0x8Fu, 0xCAu}, + {0x90u, 0x0Du}, + {0x91u, 0x05u}, + {0x92u, 0x30u}, + {0x94u, 0xFFu}, + {0x95u, 0x04u}, + {0x97u, 0x68u}, + {0x98u, 0x96u}, + {0x99u, 0x6Au}, + {0x9Au, 0x69u}, + {0x9Cu, 0x01u}, + {0x9Du, 0x1Du}, + {0x9Fu, 0xE2u}, + {0xA2u, 0x02u}, + {0xA3u, 0xFFu}, + {0xA4u, 0x22u}, + {0xA5u, 0x52u}, + {0xA6u, 0x89u}, + {0xA7u, 0x28u}, + {0xA9u, 0x01u}, + {0xAAu, 0x01u}, + {0xACu, 0x40u}, + {0xADu, 0x02u}, + {0xAEu, 0x96u}, + {0xB4u, 0xFFu}, + {0xB7u, 0xFFu}, + {0xBEu, 0x10u}, + {0xBFu, 0x40u}, + {0xD2u, 0xF6u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDFu, 0x01u}, + {0x00u, 0x80u}, + {0x01u, 0x10u}, + {0x02u, 0x40u}, + {0x03u, 0x20u}, + {0x04u, 0x02u}, + {0x05u, 0x40u}, + {0x06u, 0x08u}, + {0x07u, 0x40u}, + {0x08u, 0x10u}, + {0x09u, 0x80u}, + {0x0Au, 0xA0u}, + {0x0Cu, 0x10u}, + {0x0Du, 0x04u}, + {0x0Fu, 0x41u}, + {0x10u, 0x04u}, + {0x12u, 0x01u}, + {0x13u, 0x06u}, + {0x14u, 0x40u}, + {0x15u, 0x80u}, + {0x16u, 0x10u}, + {0x17u, 0x10u}, + {0x19u, 0x10u}, + {0x1Fu, 0x40u}, + {0x20u, 0x02u}, + {0x25u, 0x4Cu}, + {0x26u, 0x80u}, + {0x28u, 0x04u}, + {0x2Au, 0x69u}, + {0x2Bu, 0x20u}, + {0x2Eu, 0x80u}, + {0x2Fu, 0x10u}, + {0x30u, 0x40u}, + {0x31u, 0x05u}, + {0x32u, 0x50u}, + {0x33u, 0x10u}, + {0x34u, 0x08u}, + {0x36u, 0x01u}, + {0x37u, 0x20u}, + {0x38u, 0x20u}, + {0x39u, 0x10u}, + {0x3Au, 0x06u}, + {0x3Bu, 0x44u}, + {0x3Du, 0xA8u}, + {0x5Cu, 0x80u}, + {0x66u, 0x80u}, + {0x68u, 0x20u}, + {0x69u, 0x04u}, + {0x6Bu, 0x04u}, + {0x70u, 0x1Au}, + {0x72u, 0x22u}, + {0x73u, 0x03u}, + {0x88u, 0x80u}, + {0x8Au, 0x80u}, + {0x92u, 0xE4u}, + {0x93u, 0x20u}, + {0x94u, 0x20u}, + {0x96u, 0x08u}, + {0x97u, 0x43u}, + {0x98u, 0x08u}, + {0x9Au, 0x41u}, + {0x9Bu, 0x20u}, + {0x9Cu, 0x16u}, + {0x9Du, 0x05u}, + {0x9Eu, 0x84u}, + {0x9Fu, 0x04u}, + {0xA1u, 0x10u}, + {0xA3u, 0x01u}, + {0xA4u, 0x20u}, + {0xA5u, 0x08u}, + {0xA6u, 0x81u}, + {0xA7u, 0x40u}, + {0xAAu, 0x41u}, + {0xADu, 0x80u}, + {0xB1u, 0x20u}, + {0xB2u, 0x44u}, + {0xB3u, 0x04u}, + {0xB5u, 0x04u}, + {0xC0u, 0xDFu}, + {0xC2u, 0xFFu}, + {0xC4u, 0xFFu}, + {0xCAu, 0x5Fu}, + {0xCCu, 0xEFu}, + {0xCEu, 0x7Fu}, + {0xD6u, 0x10u}, + {0xD8u, 0x10u}, + {0xE0u, 0x04u}, + {0xE2u, 0x90u}, + {0xE4u, 0x20u}, + {0xE6u, 0xC3u}, + {0xE8u, 0x08u}, + {0xEAu, 0x04u}, + {0xECu, 0x01u}, + {0x01u, 0x1Cu}, + {0x02u, 0x24u}, + {0x03u, 0x22u}, + {0x05u, 0x10u}, + {0x08u, 0xB9u}, + {0x09u, 0x2Cu}, + {0x0Au, 0x40u}, + {0x0Bu, 0x11u}, + {0x10u, 0x08u}, + {0x11u, 0x40u}, + {0x12u, 0x86u}, + {0x14u, 0x80u}, + {0x15u, 0x30u}, + {0x16u, 0x07u}, + {0x17u, 0x0Cu}, + {0x19u, 0x09u}, + {0x1Au, 0x92u}, + {0x1Bu, 0x10u}, + {0x1Cu, 0x40u}, + {0x1Du, 0x80u}, + {0x1Eu, 0x8Eu}, + {0x1Fu, 0x03u}, + {0x22u, 0x24u}, + {0x29u, 0x14u}, + {0x2Au, 0x40u}, + {0x33u, 0x60u}, + {0x34u, 0x7Fu}, + {0x35u, 0x80u}, + {0x36u, 0x80u}, + {0x37u, 0x1Fu}, + {0x38u, 0x20u}, + {0x39u, 0x08u}, + {0x3Eu, 0x40u}, + {0x3Fu, 0x10u}, + {0x40u, 0x61u}, + {0x41u, 0x03u}, + {0x45u, 0x0Cu}, + {0x46u, 0x0Eu}, + {0x47u, 0x0Bu}, + {0x48u, 0x15u}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Eu, 0xF0u}, + {0x4Fu, 0x44u}, + {0x50u, 0x0Cu}, + {0x56u, 0x08u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Au, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x22u}, + {0x5Du, 0x92u}, + {0x5Fu, 0x01u}, + {0x66u, 0xC0u}, + {0x6Au, 0x40u}, + {0x6Bu, 0x02u}, + {0x80u, 0x55u}, + {0x85u, 0x0Bu}, + {0x87u, 0x04u}, + {0x88u, 0x0Fu}, + {0x89u, 0x01u}, + {0x8Au, 0xF0u}, + {0x8Bu, 0x02u}, + {0x8Cu, 0xFFu}, + {0x90u, 0xAAu}, + {0x91u, 0x07u}, + {0x93u, 0x08u}, + {0x96u, 0xFFu}, + {0x98u, 0xAAu}, + {0x99u, 0x08u}, + {0x9Du, 0x10u}, + {0x9Eu, 0x33u}, + {0xA4u, 0xAAu}, + {0xA5u, 0x04u}, + {0xA8u, 0xF0u}, + {0xA9u, 0x01u}, + {0xAAu, 0x0Fu}, + {0xABu, 0x02u}, + {0xAEu, 0xCCu}, + {0xB3u, 0x10u}, + {0xB5u, 0x0Fu}, + {0xB6u, 0xFFu}, + {0xB9u, 0x20u}, + {0xBFu, 0x14u}, + {0xD4u, 0x01u}, + {0xD6u, 0x04u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDDu, 0x20u}, + {0xDFu, 0x01u}, + {0x00u, 0x40u}, + {0x02u, 0x08u}, + {0x03u, 0x40u}, + {0x05u, 0x10u}, + {0x06u, 0x80u}, + {0x08u, 0x20u}, + {0x09u, 0x01u}, + {0x0Bu, 0x21u}, + {0x0Cu, 0x01u}, + {0x0Du, 0x08u}, + {0x0Eu, 0x01u}, + {0x0Fu, 0x08u}, + {0x11u, 0x18u}, + {0x13u, 0x40u}, + {0x17u, 0x11u}, + {0x1Bu, 0x40u}, + {0x1Du, 0x50u}, + {0x1Eu, 0x08u}, + {0x21u, 0x20u}, + {0x22u, 0x04u}, + {0x26u, 0x60u}, + {0x27u, 0x10u}, + {0x28u, 0x48u}, + {0x2Bu, 0x50u}, + {0x2Cu, 0x80u}, + {0x2Du, 0x02u}, + {0x2Fu, 0x08u}, + {0x30u, 0xA0u}, + {0x32u, 0x01u}, + {0x34u, 0x01u}, + {0x36u, 0x44u}, + {0x37u, 0x10u}, + {0x39u, 0x24u}, + {0x3Cu, 0x08u}, + {0x3Eu, 0x21u}, + {0x44u, 0x01u}, + {0x45u, 0x08u}, + {0x46u, 0x20u}, + {0x49u, 0x10u}, + {0x4Bu, 0x10u}, + {0x4Eu, 0x10u}, + {0x4Fu, 0x18u}, + {0x54u, 0x80u}, + {0x57u, 0x08u}, + {0x59u, 0x42u}, + {0x5Au, 0x28u}, + {0x5Cu, 0x10u}, + {0x5Du, 0x10u}, + {0x5Eu, 0x40u}, + {0x62u, 0x01u}, + {0x66u, 0x80u}, + {0x69u, 0x04u}, + {0x6Au, 0x02u}, + {0x82u, 0x40u}, + {0x85u, 0x20u}, + {0x86u, 0x20u}, + {0x89u, 0x10u}, + {0x8Bu, 0x40u}, + {0x8Cu, 0x08u}, + {0x8Eu, 0x01u}, + {0x8Fu, 0x01u}, + {0x93u, 0x80u}, + {0x94u, 0x50u}, + {0x95u, 0x40u}, + {0x96u, 0x10u}, + {0x99u, 0x01u}, + {0x9Bu, 0x41u}, + {0x9Cu, 0xE0u}, + {0x9Eu, 0x08u}, + {0xA0u, 0x48u}, + {0xA1u, 0x10u}, + {0xA3u, 0x10u}, + {0xA6u, 0x08u}, + {0xAAu, 0x01u}, + {0xABu, 0x42u}, + {0xACu, 0x04u}, + {0xB0u, 0x08u}, + {0xB2u, 0x02u}, + {0xB3u, 0x08u}, + {0xB7u, 0x02u}, + {0xC0u, 0x5Bu}, + {0xC2u, 0xFFu}, + {0xC4u, 0x57u}, + {0xCAu, 0x26u}, + {0xCCu, 0xFDu}, + {0xCEu, 0xE6u}, + {0xD0u, 0x50u}, + {0xD2u, 0x20u}, + {0xD6u, 0x1Fu}, + {0xD8u, 0x11u}, + {0xE0u, 0x08u}, + {0xE2u, 0x10u}, + {0xE4u, 0x20u}, + {0xE6u, 0xC1u}, + {0xE8u, 0x90u}, + {0xEEu, 0xA0u}, + {0x00u, 0x01u}, + {0x02u, 0x06u}, + {0x05u, 0x14u}, + {0x09u, 0x20u}, + {0x0Bu, 0x03u}, + {0x0Eu, 0x10u}, + {0x10u, 0x02u}, + {0x11u, 0x50u}, + {0x13u, 0x0Cu}, + {0x15u, 0x09u}, + {0x16u, 0x10u}, + {0x17u, 0x10u}, + {0x18u, 0x01u}, + {0x1Du, 0x80u}, + {0x1Eu, 0x0Fu}, + {0x25u, 0x1Cu}, + {0x27u, 0x42u}, + {0x29u, 0x10u}, + {0x2Du, 0x4Cu}, + {0x2Fu, 0x11u}, + {0x30u, 0x04u}, + {0x31u, 0x20u}, + {0x32u, 0x10u}, + {0x33u, 0xC0u}, + {0x34u, 0x03u}, + {0x35u, 0x1Fu}, + {0x36u, 0x08u}, + {0x38u, 0x20u}, + {0x39u, 0x08u}, + {0x3Au, 0x82u}, + {0x3Eu, 0x04u}, + {0x3Fu, 0x01u}, + {0x54u, 0x18u}, + {0x56u, 0x04u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x37u}, + {0x5Du, 0x30u}, + {0x5Fu, 0x01u}, + {0x80u, 0x02u}, + {0x82u, 0x04u}, + {0x83u, 0xCCu}, + {0x84u, 0x0Fu}, + {0x87u, 0x33u}, + {0x89u, 0xF0u}, + {0x8Bu, 0x0Fu}, + {0x8Cu, 0x7Fu}, + {0x8Du, 0xFFu}, + {0x91u, 0xAAu}, + {0x95u, 0x0Fu}, + {0x96u, 0x12u}, + {0x97u, 0xF0u}, + {0x98u, 0xC0u}, + {0x99u, 0xAAu}, + {0x9Cu, 0x10u}, + {0x9Du, 0x55u}, + {0x9Eu, 0x01u}, + {0xA1u, 0xFFu}, + {0xA2u, 0x04u}, + {0xA6u, 0x14u}, + {0xA7u, 0xFFu}, + {0xA8u, 0x10u}, + {0xA9u, 0xAAu}, + {0xAAu, 0x08u}, + {0xACu, 0xC0u}, + {0xAEu, 0x20u}, + {0xB0u, 0x40u}, + {0xB4u, 0x80u}, + {0xB5u, 0xFFu}, + {0xB6u, 0x3Fu}, + {0xB8u, 0xA2u}, + {0xBEu, 0x10u}, + {0xC0u, 0x25u}, + {0xC6u, 0x50u}, + {0xC7u, 0x02u}, + {0xC8u, 0x18u}, + {0xC9u, 0xFFu}, + {0xCAu, 0xFFu}, + {0xCBu, 0xFFu}, + {0xCCu, 0x42u}, + {0xCDu, 0xA0u}, + {0xCEu, 0x70u}, + {0xD0u, 0x08u}, + {0xD1u, 0x10u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDAu, 0x04u}, + {0xDBu, 0x04u}, + {0xDFu, 0x01u}, + {0xE1u, 0x48u}, + {0xE2u, 0x40u}, + {0xE3u, 0x48u}, + {0xE4u, 0x80u}, + {0xE5u, 0x48u}, + {0xE6u, 0x80u}, + {0xE7u, 0x48u}, + {0x00u, 0x80u}, + {0x03u, 0x80u}, + {0x04u, 0x40u}, + {0x05u, 0x01u}, + {0x06u, 0x20u}, + {0x0Au, 0x64u}, + {0x0Bu, 0x01u}, + {0x0Eu, 0x12u}, + {0x0Fu, 0x08u}, + {0x14u, 0x20u}, + {0x16u, 0x0Au}, + {0x17u, 0x02u}, + {0x19u, 0x04u}, + {0x1Au, 0x44u}, + {0x1Bu, 0x90u}, + {0x1Du, 0x21u}, + {0x1Fu, 0x42u}, + {0x21u, 0x15u}, + {0x22u, 0x04u}, + {0x27u, 0x08u}, + {0x28u, 0x01u}, + {0x29u, 0x08u}, + {0x2Au, 0x10u}, + {0x2Cu, 0x40u}, + {0x2Eu, 0x18u}, + {0x30u, 0x80u}, + {0x32u, 0x06u}, + {0x34u, 0x20u}, + {0x36u, 0x08u}, + {0x37u, 0x42u}, + {0x39u, 0x20u}, + {0x3Au, 0x04u}, + {0x3Cu, 0x50u}, + {0x3Eu, 0x02u}, + {0x3Fu, 0x08u}, + {0x45u, 0x20u}, + {0x4Du, 0x40u}, + {0x54u, 0x08u}, + {0x56u, 0x20u}, + {0x57u, 0x04u}, + {0x5Au, 0x02u}, + {0x60u, 0x06u}, + {0x62u, 0x01u}, + {0x6Fu, 0x01u}, + {0x81u, 0x11u}, + {0x84u, 0x04u}, + {0x85u, 0x04u}, + {0x86u, 0x10u}, + {0x89u, 0x06u}, + {0x8Cu, 0x02u}, + {0x8Du, 0x54u}, + {0x8Fu, 0x10u}, + {0x90u, 0x04u}, + {0x92u, 0x22u}, + {0x93u, 0x01u}, + {0x95u, 0x86u}, + {0x96u, 0x08u}, + {0x98u, 0x01u}, + {0x99u, 0x08u}, + {0x9Au, 0x14u}, + {0x9Cu, 0x84u}, + {0x9Du, 0x12u}, + {0x9Eu, 0x01u}, + {0x9Fu, 0x10u}, + {0xA0u, 0xC4u}, + {0xA1u, 0x01u}, + {0xA2u, 0x12u}, + {0xA8u, 0x04u}, + {0xA9u, 0x28u}, + {0xAFu, 0x01u}, + {0xB3u, 0x02u}, + {0xB6u, 0x02u}, + {0xC0u, 0xB9u}, + {0xC2u, 0xEFu}, + {0xC4u, 0xF0u}, + {0xCAu, 0xEEu}, + {0xCCu, 0xFBu}, + {0xCEu, 0xF6u}, + {0xD0u, 0x20u}, + {0xD2u, 0x10u}, + {0xD6u, 0x01u}, + {0xD8u, 0x0Du}, + {0xE0u, 0xE0u}, + {0xE2u, 0x02u}, + {0xE4u, 0x50u}, + {0xEAu, 0x04u}, + {0xECu, 0x90u}, + {0x00u, 0x60u}, + {0x01u, 0x06u}, + {0x02u, 0x04u}, + {0x04u, 0x47u}, + {0x05u, 0x07u}, + {0x06u, 0x88u}, + {0x07u, 0x48u}, + {0x08u, 0x04u}, + {0x09u, 0x4Fu}, + {0x0Au, 0x60u}, + {0x0Cu, 0x04u}, + {0x0Du, 0x81u}, + {0x0Fu, 0x40u}, + {0x11u, 0x4Cu}, + {0x12u, 0x80u}, + {0x13u, 0x03u}, + {0x14u, 0x64u}, + {0x15u, 0xB0u}, + {0x17u, 0x47u}, + {0x18u, 0x13u}, + {0x19u, 0x49u}, + {0x1Au, 0x08u}, + {0x1Bu, 0x06u}, + {0x1Du, 0x4Fu}, + {0x1Eu, 0x12u}, + {0x20u, 0x18u}, + {0x21u, 0xD8u}, + {0x22u, 0x05u}, + {0x23u, 0x27u}, + {0x24u, 0x17u}, + {0x25u, 0x5Fu}, + {0x26u, 0x08u}, + {0x27u, 0xA0u}, + {0x28u, 0x64u}, + {0x29u, 0x43u}, + {0x2Bu, 0x0Cu}, + {0x2Cu, 0x64u}, + {0x2Fu, 0x08u}, + {0x30u, 0x20u}, + {0x31u, 0x10u}, + {0x32u, 0xC0u}, + {0x33u, 0x3Fu}, + {0x34u, 0x20u}, + {0x35u, 0x20u}, + {0x36u, 0x1Fu}, + {0x37u, 0xC0u}, + {0x39u, 0x08u}, + {0x3Au, 0xC0u}, + {0x3Bu, 0x80u}, + {0x3Eu, 0x14u}, + {0x3Fu, 0x11u}, + {0x56u, 0x08u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x11u}, + {0x5Du, 0x90u}, + {0x5Fu, 0x01u}, + {0x84u, 0x6Cu}, + {0x86u, 0x03u}, + {0x8Bu, 0x01u}, + {0x8Cu, 0x31u}, + {0x8Eu, 0x46u}, + {0x90u, 0x31u}, + {0x92u, 0x0Eu}, + {0x9Au, 0x4Cu}, + {0x9Fu, 0x01u}, + {0xA2u, 0x13u}, + {0xA6u, 0x08u}, + {0xB0u, 0x4Au}, + {0xB2u, 0x0Fu}, + {0xB5u, 0x01u}, + {0xB6u, 0x30u}, + {0xB8u, 0x80u}, + {0xB9u, 0x80u}, + {0xBAu, 0x2Au}, + {0xBEu, 0x40u}, + {0xBFu, 0x10u}, + {0xC0u, 0x01u}, + {0xC6u, 0x40u}, + {0xC9u, 0xFFu}, + {0xCAu, 0x07u}, + {0xCBu, 0xFFu}, + {0xCCu, 0x40u}, + {0xCDu, 0x20u}, + {0xCEu, 0xF0u}, + {0xCFu, 0x05u}, + {0xD0u, 0x08u}, + {0xD6u, 0x02u}, + {0xD7u, 0x13u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDAu, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x73u}, + {0xDDu, 0x33u}, + {0xDFu, 0x01u}, + {0xE0u, 0x40u}, + {0xE1u, 0xA8u}, + {0xE2u, 0x40u}, + {0xE3u, 0x20u}, + {0x01u, 0x08u}, + {0x02u, 0x02u}, + {0x04u, 0x08u}, + {0x05u, 0x12u}, + {0x06u, 0x08u}, + {0x07u, 0x01u}, + {0x08u, 0x01u}, + {0x0Au, 0x48u}, + {0x0Cu, 0x04u}, + {0x0Du, 0x02u}, + {0x0Eu, 0x08u}, + {0x0Fu, 0x12u}, + {0x10u, 0xC0u}, + {0x12u, 0x10u}, + {0x15u, 0x85u}, + {0x17u, 0x50u}, + {0x19u, 0x08u}, + {0x1Au, 0xC1u}, + {0x1Bu, 0x20u}, + {0x1Cu, 0x0Au}, + {0x1Du, 0x06u}, + {0x1Fu, 0x40u}, + {0x20u, 0x04u}, + {0x23u, 0x01u}, + {0x25u, 0x41u}, + {0x26u, 0x1Cu}, + {0x27u, 0x01u}, + {0x2Du, 0x25u}, + {0x2Fu, 0x42u}, + {0x32u, 0x80u}, + {0x35u, 0x02u}, + {0x36u, 0x08u}, + {0x37u, 0x50u}, + {0x39u, 0x20u}, + {0x3Du, 0x80u}, + {0x3Eu, 0x08u}, + {0x3Fu, 0x12u}, + {0x42u, 0x01u}, + {0x48u, 0x80u}, + {0x52u, 0x10u}, + {0x59u, 0x01u}, + {0x5Du, 0x80u}, + {0x5Eu, 0x10u}, + {0x69u, 0x50u}, + {0x6Au, 0x04u}, + {0x70u, 0x20u}, + {0x71u, 0x48u}, + {0x80u, 0x80u}, + {0x81u, 0x04u}, + {0x82u, 0x10u}, + {0x86u, 0x08u}, + {0x87u, 0x01u}, + {0x88u, 0x01u}, + {0x89u, 0x81u}, + {0x8Eu, 0x41u}, + {0x8Fu, 0x10u}, + {0x91u, 0x20u}, + {0x92u, 0x22u}, + {0x95u, 0x50u}, + {0x96u, 0x04u}, + {0x99u, 0x01u}, + {0x9Au, 0x04u}, + {0x9Cu, 0xC0u}, + {0x9Du, 0x40u}, + {0xA0u, 0x40u}, + {0xA2u, 0x80u}, + {0xA4u, 0x20u}, + {0xA5u, 0x08u}, + {0xA6u, 0x0Au}, + {0xA7u, 0x30u}, + {0xAEu, 0x08u}, + {0xB4u, 0x02u}, + {0xB5u, 0x04u}, + {0xB6u, 0x40u}, + {0xC0u, 0xF5u}, + {0xC2u, 0xFAu}, + {0xC4u, 0xFCu}, + {0xCAu, 0xF0u}, + {0xCCu, 0xF8u}, + {0xCEu, 0xF4u}, + {0xD0u, 0x08u}, + {0xD6u, 0x31u}, + {0xE2u, 0xD3u}, + {0xE6u, 0x60u}, + {0xEAu, 0x10u}, + {0x81u, 0x14u}, + {0x83u, 0x49u}, + {0x85u, 0x01u}, + {0x87u, 0x26u}, + {0x89u, 0x1Fu}, + {0x95u, 0x0Au}, + {0x97u, 0x51u}, + {0x98u, 0x01u}, + {0xA5u, 0x1Fu}, + {0xA8u, 0x01u}, + {0xACu, 0x01u}, + {0xB1u, 0x60u}, + {0xB3u, 0x07u}, + {0xB5u, 0x18u}, + {0xB6u, 0x01u}, + {0xBFu, 0x01u}, + {0xC0u, 0x54u}, + {0xC1u, 0x06u}, + {0xC5u, 0xC0u}, + {0xC7u, 0xEBu}, + {0xC8u, 0x32u}, + {0xC9u, 0xFFu}, + {0xCAu, 0xFFu}, + {0xCBu, 0xFFu}, + {0xCEu, 0xF0u}, + {0xCFu, 0x44u}, + {0xD0u, 0x0Cu}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDAu, 0x04u}, + {0xDCu, 0x33u}, + {0xDDu, 0x03u}, + {0xDFu, 0x01u}, + {0xE6u, 0xC0u}, + {0xEAu, 0x40u}, + {0xEBu, 0x02u}, + {0x00u, 0x22u}, + {0x01u, 0x80u}, + {0x03u, 0x20u}, + {0x08u, 0x02u}, + {0x09u, 0x08u}, + {0x0Bu, 0x04u}, + {0x0Eu, 0x04u}, + {0x10u, 0x24u}, + {0x12u, 0x40u}, + {0x15u, 0x50u}, + {0x19u, 0xA1u}, + {0x1Au, 0x20u}, + {0x1Bu, 0x88u}, + {0x1Cu, 0x02u}, + {0x1Fu, 0x40u}, + {0x20u, 0x20u}, + {0x22u, 0x81u}, + {0x23u, 0x14u}, + {0x24u, 0x40u}, + {0x25u, 0x04u}, + {0x27u, 0x08u}, + {0x28u, 0x04u}, + {0x29u, 0x64u}, + {0x2Au, 0x40u}, + {0x2Bu, 0x80u}, + {0x2Eu, 0x04u}, + {0x30u, 0x22u}, + {0x31u, 0x08u}, + {0x35u, 0x04u}, + {0x37u, 0x08u}, + {0x38u, 0x04u}, + {0x3Bu, 0x91u}, + {0x3Du, 0x18u}, + {0x3Fu, 0x02u}, + {0x40u, 0x44u}, + {0x43u, 0x28u}, + {0x44u, 0x40u}, + {0x48u, 0x40u}, + {0x4Bu, 0x90u}, + {0x4Eu, 0x42u}, + {0x4Fu, 0x20u}, + {0x51u, 0x10u}, + {0x56u, 0x04u}, + {0x57u, 0x02u}, + {0x58u, 0x80u}, + {0x60u, 0x02u}, + {0x63u, 0x03u}, + {0x8Fu, 0x02u}, + {0xC0u, 0x0Fu}, + {0xC2u, 0x4Eu}, + {0xC4u, 0xCEu}, + {0xCAu, 0x4Fu}, + {0xCCu, 0x47u}, + {0xCEu, 0xEFu}, + {0xD0u, 0x87u}, + {0xD2u, 0x3Cu}, + {0xD6u, 0x08u}, + {0xD8u, 0x08u}, + {0xE0u, 0x10u}, + {0xE6u, 0x40u}, + {0x00u, 0x67u}, + {0x02u, 0x18u}, + {0x03u, 0x03u}, + {0x04u, 0x8Cu}, + {0x05u, 0x23u}, + {0x06u, 0x53u}, + {0x07u, 0x0Cu}, + {0x09u, 0x25u}, + {0x0Bu, 0x08u}, + {0x0Du, 0x27u}, + {0x0Eu, 0xACu}, + {0x10u, 0x1Cu}, + {0x12u, 0x60u}, + {0x13u, 0x01u}, + {0x14u, 0xFFu}, + {0x15u, 0x40u}, + {0x18u, 0x81u}, + {0x19u, 0x0Fu}, + {0x1Au, 0x26u}, + {0x1Du, 0x07u}, + {0x1Eu, 0x01u}, + {0x21u, 0x02u}, + {0x22u, 0x02u}, + {0x23u, 0x28u}, + {0x24u, 0x55u}, + {0x25u, 0x26u}, + {0x26u, 0xA8u}, + {0x27u, 0x09u}, + {0x2Bu, 0x10u}, + {0x2Du, 0x2Cu}, + {0x2Eu, 0x01u}, + {0x32u, 0xFFu}, + {0x35u, 0x1Fu}, + {0x37u, 0x60u}, + {0x39u, 0x80u}, + {0x3Eu, 0x04u}, + {0x3Fu, 0x40u}, + {0x40u, 0x64u}, + {0x44u, 0x03u}, + {0x45u, 0xD0u}, + {0x46u, 0x0Bu}, + {0x48u, 0x06u}, + {0x49u, 0xFFu}, + {0x4Au, 0x7Fu}, + {0x4Bu, 0xFFu}, + {0x4Cu, 0x42u}, + {0x4Du, 0xA0u}, + {0x4Eu, 0x70u}, + {0x50u, 0x0Cu}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Au, 0x04u}, + {0x5Fu, 0x01u}, + {0x61u, 0x09u}, + {0x62u, 0x40u}, + {0x63u, 0x09u}, + {0x64u, 0x30u}, + {0x65u, 0x09u}, + {0x82u, 0x03u}, + {0x86u, 0x03u}, + {0x8Au, 0x40u}, + {0x8Cu, 0x28u}, + {0x8Eu, 0x03u}, + {0x90u, 0x01u}, + {0x92u, 0x06u}, + {0x94u, 0x29u}, + {0x96u, 0x04u}, + {0x98u, 0x03u}, + {0x9Au, 0x20u}, + {0x9Eu, 0x03u}, + {0xA1u, 0x02u}, + {0xA3u, 0x04u}, + {0xA4u, 0x02u}, + {0xA6u, 0x11u}, + {0xA8u, 0x03u}, + {0xADu, 0x02u}, + {0xAFu, 0x05u}, + {0xB0u, 0x07u}, + {0xB2u, 0x10u}, + {0xB3u, 0x06u}, + {0xB4u, 0x60u}, + {0xB5u, 0x01u}, + {0xB6u, 0x08u}, + {0xB8u, 0x80u}, + {0xBAu, 0x02u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x00u, 0x08u}, + {0x02u, 0x41u}, + {0x04u, 0x24u}, + {0x06u, 0x41u}, + {0x08u, 0x40u}, + {0x09u, 0x40u}, + {0x0Au, 0xB0u}, + {0x0Bu, 0x04u}, + {0x0Du, 0x02u}, + {0x0Eu, 0x18u}, + {0x0Fu, 0x02u}, + {0x10u, 0x02u}, + {0x12u, 0x20u}, + {0x13u, 0x01u}, + {0x15u, 0x20u}, + {0x16u, 0x20u}, + {0x18u, 0x20u}, + {0x1Cu, 0x08u}, + {0x1Du, 0x4Au}, + {0x1Eu, 0x08u}, + {0x1Fu, 0x20u}, + {0x20u, 0x04u}, + {0x22u, 0xA0u}, + {0x26u, 0x08u}, + {0x27u, 0x04u}, + {0x29u, 0x11u}, + {0x2Bu, 0x21u}, + {0x2Cu, 0x80u}, + {0x2Fu, 0x01u}, + {0x30u, 0x42u}, + {0x32u, 0x18u}, + {0x38u, 0x04u}, + {0x39u, 0x20u}, + {0x3Au, 0x51u}, + {0x3Bu, 0x40u}, + {0x41u, 0x08u}, + {0x42u, 0x40u}, + {0x49u, 0x01u}, + {0x4Bu, 0x11u}, + {0x51u, 0x40u}, + {0x5Du, 0x10u}, + {0x5Fu, 0x80u}, + {0x66u, 0x20u}, + {0x67u, 0x02u}, + {0x6Du, 0x04u}, + {0x6Eu, 0x20u}, + {0x6Fu, 0x02u}, + {0x86u, 0x10u}, + {0x89u, 0x1Cu}, + {0x8Bu, 0x02u}, + {0x8Eu, 0x80u}, + {0x8Fu, 0x80u}, + {0x92u, 0xE0u}, + {0x93u, 0x54u}, + {0x95u, 0x80u}, + {0x99u, 0x10u}, + {0x9Au, 0x11u}, + {0x9Du, 0x41u}, + {0x9Fu, 0x04u}, + {0xA0u, 0x82u}, + {0xA1u, 0x40u}, + {0xA3u, 0x01u}, + {0xA4u, 0x04u}, + {0xA5u, 0x0Au}, + {0xA6u, 0x20u}, + {0xA7u, 0x20u}, + {0xA8u, 0x21u}, + {0xA9u, 0x84u}, + {0xADu, 0x22u}, + {0xAFu, 0x20u}, + {0xB3u, 0x41u}, + {0xB5u, 0x01u}, + {0xB6u, 0x20u}, + {0xB7u, 0x20u}, + {0xC0u, 0xFDu}, + {0xC2u, 0xFFu}, + {0xC4u, 0x6Du}, + {0xCAu, 0x9Fu}, + {0xCCu, 0x0Fu}, + {0xCEu, 0x0Fu}, + {0xD0u, 0x03u}, + {0xD2u, 0x04u}, + {0xD6u, 0x30u}, + {0xD8u, 0x30u}, + {0xE0u, 0x84u}, + {0xE2u, 0x20u}, + {0xE4u, 0x10u}, + {0xE6u, 0xC0u}, + {0xEAu, 0x01u}, + {0xECu, 0x02u}, + {0x01u, 0x12u}, + {0x03u, 0x01u}, + {0x0Du, 0x01u}, + {0x0Fu, 0x06u}, + {0x16u, 0x01u}, + {0x17u, 0x13u}, + {0x19u, 0x01u}, + {0x1Bu, 0x04u}, + {0x25u, 0x01u}, + {0x26u, 0x02u}, + {0x27u, 0x1Au}, + {0x2Bu, 0x13u}, + {0x2Fu, 0x33u}, + {0x30u, 0x02u}, + {0x31u, 0x08u}, + {0x33u, 0x20u}, + {0x34u, 0x01u}, + {0x35u, 0x10u}, + {0x37u, 0x07u}, + {0x3Bu, 0x80u}, + {0x3Fu, 0x10u}, + {0x56u, 0x08u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Du, 0x10u}, + {0x5Fu, 0x01u}, + {0x80u, 0x10u}, + {0x81u, 0x03u}, + {0x82u, 0xE0u}, + {0x84u, 0x40u}, + {0x86u, 0x18u}, + {0x87u, 0x01u}, + {0x88u, 0x0Fu}, + {0x89u, 0x01u}, + {0x8Cu, 0x50u}, + {0x8Du, 0x40u}, + {0x8Eu, 0x02u}, + {0x8Fu, 0x18u}, + {0x90u, 0x50u}, + {0x91u, 0x03u}, + {0x92u, 0x01u}, + {0x93u, 0x20u}, + {0x94u, 0x10u}, + {0x95u, 0x01u}, + {0x96u, 0x80u}, + {0x98u, 0x50u}, + {0x99u, 0x40u}, + {0x9Au, 0x04u}, + {0x9Bu, 0x07u}, + {0x9Du, 0x4Fu}, + {0x9Eu, 0x0Fu}, + {0xA1u, 0x90u}, + {0xA2u, 0x0Fu}, + {0xA3u, 0x07u}, + {0xA4u, 0x40u}, + {0xA5u, 0x42u}, + {0xA6u, 0x18u}, + {0xA7u, 0x05u}, + {0xA8u, 0x10u}, + {0xA9u, 0x1Fu}, + {0xAAu, 0x20u}, + {0xACu, 0x0Fu}, + {0xADu, 0x44u}, + {0xAFu, 0x02u}, + {0xB1u, 0x1Fu}, + {0xB3u, 0xE0u}, + {0xB4u, 0x0Fu}, + {0xB6u, 0xF0u}, + {0xB9u, 0x08u}, + {0xBAu, 0x80u}, + {0xBEu, 0x10u}, + {0xBFu, 0x04u}, + {0xD4u, 0x20u}, + {0xD6u, 0x04u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDFu, 0x01u}, + {0x00u, 0x88u}, + {0x03u, 0x8Cu}, + {0x08u, 0x04u}, + {0x0Au, 0xA0u}, + {0x0Bu, 0x06u}, + {0x0Du, 0x08u}, + {0x10u, 0x90u}, + {0x12u, 0x21u}, + {0x13u, 0x10u}, + {0x17u, 0x04u}, + {0x19u, 0x20u}, + {0x1Au, 0x09u}, + {0x1Bu, 0x80u}, + {0x1Fu, 0x11u}, + {0x20u, 0xA0u}, + {0x23u, 0x50u}, + {0x25u, 0xE1u}, + {0x26u, 0x04u}, + {0x28u, 0x15u}, + {0x29u, 0x04u}, + {0x2Au, 0x01u}, + {0x2Fu, 0x19u}, + {0x30u, 0x08u}, + {0x31u, 0x01u}, + {0x32u, 0x40u}, + {0x33u, 0x20u}, + {0x36u, 0x04u}, + {0x37u, 0x10u}, + {0x38u, 0x22u}, + {0x39u, 0x04u}, + {0x3Bu, 0x40u}, + {0x3Du, 0x82u}, + {0x58u, 0x40u}, + {0x5Au, 0x05u}, + {0x5Bu, 0x20u}, + {0x5Du, 0x80u}, + {0x5Eu, 0x02u}, + {0x5Fu, 0x01u}, + {0x60u, 0x20u}, + {0x61u, 0xA0u}, + {0x63u, 0x80u}, + {0x67u, 0x01u}, + {0x6Cu, 0x04u}, + {0x6Du, 0x08u}, + {0x84u, 0x41u}, + {0x86u, 0x10u}, + {0x87u, 0x04u}, + {0x88u, 0x10u}, + {0x8Cu, 0x84u}, + {0x90u, 0x22u}, + {0x91u, 0x04u}, + {0x92u, 0xE4u}, + {0x95u, 0x80u}, + {0x96u, 0x08u}, + {0x97u, 0x44u}, + {0x99u, 0x10u}, + {0x9Au, 0x01u}, + {0x9Bu, 0x10u}, + {0x9Cu, 0x90u}, + {0x9Du, 0x45u}, + {0x9Eu, 0x10u}, + {0xA0u, 0x8Au}, + {0xA3u, 0x01u}, + {0xA4u, 0x40u}, + {0xA6u, 0x01u}, + {0xA7u, 0x60u}, + {0xA8u, 0x02u}, + {0xA9u, 0x80u}, + {0xABu, 0x61u}, + {0xB0u, 0x01u}, + {0xB1u, 0x04u}, + {0xB3u, 0x40u}, + {0xB6u, 0x10u}, + {0xC0u, 0x0Fu}, + {0xC2u, 0x2Fu}, + {0xC4u, 0x2Fu}, + {0xCAu, 0x7Fu}, + {0xCCu, 0x6Fu}, + {0xCEu, 0x9Fu}, + {0xD6u, 0x1Fu}, + {0xD8u, 0x1Fu}, + {0xE0u, 0x80u}, + {0xE2u, 0x22u}, + {0xE4u, 0x02u}, + {0xE6u, 0x08u}, + {0xEAu, 0x04u}, + {0xECu, 0x20u}, + {0xEEu, 0x83u}, + {0x02u, 0x23u}, + {0x03u, 0x04u}, + {0x07u, 0x38u}, + {0x08u, 0x61u}, + {0x09u, 0x0Du}, + {0x0Au, 0x16u}, + {0x0Du, 0x0Du}, + {0x0Fu, 0x20u}, + {0x13u, 0x10u}, + {0x14u, 0x61u}, + {0x16u, 0x0Eu}, + {0x17u, 0x02u}, + {0x1Au, 0x08u}, + {0x1Bu, 0x11u}, + {0x1Cu, 0x5Cu}, + {0x1Eu, 0x03u}, + {0x1Fu, 0x40u}, + {0x21u, 0x18u}, + {0x27u, 0x08u}, + {0x29u, 0x18u}, + {0x2Au, 0x1Cu}, + {0x2Du, 0x10u}, + {0x32u, 0x1Au}, + {0x33u, 0x70u}, + {0x34u, 0x60u}, + {0x35u, 0x03u}, + {0x36u, 0x0Fu}, + {0x37u, 0x0Cu}, + {0x38u, 0x20u}, + {0x3Au, 0x88u}, + {0x3Bu, 0x08u}, + {0x3Eu, 0x10u}, + {0x40u, 0x02u}, + {0x47u, 0x04u}, + {0x49u, 0xFFu}, + {0x4Au, 0x07u}, + {0x4Bu, 0xFFu}, + {0x4Cu, 0x40u}, + {0x4Du, 0x20u}, + {0x4Eu, 0xF0u}, + {0x4Fu, 0x05u}, + {0x50u, 0x08u}, + {0x56u, 0x02u}, + {0x57u, 0x12u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Au, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x02u}, + {0x5Du, 0x22u}, + {0x5Fu, 0x01u}, + {0x60u, 0x40u}, + {0x61u, 0xA8u}, + {0x62u, 0x40u}, + {0x63u, 0x20u}, + {0x81u, 0xAAu}, + {0x87u, 0xFFu}, + {0x89u, 0xF0u}, + {0x8Au, 0x03u}, + {0x8Bu, 0x0Fu}, + {0x8Du, 0xFFu}, + {0x8Eu, 0x02u}, + {0x91u, 0x0Fu}, + {0x92u, 0x04u}, + {0x93u, 0xF0u}, + {0x97u, 0x33u}, + {0x99u, 0xAAu}, + {0x9Du, 0x55u}, + {0xA1u, 0xFFu}, + {0xA2u, 0x01u}, + {0xA5u, 0xAAu}, + {0xA9u, 0xFFu}, + {0xAAu, 0x04u}, + {0xAFu, 0xCCu}, + {0xB2u, 0x02u}, + {0xB3u, 0xFFu}, + {0xB4u, 0x04u}, + {0xB6u, 0x01u}, + {0xBEu, 0x54u}, + {0xBFu, 0x04u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDFu, 0x01u}, + {0x00u, 0x20u}, + {0x03u, 0x01u}, + {0x05u, 0x10u}, + {0x06u, 0x80u}, + {0x09u, 0x02u}, + {0x0Eu, 0x21u}, + {0x0Fu, 0x08u}, + {0x11u, 0x20u}, + {0x13u, 0x02u}, + {0x17u, 0x10u}, + {0x18u, 0x04u}, + {0x19u, 0x40u}, + {0x1Bu, 0x08u}, + {0x1Du, 0x28u}, + {0x1Eu, 0x21u}, + {0x22u, 0x08u}, + {0x24u, 0x09u}, + {0x25u, 0x04u}, + {0x26u, 0x20u}, + {0x27u, 0x20u}, + {0x28u, 0x06u}, + {0x2Bu, 0x50u}, + {0x2Du, 0xA8u}, + {0x2Fu, 0x80u}, + {0x30u, 0x08u}, + {0x32u, 0x10u}, + {0x33u, 0x82u}, + {0x35u, 0x01u}, + {0x36u, 0xA8u}, + {0x38u, 0x50u}, + {0x39u, 0x20u}, + {0x3Au, 0x08u}, + {0x3Bu, 0x01u}, + {0x3Cu, 0x41u}, + {0x3Du, 0x08u}, + {0x3Eu, 0x02u}, + {0x3Fu, 0x10u}, + {0x45u, 0x20u}, + {0x54u, 0x04u}, + {0x56u, 0x80u}, + {0x57u, 0x04u}, + {0x5Eu, 0x18u}, + {0x5Fu, 0x20u}, + {0x64u, 0x01u}, + {0x66u, 0x80u}, + {0x6Du, 0x90u}, + {0x6Eu, 0x04u}, + {0x74u, 0x20u}, + {0x76u, 0x21u}, + {0x83u, 0x21u}, + {0x86u, 0x02u}, + {0x87u, 0x20u}, + {0x88u, 0x0Cu}, + {0x8Bu, 0x18u}, + {0x8Cu, 0x04u}, + {0x90u, 0x40u}, + {0x94u, 0x18u}, + {0x95u, 0x40u}, + {0x96u, 0x11u}, + {0x97u, 0x60u}, + {0x99u, 0x11u}, + {0x9Bu, 0x11u}, + {0x9Cu, 0xA9u}, + {0x9Eu, 0x08u}, + {0xA0u, 0x08u}, + {0xA1u, 0x12u}, + {0xA2u, 0x80u}, + {0xA3u, 0x42u}, + {0xA4u, 0x04u}, + {0xA5u, 0x0Du}, + {0xA8u, 0x04u}, + {0xACu, 0x40u}, + {0xADu, 0x02u}, + {0xB0u, 0x20u}, + {0xB2u, 0x88u}, + {0xB3u, 0x02u}, + {0xB4u, 0x40u}, + {0xC0u, 0x53u}, + {0xC2u, 0xE8u}, + {0xC4u, 0x4Au}, + {0xCAu, 0xFFu}, + {0xCCu, 0xFFu}, + {0xCEu, 0xFFu}, + {0xD0u, 0x20u}, + {0xD6u, 0x40u}, + {0xE0u, 0x80u}, + {0xE2u, 0x20u}, + {0xE4u, 0x82u}, + {0xE8u, 0xC0u}, + {0xEAu, 0x04u}, + {0xECu, 0xA0u}, + {0xEEu, 0x02u}, + {0x01u, 0x04u}, + {0x03u, 0x40u}, + {0x09u, 0x3Cu}, + {0x0Bu, 0x82u}, + {0x0Du, 0xBFu}, + {0x13u, 0x04u}, + {0x19u, 0x08u}, + {0x1Fu, 0x23u}, + {0x21u, 0x1Cu}, + {0x23u, 0xA1u}, + {0x25u, 0x18u}, + {0x26u, 0x01u}, + {0x29u, 0xA7u}, + {0x2Bu, 0x18u}, + {0x2Du, 0x10u}, + {0x2Eu, 0x01u}, + {0x31u, 0x40u}, + {0x33u, 0x1Fu}, + {0x34u, 0x01u}, + {0x35u, 0x80u}, + {0x37u, 0x38u}, + {0x39u, 0x20u}, + {0x3Au, 0x02u}, + {0x3Bu, 0x08u}, + {0x3Eu, 0x10u}, + {0x40u, 0x34u}, + {0x41u, 0x05u}, + {0x42u, 0x01u}, + {0x44u, 0x02u}, + {0x45u, 0x0Cu}, + {0x47u, 0xE0u}, + {0x48u, 0x21u}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Cu, 0x62u}, + {0x4Du, 0xA0u}, + {0x4Eu, 0xF0u}, + {0x4Fu, 0x41u}, + {0x50u, 0x0Cu}, + {0x54u, 0x18u}, + {0x56u, 0x04u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Au, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x22u}, + {0x5Du, 0x22u}, + {0x5Fu, 0x01u}, + {0x66u, 0x40u}, + {0x67u, 0x02u}, + {0x69u, 0x10u}, + {0x6Au, 0x30u}, + {0x6Bu, 0x10u}, + {0x6Du, 0x10u}, + {0x6Eu, 0x10u}, + {0x6Fu, 0x12u}, + {0x80u, 0x1Fu}, + {0x82u, 0xE0u}, + {0x84u, 0x0Cu}, + {0x85u, 0x9Fu}, + {0x88u, 0xC3u}, + {0x89u, 0x9Fu}, + {0x8Cu, 0x08u}, + {0x8Du, 0x80u}, + {0x90u, 0x41u}, + {0x91u, 0x04u}, + {0x93u, 0x38u}, + {0x94u, 0xF3u}, + {0x96u, 0x0Cu}, + {0x98u, 0x04u}, + {0x99u, 0x12u}, + {0x9Bu, 0x45u}, + {0x9Cu, 0xFFu}, + {0xA2u, 0xE3u}, + {0xA4u, 0x1Cu}, + {0xA6u, 0xE3u}, + {0xA8u, 0x82u}, + {0xADu, 0x09u}, + {0xAFu, 0x46u}, + {0xB0u, 0x2Cu}, + {0xB1u, 0x1Cu}, + {0xB2u, 0x0Fu}, + {0xB3u, 0x03u}, + {0xB4u, 0x10u}, + {0xB5u, 0x60u}, + {0xB6u, 0xC0u}, + {0xB7u, 0x80u}, + {0xBAu, 0x0Au}, + {0xBEu, 0x10u}, + {0xBFu, 0x10u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDCu, 0x22u}, + {0xDFu, 0x01u}, + {0x05u, 0x85u}, + {0x06u, 0x21u}, + {0x07u, 0x04u}, + {0x0Cu, 0x20u}, + {0x0Eu, 0x62u}, + {0x0Fu, 0x02u}, + {0x10u, 0x02u}, + {0x13u, 0x08u}, + {0x15u, 0x08u}, + {0x17u, 0x21u}, + {0x18u, 0x80u}, + {0x19u, 0x10u}, + {0x1Bu, 0x01u}, + {0x1Du, 0x01u}, + {0x1Eu, 0x29u}, + {0x1Fu, 0x08u}, + {0x21u, 0x44u}, + {0x22u, 0x01u}, + {0x23u, 0x1Au}, + {0x24u, 0x04u}, + {0x25u, 0x80u}, + {0x26u, 0x02u}, + {0x27u, 0x21u}, + {0x29u, 0x85u}, + {0x2Bu, 0x08u}, + {0x2Fu, 0x03u}, + {0x30u, 0x20u}, + {0x31u, 0x80u}, + {0x32u, 0x01u}, + {0x36u, 0x02u}, + {0x37u, 0x20u}, + {0x38u, 0x80u}, + {0x3Bu, 0x12u}, + {0x3Du, 0x90u}, + {0x3Eu, 0x04u}, + {0x40u, 0x04u}, + {0x41u, 0x40u}, + {0x43u, 0x09u}, + {0x48u, 0x10u}, + {0x4Au, 0x01u}, + {0x50u, 0x02u}, + {0x5Au, 0x01u}, + {0x61u, 0x50u}, + {0x63u, 0x80u}, + {0x82u, 0x42u}, + {0x83u, 0x06u}, + {0x88u, 0x80u}, + {0x89u, 0x10u}, + {0x8Du, 0x40u}, + {0x8Fu, 0x40u}, + {0x91u, 0x10u}, + {0x92u, 0x04u}, + {0x95u, 0x60u}, + {0x99u, 0x40u}, + {0x9Au, 0x21u}, + {0x9Cu, 0x80u}, + {0x9Fu, 0x02u}, + {0xA0u, 0x20u}, + {0xA1u, 0x40u}, + {0xA4u, 0x10u}, + {0xA6u, 0x04u}, + {0xACu, 0x02u}, + {0xAFu, 0x40u}, + {0xB1u, 0x20u}, + {0xB2u, 0x08u}, + {0xB3u, 0x90u}, + {0xB4u, 0x20u}, + {0xB5u, 0x89u}, + {0xB6u, 0x10u}, + {0xB7u, 0x10u}, + {0xC0u, 0xF0u}, + {0xC2u, 0xF0u}, + {0xC4u, 0x75u}, + {0xCAu, 0x1Fu}, + {0xCCu, 0xADu}, + {0xCEu, 0x7Du}, + {0xD0u, 0x0Fu}, + {0xD2u, 0x08u}, + {0xD6u, 0x01u}, + {0xD8u, 0x0Du}, + {0xE0u, 0x40u}, + {0xE4u, 0x20u}, + {0xE6u, 0x40u}, + {0xE8u, 0xF0u}, + {0xEAu, 0x01u}, + {0xECu, 0x40u}, + {0x33u, 0x11u}, + {0x35u, 0x80u}, + {0x37u, 0x08u}, + {0x38u, 0x20u}, + {0x87u, 0x01u}, + {0x8Bu, 0x20u}, + {0xCCu, 0xF0u}, + {0xCEu, 0x10u}, + {0xE2u, 0x40u}, + {0x04u, 0x04u}, + {0x32u, 0x42u}, + {0x35u, 0x08u}, + {0x36u, 0x40u}, + {0x3Au, 0x80u}, + {0x58u, 0x10u}, + {0x63u, 0x40u}, + {0x86u, 0x02u}, + {0x8Du, 0x88u}, + {0x94u, 0x20u}, + {0x9Du, 0x80u}, + {0x9Fu, 0x08u}, + {0xA3u, 0x20u}, + {0xABu, 0x10u}, + {0xC0u, 0x20u}, + {0xCCu, 0xF0u}, + {0xCEu, 0x10u}, + {0xD4u, 0x80u}, + {0xD8u, 0x40u}, + {0xE2u, 0x40u}, + {0xEAu, 0x20u}, + {0x33u, 0x40u}, + {0x35u, 0x80u}, + {0x3Eu, 0x10u}, + {0x50u, 0x80u}, + {0x54u, 0x10u}, + {0x59u, 0x04u}, + {0x86u, 0x80u}, + {0x8Du, 0x04u}, + {0x90u, 0x04u}, + {0x94u, 0x20u}, + {0x96u, 0x80u}, + {0x97u, 0x40u}, + {0x9Cu, 0x10u}, + {0x9Eu, 0x80u}, + {0x9Fu, 0x08u}, + {0xA3u, 0x20u}, + {0xA6u, 0x40u}, + {0xCCu, 0x30u}, + {0xCEu, 0x20u}, + {0xD4u, 0x60u}, + {0xD6u, 0x40u}, + {0xE2u, 0x40u}, + {0x80u, 0x04u}, + {0x83u, 0x40u}, + {0x84u, 0x10u}, + {0x88u, 0x30u}, + {0x89u, 0x10u}, + {0x8Cu, 0x10u}, + {0x8Eu, 0x40u}, + {0x90u, 0x04u}, + {0x94u, 0x20u}, + {0x96u, 0x90u}, + {0x97u, 0x40u}, + {0x9Cu, 0x10u}, + {0x9Du, 0x80u}, + {0x9Fu, 0x48u}, + {0xA3u, 0x20u}, + {0xA4u, 0x90u}, + {0xA6u, 0x40u}, + {0xE0u, 0x20u}, + {0xE6u, 0xC0u}, + {0x16u, 0x10u}, + {0x7Du, 0x02u}, + {0x7Eu, 0x01u}, + {0x8Du, 0x01u}, + {0xC4u, 0x04u}, + {0xDEu, 0x05u}, + {0xE0u, 0x08u}, + {0x09u, 0x10u}, + {0x0Cu, 0x04u}, + {0x5Bu, 0x08u}, + {0x66u, 0x20u}, + {0x81u, 0x10u}, + {0x86u, 0x04u}, + {0x88u, 0x04u}, + {0x8Au, 0x11u}, + {0x8Eu, 0x04u}, + {0x96u, 0x02u}, + {0x9Au, 0x10u}, + {0xC2u, 0x06u}, + {0xD6u, 0x02u}, + {0xD8u, 0x01u}, + {0xE0u, 0x04u}, + {0xE2u, 0x02u}, + {0xE6u, 0x05u}, + {0x07u, 0x10u}, + {0x44u, 0x10u}, + {0x86u, 0x10u}, + {0x96u, 0x04u}, + {0x98u, 0x04u}, + {0x9Eu, 0x20u}, + {0x9Fu, 0x18u}, + {0xA1u, 0x10u}, + {0xA6u, 0x04u}, + {0xABu, 0x10u}, + {0xC0u, 0x04u}, + {0xD0u, 0x01u}, + {0x08u, 0x02u}, + {0x0Au, 0x04u}, + {0x0Eu, 0x08u}, + {0x0Fu, 0x40u}, + {0x12u, 0x18u}, + {0x17u, 0x02u}, + {0x83u, 0x02u}, + {0x86u, 0x01u}, + {0x8Cu, 0x02u}, + {0x96u, 0x04u}, + {0x98u, 0x04u}, + {0x9Cu, 0x10u}, + {0x9Eu, 0x30u}, + {0x9Fu, 0x08u}, + {0xA1u, 0x10u}, + {0xA6u, 0x04u}, + {0xC2u, 0x0Fu}, + {0xC4u, 0x0Eu}, + {0xE2u, 0x08u}, + {0x51u, 0x04u}, + {0x57u, 0x20u}, + {0x58u, 0x20u}, + {0x87u, 0x10u}, + {0x8Au, 0x80u}, + {0x8Bu, 0x40u}, + {0x95u, 0x20u}, + {0x96u, 0x10u}, + {0x97u, 0x40u}, + {0x98u, 0x20u}, + {0x9Fu, 0x88u}, + {0xA3u, 0x20u}, + {0xA9u, 0x80u}, + {0xAEu, 0x40u}, + {0xB0u, 0x80u}, + {0xB3u, 0x80u}, + {0xD4u, 0xE0u}, + {0xE4u, 0x40u}, + {0xEAu, 0x20u}, + {0xEEu, 0x40u}, + {0x03u, 0x10u}, + {0x13u, 0x01u}, + {0x14u, 0x20u}, + {0x1Fu, 0x10u}, + {0x21u, 0x10u}, + {0x23u, 0x80u}, + {0x26u, 0x80u}, + {0x5Fu, 0x02u}, + {0x63u, 0x02u}, + {0x83u, 0x10u}, + {0x87u, 0x01u}, + {0x88u, 0x20u}, + {0x89u, 0x04u}, + {0x8Bu, 0x02u}, + {0x8Fu, 0x09u}, + {0x95u, 0x28u}, + {0x97u, 0x20u}, + {0x9Fu, 0x88u}, + {0xA6u, 0x80u}, + {0xAAu, 0x10u}, + {0xC0u, 0x10u}, + {0xC4u, 0x30u}, + {0xC6u, 0x80u}, + {0xC8u, 0x70u}, + {0xD6u, 0xC0u}, + {0xE0u, 0x20u}, + {0xE6u, 0x10u}, + {0xEAu, 0x80u}, + {0x13u, 0x28u}, + {0x16u, 0x20u}, + {0x5Eu, 0x01u}, + {0x66u, 0x01u}, + {0x78u, 0x04u}, + {0x7Du, 0x20u}, + {0x84u, 0x10u}, + {0x8Eu, 0x01u}, + {0x92u, 0x01u}, + {0x98u, 0x04u}, + {0x9Cu, 0x10u}, + {0x9Eu, 0x20u}, + {0x9Fu, 0x08u}, + {0xA1u, 0x10u}, + {0xAAu, 0x08u}, + {0xAFu, 0x40u}, + {0xC4u, 0x0Eu}, + {0xD6u, 0x01u}, + {0xD8u, 0x01u}, + {0xDEu, 0x03u}, + {0xE4u, 0x02u}, + {0x14u, 0x10u}, + {0x88u, 0x10u}, + {0xABu, 0x20u}, + {0xC4u, 0x04u}, + {0xE2u, 0x04u}, + {0x10u, 0x07u}, + {0x11u, 0x01u}, + {0x1Au, 0x03u}, + {0x1Bu, 0x01u}, + {0x1Cu, 0x05u}, + }; + + + + CYPACKED typedef struct { + void CYFAR *address; + uint16 size; + } CYPACKED_ATTR cfg_memset_t; + + + CYPACKED typedef struct { + void CYFAR *dest; + const void CYCODE *src; + uint16 size; + } CYPACKED_ATTR cfg_memcpy_t; + + static const cfg_memset_t CYCODE cfg_memset_list[] = { + /* address, size */ + {(void CYFAR *)(CYREG_I2C_XCFG), 25u}, + {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, + {(void CYFAR *)(CYREG_PRT4_DR), 48u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 3584u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P7_U1_BASE), 384u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, + {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, + {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, + {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, + }; + + /* IOPORT_7 Address: CYDEV_PRTDSI_PRT12_BASE Size (bytes): 6 */ + static const uint8 CYCODE BS_IOPORT_7_VAL[] = { + 0x41u, 0x03u, 0x00u, 0x00u, 0x1Cu, 0x00u}; + + /* IDMUX_IRQ Address: CYREG_IDMUX_IRQ_CTL0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IDMUX_IRQ_VAL[] = { + 0xFFu, 0xABu, 0xAAu, 0xC0u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* UDB_0_5_0_CONFIG Address: CYDEV_UCFG_B0_P7_U0_BASE Size (bytes): 128 */ + static const uint8 CYCODE BS_UDB_0_5_0_CONFIG_VAL[] = { + 0x00u, 0x22u, 0xB1u, 0x80u, 0xFFu, 0x7Fu, 0x00u, 0x00u, 0xF9u, 0x73u, 0x06u, 0x0Cu, 0x4Eu, 0x00u, 0x91u, 0x33u, + 0x40u, 0x33u, 0x00u, 0x00u, 0x06u, 0x0Cu, 0x00u, 0x00u, 0x00u, 0x04u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x04u, 0x0Fu, 0x00u, 0x70u, 0x02u, 0x11u, 0x00u, 0x00u, 0xCEu, 0x0Cu, 0x21u, 0x73u, 0x00u, 0x08u, 0x00u, 0x00u, + 0x08u, 0x30u, 0x86u, 0x0Fu, 0x76u, 0x80u, 0x07u, 0x40u, 0x00u, 0x80u, 0xA0u, 0x08u, 0x00u, 0x00u, 0x01u, 0x00u, + 0x65u, 0x02u, 0x03u, 0x00u, 0x04u, 0xC0u, 0xE0u, 0x00u, 0x0Au, 0xFFu, 0xFFu, 0xFFu, 0x62u, 0xA0u, 0xF0u, 0x41u, + 0x0Cu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x04u, 0x04u, 0x04u, 0x04u, 0x33u, 0x93u, 0x00u, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x02u, 0x00u, 0x10u, 0x30u, 0x10u, 0x00u, 0x10u, 0x10u, 0x12u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ + static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { + 0x8Fu, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Bu, 0x01u, 0x03u, 0x00u, 0x8Du, 0x01u, 0x8Au, 0x01u}; + + static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { + /* dest, src, size */ + {(void CYFAR *)(CYDEV_PRTDSI_PRT12_BASE), BS_IOPORT_7_VAL, 6u}, + {(void CYFAR *)(CYREG_IDMUX_IRQ_CTL0), BS_IDMUX_IRQ_VAL, 8u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P7_U0_BASE), BS_UDB_0_5_0_CONFIG_VAL, 128u}, + {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, + }; + + uint8 CYDATA i; + + /* Zero out critical memory blocks before beginning configuration */ + for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) + { + const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; + CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); + } + + /* Copy device configuration data into registers */ + for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) + { + const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i]; + void * CYDATA destPtr = mc->dest; + const void CYCODE * CYDATA srcPtr = mc->src; + uint16 CYDATA numBytes = mc->size; + CYCONFIGCPYCODE(destPtr, srcPtr, numBytes); + } + + cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); + + /* Perform normal device configuration. Order is not critical for these items. */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_DSM0_CR3), 0x0Au); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_LUT3_CR), 0x0303u); + + /* Enable digital routing */ + CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u); + + /* Enable UDB array */ + CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u); + } + + + /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DR), (const void CYCODE *)(BS_IOPINS0_0_VAL), 10u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR), (const void CYCODE *)(BS_IOPINS0_7_VAL), 10u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR + 0x0000000Bu), (const void CYCODE *)(BS_IOPINS1_7_VAL), 5u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT1_DR), (const void CYCODE *)(BS_IOPINS0_1_VAL), 10u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DR), (const void CYCODE *)(BS_IOPINS0_2_VAL), 10u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DM0), (const void CYCODE *)(BS_IOPINS0_3_VAL), 8u); + /* Switch Boost to the precision bandgap reference from its internal reference */ + CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u)); + + /* Perform basic analog initialization to defaults */ + AnalogSetDefault(); + + /* Configure alternate active mode */ + CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u); +} diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/cyfitter_cfg.h b/source/hic_hal/cypress/psoc5lp/PSoC5/cyfitter_cfg.h new file mode 100644 index 0000000000..657ababad4 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/cyfitter_cfg.h @@ -0,0 +1,48 @@ +/******************************************************************************* +* File Name: cyfitter_cfg.h +* +* Description: +* This file provides basic startup and mux configuration settings +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#ifndef CYFITTER_CFG_H +#define CYFITTER_CFG_H + +#include "cytypes.h" + +extern void cyfitter_cfg(void); + +/* Analog Set/Unset methods */ +extern void SetAnalogRoutingPumps(uint8 enabled); +extern void AdcMux_Set(uint8 channel); +extern void AdcMux_Unset(uint8 channel); +extern void ADC_DelSig_AMux_Set(uint8 channel); +extern void ADC_DelSig_AMux_Unset(uint8 channel); +/* ADC_DelSig_AMux__addrTable is an implementation detail of the AMux. + Code that depends on it may be incompatible with other versions + of PSoC Creator. */ +extern uint8 CYXDATA * const CYCODE ADC_DelSig_AMux__addrTable[2]; +/* ADC_DelSig_AMux__maskTable is an implementation detail of the AMux. + Code that depends on it may be incompatible with other versions + of PSoC Creator. */ +extern const uint8 CYCODE ADC_DelSig_AMux__maskTable[2]; + + +#endif /* CYFITTER_CFG_H */ + +/*[]*/ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/cypins.h b/source/hic_hal/cypress/psoc5lp/PSoC5/cypins.h new file mode 100644 index 0000000000..0d831de7f0 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/cypins.h @@ -0,0 +1,317 @@ +/***************************************************************************//** +* \file cypins.h +* \version 5.70 +* +* \brief This file contains the function prototypes and constants used for a +* port/pin in access and control. +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_BOOT_CYPINS_H) +#define CY_BOOT_CYPINS_H + +#include "cyfitter.h" +#include "cytypes.h" + + +/************************************** +* API Parameter Constants +**************************************/ + +#define CY_PINS_PC_DRIVE_MODE_SHIFT (0x01u) +#define CY_PINS_PC_DRIVE_MODE_MASK ((uint8)(0x07u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_0 ((uint8)(0x00u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_1 ((uint8)(0x01u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_2 ((uint8)(0x02u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_3 ((uint8)(0x03u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_4 ((uint8)(0x04u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_5 ((uint8)(0x05u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_6 ((uint8)(0x06u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_7 ((uint8)(0x07u << CY_PINS_PC_DRIVE_MODE_SHIFT)) + + +/* SetPinDriveMode */ +#define CY_PINS_DM_ALG_HIZ (CY_PINS_PC_DRIVE_MODE_0) +#define CY_PINS_DM_DIG_HIZ (CY_PINS_PC_DRIVE_MODE_1) +#define CY_PINS_DM_RES_UP (CY_PINS_PC_DRIVE_MODE_2) +#define CY_PINS_DM_RES_DWN (CY_PINS_PC_DRIVE_MODE_3) +#define CY_PINS_DM_OD_LO (CY_PINS_PC_DRIVE_MODE_4) +#define CY_PINS_DM_OD_HI (CY_PINS_PC_DRIVE_MODE_5) +#define CY_PINS_DM_STRONG (CY_PINS_PC_DRIVE_MODE_6) +#define CY_PINS_DM_RES_UPDWN (CY_PINS_PC_DRIVE_MODE_7) + + +/************************************** +* Register Constants +**************************************/ + +/* Port Pin Configuration Register */ +#define CY_PINS_PC_DATAOUT (0x01u) +#define CY_PINS_PC_PIN_FASTSLEW (0xBFu) +#define CY_PINS_PC_PIN_SLOWSLEW (0x40u) +#define CY_PINS_PC_PIN_STATE (0x10u) +#define CY_PINS_PC_BIDIR_EN (0x20u) +#define CY_PINS_PC_SLEW (0x40u) +#define CY_PINS_PC_BYPASS (0x80u) + + +/************************************** +* Pin API Macros +**************************************/ + +/******************************************************************************* +* Macro Name: CyPins_ReadPin +****************************************************************************//** +* +* Reads the current value on the pin (pin state, PS). +* +* \param pinPC: Port pin configuration register (uint16). +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* \param in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* \return +* Pin state +* 0: Logic low value +* Non-0: Logic high value +* +*******************************************************************************/ +#define CyPins_ReadPin(pinPC) ( *(reg8 *)(pinPC) & CY_PINS_PC_PIN_STATE ) + + +/******************************************************************************* +* Macro Name: CyPins_SetPin +****************************************************************************//** +* +* Set the output value for the pin (data register, DR) to a logic high. +* +* Note that this only has an effect for pins configured as software pins that +* are not driven by hardware. +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param pinPC: Port pin configuration register (uint16). +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* \param in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +*******************************************************************************/ +#define CyPins_SetPin(pinPC) ( *(reg8 *)(pinPC) |= CY_PINS_PC_DATAOUT) + + +/******************************************************************************* +* Macro Name: CyPins_ClearPin +****************************************************************************//** +* +* This macro sets the state of the specified pin to 0. +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param pinPC: address of a Pin Configuration register. +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* \param in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +*******************************************************************************/ +#define CyPins_ClearPin(pinPC) ( *(reg8 *)(pinPC) &= ((uint8)(~CY_PINS_PC_DATAOUT))) + + +/******************************************************************************* +* Macro Name: CyPins_SetPinDriveMode +****************************************************************************//** +* +* Sets the drive mode for the pin (DM). +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param pinPC: Port pin configuration register (uint16) +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* \param in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* \param mode: Desired drive mode +* +* Define Source +* PIN_DM_ALG_HIZ Analog HiZ +* PIN_DM_DIG_HIZ Digital HiZ +* PIN_DM_RES_UP Resistive pull up +* PIN_DM_RES_DWN Resistive pull down +* PIN_DM_OD_LO Open drain - drive low +* PIN_DM_OD_HI Open drain - drive high +* PIN_DM_STRONG Strong CMOS Output +* PIN_DM_RES_UPDWN Resistive pull up/down +* +*******************************************************************************/ +#define CyPins_SetPinDriveMode(pinPC, mode) \ + ( *(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & ((uint8)(~CY_PINS_PC_DRIVE_MODE_MASK))) | \ + ((mode) & CY_PINS_PC_DRIVE_MODE_MASK)) + + +/******************************************************************************* +* Macro Name: CyPins_ReadPinDriveMode +****************************************************************************//** +* +* Reads the drive mode for the pin (DM). +* +* \param pinPC: Port pin configuration register (uint16) +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* \param in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* +* \return +* mode: The current drive mode for the pin +* +* Define Source +* PIN_DM_ALG_HIZ Analog HiZ +* PIN_DM_DIG_HIZ Digital HiZ +* PIN_DM_RES_UP Resistive pull up +* PIN_DM_RES_DWN Resistive pull down +* PIN_DM_OD_LO Open drain - drive low +* PIN_DM_OD_HI Open drain - drive high +* PIN_DM_STRONG Strong CMOS Output +* PIN_DM_RES_UPDWN Resistive pull up/down +* +*******************************************************************************/ +#define CyPins_ReadPinDriveMode(pinPC) (*(reg8 *)(pinPC) & CY_PINS_PC_DRIVE_MODE_MASK) + + +/******************************************************************************* +* Macro Name: CyPins_FastSlew +****************************************************************************//** +* +* Set the slew rate for the pin to fast the edge rate. +* Note that this only applies for pins in strong output drive modes, +* not to resistive drive modes. +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param pinPC: address of a Pin Configuration register. +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* \param in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* +*******************************************************************************/ +#define CyPins_FastSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & CY_PINS_PC_PIN_FASTSLEW)) + + +/******************************************************************************* +* Macro Name: CyPins_SlowSlew +****************************************************************************//** +* +* Set the slew rate for the pin to slow the edge rate. +* Note that this only applies for pins in strong output drive modes, +* not to resistive drive modes. +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param pinPC: address of a Pin Configuration register. +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* \param in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +*******************************************************************************/ +#define CyPins_SlowSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) | CY_PINS_PC_PIN_SLOWSLEW)) + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define PC_DRIVE_MODE_SHIFT (CY_PINS_PC_DRIVE_MODE_SHIFT) +#define PC_DRIVE_MODE_MASK (CY_PINS_PC_DRIVE_MODE_MASK) +#define PC_DRIVE_MODE_0 (CY_PINS_PC_DRIVE_MODE_0) +#define PC_DRIVE_MODE_1 (CY_PINS_PC_DRIVE_MODE_1) +#define PC_DRIVE_MODE_2 (CY_PINS_PC_DRIVE_MODE_2) +#define PC_DRIVE_MODE_3 (CY_PINS_PC_DRIVE_MODE_3) +#define PC_DRIVE_MODE_4 (CY_PINS_PC_DRIVE_MODE_4) +#define PC_DRIVE_MODE_5 (CY_PINS_PC_DRIVE_MODE_5) +#define PC_DRIVE_MODE_6 (CY_PINS_PC_DRIVE_MODE_6) +#define PC_DRIVE_MODE_7 (CY_PINS_PC_DRIVE_MODE_7) + +#define PIN_DM_ALG_HIZ (CY_PINS_DM_ALG_HIZ) +#define PIN_DM_DIG_HIZ (CY_PINS_DM_DIG_HIZ) +#define PIN_DM_RES_UP (CY_PINS_DM_RES_UP) +#define PIN_DM_RES_DWN (CY_PINS_DM_RES_DWN) +#define PIN_DM_OD_LO (CY_PINS_DM_OD_LO) +#define PIN_DM_OD_HI (CY_PINS_DM_OD_HI) +#define PIN_DM_STRONG (CY_PINS_DM_STRONG) +#define PIN_DM_RES_UPDWN (CY_PINS_DM_RES_UPDWN) + +#define PC_DATAOUT (CY_PINS_PC_DATAOUT) +#define PC_PIN_FASTSLEW (CY_PINS_PC_PIN_FASTSLEW) +#define PC_PIN_SLOWSLEW (CY_PINS_PC_PIN_SLOWSLEW) +#define PC_PIN_STATE (CY_PINS_PC_PIN_STATE) +#define PC_BIDIR_EN (CY_PINS_PC_BIDIR_EN) +#define PC_SLEW (CY_PINS_PC_SLEW) +#define PC_BYPASS (CY_PINS_PC_BYPASS) + +#endif /* (CY_BOOT_CYPINS_H) */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/PSoC5/cytypes.h b/source/hic_hal/cypress/psoc5lp/PSoC5/cytypes.h new file mode 100644 index 0000000000..dc4be974e3 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/PSoC5/cytypes.h @@ -0,0 +1,1505 @@ +/***************************************************************************//** +* \file cytypes.h +* \version 5.70 +* +* \brief CyTypes provides register access macros and approved types for use in +* firmware. +* +* \note Due to endiannesses of the hardware and some compilers, the register +* access macros for big endian compilers use some library calls to arrange +* data the correct way. +* +* Register Access macros and functions perform their operations on an +* input of the type pointer to void. The arguments passed to it should be +* pointers to the type associated with the register size. +* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value) +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#if !defined(CY_BOOT_CYTYPES_H) +#define CY_BOOT_CYTYPES_H + +#if defined(__C51__) + #include +#endif /* (__C51__) */ + +/* ARM and C99 or later */ +#if defined(__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) + #include +#endif /* (__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) */ + +#include "cyfitter.h" + + +#if defined( __ICCARM__ ) + /* Suppress warning for multiple volatile variables in an expression. */ + /* This is common in component code and usage is not order dependent. */ + #pragma diag_suppress=Pa082 +#endif /* defined( __ICCARM__ ) */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + + +/******************************************************************************* +* FAMILY encodes the overall architectural family +*******************************************************************************/ +#define CY_PSOC3 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) +#define CY_PSOC4 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) +#define CY_PSOC5 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5) + + +/******************************************************************************* +* MEMBER encodes both the family and the detailed architecture +*******************************************************************************/ +#ifdef CYDEV_CHIP_MEMBER_4D + #define CY_PSOC4_4000 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D) +#else + #define CY_PSOC4_4000 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4D */ + +#define CY_PSOC4_4100 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) +#define CY_PSOC4_4200 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) + +#ifdef CYDEV_CHIP_MEMBER_4F + #define CY_PSOC4_4100BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F) + #define CY_PSOC4_4200BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F) +#else + #define CY_PSOC4_4100BL (0u != 0u) + #define CY_PSOC4_4200BL (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4F */ + +#ifdef CYDEV_CHIP_MEMBER_4M + #define CY_PSOC4_4100M (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4M) + #define CY_PSOC4_4200M (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4M) +#else + #define CY_PSOC4_4100M (0u != 0u) + #define CY_PSOC4_4200M (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4M */ + +#ifdef CYDEV_CHIP_MEMBER_4H + #define CY_PSOC4_4200D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4H) +#else + #define CY_PSOC4_4200D (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4H */ + +#ifdef CYDEV_CHIP_MEMBER_4L + #define CY_PSOC4_4200L (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4L) +#else + #define CY_PSOC4_4200L (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4L */ + +#ifdef CYDEV_CHIP_MEMBER_4U + #define CY_PSOC4_4000U (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4U) +#else + #define CY_PSOC4_4000U (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4U */ + +#ifdef CYDEV_CHIP_MEMBER_4J + #define CY_PSOC4_4000S (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4J) +#else + #define CY_PSOC4_4000S (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4J */ + +#ifdef CYDEV_CHIP_MEMBER_4K + #define CY_PSOC4_4100S (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4K) +#else + #define CY_PSOC4_4100S (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4K */ + +#ifdef CYDEV_CHIP_MEMBER_4I + #define CY_PSOC4_4400 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4I) +#else + #define CY_PSOC4_4400 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4I */ + +#ifdef CYDEV_CHIP_MEMBER_4E + #define CY_CCG2 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4E) +#else + #define CY_CCG2 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4E */ + +#ifdef CYDEV_CHIP_MEMBER_4O + #define CY_CCG3 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4O) +#else + #define CY_CCG3 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4O */ + +#ifdef CYDEV_CHIP_MEMBER_4R + #define CY_CCG3PA (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4R) +#else + #define CY_CCG3PA (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4R */ + +#ifdef CYDEV_CHIP_MEMBER_4N + #define CY_CCG4 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4N) +#else + #define CY_CCG4 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4N */ + +#ifdef CYDEV_CHIP_MEMBER_4S + #define CY_CCG5 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4S) +#else + #define CY_CCG5 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4S */ + +#ifdef CYDEV_CHIP_MEMBER_4P + #define CY_PSOC4_4100BLII (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4P) + #define CY_PSOC4_4200BLII (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4P) +#else + #define CY_PSOC4_4100BLII (0u != 0u) + #define CY_PSOC4_4200BLII (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4P */ + +#ifdef CYDEV_CHIP_MEMBER_4V + #define CY_PSOC4_4100MS (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4V) + #define CY_PSOC4_4100MS (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4V) +#else + #define CY_PSOC4_4100MS (0u != 0u) + #define CY_PSOC4_4100MS (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4V */ + +#define CY_IP_HOBTO_DEVICE (!(0 == 1)) + + +/******************************************************************************* +* IP blocks +*******************************************************************************/ +#if (CY_PSOC4) + + /* Using SRSSv2 or SRS-Lite */ + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_SRSSV2 (0 != 0) + #define CY_IP_SRSSLT (!CY_IP_SRSSV2) + #else + #define CY_IP_SRSSV2 (0 == 0) + #define CY_IP_SRSSLT (!CY_IP_SRSSV2) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_CPUSSV3 (0 == 1) + #define CY_IP_CPUSSV2 (0 == 1) + #define CY_IP_CPUSS (0 == 1) + #else + #define CY_IP_CPUSSV3 (0 != 0) + #define CY_IP_CPUSSV2 (0 != 0) + #define CY_IP_CPUSS (0 == 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* CM0 present or CM0+ present (1=CM0, 0=CM0+) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_CPUSS_CM0 (0 == 0) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_CPUSS_CM0 (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #define CY_IP_CPUSS_CM0PLUS (!CY_IP_CPUSS_CM0) + #else + #define CY_IP_CPUSS_CM0 (0 == 0) + #define CY_IP_CPUSS_CM0PLUS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Flash memory present or not (1=Flash present, 0=Flash not present) */ + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_CPUSS_FLASHC_PRESENT (0 == 0) + #else + #define CY_IP_CPUSS_FLASHC_PRESENT (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Product uses FLASH-Lite or regular FLASH */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_FM (-1 == 0) + #define CY_IP_FMLT (-1 == 1) + #define CY_IP_FS (-1 == 2) + #define CY_IP_FSLT (-1 == 3) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_FM (-1 == 0) + #define CY_IP_FMLT (-1 == 1) + #define CY_IP_FS (-1 == 2) + #define CY_IP_FSLT (-1 == 3) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_FM (!CY_IP_FMLT) /* Regular FLASH */ + #define CY_IP_FMLT (0 != 0) /* FLASH-Lite */ + #define CY_IP_FS (0 != 0) /* FS */ + #define CY_IP_FSLT (0 != 0) /* FSLT */ + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Enable simultaneous execution/programming in multi-macro devices */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_FLASH_PARALLEL_PGM_EN (-1 == 1) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_FLASH_PARALLEL_PGM_EN (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_FLASH_PARALLEL_PGM_EN (0u != 0u) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Number of Flash macros used in the device (0, 1 or 2) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_FLASH_MACROS (-1u) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_FLASH_MACROS (-1u) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_FLASH_MACROS (1u) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* Number of interrupt request inputs to CM0 */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_INT_NR (-1u) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_INT_NR (-1u) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_INT_NR (32u) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Presence of the BLESS IP block */ + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_BLESS (0 != 0) + #define CY_IP_BLESSV3 (CYIPBLOCK_m0s8bless_VERSION == 3) + #else + #define CY_IP_BLESS (0 != 0) + #define CY_IP_BLESSV3 (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_USBDEV (0 != 0) + #else + #define CY_IP_USBDEV (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /*************************************************************************** + * Devices with the SPCIF_SYNCHRONOUS parameter set to one will not use + * the 36MHz Oscillator for Flash operation. Instead, flash write function + * ensures that the charge pump clock and the higher frequency clock (HFCLK) + * are set to the IMO at 48MHz prior to writing the flash. + ***************************************************************************/ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_SPCIF_SYNCHRONOUS (-1 == 1) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_SPCIF_SYNCHRONOUS (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_SPCIF_SYNCHRONOUS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* Watch Crystal Oscillator (WCO) is present (32kHz) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_BLESS) + #define CY_IP_WCO_WCO (0 != 0) + #define CY_IP_WCO_SRSSV2 (0 != 0) + #if (CY_IP_BLESSV3) + #define CY_IP_WCO_WCOV2 (0 == 0) + #define CY_IP_WCO_BLESS (0 != 0) + #else + #define CY_IP_WCO_WCOV2 (0 != 0) + #define CY_IP_WCO_BLESS (0 == 0) + #endif + #else + #define CY_IP_WCO_BLESS (0 != 0) + #define CY_IP_WCO_WCO (0 == 1) + #define CY_IP_WCO_WCOV2 (0 != 0) + #define CY_IP_WCO_SRSSV2 (-1 == 1) + #endif /* (CY_IP_BLESS) */ + #else + #define CY_IP_WCO_BLESS (0 != 0) + #define CY_IP_WCO_WCO (0 != 0) + #define CY_IP_WCO_WCOV2 (0 != 0) + #define CY_IP_WCO_SRSSV2 (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #define CY_IP_WCO (CY_IP_WCO_BLESS || CY_IP_WCO_WCO || CY_IP_WCO_WCOV2 || CY_IP_WCO_SRSSV2) + + /* External Crystal Oscillator is present (high frequency) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_BLESS) + #define CY_IP_ECO_SRSSV2 (0 != 0) + #define CY_IP_ECO_SRSSLT (0 != 0) + + #if (CY_IP_BLESSV3) + #define CY_IP_ECO_BLESS (0 != 0) + #define CY_IP_ECO_BLESSV3 (0 == 0) + #else + #define CY_IP_ECO_BLESS (0 == 0) + #define CY_IP_ECO_BLESSV3 (0 != 0) + #endif + #else + #define CY_IP_ECO_BLESS (0 != 0) + #define CY_IP_ECO_BLESSV3 (0 != 0) + #define CY_IP_ECO_SRSSV2 (-1 == 1) + #define CY_IP_ECO_SRSSLT ((0 != 0) && (0 != 0)) + #endif /* (CY_IP_BLESS) */ + #else + #define CY_IP_ECO_BLESS (0 != 0) + #define CY_IP_ECO_BLESSV3 (0 != 0) + #define CY_IP_ECO_SRSSV2 (0 != 0) + #define CY_IP_ECO_SRSSLT (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #define CY_IP_ECO (CY_IP_ECO_BLESS || CY_IP_ECO_SRSSV2 || CY_IP_ECO_BLESSV3 || CY_IP_ECO_SRSSLT) + + /* PLL is present */ + #if (CY_IP_HOBTO_DEVICE) + #if(CY_IP_SRSSV2) + #define CY_IP_PLL ((-1 != 0) || \ + (-1 != 0)) + + #define CY_IP_PLL_NR (-1u + \ + -1u) + + #elif (CY_IP_SRSSLT) + #define CY_IP_PLL (-1 == 1) + + #define CY_IP_PLL_NR (1) + #else + #define CY_IP_PLL (0 != 0) + #define CY_IP_PLL_NR (0) + #endif /* (CY_IP_SRSSV2) */ + #else + #define CY_IP_PLL (0 != 0) + #define CY_IP_PLL_NR (0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* Clock Source clk_lf implemented in SysTick Counter. When 0, not implemented, 1=implemented */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_SYSTICK_LFCLK_SOURCE (-1 != 0) + #else /* CY_IP_CPUSSV3 */ + #define CY_SYSTICK_LFCLK_SOURCE (-1 != 0) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_SYSTICK_LFCLK_SOURCE (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Flash Macro 0 has extra rows */ + #if (CY_IP_HOBTO_DEVICE) + #ifdef CYREG_SFLASH_MACRO_0_FREE_SFLASH0 + #define CY_SFLASH_XTRA_ROWS (0 == 0) + #else + #define CY_SFLASH_XTRA_ROWS (0 != 0) + #endif /* CYREG_SFLASH_MACRO_0_FREE_SFLASH0 */ + + #else + #define CY_SFLASH_XTRA_ROWS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + #if (CY_IP_USBDEV) + #define CY_IP_IMO_TRIMMABLE_BY_USB (0 == 0) + #else + #define CY_IP_IMO_TRIMMABLE_BY_USB (0 != 0) + #endif /* (CY_IP_USBDEV) */ + + + #if (CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2) + #define CY_IP_IMO_TRIMMABLE_BY_WCO (0 == 0) + #else + #define CY_IP_IMO_TRIMMABLE_BY_WCO (0 != 0) + #endif /* (CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2) */ + + + /* DW/DMA Controller present (0=No, 1=Yes) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_DMAC_PRESENT (-1 == 1) + #else + #define CY_IP_DMAC_PRESENT (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_DMAC_PRESENT (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_PASS (0 == 1) + #else + #define CY_IP_PASS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + + /* Number of external slave ports on System Interconnect */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_SL_NR (-1) + #else + #define CY_IP_SL_NR (-1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_SL_NR (0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + +#else + + #if (CY_PSOC3) + #define CY_SYSTICK_LFCLK_SOURCE (0 != 0) + #else /* PSoC 5LP */ + #define CY_SYSTICK_LFCLK_SOURCE (0 == 0) + #endif /* (CY_PSOC3) */ + +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* The components version defines. Available started from cy_boot 4.20 +* Use the following construction in order to identify cy_boot version: +* (defined(CY_BOOT_VERSION) && CY_BOOT_VERSION >= CY_BOOT_4_20) +*******************************************************************************/ +#define CY_BOOT_4_20 (420u) +#define CY_BOOT_5_0 (500u) +#define CY_BOOT_5_10 (510u) +#define CY_BOOT_5_20 (520u) +#define CY_BOOT_5_30 (530u) +#define CY_BOOT_5_40 (540u) +#define CY_BOOT_5_50 (550u) +#define CY_BOOT_5_60 (560u) +#define CY_BOOT_5_70 (570u) +#define CY_BOOT_VERSION (CY_BOOT_5_70) + + +/******************************************************************************* +* Base Types. Acceptable types from MISRA-C specifying signedness and size. +*******************************************************************************/ +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned long uint32; +typedef signed char int8; +typedef signed short int16; +typedef signed long int32; +typedef float float32; + +#if(!CY_PSOC3) + + typedef double float64; + typedef long long int64; + typedef unsigned long long uint64; + +#endif /* (!CY_PSOC3) */ + +/* Signed or unsigned depending on compiler selection */ +typedef char char8; + + +/******************************************************************************* +* Memory address functions prototypes +*******************************************************************************/ +#if(CY_PSOC3) + + /*************************************************************************** + * Prototypes for absolute memory address functions (cymem.a51) with built-in + * endian conversion. These functions should be called through the + * CY_GET_XTND_REGxx and CY_SET_XTND_REGxx macros. + ***************************************************************************/ + extern uint8 cyread8 (const volatile void far *addr); + extern void cywrite8 (volatile void far *addr, uint8 value); + + extern uint16 cyread16 (const volatile void far *addr); + extern uint16 cyread16_nodpx(const volatile void far *addr); + + extern void cywrite16 (volatile void far *addr, uint16 value); + extern void cywrite16_nodpx(volatile void far *addr, uint16 value); + + extern uint32 cyread24 (const volatile void far *addr); + extern uint32 cyread24_nodpx(const volatile void far *addr); + + extern void cywrite24 (volatile void far *addr, uint32 value); + extern void cywrite24_nodpx(volatile void far *addr, uint32 value); + + extern uint32 cyread32 (const volatile void far *addr); + extern uint32 cyread32_nodpx(const volatile void far *addr); + + extern void cywrite32 (volatile void far *addr, uint32 value); + extern void cywrite32_nodpx(volatile void far *addr, uint32 value); + + + /*************************************************************************** + * Memory access routines from cymem.a51 for the generated device + * configuration code. These functions may be subject to change in future + * revisions of the cy_boot component and they are not available for all + * devices. Most code should use memset or memcpy instead. + ***************************************************************************/ + void cymemzero(void far *addr, uint16 size); + void cyconfigcpy(uint16 size, const void far *src, void far *dest) large; + void cyconfigcpycode(uint16 size, const void code *src, void far *dest); + + #define CYCONFIGCPY_DECLARED (1) + +#else + + /* Prototype for function to set 24-bit register. Located at cyutils.c */ + extern void CySetReg24(uint32 volatile * addr, uint32 value); + + #if(CY_PSOC4) + + extern uint32 CyGetReg24(uint32 const volatile * addr); + + #endif /* (CY_PSOC4) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Memory model definitions. To allow code to be 8051-ARM agnostic. +*******************************************************************************/ +#if(CY_PSOC3) + + #define CYBDATA bdata + #define CYBIT bit + #define CYCODE code + #define CYCOMPACT compact + #define CYDATA data + #define CYFAR far + #define CYIDATA idata + #define CYLARGE large + #define CYPDATA pdata + #define CYREENTRANT reentrant + #define CYSMALL small + #define CYXDATA xdata + #define XDATA xdata + + #define CY_NOINIT + +#else + + #define CYBDATA + #define CYBIT uint8 + #define CYCODE + #define CYCOMPACT + #define CYDATA + #define CYFAR + #define CYIDATA + #define CYLARGE + #define CYPDATA + #define CYREENTRANT + #define CYSMALL + #define CYXDATA + #define XDATA + + #if defined(__ARMCC_VERSION) + + #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init)) + #define CY_NORETURN __attribute__ ((noreturn)) + #define CY_SECTION(name) __attribute__ ((section(name))) + + /* Specifies a minimum alignment (in bytes) for variables of the + * specified type. + */ + #define CY_ALIGN(align) __align(align) + + + /* Attached to an enum, struct, or union type definition, specified that + * the minimum required memory be used to represent the type. + */ + #define CY_PACKED + #define CY_PACKED_ATTR __attribute__ ((packed)) + #define CY_INLINE __inline + #elif defined (__GNUC__) + + #define CY_NOINIT __attribute__ ((section(".noinit"))) + #define CY_NORETURN __attribute__ ((noreturn)) + #define CY_SECTION(name) __attribute__ ((section(name))) + #define CY_ALIGN(align) __attribute__ ((aligned(align))) + #define CY_PACKED + #define CY_PACKED_ATTR __attribute__ ((packed)) + #define CY_INLINE inline + #elif defined (__ICCARM__) + + #define CY_NOINIT __no_init + #define CY_NORETURN __noreturn + #define CY_PACKED __packed + #define CY_PACKED_ATTR + #define CY_INLINE inline + #endif /* (__ARMCC_VERSION) */ + +#endif /* (CY_PSOC3) */ + + +#if(CY_PSOC3) + + /* 8051 naturally returns 8 bit value. */ + typedef unsigned char cystatus; + +#else + + /* ARM naturally returns 32 bit value. */ + typedef unsigned long cystatus; + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Hardware Register Types. +*******************************************************************************/ +typedef volatile uint8 CYXDATA reg8; +typedef volatile uint16 CYXDATA reg16; +typedef volatile uint32 CYXDATA reg32; + + +/******************************************************************************* +* Interrupt Types and Macros +*******************************************************************************/ +#if(CY_PSOC3) + + #define CY_ISR(FuncName) void FuncName (void) interrupt 0 + #define CY_ISR_PROTO(FuncName) void FuncName (void) + typedef void (CYCODE * cyisraddress)(void); + +#else + + #define CY_ISR(FuncName) void FuncName (void) + #define CY_ISR_PROTO(FuncName) void FuncName (void) + typedef void (* cyisraddress)(void); + + #if defined (__ICCARM__) + typedef union { cyisraddress __fun; void * __ptr; } intvec_elem; + #endif /* defined (__ICCARM__) */ + +#endif /* (CY_PSOC3) */ + + +#define CY_M_PI (3.14159265358979323846264338327) + + +/** +* \addtogroup group_register_access +A library of macros provides read and write access to the registers of the device. These macros are used with the +defined values made available in the generated cydevice_trm.h and cyfitter.h files. Access to registers should be made +using these macros and not the functions that are used to implement the macros. This allows for device independent code +generation. + +The PSoC 4 processor architecture use little endian ordering. + +SRAM and Flash storage in all architectures is done using the endianness of the architecture and compilers. However, +the registers in all these chips are laid out in little endian order. These macros allow register accesses to match this +little endian ordering. If you perform operations on multi-byte registers without using these macros, you must consider +the byte ordering of the specific architecture. Examples include usage of DMA to transfer between memory and registers, +as well as function calls that are passed an array of bytes in memory. + +The PSoC 4 requires these accesses to be aligned to the width of the transaction. + +The PSoC 4 requires peripheral register accesses to match the hardware register size. Otherwise, the peripheral might +ignore the transfer and Hard Fault exception will be generated. + +*/ + +/** @} group_register_access */ + + +/** +* \addtogroup group_register_access_macros Register Access +* \ingroup group_register_access +* @{ +*/ + +#if(CY_PSOC3) + /******************************************************************************* + * Macro Name: CY_GET_REG8(addr) + ****************************************************************************//** + * + * Reads the 8-bit value from the specified register. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG8(addr, value) + ****************************************************************************//** + * + * Writes the 8-bit value to the specified register. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + + /******************************************************************************* + * Macro Name: CY_GET_REG16(addr) + ****************************************************************************//** + * + * Reads the 16-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG16(addr) cyread16_nodpx ((const volatile void far *)(const reg16 *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_REG16(addr, value) + ****************************************************************************//** + * + * Writes the 16-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG16(addr, value) cywrite16_nodpx((volatile void far *)(reg16 *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_REG24(addr) + ****************************************************************************//** + * + * Reads the 24-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG24(addr) cyread24_nodpx ((const volatile void far *)(const reg32 *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_REG24(addr, value) + ****************************************************************************//** + * + * Writes the 24-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG24(addr, value) cywrite24_nodpx((volatile void far *)(reg32 *)(addr),value) + + + /******************************************************************************* + * Macro Name: CY_GET_REG32(addr) + ****************************************************************************//** + * + * Reads the 32-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG32(addr) cyread32_nodpx ((const volatile void far *)(const reg32 *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_REG32(addr, value) + ****************************************************************************//** + * + * Writes the 32-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG32(addr, value) cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG8(addr) + ****************************************************************************//** + * + * Reads the 8-bit value from the specified register. + * Identical to \ref CY_GET_REG8 for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG8(addr) cyread8((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG8(addr, value) + ****************************************************************************//** + * + * Writes the 8-bit value to the specified register. + * Identical to \ref CY_SET_REG8 for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG8(addr, value) cywrite8((volatile void far *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG16(addr) + ****************************************************************************//** + * + * Reads the 16-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_GET_REG16 + * for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG16(addr) cyread16((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG16(addr, value) + ****************************************************************************//** + * + * Writes the 16-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_SET_REG16 + * for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG16(addr, value) cywrite16((volatile void far *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG24(addr) + ****************************************************************************//** + * + * Reads the 24-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_GET_REG24 + * for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG24(addr) cyread24((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG24(addr, value) + ****************************************************************************//** + * + * Writes the 24-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_SET_REG24 + * for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG24(addr, value) cywrite24((volatile void far *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG32(addr) + ****************************************************************************//** + * + * Reads the 32-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_GET_REG32 + * for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG32(addr) cyread32((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG32(addr, value) + ****************************************************************************//** + * + * Writes the 32-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_SET_REG32 + * for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG32(addr, value) cywrite32((volatile void far *)(addr), value) + +#else + + #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) + #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + #define CY_GET_REG16(addr) (*((const reg16 *)(addr))) + #define CY_SET_REG16(addr, value) (*((reg16 *)(addr)) = (uint16)(value)) + + + #define CY_SET_REG24(addr, value) CySetReg24((reg32 *) (addr), (value)) + #if(CY_PSOC4) + #define CY_GET_REG24(addr) CyGetReg24((const reg32 *) (addr)) + #else + #define CY_GET_REG24(addr) (*((const reg32 *)(addr)) & 0x00FFFFFFu) + #endif /* (CY_PSOC4) */ + + + #define CY_GET_REG32(addr) (*((const reg32 *)(addr))) + #define CY_SET_REG32(addr, value) (*((reg32 *)(addr)) = (uint32)(value)) + + /* To allow code to be 8051-ARM agnostic. */ + #define CY_GET_XTND_REG8(addr) CY_GET_REG8(addr) + #define CY_SET_XTND_REG8(addr, value) CY_SET_REG8(addr, value) + + #define CY_GET_XTND_REG16(addr) CY_GET_REG16(addr) + #define CY_SET_XTND_REG16(addr, value) CY_SET_REG16(addr, value) + + #define CY_GET_XTND_REG24(addr) CY_GET_REG24(addr) + #define CY_SET_XTND_REG24(addr, value) CY_SET_REG24(addr, value) + + #define CY_GET_XTND_REG32(addr) CY_GET_REG32(addr) + #define CY_SET_XTND_REG32(addr, value) CY_SET_REG32(addr, value) + +#endif /* (CY_PSOC3) */ +/** @} group_register_access_macros */ + + +/** +* \addtogroup group_register_access_bits Bit Manipulation +* \ingroup group_register_access +* @{ +*/ + +#if(CY_PSOC4) + + /******************************************************************************* + * Macro Name: CY_GET_FIELD_MASK(regSize, bitFieldName) + ****************************************************************************//** + * + * Returns the bit field mask for the specified register size and bit field + * name. + * + * \param regSize Size of the register in bits. + * \param bitFieldName Fully qualified name of the bit field. The biFieldName + * is automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * \return Returns the bit mask. + * + *******************************************************************************/ + #define CY_GET_FIELD_MASK(regSize, bitFieldName) \ + ((((uint ## regSize) 0xFFFFFFFFu << ((uint32)(regSize) - bitFieldName ## __SIZE - bitFieldName ## __OFFSET)) >>\ + ((uint32)(regSize) - bitFieldName ## __SIZE)) << bitFieldName ## __OFFSET) + + + /******************************************************************************* + * Macro Name: CY_GET_REG8_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the specified 8-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register will remain uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on 32-bit and 16-bit width registers will generate a + * hard fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName: The fully qualified name of the PSoC 4 device register. + * \param bitFieldName: fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family + * register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, + * otherwise. The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_REG8_FIELD(registerName, bitFieldName) \ + ((CY_GET_REG8((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG8_FIELD(registerName, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value of the specified 8-bit register to the + * required value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on the 32-bit and 16-bit width registers, generates a + * hard fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family + * register TRM. + * + *******************************************************************************/ + #define CY_SET_REG8_FIELD(registerName, bitFieldName, value) \ + CY_SET_REG8((registerName), \ + ((CY_GET_REG8((registerName)) & ~CY_GET_FIELD_MASK(8, bitFieldName)) | \ + (((uint8)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(8, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_CLEAR_REG8_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Clears the specified bit field of the specified 8-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a + * hard fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the + * possible values the field can take, please, refer to a respective PSoC + * family register TRM. + * + *******************************************************************************/ + #define CY_CLEAR_REG8_FIELD(registerName, bitFieldName) \ + (CY_SET_REG8((registerName), (CY_GET_REG8((registerName)) & ~CY_GET_FIELD_MASK(8, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_GET_REG16_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the specified 16-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a + * hardfault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the + * possible values the field can take, please, refer to a respective PSoC + * family register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, + * otherwise. The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_REG16_FIELD(registerName, bitFieldName) \ + ((CY_GET_REG16((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG16_FIELD(registerName, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value of the specified 16-bit register to the + * required value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a hard + * fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerNam The fully qualified name of the PSoC 4 device register. + * \param bitFieldName: fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family + * register TRM. + * + *******************************************************************************/ + #define CY_SET_REG16_FIELD(registerName, bitFieldName, value) \ + CY_SET_REG16((registerName), \ + ((CY_GET_REG16((registerName)) & ~CY_GET_FIELD_MASK(16, bitFieldName)) | \ + (((uint16)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(16, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_CLEAR_REG16_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Clears the specified bit field of the specified 16-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a hard + * fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName: The fully qualified name of the PSoC 4 device register. + * \param bitFieldName: fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family register + * TRM. + * + *******************************************************************************/ + #define CY_CLEAR_REG16_FIELD(registerName, bitFieldName)\ + (CY_SET_REG16((registerName), (CY_GET_REG16((registerName)) & ~CY_GET_FIELD_MASK(16, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_GET_REG32_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the specified 32-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 16-bit and 8-bit width registers generates a hard + * fault exception. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName The Fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * + * For fully qualified names of the register and bit fields, please, refer to + * a respective PSoC family register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, otherwise. + * The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_REG32_FIELD(registerName, bitFieldName) \ + ((CY_GET_REG32((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFFFFFFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG32_FIELD(registerName, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value of the specified 32-bit register to the + * required value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 16-bit and 8-bit width registers generates a hard + * fault exception. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family register + * TRM. + * + *******************************************************************************/ + #define CY_SET_REG32_FIELD(registerName, bitFieldName, value) \ + CY_SET_REG32((registerName), \ + ((CY_GET_REG32((registerName)) & ~CY_GET_FIELD_MASK(32, bitFieldName)) | \ + (((uint32)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(32, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_CLEAR_REG32_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Clears the specified bit field of the specified 32-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 16-bit and 8-bit width registers generates a hard + * fault exception. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family register + * TRM. + * + *******************************************************************************/ + #define CY_CLEAR_REG32_FIELD(registerName, bitFieldName) \ + (CY_SET_REG32((registerName), (CY_GET_REG32((registerName)) & ~CY_GET_FIELD_MASK(32, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_GET_FIELD(regValue, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the given 32-bit value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * This macro has to be used in conjunction with \ref CY_GET_REG32 for atomic + * reads. + * + * \param regValue The value as read by \ref CY_GET_REG32. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * + * For fully qualified names of the bit field and the possible values the field + * can take, please, refer to a respective PSoC family register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, + * otherwise. The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_FIELD(regValue, bitFieldName) \ + (((regValue) >> bitFieldName ## __OFFSET) & (~(0xFFFFFFFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_FIELD(regValue, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value within a given 32-bit value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * This macro has to be used in conjunction with \ref CY_GET_REG32 for atomic + * reads and \ref CY_SET_REG32 for atomic writes. + * + * \param regValue The value as read by \ref CY_GET_REG32. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the bit field and the possible values the field + * can take, please, refer to the respective PSoC family register TRM. + * + *******************************************************************************/ + #define CY_SET_FIELD(regValue, bitFieldName, value) \ + ((regValue) = \ + ((((uint32)(value) & (~(0xFFFFFFu << bitFieldName ## __SIZE))) << bitFieldName ## __OFFSET)) | \ + ((uint32)(regValue) & (((~(0xFFu << bitFieldName ## __SIZE))) << bitFieldName ## __OFFSET))) + +#endif /* (CY_PSOC4) */ + +/** @} group_register_access_bits */ + + +/******************************************************************************* +* Data manipulation defines +*******************************************************************************/ + +/* Get 8 bits of 16 bit value. */ +#define LO8(x) ((uint8) ((x) & 0xFFu)) +#define HI8(x) ((uint8) ((uint16)(x) >> 8)) + +/* Get 16 bits of 32 bit value. */ +#define LO16(x) ((uint16) ((x) & 0xFFFFu)) +#define HI16(x) ((uint16) ((uint32)(x) >> 16)) + +/* Swap the byte ordering of 32 bit value */ +#define CYSWAP_ENDIAN32(x) \ + ((uint32)((((x) >> 24) & 0x000000FFu) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24))) + +/* Swap the byte ordering of 16 bit value */ +#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | (((x) >> 8) & 0x00FFu))) + + +/******************************************************************************* +* Defines the standard return values used in PSoC content. A function is +* not limited to these return values but can use them when returning standard +* error values. Return values can be overloaded if documented in the function +* header. On the 8051 a function can use a larger return type but still use the +* defined return codes. +* +* Zero is successful, all other values indicate some form of failure. 1 - 0x7F - +* standard defined values; 0x80 - ... - user or content defined values. +*******************************************************************************/ +#define CYRET_SUCCESS (0x00u) /* Successful */ +#define CYRET_BAD_PARAM (0x01u) /* One or more invalid parameters */ +#define CYRET_INVALID_OBJECT (0x02u) /* Invalid object specified */ +#define CYRET_MEMORY (0x03u) /* Memory related failure */ +#define CYRET_LOCKED (0x04u) /* Resource lock failure */ +#define CYRET_EMPTY (0x05u) /* No more objects available */ +#define CYRET_BAD_DATA (0x06u) /* Bad data received (CRC or other error check) */ +#define CYRET_STARTED (0x07u) /* Operation started, but not necessarily completed yet */ +#define CYRET_FINISHED (0x08u) /* Operation completed */ +#define CYRET_CANCELED (0x09u) /* Operation canceled */ +#define CYRET_TIMEOUT (0x10u) /* Operation timed out */ +#define CYRET_INVALID_STATE (0x11u) /* Operation not setup or is in an improper state */ +#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFu) /* Unknown failure */ + + +/******************************************************************************* +* Intrinsic Defines: Processor NOP instruction +*******************************************************************************/ +#if(CY_PSOC3) + + #define CY_NOP _nop_() + +#else + + #if defined(__ARMCC_VERSION) + + /* RealView */ + #define CY_NOP __nop() + + #else + + /* GCC */ + #define CY_NOP __asm("NOP\n") + + #endif /* defined(__ARMCC_VERSION) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting from cy_boot 5.10 +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define CY_IP_S8FS CY_IP_FS + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting from cy_boot 3.10 +*******************************************************************************/ +#define CY_UDB_V0 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A) +#define CY_UDB_V1 (!CY_UDB_V0) +#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) +#ifdef CYDEV_CHIP_MEMBER_4D + #define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D) + #define CY_PSOC4SF (CY_PSOC4D) +#else + #define CY_PSOC4D (0u != 0u) + #define CY_PSOC4SF (CY_PSOC4D) +#endif /* CYDEV_CHIP_MEMBER_4D */ +#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A) +#ifdef CYDEV_CHIP_MEMBER_5B + #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B) +#else + #define CY_PSOC5LP (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_5B */ + +#if (!CY_PSOC4) + + /* Device is PSoC 3 and the revision is ES2 or earlier */ + #define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ + (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2)) + + /* Device is PSoC 3 and the revision is ES3 or later */ + #define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ + (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3)) + + /* Device is PSoC 5 and the revision is ES1 or earlier */ + #define CY_PSOC5_ES1 (CY_PSOC5A && \ + (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1)) + + /* Device is PSoC 5 and the revision is ES2 or later */ + #define CY_PSOC5_ES2 (CY_PSOC5A && \ + (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1)) + +#endif /* (!CY_PSOC4) */ + +#endif /* CY_BOOT_CYTYPES_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/armcc/CyBootAsmRv.s b/source/hic_hal/cypress/psoc5lp/armcc/CyBootAsmRv.s new file mode 100644 index 0000000000..8fe93b80a7 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/armcc/CyBootAsmRv.s @@ -0,0 +1,171 @@ +;------------------------------------------------------------------------------- +; FILENAME: CyBootAsmRv.s +; Version 5.70 +; +; DESCRIPTION: +; Assembly routines for RealView. +; +;------------------------------------------------------------------------------- +; Copyright (2019) Cypress Semiconductor Corporation +; or a subsidiary of Cypress Semiconductor Corporation. +; +; Licensed under the Apache License, Version 2.0 (the "License"); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +;------------------------------------------------------------------------------- + + AREA |.text|,CODE,ALIGN=3 + THUMB + EXTERN Reset + + GET cyfitterrv.inc + +;------------------------------------------------------------------------------- +; Function Name: CyDelayCycles +;------------------------------------------------------------------------------- +; +; Summary: +; Delays for the specified number of cycles. +; +; Parameters: +; uint32 cycles: number of cycles to delay. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyDelayCycles(uint32 cycles) + ALIGN 8 +CyDelayCycles FUNCTION + EXPORT CyDelayCycles + IF CYDEV_INSTRUCT_CACHE_ENABLED == 1 + ; cycles bytes + ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4 + LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags + BEQ CyDelayCycles_done ; 2 2 Skip if 0 + NOP ; 1 2 Loop alignment padding +CyDelayCycles_loop + SUBS r0, r0, #1 ; 1 2 + MOV r0, r0 ; 1 2 Pad loop to power of two cycles + BNE CyDelayCycles_loop ; 2 2 + NOP ; 1 2 Loop alignment padding +CyDelayCycles_done + BX lr ; 3 2 + + ELSE + + CMP r0, #20 ; 1 2 If delay is short - jump to cycle + BLS CyDelayCycles_short ; 1 2 + PUSH {r1} ; 2 2 PUSH r1 to stack + MOVS r1, #1 ; 1 2 + + SUBS r0, r0, #20 ; 1 2 Subtract overhead + LDR r1,=CYREG_CACHE_CC_CTL; 2 2 Load flash wait cycles value + LDRB r1, [r1, #0] ; 2 2 + ANDS r1, #0xC0 ; 1 2 + + LSRS r1, r1, #6 ; 1 2 + PUSH {r2} ; 1 2 PUSH r2 to stack + LDR r2, =cy_flash_cycles ; 2 2 + LDRB r1, [r2, r1] ; 2 2 + + POP {r2} ; 2 2 POP r2 from stack + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + +CyDelayCycles_loop + SBCS r0, r0, r1 ; 1 2 + BPL CyDelayCycles_loop ; 3 2 + NOP ; 1 2 Loop alignment padding + NOP ; 1 2 Loop alignment padding + + POP {r1} ; 2 2 POP r1 from stack +CyDelayCycles_done + BX lr ; 3 2 + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + +CyDelayCycles_short + SBCS r0, r0, #4 ; 1 2 + BPL CyDelayCycles_short ; 3 2 + BX lr ; 3 2 + +cy_flash_cycles +byte_1 DCB 0x0B +byte_2 DCB 0x05 +byte_3 DCB 0x07 +byte_4 DCB 0x09 + + ENDIF + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: CyEnterCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyEnterCriticalSection disables interrupts and returns a value indicating +; whether interrupts were previously enabled (the actual value depends on +; whether the device is PSoC 3 or PSoC 5). +; +; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +; with interrupts still enabled. The test and set of the interrupt bits is not +; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a +; corrupting processor state, it must be the policy that all interrupt routines +; restore the interrupt enable bits as they were found on entry. +; +; Parameters: +; None +; +; Return: +; uint8 +; Returns 0 if interrupts were previously enabled or 1 if interrupts +; were previously disabled. +; +;------------------------------------------------------------------------------- +; uint8 CyEnterCriticalSection(void) +CyEnterCriticalSection FUNCTION + EXPORT CyEnterCriticalSection + MRS r0, PRIMASK ; Save and return interrupt state + CPSID I ; Disable interrupts + BX lr + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: CyExitCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyExitCriticalSection re-enables interrupts if they were enabled before +; CyEnterCriticalSection was called. The argument should be the value returned +; from CyEnterCriticalSection. +; +; Parameters: +; uint8 savedIntrStatus: +; Saved interrupt status returned by the CyEnterCriticalSection function. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyExitCriticalSection(uint8 savedIntrStatus) +CyExitCriticalSection FUNCTION + EXPORT CyExitCriticalSection + MSR PRIMASK, r0 ; Restore interrupt state + BX lr + ENDFUNC + + END + +; [] END OF FILE diff --git a/source/hic_hal/cypress/psoc5lp/armcc/cydevicerv.inc b/source/hic_hal/cypress/psoc5lp/armcc/cydevicerv.inc new file mode 100644 index 0000000000..4e5d264615 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/armcc/cydevicerv.inc @@ -0,0 +1,16046 @@ +; +; File Name: cydevicerv.inc +; Description: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright (2019) Cypress Semiconductor Corporation +; or a subsidiary of Cypress Semiconductor Corporation. +; +; Licensed under the Apache License, Version 2.0 (the "License"); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:CYDEV_FLASH_BASE +CYDEV_FLASH_BASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_SIZE +CYDEV_FLASH_SIZE EQU 0x00040000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_DATA_MBASE +CYDEV_FLASH_DATA_MBASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_DATA_MSIZE +CYDEV_FLASH_DATA_MSIZE EQU 0x00040000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_BASE +CYDEV_SRAM_BASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_SIZE +CYDEV_SRAM_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE64K_MBASE +CYDEV_SRAM_CODE64K_MBASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE64K_MSIZE +CYDEV_SRAM_CODE64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE32K_MBASE +CYDEV_SRAM_CODE32K_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE32K_MSIZE +CYDEV_SRAM_CODE32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE16K_MBASE +CYDEV_SRAM_CODE16K_MBASE EQU 0x1fffe000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE16K_MSIZE +CYDEV_SRAM_CODE16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE_MBASE +CYDEV_SRAM_CODE_MBASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE_MSIZE +CYDEV_SRAM_CODE_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA_MBASE +CYDEV_SRAM_DATA_MBASE EQU 0x20000000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA_MSIZE +CYDEV_SRAM_DATA_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA16K_MBASE +CYDEV_SRAM_DATA16K_MBASE EQU 0x20001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA16K_MSIZE +CYDEV_SRAM_DATA16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA32K_MBASE +CYDEV_SRAM_DATA32K_MBASE EQU 0x20002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA32K_MSIZE +CYDEV_SRAM_DATA32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA64K_MBASE +CYDEV_SRAM_DATA64K_MBASE EQU 0x20004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA64K_MSIZE +CYDEV_SRAM_DATA64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_BASE +CYDEV_DMA_BASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SIZE +CYDEV_DMA_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM64K_MBASE +CYDEV_DMA_SRAM64K_MBASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM64K_MSIZE +CYDEV_DMA_SRAM64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM32K_MBASE +CYDEV_DMA_SRAM32K_MBASE EQU 0x2000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM32K_MSIZE +CYDEV_DMA_SRAM32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM16K_MBASE +CYDEV_DMA_SRAM16K_MBASE EQU 0x2000e000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM16K_MSIZE +CYDEV_DMA_SRAM16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM_MBASE +CYDEV_DMA_SRAM_MBASE EQU 0x2000f000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM_MSIZE +CYDEV_DMA_SRAM_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BASE +CYDEV_CLKDIST_BASE EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_SIZE +CYDEV_CLKDIST_SIZE EQU 0x00000110 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_CR +CYDEV_CLKDIST_CR EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_LD +CYDEV_CLKDIST_LD EQU 0x40004001 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_WRK0 +CYDEV_CLKDIST_WRK0 EQU 0x40004002 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_WRK1 +CYDEV_CLKDIST_WRK1 EQU 0x40004003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_MSTR0 +CYDEV_CLKDIST_MSTR0 EQU 0x40004004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_MSTR1 +CYDEV_CLKDIST_MSTR1 EQU 0x40004005 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BCFG0 +CYDEV_CLKDIST_BCFG0 EQU 0x40004006 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BCFG1 +CYDEV_CLKDIST_BCFG1 EQU 0x40004007 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BCFG2 +CYDEV_CLKDIST_BCFG2 EQU 0x40004008 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_UCFG +CYDEV_CLKDIST_UCFG EQU 0x40004009 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DLY0 +CYDEV_CLKDIST_DLY0 EQU 0x4000400a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DLY1 +CYDEV_CLKDIST_DLY1 EQU 0x4000400b + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DMASK +CYDEV_CLKDIST_DMASK EQU 0x40004010 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_AMASK +CYDEV_CLKDIST_AMASK EQU 0x40004014 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_BASE +CYDEV_CLKDIST_DCFG0_BASE EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_SIZE +CYDEV_CLKDIST_DCFG0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG0 +CYDEV_CLKDIST_DCFG0_CFG0 EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG1 +CYDEV_CLKDIST_DCFG0_CFG1 EQU 0x40004081 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG2 +CYDEV_CLKDIST_DCFG0_CFG2 EQU 0x40004082 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_BASE +CYDEV_CLKDIST_DCFG1_BASE EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_SIZE +CYDEV_CLKDIST_DCFG1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG0 +CYDEV_CLKDIST_DCFG1_CFG0 EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG1 +CYDEV_CLKDIST_DCFG1_CFG1 EQU 0x40004085 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG2 +CYDEV_CLKDIST_DCFG1_CFG2 EQU 0x40004086 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_BASE +CYDEV_CLKDIST_DCFG2_BASE EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_SIZE +CYDEV_CLKDIST_DCFG2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG0 +CYDEV_CLKDIST_DCFG2_CFG0 EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG1 +CYDEV_CLKDIST_DCFG2_CFG1 EQU 0x40004089 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG2 +CYDEV_CLKDIST_DCFG2_CFG2 EQU 0x4000408a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_BASE +CYDEV_CLKDIST_DCFG3_BASE EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_SIZE +CYDEV_CLKDIST_DCFG3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG0 +CYDEV_CLKDIST_DCFG3_CFG0 EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG1 +CYDEV_CLKDIST_DCFG3_CFG1 EQU 0x4000408d + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG2 +CYDEV_CLKDIST_DCFG3_CFG2 EQU 0x4000408e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_BASE +CYDEV_CLKDIST_DCFG4_BASE EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_SIZE +CYDEV_CLKDIST_DCFG4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG0 +CYDEV_CLKDIST_DCFG4_CFG0 EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG1 +CYDEV_CLKDIST_DCFG4_CFG1 EQU 0x40004091 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG2 +CYDEV_CLKDIST_DCFG4_CFG2 EQU 0x40004092 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_BASE +CYDEV_CLKDIST_DCFG5_BASE EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_SIZE +CYDEV_CLKDIST_DCFG5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG0 +CYDEV_CLKDIST_DCFG5_CFG0 EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG1 +CYDEV_CLKDIST_DCFG5_CFG1 EQU 0x40004095 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG2 +CYDEV_CLKDIST_DCFG5_CFG2 EQU 0x40004096 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_BASE +CYDEV_CLKDIST_DCFG6_BASE EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_SIZE +CYDEV_CLKDIST_DCFG6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG0 +CYDEV_CLKDIST_DCFG6_CFG0 EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG1 +CYDEV_CLKDIST_DCFG6_CFG1 EQU 0x40004099 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG2 +CYDEV_CLKDIST_DCFG6_CFG2 EQU 0x4000409a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_BASE +CYDEV_CLKDIST_DCFG7_BASE EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_SIZE +CYDEV_CLKDIST_DCFG7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG0 +CYDEV_CLKDIST_DCFG7_CFG0 EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG1 +CYDEV_CLKDIST_DCFG7_CFG1 EQU 0x4000409d + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG2 +CYDEV_CLKDIST_DCFG7_CFG2 EQU 0x4000409e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_BASE +CYDEV_CLKDIST_ACFG0_BASE EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_SIZE +CYDEV_CLKDIST_ACFG0_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG0 +CYDEV_CLKDIST_ACFG0_CFG0 EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG1 +CYDEV_CLKDIST_ACFG0_CFG1 EQU 0x40004101 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG2 +CYDEV_CLKDIST_ACFG0_CFG2 EQU 0x40004102 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG3 +CYDEV_CLKDIST_ACFG0_CFG3 EQU 0x40004103 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_BASE +CYDEV_CLKDIST_ACFG1_BASE EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_SIZE +CYDEV_CLKDIST_ACFG1_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG0 +CYDEV_CLKDIST_ACFG1_CFG0 EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG1 +CYDEV_CLKDIST_ACFG1_CFG1 EQU 0x40004105 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG2 +CYDEV_CLKDIST_ACFG1_CFG2 EQU 0x40004106 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG3 +CYDEV_CLKDIST_ACFG1_CFG3 EQU 0x40004107 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_BASE +CYDEV_CLKDIST_ACFG2_BASE EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_SIZE +CYDEV_CLKDIST_ACFG2_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG0 +CYDEV_CLKDIST_ACFG2_CFG0 EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG1 +CYDEV_CLKDIST_ACFG2_CFG1 EQU 0x40004109 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG2 +CYDEV_CLKDIST_ACFG2_CFG2 EQU 0x4000410a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG3 +CYDEV_CLKDIST_ACFG2_CFG3 EQU 0x4000410b + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_BASE +CYDEV_CLKDIST_ACFG3_BASE EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_SIZE +CYDEV_CLKDIST_ACFG3_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG0 +CYDEV_CLKDIST_ACFG3_CFG0 EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG1 +CYDEV_CLKDIST_ACFG3_CFG1 EQU 0x4000410d + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG2 +CYDEV_CLKDIST_ACFG3_CFG2 EQU 0x4000410e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG3 +CYDEV_CLKDIST_ACFG3_CFG3 EQU 0x4000410f + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_BASE +CYDEV_FASTCLK_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_SIZE +CYDEV_FASTCLK_SIZE EQU 0x00000026 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_BASE +CYDEV_FASTCLK_IMO_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_SIZE +CYDEV_FASTCLK_IMO_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_CR +CYDEV_FASTCLK_IMO_CR EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_BASE +CYDEV_FASTCLK_XMHZ_BASE EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_SIZE +CYDEV_FASTCLK_XMHZ_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CSR +CYDEV_FASTCLK_XMHZ_CSR EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CFG0 +CYDEV_FASTCLK_XMHZ_CFG0 EQU 0x40004212 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CFG1 +CYDEV_FASTCLK_XMHZ_CFG1 EQU 0x40004213 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_BASE +CYDEV_FASTCLK_PLL_BASE EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SIZE +CYDEV_FASTCLK_PLL_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_CFG0 +CYDEV_FASTCLK_PLL_CFG0 EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_CFG1 +CYDEV_FASTCLK_PLL_CFG1 EQU 0x40004221 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_P +CYDEV_FASTCLK_PLL_P EQU 0x40004222 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_Q +CYDEV_FASTCLK_PLL_Q EQU 0x40004223 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SR +CYDEV_FASTCLK_PLL_SR EQU 0x40004225 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_BASE +CYDEV_SLOWCLK_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_SIZE +CYDEV_SLOWCLK_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_BASE +CYDEV_SLOWCLK_ILO_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_SIZE +CYDEV_SLOWCLK_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_CR0 +CYDEV_SLOWCLK_ILO_CR0 EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_CR1 +CYDEV_SLOWCLK_ILO_CR1 EQU 0x40004301 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_BASE +CYDEV_SLOWCLK_X32_BASE EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_SIZE +CYDEV_SLOWCLK_X32_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_CR +CYDEV_SLOWCLK_X32_CR EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_CFG +CYDEV_SLOWCLK_X32_CFG EQU 0x40004309 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_TST +CYDEV_SLOWCLK_X32_TST EQU 0x4000430a + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_BASE +CYDEV_BOOST_BASE EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SIZE +CYDEV_BOOST_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR0 +CYDEV_BOOST_CR0 EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR1 +CYDEV_BOOST_CR1 EQU 0x40004321 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR2 +CYDEV_BOOST_CR2 EQU 0x40004322 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR3 +CYDEV_BOOST_CR3 EQU 0x40004323 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SR +CYDEV_BOOST_SR EQU 0x40004324 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR4 +CYDEV_BOOST_CR4 EQU 0x40004325 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SR2 +CYDEV_BOOST_SR2 EQU 0x40004326 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_BASE +CYDEV_PWRSYS_BASE EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_SIZE +CYDEV_PWRSYS_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_CR0 +CYDEV_PWRSYS_CR0 EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_CR1 +CYDEV_PWRSYS_CR1 EQU 0x40004331 + ENDIF + IF :LNOT::DEF:CYDEV_PM_BASE +CYDEV_PM_BASE EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYDEV_PM_SIZE +CYDEV_PM_SIZE EQU 0x00000057 + ENDIF + IF :LNOT::DEF:CYDEV_PM_TW_CFG0 +CYDEV_PM_TW_CFG0 EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYDEV_PM_TW_CFG1 +CYDEV_PM_TW_CFG1 EQU 0x40004381 + ENDIF + IF :LNOT::DEF:CYDEV_PM_TW_CFG2 +CYDEV_PM_TW_CFG2 EQU 0x40004382 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WDT_CFG +CYDEV_PM_WDT_CFG EQU 0x40004383 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WDT_CR +CYDEV_PM_WDT_CR EQU 0x40004384 + ENDIF + IF :LNOT::DEF:CYDEV_PM_INT_SR +CYDEV_PM_INT_SR EQU 0x40004390 + ENDIF + IF :LNOT::DEF:CYDEV_PM_MODE_CFG0 +CYDEV_PM_MODE_CFG0 EQU 0x40004391 + ENDIF + IF :LNOT::DEF:CYDEV_PM_MODE_CFG1 +CYDEV_PM_MODE_CFG1 EQU 0x40004392 + ENDIF + IF :LNOT::DEF:CYDEV_PM_MODE_CSR +CYDEV_PM_MODE_CSR EQU 0x40004393 + ENDIF + IF :LNOT::DEF:CYDEV_PM_USB_CR0 +CYDEV_PM_USB_CR0 EQU 0x40004394 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG0 +CYDEV_PM_WAKEUP_CFG0 EQU 0x40004398 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG1 +CYDEV_PM_WAKEUP_CFG1 EQU 0x40004399 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG2 +CYDEV_PM_WAKEUP_CFG2 EQU 0x4000439a + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_BASE +CYDEV_PM_ACT_BASE EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_SIZE +CYDEV_PM_ACT_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG0 +CYDEV_PM_ACT_CFG0 EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG1 +CYDEV_PM_ACT_CFG1 EQU 0x400043a1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG2 +CYDEV_PM_ACT_CFG2 EQU 0x400043a2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG3 +CYDEV_PM_ACT_CFG3 EQU 0x400043a3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG4 +CYDEV_PM_ACT_CFG4 EQU 0x400043a4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG5 +CYDEV_PM_ACT_CFG5 EQU 0x400043a5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG6 +CYDEV_PM_ACT_CFG6 EQU 0x400043a6 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG7 +CYDEV_PM_ACT_CFG7 EQU 0x400043a7 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG8 +CYDEV_PM_ACT_CFG8 EQU 0x400043a8 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG9 +CYDEV_PM_ACT_CFG9 EQU 0x400043a9 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG10 +CYDEV_PM_ACT_CFG10 EQU 0x400043aa + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG11 +CYDEV_PM_ACT_CFG11 EQU 0x400043ab + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG12 +CYDEV_PM_ACT_CFG12 EQU 0x400043ac + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG13 +CYDEV_PM_ACT_CFG13 EQU 0x400043ad + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_BASE +CYDEV_PM_STBY_BASE EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_SIZE +CYDEV_PM_STBY_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG0 +CYDEV_PM_STBY_CFG0 EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG1 +CYDEV_PM_STBY_CFG1 EQU 0x400043b1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG2 +CYDEV_PM_STBY_CFG2 EQU 0x400043b2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG3 +CYDEV_PM_STBY_CFG3 EQU 0x400043b3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG4 +CYDEV_PM_STBY_CFG4 EQU 0x400043b4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG5 +CYDEV_PM_STBY_CFG5 EQU 0x400043b5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG6 +CYDEV_PM_STBY_CFG6 EQU 0x400043b6 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG7 +CYDEV_PM_STBY_CFG7 EQU 0x400043b7 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG8 +CYDEV_PM_STBY_CFG8 EQU 0x400043b8 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG9 +CYDEV_PM_STBY_CFG9 EQU 0x400043b9 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG10 +CYDEV_PM_STBY_CFG10 EQU 0x400043ba + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG11 +CYDEV_PM_STBY_CFG11 EQU 0x400043bb + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG12 +CYDEV_PM_STBY_CFG12 EQU 0x400043bc + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG13 +CYDEV_PM_STBY_CFG13 EQU 0x400043bd + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_BASE +CYDEV_PM_AVAIL_BASE EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SIZE +CYDEV_PM_AVAIL_SIZE EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR0 +CYDEV_PM_AVAIL_CR0 EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR1 +CYDEV_PM_AVAIL_CR1 EQU 0x400043c1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR2 +CYDEV_PM_AVAIL_CR2 EQU 0x400043c2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR3 +CYDEV_PM_AVAIL_CR3 EQU 0x400043c3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR4 +CYDEV_PM_AVAIL_CR4 EQU 0x400043c4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR5 +CYDEV_PM_AVAIL_CR5 EQU 0x400043c5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR6 +CYDEV_PM_AVAIL_CR6 EQU 0x400043c6 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR0 +CYDEV_PM_AVAIL_SR0 EQU 0x400043d0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR1 +CYDEV_PM_AVAIL_SR1 EQU 0x400043d1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR2 +CYDEV_PM_AVAIL_SR2 EQU 0x400043d2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR3 +CYDEV_PM_AVAIL_SR3 EQU 0x400043d3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR4 +CYDEV_PM_AVAIL_SR4 EQU 0x400043d4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR5 +CYDEV_PM_AVAIL_SR5 EQU 0x400043d5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR6 +CYDEV_PM_AVAIL_SR6 EQU 0x400043d6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_BASE +CYDEV_PICU_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SIZE +CYDEV_PICU_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_BASE +CYDEV_PICU_INTTYPE_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_SIZE +CYDEV_PICU_INTTYPE_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_BASE +CYDEV_PICU_INTTYPE_PICU0_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_SIZE +CYDEV_PICU_INTTYPE_PICU0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 EQU 0x40004501 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 EQU 0x40004502 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 EQU 0x40004503 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 EQU 0x40004504 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 EQU 0x40004505 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 EQU 0x40004506 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 EQU 0x40004507 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_BASE +CYDEV_PICU_INTTYPE_PICU1_BASE EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_SIZE +CYDEV_PICU_INTTYPE_PICU1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 EQU 0x40004509 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 EQU 0x4000450a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 EQU 0x4000450b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 EQU 0x4000450c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 EQU 0x4000450d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 EQU 0x4000450e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 EQU 0x4000450f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_BASE +CYDEV_PICU_INTTYPE_PICU2_BASE EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_SIZE +CYDEV_PICU_INTTYPE_PICU2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 EQU 0x40004511 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 EQU 0x40004512 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 EQU 0x40004513 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 EQU 0x40004514 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 EQU 0x40004515 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 EQU 0x40004516 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 EQU 0x40004517 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_BASE +CYDEV_PICU_INTTYPE_PICU3_BASE EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_SIZE +CYDEV_PICU_INTTYPE_PICU3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 EQU 0x40004519 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 EQU 0x4000451a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 EQU 0x4000451b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 EQU 0x4000451c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 EQU 0x4000451d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 EQU 0x4000451e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 EQU 0x4000451f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_BASE +CYDEV_PICU_INTTYPE_PICU4_BASE EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_SIZE +CYDEV_PICU_INTTYPE_PICU4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 EQU 0x40004521 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 EQU 0x40004522 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 EQU 0x40004523 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 EQU 0x40004524 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 EQU 0x40004525 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 EQU 0x40004526 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 EQU 0x40004527 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_BASE +CYDEV_PICU_INTTYPE_PICU5_BASE EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_SIZE +CYDEV_PICU_INTTYPE_PICU5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 EQU 0x40004529 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 EQU 0x4000452a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 EQU 0x4000452b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 EQU 0x4000452c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 EQU 0x4000452d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 EQU 0x4000452e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 EQU 0x4000452f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_BASE +CYDEV_PICU_INTTYPE_PICU6_BASE EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_SIZE +CYDEV_PICU_INTTYPE_PICU6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 EQU 0x40004531 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 EQU 0x40004532 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 EQU 0x40004533 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 EQU 0x40004534 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 EQU 0x40004535 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 EQU 0x40004536 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 EQU 0x40004537 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_BASE +CYDEV_PICU_INTTYPE_PICU12_BASE EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_SIZE +CYDEV_PICU_INTTYPE_PICU12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 EQU 0x40004561 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 EQU 0x40004562 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 EQU 0x40004563 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 EQU 0x40004564 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 EQU 0x40004565 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 EQU 0x40004566 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 EQU 0x40004567 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_BASE +CYDEV_PICU_INTTYPE_PICU15_BASE EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_SIZE +CYDEV_PICU_INTTYPE_PICU15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 EQU 0x40004579 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 EQU 0x4000457a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 EQU 0x4000457b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 EQU 0x4000457c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 EQU 0x4000457d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 EQU 0x4000457e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 EQU 0x4000457f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_BASE +CYDEV_PICU_STAT_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_SIZE +CYDEV_PICU_STAT_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_BASE +CYDEV_PICU_STAT_PICU0_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_SIZE +CYDEV_PICU_STAT_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_INTSTAT +CYDEV_PICU_STAT_PICU0_INTSTAT EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_BASE +CYDEV_PICU_STAT_PICU1_BASE EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_SIZE +CYDEV_PICU_STAT_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_INTSTAT +CYDEV_PICU_STAT_PICU1_INTSTAT EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_BASE +CYDEV_PICU_STAT_PICU2_BASE EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_SIZE +CYDEV_PICU_STAT_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_INTSTAT +CYDEV_PICU_STAT_PICU2_INTSTAT EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_BASE +CYDEV_PICU_STAT_PICU3_BASE EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_SIZE +CYDEV_PICU_STAT_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_INTSTAT +CYDEV_PICU_STAT_PICU3_INTSTAT EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_BASE +CYDEV_PICU_STAT_PICU4_BASE EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_SIZE +CYDEV_PICU_STAT_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_INTSTAT +CYDEV_PICU_STAT_PICU4_INTSTAT EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_BASE +CYDEV_PICU_STAT_PICU5_BASE EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_SIZE +CYDEV_PICU_STAT_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_INTSTAT +CYDEV_PICU_STAT_PICU5_INTSTAT EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_BASE +CYDEV_PICU_STAT_PICU6_BASE EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_SIZE +CYDEV_PICU_STAT_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_INTSTAT +CYDEV_PICU_STAT_PICU6_INTSTAT EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_BASE +CYDEV_PICU_STAT_PICU12_BASE EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_SIZE +CYDEV_PICU_STAT_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_INTSTAT +CYDEV_PICU_STAT_PICU12_INTSTAT EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_BASE +CYDEV_PICU_STAT_PICU15_BASE EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_SIZE +CYDEV_PICU_STAT_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_INTSTAT +CYDEV_PICU_STAT_PICU15_INTSTAT EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_BASE +CYDEV_PICU_SNAP_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_SIZE +CYDEV_PICU_SNAP_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_BASE +CYDEV_PICU_SNAP_PICU0_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SIZE +CYDEV_PICU_SNAP_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SNAP +CYDEV_PICU_SNAP_PICU0_SNAP EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_BASE +CYDEV_PICU_SNAP_PICU1_BASE EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SIZE +CYDEV_PICU_SNAP_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SNAP +CYDEV_PICU_SNAP_PICU1_SNAP EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_BASE +CYDEV_PICU_SNAP_PICU2_BASE EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SIZE +CYDEV_PICU_SNAP_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SNAP +CYDEV_PICU_SNAP_PICU2_SNAP EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_BASE +CYDEV_PICU_SNAP_PICU3_BASE EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SIZE +CYDEV_PICU_SNAP_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SNAP +CYDEV_PICU_SNAP_PICU3_SNAP EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_BASE +CYDEV_PICU_SNAP_PICU4_BASE EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SIZE +CYDEV_PICU_SNAP_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SNAP +CYDEV_PICU_SNAP_PICU4_SNAP EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_BASE +CYDEV_PICU_SNAP_PICU5_BASE EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SIZE +CYDEV_PICU_SNAP_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SNAP +CYDEV_PICU_SNAP_PICU5_SNAP EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_BASE +CYDEV_PICU_SNAP_PICU6_BASE EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SIZE +CYDEV_PICU_SNAP_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SNAP +CYDEV_PICU_SNAP_PICU6_SNAP EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_BASE +CYDEV_PICU_SNAP_PICU12_BASE EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SIZE +CYDEV_PICU_SNAP_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SNAP +CYDEV_PICU_SNAP_PICU12_SNAP EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_BASE +CYDEV_PICU_SNAP_PICU_15_BASE EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SIZE +CYDEV_PICU_SNAP_PICU_15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SNAP_15 +CYDEV_PICU_SNAP_PICU_15_SNAP_15 EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_BASE +CYDEV_PICU_DISABLE_COR_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_SIZE +CYDEV_PICU_DISABLE_COR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_BASE +CYDEV_PICU_DISABLE_COR_PICU0_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_SIZE +CYDEV_PICU_DISABLE_COR_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_BASE +CYDEV_PICU_DISABLE_COR_PICU1_BASE EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_SIZE +CYDEV_PICU_DISABLE_COR_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_BASE +CYDEV_PICU_DISABLE_COR_PICU2_BASE EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_SIZE +CYDEV_PICU_DISABLE_COR_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_BASE +CYDEV_PICU_DISABLE_COR_PICU3_BASE EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_SIZE +CYDEV_PICU_DISABLE_COR_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_BASE +CYDEV_PICU_DISABLE_COR_PICU4_BASE EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_SIZE +CYDEV_PICU_DISABLE_COR_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_BASE +CYDEV_PICU_DISABLE_COR_PICU5_BASE EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_SIZE +CYDEV_PICU_DISABLE_COR_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_BASE +CYDEV_PICU_DISABLE_COR_PICU6_BASE EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_SIZE +CYDEV_PICU_DISABLE_COR_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_BASE +CYDEV_PICU_DISABLE_COR_PICU12_BASE EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_SIZE +CYDEV_PICU_DISABLE_COR_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_BASE +CYDEV_PICU_DISABLE_COR_PICU15_BASE EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_SIZE +CYDEV_PICU_DISABLE_COR_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_BASE +CYDEV_MFGCFG_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_SIZE +CYDEV_MFGCFG_SIZE EQU 0x000000ed + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_BASE +CYDEV_MFGCFG_ANAIF_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SIZE +CYDEV_MFGCFG_ANAIF_SIZE EQU 0x00000038 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_BASE +CYDEV_MFGCFG_ANAIF_DAC0_BASE EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_SIZE +CYDEV_MFGCFG_ANAIF_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_TR +CYDEV_MFGCFG_ANAIF_DAC0_TR EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_BASE +CYDEV_MFGCFG_ANAIF_DAC1_BASE EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_SIZE +CYDEV_MFGCFG_ANAIF_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_TR +CYDEV_MFGCFG_ANAIF_DAC1_TR EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_BASE +CYDEV_MFGCFG_ANAIF_DAC2_BASE EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_SIZE +CYDEV_MFGCFG_ANAIF_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_TR +CYDEV_MFGCFG_ANAIF_DAC2_TR EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_BASE +CYDEV_MFGCFG_ANAIF_DAC3_BASE EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_SIZE +CYDEV_MFGCFG_ANAIF_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_TR +CYDEV_MFGCFG_ANAIF_DAC3_TR EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 +CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_BASE +CYDEV_MFGCFG_ANAIF_SAR0_BASE EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_SIZE +CYDEV_MFGCFG_ANAIF_SAR0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_TR0 +CYDEV_MFGCFG_ANAIF_SAR0_TR0 EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_BASE +CYDEV_MFGCFG_ANAIF_SAR1_BASE EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_SIZE +CYDEV_MFGCFG_ANAIF_SAR1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_TR0 +CYDEV_MFGCFG_ANAIF_SAR1_TR0 EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_BASE +CYDEV_MFGCFG_ANAIF_OPAMP0_BASE EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 EQU 0x40004621 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_BASE +CYDEV_MFGCFG_ANAIF_OPAMP1_BASE EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 EQU 0x40004623 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_BASE +CYDEV_MFGCFG_ANAIF_OPAMP2_BASE EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 EQU 0x40004625 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_BASE +CYDEV_MFGCFG_ANAIF_OPAMP3_BASE EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 EQU 0x40004627 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_BASE +CYDEV_MFGCFG_ANAIF_CMP0_BASE EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_SIZE +CYDEV_MFGCFG_ANAIF_CMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_TR0 +CYDEV_MFGCFG_ANAIF_CMP0_TR0 EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_TR1 +CYDEV_MFGCFG_ANAIF_CMP0_TR1 EQU 0x40004631 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_BASE +CYDEV_MFGCFG_ANAIF_CMP1_BASE EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_SIZE +CYDEV_MFGCFG_ANAIF_CMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_TR0 +CYDEV_MFGCFG_ANAIF_CMP1_TR0 EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_TR1 +CYDEV_MFGCFG_ANAIF_CMP1_TR1 EQU 0x40004633 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_BASE +CYDEV_MFGCFG_ANAIF_CMP2_BASE EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_SIZE +CYDEV_MFGCFG_ANAIF_CMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_TR0 +CYDEV_MFGCFG_ANAIF_CMP2_TR0 EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_TR1 +CYDEV_MFGCFG_ANAIF_CMP2_TR1 EQU 0x40004635 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_BASE +CYDEV_MFGCFG_ANAIF_CMP3_BASE EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_SIZE +CYDEV_MFGCFG_ANAIF_CMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_TR0 +CYDEV_MFGCFG_ANAIF_CMP3_TR0 EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_TR1 +CYDEV_MFGCFG_ANAIF_CMP3_TR1 EQU 0x40004637 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BASE +CYDEV_MFGCFG_PWRSYS_BASE EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SIZE +CYDEV_MFGCFG_PWRSYS_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_HIB_TR0 +CYDEV_MFGCFG_PWRSYS_HIB_TR0 EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_HIB_TR1 +CYDEV_MFGCFG_PWRSYS_HIB_TR1 EQU 0x40004681 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_I2C_TR +CYDEV_MFGCFG_PWRSYS_I2C_TR EQU 0x40004682 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SLP_TR +CYDEV_MFGCFG_PWRSYS_SLP_TR EQU 0x40004683 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BUZZ_TR +CYDEV_MFGCFG_PWRSYS_BUZZ_TR EQU 0x40004684 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR0 +CYDEV_MFGCFG_PWRSYS_WAKE_TR0 EQU 0x40004685 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR1 +CYDEV_MFGCFG_PWRSYS_WAKE_TR1 EQU 0x40004686 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BREF_TR +CYDEV_MFGCFG_PWRSYS_BREF_TR EQU 0x40004687 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BG_TR +CYDEV_MFGCFG_PWRSYS_BG_TR EQU 0x40004688 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR2 +CYDEV_MFGCFG_PWRSYS_WAKE_TR2 EQU 0x40004689 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR3 +CYDEV_MFGCFG_PWRSYS_WAKE_TR3 EQU 0x4000468a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_BASE +CYDEV_MFGCFG_ILO_BASE EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_SIZE +CYDEV_MFGCFG_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_TR0 +CYDEV_MFGCFG_ILO_TR0 EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_TR1 +CYDEV_MFGCFG_ILO_TR1 EQU 0x40004691 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_BASE +CYDEV_MFGCFG_X32_BASE EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_SIZE +CYDEV_MFGCFG_X32_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_TR +CYDEV_MFGCFG_X32_TR EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_BASE +CYDEV_MFGCFG_IMO_BASE EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_SIZE +CYDEV_MFGCFG_IMO_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR0 +CYDEV_MFGCFG_IMO_TR0 EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR1 +CYDEV_MFGCFG_IMO_TR1 EQU 0x400046a1 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_GAIN +CYDEV_MFGCFG_IMO_GAIN EQU 0x400046a2 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_C36M +CYDEV_MFGCFG_IMO_C36M EQU 0x400046a3 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR2 +CYDEV_MFGCFG_IMO_TR2 EQU 0x400046a4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_BASE +CYDEV_MFGCFG_XMHZ_BASE EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_SIZE +CYDEV_MFGCFG_XMHZ_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_TR +CYDEV_MFGCFG_XMHZ_TR EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_DLY +CYDEV_MFGCFG_DLY EQU 0x400046c0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_BASE +CYDEV_MFGCFG_MLOGIC_BASE EQU 0x400046e0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SIZE +CYDEV_MFGCFG_MLOGIC_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_DMPSTR +CYDEV_MFGCFG_MLOGIC_DMPSTR EQU 0x400046e2 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_BASE +CYDEV_MFGCFG_MLOGIC_SEG_BASE EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_SIZE +CYDEV_MFGCFG_MLOGIC_SEG_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_CR +CYDEV_MFGCFG_MLOGIC_SEG_CR EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_CFG0 +CYDEV_MFGCFG_MLOGIC_SEG_CFG0 EQU 0x400046e5 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_DEBUG +CYDEV_MFGCFG_MLOGIC_DEBUG EQU 0x400046e8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR +CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_REV_ID +CYDEV_MFGCFG_MLOGIC_REV_ID EQU 0x400046ec + ENDIF + IF :LNOT::DEF:CYDEV_RESET_BASE +CYDEV_RESET_BASE EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SIZE +CYDEV_RESET_SIZE EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR0 +CYDEV_RESET_IPOR_CR0 EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR1 +CYDEV_RESET_IPOR_CR1 EQU 0x400046f1 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR2 +CYDEV_RESET_IPOR_CR2 EQU 0x400046f2 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR3 +CYDEV_RESET_IPOR_CR3 EQU 0x400046f3 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR0 +CYDEV_RESET_CR0 EQU 0x400046f4 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR1 +CYDEV_RESET_CR1 EQU 0x400046f5 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR2 +CYDEV_RESET_CR2 EQU 0x400046f6 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR3 +CYDEV_RESET_CR3 EQU 0x400046f7 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR4 +CYDEV_RESET_CR4 EQU 0x400046f8 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR5 +CYDEV_RESET_CR5 EQU 0x400046f9 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR0 +CYDEV_RESET_SR0 EQU 0x400046fa + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR1 +CYDEV_RESET_SR1 EQU 0x400046fb + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR2 +CYDEV_RESET_SR2 EQU 0x400046fc + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR3 +CYDEV_RESET_SR3 EQU 0x400046fd + ENDIF + IF :LNOT::DEF:CYDEV_RESET_TR +CYDEV_RESET_TR EQU 0x400046fe + ENDIF + IF :LNOT::DEF:CYDEV_SPC_BASE +CYDEV_SPC_BASE EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_SIZE +CYDEV_SPC_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_FM_EE_CR +CYDEV_SPC_FM_EE_CR EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_FM_EE_WAKE_CNT +CYDEV_SPC_FM_EE_WAKE_CNT EQU 0x40004701 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_EE_SCR +CYDEV_SPC_EE_SCR EQU 0x40004702 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_EE_ERR +CYDEV_SPC_EE_ERR EQU 0x40004703 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_CPU_DATA +CYDEV_SPC_CPU_DATA EQU 0x40004720 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMA_DATA +CYDEV_SPC_DMA_DATA EQU 0x40004721 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_SR +CYDEV_SPC_SR EQU 0x40004722 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_CR +CYDEV_SPC_CR EQU 0x40004723 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_BASE +CYDEV_SPC_DMM_MAP_BASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SIZE +CYDEV_SPC_DMM_MAP_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SRAM_MBASE +CYDEV_SPC_DMM_MAP_SRAM_MBASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SRAM_MSIZE +CYDEV_SPC_DMM_MAP_SRAM_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_BASE +CYDEV_CACHE_BASE EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_SIZE +CYDEV_CACHE_SIZE EQU 0x0000009c + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_CC_CTL +CYDEV_CACHE_CC_CTL EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_ECC_CORR +CYDEV_CACHE_ECC_CORR EQU 0x40004880 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_ECC_ERR +CYDEV_CACHE_ECC_ERR EQU 0x40004888 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_FLASH_ERR +CYDEV_CACHE_FLASH_ERR EQU 0x40004890 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_HITMISS +CYDEV_CACHE_HITMISS EQU 0x40004898 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_BASE +CYDEV_I2C_BASE EQU 0x40004900 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_SIZE +CYDEV_I2C_SIZE EQU 0x000000e1 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_XCFG +CYDEV_I2C_XCFG EQU 0x400049c8 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_ADR +CYDEV_I2C_ADR EQU 0x400049ca + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CFG +CYDEV_I2C_CFG EQU 0x400049d6 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CSR +CYDEV_I2C_CSR EQU 0x400049d7 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_D +CYDEV_I2C_D EQU 0x400049d8 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_MCSR +CYDEV_I2C_MCSR EQU 0x400049d9 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CLK_DIV1 +CYDEV_I2C_CLK_DIV1 EQU 0x400049db + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CLK_DIV2 +CYDEV_I2C_CLK_DIV2 EQU 0x400049dc + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_CSR +CYDEV_I2C_TMOUT_CSR EQU 0x400049dd + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_SR +CYDEV_I2C_TMOUT_SR EQU 0x400049de + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_CFG0 +CYDEV_I2C_TMOUT_CFG0 EQU 0x400049df + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_CFG1 +CYDEV_I2C_TMOUT_CFG1 EQU 0x400049e0 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_BASE +CYDEV_DEC_BASE EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SIZE +CYDEV_DEC_SIZE EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_CR +CYDEV_DEC_CR EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SR +CYDEV_DEC_SR EQU 0x40004e01 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SHIFT1 +CYDEV_DEC_SHIFT1 EQU 0x40004e02 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SHIFT2 +CYDEV_DEC_SHIFT2 EQU 0x40004e03 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_DR2 +CYDEV_DEC_DR2 EQU 0x40004e04 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_DR2H +CYDEV_DEC_DR2H EQU 0x40004e05 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_DR1 +CYDEV_DEC_DR1 EQU 0x40004e06 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OCOR +CYDEV_DEC_OCOR EQU 0x40004e08 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OCORM +CYDEV_DEC_OCORM EQU 0x40004e09 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OCORH +CYDEV_DEC_OCORH EQU 0x40004e0a + ENDIF + IF :LNOT::DEF:CYDEV_DEC_GCOR +CYDEV_DEC_GCOR EQU 0x40004e0c + ENDIF + IF :LNOT::DEF:CYDEV_DEC_GCORH +CYDEV_DEC_GCORH EQU 0x40004e0d + ENDIF + IF :LNOT::DEF:CYDEV_DEC_GVAL +CYDEV_DEC_GVAL EQU 0x40004e0e + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMP +CYDEV_DEC_OUTSAMP EQU 0x40004e10 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMPM +CYDEV_DEC_OUTSAMPM EQU 0x40004e11 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMPH +CYDEV_DEC_OUTSAMPH EQU 0x40004e12 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMPS +CYDEV_DEC_OUTSAMPS EQU 0x40004e13 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_COHER +CYDEV_DEC_COHER EQU 0x40004e14 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_BASE +CYDEV_TMR0_BASE EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_SIZE +CYDEV_TMR0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CFG0 +CYDEV_TMR0_CFG0 EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CFG1 +CYDEV_TMR0_CFG1 EQU 0x40004f01 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CFG2 +CYDEV_TMR0_CFG2 EQU 0x40004f02 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_SR0 +CYDEV_TMR0_SR0 EQU 0x40004f03 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_PER0 +CYDEV_TMR0_PER0 EQU 0x40004f04 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_PER1 +CYDEV_TMR0_PER1 EQU 0x40004f05 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CNT_CMP0 +CYDEV_TMR0_CNT_CMP0 EQU 0x40004f06 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CNT_CMP1 +CYDEV_TMR0_CNT_CMP1 EQU 0x40004f07 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CAP0 +CYDEV_TMR0_CAP0 EQU 0x40004f08 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CAP1 +CYDEV_TMR0_CAP1 EQU 0x40004f09 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_RT0 +CYDEV_TMR0_RT0 EQU 0x40004f0a + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_RT1 +CYDEV_TMR0_RT1 EQU 0x40004f0b + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_BASE +CYDEV_TMR1_BASE EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_SIZE +CYDEV_TMR1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CFG0 +CYDEV_TMR1_CFG0 EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CFG1 +CYDEV_TMR1_CFG1 EQU 0x40004f0d + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CFG2 +CYDEV_TMR1_CFG2 EQU 0x40004f0e + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_SR0 +CYDEV_TMR1_SR0 EQU 0x40004f0f + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_PER0 +CYDEV_TMR1_PER0 EQU 0x40004f10 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_PER1 +CYDEV_TMR1_PER1 EQU 0x40004f11 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CNT_CMP0 +CYDEV_TMR1_CNT_CMP0 EQU 0x40004f12 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CNT_CMP1 +CYDEV_TMR1_CNT_CMP1 EQU 0x40004f13 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CAP0 +CYDEV_TMR1_CAP0 EQU 0x40004f14 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CAP1 +CYDEV_TMR1_CAP1 EQU 0x40004f15 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_RT0 +CYDEV_TMR1_RT0 EQU 0x40004f16 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_RT1 +CYDEV_TMR1_RT1 EQU 0x40004f17 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_BASE +CYDEV_TMR2_BASE EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_SIZE +CYDEV_TMR2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CFG0 +CYDEV_TMR2_CFG0 EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CFG1 +CYDEV_TMR2_CFG1 EQU 0x40004f19 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CFG2 +CYDEV_TMR2_CFG2 EQU 0x40004f1a + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_SR0 +CYDEV_TMR2_SR0 EQU 0x40004f1b + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_PER0 +CYDEV_TMR2_PER0 EQU 0x40004f1c + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_PER1 +CYDEV_TMR2_PER1 EQU 0x40004f1d + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CNT_CMP0 +CYDEV_TMR2_CNT_CMP0 EQU 0x40004f1e + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CNT_CMP1 +CYDEV_TMR2_CNT_CMP1 EQU 0x40004f1f + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CAP0 +CYDEV_TMR2_CAP0 EQU 0x40004f20 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CAP1 +CYDEV_TMR2_CAP1 EQU 0x40004f21 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_RT0 +CYDEV_TMR2_RT0 EQU 0x40004f22 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_RT1 +CYDEV_TMR2_RT1 EQU 0x40004f23 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_BASE +CYDEV_TMR3_BASE EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_SIZE +CYDEV_TMR3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CFG0 +CYDEV_TMR3_CFG0 EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CFG1 +CYDEV_TMR3_CFG1 EQU 0x40004f25 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CFG2 +CYDEV_TMR3_CFG2 EQU 0x40004f26 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_SR0 +CYDEV_TMR3_SR0 EQU 0x40004f27 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_PER0 +CYDEV_TMR3_PER0 EQU 0x40004f28 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_PER1 +CYDEV_TMR3_PER1 EQU 0x40004f29 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CNT_CMP0 +CYDEV_TMR3_CNT_CMP0 EQU 0x40004f2a + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CNT_CMP1 +CYDEV_TMR3_CNT_CMP1 EQU 0x40004f2b + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CAP0 +CYDEV_TMR3_CAP0 EQU 0x40004f2c + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CAP1 +CYDEV_TMR3_CAP1 EQU 0x40004f2d + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_RT0 +CYDEV_TMR3_RT0 EQU 0x40004f2e + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_RT1 +CYDEV_TMR3_RT1 EQU 0x40004f2f + ENDIF + IF :LNOT::DEF:CYDEV_IO_BASE +CYDEV_IO_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_SIZE +CYDEV_IO_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_BASE +CYDEV_IO_PC_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_SIZE +CYDEV_IO_PC_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_BASE +CYDEV_IO_PC_PRT0_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_SIZE +CYDEV_IO_PC_PRT0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC0 +CYDEV_IO_PC_PRT0_PC0 EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC1 +CYDEV_IO_PC_PRT0_PC1 EQU 0x40005001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC2 +CYDEV_IO_PC_PRT0_PC2 EQU 0x40005002 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC3 +CYDEV_IO_PC_PRT0_PC3 EQU 0x40005003 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC4 +CYDEV_IO_PC_PRT0_PC4 EQU 0x40005004 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC5 +CYDEV_IO_PC_PRT0_PC5 EQU 0x40005005 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC6 +CYDEV_IO_PC_PRT0_PC6 EQU 0x40005006 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC7 +CYDEV_IO_PC_PRT0_PC7 EQU 0x40005007 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_BASE +CYDEV_IO_PC_PRT1_BASE EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_SIZE +CYDEV_IO_PC_PRT1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC0 +CYDEV_IO_PC_PRT1_PC0 EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC1 +CYDEV_IO_PC_PRT1_PC1 EQU 0x40005009 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC2 +CYDEV_IO_PC_PRT1_PC2 EQU 0x4000500a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC3 +CYDEV_IO_PC_PRT1_PC3 EQU 0x4000500b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC4 +CYDEV_IO_PC_PRT1_PC4 EQU 0x4000500c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC5 +CYDEV_IO_PC_PRT1_PC5 EQU 0x4000500d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC6 +CYDEV_IO_PC_PRT1_PC6 EQU 0x4000500e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC7 +CYDEV_IO_PC_PRT1_PC7 EQU 0x4000500f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_BASE +CYDEV_IO_PC_PRT2_BASE EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_SIZE +CYDEV_IO_PC_PRT2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC0 +CYDEV_IO_PC_PRT2_PC0 EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC1 +CYDEV_IO_PC_PRT2_PC1 EQU 0x40005011 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC2 +CYDEV_IO_PC_PRT2_PC2 EQU 0x40005012 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC3 +CYDEV_IO_PC_PRT2_PC3 EQU 0x40005013 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC4 +CYDEV_IO_PC_PRT2_PC4 EQU 0x40005014 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC5 +CYDEV_IO_PC_PRT2_PC5 EQU 0x40005015 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC6 +CYDEV_IO_PC_PRT2_PC6 EQU 0x40005016 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC7 +CYDEV_IO_PC_PRT2_PC7 EQU 0x40005017 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_BASE +CYDEV_IO_PC_PRT3_BASE EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_SIZE +CYDEV_IO_PC_PRT3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC0 +CYDEV_IO_PC_PRT3_PC0 EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC1 +CYDEV_IO_PC_PRT3_PC1 EQU 0x40005019 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC2 +CYDEV_IO_PC_PRT3_PC2 EQU 0x4000501a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC3 +CYDEV_IO_PC_PRT3_PC3 EQU 0x4000501b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC4 +CYDEV_IO_PC_PRT3_PC4 EQU 0x4000501c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC5 +CYDEV_IO_PC_PRT3_PC5 EQU 0x4000501d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC6 +CYDEV_IO_PC_PRT3_PC6 EQU 0x4000501e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC7 +CYDEV_IO_PC_PRT3_PC7 EQU 0x4000501f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_BASE +CYDEV_IO_PC_PRT4_BASE EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_SIZE +CYDEV_IO_PC_PRT4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC0 +CYDEV_IO_PC_PRT4_PC0 EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC1 +CYDEV_IO_PC_PRT4_PC1 EQU 0x40005021 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC2 +CYDEV_IO_PC_PRT4_PC2 EQU 0x40005022 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC3 +CYDEV_IO_PC_PRT4_PC3 EQU 0x40005023 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC4 +CYDEV_IO_PC_PRT4_PC4 EQU 0x40005024 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC5 +CYDEV_IO_PC_PRT4_PC5 EQU 0x40005025 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC6 +CYDEV_IO_PC_PRT4_PC6 EQU 0x40005026 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC7 +CYDEV_IO_PC_PRT4_PC7 EQU 0x40005027 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_BASE +CYDEV_IO_PC_PRT5_BASE EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_SIZE +CYDEV_IO_PC_PRT5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC0 +CYDEV_IO_PC_PRT5_PC0 EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC1 +CYDEV_IO_PC_PRT5_PC1 EQU 0x40005029 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC2 +CYDEV_IO_PC_PRT5_PC2 EQU 0x4000502a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC3 +CYDEV_IO_PC_PRT5_PC3 EQU 0x4000502b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC4 +CYDEV_IO_PC_PRT5_PC4 EQU 0x4000502c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC5 +CYDEV_IO_PC_PRT5_PC5 EQU 0x4000502d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC6 +CYDEV_IO_PC_PRT5_PC6 EQU 0x4000502e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC7 +CYDEV_IO_PC_PRT5_PC7 EQU 0x4000502f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_BASE +CYDEV_IO_PC_PRT6_BASE EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_SIZE +CYDEV_IO_PC_PRT6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC0 +CYDEV_IO_PC_PRT6_PC0 EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC1 +CYDEV_IO_PC_PRT6_PC1 EQU 0x40005031 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC2 +CYDEV_IO_PC_PRT6_PC2 EQU 0x40005032 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC3 +CYDEV_IO_PC_PRT6_PC3 EQU 0x40005033 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC4 +CYDEV_IO_PC_PRT6_PC4 EQU 0x40005034 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC5 +CYDEV_IO_PC_PRT6_PC5 EQU 0x40005035 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC6 +CYDEV_IO_PC_PRT6_PC6 EQU 0x40005036 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC7 +CYDEV_IO_PC_PRT6_PC7 EQU 0x40005037 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_BASE +CYDEV_IO_PC_PRT12_BASE EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_SIZE +CYDEV_IO_PC_PRT12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC0 +CYDEV_IO_PC_PRT12_PC0 EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC1 +CYDEV_IO_PC_PRT12_PC1 EQU 0x40005061 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC2 +CYDEV_IO_PC_PRT12_PC2 EQU 0x40005062 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC3 +CYDEV_IO_PC_PRT12_PC3 EQU 0x40005063 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC4 +CYDEV_IO_PC_PRT12_PC4 EQU 0x40005064 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC5 +CYDEV_IO_PC_PRT12_PC5 EQU 0x40005065 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC6 +CYDEV_IO_PC_PRT12_PC6 EQU 0x40005066 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC7 +CYDEV_IO_PC_PRT12_PC7 EQU 0x40005067 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_BASE +CYDEV_IO_PC_PRT15_BASE EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_SIZE +CYDEV_IO_PC_PRT15_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC0 +CYDEV_IO_PC_PRT15_PC0 EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC1 +CYDEV_IO_PC_PRT15_PC1 EQU 0x40005079 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC2 +CYDEV_IO_PC_PRT15_PC2 EQU 0x4000507a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC3 +CYDEV_IO_PC_PRT15_PC3 EQU 0x4000507b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC4 +CYDEV_IO_PC_PRT15_PC4 EQU 0x4000507c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC5 +CYDEV_IO_PC_PRT15_PC5 EQU 0x4000507d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_BASE +CYDEV_IO_PC_PRT15_7_6_BASE EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_SIZE +CYDEV_IO_PC_PRT15_7_6_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_PC0 +CYDEV_IO_PC_PRT15_7_6_PC0 EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_PC1 +CYDEV_IO_PC_PRT15_7_6_PC1 EQU 0x4000507f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_BASE +CYDEV_IO_DR_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_SIZE +CYDEV_IO_DR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_BASE +CYDEV_IO_DR_PRT0_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_SIZE +CYDEV_IO_DR_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_DR_ALIAS +CYDEV_IO_DR_PRT0_DR_ALIAS EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_BASE +CYDEV_IO_DR_PRT1_BASE EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_SIZE +CYDEV_IO_DR_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_DR_ALIAS +CYDEV_IO_DR_PRT1_DR_ALIAS EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_BASE +CYDEV_IO_DR_PRT2_BASE EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_SIZE +CYDEV_IO_DR_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_DR_ALIAS +CYDEV_IO_DR_PRT2_DR_ALIAS EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_BASE +CYDEV_IO_DR_PRT3_BASE EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_SIZE +CYDEV_IO_DR_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_DR_ALIAS +CYDEV_IO_DR_PRT3_DR_ALIAS EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_BASE +CYDEV_IO_DR_PRT4_BASE EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_SIZE +CYDEV_IO_DR_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_DR_ALIAS +CYDEV_IO_DR_PRT4_DR_ALIAS EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_BASE +CYDEV_IO_DR_PRT5_BASE EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_SIZE +CYDEV_IO_DR_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_DR_ALIAS +CYDEV_IO_DR_PRT5_DR_ALIAS EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_BASE +CYDEV_IO_DR_PRT6_BASE EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_SIZE +CYDEV_IO_DR_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_DR_ALIAS +CYDEV_IO_DR_PRT6_DR_ALIAS EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_BASE +CYDEV_IO_DR_PRT12_BASE EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_SIZE +CYDEV_IO_DR_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_DR_ALIAS +CYDEV_IO_DR_PRT12_DR_ALIAS EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_BASE +CYDEV_IO_DR_PRT15_BASE EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_SIZE +CYDEV_IO_DR_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_DR_15_ALIAS +CYDEV_IO_DR_PRT15_DR_15_ALIAS EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_BASE +CYDEV_IO_PS_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_SIZE +CYDEV_IO_PS_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_BASE +CYDEV_IO_PS_PRT0_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_SIZE +CYDEV_IO_PS_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_PS_ALIAS +CYDEV_IO_PS_PRT0_PS_ALIAS EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_BASE +CYDEV_IO_PS_PRT1_BASE EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_SIZE +CYDEV_IO_PS_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_PS_ALIAS +CYDEV_IO_PS_PRT1_PS_ALIAS EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_BASE +CYDEV_IO_PS_PRT2_BASE EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_SIZE +CYDEV_IO_PS_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_PS_ALIAS +CYDEV_IO_PS_PRT2_PS_ALIAS EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_BASE +CYDEV_IO_PS_PRT3_BASE EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_SIZE +CYDEV_IO_PS_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_PS_ALIAS +CYDEV_IO_PS_PRT3_PS_ALIAS EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_BASE +CYDEV_IO_PS_PRT4_BASE EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_SIZE +CYDEV_IO_PS_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_PS_ALIAS +CYDEV_IO_PS_PRT4_PS_ALIAS EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_BASE +CYDEV_IO_PS_PRT5_BASE EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_SIZE +CYDEV_IO_PS_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_PS_ALIAS +CYDEV_IO_PS_PRT5_PS_ALIAS EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_BASE +CYDEV_IO_PS_PRT6_BASE EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_SIZE +CYDEV_IO_PS_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_PS_ALIAS +CYDEV_IO_PS_PRT6_PS_ALIAS EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_BASE +CYDEV_IO_PS_PRT12_BASE EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_SIZE +CYDEV_IO_PS_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_PS_ALIAS +CYDEV_IO_PS_PRT12_PS_ALIAS EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_BASE +CYDEV_IO_PS_PRT15_BASE EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_SIZE +CYDEV_IO_PS_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_PS15_ALIAS +CYDEV_IO_PS_PRT15_PS15_ALIAS EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_BASE +CYDEV_IO_PRT_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_SIZE +CYDEV_IO_PRT_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BASE +CYDEV_IO_PRT_PRT0_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SIZE +CYDEV_IO_PRT_PRT0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DR +CYDEV_IO_PRT_PRT0_DR EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_PS +CYDEV_IO_PRT_PRT0_PS EQU 0x40005101 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM0 +CYDEV_IO_PRT_PRT0_DM0 EQU 0x40005102 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM1 +CYDEV_IO_PRT_PRT0_DM1 EQU 0x40005103 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM2 +CYDEV_IO_PRT_PRT0_DM2 EQU 0x40005104 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SLW +CYDEV_IO_PRT_PRT0_SLW EQU 0x40005105 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BYP +CYDEV_IO_PRT_PRT0_BYP EQU 0x40005106 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BIE +CYDEV_IO_PRT_PRT0_BIE EQU 0x40005107 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_INP_DIS +CYDEV_IO_PRT_PRT0_INP_DIS EQU 0x40005108 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_CTL +CYDEV_IO_PRT_PRT0_CTL EQU 0x40005109 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_PRT +CYDEV_IO_PRT_PRT0_PRT EQU 0x4000510a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BIT_MASK +CYDEV_IO_PRT_PRT0_BIT_MASK EQU 0x4000510b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_AMUX +CYDEV_IO_PRT_PRT0_AMUX EQU 0x4000510c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_AG +CYDEV_IO_PRT_PRT0_AG EQU 0x4000510d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_LCD_COM_SEG +CYDEV_IO_PRT_PRT0_LCD_COM_SEG EQU 0x4000510e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_LCD_EN +CYDEV_IO_PRT_PRT0_LCD_EN EQU 0x4000510f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BASE +CYDEV_IO_PRT_PRT1_BASE EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SIZE +CYDEV_IO_PRT_PRT1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DR +CYDEV_IO_PRT_PRT1_DR EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_PS +CYDEV_IO_PRT_PRT1_PS EQU 0x40005111 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM0 +CYDEV_IO_PRT_PRT1_DM0 EQU 0x40005112 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM1 +CYDEV_IO_PRT_PRT1_DM1 EQU 0x40005113 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM2 +CYDEV_IO_PRT_PRT1_DM2 EQU 0x40005114 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SLW +CYDEV_IO_PRT_PRT1_SLW EQU 0x40005115 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BYP +CYDEV_IO_PRT_PRT1_BYP EQU 0x40005116 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BIE +CYDEV_IO_PRT_PRT1_BIE EQU 0x40005117 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_INP_DIS +CYDEV_IO_PRT_PRT1_INP_DIS EQU 0x40005118 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_CTL +CYDEV_IO_PRT_PRT1_CTL EQU 0x40005119 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_PRT +CYDEV_IO_PRT_PRT1_PRT EQU 0x4000511a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BIT_MASK +CYDEV_IO_PRT_PRT1_BIT_MASK EQU 0x4000511b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_AMUX +CYDEV_IO_PRT_PRT1_AMUX EQU 0x4000511c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_AG +CYDEV_IO_PRT_PRT1_AG EQU 0x4000511d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_LCD_COM_SEG +CYDEV_IO_PRT_PRT1_LCD_COM_SEG EQU 0x4000511e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_LCD_EN +CYDEV_IO_PRT_PRT1_LCD_EN EQU 0x4000511f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BASE +CYDEV_IO_PRT_PRT2_BASE EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SIZE +CYDEV_IO_PRT_PRT2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DR +CYDEV_IO_PRT_PRT2_DR EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_PS +CYDEV_IO_PRT_PRT2_PS EQU 0x40005121 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM0 +CYDEV_IO_PRT_PRT2_DM0 EQU 0x40005122 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM1 +CYDEV_IO_PRT_PRT2_DM1 EQU 0x40005123 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM2 +CYDEV_IO_PRT_PRT2_DM2 EQU 0x40005124 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SLW +CYDEV_IO_PRT_PRT2_SLW EQU 0x40005125 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BYP +CYDEV_IO_PRT_PRT2_BYP EQU 0x40005126 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BIE +CYDEV_IO_PRT_PRT2_BIE EQU 0x40005127 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_INP_DIS +CYDEV_IO_PRT_PRT2_INP_DIS EQU 0x40005128 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_CTL +CYDEV_IO_PRT_PRT2_CTL EQU 0x40005129 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_PRT +CYDEV_IO_PRT_PRT2_PRT EQU 0x4000512a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BIT_MASK +CYDEV_IO_PRT_PRT2_BIT_MASK EQU 0x4000512b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_AMUX +CYDEV_IO_PRT_PRT2_AMUX EQU 0x4000512c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_AG +CYDEV_IO_PRT_PRT2_AG EQU 0x4000512d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_LCD_COM_SEG +CYDEV_IO_PRT_PRT2_LCD_COM_SEG EQU 0x4000512e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_LCD_EN +CYDEV_IO_PRT_PRT2_LCD_EN EQU 0x4000512f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BASE +CYDEV_IO_PRT_PRT3_BASE EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SIZE +CYDEV_IO_PRT_PRT3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DR +CYDEV_IO_PRT_PRT3_DR EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_PS +CYDEV_IO_PRT_PRT3_PS EQU 0x40005131 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM0 +CYDEV_IO_PRT_PRT3_DM0 EQU 0x40005132 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM1 +CYDEV_IO_PRT_PRT3_DM1 EQU 0x40005133 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM2 +CYDEV_IO_PRT_PRT3_DM2 EQU 0x40005134 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SLW +CYDEV_IO_PRT_PRT3_SLW EQU 0x40005135 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BYP +CYDEV_IO_PRT_PRT3_BYP EQU 0x40005136 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BIE +CYDEV_IO_PRT_PRT3_BIE EQU 0x40005137 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_INP_DIS +CYDEV_IO_PRT_PRT3_INP_DIS EQU 0x40005138 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_CTL +CYDEV_IO_PRT_PRT3_CTL EQU 0x40005139 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_PRT +CYDEV_IO_PRT_PRT3_PRT EQU 0x4000513a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BIT_MASK +CYDEV_IO_PRT_PRT3_BIT_MASK EQU 0x4000513b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_AMUX +CYDEV_IO_PRT_PRT3_AMUX EQU 0x4000513c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_AG +CYDEV_IO_PRT_PRT3_AG EQU 0x4000513d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_LCD_COM_SEG +CYDEV_IO_PRT_PRT3_LCD_COM_SEG EQU 0x4000513e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_LCD_EN +CYDEV_IO_PRT_PRT3_LCD_EN EQU 0x4000513f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BASE +CYDEV_IO_PRT_PRT4_BASE EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SIZE +CYDEV_IO_PRT_PRT4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DR +CYDEV_IO_PRT_PRT4_DR EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_PS +CYDEV_IO_PRT_PRT4_PS EQU 0x40005141 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM0 +CYDEV_IO_PRT_PRT4_DM0 EQU 0x40005142 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM1 +CYDEV_IO_PRT_PRT4_DM1 EQU 0x40005143 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM2 +CYDEV_IO_PRT_PRT4_DM2 EQU 0x40005144 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SLW +CYDEV_IO_PRT_PRT4_SLW EQU 0x40005145 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BYP +CYDEV_IO_PRT_PRT4_BYP EQU 0x40005146 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BIE +CYDEV_IO_PRT_PRT4_BIE EQU 0x40005147 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_INP_DIS +CYDEV_IO_PRT_PRT4_INP_DIS EQU 0x40005148 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_CTL +CYDEV_IO_PRT_PRT4_CTL EQU 0x40005149 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_PRT +CYDEV_IO_PRT_PRT4_PRT EQU 0x4000514a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BIT_MASK +CYDEV_IO_PRT_PRT4_BIT_MASK EQU 0x4000514b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_AMUX +CYDEV_IO_PRT_PRT4_AMUX EQU 0x4000514c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_AG +CYDEV_IO_PRT_PRT4_AG EQU 0x4000514d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_LCD_COM_SEG +CYDEV_IO_PRT_PRT4_LCD_COM_SEG EQU 0x4000514e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_LCD_EN +CYDEV_IO_PRT_PRT4_LCD_EN EQU 0x4000514f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BASE +CYDEV_IO_PRT_PRT5_BASE EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SIZE +CYDEV_IO_PRT_PRT5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DR +CYDEV_IO_PRT_PRT5_DR EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_PS +CYDEV_IO_PRT_PRT5_PS EQU 0x40005151 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM0 +CYDEV_IO_PRT_PRT5_DM0 EQU 0x40005152 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM1 +CYDEV_IO_PRT_PRT5_DM1 EQU 0x40005153 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM2 +CYDEV_IO_PRT_PRT5_DM2 EQU 0x40005154 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SLW +CYDEV_IO_PRT_PRT5_SLW EQU 0x40005155 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BYP +CYDEV_IO_PRT_PRT5_BYP EQU 0x40005156 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BIE +CYDEV_IO_PRT_PRT5_BIE EQU 0x40005157 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_INP_DIS +CYDEV_IO_PRT_PRT5_INP_DIS EQU 0x40005158 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_CTL +CYDEV_IO_PRT_PRT5_CTL EQU 0x40005159 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_PRT +CYDEV_IO_PRT_PRT5_PRT EQU 0x4000515a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BIT_MASK +CYDEV_IO_PRT_PRT5_BIT_MASK EQU 0x4000515b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_AMUX +CYDEV_IO_PRT_PRT5_AMUX EQU 0x4000515c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_AG +CYDEV_IO_PRT_PRT5_AG EQU 0x4000515d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_LCD_COM_SEG +CYDEV_IO_PRT_PRT5_LCD_COM_SEG EQU 0x4000515e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_LCD_EN +CYDEV_IO_PRT_PRT5_LCD_EN EQU 0x4000515f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BASE +CYDEV_IO_PRT_PRT6_BASE EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SIZE +CYDEV_IO_PRT_PRT6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DR +CYDEV_IO_PRT_PRT6_DR EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_PS +CYDEV_IO_PRT_PRT6_PS EQU 0x40005161 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM0 +CYDEV_IO_PRT_PRT6_DM0 EQU 0x40005162 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM1 +CYDEV_IO_PRT_PRT6_DM1 EQU 0x40005163 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM2 +CYDEV_IO_PRT_PRT6_DM2 EQU 0x40005164 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SLW +CYDEV_IO_PRT_PRT6_SLW EQU 0x40005165 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BYP +CYDEV_IO_PRT_PRT6_BYP EQU 0x40005166 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BIE +CYDEV_IO_PRT_PRT6_BIE EQU 0x40005167 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_INP_DIS +CYDEV_IO_PRT_PRT6_INP_DIS EQU 0x40005168 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_CTL +CYDEV_IO_PRT_PRT6_CTL EQU 0x40005169 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_PRT +CYDEV_IO_PRT_PRT6_PRT EQU 0x4000516a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BIT_MASK +CYDEV_IO_PRT_PRT6_BIT_MASK EQU 0x4000516b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_AMUX +CYDEV_IO_PRT_PRT6_AMUX EQU 0x4000516c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_AG +CYDEV_IO_PRT_PRT6_AG EQU 0x4000516d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_LCD_COM_SEG +CYDEV_IO_PRT_PRT6_LCD_COM_SEG EQU 0x4000516e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_LCD_EN +CYDEV_IO_PRT_PRT6_LCD_EN EQU 0x4000516f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BASE +CYDEV_IO_PRT_PRT12_BASE EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIZE +CYDEV_IO_PRT_PRT12_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DR +CYDEV_IO_PRT_PRT12_DR EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_PS +CYDEV_IO_PRT_PRT12_PS EQU 0x400051c1 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM0 +CYDEV_IO_PRT_PRT12_DM0 EQU 0x400051c2 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM1 +CYDEV_IO_PRT_PRT12_DM1 EQU 0x400051c3 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM2 +CYDEV_IO_PRT_PRT12_DM2 EQU 0x400051c4 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SLW +CYDEV_IO_PRT_PRT12_SLW EQU 0x400051c5 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BYP +CYDEV_IO_PRT_PRT12_BYP EQU 0x400051c6 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BIE +CYDEV_IO_PRT_PRT12_BIE EQU 0x400051c7 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_INP_DIS +CYDEV_IO_PRT_PRT12_INP_DIS EQU 0x400051c8 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_HYST_EN +CYDEV_IO_PRT_PRT12_SIO_HYST_EN EQU 0x400051c9 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_PRT +CYDEV_IO_PRT_PRT12_PRT EQU 0x400051ca + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BIT_MASK +CYDEV_IO_PRT_PRT12_BIT_MASK EQU 0x400051cb + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ +CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ EQU 0x400051cc + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_AG +CYDEV_IO_PRT_PRT12_AG EQU 0x400051cd + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_CFG +CYDEV_IO_PRT_PRT12_SIO_CFG EQU 0x400051ce + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_DIFF +CYDEV_IO_PRT_PRT12_SIO_DIFF EQU 0x400051cf + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BASE +CYDEV_IO_PRT_PRT15_BASE EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SIZE +CYDEV_IO_PRT_PRT15_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DR +CYDEV_IO_PRT_PRT15_DR EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_PS +CYDEV_IO_PRT_PRT15_PS EQU 0x400051f1 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM0 +CYDEV_IO_PRT_PRT15_DM0 EQU 0x400051f2 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM1 +CYDEV_IO_PRT_PRT15_DM1 EQU 0x400051f3 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM2 +CYDEV_IO_PRT_PRT15_DM2 EQU 0x400051f4 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SLW +CYDEV_IO_PRT_PRT15_SLW EQU 0x400051f5 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BYP +CYDEV_IO_PRT_PRT15_BYP EQU 0x400051f6 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BIE +CYDEV_IO_PRT_PRT15_BIE EQU 0x400051f7 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_INP_DIS +CYDEV_IO_PRT_PRT15_INP_DIS EQU 0x400051f8 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_CTL +CYDEV_IO_PRT_PRT15_CTL EQU 0x400051f9 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_PRT +CYDEV_IO_PRT_PRT15_PRT EQU 0x400051fa + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BIT_MASK +CYDEV_IO_PRT_PRT15_BIT_MASK EQU 0x400051fb + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_AMUX +CYDEV_IO_PRT_PRT15_AMUX EQU 0x400051fc + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_AG +CYDEV_IO_PRT_PRT15_AG EQU 0x400051fd + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_LCD_COM_SEG +CYDEV_IO_PRT_PRT15_LCD_COM_SEG EQU 0x400051fe + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_LCD_EN +CYDEV_IO_PRT_PRT15_LCD_EN EQU 0x400051ff + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_BASE +CYDEV_PRTDSI_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_SIZE +CYDEV_PRTDSI_SIZE EQU 0x0000007f + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_BASE +CYDEV_PRTDSI_PRT0_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SIZE +CYDEV_PRTDSI_PRT0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OUT_SEL0 +CYDEV_PRTDSI_PRT0_OUT_SEL0 EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OUT_SEL1 +CYDEV_PRTDSI_PRT0_OUT_SEL1 EQU 0x40005201 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OE_SEL0 +CYDEV_PRTDSI_PRT0_OE_SEL0 EQU 0x40005202 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OE_SEL1 +CYDEV_PRTDSI_PRT0_OE_SEL1 EQU 0x40005203 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_DBL_SYNC_IN +CYDEV_PRTDSI_PRT0_DBL_SYNC_IN EQU 0x40005204 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SYNC_OUT +CYDEV_PRTDSI_PRT0_SYNC_OUT EQU 0x40005205 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_CAPS_SEL +CYDEV_PRTDSI_PRT0_CAPS_SEL EQU 0x40005206 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_BASE +CYDEV_PRTDSI_PRT1_BASE EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SIZE +CYDEV_PRTDSI_PRT1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OUT_SEL0 +CYDEV_PRTDSI_PRT1_OUT_SEL0 EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OUT_SEL1 +CYDEV_PRTDSI_PRT1_OUT_SEL1 EQU 0x40005209 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OE_SEL0 +CYDEV_PRTDSI_PRT1_OE_SEL0 EQU 0x4000520a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OE_SEL1 +CYDEV_PRTDSI_PRT1_OE_SEL1 EQU 0x4000520b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_DBL_SYNC_IN +CYDEV_PRTDSI_PRT1_DBL_SYNC_IN EQU 0x4000520c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SYNC_OUT +CYDEV_PRTDSI_PRT1_SYNC_OUT EQU 0x4000520d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_CAPS_SEL +CYDEV_PRTDSI_PRT1_CAPS_SEL EQU 0x4000520e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_BASE +CYDEV_PRTDSI_PRT2_BASE EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SIZE +CYDEV_PRTDSI_PRT2_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OUT_SEL0 +CYDEV_PRTDSI_PRT2_OUT_SEL0 EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OUT_SEL1 +CYDEV_PRTDSI_PRT2_OUT_SEL1 EQU 0x40005211 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OE_SEL0 +CYDEV_PRTDSI_PRT2_OE_SEL0 EQU 0x40005212 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OE_SEL1 +CYDEV_PRTDSI_PRT2_OE_SEL1 EQU 0x40005213 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_DBL_SYNC_IN +CYDEV_PRTDSI_PRT2_DBL_SYNC_IN EQU 0x40005214 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SYNC_OUT +CYDEV_PRTDSI_PRT2_SYNC_OUT EQU 0x40005215 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_CAPS_SEL +CYDEV_PRTDSI_PRT2_CAPS_SEL EQU 0x40005216 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_BASE +CYDEV_PRTDSI_PRT3_BASE EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SIZE +CYDEV_PRTDSI_PRT3_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OUT_SEL0 +CYDEV_PRTDSI_PRT3_OUT_SEL0 EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OUT_SEL1 +CYDEV_PRTDSI_PRT3_OUT_SEL1 EQU 0x40005219 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OE_SEL0 +CYDEV_PRTDSI_PRT3_OE_SEL0 EQU 0x4000521a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OE_SEL1 +CYDEV_PRTDSI_PRT3_OE_SEL1 EQU 0x4000521b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_DBL_SYNC_IN +CYDEV_PRTDSI_PRT3_DBL_SYNC_IN EQU 0x4000521c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SYNC_OUT +CYDEV_PRTDSI_PRT3_SYNC_OUT EQU 0x4000521d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_CAPS_SEL +CYDEV_PRTDSI_PRT3_CAPS_SEL EQU 0x4000521e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_BASE +CYDEV_PRTDSI_PRT4_BASE EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SIZE +CYDEV_PRTDSI_PRT4_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OUT_SEL0 +CYDEV_PRTDSI_PRT4_OUT_SEL0 EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OUT_SEL1 +CYDEV_PRTDSI_PRT4_OUT_SEL1 EQU 0x40005221 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OE_SEL0 +CYDEV_PRTDSI_PRT4_OE_SEL0 EQU 0x40005222 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OE_SEL1 +CYDEV_PRTDSI_PRT4_OE_SEL1 EQU 0x40005223 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_DBL_SYNC_IN +CYDEV_PRTDSI_PRT4_DBL_SYNC_IN EQU 0x40005224 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SYNC_OUT +CYDEV_PRTDSI_PRT4_SYNC_OUT EQU 0x40005225 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_CAPS_SEL +CYDEV_PRTDSI_PRT4_CAPS_SEL EQU 0x40005226 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_BASE +CYDEV_PRTDSI_PRT5_BASE EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SIZE +CYDEV_PRTDSI_PRT5_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OUT_SEL0 +CYDEV_PRTDSI_PRT5_OUT_SEL0 EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OUT_SEL1 +CYDEV_PRTDSI_PRT5_OUT_SEL1 EQU 0x40005229 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OE_SEL0 +CYDEV_PRTDSI_PRT5_OE_SEL0 EQU 0x4000522a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OE_SEL1 +CYDEV_PRTDSI_PRT5_OE_SEL1 EQU 0x4000522b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_DBL_SYNC_IN +CYDEV_PRTDSI_PRT5_DBL_SYNC_IN EQU 0x4000522c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SYNC_OUT +CYDEV_PRTDSI_PRT5_SYNC_OUT EQU 0x4000522d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_CAPS_SEL +CYDEV_PRTDSI_PRT5_CAPS_SEL EQU 0x4000522e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_BASE +CYDEV_PRTDSI_PRT6_BASE EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SIZE +CYDEV_PRTDSI_PRT6_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OUT_SEL0 +CYDEV_PRTDSI_PRT6_OUT_SEL0 EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OUT_SEL1 +CYDEV_PRTDSI_PRT6_OUT_SEL1 EQU 0x40005231 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OE_SEL0 +CYDEV_PRTDSI_PRT6_OE_SEL0 EQU 0x40005232 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OE_SEL1 +CYDEV_PRTDSI_PRT6_OE_SEL1 EQU 0x40005233 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_DBL_SYNC_IN +CYDEV_PRTDSI_PRT6_DBL_SYNC_IN EQU 0x40005234 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SYNC_OUT +CYDEV_PRTDSI_PRT6_SYNC_OUT EQU 0x40005235 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_CAPS_SEL +CYDEV_PRTDSI_PRT6_CAPS_SEL EQU 0x40005236 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_BASE +CYDEV_PRTDSI_PRT12_BASE EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SIZE +CYDEV_PRTDSI_PRT12_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OUT_SEL0 +CYDEV_PRTDSI_PRT12_OUT_SEL0 EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OUT_SEL1 +CYDEV_PRTDSI_PRT12_OUT_SEL1 EQU 0x40005261 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OE_SEL0 +CYDEV_PRTDSI_PRT12_OE_SEL0 EQU 0x40005262 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OE_SEL1 +CYDEV_PRTDSI_PRT12_OE_SEL1 EQU 0x40005263 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_DBL_SYNC_IN +CYDEV_PRTDSI_PRT12_DBL_SYNC_IN EQU 0x40005264 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SYNC_OUT +CYDEV_PRTDSI_PRT12_SYNC_OUT EQU 0x40005265 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_BASE +CYDEV_PRTDSI_PRT15_BASE EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SIZE +CYDEV_PRTDSI_PRT15_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OUT_SEL0 +CYDEV_PRTDSI_PRT15_OUT_SEL0 EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OUT_SEL1 +CYDEV_PRTDSI_PRT15_OUT_SEL1 EQU 0x40005279 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OE_SEL0 +CYDEV_PRTDSI_PRT15_OE_SEL0 EQU 0x4000527a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OE_SEL1 +CYDEV_PRTDSI_PRT15_OE_SEL1 EQU 0x4000527b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_DBL_SYNC_IN +CYDEV_PRTDSI_PRT15_DBL_SYNC_IN EQU 0x4000527c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SYNC_OUT +CYDEV_PRTDSI_PRT15_SYNC_OUT EQU 0x4000527d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_CAPS_SEL +CYDEV_PRTDSI_PRT15_CAPS_SEL EQU 0x4000527e + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_BASE +CYDEV_EMIF_BASE EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_SIZE +CYDEV_EMIF_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_NO_UDB +CYDEV_EMIF_NO_UDB EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_RP_WAIT_STATES +CYDEV_EMIF_RP_WAIT_STATES EQU 0x40005401 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_MEM_DWN +CYDEV_EMIF_MEM_DWN EQU 0x40005402 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_MEMCLK_DIV +CYDEV_EMIF_MEMCLK_DIV EQU 0x40005403 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_CLOCK_EN +CYDEV_EMIF_CLOCK_EN EQU 0x40005404 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_EM_TYPE +CYDEV_EMIF_EM_TYPE EQU 0x40005405 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_WP_WAIT_STATES +CYDEV_EMIF_WP_WAIT_STATES EQU 0x40005406 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_BASE +CYDEV_ANAIF_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_SIZE +CYDEV_ANAIF_SIZE EQU 0x000003a9 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BASE +CYDEV_ANAIF_CFG_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SIZE +CYDEV_ANAIF_CFG_SIZE EQU 0x0000010f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_BASE +CYDEV_ANAIF_CFG_SC0_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_SIZE +CYDEV_ANAIF_CFG_SC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR0 +CYDEV_ANAIF_CFG_SC0_CR0 EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR1 +CYDEV_ANAIF_CFG_SC0_CR1 EQU 0x40005801 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR2 +CYDEV_ANAIF_CFG_SC0_CR2 EQU 0x40005802 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_BASE +CYDEV_ANAIF_CFG_SC1_BASE EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_SIZE +CYDEV_ANAIF_CFG_SC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR0 +CYDEV_ANAIF_CFG_SC1_CR0 EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR1 +CYDEV_ANAIF_CFG_SC1_CR1 EQU 0x40005805 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR2 +CYDEV_ANAIF_CFG_SC1_CR2 EQU 0x40005806 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_BASE +CYDEV_ANAIF_CFG_SC2_BASE EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_SIZE +CYDEV_ANAIF_CFG_SC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR0 +CYDEV_ANAIF_CFG_SC2_CR0 EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR1 +CYDEV_ANAIF_CFG_SC2_CR1 EQU 0x40005809 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR2 +CYDEV_ANAIF_CFG_SC2_CR2 EQU 0x4000580a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_BASE +CYDEV_ANAIF_CFG_SC3_BASE EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_SIZE +CYDEV_ANAIF_CFG_SC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR0 +CYDEV_ANAIF_CFG_SC3_CR0 EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR1 +CYDEV_ANAIF_CFG_SC3_CR1 EQU 0x4000580d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR2 +CYDEV_ANAIF_CFG_SC3_CR2 EQU 0x4000580e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_BASE +CYDEV_ANAIF_CFG_DAC0_BASE EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_SIZE +CYDEV_ANAIF_CFG_DAC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_CR0 +CYDEV_ANAIF_CFG_DAC0_CR0 EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_CR1 +CYDEV_ANAIF_CFG_DAC0_CR1 EQU 0x40005821 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_TST +CYDEV_ANAIF_CFG_DAC0_TST EQU 0x40005822 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_BASE +CYDEV_ANAIF_CFG_DAC1_BASE EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_SIZE +CYDEV_ANAIF_CFG_DAC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_CR0 +CYDEV_ANAIF_CFG_DAC1_CR0 EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_CR1 +CYDEV_ANAIF_CFG_DAC1_CR1 EQU 0x40005825 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_TST +CYDEV_ANAIF_CFG_DAC1_TST EQU 0x40005826 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_BASE +CYDEV_ANAIF_CFG_DAC2_BASE EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_SIZE +CYDEV_ANAIF_CFG_DAC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_CR0 +CYDEV_ANAIF_CFG_DAC2_CR0 EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_CR1 +CYDEV_ANAIF_CFG_DAC2_CR1 EQU 0x40005829 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_TST +CYDEV_ANAIF_CFG_DAC2_TST EQU 0x4000582a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_BASE +CYDEV_ANAIF_CFG_DAC3_BASE EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_SIZE +CYDEV_ANAIF_CFG_DAC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_CR0 +CYDEV_ANAIF_CFG_DAC3_CR0 EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_CR1 +CYDEV_ANAIF_CFG_DAC3_CR1 EQU 0x4000582d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_TST +CYDEV_ANAIF_CFG_DAC3_TST EQU 0x4000582e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_BASE +CYDEV_ANAIF_CFG_CMP0_BASE EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_SIZE +CYDEV_ANAIF_CFG_CMP0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_CR +CYDEV_ANAIF_CFG_CMP0_CR EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_BASE +CYDEV_ANAIF_CFG_CMP1_BASE EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_SIZE +CYDEV_ANAIF_CFG_CMP1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_CR +CYDEV_ANAIF_CFG_CMP1_CR EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_BASE +CYDEV_ANAIF_CFG_CMP2_BASE EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_SIZE +CYDEV_ANAIF_CFG_CMP2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_CR +CYDEV_ANAIF_CFG_CMP2_CR EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_BASE +CYDEV_ANAIF_CFG_CMP3_BASE EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_SIZE +CYDEV_ANAIF_CFG_CMP3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_CR +CYDEV_ANAIF_CFG_CMP3_CR EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_BASE +CYDEV_ANAIF_CFG_LUT0_BASE EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_SIZE +CYDEV_ANAIF_CFG_LUT0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_CR +CYDEV_ANAIF_CFG_LUT0_CR EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_MX +CYDEV_ANAIF_CFG_LUT0_MX EQU 0x40005849 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_BASE +CYDEV_ANAIF_CFG_LUT1_BASE EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_SIZE +CYDEV_ANAIF_CFG_LUT1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_CR +CYDEV_ANAIF_CFG_LUT1_CR EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_MX +CYDEV_ANAIF_CFG_LUT1_MX EQU 0x4000584b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_BASE +CYDEV_ANAIF_CFG_LUT2_BASE EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_SIZE +CYDEV_ANAIF_CFG_LUT2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_CR +CYDEV_ANAIF_CFG_LUT2_CR EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_MX +CYDEV_ANAIF_CFG_LUT2_MX EQU 0x4000584d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_BASE +CYDEV_ANAIF_CFG_LUT3_BASE EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_SIZE +CYDEV_ANAIF_CFG_LUT3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_CR +CYDEV_ANAIF_CFG_LUT3_CR EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_MX +CYDEV_ANAIF_CFG_LUT3_MX EQU 0x4000584f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_BASE +CYDEV_ANAIF_CFG_OPAMP0_BASE EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_SIZE +CYDEV_ANAIF_CFG_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_CR +CYDEV_ANAIF_CFG_OPAMP0_CR EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_RSVD +CYDEV_ANAIF_CFG_OPAMP0_RSVD EQU 0x40005859 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_BASE +CYDEV_ANAIF_CFG_OPAMP1_BASE EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_SIZE +CYDEV_ANAIF_CFG_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_CR +CYDEV_ANAIF_CFG_OPAMP1_CR EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_RSVD +CYDEV_ANAIF_CFG_OPAMP1_RSVD EQU 0x4000585b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_BASE +CYDEV_ANAIF_CFG_OPAMP2_BASE EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_SIZE +CYDEV_ANAIF_CFG_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_CR +CYDEV_ANAIF_CFG_OPAMP2_CR EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_RSVD +CYDEV_ANAIF_CFG_OPAMP2_RSVD EQU 0x4000585d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_BASE +CYDEV_ANAIF_CFG_OPAMP3_BASE EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_SIZE +CYDEV_ANAIF_CFG_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_CR +CYDEV_ANAIF_CFG_OPAMP3_CR EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_RSVD +CYDEV_ANAIF_CFG_OPAMP3_RSVD EQU 0x4000585f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_BASE +CYDEV_ANAIF_CFG_LCDDAC_BASE EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_SIZE +CYDEV_ANAIF_CFG_LCDDAC_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_CR0 +CYDEV_ANAIF_CFG_LCDDAC_CR0 EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_CR1 +CYDEV_ANAIF_CFG_LCDDAC_CR1 EQU 0x40005869 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_BASE +CYDEV_ANAIF_CFG_LCDDRV_BASE EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_SIZE +CYDEV_ANAIF_CFG_LCDDRV_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_CR +CYDEV_ANAIF_CFG_LCDDRV_CR EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_BASE +CYDEV_ANAIF_CFG_LCDTMR_BASE EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_SIZE +CYDEV_ANAIF_CFG_LCDTMR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_CFG +CYDEV_ANAIF_CFG_LCDTMR_CFG EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_BASE +CYDEV_ANAIF_CFG_BG_BASE EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_SIZE +CYDEV_ANAIF_CFG_BG_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_CR0 +CYDEV_ANAIF_CFG_BG_CR0 EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_RSVD +CYDEV_ANAIF_CFG_BG_RSVD EQU 0x4000586d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_DFT0 +CYDEV_ANAIF_CFG_BG_DFT0 EQU 0x4000586e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_DFT1 +CYDEV_ANAIF_CFG_BG_DFT1 EQU 0x4000586f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_BASE +CYDEV_ANAIF_CFG_CAPSL_BASE EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_SIZE +CYDEV_ANAIF_CFG_CAPSL_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_CFG0 +CYDEV_ANAIF_CFG_CAPSL_CFG0 EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_CFG1 +CYDEV_ANAIF_CFG_CAPSL_CFG1 EQU 0x40005871 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_BASE +CYDEV_ANAIF_CFG_CAPSR_BASE EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_SIZE +CYDEV_ANAIF_CFG_CAPSR_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_CFG0 +CYDEV_ANAIF_CFG_CAPSR_CFG0 EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_CFG1 +CYDEV_ANAIF_CFG_CAPSR_CFG1 EQU 0x40005873 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_BASE +CYDEV_ANAIF_CFG_PUMP_BASE EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_SIZE +CYDEV_ANAIF_CFG_PUMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_CR0 +CYDEV_ANAIF_CFG_PUMP_CR0 EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_CR1 +CYDEV_ANAIF_CFG_PUMP_CR1 EQU 0x40005877 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_BASE +CYDEV_ANAIF_CFG_LPF0_BASE EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_SIZE +CYDEV_ANAIF_CFG_LPF0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_CR0 +CYDEV_ANAIF_CFG_LPF0_CR0 EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_RSVD +CYDEV_ANAIF_CFG_LPF0_RSVD EQU 0x40005879 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_BASE +CYDEV_ANAIF_CFG_LPF1_BASE EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_SIZE +CYDEV_ANAIF_CFG_LPF1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_CR0 +CYDEV_ANAIF_CFG_LPF1_CR0 EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_RSVD +CYDEV_ANAIF_CFG_LPF1_RSVD EQU 0x4000587b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_BASE +CYDEV_ANAIF_CFG_MISC_BASE EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_SIZE +CYDEV_ANAIF_CFG_MISC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_CR0 +CYDEV_ANAIF_CFG_MISC_CR0 EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BASE +CYDEV_ANAIF_CFG_DSM0_BASE EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_SIZE +CYDEV_ANAIF_CFG_DSM0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR0 +CYDEV_ANAIF_CFG_DSM0_CR0 EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR1 +CYDEV_ANAIF_CFG_DSM0_CR1 EQU 0x40005881 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR2 +CYDEV_ANAIF_CFG_DSM0_CR2 EQU 0x40005882 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR3 +CYDEV_ANAIF_CFG_DSM0_CR3 EQU 0x40005883 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR4 +CYDEV_ANAIF_CFG_DSM0_CR4 EQU 0x40005884 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR5 +CYDEV_ANAIF_CFG_DSM0_CR5 EQU 0x40005885 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR6 +CYDEV_ANAIF_CFG_DSM0_CR6 EQU 0x40005886 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR7 +CYDEV_ANAIF_CFG_DSM0_CR7 EQU 0x40005887 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR8 +CYDEV_ANAIF_CFG_DSM0_CR8 EQU 0x40005888 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR9 +CYDEV_ANAIF_CFG_DSM0_CR9 EQU 0x40005889 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR10 +CYDEV_ANAIF_CFG_DSM0_CR10 EQU 0x4000588a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR11 +CYDEV_ANAIF_CFG_DSM0_CR11 EQU 0x4000588b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR12 +CYDEV_ANAIF_CFG_DSM0_CR12 EQU 0x4000588c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR13 +CYDEV_ANAIF_CFG_DSM0_CR13 EQU 0x4000588d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR14 +CYDEV_ANAIF_CFG_DSM0_CR14 EQU 0x4000588e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR15 +CYDEV_ANAIF_CFG_DSM0_CR15 EQU 0x4000588f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR16 +CYDEV_ANAIF_CFG_DSM0_CR16 EQU 0x40005890 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR17 +CYDEV_ANAIF_CFG_DSM0_CR17 EQU 0x40005891 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF0 +CYDEV_ANAIF_CFG_DSM0_REF0 EQU 0x40005892 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF1 +CYDEV_ANAIF_CFG_DSM0_REF1 EQU 0x40005893 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF2 +CYDEV_ANAIF_CFG_DSM0_REF2 EQU 0x40005894 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF3 +CYDEV_ANAIF_CFG_DSM0_REF3 EQU 0x40005895 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_DEM0 +CYDEV_ANAIF_CFG_DSM0_DEM0 EQU 0x40005896 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_DEM1 +CYDEV_ANAIF_CFG_DSM0_DEM1 EQU 0x40005897 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_TST0 +CYDEV_ANAIF_CFG_DSM0_TST0 EQU 0x40005898 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_TST1 +CYDEV_ANAIF_CFG_DSM0_TST1 EQU 0x40005899 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF0 +CYDEV_ANAIF_CFG_DSM0_BUF0 EQU 0x4000589a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF1 +CYDEV_ANAIF_CFG_DSM0_BUF1 EQU 0x4000589b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF2 +CYDEV_ANAIF_CFG_DSM0_BUF2 EQU 0x4000589c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF3 +CYDEV_ANAIF_CFG_DSM0_BUF3 EQU 0x4000589d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_MISC +CYDEV_ANAIF_CFG_DSM0_MISC EQU 0x4000589e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_RSVD1 +CYDEV_ANAIF_CFG_DSM0_RSVD1 EQU 0x4000589f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_BASE +CYDEV_ANAIF_CFG_SAR0_BASE EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_SIZE +CYDEV_ANAIF_CFG_SAR0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR0 +CYDEV_ANAIF_CFG_SAR0_CSR0 EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR1 +CYDEV_ANAIF_CFG_SAR0_CSR1 EQU 0x40005901 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR2 +CYDEV_ANAIF_CFG_SAR0_CSR2 EQU 0x40005902 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR3 +CYDEV_ANAIF_CFG_SAR0_CSR3 EQU 0x40005903 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR4 +CYDEV_ANAIF_CFG_SAR0_CSR4 EQU 0x40005904 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR5 +CYDEV_ANAIF_CFG_SAR0_CSR5 EQU 0x40005905 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR6 +CYDEV_ANAIF_CFG_SAR0_CSR6 EQU 0x40005906 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_BASE +CYDEV_ANAIF_CFG_SAR1_BASE EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_SIZE +CYDEV_ANAIF_CFG_SAR1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR0 +CYDEV_ANAIF_CFG_SAR1_CSR0 EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR1 +CYDEV_ANAIF_CFG_SAR1_CSR1 EQU 0x40005909 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR2 +CYDEV_ANAIF_CFG_SAR1_CSR2 EQU 0x4000590a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR3 +CYDEV_ANAIF_CFG_SAR1_CSR3 EQU 0x4000590b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR4 +CYDEV_ANAIF_CFG_SAR1_CSR4 EQU 0x4000590c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR5 +CYDEV_ANAIF_CFG_SAR1_CSR5 EQU 0x4000590d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR6 +CYDEV_ANAIF_CFG_SAR1_CSR6 EQU 0x4000590e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BASE +CYDEV_ANAIF_RT_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SIZE +CYDEV_ANAIF_RT_SIZE EQU 0x00000162 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BASE +CYDEV_ANAIF_RT_SC0_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SIZE +CYDEV_ANAIF_RT_SC0_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW0 +CYDEV_ANAIF_RT_SC0_SW0 EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW2 +CYDEV_ANAIF_RT_SC0_SW2 EQU 0x40005a02 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW3 +CYDEV_ANAIF_RT_SC0_SW3 EQU 0x40005a03 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW4 +CYDEV_ANAIF_RT_SC0_SW4 EQU 0x40005a04 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW6 +CYDEV_ANAIF_RT_SC0_SW6 EQU 0x40005a06 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW7 +CYDEV_ANAIF_RT_SC0_SW7 EQU 0x40005a07 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW8 +CYDEV_ANAIF_RT_SC0_SW8 EQU 0x40005a08 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW10 +CYDEV_ANAIF_RT_SC0_SW10 EQU 0x40005a0a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_CLK +CYDEV_ANAIF_RT_SC0_CLK EQU 0x40005a0b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BST +CYDEV_ANAIF_RT_SC0_BST EQU 0x40005a0c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BASE +CYDEV_ANAIF_RT_SC1_BASE EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SIZE +CYDEV_ANAIF_RT_SC1_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW0 +CYDEV_ANAIF_RT_SC1_SW0 EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW2 +CYDEV_ANAIF_RT_SC1_SW2 EQU 0x40005a12 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW3 +CYDEV_ANAIF_RT_SC1_SW3 EQU 0x40005a13 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW4 +CYDEV_ANAIF_RT_SC1_SW4 EQU 0x40005a14 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW6 +CYDEV_ANAIF_RT_SC1_SW6 EQU 0x40005a16 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW7 +CYDEV_ANAIF_RT_SC1_SW7 EQU 0x40005a17 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW8 +CYDEV_ANAIF_RT_SC1_SW8 EQU 0x40005a18 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW10 +CYDEV_ANAIF_RT_SC1_SW10 EQU 0x40005a1a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_CLK +CYDEV_ANAIF_RT_SC1_CLK EQU 0x40005a1b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BST +CYDEV_ANAIF_RT_SC1_BST EQU 0x40005a1c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BASE +CYDEV_ANAIF_RT_SC2_BASE EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SIZE +CYDEV_ANAIF_RT_SC2_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW0 +CYDEV_ANAIF_RT_SC2_SW0 EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW2 +CYDEV_ANAIF_RT_SC2_SW2 EQU 0x40005a22 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW3 +CYDEV_ANAIF_RT_SC2_SW3 EQU 0x40005a23 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW4 +CYDEV_ANAIF_RT_SC2_SW4 EQU 0x40005a24 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW6 +CYDEV_ANAIF_RT_SC2_SW6 EQU 0x40005a26 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW7 +CYDEV_ANAIF_RT_SC2_SW7 EQU 0x40005a27 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW8 +CYDEV_ANAIF_RT_SC2_SW8 EQU 0x40005a28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW10 +CYDEV_ANAIF_RT_SC2_SW10 EQU 0x40005a2a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_CLK +CYDEV_ANAIF_RT_SC2_CLK EQU 0x40005a2b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BST +CYDEV_ANAIF_RT_SC2_BST EQU 0x40005a2c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BASE +CYDEV_ANAIF_RT_SC3_BASE EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SIZE +CYDEV_ANAIF_RT_SC3_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW0 +CYDEV_ANAIF_RT_SC3_SW0 EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW2 +CYDEV_ANAIF_RT_SC3_SW2 EQU 0x40005a32 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW3 +CYDEV_ANAIF_RT_SC3_SW3 EQU 0x40005a33 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW4 +CYDEV_ANAIF_RT_SC3_SW4 EQU 0x40005a34 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW6 +CYDEV_ANAIF_RT_SC3_SW6 EQU 0x40005a36 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW7 +CYDEV_ANAIF_RT_SC3_SW7 EQU 0x40005a37 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW8 +CYDEV_ANAIF_RT_SC3_SW8 EQU 0x40005a38 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW10 +CYDEV_ANAIF_RT_SC3_SW10 EQU 0x40005a3a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_CLK +CYDEV_ANAIF_RT_SC3_CLK EQU 0x40005a3b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BST +CYDEV_ANAIF_RT_SC3_BST EQU 0x40005a3c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_BASE +CYDEV_ANAIF_RT_DAC0_BASE EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SIZE +CYDEV_ANAIF_RT_DAC0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW0 +CYDEV_ANAIF_RT_DAC0_SW0 EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW2 +CYDEV_ANAIF_RT_DAC0_SW2 EQU 0x40005a82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW3 +CYDEV_ANAIF_RT_DAC0_SW3 EQU 0x40005a83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW4 +CYDEV_ANAIF_RT_DAC0_SW4 EQU 0x40005a84 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_STROBE +CYDEV_ANAIF_RT_DAC0_STROBE EQU 0x40005a87 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_BASE +CYDEV_ANAIF_RT_DAC1_BASE EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SIZE +CYDEV_ANAIF_RT_DAC1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW0 +CYDEV_ANAIF_RT_DAC1_SW0 EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW2 +CYDEV_ANAIF_RT_DAC1_SW2 EQU 0x40005a8a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW3 +CYDEV_ANAIF_RT_DAC1_SW3 EQU 0x40005a8b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW4 +CYDEV_ANAIF_RT_DAC1_SW4 EQU 0x40005a8c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_STROBE +CYDEV_ANAIF_RT_DAC1_STROBE EQU 0x40005a8f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_BASE +CYDEV_ANAIF_RT_DAC2_BASE EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SIZE +CYDEV_ANAIF_RT_DAC2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW0 +CYDEV_ANAIF_RT_DAC2_SW0 EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW2 +CYDEV_ANAIF_RT_DAC2_SW2 EQU 0x40005a92 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW3 +CYDEV_ANAIF_RT_DAC2_SW3 EQU 0x40005a93 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW4 +CYDEV_ANAIF_RT_DAC2_SW4 EQU 0x40005a94 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_STROBE +CYDEV_ANAIF_RT_DAC2_STROBE EQU 0x40005a97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_BASE +CYDEV_ANAIF_RT_DAC3_BASE EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SIZE +CYDEV_ANAIF_RT_DAC3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW0 +CYDEV_ANAIF_RT_DAC3_SW0 EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW2 +CYDEV_ANAIF_RT_DAC3_SW2 EQU 0x40005a9a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW3 +CYDEV_ANAIF_RT_DAC3_SW3 EQU 0x40005a9b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW4 +CYDEV_ANAIF_RT_DAC3_SW4 EQU 0x40005a9c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_STROBE +CYDEV_ANAIF_RT_DAC3_STROBE EQU 0x40005a9f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_BASE +CYDEV_ANAIF_RT_CMP0_BASE EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SIZE +CYDEV_ANAIF_RT_CMP0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW0 +CYDEV_ANAIF_RT_CMP0_SW0 EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW2 +CYDEV_ANAIF_RT_CMP0_SW2 EQU 0x40005ac2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW3 +CYDEV_ANAIF_RT_CMP0_SW3 EQU 0x40005ac3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW4 +CYDEV_ANAIF_RT_CMP0_SW4 EQU 0x40005ac4 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW6 +CYDEV_ANAIF_RT_CMP0_SW6 EQU 0x40005ac6 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_CLK +CYDEV_ANAIF_RT_CMP0_CLK EQU 0x40005ac7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_BASE +CYDEV_ANAIF_RT_CMP1_BASE EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SIZE +CYDEV_ANAIF_RT_CMP1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW0 +CYDEV_ANAIF_RT_CMP1_SW0 EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW2 +CYDEV_ANAIF_RT_CMP1_SW2 EQU 0x40005aca + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW3 +CYDEV_ANAIF_RT_CMP1_SW3 EQU 0x40005acb + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW4 +CYDEV_ANAIF_RT_CMP1_SW4 EQU 0x40005acc + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW6 +CYDEV_ANAIF_RT_CMP1_SW6 EQU 0x40005ace + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_CLK +CYDEV_ANAIF_RT_CMP1_CLK EQU 0x40005acf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_BASE +CYDEV_ANAIF_RT_CMP2_BASE EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SIZE +CYDEV_ANAIF_RT_CMP2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW0 +CYDEV_ANAIF_RT_CMP2_SW0 EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW2 +CYDEV_ANAIF_RT_CMP2_SW2 EQU 0x40005ad2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW3 +CYDEV_ANAIF_RT_CMP2_SW3 EQU 0x40005ad3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW4 +CYDEV_ANAIF_RT_CMP2_SW4 EQU 0x40005ad4 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW6 +CYDEV_ANAIF_RT_CMP2_SW6 EQU 0x40005ad6 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_CLK +CYDEV_ANAIF_RT_CMP2_CLK EQU 0x40005ad7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_BASE +CYDEV_ANAIF_RT_CMP3_BASE EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SIZE +CYDEV_ANAIF_RT_CMP3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW0 +CYDEV_ANAIF_RT_CMP3_SW0 EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW2 +CYDEV_ANAIF_RT_CMP3_SW2 EQU 0x40005ada + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW3 +CYDEV_ANAIF_RT_CMP3_SW3 EQU 0x40005adb + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW4 +CYDEV_ANAIF_RT_CMP3_SW4 EQU 0x40005adc + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW6 +CYDEV_ANAIF_RT_CMP3_SW6 EQU 0x40005ade + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_CLK +CYDEV_ANAIF_RT_CMP3_CLK EQU 0x40005adf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_BASE +CYDEV_ANAIF_RT_DSM0_BASE EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SIZE +CYDEV_ANAIF_RT_DSM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW0 +CYDEV_ANAIF_RT_DSM0_SW0 EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW2 +CYDEV_ANAIF_RT_DSM0_SW2 EQU 0x40005b02 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW3 +CYDEV_ANAIF_RT_DSM0_SW3 EQU 0x40005b03 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW4 +CYDEV_ANAIF_RT_DSM0_SW4 EQU 0x40005b04 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW6 +CYDEV_ANAIF_RT_DSM0_SW6 EQU 0x40005b06 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_CLK +CYDEV_ANAIF_RT_DSM0_CLK EQU 0x40005b07 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_BASE +CYDEV_ANAIF_RT_SAR0_BASE EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SIZE +CYDEV_ANAIF_RT_SAR0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW0 +CYDEV_ANAIF_RT_SAR0_SW0 EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW2 +CYDEV_ANAIF_RT_SAR0_SW2 EQU 0x40005b22 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW3 +CYDEV_ANAIF_RT_SAR0_SW3 EQU 0x40005b23 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW4 +CYDEV_ANAIF_RT_SAR0_SW4 EQU 0x40005b24 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW6 +CYDEV_ANAIF_RT_SAR0_SW6 EQU 0x40005b26 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_CLK +CYDEV_ANAIF_RT_SAR0_CLK EQU 0x40005b27 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_BASE +CYDEV_ANAIF_RT_SAR1_BASE EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SIZE +CYDEV_ANAIF_RT_SAR1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW0 +CYDEV_ANAIF_RT_SAR1_SW0 EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW2 +CYDEV_ANAIF_RT_SAR1_SW2 EQU 0x40005b2a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW3 +CYDEV_ANAIF_RT_SAR1_SW3 EQU 0x40005b2b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW4 +CYDEV_ANAIF_RT_SAR1_SW4 EQU 0x40005b2c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW6 +CYDEV_ANAIF_RT_SAR1_SW6 EQU 0x40005b2e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_CLK +CYDEV_ANAIF_RT_SAR1_CLK EQU 0x40005b2f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_BASE +CYDEV_ANAIF_RT_OPAMP0_BASE EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SIZE +CYDEV_ANAIF_RT_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_MX +CYDEV_ANAIF_RT_OPAMP0_MX EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SW +CYDEV_ANAIF_RT_OPAMP0_SW EQU 0x40005b41 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_BASE +CYDEV_ANAIF_RT_OPAMP1_BASE EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SIZE +CYDEV_ANAIF_RT_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_MX +CYDEV_ANAIF_RT_OPAMP1_MX EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SW +CYDEV_ANAIF_RT_OPAMP1_SW EQU 0x40005b43 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_BASE +CYDEV_ANAIF_RT_OPAMP2_BASE EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SIZE +CYDEV_ANAIF_RT_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_MX +CYDEV_ANAIF_RT_OPAMP2_MX EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SW +CYDEV_ANAIF_RT_OPAMP2_SW EQU 0x40005b45 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_BASE +CYDEV_ANAIF_RT_OPAMP3_BASE EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SIZE +CYDEV_ANAIF_RT_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_MX +CYDEV_ANAIF_RT_OPAMP3_MX EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SW +CYDEV_ANAIF_RT_OPAMP3_SW EQU 0x40005b47 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_BASE +CYDEV_ANAIF_RT_LCDDAC_BASE EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SIZE +CYDEV_ANAIF_RT_LCDDAC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW0 +CYDEV_ANAIF_RT_LCDDAC_SW0 EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW1 +CYDEV_ANAIF_RT_LCDDAC_SW1 EQU 0x40005b51 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW2 +CYDEV_ANAIF_RT_LCDDAC_SW2 EQU 0x40005b52 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW3 +CYDEV_ANAIF_RT_LCDDAC_SW3 EQU 0x40005b53 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW4 +CYDEV_ANAIF_RT_LCDDAC_SW4 EQU 0x40005b54 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_BASE +CYDEV_ANAIF_RT_SC_BASE EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_SIZE +CYDEV_ANAIF_RT_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_MISC +CYDEV_ANAIF_RT_SC_MISC EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_BASE +CYDEV_ANAIF_RT_BUS_BASE EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SIZE +CYDEV_ANAIF_RT_BUS_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW0 +CYDEV_ANAIF_RT_BUS_SW0 EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW2 +CYDEV_ANAIF_RT_BUS_SW2 EQU 0x40005b5a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW3 +CYDEV_ANAIF_RT_BUS_SW3 EQU 0x40005b5b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_BASE +CYDEV_ANAIF_RT_DFT_BASE EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_SIZE +CYDEV_ANAIF_RT_DFT_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR0 +CYDEV_ANAIF_RT_DFT_CR0 EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR1 +CYDEV_ANAIF_RT_DFT_CR1 EQU 0x40005b5d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR2 +CYDEV_ANAIF_RT_DFT_CR2 EQU 0x40005b5e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR3 +CYDEV_ANAIF_RT_DFT_CR3 EQU 0x40005b5f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR4 +CYDEV_ANAIF_RT_DFT_CR4 EQU 0x40005b60 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR5 +CYDEV_ANAIF_RT_DFT_CR5 EQU 0x40005b61 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_BASE +CYDEV_ANAIF_WRK_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SIZE +CYDEV_ANAIF_WRK_SIZE EQU 0x00000029 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_BASE +CYDEV_ANAIF_WRK_DAC0_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_SIZE +CYDEV_ANAIF_WRK_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_D +CYDEV_ANAIF_WRK_DAC0_D EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_BASE +CYDEV_ANAIF_WRK_DAC1_BASE EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_SIZE +CYDEV_ANAIF_WRK_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_D +CYDEV_ANAIF_WRK_DAC1_D EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_BASE +CYDEV_ANAIF_WRK_DAC2_BASE EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_SIZE +CYDEV_ANAIF_WRK_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_D +CYDEV_ANAIF_WRK_DAC2_D EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_BASE +CYDEV_ANAIF_WRK_DAC3_BASE EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_SIZE +CYDEV_ANAIF_WRK_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_D +CYDEV_ANAIF_WRK_DAC3_D EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_BASE +CYDEV_ANAIF_WRK_DSM0_BASE EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_SIZE +CYDEV_ANAIF_WRK_DSM0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_OUT0 +CYDEV_ANAIF_WRK_DSM0_OUT0 EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_OUT1 +CYDEV_ANAIF_WRK_DSM0_OUT1 EQU 0x40005b89 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_BASE +CYDEV_ANAIF_WRK_LUT_BASE EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SIZE +CYDEV_ANAIF_WRK_LUT_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SR +CYDEV_ANAIF_WRK_LUT_SR EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_WRK1 +CYDEV_ANAIF_WRK_LUT_WRK1 EQU 0x40005b91 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_MSK +CYDEV_ANAIF_WRK_LUT_MSK EQU 0x40005b92 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_CLK +CYDEV_ANAIF_WRK_LUT_CLK EQU 0x40005b93 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_CPTR +CYDEV_ANAIF_WRK_LUT_CPTR EQU 0x40005b94 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_BASE +CYDEV_ANAIF_WRK_CMP_BASE EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_SIZE +CYDEV_ANAIF_WRK_CMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_WRK +CYDEV_ANAIF_WRK_CMP_WRK EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_TST +CYDEV_ANAIF_WRK_CMP_TST EQU 0x40005b97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_BASE +CYDEV_ANAIF_WRK_SC_BASE EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SIZE +CYDEV_ANAIF_WRK_SC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SR +CYDEV_ANAIF_WRK_SC_SR EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_WRK1 +CYDEV_ANAIF_WRK_SC_WRK1 EQU 0x40005b99 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_MSK +CYDEV_ANAIF_WRK_SC_MSK EQU 0x40005b9a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_CMPINV +CYDEV_ANAIF_WRK_SC_CMPINV EQU 0x40005b9b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_CPTR +CYDEV_ANAIF_WRK_SC_CPTR EQU 0x40005b9c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_BASE +CYDEV_ANAIF_WRK_SAR0_BASE EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_SIZE +CYDEV_ANAIF_WRK_SAR0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_WRK0 +CYDEV_ANAIF_WRK_SAR0_WRK0 EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_WRK1 +CYDEV_ANAIF_WRK_SAR0_WRK1 EQU 0x40005ba1 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_BASE +CYDEV_ANAIF_WRK_SAR1_BASE EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_SIZE +CYDEV_ANAIF_WRK_SAR1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_WRK0 +CYDEV_ANAIF_WRK_SAR1_WRK0 EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_WRK1 +CYDEV_ANAIF_WRK_SAR1_WRK1 EQU 0x40005ba3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_BASE +CYDEV_ANAIF_WRK_SARS_BASE EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SIZE +CYDEV_ANAIF_WRK_SARS_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SOF +CYDEV_ANAIF_WRK_SARS_SOF EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BASE +CYDEV_USB_BASE EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIZE +CYDEV_USB_SIZE EQU 0x00000300 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR0 +CYDEV_USB_EP0_DR0 EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR1 +CYDEV_USB_EP0_DR1 EQU 0x40006001 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR2 +CYDEV_USB_EP0_DR2 EQU 0x40006002 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR3 +CYDEV_USB_EP0_DR3 EQU 0x40006003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR4 +CYDEV_USB_EP0_DR4 EQU 0x40006004 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR5 +CYDEV_USB_EP0_DR5 EQU 0x40006005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR6 +CYDEV_USB_EP0_DR6 EQU 0x40006006 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR7 +CYDEV_USB_EP0_DR7 EQU 0x40006007 + ENDIF + IF :LNOT::DEF:CYDEV_USB_CR0 +CYDEV_USB_CR0 EQU 0x40006008 + ENDIF + IF :LNOT::DEF:CYDEV_USB_CR1 +CYDEV_USB_CR1 EQU 0x40006009 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP_INT_EN +CYDEV_USB_SIE_EP_INT_EN EQU 0x4000600a + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP_INT_SR +CYDEV_USB_SIE_EP_INT_SR EQU 0x4000600b + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_BASE +CYDEV_USB_SIE_EP1_BASE EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_SIZE +CYDEV_USB_SIE_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CNT0 +CYDEV_USB_SIE_EP1_CNT0 EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CNT1 +CYDEV_USB_SIE_EP1_CNT1 EQU 0x4000600d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CR0 +CYDEV_USB_SIE_EP1_CR0 EQU 0x4000600e + ENDIF + IF :LNOT::DEF:CYDEV_USB_USBIO_CR0 +CYDEV_USB_USBIO_CR0 EQU 0x40006010 + ENDIF + IF :LNOT::DEF:CYDEV_USB_USBIO_CR1 +CYDEV_USB_USBIO_CR1 EQU 0x40006012 + ENDIF + IF :LNOT::DEF:CYDEV_USB_DYN_RECONFIG +CYDEV_USB_DYN_RECONFIG EQU 0x40006014 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SOF0 +CYDEV_USB_SOF0 EQU 0x40006018 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SOF1 +CYDEV_USB_SOF1 EQU 0x40006019 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_BASE +CYDEV_USB_SIE_EP2_BASE EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_SIZE +CYDEV_USB_SIE_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CNT0 +CYDEV_USB_SIE_EP2_CNT0 EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CNT1 +CYDEV_USB_SIE_EP2_CNT1 EQU 0x4000601d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CR0 +CYDEV_USB_SIE_EP2_CR0 EQU 0x4000601e + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_CR +CYDEV_USB_EP0_CR EQU 0x40006028 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_CNT +CYDEV_USB_EP0_CNT EQU 0x40006029 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_BASE +CYDEV_USB_SIE_EP3_BASE EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_SIZE +CYDEV_USB_SIE_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CNT0 +CYDEV_USB_SIE_EP3_CNT0 EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CNT1 +CYDEV_USB_SIE_EP3_CNT1 EQU 0x4000602d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CR0 +CYDEV_USB_SIE_EP3_CR0 EQU 0x4000602e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_BASE +CYDEV_USB_SIE_EP4_BASE EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_SIZE +CYDEV_USB_SIE_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CNT0 +CYDEV_USB_SIE_EP4_CNT0 EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CNT1 +CYDEV_USB_SIE_EP4_CNT1 EQU 0x4000603d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CR0 +CYDEV_USB_SIE_EP4_CR0 EQU 0x4000603e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_BASE +CYDEV_USB_SIE_EP5_BASE EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_SIZE +CYDEV_USB_SIE_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CNT0 +CYDEV_USB_SIE_EP5_CNT0 EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CNT1 +CYDEV_USB_SIE_EP5_CNT1 EQU 0x4000604d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CR0 +CYDEV_USB_SIE_EP5_CR0 EQU 0x4000604e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_BASE +CYDEV_USB_SIE_EP6_BASE EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_SIZE +CYDEV_USB_SIE_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CNT0 +CYDEV_USB_SIE_EP6_CNT0 EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CNT1 +CYDEV_USB_SIE_EP6_CNT1 EQU 0x4000605d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CR0 +CYDEV_USB_SIE_EP6_CR0 EQU 0x4000605e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_BASE +CYDEV_USB_SIE_EP7_BASE EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_SIZE +CYDEV_USB_SIE_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CNT0 +CYDEV_USB_SIE_EP7_CNT0 EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CNT1 +CYDEV_USB_SIE_EP7_CNT1 EQU 0x4000606d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CR0 +CYDEV_USB_SIE_EP7_CR0 EQU 0x4000606e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_BASE +CYDEV_USB_SIE_EP8_BASE EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_SIZE +CYDEV_USB_SIE_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CNT0 +CYDEV_USB_SIE_EP8_CNT0 EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CNT1 +CYDEV_USB_SIE_EP8_CNT1 EQU 0x4000607d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CR0 +CYDEV_USB_SIE_EP8_CR0 EQU 0x4000607e + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_BASE +CYDEV_USB_ARB_EP1_BASE EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SIZE +CYDEV_USB_ARB_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_CFG +CYDEV_USB_ARB_EP1_CFG EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_INT_EN +CYDEV_USB_ARB_EP1_INT_EN EQU 0x40006081 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SR +CYDEV_USB_ARB_EP1_SR EQU 0x40006082 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_BASE +CYDEV_USB_ARB_RW1_BASE EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_SIZE +CYDEV_USB_ARB_RW1_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_WA +CYDEV_USB_ARB_RW1_WA EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_WA_MSB +CYDEV_USB_ARB_RW1_WA_MSB EQU 0x40006085 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_RA +CYDEV_USB_ARB_RW1_RA EQU 0x40006086 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_RA_MSB +CYDEV_USB_ARB_RW1_RA_MSB EQU 0x40006087 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_DR +CYDEV_USB_ARB_RW1_DR EQU 0x40006088 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BUF_SIZE +CYDEV_USB_BUF_SIZE EQU 0x4000608c + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP_ACTIVE +CYDEV_USB_EP_ACTIVE EQU 0x4000608e + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP_TYPE +CYDEV_USB_EP_TYPE EQU 0x4000608f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_BASE +CYDEV_USB_ARB_EP2_BASE EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SIZE +CYDEV_USB_ARB_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_CFG +CYDEV_USB_ARB_EP2_CFG EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_INT_EN +CYDEV_USB_ARB_EP2_INT_EN EQU 0x40006091 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SR +CYDEV_USB_ARB_EP2_SR EQU 0x40006092 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_BASE +CYDEV_USB_ARB_RW2_BASE EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_SIZE +CYDEV_USB_ARB_RW2_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_WA +CYDEV_USB_ARB_RW2_WA EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_WA_MSB +CYDEV_USB_ARB_RW2_WA_MSB EQU 0x40006095 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_RA +CYDEV_USB_ARB_RW2_RA EQU 0x40006096 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_RA_MSB +CYDEV_USB_ARB_RW2_RA_MSB EQU 0x40006097 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_DR +CYDEV_USB_ARB_RW2_DR EQU 0x40006098 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_CFG +CYDEV_USB_ARB_CFG EQU 0x4000609c + ENDIF + IF :LNOT::DEF:CYDEV_USB_USB_CLK_EN +CYDEV_USB_USB_CLK_EN EQU 0x4000609d + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_INT_EN +CYDEV_USB_ARB_INT_EN EQU 0x4000609e + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_INT_SR +CYDEV_USB_ARB_INT_SR EQU 0x4000609f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_BASE +CYDEV_USB_ARB_EP3_BASE EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SIZE +CYDEV_USB_ARB_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_CFG +CYDEV_USB_ARB_EP3_CFG EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_INT_EN +CYDEV_USB_ARB_EP3_INT_EN EQU 0x400060a1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SR +CYDEV_USB_ARB_EP3_SR EQU 0x400060a2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_BASE +CYDEV_USB_ARB_RW3_BASE EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_SIZE +CYDEV_USB_ARB_RW3_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_WA +CYDEV_USB_ARB_RW3_WA EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_WA_MSB +CYDEV_USB_ARB_RW3_WA_MSB EQU 0x400060a5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_RA +CYDEV_USB_ARB_RW3_RA EQU 0x400060a6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_RA_MSB +CYDEV_USB_ARB_RW3_RA_MSB EQU 0x400060a7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_DR +CYDEV_USB_ARB_RW3_DR EQU 0x400060a8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_CWA +CYDEV_USB_CWA EQU 0x400060ac + ENDIF + IF :LNOT::DEF:CYDEV_USB_CWA_MSB +CYDEV_USB_CWA_MSB EQU 0x400060ad + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_BASE +CYDEV_USB_ARB_EP4_BASE EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SIZE +CYDEV_USB_ARB_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_CFG +CYDEV_USB_ARB_EP4_CFG EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_INT_EN +CYDEV_USB_ARB_EP4_INT_EN EQU 0x400060b1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SR +CYDEV_USB_ARB_EP4_SR EQU 0x400060b2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_BASE +CYDEV_USB_ARB_RW4_BASE EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_SIZE +CYDEV_USB_ARB_RW4_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_WA +CYDEV_USB_ARB_RW4_WA EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_WA_MSB +CYDEV_USB_ARB_RW4_WA_MSB EQU 0x400060b5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_RA +CYDEV_USB_ARB_RW4_RA EQU 0x400060b6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_RA_MSB +CYDEV_USB_ARB_RW4_RA_MSB EQU 0x400060b7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_DR +CYDEV_USB_ARB_RW4_DR EQU 0x400060b8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_DMA_THRES +CYDEV_USB_DMA_THRES EQU 0x400060bc + ENDIF + IF :LNOT::DEF:CYDEV_USB_DMA_THRES_MSB +CYDEV_USB_DMA_THRES_MSB EQU 0x400060bd + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_BASE +CYDEV_USB_ARB_EP5_BASE EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SIZE +CYDEV_USB_ARB_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_CFG +CYDEV_USB_ARB_EP5_CFG EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_INT_EN +CYDEV_USB_ARB_EP5_INT_EN EQU 0x400060c1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SR +CYDEV_USB_ARB_EP5_SR EQU 0x400060c2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_BASE +CYDEV_USB_ARB_RW5_BASE EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_SIZE +CYDEV_USB_ARB_RW5_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_WA +CYDEV_USB_ARB_RW5_WA EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_WA_MSB +CYDEV_USB_ARB_RW5_WA_MSB EQU 0x400060c5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_RA +CYDEV_USB_ARB_RW5_RA EQU 0x400060c6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_RA_MSB +CYDEV_USB_ARB_RW5_RA_MSB EQU 0x400060c7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_DR +CYDEV_USB_ARB_RW5_DR EQU 0x400060c8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BUS_RST_CNT +CYDEV_USB_BUS_RST_CNT EQU 0x400060cc + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_BASE +CYDEV_USB_ARB_EP6_BASE EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SIZE +CYDEV_USB_ARB_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_CFG +CYDEV_USB_ARB_EP6_CFG EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_INT_EN +CYDEV_USB_ARB_EP6_INT_EN EQU 0x400060d1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SR +CYDEV_USB_ARB_EP6_SR EQU 0x400060d2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_BASE +CYDEV_USB_ARB_RW6_BASE EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_SIZE +CYDEV_USB_ARB_RW6_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_WA +CYDEV_USB_ARB_RW6_WA EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_WA_MSB +CYDEV_USB_ARB_RW6_WA_MSB EQU 0x400060d5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_RA +CYDEV_USB_ARB_RW6_RA EQU 0x400060d6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_RA_MSB +CYDEV_USB_ARB_RW6_RA_MSB EQU 0x400060d7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_DR +CYDEV_USB_ARB_RW6_DR EQU 0x400060d8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_BASE +CYDEV_USB_ARB_EP7_BASE EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SIZE +CYDEV_USB_ARB_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_CFG +CYDEV_USB_ARB_EP7_CFG EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_INT_EN +CYDEV_USB_ARB_EP7_INT_EN EQU 0x400060e1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SR +CYDEV_USB_ARB_EP7_SR EQU 0x400060e2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_BASE +CYDEV_USB_ARB_RW7_BASE EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_SIZE +CYDEV_USB_ARB_RW7_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_WA +CYDEV_USB_ARB_RW7_WA EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_WA_MSB +CYDEV_USB_ARB_RW7_WA_MSB EQU 0x400060e5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_RA +CYDEV_USB_ARB_RW7_RA EQU 0x400060e6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_RA_MSB +CYDEV_USB_ARB_RW7_RA_MSB EQU 0x400060e7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_DR +CYDEV_USB_ARB_RW7_DR EQU 0x400060e8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_BASE +CYDEV_USB_ARB_EP8_BASE EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SIZE +CYDEV_USB_ARB_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_CFG +CYDEV_USB_ARB_EP8_CFG EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_INT_EN +CYDEV_USB_ARB_EP8_INT_EN EQU 0x400060f1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SR +CYDEV_USB_ARB_EP8_SR EQU 0x400060f2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_BASE +CYDEV_USB_ARB_RW8_BASE EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_SIZE +CYDEV_USB_ARB_RW8_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_WA +CYDEV_USB_ARB_RW8_WA EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_WA_MSB +CYDEV_USB_ARB_RW8_WA_MSB EQU 0x400060f5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_RA +CYDEV_USB_ARB_RW8_RA EQU 0x400060f6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_RA_MSB +CYDEV_USB_ARB_RW8_RA_MSB EQU 0x400060f7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_DR +CYDEV_USB_ARB_RW8_DR EQU 0x400060f8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_BASE +CYDEV_USB_MEM_BASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_SIZE +CYDEV_USB_MEM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_DATA_MBASE +CYDEV_USB_MEM_DATA_MBASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_DATA_MSIZE +CYDEV_USB_MEM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_BASE +CYDEV_UWRK_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_SIZE +CYDEV_UWRK_SIZE EQU 0x00000b60 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_BASE +CYDEV_UWRK_UWRK8_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_SIZE +CYDEV_UWRK_UWRK8_SIZE EQU 0x000003b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_BASE +CYDEV_UWRK_UWRK8_B0_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_SIZE +CYDEV_UWRK_UWRK8_B0_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_A0 +CYDEV_UWRK_UWRK8_B0_UDB00_A0 EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_A0 +CYDEV_UWRK_UWRK8_B0_UDB01_A0 EQU 0x40006401 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_A0 +CYDEV_UWRK_UWRK8_B0_UDB02_A0 EQU 0x40006402 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_A0 +CYDEV_UWRK_UWRK8_B0_UDB03_A0 EQU 0x40006403 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_A0 +CYDEV_UWRK_UWRK8_B0_UDB04_A0 EQU 0x40006404 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_A0 +CYDEV_UWRK_UWRK8_B0_UDB05_A0 EQU 0x40006405 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_A0 +CYDEV_UWRK_UWRK8_B0_UDB06_A0 EQU 0x40006406 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_A0 +CYDEV_UWRK_UWRK8_B0_UDB07_A0 EQU 0x40006407 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_A0 +CYDEV_UWRK_UWRK8_B0_UDB08_A0 EQU 0x40006408 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_A0 +CYDEV_UWRK_UWRK8_B0_UDB09_A0 EQU 0x40006409 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_A0 +CYDEV_UWRK_UWRK8_B0_UDB10_A0 EQU 0x4000640a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_A0 +CYDEV_UWRK_UWRK8_B0_UDB11_A0 EQU 0x4000640b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_A0 +CYDEV_UWRK_UWRK8_B0_UDB12_A0 EQU 0x4000640c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_A0 +CYDEV_UWRK_UWRK8_B0_UDB13_A0 EQU 0x4000640d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_A0 +CYDEV_UWRK_UWRK8_B0_UDB14_A0 EQU 0x4000640e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_A0 +CYDEV_UWRK_UWRK8_B0_UDB15_A0 EQU 0x4000640f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_A1 +CYDEV_UWRK_UWRK8_B0_UDB00_A1 EQU 0x40006410 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_A1 +CYDEV_UWRK_UWRK8_B0_UDB01_A1 EQU 0x40006411 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_A1 +CYDEV_UWRK_UWRK8_B0_UDB02_A1 EQU 0x40006412 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_A1 +CYDEV_UWRK_UWRK8_B0_UDB03_A1 EQU 0x40006413 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_A1 +CYDEV_UWRK_UWRK8_B0_UDB04_A1 EQU 0x40006414 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_A1 +CYDEV_UWRK_UWRK8_B0_UDB05_A1 EQU 0x40006415 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_A1 +CYDEV_UWRK_UWRK8_B0_UDB06_A1 EQU 0x40006416 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_A1 +CYDEV_UWRK_UWRK8_B0_UDB07_A1 EQU 0x40006417 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_A1 +CYDEV_UWRK_UWRK8_B0_UDB08_A1 EQU 0x40006418 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_A1 +CYDEV_UWRK_UWRK8_B0_UDB09_A1 EQU 0x40006419 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_A1 +CYDEV_UWRK_UWRK8_B0_UDB10_A1 EQU 0x4000641a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_A1 +CYDEV_UWRK_UWRK8_B0_UDB11_A1 EQU 0x4000641b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_A1 +CYDEV_UWRK_UWRK8_B0_UDB12_A1 EQU 0x4000641c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_A1 +CYDEV_UWRK_UWRK8_B0_UDB13_A1 EQU 0x4000641d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_A1 +CYDEV_UWRK_UWRK8_B0_UDB14_A1 EQU 0x4000641e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_A1 +CYDEV_UWRK_UWRK8_B0_UDB15_A1 EQU 0x4000641f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_D0 +CYDEV_UWRK_UWRK8_B0_UDB00_D0 EQU 0x40006420 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_D0 +CYDEV_UWRK_UWRK8_B0_UDB01_D0 EQU 0x40006421 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_D0 +CYDEV_UWRK_UWRK8_B0_UDB02_D0 EQU 0x40006422 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_D0 +CYDEV_UWRK_UWRK8_B0_UDB03_D0 EQU 0x40006423 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_D0 +CYDEV_UWRK_UWRK8_B0_UDB04_D0 EQU 0x40006424 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_D0 +CYDEV_UWRK_UWRK8_B0_UDB05_D0 EQU 0x40006425 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_D0 +CYDEV_UWRK_UWRK8_B0_UDB06_D0 EQU 0x40006426 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_D0 +CYDEV_UWRK_UWRK8_B0_UDB07_D0 EQU 0x40006427 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_D0 +CYDEV_UWRK_UWRK8_B0_UDB08_D0 EQU 0x40006428 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_D0 +CYDEV_UWRK_UWRK8_B0_UDB09_D0 EQU 0x40006429 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_D0 +CYDEV_UWRK_UWRK8_B0_UDB10_D0 EQU 0x4000642a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_D0 +CYDEV_UWRK_UWRK8_B0_UDB11_D0 EQU 0x4000642b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_D0 +CYDEV_UWRK_UWRK8_B0_UDB12_D0 EQU 0x4000642c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_D0 +CYDEV_UWRK_UWRK8_B0_UDB13_D0 EQU 0x4000642d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_D0 +CYDEV_UWRK_UWRK8_B0_UDB14_D0 EQU 0x4000642e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_D0 +CYDEV_UWRK_UWRK8_B0_UDB15_D0 EQU 0x4000642f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_D1 +CYDEV_UWRK_UWRK8_B0_UDB00_D1 EQU 0x40006430 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_D1 +CYDEV_UWRK_UWRK8_B0_UDB01_D1 EQU 0x40006431 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_D1 +CYDEV_UWRK_UWRK8_B0_UDB02_D1 EQU 0x40006432 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_D1 +CYDEV_UWRK_UWRK8_B0_UDB03_D1 EQU 0x40006433 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_D1 +CYDEV_UWRK_UWRK8_B0_UDB04_D1 EQU 0x40006434 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_D1 +CYDEV_UWRK_UWRK8_B0_UDB05_D1 EQU 0x40006435 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_D1 +CYDEV_UWRK_UWRK8_B0_UDB06_D1 EQU 0x40006436 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_D1 +CYDEV_UWRK_UWRK8_B0_UDB07_D1 EQU 0x40006437 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_D1 +CYDEV_UWRK_UWRK8_B0_UDB08_D1 EQU 0x40006438 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_D1 +CYDEV_UWRK_UWRK8_B0_UDB09_D1 EQU 0x40006439 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_D1 +CYDEV_UWRK_UWRK8_B0_UDB10_D1 EQU 0x4000643a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_D1 +CYDEV_UWRK_UWRK8_B0_UDB11_D1 EQU 0x4000643b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_D1 +CYDEV_UWRK_UWRK8_B0_UDB12_D1 EQU 0x4000643c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_D1 +CYDEV_UWRK_UWRK8_B0_UDB13_D1 EQU 0x4000643d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_D1 +CYDEV_UWRK_UWRK8_B0_UDB14_D1 EQU 0x4000643e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_D1 +CYDEV_UWRK_UWRK8_B0_UDB15_D1 EQU 0x4000643f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_F0 +CYDEV_UWRK_UWRK8_B0_UDB00_F0 EQU 0x40006440 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_F0 +CYDEV_UWRK_UWRK8_B0_UDB01_F0 EQU 0x40006441 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_F0 +CYDEV_UWRK_UWRK8_B0_UDB02_F0 EQU 0x40006442 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_F0 +CYDEV_UWRK_UWRK8_B0_UDB03_F0 EQU 0x40006443 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_F0 +CYDEV_UWRK_UWRK8_B0_UDB04_F0 EQU 0x40006444 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_F0 +CYDEV_UWRK_UWRK8_B0_UDB05_F0 EQU 0x40006445 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_F0 +CYDEV_UWRK_UWRK8_B0_UDB06_F0 EQU 0x40006446 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_F0 +CYDEV_UWRK_UWRK8_B0_UDB07_F0 EQU 0x40006447 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_F0 +CYDEV_UWRK_UWRK8_B0_UDB08_F0 EQU 0x40006448 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_F0 +CYDEV_UWRK_UWRK8_B0_UDB09_F0 EQU 0x40006449 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_F0 +CYDEV_UWRK_UWRK8_B0_UDB10_F0 EQU 0x4000644a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_F0 +CYDEV_UWRK_UWRK8_B0_UDB11_F0 EQU 0x4000644b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_F0 +CYDEV_UWRK_UWRK8_B0_UDB12_F0 EQU 0x4000644c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_F0 +CYDEV_UWRK_UWRK8_B0_UDB13_F0 EQU 0x4000644d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_F0 +CYDEV_UWRK_UWRK8_B0_UDB14_F0 EQU 0x4000644e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_F0 +CYDEV_UWRK_UWRK8_B0_UDB15_F0 EQU 0x4000644f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_F1 +CYDEV_UWRK_UWRK8_B0_UDB00_F1 EQU 0x40006450 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_F1 +CYDEV_UWRK_UWRK8_B0_UDB01_F1 EQU 0x40006451 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_F1 +CYDEV_UWRK_UWRK8_B0_UDB02_F1 EQU 0x40006452 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_F1 +CYDEV_UWRK_UWRK8_B0_UDB03_F1 EQU 0x40006453 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_F1 +CYDEV_UWRK_UWRK8_B0_UDB04_F1 EQU 0x40006454 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_F1 +CYDEV_UWRK_UWRK8_B0_UDB05_F1 EQU 0x40006455 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_F1 +CYDEV_UWRK_UWRK8_B0_UDB06_F1 EQU 0x40006456 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_F1 +CYDEV_UWRK_UWRK8_B0_UDB07_F1 EQU 0x40006457 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_F1 +CYDEV_UWRK_UWRK8_B0_UDB08_F1 EQU 0x40006458 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_F1 +CYDEV_UWRK_UWRK8_B0_UDB09_F1 EQU 0x40006459 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_F1 +CYDEV_UWRK_UWRK8_B0_UDB10_F1 EQU 0x4000645a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_F1 +CYDEV_UWRK_UWRK8_B0_UDB11_F1 EQU 0x4000645b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_F1 +CYDEV_UWRK_UWRK8_B0_UDB12_F1 EQU 0x4000645c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_F1 +CYDEV_UWRK_UWRK8_B0_UDB13_F1 EQU 0x4000645d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_F1 +CYDEV_UWRK_UWRK8_B0_UDB14_F1 EQU 0x4000645e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_F1 +CYDEV_UWRK_UWRK8_B0_UDB15_F1 EQU 0x4000645f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_ST +CYDEV_UWRK_UWRK8_B0_UDB00_ST EQU 0x40006460 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_ST +CYDEV_UWRK_UWRK8_B0_UDB01_ST EQU 0x40006461 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_ST +CYDEV_UWRK_UWRK8_B0_UDB02_ST EQU 0x40006462 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_ST +CYDEV_UWRK_UWRK8_B0_UDB03_ST EQU 0x40006463 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_ST +CYDEV_UWRK_UWRK8_B0_UDB04_ST EQU 0x40006464 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_ST +CYDEV_UWRK_UWRK8_B0_UDB05_ST EQU 0x40006465 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_ST +CYDEV_UWRK_UWRK8_B0_UDB06_ST EQU 0x40006466 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_ST +CYDEV_UWRK_UWRK8_B0_UDB07_ST EQU 0x40006467 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_ST +CYDEV_UWRK_UWRK8_B0_UDB08_ST EQU 0x40006468 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_ST +CYDEV_UWRK_UWRK8_B0_UDB09_ST EQU 0x40006469 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_ST +CYDEV_UWRK_UWRK8_B0_UDB10_ST EQU 0x4000646a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_ST +CYDEV_UWRK_UWRK8_B0_UDB11_ST EQU 0x4000646b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_ST +CYDEV_UWRK_UWRK8_B0_UDB12_ST EQU 0x4000646c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_ST +CYDEV_UWRK_UWRK8_B0_UDB13_ST EQU 0x4000646d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_ST +CYDEV_UWRK_UWRK8_B0_UDB14_ST EQU 0x4000646e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_ST +CYDEV_UWRK_UWRK8_B0_UDB15_ST EQU 0x4000646f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_CTL +CYDEV_UWRK_UWRK8_B0_UDB00_CTL EQU 0x40006470 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_CTL +CYDEV_UWRK_UWRK8_B0_UDB01_CTL EQU 0x40006471 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_CTL +CYDEV_UWRK_UWRK8_B0_UDB02_CTL EQU 0x40006472 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_CTL +CYDEV_UWRK_UWRK8_B0_UDB03_CTL EQU 0x40006473 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_CTL +CYDEV_UWRK_UWRK8_B0_UDB04_CTL EQU 0x40006474 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_CTL +CYDEV_UWRK_UWRK8_B0_UDB05_CTL EQU 0x40006475 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_CTL +CYDEV_UWRK_UWRK8_B0_UDB06_CTL EQU 0x40006476 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_CTL +CYDEV_UWRK_UWRK8_B0_UDB07_CTL EQU 0x40006477 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_CTL +CYDEV_UWRK_UWRK8_B0_UDB08_CTL EQU 0x40006478 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_CTL +CYDEV_UWRK_UWRK8_B0_UDB09_CTL EQU 0x40006479 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_CTL +CYDEV_UWRK_UWRK8_B0_UDB10_CTL EQU 0x4000647a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_CTL +CYDEV_UWRK_UWRK8_B0_UDB11_CTL EQU 0x4000647b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_CTL +CYDEV_UWRK_UWRK8_B0_UDB12_CTL EQU 0x4000647c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_CTL +CYDEV_UWRK_UWRK8_B0_UDB13_CTL EQU 0x4000647d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_CTL +CYDEV_UWRK_UWRK8_B0_UDB14_CTL EQU 0x4000647e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_CTL +CYDEV_UWRK_UWRK8_B0_UDB15_CTL EQU 0x4000647f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_MSK +CYDEV_UWRK_UWRK8_B0_UDB00_MSK EQU 0x40006480 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_MSK +CYDEV_UWRK_UWRK8_B0_UDB01_MSK EQU 0x40006481 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_MSK +CYDEV_UWRK_UWRK8_B0_UDB02_MSK EQU 0x40006482 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_MSK +CYDEV_UWRK_UWRK8_B0_UDB03_MSK EQU 0x40006483 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_MSK +CYDEV_UWRK_UWRK8_B0_UDB04_MSK EQU 0x40006484 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_MSK +CYDEV_UWRK_UWRK8_B0_UDB05_MSK EQU 0x40006485 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_MSK +CYDEV_UWRK_UWRK8_B0_UDB06_MSK EQU 0x40006486 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_MSK +CYDEV_UWRK_UWRK8_B0_UDB07_MSK EQU 0x40006487 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_MSK +CYDEV_UWRK_UWRK8_B0_UDB08_MSK EQU 0x40006488 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_MSK +CYDEV_UWRK_UWRK8_B0_UDB09_MSK EQU 0x40006489 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_MSK +CYDEV_UWRK_UWRK8_B0_UDB10_MSK EQU 0x4000648a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_MSK +CYDEV_UWRK_UWRK8_B0_UDB11_MSK EQU 0x4000648b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_MSK +CYDEV_UWRK_UWRK8_B0_UDB12_MSK EQU 0x4000648c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_MSK +CYDEV_UWRK_UWRK8_B0_UDB13_MSK EQU 0x4000648d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_MSK +CYDEV_UWRK_UWRK8_B0_UDB14_MSK EQU 0x4000648e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_MSK +CYDEV_UWRK_UWRK8_B0_UDB15_MSK EQU 0x4000648f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_ACTL +CYDEV_UWRK_UWRK8_B0_UDB00_ACTL EQU 0x40006490 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_ACTL +CYDEV_UWRK_UWRK8_B0_UDB01_ACTL EQU 0x40006491 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_ACTL +CYDEV_UWRK_UWRK8_B0_UDB02_ACTL EQU 0x40006492 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_ACTL +CYDEV_UWRK_UWRK8_B0_UDB03_ACTL EQU 0x40006493 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_ACTL +CYDEV_UWRK_UWRK8_B0_UDB04_ACTL EQU 0x40006494 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_ACTL +CYDEV_UWRK_UWRK8_B0_UDB05_ACTL EQU 0x40006495 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_ACTL +CYDEV_UWRK_UWRK8_B0_UDB06_ACTL EQU 0x40006496 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_ACTL +CYDEV_UWRK_UWRK8_B0_UDB07_ACTL EQU 0x40006497 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_ACTL +CYDEV_UWRK_UWRK8_B0_UDB08_ACTL EQU 0x40006498 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_ACTL +CYDEV_UWRK_UWRK8_B0_UDB09_ACTL EQU 0x40006499 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_ACTL +CYDEV_UWRK_UWRK8_B0_UDB10_ACTL EQU 0x4000649a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_ACTL +CYDEV_UWRK_UWRK8_B0_UDB11_ACTL EQU 0x4000649b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_ACTL +CYDEV_UWRK_UWRK8_B0_UDB12_ACTL EQU 0x4000649c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_ACTL +CYDEV_UWRK_UWRK8_B0_UDB13_ACTL EQU 0x4000649d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_ACTL +CYDEV_UWRK_UWRK8_B0_UDB14_ACTL EQU 0x4000649e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_ACTL +CYDEV_UWRK_UWRK8_B0_UDB15_ACTL EQU 0x4000649f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_MC +CYDEV_UWRK_UWRK8_B0_UDB00_MC EQU 0x400064a0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_MC +CYDEV_UWRK_UWRK8_B0_UDB01_MC EQU 0x400064a1 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_MC +CYDEV_UWRK_UWRK8_B0_UDB02_MC EQU 0x400064a2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_MC +CYDEV_UWRK_UWRK8_B0_UDB03_MC EQU 0x400064a3 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_MC +CYDEV_UWRK_UWRK8_B0_UDB04_MC EQU 0x400064a4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_MC +CYDEV_UWRK_UWRK8_B0_UDB05_MC EQU 0x400064a5 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_MC +CYDEV_UWRK_UWRK8_B0_UDB06_MC EQU 0x400064a6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_MC +CYDEV_UWRK_UWRK8_B0_UDB07_MC EQU 0x400064a7 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_MC +CYDEV_UWRK_UWRK8_B0_UDB08_MC EQU 0x400064a8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_MC +CYDEV_UWRK_UWRK8_B0_UDB09_MC EQU 0x400064a9 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_MC +CYDEV_UWRK_UWRK8_B0_UDB10_MC EQU 0x400064aa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_MC +CYDEV_UWRK_UWRK8_B0_UDB11_MC EQU 0x400064ab + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_MC +CYDEV_UWRK_UWRK8_B0_UDB12_MC EQU 0x400064ac + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_MC +CYDEV_UWRK_UWRK8_B0_UDB13_MC EQU 0x400064ad + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_MC +CYDEV_UWRK_UWRK8_B0_UDB14_MC EQU 0x400064ae + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_MC +CYDEV_UWRK_UWRK8_B0_UDB15_MC EQU 0x400064af + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_BASE +CYDEV_UWRK_UWRK8_B1_BASE EQU 0x40006500 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_SIZE +CYDEV_UWRK_UWRK8_B1_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_A0 +CYDEV_UWRK_UWRK8_B1_UDB04_A0 EQU 0x40006504 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_A0 +CYDEV_UWRK_UWRK8_B1_UDB05_A0 EQU 0x40006505 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_A0 +CYDEV_UWRK_UWRK8_B1_UDB06_A0 EQU 0x40006506 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_A0 +CYDEV_UWRK_UWRK8_B1_UDB07_A0 EQU 0x40006507 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_A0 +CYDEV_UWRK_UWRK8_B1_UDB08_A0 EQU 0x40006508 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_A0 +CYDEV_UWRK_UWRK8_B1_UDB09_A0 EQU 0x40006509 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_A0 +CYDEV_UWRK_UWRK8_B1_UDB10_A0 EQU 0x4000650a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_A0 +CYDEV_UWRK_UWRK8_B1_UDB11_A0 EQU 0x4000650b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_A1 +CYDEV_UWRK_UWRK8_B1_UDB04_A1 EQU 0x40006514 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_A1 +CYDEV_UWRK_UWRK8_B1_UDB05_A1 EQU 0x40006515 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_A1 +CYDEV_UWRK_UWRK8_B1_UDB06_A1 EQU 0x40006516 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_A1 +CYDEV_UWRK_UWRK8_B1_UDB07_A1 EQU 0x40006517 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_A1 +CYDEV_UWRK_UWRK8_B1_UDB08_A1 EQU 0x40006518 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_A1 +CYDEV_UWRK_UWRK8_B1_UDB09_A1 EQU 0x40006519 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_A1 +CYDEV_UWRK_UWRK8_B1_UDB10_A1 EQU 0x4000651a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_A1 +CYDEV_UWRK_UWRK8_B1_UDB11_A1 EQU 0x4000651b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_D0 +CYDEV_UWRK_UWRK8_B1_UDB04_D0 EQU 0x40006524 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_D0 +CYDEV_UWRK_UWRK8_B1_UDB05_D0 EQU 0x40006525 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_D0 +CYDEV_UWRK_UWRK8_B1_UDB06_D0 EQU 0x40006526 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_D0 +CYDEV_UWRK_UWRK8_B1_UDB07_D0 EQU 0x40006527 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_D0 +CYDEV_UWRK_UWRK8_B1_UDB08_D0 EQU 0x40006528 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_D0 +CYDEV_UWRK_UWRK8_B1_UDB09_D0 EQU 0x40006529 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_D0 +CYDEV_UWRK_UWRK8_B1_UDB10_D0 EQU 0x4000652a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_D0 +CYDEV_UWRK_UWRK8_B1_UDB11_D0 EQU 0x4000652b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_D1 +CYDEV_UWRK_UWRK8_B1_UDB04_D1 EQU 0x40006534 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_D1 +CYDEV_UWRK_UWRK8_B1_UDB05_D1 EQU 0x40006535 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_D1 +CYDEV_UWRK_UWRK8_B1_UDB06_D1 EQU 0x40006536 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_D1 +CYDEV_UWRK_UWRK8_B1_UDB07_D1 EQU 0x40006537 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_D1 +CYDEV_UWRK_UWRK8_B1_UDB08_D1 EQU 0x40006538 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_D1 +CYDEV_UWRK_UWRK8_B1_UDB09_D1 EQU 0x40006539 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_D1 +CYDEV_UWRK_UWRK8_B1_UDB10_D1 EQU 0x4000653a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_D1 +CYDEV_UWRK_UWRK8_B1_UDB11_D1 EQU 0x4000653b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_F0 +CYDEV_UWRK_UWRK8_B1_UDB04_F0 EQU 0x40006544 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_F0 +CYDEV_UWRK_UWRK8_B1_UDB05_F0 EQU 0x40006545 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_F0 +CYDEV_UWRK_UWRK8_B1_UDB06_F0 EQU 0x40006546 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_F0 +CYDEV_UWRK_UWRK8_B1_UDB07_F0 EQU 0x40006547 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_F0 +CYDEV_UWRK_UWRK8_B1_UDB08_F0 EQU 0x40006548 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_F0 +CYDEV_UWRK_UWRK8_B1_UDB09_F0 EQU 0x40006549 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_F0 +CYDEV_UWRK_UWRK8_B1_UDB10_F0 EQU 0x4000654a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_F0 +CYDEV_UWRK_UWRK8_B1_UDB11_F0 EQU 0x4000654b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_F1 +CYDEV_UWRK_UWRK8_B1_UDB04_F1 EQU 0x40006554 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_F1 +CYDEV_UWRK_UWRK8_B1_UDB05_F1 EQU 0x40006555 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_F1 +CYDEV_UWRK_UWRK8_B1_UDB06_F1 EQU 0x40006556 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_F1 +CYDEV_UWRK_UWRK8_B1_UDB07_F1 EQU 0x40006557 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_F1 +CYDEV_UWRK_UWRK8_B1_UDB08_F1 EQU 0x40006558 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_F1 +CYDEV_UWRK_UWRK8_B1_UDB09_F1 EQU 0x40006559 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_F1 +CYDEV_UWRK_UWRK8_B1_UDB10_F1 EQU 0x4000655a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_F1 +CYDEV_UWRK_UWRK8_B1_UDB11_F1 EQU 0x4000655b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_ST +CYDEV_UWRK_UWRK8_B1_UDB04_ST EQU 0x40006564 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_ST +CYDEV_UWRK_UWRK8_B1_UDB05_ST EQU 0x40006565 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_ST +CYDEV_UWRK_UWRK8_B1_UDB06_ST EQU 0x40006566 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_ST +CYDEV_UWRK_UWRK8_B1_UDB07_ST EQU 0x40006567 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_ST +CYDEV_UWRK_UWRK8_B1_UDB08_ST EQU 0x40006568 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_ST +CYDEV_UWRK_UWRK8_B1_UDB09_ST EQU 0x40006569 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_ST +CYDEV_UWRK_UWRK8_B1_UDB10_ST EQU 0x4000656a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_ST +CYDEV_UWRK_UWRK8_B1_UDB11_ST EQU 0x4000656b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_CTL +CYDEV_UWRK_UWRK8_B1_UDB04_CTL EQU 0x40006574 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_CTL +CYDEV_UWRK_UWRK8_B1_UDB05_CTL EQU 0x40006575 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_CTL +CYDEV_UWRK_UWRK8_B1_UDB06_CTL EQU 0x40006576 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_CTL +CYDEV_UWRK_UWRK8_B1_UDB07_CTL EQU 0x40006577 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_CTL +CYDEV_UWRK_UWRK8_B1_UDB08_CTL EQU 0x40006578 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_CTL +CYDEV_UWRK_UWRK8_B1_UDB09_CTL EQU 0x40006579 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_CTL +CYDEV_UWRK_UWRK8_B1_UDB10_CTL EQU 0x4000657a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_CTL +CYDEV_UWRK_UWRK8_B1_UDB11_CTL EQU 0x4000657b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_MSK +CYDEV_UWRK_UWRK8_B1_UDB04_MSK EQU 0x40006584 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_MSK +CYDEV_UWRK_UWRK8_B1_UDB05_MSK EQU 0x40006585 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_MSK +CYDEV_UWRK_UWRK8_B1_UDB06_MSK EQU 0x40006586 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_MSK +CYDEV_UWRK_UWRK8_B1_UDB07_MSK EQU 0x40006587 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_MSK +CYDEV_UWRK_UWRK8_B1_UDB08_MSK EQU 0x40006588 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_MSK +CYDEV_UWRK_UWRK8_B1_UDB09_MSK EQU 0x40006589 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_MSK +CYDEV_UWRK_UWRK8_B1_UDB10_MSK EQU 0x4000658a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_MSK +CYDEV_UWRK_UWRK8_B1_UDB11_MSK EQU 0x4000658b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_ACTL +CYDEV_UWRK_UWRK8_B1_UDB04_ACTL EQU 0x40006594 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_ACTL +CYDEV_UWRK_UWRK8_B1_UDB05_ACTL EQU 0x40006595 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_ACTL +CYDEV_UWRK_UWRK8_B1_UDB06_ACTL EQU 0x40006596 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_ACTL +CYDEV_UWRK_UWRK8_B1_UDB07_ACTL EQU 0x40006597 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_ACTL +CYDEV_UWRK_UWRK8_B1_UDB08_ACTL EQU 0x40006598 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_ACTL +CYDEV_UWRK_UWRK8_B1_UDB09_ACTL EQU 0x40006599 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_ACTL +CYDEV_UWRK_UWRK8_B1_UDB10_ACTL EQU 0x4000659a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_ACTL +CYDEV_UWRK_UWRK8_B1_UDB11_ACTL EQU 0x4000659b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_MC +CYDEV_UWRK_UWRK8_B1_UDB04_MC EQU 0x400065a4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_MC +CYDEV_UWRK_UWRK8_B1_UDB05_MC EQU 0x400065a5 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_MC +CYDEV_UWRK_UWRK8_B1_UDB06_MC EQU 0x400065a6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_MC +CYDEV_UWRK_UWRK8_B1_UDB07_MC EQU 0x400065a7 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_MC +CYDEV_UWRK_UWRK8_B1_UDB08_MC EQU 0x400065a8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_MC +CYDEV_UWRK_UWRK8_B1_UDB09_MC EQU 0x400065a9 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_MC +CYDEV_UWRK_UWRK8_B1_UDB10_MC EQU 0x400065aa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_MC +CYDEV_UWRK_UWRK8_B1_UDB11_MC EQU 0x400065ab + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_BASE +CYDEV_UWRK_UWRK16_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_SIZE +CYDEV_UWRK_UWRK16_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_BASE +CYDEV_UWRK_UWRK16_CAT_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_SIZE +CYDEV_UWRK_UWRK16_CAT_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_BASE +CYDEV_UWRK_UWRK16_CAT_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_SIZE +CYDEV_UWRK_UWRK16_CAT_B0_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 EQU 0x4000681e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 EQU 0x4000685e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 EQU 0x4000689e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL EQU 0x400068de + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL EQU 0x4000691e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 EQU 0x4000695e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_BASE +CYDEV_UWRK_UWRK16_CAT_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_SIZE +CYDEV_UWRK_UWRK16_CAT_B1_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_BASE +CYDEV_UWRK_UWRK16_DEF_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_SIZE +CYDEV_UWRK_UWRK16_DEF_SIZE EQU 0x0000075e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_BASE +CYDEV_UWRK_UWRK16_DEF_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_SIZE +CYDEV_UWRK_UWRK16_DEF_B0_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 EQU 0x40006820 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 EQU 0x40006822 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 EQU 0x40006824 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 EQU 0x40006826 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 EQU 0x40006828 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 EQU 0x4000682a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 EQU 0x4000682c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 EQU 0x4000682e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 EQU 0x40006830 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 EQU 0x40006832 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 EQU 0x40006834 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 EQU 0x40006836 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 EQU 0x40006838 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 EQU 0x4000683a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 EQU 0x4000683c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 EQU 0x40006860 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 EQU 0x40006862 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 EQU 0x40006864 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 EQU 0x40006866 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 EQU 0x40006868 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 EQU 0x4000686a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 EQU 0x4000686c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 EQU 0x4000686e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 EQU 0x40006870 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 EQU 0x40006872 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 EQU 0x40006874 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 EQU 0x40006876 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 EQU 0x40006878 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 EQU 0x4000687a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 EQU 0x4000687c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 EQU 0x400068a0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 EQU 0x400068a2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 EQU 0x400068a4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 EQU 0x400068a6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 EQU 0x400068a8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 EQU 0x400068aa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 EQU 0x400068ac + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 EQU 0x400068ae + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 EQU 0x400068b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 EQU 0x400068b2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 EQU 0x400068b4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 EQU 0x400068b6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 EQU 0x400068b8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 EQU 0x400068ba + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 EQU 0x400068bc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL EQU 0x400068e0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL EQU 0x400068e2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL EQU 0x400068e4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL EQU 0x400068e6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL EQU 0x400068e8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL EQU 0x400068ea + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL EQU 0x400068ec + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL EQU 0x400068ee + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL EQU 0x400068f0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL EQU 0x400068f2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL EQU 0x400068f4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL EQU 0x400068f6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL EQU 0x400068f8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL EQU 0x400068fa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL EQU 0x400068fc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL EQU 0x40006920 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL EQU 0x40006922 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL EQU 0x40006924 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL EQU 0x40006926 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL EQU 0x40006928 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL EQU 0x4000692a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL EQU 0x4000692c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL EQU 0x4000692e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL EQU 0x40006930 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL EQU 0x40006932 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL EQU 0x40006934 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL EQU 0x40006936 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL EQU 0x40006938 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL EQU 0x4000693a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL EQU 0x4000693c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_BASE +CYDEV_UWRK_UWRK16_DEF_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_SIZE +CYDEV_UWRK_UWRK16_DEF_B1_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 EQU 0x40006a28 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 EQU 0x40006a2a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 EQU 0x40006a2c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 EQU 0x40006a2e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 EQU 0x40006a30 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 EQU 0x40006a32 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 EQU 0x40006a34 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 EQU 0x40006a36 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 EQU 0x40006a68 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 EQU 0x40006a6a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 EQU 0x40006a6c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 EQU 0x40006a6e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 EQU 0x40006a70 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 EQU 0x40006a72 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 EQU 0x40006a74 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 EQU 0x40006a76 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 EQU 0x40006aa8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 EQU 0x40006aaa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 EQU 0x40006aac + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 EQU 0x40006aae + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 EQU 0x40006ab0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 EQU 0x40006ab2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 EQU 0x40006ab4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 EQU 0x40006ab6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL EQU 0x40006ae8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL EQU 0x40006aea + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL EQU 0x40006aec + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL EQU 0x40006aee + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL EQU 0x40006af0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL EQU 0x40006af2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL EQU 0x40006af4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL EQU 0x40006af6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL EQU 0x40006b28 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL EQU 0x40006b2a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL EQU 0x40006b2c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL EQU 0x40006b2e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL EQU 0x40006b30 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL EQU 0x40006b32 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL EQU 0x40006b34 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL EQU 0x40006b36 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_BASE +CYDEV_PHUB_BASE EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_SIZE +CYDEV_PHUB_SIZE EQU 0x00000c00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFG +CYDEV_PHUB_CFG EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_ERR +CYDEV_PHUB_ERR EQU 0x40007004 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_ERR_ADR +CYDEV_PHUB_ERR_ADR EQU 0x40007008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASE +CYDEV_PHUB_CH0_BASE EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_SIZE +CYDEV_PHUB_CH0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASIC_CFG +CYDEV_PHUB_CH0_BASIC_CFG EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_ACTION +CYDEV_PHUB_CH0_ACTION EQU 0x40007014 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASIC_STATUS +CYDEV_PHUB_CH0_BASIC_STATUS EQU 0x40007018 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASE +CYDEV_PHUB_CH1_BASE EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_SIZE +CYDEV_PHUB_CH1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASIC_CFG +CYDEV_PHUB_CH1_BASIC_CFG EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_ACTION +CYDEV_PHUB_CH1_ACTION EQU 0x40007024 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASIC_STATUS +CYDEV_PHUB_CH1_BASIC_STATUS EQU 0x40007028 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASE +CYDEV_PHUB_CH2_BASE EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_SIZE +CYDEV_PHUB_CH2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASIC_CFG +CYDEV_PHUB_CH2_BASIC_CFG EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_ACTION +CYDEV_PHUB_CH2_ACTION EQU 0x40007034 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASIC_STATUS +CYDEV_PHUB_CH2_BASIC_STATUS EQU 0x40007038 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASE +CYDEV_PHUB_CH3_BASE EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_SIZE +CYDEV_PHUB_CH3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASIC_CFG +CYDEV_PHUB_CH3_BASIC_CFG EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_ACTION +CYDEV_PHUB_CH3_ACTION EQU 0x40007044 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASIC_STATUS +CYDEV_PHUB_CH3_BASIC_STATUS EQU 0x40007048 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASE +CYDEV_PHUB_CH4_BASE EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_SIZE +CYDEV_PHUB_CH4_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASIC_CFG +CYDEV_PHUB_CH4_BASIC_CFG EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_ACTION +CYDEV_PHUB_CH4_ACTION EQU 0x40007054 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASIC_STATUS +CYDEV_PHUB_CH4_BASIC_STATUS EQU 0x40007058 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASE +CYDEV_PHUB_CH5_BASE EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_SIZE +CYDEV_PHUB_CH5_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASIC_CFG +CYDEV_PHUB_CH5_BASIC_CFG EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_ACTION +CYDEV_PHUB_CH5_ACTION EQU 0x40007064 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASIC_STATUS +CYDEV_PHUB_CH5_BASIC_STATUS EQU 0x40007068 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASE +CYDEV_PHUB_CH6_BASE EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_SIZE +CYDEV_PHUB_CH6_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASIC_CFG +CYDEV_PHUB_CH6_BASIC_CFG EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_ACTION +CYDEV_PHUB_CH6_ACTION EQU 0x40007074 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASIC_STATUS +CYDEV_PHUB_CH6_BASIC_STATUS EQU 0x40007078 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASE +CYDEV_PHUB_CH7_BASE EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_SIZE +CYDEV_PHUB_CH7_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASIC_CFG +CYDEV_PHUB_CH7_BASIC_CFG EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_ACTION +CYDEV_PHUB_CH7_ACTION EQU 0x40007084 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASIC_STATUS +CYDEV_PHUB_CH7_BASIC_STATUS EQU 0x40007088 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASE +CYDEV_PHUB_CH8_BASE EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_SIZE +CYDEV_PHUB_CH8_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASIC_CFG +CYDEV_PHUB_CH8_BASIC_CFG EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_ACTION +CYDEV_PHUB_CH8_ACTION EQU 0x40007094 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASIC_STATUS +CYDEV_PHUB_CH8_BASIC_STATUS EQU 0x40007098 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASE +CYDEV_PHUB_CH9_BASE EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_SIZE +CYDEV_PHUB_CH9_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASIC_CFG +CYDEV_PHUB_CH9_BASIC_CFG EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_ACTION +CYDEV_PHUB_CH9_ACTION EQU 0x400070a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASIC_STATUS +CYDEV_PHUB_CH9_BASIC_STATUS EQU 0x400070a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASE +CYDEV_PHUB_CH10_BASE EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_SIZE +CYDEV_PHUB_CH10_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASIC_CFG +CYDEV_PHUB_CH10_BASIC_CFG EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_ACTION +CYDEV_PHUB_CH10_ACTION EQU 0x400070b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASIC_STATUS +CYDEV_PHUB_CH10_BASIC_STATUS EQU 0x400070b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASE +CYDEV_PHUB_CH11_BASE EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_SIZE +CYDEV_PHUB_CH11_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASIC_CFG +CYDEV_PHUB_CH11_BASIC_CFG EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_ACTION +CYDEV_PHUB_CH11_ACTION EQU 0x400070c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASIC_STATUS +CYDEV_PHUB_CH11_BASIC_STATUS EQU 0x400070c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASE +CYDEV_PHUB_CH12_BASE EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_SIZE +CYDEV_PHUB_CH12_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASIC_CFG +CYDEV_PHUB_CH12_BASIC_CFG EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_ACTION +CYDEV_PHUB_CH12_ACTION EQU 0x400070d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASIC_STATUS +CYDEV_PHUB_CH12_BASIC_STATUS EQU 0x400070d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASE +CYDEV_PHUB_CH13_BASE EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_SIZE +CYDEV_PHUB_CH13_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASIC_CFG +CYDEV_PHUB_CH13_BASIC_CFG EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_ACTION +CYDEV_PHUB_CH13_ACTION EQU 0x400070e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASIC_STATUS +CYDEV_PHUB_CH13_BASIC_STATUS EQU 0x400070e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASE +CYDEV_PHUB_CH14_BASE EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_SIZE +CYDEV_PHUB_CH14_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASIC_CFG +CYDEV_PHUB_CH14_BASIC_CFG EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_ACTION +CYDEV_PHUB_CH14_ACTION EQU 0x400070f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASIC_STATUS +CYDEV_PHUB_CH14_BASIC_STATUS EQU 0x400070f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASE +CYDEV_PHUB_CH15_BASE EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_SIZE +CYDEV_PHUB_CH15_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASIC_CFG +CYDEV_PHUB_CH15_BASIC_CFG EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_ACTION +CYDEV_PHUB_CH15_ACTION EQU 0x40007104 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASIC_STATUS +CYDEV_PHUB_CH15_BASIC_STATUS EQU 0x40007108 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASE +CYDEV_PHUB_CH16_BASE EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_SIZE +CYDEV_PHUB_CH16_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASIC_CFG +CYDEV_PHUB_CH16_BASIC_CFG EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_ACTION +CYDEV_PHUB_CH16_ACTION EQU 0x40007114 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASIC_STATUS +CYDEV_PHUB_CH16_BASIC_STATUS EQU 0x40007118 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASE +CYDEV_PHUB_CH17_BASE EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_SIZE +CYDEV_PHUB_CH17_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASIC_CFG +CYDEV_PHUB_CH17_BASIC_CFG EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_ACTION +CYDEV_PHUB_CH17_ACTION EQU 0x40007124 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASIC_STATUS +CYDEV_PHUB_CH17_BASIC_STATUS EQU 0x40007128 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASE +CYDEV_PHUB_CH18_BASE EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_SIZE +CYDEV_PHUB_CH18_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASIC_CFG +CYDEV_PHUB_CH18_BASIC_CFG EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_ACTION +CYDEV_PHUB_CH18_ACTION EQU 0x40007134 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASIC_STATUS +CYDEV_PHUB_CH18_BASIC_STATUS EQU 0x40007138 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASE +CYDEV_PHUB_CH19_BASE EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_SIZE +CYDEV_PHUB_CH19_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASIC_CFG +CYDEV_PHUB_CH19_BASIC_CFG EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_ACTION +CYDEV_PHUB_CH19_ACTION EQU 0x40007144 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASIC_STATUS +CYDEV_PHUB_CH19_BASIC_STATUS EQU 0x40007148 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASE +CYDEV_PHUB_CH20_BASE EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_SIZE +CYDEV_PHUB_CH20_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASIC_CFG +CYDEV_PHUB_CH20_BASIC_CFG EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_ACTION +CYDEV_PHUB_CH20_ACTION EQU 0x40007154 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASIC_STATUS +CYDEV_PHUB_CH20_BASIC_STATUS EQU 0x40007158 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASE +CYDEV_PHUB_CH21_BASE EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_SIZE +CYDEV_PHUB_CH21_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASIC_CFG +CYDEV_PHUB_CH21_BASIC_CFG EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_ACTION +CYDEV_PHUB_CH21_ACTION EQU 0x40007164 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASIC_STATUS +CYDEV_PHUB_CH21_BASIC_STATUS EQU 0x40007168 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASE +CYDEV_PHUB_CH22_BASE EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_SIZE +CYDEV_PHUB_CH22_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASIC_CFG +CYDEV_PHUB_CH22_BASIC_CFG EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_ACTION +CYDEV_PHUB_CH22_ACTION EQU 0x40007174 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASIC_STATUS +CYDEV_PHUB_CH22_BASIC_STATUS EQU 0x40007178 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASE +CYDEV_PHUB_CH23_BASE EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_SIZE +CYDEV_PHUB_CH23_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASIC_CFG +CYDEV_PHUB_CH23_BASIC_CFG EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_ACTION +CYDEV_PHUB_CH23_ACTION EQU 0x40007184 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASIC_STATUS +CYDEV_PHUB_CH23_BASIC_STATUS EQU 0x40007188 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_BASE +CYDEV_PHUB_CFGMEM0_BASE EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_SIZE +CYDEV_PHUB_CFGMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_CFG0 +CYDEV_PHUB_CFGMEM0_CFG0 EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_CFG1 +CYDEV_PHUB_CFGMEM0_CFG1 EQU 0x40007604 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_BASE +CYDEV_PHUB_CFGMEM1_BASE EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_SIZE +CYDEV_PHUB_CFGMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_CFG0 +CYDEV_PHUB_CFGMEM1_CFG0 EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_CFG1 +CYDEV_PHUB_CFGMEM1_CFG1 EQU 0x4000760c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_BASE +CYDEV_PHUB_CFGMEM2_BASE EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_SIZE +CYDEV_PHUB_CFGMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_CFG0 +CYDEV_PHUB_CFGMEM2_CFG0 EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_CFG1 +CYDEV_PHUB_CFGMEM2_CFG1 EQU 0x40007614 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_BASE +CYDEV_PHUB_CFGMEM3_BASE EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_SIZE +CYDEV_PHUB_CFGMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_CFG0 +CYDEV_PHUB_CFGMEM3_CFG0 EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_CFG1 +CYDEV_PHUB_CFGMEM3_CFG1 EQU 0x4000761c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_BASE +CYDEV_PHUB_CFGMEM4_BASE EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_SIZE +CYDEV_PHUB_CFGMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_CFG0 +CYDEV_PHUB_CFGMEM4_CFG0 EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_CFG1 +CYDEV_PHUB_CFGMEM4_CFG1 EQU 0x40007624 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_BASE +CYDEV_PHUB_CFGMEM5_BASE EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_SIZE +CYDEV_PHUB_CFGMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_CFG0 +CYDEV_PHUB_CFGMEM5_CFG0 EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_CFG1 +CYDEV_PHUB_CFGMEM5_CFG1 EQU 0x4000762c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_BASE +CYDEV_PHUB_CFGMEM6_BASE EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_SIZE +CYDEV_PHUB_CFGMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_CFG0 +CYDEV_PHUB_CFGMEM6_CFG0 EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_CFG1 +CYDEV_PHUB_CFGMEM6_CFG1 EQU 0x40007634 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_BASE +CYDEV_PHUB_CFGMEM7_BASE EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_SIZE +CYDEV_PHUB_CFGMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_CFG0 +CYDEV_PHUB_CFGMEM7_CFG0 EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_CFG1 +CYDEV_PHUB_CFGMEM7_CFG1 EQU 0x4000763c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_BASE +CYDEV_PHUB_CFGMEM8_BASE EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_SIZE +CYDEV_PHUB_CFGMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_CFG0 +CYDEV_PHUB_CFGMEM8_CFG0 EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_CFG1 +CYDEV_PHUB_CFGMEM8_CFG1 EQU 0x40007644 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_BASE +CYDEV_PHUB_CFGMEM9_BASE EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_SIZE +CYDEV_PHUB_CFGMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_CFG0 +CYDEV_PHUB_CFGMEM9_CFG0 EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_CFG1 +CYDEV_PHUB_CFGMEM9_CFG1 EQU 0x4000764c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_BASE +CYDEV_PHUB_CFGMEM10_BASE EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_SIZE +CYDEV_PHUB_CFGMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_CFG0 +CYDEV_PHUB_CFGMEM10_CFG0 EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_CFG1 +CYDEV_PHUB_CFGMEM10_CFG1 EQU 0x40007654 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_BASE +CYDEV_PHUB_CFGMEM11_BASE EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_SIZE +CYDEV_PHUB_CFGMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_CFG0 +CYDEV_PHUB_CFGMEM11_CFG0 EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_CFG1 +CYDEV_PHUB_CFGMEM11_CFG1 EQU 0x4000765c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_BASE +CYDEV_PHUB_CFGMEM12_BASE EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_SIZE +CYDEV_PHUB_CFGMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_CFG0 +CYDEV_PHUB_CFGMEM12_CFG0 EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_CFG1 +CYDEV_PHUB_CFGMEM12_CFG1 EQU 0x40007664 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_BASE +CYDEV_PHUB_CFGMEM13_BASE EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_SIZE +CYDEV_PHUB_CFGMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_CFG0 +CYDEV_PHUB_CFGMEM13_CFG0 EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_CFG1 +CYDEV_PHUB_CFGMEM13_CFG1 EQU 0x4000766c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_BASE +CYDEV_PHUB_CFGMEM14_BASE EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_SIZE +CYDEV_PHUB_CFGMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_CFG0 +CYDEV_PHUB_CFGMEM14_CFG0 EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_CFG1 +CYDEV_PHUB_CFGMEM14_CFG1 EQU 0x40007674 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_BASE +CYDEV_PHUB_CFGMEM15_BASE EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_SIZE +CYDEV_PHUB_CFGMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_CFG0 +CYDEV_PHUB_CFGMEM15_CFG0 EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_CFG1 +CYDEV_PHUB_CFGMEM15_CFG1 EQU 0x4000767c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_BASE +CYDEV_PHUB_CFGMEM16_BASE EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_SIZE +CYDEV_PHUB_CFGMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_CFG0 +CYDEV_PHUB_CFGMEM16_CFG0 EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_CFG1 +CYDEV_PHUB_CFGMEM16_CFG1 EQU 0x40007684 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_BASE +CYDEV_PHUB_CFGMEM17_BASE EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_SIZE +CYDEV_PHUB_CFGMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_CFG0 +CYDEV_PHUB_CFGMEM17_CFG0 EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_CFG1 +CYDEV_PHUB_CFGMEM17_CFG1 EQU 0x4000768c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_BASE +CYDEV_PHUB_CFGMEM18_BASE EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_SIZE +CYDEV_PHUB_CFGMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_CFG0 +CYDEV_PHUB_CFGMEM18_CFG0 EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_CFG1 +CYDEV_PHUB_CFGMEM18_CFG1 EQU 0x40007694 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_BASE +CYDEV_PHUB_CFGMEM19_BASE EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_SIZE +CYDEV_PHUB_CFGMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_CFG0 +CYDEV_PHUB_CFGMEM19_CFG0 EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_CFG1 +CYDEV_PHUB_CFGMEM19_CFG1 EQU 0x4000769c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_BASE +CYDEV_PHUB_CFGMEM20_BASE EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_SIZE +CYDEV_PHUB_CFGMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_CFG0 +CYDEV_PHUB_CFGMEM20_CFG0 EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_CFG1 +CYDEV_PHUB_CFGMEM20_CFG1 EQU 0x400076a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_BASE +CYDEV_PHUB_CFGMEM21_BASE EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_SIZE +CYDEV_PHUB_CFGMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_CFG0 +CYDEV_PHUB_CFGMEM21_CFG0 EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_CFG1 +CYDEV_PHUB_CFGMEM21_CFG1 EQU 0x400076ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_BASE +CYDEV_PHUB_CFGMEM22_BASE EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_SIZE +CYDEV_PHUB_CFGMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_CFG0 +CYDEV_PHUB_CFGMEM22_CFG0 EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_CFG1 +CYDEV_PHUB_CFGMEM22_CFG1 EQU 0x400076b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_BASE +CYDEV_PHUB_CFGMEM23_BASE EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_SIZE +CYDEV_PHUB_CFGMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_CFG0 +CYDEV_PHUB_CFGMEM23_CFG0 EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_CFG1 +CYDEV_PHUB_CFGMEM23_CFG1 EQU 0x400076bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_BASE +CYDEV_PHUB_TDMEM0_BASE EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_SIZE +CYDEV_PHUB_TDMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_ORIG_TD0 +CYDEV_PHUB_TDMEM0_ORIG_TD0 EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_ORIG_TD1 +CYDEV_PHUB_TDMEM0_ORIG_TD1 EQU 0x40007804 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_BASE +CYDEV_PHUB_TDMEM1_BASE EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_SIZE +CYDEV_PHUB_TDMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_ORIG_TD0 +CYDEV_PHUB_TDMEM1_ORIG_TD0 EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_ORIG_TD1 +CYDEV_PHUB_TDMEM1_ORIG_TD1 EQU 0x4000780c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_BASE +CYDEV_PHUB_TDMEM2_BASE EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_SIZE +CYDEV_PHUB_TDMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_ORIG_TD0 +CYDEV_PHUB_TDMEM2_ORIG_TD0 EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_ORIG_TD1 +CYDEV_PHUB_TDMEM2_ORIG_TD1 EQU 0x40007814 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_BASE +CYDEV_PHUB_TDMEM3_BASE EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_SIZE +CYDEV_PHUB_TDMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_ORIG_TD0 +CYDEV_PHUB_TDMEM3_ORIG_TD0 EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_ORIG_TD1 +CYDEV_PHUB_TDMEM3_ORIG_TD1 EQU 0x4000781c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_BASE +CYDEV_PHUB_TDMEM4_BASE EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_SIZE +CYDEV_PHUB_TDMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_ORIG_TD0 +CYDEV_PHUB_TDMEM4_ORIG_TD0 EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_ORIG_TD1 +CYDEV_PHUB_TDMEM4_ORIG_TD1 EQU 0x40007824 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_BASE +CYDEV_PHUB_TDMEM5_BASE EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_SIZE +CYDEV_PHUB_TDMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_ORIG_TD0 +CYDEV_PHUB_TDMEM5_ORIG_TD0 EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_ORIG_TD1 +CYDEV_PHUB_TDMEM5_ORIG_TD1 EQU 0x4000782c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_BASE +CYDEV_PHUB_TDMEM6_BASE EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_SIZE +CYDEV_PHUB_TDMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_ORIG_TD0 +CYDEV_PHUB_TDMEM6_ORIG_TD0 EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_ORIG_TD1 +CYDEV_PHUB_TDMEM6_ORIG_TD1 EQU 0x40007834 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_BASE +CYDEV_PHUB_TDMEM7_BASE EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_SIZE +CYDEV_PHUB_TDMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_ORIG_TD0 +CYDEV_PHUB_TDMEM7_ORIG_TD0 EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_ORIG_TD1 +CYDEV_PHUB_TDMEM7_ORIG_TD1 EQU 0x4000783c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_BASE +CYDEV_PHUB_TDMEM8_BASE EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_SIZE +CYDEV_PHUB_TDMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_ORIG_TD0 +CYDEV_PHUB_TDMEM8_ORIG_TD0 EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_ORIG_TD1 +CYDEV_PHUB_TDMEM8_ORIG_TD1 EQU 0x40007844 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_BASE +CYDEV_PHUB_TDMEM9_BASE EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_SIZE +CYDEV_PHUB_TDMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_ORIG_TD0 +CYDEV_PHUB_TDMEM9_ORIG_TD0 EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_ORIG_TD1 +CYDEV_PHUB_TDMEM9_ORIG_TD1 EQU 0x4000784c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_BASE +CYDEV_PHUB_TDMEM10_BASE EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_SIZE +CYDEV_PHUB_TDMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_ORIG_TD0 +CYDEV_PHUB_TDMEM10_ORIG_TD0 EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_ORIG_TD1 +CYDEV_PHUB_TDMEM10_ORIG_TD1 EQU 0x40007854 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_BASE +CYDEV_PHUB_TDMEM11_BASE EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_SIZE +CYDEV_PHUB_TDMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_ORIG_TD0 +CYDEV_PHUB_TDMEM11_ORIG_TD0 EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_ORIG_TD1 +CYDEV_PHUB_TDMEM11_ORIG_TD1 EQU 0x4000785c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_BASE +CYDEV_PHUB_TDMEM12_BASE EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_SIZE +CYDEV_PHUB_TDMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_ORIG_TD0 +CYDEV_PHUB_TDMEM12_ORIG_TD0 EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_ORIG_TD1 +CYDEV_PHUB_TDMEM12_ORIG_TD1 EQU 0x40007864 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_BASE +CYDEV_PHUB_TDMEM13_BASE EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_SIZE +CYDEV_PHUB_TDMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_ORIG_TD0 +CYDEV_PHUB_TDMEM13_ORIG_TD0 EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_ORIG_TD1 +CYDEV_PHUB_TDMEM13_ORIG_TD1 EQU 0x4000786c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_BASE +CYDEV_PHUB_TDMEM14_BASE EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_SIZE +CYDEV_PHUB_TDMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_ORIG_TD0 +CYDEV_PHUB_TDMEM14_ORIG_TD0 EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_ORIG_TD1 +CYDEV_PHUB_TDMEM14_ORIG_TD1 EQU 0x40007874 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_BASE +CYDEV_PHUB_TDMEM15_BASE EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_SIZE +CYDEV_PHUB_TDMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_ORIG_TD0 +CYDEV_PHUB_TDMEM15_ORIG_TD0 EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_ORIG_TD1 +CYDEV_PHUB_TDMEM15_ORIG_TD1 EQU 0x4000787c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_BASE +CYDEV_PHUB_TDMEM16_BASE EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_SIZE +CYDEV_PHUB_TDMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_ORIG_TD0 +CYDEV_PHUB_TDMEM16_ORIG_TD0 EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_ORIG_TD1 +CYDEV_PHUB_TDMEM16_ORIG_TD1 EQU 0x40007884 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_BASE +CYDEV_PHUB_TDMEM17_BASE EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_SIZE +CYDEV_PHUB_TDMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_ORIG_TD0 +CYDEV_PHUB_TDMEM17_ORIG_TD0 EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_ORIG_TD1 +CYDEV_PHUB_TDMEM17_ORIG_TD1 EQU 0x4000788c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_BASE +CYDEV_PHUB_TDMEM18_BASE EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_SIZE +CYDEV_PHUB_TDMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_ORIG_TD0 +CYDEV_PHUB_TDMEM18_ORIG_TD0 EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_ORIG_TD1 +CYDEV_PHUB_TDMEM18_ORIG_TD1 EQU 0x40007894 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_BASE +CYDEV_PHUB_TDMEM19_BASE EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_SIZE +CYDEV_PHUB_TDMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_ORIG_TD0 +CYDEV_PHUB_TDMEM19_ORIG_TD0 EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_ORIG_TD1 +CYDEV_PHUB_TDMEM19_ORIG_TD1 EQU 0x4000789c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_BASE +CYDEV_PHUB_TDMEM20_BASE EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_SIZE +CYDEV_PHUB_TDMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_ORIG_TD0 +CYDEV_PHUB_TDMEM20_ORIG_TD0 EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_ORIG_TD1 +CYDEV_PHUB_TDMEM20_ORIG_TD1 EQU 0x400078a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_BASE +CYDEV_PHUB_TDMEM21_BASE EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_SIZE +CYDEV_PHUB_TDMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_ORIG_TD0 +CYDEV_PHUB_TDMEM21_ORIG_TD0 EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_ORIG_TD1 +CYDEV_PHUB_TDMEM21_ORIG_TD1 EQU 0x400078ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_BASE +CYDEV_PHUB_TDMEM22_BASE EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_SIZE +CYDEV_PHUB_TDMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_ORIG_TD0 +CYDEV_PHUB_TDMEM22_ORIG_TD0 EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_ORIG_TD1 +CYDEV_PHUB_TDMEM22_ORIG_TD1 EQU 0x400078b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_BASE +CYDEV_PHUB_TDMEM23_BASE EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_SIZE +CYDEV_PHUB_TDMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_ORIG_TD0 +CYDEV_PHUB_TDMEM23_ORIG_TD0 EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_ORIG_TD1 +CYDEV_PHUB_TDMEM23_ORIG_TD1 EQU 0x400078bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_BASE +CYDEV_PHUB_TDMEM24_BASE EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_SIZE +CYDEV_PHUB_TDMEM24_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_ORIG_TD0 +CYDEV_PHUB_TDMEM24_ORIG_TD0 EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_ORIG_TD1 +CYDEV_PHUB_TDMEM24_ORIG_TD1 EQU 0x400078c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_BASE +CYDEV_PHUB_TDMEM25_BASE EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_SIZE +CYDEV_PHUB_TDMEM25_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_ORIG_TD0 +CYDEV_PHUB_TDMEM25_ORIG_TD0 EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_ORIG_TD1 +CYDEV_PHUB_TDMEM25_ORIG_TD1 EQU 0x400078cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_BASE +CYDEV_PHUB_TDMEM26_BASE EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_SIZE +CYDEV_PHUB_TDMEM26_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_ORIG_TD0 +CYDEV_PHUB_TDMEM26_ORIG_TD0 EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_ORIG_TD1 +CYDEV_PHUB_TDMEM26_ORIG_TD1 EQU 0x400078d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_BASE +CYDEV_PHUB_TDMEM27_BASE EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_SIZE +CYDEV_PHUB_TDMEM27_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_ORIG_TD0 +CYDEV_PHUB_TDMEM27_ORIG_TD0 EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_ORIG_TD1 +CYDEV_PHUB_TDMEM27_ORIG_TD1 EQU 0x400078dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_BASE +CYDEV_PHUB_TDMEM28_BASE EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_SIZE +CYDEV_PHUB_TDMEM28_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_ORIG_TD0 +CYDEV_PHUB_TDMEM28_ORIG_TD0 EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_ORIG_TD1 +CYDEV_PHUB_TDMEM28_ORIG_TD1 EQU 0x400078e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_BASE +CYDEV_PHUB_TDMEM29_BASE EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_SIZE +CYDEV_PHUB_TDMEM29_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_ORIG_TD0 +CYDEV_PHUB_TDMEM29_ORIG_TD0 EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_ORIG_TD1 +CYDEV_PHUB_TDMEM29_ORIG_TD1 EQU 0x400078ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_BASE +CYDEV_PHUB_TDMEM30_BASE EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_SIZE +CYDEV_PHUB_TDMEM30_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_ORIG_TD0 +CYDEV_PHUB_TDMEM30_ORIG_TD0 EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_ORIG_TD1 +CYDEV_PHUB_TDMEM30_ORIG_TD1 EQU 0x400078f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_BASE +CYDEV_PHUB_TDMEM31_BASE EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_SIZE +CYDEV_PHUB_TDMEM31_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_ORIG_TD0 +CYDEV_PHUB_TDMEM31_ORIG_TD0 EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_ORIG_TD1 +CYDEV_PHUB_TDMEM31_ORIG_TD1 EQU 0x400078fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_BASE +CYDEV_PHUB_TDMEM32_BASE EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_SIZE +CYDEV_PHUB_TDMEM32_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_ORIG_TD0 +CYDEV_PHUB_TDMEM32_ORIG_TD0 EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_ORIG_TD1 +CYDEV_PHUB_TDMEM32_ORIG_TD1 EQU 0x40007904 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_BASE +CYDEV_PHUB_TDMEM33_BASE EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_SIZE +CYDEV_PHUB_TDMEM33_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_ORIG_TD0 +CYDEV_PHUB_TDMEM33_ORIG_TD0 EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_ORIG_TD1 +CYDEV_PHUB_TDMEM33_ORIG_TD1 EQU 0x4000790c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_BASE +CYDEV_PHUB_TDMEM34_BASE EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_SIZE +CYDEV_PHUB_TDMEM34_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_ORIG_TD0 +CYDEV_PHUB_TDMEM34_ORIG_TD0 EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_ORIG_TD1 +CYDEV_PHUB_TDMEM34_ORIG_TD1 EQU 0x40007914 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_BASE +CYDEV_PHUB_TDMEM35_BASE EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_SIZE +CYDEV_PHUB_TDMEM35_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_ORIG_TD0 +CYDEV_PHUB_TDMEM35_ORIG_TD0 EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_ORIG_TD1 +CYDEV_PHUB_TDMEM35_ORIG_TD1 EQU 0x4000791c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_BASE +CYDEV_PHUB_TDMEM36_BASE EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_SIZE +CYDEV_PHUB_TDMEM36_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_ORIG_TD0 +CYDEV_PHUB_TDMEM36_ORIG_TD0 EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_ORIG_TD1 +CYDEV_PHUB_TDMEM36_ORIG_TD1 EQU 0x40007924 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_BASE +CYDEV_PHUB_TDMEM37_BASE EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_SIZE +CYDEV_PHUB_TDMEM37_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_ORIG_TD0 +CYDEV_PHUB_TDMEM37_ORIG_TD0 EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_ORIG_TD1 +CYDEV_PHUB_TDMEM37_ORIG_TD1 EQU 0x4000792c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_BASE +CYDEV_PHUB_TDMEM38_BASE EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_SIZE +CYDEV_PHUB_TDMEM38_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_ORIG_TD0 +CYDEV_PHUB_TDMEM38_ORIG_TD0 EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_ORIG_TD1 +CYDEV_PHUB_TDMEM38_ORIG_TD1 EQU 0x40007934 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_BASE +CYDEV_PHUB_TDMEM39_BASE EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_SIZE +CYDEV_PHUB_TDMEM39_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_ORIG_TD0 +CYDEV_PHUB_TDMEM39_ORIG_TD0 EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_ORIG_TD1 +CYDEV_PHUB_TDMEM39_ORIG_TD1 EQU 0x4000793c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_BASE +CYDEV_PHUB_TDMEM40_BASE EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_SIZE +CYDEV_PHUB_TDMEM40_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_ORIG_TD0 +CYDEV_PHUB_TDMEM40_ORIG_TD0 EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_ORIG_TD1 +CYDEV_PHUB_TDMEM40_ORIG_TD1 EQU 0x40007944 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_BASE +CYDEV_PHUB_TDMEM41_BASE EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_SIZE +CYDEV_PHUB_TDMEM41_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_ORIG_TD0 +CYDEV_PHUB_TDMEM41_ORIG_TD0 EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_ORIG_TD1 +CYDEV_PHUB_TDMEM41_ORIG_TD1 EQU 0x4000794c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_BASE +CYDEV_PHUB_TDMEM42_BASE EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_SIZE +CYDEV_PHUB_TDMEM42_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_ORIG_TD0 +CYDEV_PHUB_TDMEM42_ORIG_TD0 EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_ORIG_TD1 +CYDEV_PHUB_TDMEM42_ORIG_TD1 EQU 0x40007954 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_BASE +CYDEV_PHUB_TDMEM43_BASE EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_SIZE +CYDEV_PHUB_TDMEM43_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_ORIG_TD0 +CYDEV_PHUB_TDMEM43_ORIG_TD0 EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_ORIG_TD1 +CYDEV_PHUB_TDMEM43_ORIG_TD1 EQU 0x4000795c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_BASE +CYDEV_PHUB_TDMEM44_BASE EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_SIZE +CYDEV_PHUB_TDMEM44_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_ORIG_TD0 +CYDEV_PHUB_TDMEM44_ORIG_TD0 EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_ORIG_TD1 +CYDEV_PHUB_TDMEM44_ORIG_TD1 EQU 0x40007964 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_BASE +CYDEV_PHUB_TDMEM45_BASE EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_SIZE +CYDEV_PHUB_TDMEM45_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_ORIG_TD0 +CYDEV_PHUB_TDMEM45_ORIG_TD0 EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_ORIG_TD1 +CYDEV_PHUB_TDMEM45_ORIG_TD1 EQU 0x4000796c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_BASE +CYDEV_PHUB_TDMEM46_BASE EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_SIZE +CYDEV_PHUB_TDMEM46_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_ORIG_TD0 +CYDEV_PHUB_TDMEM46_ORIG_TD0 EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_ORIG_TD1 +CYDEV_PHUB_TDMEM46_ORIG_TD1 EQU 0x40007974 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_BASE +CYDEV_PHUB_TDMEM47_BASE EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_SIZE +CYDEV_PHUB_TDMEM47_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_ORIG_TD0 +CYDEV_PHUB_TDMEM47_ORIG_TD0 EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_ORIG_TD1 +CYDEV_PHUB_TDMEM47_ORIG_TD1 EQU 0x4000797c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_BASE +CYDEV_PHUB_TDMEM48_BASE EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_SIZE +CYDEV_PHUB_TDMEM48_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_ORIG_TD0 +CYDEV_PHUB_TDMEM48_ORIG_TD0 EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_ORIG_TD1 +CYDEV_PHUB_TDMEM48_ORIG_TD1 EQU 0x40007984 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_BASE +CYDEV_PHUB_TDMEM49_BASE EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_SIZE +CYDEV_PHUB_TDMEM49_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_ORIG_TD0 +CYDEV_PHUB_TDMEM49_ORIG_TD0 EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_ORIG_TD1 +CYDEV_PHUB_TDMEM49_ORIG_TD1 EQU 0x4000798c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_BASE +CYDEV_PHUB_TDMEM50_BASE EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_SIZE +CYDEV_PHUB_TDMEM50_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_ORIG_TD0 +CYDEV_PHUB_TDMEM50_ORIG_TD0 EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_ORIG_TD1 +CYDEV_PHUB_TDMEM50_ORIG_TD1 EQU 0x40007994 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_BASE +CYDEV_PHUB_TDMEM51_BASE EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_SIZE +CYDEV_PHUB_TDMEM51_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_ORIG_TD0 +CYDEV_PHUB_TDMEM51_ORIG_TD0 EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_ORIG_TD1 +CYDEV_PHUB_TDMEM51_ORIG_TD1 EQU 0x4000799c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_BASE +CYDEV_PHUB_TDMEM52_BASE EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_SIZE +CYDEV_PHUB_TDMEM52_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_ORIG_TD0 +CYDEV_PHUB_TDMEM52_ORIG_TD0 EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_ORIG_TD1 +CYDEV_PHUB_TDMEM52_ORIG_TD1 EQU 0x400079a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_BASE +CYDEV_PHUB_TDMEM53_BASE EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_SIZE +CYDEV_PHUB_TDMEM53_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_ORIG_TD0 +CYDEV_PHUB_TDMEM53_ORIG_TD0 EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_ORIG_TD1 +CYDEV_PHUB_TDMEM53_ORIG_TD1 EQU 0x400079ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_BASE +CYDEV_PHUB_TDMEM54_BASE EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_SIZE +CYDEV_PHUB_TDMEM54_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_ORIG_TD0 +CYDEV_PHUB_TDMEM54_ORIG_TD0 EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_ORIG_TD1 +CYDEV_PHUB_TDMEM54_ORIG_TD1 EQU 0x400079b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_BASE +CYDEV_PHUB_TDMEM55_BASE EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_SIZE +CYDEV_PHUB_TDMEM55_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_ORIG_TD0 +CYDEV_PHUB_TDMEM55_ORIG_TD0 EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_ORIG_TD1 +CYDEV_PHUB_TDMEM55_ORIG_TD1 EQU 0x400079bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_BASE +CYDEV_PHUB_TDMEM56_BASE EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_SIZE +CYDEV_PHUB_TDMEM56_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_ORIG_TD0 +CYDEV_PHUB_TDMEM56_ORIG_TD0 EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_ORIG_TD1 +CYDEV_PHUB_TDMEM56_ORIG_TD1 EQU 0x400079c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_BASE +CYDEV_PHUB_TDMEM57_BASE EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_SIZE +CYDEV_PHUB_TDMEM57_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_ORIG_TD0 +CYDEV_PHUB_TDMEM57_ORIG_TD0 EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_ORIG_TD1 +CYDEV_PHUB_TDMEM57_ORIG_TD1 EQU 0x400079cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_BASE +CYDEV_PHUB_TDMEM58_BASE EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_SIZE +CYDEV_PHUB_TDMEM58_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_ORIG_TD0 +CYDEV_PHUB_TDMEM58_ORIG_TD0 EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_ORIG_TD1 +CYDEV_PHUB_TDMEM58_ORIG_TD1 EQU 0x400079d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_BASE +CYDEV_PHUB_TDMEM59_BASE EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_SIZE +CYDEV_PHUB_TDMEM59_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_ORIG_TD0 +CYDEV_PHUB_TDMEM59_ORIG_TD0 EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_ORIG_TD1 +CYDEV_PHUB_TDMEM59_ORIG_TD1 EQU 0x400079dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_BASE +CYDEV_PHUB_TDMEM60_BASE EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_SIZE +CYDEV_PHUB_TDMEM60_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_ORIG_TD0 +CYDEV_PHUB_TDMEM60_ORIG_TD0 EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_ORIG_TD1 +CYDEV_PHUB_TDMEM60_ORIG_TD1 EQU 0x400079e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_BASE +CYDEV_PHUB_TDMEM61_BASE EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_SIZE +CYDEV_PHUB_TDMEM61_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_ORIG_TD0 +CYDEV_PHUB_TDMEM61_ORIG_TD0 EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_ORIG_TD1 +CYDEV_PHUB_TDMEM61_ORIG_TD1 EQU 0x400079ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_BASE +CYDEV_PHUB_TDMEM62_BASE EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_SIZE +CYDEV_PHUB_TDMEM62_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_ORIG_TD0 +CYDEV_PHUB_TDMEM62_ORIG_TD0 EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_ORIG_TD1 +CYDEV_PHUB_TDMEM62_ORIG_TD1 EQU 0x400079f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_BASE +CYDEV_PHUB_TDMEM63_BASE EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_SIZE +CYDEV_PHUB_TDMEM63_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_ORIG_TD0 +CYDEV_PHUB_TDMEM63_ORIG_TD0 EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_ORIG_TD1 +CYDEV_PHUB_TDMEM63_ORIG_TD1 EQU 0x400079fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_BASE +CYDEV_PHUB_TDMEM64_BASE EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_SIZE +CYDEV_PHUB_TDMEM64_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_ORIG_TD0 +CYDEV_PHUB_TDMEM64_ORIG_TD0 EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_ORIG_TD1 +CYDEV_PHUB_TDMEM64_ORIG_TD1 EQU 0x40007a04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_BASE +CYDEV_PHUB_TDMEM65_BASE EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_SIZE +CYDEV_PHUB_TDMEM65_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_ORIG_TD0 +CYDEV_PHUB_TDMEM65_ORIG_TD0 EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_ORIG_TD1 +CYDEV_PHUB_TDMEM65_ORIG_TD1 EQU 0x40007a0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_BASE +CYDEV_PHUB_TDMEM66_BASE EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_SIZE +CYDEV_PHUB_TDMEM66_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_ORIG_TD0 +CYDEV_PHUB_TDMEM66_ORIG_TD0 EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_ORIG_TD1 +CYDEV_PHUB_TDMEM66_ORIG_TD1 EQU 0x40007a14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_BASE +CYDEV_PHUB_TDMEM67_BASE EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_SIZE +CYDEV_PHUB_TDMEM67_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_ORIG_TD0 +CYDEV_PHUB_TDMEM67_ORIG_TD0 EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_ORIG_TD1 +CYDEV_PHUB_TDMEM67_ORIG_TD1 EQU 0x40007a1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_BASE +CYDEV_PHUB_TDMEM68_BASE EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_SIZE +CYDEV_PHUB_TDMEM68_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_ORIG_TD0 +CYDEV_PHUB_TDMEM68_ORIG_TD0 EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_ORIG_TD1 +CYDEV_PHUB_TDMEM68_ORIG_TD1 EQU 0x40007a24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_BASE +CYDEV_PHUB_TDMEM69_BASE EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_SIZE +CYDEV_PHUB_TDMEM69_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_ORIG_TD0 +CYDEV_PHUB_TDMEM69_ORIG_TD0 EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_ORIG_TD1 +CYDEV_PHUB_TDMEM69_ORIG_TD1 EQU 0x40007a2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_BASE +CYDEV_PHUB_TDMEM70_BASE EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_SIZE +CYDEV_PHUB_TDMEM70_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_ORIG_TD0 +CYDEV_PHUB_TDMEM70_ORIG_TD0 EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_ORIG_TD1 +CYDEV_PHUB_TDMEM70_ORIG_TD1 EQU 0x40007a34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_BASE +CYDEV_PHUB_TDMEM71_BASE EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_SIZE +CYDEV_PHUB_TDMEM71_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_ORIG_TD0 +CYDEV_PHUB_TDMEM71_ORIG_TD0 EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_ORIG_TD1 +CYDEV_PHUB_TDMEM71_ORIG_TD1 EQU 0x40007a3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_BASE +CYDEV_PHUB_TDMEM72_BASE EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_SIZE +CYDEV_PHUB_TDMEM72_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_ORIG_TD0 +CYDEV_PHUB_TDMEM72_ORIG_TD0 EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_ORIG_TD1 +CYDEV_PHUB_TDMEM72_ORIG_TD1 EQU 0x40007a44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_BASE +CYDEV_PHUB_TDMEM73_BASE EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_SIZE +CYDEV_PHUB_TDMEM73_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_ORIG_TD0 +CYDEV_PHUB_TDMEM73_ORIG_TD0 EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_ORIG_TD1 +CYDEV_PHUB_TDMEM73_ORIG_TD1 EQU 0x40007a4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_BASE +CYDEV_PHUB_TDMEM74_BASE EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_SIZE +CYDEV_PHUB_TDMEM74_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_ORIG_TD0 +CYDEV_PHUB_TDMEM74_ORIG_TD0 EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_ORIG_TD1 +CYDEV_PHUB_TDMEM74_ORIG_TD1 EQU 0x40007a54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_BASE +CYDEV_PHUB_TDMEM75_BASE EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_SIZE +CYDEV_PHUB_TDMEM75_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_ORIG_TD0 +CYDEV_PHUB_TDMEM75_ORIG_TD0 EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_ORIG_TD1 +CYDEV_PHUB_TDMEM75_ORIG_TD1 EQU 0x40007a5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_BASE +CYDEV_PHUB_TDMEM76_BASE EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_SIZE +CYDEV_PHUB_TDMEM76_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_ORIG_TD0 +CYDEV_PHUB_TDMEM76_ORIG_TD0 EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_ORIG_TD1 +CYDEV_PHUB_TDMEM76_ORIG_TD1 EQU 0x40007a64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_BASE +CYDEV_PHUB_TDMEM77_BASE EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_SIZE +CYDEV_PHUB_TDMEM77_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_ORIG_TD0 +CYDEV_PHUB_TDMEM77_ORIG_TD0 EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_ORIG_TD1 +CYDEV_PHUB_TDMEM77_ORIG_TD1 EQU 0x40007a6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_BASE +CYDEV_PHUB_TDMEM78_BASE EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_SIZE +CYDEV_PHUB_TDMEM78_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_ORIG_TD0 +CYDEV_PHUB_TDMEM78_ORIG_TD0 EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_ORIG_TD1 +CYDEV_PHUB_TDMEM78_ORIG_TD1 EQU 0x40007a74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_BASE +CYDEV_PHUB_TDMEM79_BASE EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_SIZE +CYDEV_PHUB_TDMEM79_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_ORIG_TD0 +CYDEV_PHUB_TDMEM79_ORIG_TD0 EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_ORIG_TD1 +CYDEV_PHUB_TDMEM79_ORIG_TD1 EQU 0x40007a7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_BASE +CYDEV_PHUB_TDMEM80_BASE EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_SIZE +CYDEV_PHUB_TDMEM80_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_ORIG_TD0 +CYDEV_PHUB_TDMEM80_ORIG_TD0 EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_ORIG_TD1 +CYDEV_PHUB_TDMEM80_ORIG_TD1 EQU 0x40007a84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_BASE +CYDEV_PHUB_TDMEM81_BASE EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_SIZE +CYDEV_PHUB_TDMEM81_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_ORIG_TD0 +CYDEV_PHUB_TDMEM81_ORIG_TD0 EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_ORIG_TD1 +CYDEV_PHUB_TDMEM81_ORIG_TD1 EQU 0x40007a8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_BASE +CYDEV_PHUB_TDMEM82_BASE EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_SIZE +CYDEV_PHUB_TDMEM82_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_ORIG_TD0 +CYDEV_PHUB_TDMEM82_ORIG_TD0 EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_ORIG_TD1 +CYDEV_PHUB_TDMEM82_ORIG_TD1 EQU 0x40007a94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_BASE +CYDEV_PHUB_TDMEM83_BASE EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_SIZE +CYDEV_PHUB_TDMEM83_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_ORIG_TD0 +CYDEV_PHUB_TDMEM83_ORIG_TD0 EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_ORIG_TD1 +CYDEV_PHUB_TDMEM83_ORIG_TD1 EQU 0x40007a9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_BASE +CYDEV_PHUB_TDMEM84_BASE EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_SIZE +CYDEV_PHUB_TDMEM84_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_ORIG_TD0 +CYDEV_PHUB_TDMEM84_ORIG_TD0 EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_ORIG_TD1 +CYDEV_PHUB_TDMEM84_ORIG_TD1 EQU 0x40007aa4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_BASE +CYDEV_PHUB_TDMEM85_BASE EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_SIZE +CYDEV_PHUB_TDMEM85_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_ORIG_TD0 +CYDEV_PHUB_TDMEM85_ORIG_TD0 EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_ORIG_TD1 +CYDEV_PHUB_TDMEM85_ORIG_TD1 EQU 0x40007aac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_BASE +CYDEV_PHUB_TDMEM86_BASE EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_SIZE +CYDEV_PHUB_TDMEM86_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_ORIG_TD0 +CYDEV_PHUB_TDMEM86_ORIG_TD0 EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_ORIG_TD1 +CYDEV_PHUB_TDMEM86_ORIG_TD1 EQU 0x40007ab4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_BASE +CYDEV_PHUB_TDMEM87_BASE EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_SIZE +CYDEV_PHUB_TDMEM87_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_ORIG_TD0 +CYDEV_PHUB_TDMEM87_ORIG_TD0 EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_ORIG_TD1 +CYDEV_PHUB_TDMEM87_ORIG_TD1 EQU 0x40007abc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_BASE +CYDEV_PHUB_TDMEM88_BASE EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_SIZE +CYDEV_PHUB_TDMEM88_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_ORIG_TD0 +CYDEV_PHUB_TDMEM88_ORIG_TD0 EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_ORIG_TD1 +CYDEV_PHUB_TDMEM88_ORIG_TD1 EQU 0x40007ac4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_BASE +CYDEV_PHUB_TDMEM89_BASE EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_SIZE +CYDEV_PHUB_TDMEM89_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_ORIG_TD0 +CYDEV_PHUB_TDMEM89_ORIG_TD0 EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_ORIG_TD1 +CYDEV_PHUB_TDMEM89_ORIG_TD1 EQU 0x40007acc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_BASE +CYDEV_PHUB_TDMEM90_BASE EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_SIZE +CYDEV_PHUB_TDMEM90_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_ORIG_TD0 +CYDEV_PHUB_TDMEM90_ORIG_TD0 EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_ORIG_TD1 +CYDEV_PHUB_TDMEM90_ORIG_TD1 EQU 0x40007ad4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_BASE +CYDEV_PHUB_TDMEM91_BASE EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_SIZE +CYDEV_PHUB_TDMEM91_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_ORIG_TD0 +CYDEV_PHUB_TDMEM91_ORIG_TD0 EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_ORIG_TD1 +CYDEV_PHUB_TDMEM91_ORIG_TD1 EQU 0x40007adc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_BASE +CYDEV_PHUB_TDMEM92_BASE EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_SIZE +CYDEV_PHUB_TDMEM92_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_ORIG_TD0 +CYDEV_PHUB_TDMEM92_ORIG_TD0 EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_ORIG_TD1 +CYDEV_PHUB_TDMEM92_ORIG_TD1 EQU 0x40007ae4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_BASE +CYDEV_PHUB_TDMEM93_BASE EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_SIZE +CYDEV_PHUB_TDMEM93_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_ORIG_TD0 +CYDEV_PHUB_TDMEM93_ORIG_TD0 EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_ORIG_TD1 +CYDEV_PHUB_TDMEM93_ORIG_TD1 EQU 0x40007aec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_BASE +CYDEV_PHUB_TDMEM94_BASE EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_SIZE +CYDEV_PHUB_TDMEM94_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_ORIG_TD0 +CYDEV_PHUB_TDMEM94_ORIG_TD0 EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_ORIG_TD1 +CYDEV_PHUB_TDMEM94_ORIG_TD1 EQU 0x40007af4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_BASE +CYDEV_PHUB_TDMEM95_BASE EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_SIZE +CYDEV_PHUB_TDMEM95_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_ORIG_TD0 +CYDEV_PHUB_TDMEM95_ORIG_TD0 EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_ORIG_TD1 +CYDEV_PHUB_TDMEM95_ORIG_TD1 EQU 0x40007afc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_BASE +CYDEV_PHUB_TDMEM96_BASE EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_SIZE +CYDEV_PHUB_TDMEM96_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_ORIG_TD0 +CYDEV_PHUB_TDMEM96_ORIG_TD0 EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_ORIG_TD1 +CYDEV_PHUB_TDMEM96_ORIG_TD1 EQU 0x40007b04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_BASE +CYDEV_PHUB_TDMEM97_BASE EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_SIZE +CYDEV_PHUB_TDMEM97_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_ORIG_TD0 +CYDEV_PHUB_TDMEM97_ORIG_TD0 EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_ORIG_TD1 +CYDEV_PHUB_TDMEM97_ORIG_TD1 EQU 0x40007b0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_BASE +CYDEV_PHUB_TDMEM98_BASE EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_SIZE +CYDEV_PHUB_TDMEM98_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_ORIG_TD0 +CYDEV_PHUB_TDMEM98_ORIG_TD0 EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_ORIG_TD1 +CYDEV_PHUB_TDMEM98_ORIG_TD1 EQU 0x40007b14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_BASE +CYDEV_PHUB_TDMEM99_BASE EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_SIZE +CYDEV_PHUB_TDMEM99_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_ORIG_TD0 +CYDEV_PHUB_TDMEM99_ORIG_TD0 EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_ORIG_TD1 +CYDEV_PHUB_TDMEM99_ORIG_TD1 EQU 0x40007b1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_BASE +CYDEV_PHUB_TDMEM100_BASE EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_SIZE +CYDEV_PHUB_TDMEM100_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_ORIG_TD0 +CYDEV_PHUB_TDMEM100_ORIG_TD0 EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_ORIG_TD1 +CYDEV_PHUB_TDMEM100_ORIG_TD1 EQU 0x40007b24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_BASE +CYDEV_PHUB_TDMEM101_BASE EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_SIZE +CYDEV_PHUB_TDMEM101_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_ORIG_TD0 +CYDEV_PHUB_TDMEM101_ORIG_TD0 EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_ORIG_TD1 +CYDEV_PHUB_TDMEM101_ORIG_TD1 EQU 0x40007b2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_BASE +CYDEV_PHUB_TDMEM102_BASE EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_SIZE +CYDEV_PHUB_TDMEM102_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_ORIG_TD0 +CYDEV_PHUB_TDMEM102_ORIG_TD0 EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_ORIG_TD1 +CYDEV_PHUB_TDMEM102_ORIG_TD1 EQU 0x40007b34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_BASE +CYDEV_PHUB_TDMEM103_BASE EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_SIZE +CYDEV_PHUB_TDMEM103_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_ORIG_TD0 +CYDEV_PHUB_TDMEM103_ORIG_TD0 EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_ORIG_TD1 +CYDEV_PHUB_TDMEM103_ORIG_TD1 EQU 0x40007b3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_BASE +CYDEV_PHUB_TDMEM104_BASE EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_SIZE +CYDEV_PHUB_TDMEM104_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_ORIG_TD0 +CYDEV_PHUB_TDMEM104_ORIG_TD0 EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_ORIG_TD1 +CYDEV_PHUB_TDMEM104_ORIG_TD1 EQU 0x40007b44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_BASE +CYDEV_PHUB_TDMEM105_BASE EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_SIZE +CYDEV_PHUB_TDMEM105_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_ORIG_TD0 +CYDEV_PHUB_TDMEM105_ORIG_TD0 EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_ORIG_TD1 +CYDEV_PHUB_TDMEM105_ORIG_TD1 EQU 0x40007b4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_BASE +CYDEV_PHUB_TDMEM106_BASE EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_SIZE +CYDEV_PHUB_TDMEM106_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_ORIG_TD0 +CYDEV_PHUB_TDMEM106_ORIG_TD0 EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_ORIG_TD1 +CYDEV_PHUB_TDMEM106_ORIG_TD1 EQU 0x40007b54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_BASE +CYDEV_PHUB_TDMEM107_BASE EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_SIZE +CYDEV_PHUB_TDMEM107_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_ORIG_TD0 +CYDEV_PHUB_TDMEM107_ORIG_TD0 EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_ORIG_TD1 +CYDEV_PHUB_TDMEM107_ORIG_TD1 EQU 0x40007b5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_BASE +CYDEV_PHUB_TDMEM108_BASE EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_SIZE +CYDEV_PHUB_TDMEM108_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_ORIG_TD0 +CYDEV_PHUB_TDMEM108_ORIG_TD0 EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_ORIG_TD1 +CYDEV_PHUB_TDMEM108_ORIG_TD1 EQU 0x40007b64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_BASE +CYDEV_PHUB_TDMEM109_BASE EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_SIZE +CYDEV_PHUB_TDMEM109_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_ORIG_TD0 +CYDEV_PHUB_TDMEM109_ORIG_TD0 EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_ORIG_TD1 +CYDEV_PHUB_TDMEM109_ORIG_TD1 EQU 0x40007b6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_BASE +CYDEV_PHUB_TDMEM110_BASE EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_SIZE +CYDEV_PHUB_TDMEM110_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_ORIG_TD0 +CYDEV_PHUB_TDMEM110_ORIG_TD0 EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_ORIG_TD1 +CYDEV_PHUB_TDMEM110_ORIG_TD1 EQU 0x40007b74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_BASE +CYDEV_PHUB_TDMEM111_BASE EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_SIZE +CYDEV_PHUB_TDMEM111_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_ORIG_TD0 +CYDEV_PHUB_TDMEM111_ORIG_TD0 EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_ORIG_TD1 +CYDEV_PHUB_TDMEM111_ORIG_TD1 EQU 0x40007b7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_BASE +CYDEV_PHUB_TDMEM112_BASE EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_SIZE +CYDEV_PHUB_TDMEM112_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_ORIG_TD0 +CYDEV_PHUB_TDMEM112_ORIG_TD0 EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_ORIG_TD1 +CYDEV_PHUB_TDMEM112_ORIG_TD1 EQU 0x40007b84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_BASE +CYDEV_PHUB_TDMEM113_BASE EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_SIZE +CYDEV_PHUB_TDMEM113_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_ORIG_TD0 +CYDEV_PHUB_TDMEM113_ORIG_TD0 EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_ORIG_TD1 +CYDEV_PHUB_TDMEM113_ORIG_TD1 EQU 0x40007b8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_BASE +CYDEV_PHUB_TDMEM114_BASE EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_SIZE +CYDEV_PHUB_TDMEM114_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_ORIG_TD0 +CYDEV_PHUB_TDMEM114_ORIG_TD0 EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_ORIG_TD1 +CYDEV_PHUB_TDMEM114_ORIG_TD1 EQU 0x40007b94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_BASE +CYDEV_PHUB_TDMEM115_BASE EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_SIZE +CYDEV_PHUB_TDMEM115_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_ORIG_TD0 +CYDEV_PHUB_TDMEM115_ORIG_TD0 EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_ORIG_TD1 +CYDEV_PHUB_TDMEM115_ORIG_TD1 EQU 0x40007b9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_BASE +CYDEV_PHUB_TDMEM116_BASE EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_SIZE +CYDEV_PHUB_TDMEM116_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_ORIG_TD0 +CYDEV_PHUB_TDMEM116_ORIG_TD0 EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_ORIG_TD1 +CYDEV_PHUB_TDMEM116_ORIG_TD1 EQU 0x40007ba4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_BASE +CYDEV_PHUB_TDMEM117_BASE EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_SIZE +CYDEV_PHUB_TDMEM117_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_ORIG_TD0 +CYDEV_PHUB_TDMEM117_ORIG_TD0 EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_ORIG_TD1 +CYDEV_PHUB_TDMEM117_ORIG_TD1 EQU 0x40007bac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_BASE +CYDEV_PHUB_TDMEM118_BASE EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_SIZE +CYDEV_PHUB_TDMEM118_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_ORIG_TD0 +CYDEV_PHUB_TDMEM118_ORIG_TD0 EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_ORIG_TD1 +CYDEV_PHUB_TDMEM118_ORIG_TD1 EQU 0x40007bb4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_BASE +CYDEV_PHUB_TDMEM119_BASE EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_SIZE +CYDEV_PHUB_TDMEM119_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_ORIG_TD0 +CYDEV_PHUB_TDMEM119_ORIG_TD0 EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_ORIG_TD1 +CYDEV_PHUB_TDMEM119_ORIG_TD1 EQU 0x40007bbc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_BASE +CYDEV_PHUB_TDMEM120_BASE EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_SIZE +CYDEV_PHUB_TDMEM120_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_ORIG_TD0 +CYDEV_PHUB_TDMEM120_ORIG_TD0 EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_ORIG_TD1 +CYDEV_PHUB_TDMEM120_ORIG_TD1 EQU 0x40007bc4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_BASE +CYDEV_PHUB_TDMEM121_BASE EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_SIZE +CYDEV_PHUB_TDMEM121_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_ORIG_TD0 +CYDEV_PHUB_TDMEM121_ORIG_TD0 EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_ORIG_TD1 +CYDEV_PHUB_TDMEM121_ORIG_TD1 EQU 0x40007bcc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_BASE +CYDEV_PHUB_TDMEM122_BASE EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_SIZE +CYDEV_PHUB_TDMEM122_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_ORIG_TD0 +CYDEV_PHUB_TDMEM122_ORIG_TD0 EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_ORIG_TD1 +CYDEV_PHUB_TDMEM122_ORIG_TD1 EQU 0x40007bd4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_BASE +CYDEV_PHUB_TDMEM123_BASE EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_SIZE +CYDEV_PHUB_TDMEM123_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_ORIG_TD0 +CYDEV_PHUB_TDMEM123_ORIG_TD0 EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_ORIG_TD1 +CYDEV_PHUB_TDMEM123_ORIG_TD1 EQU 0x40007bdc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_BASE +CYDEV_PHUB_TDMEM124_BASE EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_SIZE +CYDEV_PHUB_TDMEM124_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_ORIG_TD0 +CYDEV_PHUB_TDMEM124_ORIG_TD0 EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_ORIG_TD1 +CYDEV_PHUB_TDMEM124_ORIG_TD1 EQU 0x40007be4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_BASE +CYDEV_PHUB_TDMEM125_BASE EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_SIZE +CYDEV_PHUB_TDMEM125_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_ORIG_TD0 +CYDEV_PHUB_TDMEM125_ORIG_TD0 EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_ORIG_TD1 +CYDEV_PHUB_TDMEM125_ORIG_TD1 EQU 0x40007bec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_BASE +CYDEV_PHUB_TDMEM126_BASE EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_SIZE +CYDEV_PHUB_TDMEM126_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_ORIG_TD0 +CYDEV_PHUB_TDMEM126_ORIG_TD0 EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_ORIG_TD1 +CYDEV_PHUB_TDMEM126_ORIG_TD1 EQU 0x40007bf4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_BASE +CYDEV_PHUB_TDMEM127_BASE EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_SIZE +CYDEV_PHUB_TDMEM127_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_ORIG_TD0 +CYDEV_PHUB_TDMEM127_ORIG_TD0 EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_ORIG_TD1 +CYDEV_PHUB_TDMEM127_ORIG_TD1 EQU 0x40007bfc + ENDIF + IF :LNOT::DEF:CYDEV_EE_BASE +CYDEV_EE_BASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYDEV_EE_SIZE +CYDEV_EE_SIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYDEV_EE_DATA_MBASE +CYDEV_EE_DATA_MBASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYDEV_EE_DATA_MSIZE +CYDEV_EE_DATA_MSIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_BASE +CYDEV_CAN0_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_SIZE +CYDEV_CAN0_SIZE EQU 0x000002a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_BASE +CYDEV_CAN0_CSR_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_SIZE +CYDEV_CAN0_CSR_SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_INT_SR +CYDEV_CAN0_CSR_INT_SR EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_INT_EN +CYDEV_CAN0_CSR_INT_EN EQU 0x4000a004 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_BUF_SR +CYDEV_CAN0_CSR_BUF_SR EQU 0x4000a008 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_ERR_SR +CYDEV_CAN0_CSR_ERR_SR EQU 0x4000a00c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_CMD +CYDEV_CAN0_CSR_CMD EQU 0x4000a010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_CFG +CYDEV_CAN0_CSR_CFG EQU 0x4000a014 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_BASE +CYDEV_CAN0_TX0_BASE EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_SIZE +CYDEV_CAN0_TX0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_CMD +CYDEV_CAN0_TX0_CMD EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_ID +CYDEV_CAN0_TX0_ID EQU 0x4000a024 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_DH +CYDEV_CAN0_TX0_DH EQU 0x4000a028 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_DL +CYDEV_CAN0_TX0_DL EQU 0x4000a02c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_BASE +CYDEV_CAN0_TX1_BASE EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_SIZE +CYDEV_CAN0_TX1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_CMD +CYDEV_CAN0_TX1_CMD EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_ID +CYDEV_CAN0_TX1_ID EQU 0x4000a034 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_DH +CYDEV_CAN0_TX1_DH EQU 0x4000a038 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_DL +CYDEV_CAN0_TX1_DL EQU 0x4000a03c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_BASE +CYDEV_CAN0_TX2_BASE EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_SIZE +CYDEV_CAN0_TX2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_CMD +CYDEV_CAN0_TX2_CMD EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_ID +CYDEV_CAN0_TX2_ID EQU 0x4000a044 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_DH +CYDEV_CAN0_TX2_DH EQU 0x4000a048 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_DL +CYDEV_CAN0_TX2_DL EQU 0x4000a04c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_BASE +CYDEV_CAN0_TX3_BASE EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_SIZE +CYDEV_CAN0_TX3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_CMD +CYDEV_CAN0_TX3_CMD EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_ID +CYDEV_CAN0_TX3_ID EQU 0x4000a054 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_DH +CYDEV_CAN0_TX3_DH EQU 0x4000a058 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_DL +CYDEV_CAN0_TX3_DL EQU 0x4000a05c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_BASE +CYDEV_CAN0_TX4_BASE EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_SIZE +CYDEV_CAN0_TX4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_CMD +CYDEV_CAN0_TX4_CMD EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_ID +CYDEV_CAN0_TX4_ID EQU 0x4000a064 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_DH +CYDEV_CAN0_TX4_DH EQU 0x4000a068 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_DL +CYDEV_CAN0_TX4_DL EQU 0x4000a06c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_BASE +CYDEV_CAN0_TX5_BASE EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_SIZE +CYDEV_CAN0_TX5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_CMD +CYDEV_CAN0_TX5_CMD EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_ID +CYDEV_CAN0_TX5_ID EQU 0x4000a074 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_DH +CYDEV_CAN0_TX5_DH EQU 0x4000a078 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_DL +CYDEV_CAN0_TX5_DL EQU 0x4000a07c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_BASE +CYDEV_CAN0_TX6_BASE EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_SIZE +CYDEV_CAN0_TX6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_CMD +CYDEV_CAN0_TX6_CMD EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_ID +CYDEV_CAN0_TX6_ID EQU 0x4000a084 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_DH +CYDEV_CAN0_TX6_DH EQU 0x4000a088 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_DL +CYDEV_CAN0_TX6_DL EQU 0x4000a08c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_BASE +CYDEV_CAN0_TX7_BASE EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_SIZE +CYDEV_CAN0_TX7_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_CMD +CYDEV_CAN0_TX7_CMD EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_ID +CYDEV_CAN0_TX7_ID EQU 0x4000a094 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_DH +CYDEV_CAN0_TX7_DH EQU 0x4000a098 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_DL +CYDEV_CAN0_TX7_DL EQU 0x4000a09c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_BASE +CYDEV_CAN0_RX0_BASE EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_SIZE +CYDEV_CAN0_RX0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_CMD +CYDEV_CAN0_RX0_CMD EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_ID +CYDEV_CAN0_RX0_ID EQU 0x4000a0a4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_DH +CYDEV_CAN0_RX0_DH EQU 0x4000a0a8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_DL +CYDEV_CAN0_RX0_DL EQU 0x4000a0ac + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_AMR +CYDEV_CAN0_RX0_AMR EQU 0x4000a0b0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_ACR +CYDEV_CAN0_RX0_ACR EQU 0x4000a0b4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_AMRD +CYDEV_CAN0_RX0_AMRD EQU 0x4000a0b8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_ACRD +CYDEV_CAN0_RX0_ACRD EQU 0x4000a0bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_BASE +CYDEV_CAN0_RX1_BASE EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_SIZE +CYDEV_CAN0_RX1_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_CMD +CYDEV_CAN0_RX1_CMD EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_ID +CYDEV_CAN0_RX1_ID EQU 0x4000a0c4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_DH +CYDEV_CAN0_RX1_DH EQU 0x4000a0c8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_DL +CYDEV_CAN0_RX1_DL EQU 0x4000a0cc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_AMR +CYDEV_CAN0_RX1_AMR EQU 0x4000a0d0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_ACR +CYDEV_CAN0_RX1_ACR EQU 0x4000a0d4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_AMRD +CYDEV_CAN0_RX1_AMRD EQU 0x4000a0d8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_ACRD +CYDEV_CAN0_RX1_ACRD EQU 0x4000a0dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_BASE +CYDEV_CAN0_RX2_BASE EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_SIZE +CYDEV_CAN0_RX2_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_CMD +CYDEV_CAN0_RX2_CMD EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_ID +CYDEV_CAN0_RX2_ID EQU 0x4000a0e4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_DH +CYDEV_CAN0_RX2_DH EQU 0x4000a0e8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_DL +CYDEV_CAN0_RX2_DL EQU 0x4000a0ec + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_AMR +CYDEV_CAN0_RX2_AMR EQU 0x4000a0f0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_ACR +CYDEV_CAN0_RX2_ACR EQU 0x4000a0f4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_AMRD +CYDEV_CAN0_RX2_AMRD EQU 0x4000a0f8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_ACRD +CYDEV_CAN0_RX2_ACRD EQU 0x4000a0fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_BASE +CYDEV_CAN0_RX3_BASE EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_SIZE +CYDEV_CAN0_RX3_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_CMD +CYDEV_CAN0_RX3_CMD EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_ID +CYDEV_CAN0_RX3_ID EQU 0x4000a104 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_DH +CYDEV_CAN0_RX3_DH EQU 0x4000a108 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_DL +CYDEV_CAN0_RX3_DL EQU 0x4000a10c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_AMR +CYDEV_CAN0_RX3_AMR EQU 0x4000a110 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_ACR +CYDEV_CAN0_RX3_ACR EQU 0x4000a114 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_AMRD +CYDEV_CAN0_RX3_AMRD EQU 0x4000a118 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_ACRD +CYDEV_CAN0_RX3_ACRD EQU 0x4000a11c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_BASE +CYDEV_CAN0_RX4_BASE EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_SIZE +CYDEV_CAN0_RX4_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_CMD +CYDEV_CAN0_RX4_CMD EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_ID +CYDEV_CAN0_RX4_ID EQU 0x4000a124 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_DH +CYDEV_CAN0_RX4_DH EQU 0x4000a128 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_DL +CYDEV_CAN0_RX4_DL EQU 0x4000a12c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_AMR +CYDEV_CAN0_RX4_AMR EQU 0x4000a130 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_ACR +CYDEV_CAN0_RX4_ACR EQU 0x4000a134 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_AMRD +CYDEV_CAN0_RX4_AMRD EQU 0x4000a138 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_ACRD +CYDEV_CAN0_RX4_ACRD EQU 0x4000a13c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_BASE +CYDEV_CAN0_RX5_BASE EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_SIZE +CYDEV_CAN0_RX5_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_CMD +CYDEV_CAN0_RX5_CMD EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_ID +CYDEV_CAN0_RX5_ID EQU 0x4000a144 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_DH +CYDEV_CAN0_RX5_DH EQU 0x4000a148 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_DL +CYDEV_CAN0_RX5_DL EQU 0x4000a14c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_AMR +CYDEV_CAN0_RX5_AMR EQU 0x4000a150 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_ACR +CYDEV_CAN0_RX5_ACR EQU 0x4000a154 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_AMRD +CYDEV_CAN0_RX5_AMRD EQU 0x4000a158 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_ACRD +CYDEV_CAN0_RX5_ACRD EQU 0x4000a15c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_BASE +CYDEV_CAN0_RX6_BASE EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_SIZE +CYDEV_CAN0_RX6_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_CMD +CYDEV_CAN0_RX6_CMD EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_ID +CYDEV_CAN0_RX6_ID EQU 0x4000a164 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_DH +CYDEV_CAN0_RX6_DH EQU 0x4000a168 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_DL +CYDEV_CAN0_RX6_DL EQU 0x4000a16c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_AMR +CYDEV_CAN0_RX6_AMR EQU 0x4000a170 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_ACR +CYDEV_CAN0_RX6_ACR EQU 0x4000a174 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_AMRD +CYDEV_CAN0_RX6_AMRD EQU 0x4000a178 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_ACRD +CYDEV_CAN0_RX6_ACRD EQU 0x4000a17c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_BASE +CYDEV_CAN0_RX7_BASE EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_SIZE +CYDEV_CAN0_RX7_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_CMD +CYDEV_CAN0_RX7_CMD EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_ID +CYDEV_CAN0_RX7_ID EQU 0x4000a184 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_DH +CYDEV_CAN0_RX7_DH EQU 0x4000a188 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_DL +CYDEV_CAN0_RX7_DL EQU 0x4000a18c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_AMR +CYDEV_CAN0_RX7_AMR EQU 0x4000a190 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_ACR +CYDEV_CAN0_RX7_ACR EQU 0x4000a194 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_AMRD +CYDEV_CAN0_RX7_AMRD EQU 0x4000a198 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_ACRD +CYDEV_CAN0_RX7_ACRD EQU 0x4000a19c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_BASE +CYDEV_CAN0_RX8_BASE EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_SIZE +CYDEV_CAN0_RX8_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_CMD +CYDEV_CAN0_RX8_CMD EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_ID +CYDEV_CAN0_RX8_ID EQU 0x4000a1a4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_DH +CYDEV_CAN0_RX8_DH EQU 0x4000a1a8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_DL +CYDEV_CAN0_RX8_DL EQU 0x4000a1ac + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_AMR +CYDEV_CAN0_RX8_AMR EQU 0x4000a1b0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_ACR +CYDEV_CAN0_RX8_ACR EQU 0x4000a1b4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_AMRD +CYDEV_CAN0_RX8_AMRD EQU 0x4000a1b8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_ACRD +CYDEV_CAN0_RX8_ACRD EQU 0x4000a1bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_BASE +CYDEV_CAN0_RX9_BASE EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_SIZE +CYDEV_CAN0_RX9_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_CMD +CYDEV_CAN0_RX9_CMD EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_ID +CYDEV_CAN0_RX9_ID EQU 0x4000a1c4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_DH +CYDEV_CAN0_RX9_DH EQU 0x4000a1c8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_DL +CYDEV_CAN0_RX9_DL EQU 0x4000a1cc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_AMR +CYDEV_CAN0_RX9_AMR EQU 0x4000a1d0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_ACR +CYDEV_CAN0_RX9_ACR EQU 0x4000a1d4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_AMRD +CYDEV_CAN0_RX9_AMRD EQU 0x4000a1d8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_ACRD +CYDEV_CAN0_RX9_ACRD EQU 0x4000a1dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_BASE +CYDEV_CAN0_RX10_BASE EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_SIZE +CYDEV_CAN0_RX10_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_CMD +CYDEV_CAN0_RX10_CMD EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_ID +CYDEV_CAN0_RX10_ID EQU 0x4000a1e4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_DH +CYDEV_CAN0_RX10_DH EQU 0x4000a1e8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_DL +CYDEV_CAN0_RX10_DL EQU 0x4000a1ec + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_AMR +CYDEV_CAN0_RX10_AMR EQU 0x4000a1f0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_ACR +CYDEV_CAN0_RX10_ACR EQU 0x4000a1f4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_AMRD +CYDEV_CAN0_RX10_AMRD EQU 0x4000a1f8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_ACRD +CYDEV_CAN0_RX10_ACRD EQU 0x4000a1fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_BASE +CYDEV_CAN0_RX11_BASE EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_SIZE +CYDEV_CAN0_RX11_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_CMD +CYDEV_CAN0_RX11_CMD EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_ID +CYDEV_CAN0_RX11_ID EQU 0x4000a204 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_DH +CYDEV_CAN0_RX11_DH EQU 0x4000a208 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_DL +CYDEV_CAN0_RX11_DL EQU 0x4000a20c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_AMR +CYDEV_CAN0_RX11_AMR EQU 0x4000a210 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_ACR +CYDEV_CAN0_RX11_ACR EQU 0x4000a214 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_AMRD +CYDEV_CAN0_RX11_AMRD EQU 0x4000a218 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_ACRD +CYDEV_CAN0_RX11_ACRD EQU 0x4000a21c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_BASE +CYDEV_CAN0_RX12_BASE EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_SIZE +CYDEV_CAN0_RX12_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_CMD +CYDEV_CAN0_RX12_CMD EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_ID +CYDEV_CAN0_RX12_ID EQU 0x4000a224 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_DH +CYDEV_CAN0_RX12_DH EQU 0x4000a228 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_DL +CYDEV_CAN0_RX12_DL EQU 0x4000a22c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_AMR +CYDEV_CAN0_RX12_AMR EQU 0x4000a230 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_ACR +CYDEV_CAN0_RX12_ACR EQU 0x4000a234 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_AMRD +CYDEV_CAN0_RX12_AMRD EQU 0x4000a238 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_ACRD +CYDEV_CAN0_RX12_ACRD EQU 0x4000a23c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_BASE +CYDEV_CAN0_RX13_BASE EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_SIZE +CYDEV_CAN0_RX13_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_CMD +CYDEV_CAN0_RX13_CMD EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_ID +CYDEV_CAN0_RX13_ID EQU 0x4000a244 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_DH +CYDEV_CAN0_RX13_DH EQU 0x4000a248 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_DL +CYDEV_CAN0_RX13_DL EQU 0x4000a24c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_AMR +CYDEV_CAN0_RX13_AMR EQU 0x4000a250 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_ACR +CYDEV_CAN0_RX13_ACR EQU 0x4000a254 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_AMRD +CYDEV_CAN0_RX13_AMRD EQU 0x4000a258 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_ACRD +CYDEV_CAN0_RX13_ACRD EQU 0x4000a25c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_BASE +CYDEV_CAN0_RX14_BASE EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_SIZE +CYDEV_CAN0_RX14_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_CMD +CYDEV_CAN0_RX14_CMD EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_ID +CYDEV_CAN0_RX14_ID EQU 0x4000a264 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_DH +CYDEV_CAN0_RX14_DH EQU 0x4000a268 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_DL +CYDEV_CAN0_RX14_DL EQU 0x4000a26c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_AMR +CYDEV_CAN0_RX14_AMR EQU 0x4000a270 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_ACR +CYDEV_CAN0_RX14_ACR EQU 0x4000a274 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_AMRD +CYDEV_CAN0_RX14_AMRD EQU 0x4000a278 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_ACRD +CYDEV_CAN0_RX14_ACRD EQU 0x4000a27c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_BASE +CYDEV_CAN0_RX15_BASE EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_SIZE +CYDEV_CAN0_RX15_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_CMD +CYDEV_CAN0_RX15_CMD EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_ID +CYDEV_CAN0_RX15_ID EQU 0x4000a284 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_DH +CYDEV_CAN0_RX15_DH EQU 0x4000a288 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_DL +CYDEV_CAN0_RX15_DL EQU 0x4000a28c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_AMR +CYDEV_CAN0_RX15_AMR EQU 0x4000a290 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_ACR +CYDEV_CAN0_RX15_ACR EQU 0x4000a294 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_AMRD +CYDEV_CAN0_RX15_AMRD EQU 0x4000a298 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_ACRD +CYDEV_CAN0_RX15_ACRD EQU 0x4000a29c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_BASE +CYDEV_DFB0_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SIZE +CYDEV_DFB0_SIZE EQU 0x000007b5 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_BASE +CYDEV_DFB0_DPA_SRAM_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_SIZE +CYDEV_DFB0_DPA_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_DATA_MBASE +CYDEV_DFB0_DPA_SRAM_DATA_MBASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_DATA_MSIZE +CYDEV_DFB0_DPA_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_BASE +CYDEV_DFB0_DPB_SRAM_BASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_SIZE +CYDEV_DFB0_DPB_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_DATA_MBASE +CYDEV_DFB0_DPB_SRAM_DATA_MBASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_DATA_MSIZE +CYDEV_DFB0_DPB_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_BASE +CYDEV_DFB0_CSA_SRAM_BASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_SIZE +CYDEV_DFB0_CSA_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_DATA_MBASE +CYDEV_DFB0_CSA_SRAM_DATA_MBASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_DATA_MSIZE +CYDEV_DFB0_CSA_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_BASE +CYDEV_DFB0_CSB_SRAM_BASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_SIZE +CYDEV_DFB0_CSB_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_DATA_MBASE +CYDEV_DFB0_CSB_SRAM_DATA_MBASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_DATA_MSIZE +CYDEV_DFB0_CSB_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_BASE +CYDEV_DFB0_FSM_SRAM_BASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_SIZE +CYDEV_DFB0_FSM_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_DATA_MBASE +CYDEV_DFB0_FSM_SRAM_DATA_MBASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_DATA_MSIZE +CYDEV_DFB0_FSM_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_BASE +CYDEV_DFB0_ACU_SRAM_BASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_SIZE +CYDEV_DFB0_ACU_SRAM_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_DATA_MBASE +CYDEV_DFB0_ACU_SRAM_DATA_MBASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_DATA_MSIZE +CYDEV_DFB0_ACU_SRAM_DATA_MSIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CR +CYDEV_DFB0_CR EQU 0x4000c780 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SR +CYDEV_DFB0_SR EQU 0x4000c784 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_RAM_EN +CYDEV_DFB0_RAM_EN EQU 0x4000c788 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_RAM_DIR +CYDEV_DFB0_RAM_DIR EQU 0x4000c78c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SEMA +CYDEV_DFB0_SEMA EQU 0x4000c790 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DSI_CTRL +CYDEV_DFB0_DSI_CTRL EQU 0x4000c794 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_INT_CTRL +CYDEV_DFB0_INT_CTRL EQU 0x4000c798 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DMA_CTRL +CYDEV_DFB0_DMA_CTRL EQU 0x4000c79c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEA +CYDEV_DFB0_STAGEA EQU 0x4000c7a0 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEAM +CYDEV_DFB0_STAGEAM EQU 0x4000c7a1 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEAH +CYDEV_DFB0_STAGEAH EQU 0x4000c7a2 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEB +CYDEV_DFB0_STAGEB EQU 0x4000c7a4 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEBM +CYDEV_DFB0_STAGEBM EQU 0x4000c7a5 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEBH +CYDEV_DFB0_STAGEBH EQU 0x4000c7a6 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDA +CYDEV_DFB0_HOLDA EQU 0x4000c7a8 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDAM +CYDEV_DFB0_HOLDAM EQU 0x4000c7a9 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDAH +CYDEV_DFB0_HOLDAH EQU 0x4000c7aa + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDAS +CYDEV_DFB0_HOLDAS EQU 0x4000c7ab + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDB +CYDEV_DFB0_HOLDB EQU 0x4000c7ac + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDBM +CYDEV_DFB0_HOLDBM EQU 0x4000c7ad + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDBH +CYDEV_DFB0_HOLDBH EQU 0x4000c7ae + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDBS +CYDEV_DFB0_HOLDBS EQU 0x4000c7af + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_COHER +CYDEV_DFB0_COHER EQU 0x4000c7b0 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DALIGN +CYDEV_DFB0_DALIGN EQU 0x4000c7b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BASE +CYDEV_UCFG_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_SIZE +CYDEV_UCFG_SIZE EQU 0x00005040 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_BASE +CYDEV_UCFG_B0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_SIZE +CYDEV_UCFG_B0_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_BASE +CYDEV_UCFG_B0_P0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_SIZE +CYDEV_UCFG_B0_P0_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_BASE +CYDEV_UCFG_B0_P0_U0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_SIZE +CYDEV_UCFG_B0_P0_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT0 +CYDEV_UCFG_B0_P0_U0_PLD_IT0 EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT1 +CYDEV_UCFG_B0_P0_U0_PLD_IT1 EQU 0x40010004 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT2 +CYDEV_UCFG_B0_P0_U0_PLD_IT2 EQU 0x40010008 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT3 +CYDEV_UCFG_B0_P0_U0_PLD_IT3 EQU 0x4001000c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT4 +CYDEV_UCFG_B0_P0_U0_PLD_IT4 EQU 0x40010010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT5 +CYDEV_UCFG_B0_P0_U0_PLD_IT5 EQU 0x40010014 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT6 +CYDEV_UCFG_B0_P0_U0_PLD_IT6 EQU 0x40010018 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT7 +CYDEV_UCFG_B0_P0_U0_PLD_IT7 EQU 0x4001001c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT8 +CYDEV_UCFG_B0_P0_U0_PLD_IT8 EQU 0x40010020 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT9 +CYDEV_UCFG_B0_P0_U0_PLD_IT9 EQU 0x40010024 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT10 +CYDEV_UCFG_B0_P0_U0_PLD_IT10 EQU 0x40010028 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT11 +CYDEV_UCFG_B0_P0_U0_PLD_IT11 EQU 0x4001002c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT0 +CYDEV_UCFG_B0_P0_U0_PLD_ORT0 EQU 0x40010030 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT1 +CYDEV_UCFG_B0_P0_U0_PLD_ORT1 EQU 0x40010032 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT2 +CYDEV_UCFG_B0_P0_U0_PLD_ORT2 EQU 0x40010034 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT3 +CYDEV_UCFG_B0_P0_U0_PLD_ORT3 EQU 0x40010036 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST EQU 0x40010038 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB EQU 0x4001003a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET EQU 0x4001003c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS EQU 0x4001003e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG0 +CYDEV_UCFG_B0_P0_U0_CFG0 EQU 0x40010040 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG1 +CYDEV_UCFG_B0_P0_U0_CFG1 EQU 0x40010041 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG2 +CYDEV_UCFG_B0_P0_U0_CFG2 EQU 0x40010042 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG3 +CYDEV_UCFG_B0_P0_U0_CFG3 EQU 0x40010043 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG4 +CYDEV_UCFG_B0_P0_U0_CFG4 EQU 0x40010044 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG5 +CYDEV_UCFG_B0_P0_U0_CFG5 EQU 0x40010045 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG6 +CYDEV_UCFG_B0_P0_U0_CFG6 EQU 0x40010046 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG7 +CYDEV_UCFG_B0_P0_U0_CFG7 EQU 0x40010047 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG8 +CYDEV_UCFG_B0_P0_U0_CFG8 EQU 0x40010048 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG9 +CYDEV_UCFG_B0_P0_U0_CFG9 EQU 0x40010049 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG10 +CYDEV_UCFG_B0_P0_U0_CFG10 EQU 0x4001004a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG11 +CYDEV_UCFG_B0_P0_U0_CFG11 EQU 0x4001004b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG12 +CYDEV_UCFG_B0_P0_U0_CFG12 EQU 0x4001004c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG13 +CYDEV_UCFG_B0_P0_U0_CFG13 EQU 0x4001004d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG14 +CYDEV_UCFG_B0_P0_U0_CFG14 EQU 0x4001004e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG15 +CYDEV_UCFG_B0_P0_U0_CFG15 EQU 0x4001004f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG16 +CYDEV_UCFG_B0_P0_U0_CFG16 EQU 0x40010050 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG17 +CYDEV_UCFG_B0_P0_U0_CFG17 EQU 0x40010051 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG18 +CYDEV_UCFG_B0_P0_U0_CFG18 EQU 0x40010052 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG19 +CYDEV_UCFG_B0_P0_U0_CFG19 EQU 0x40010053 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG20 +CYDEV_UCFG_B0_P0_U0_CFG20 EQU 0x40010054 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG21 +CYDEV_UCFG_B0_P0_U0_CFG21 EQU 0x40010055 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG22 +CYDEV_UCFG_B0_P0_U0_CFG22 EQU 0x40010056 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG23 +CYDEV_UCFG_B0_P0_U0_CFG23 EQU 0x40010057 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG24 +CYDEV_UCFG_B0_P0_U0_CFG24 EQU 0x40010058 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG25 +CYDEV_UCFG_B0_P0_U0_CFG25 EQU 0x40010059 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG26 +CYDEV_UCFG_B0_P0_U0_CFG26 EQU 0x4001005a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG27 +CYDEV_UCFG_B0_P0_U0_CFG27 EQU 0x4001005b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG28 +CYDEV_UCFG_B0_P0_U0_CFG28 EQU 0x4001005c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG29 +CYDEV_UCFG_B0_P0_U0_CFG29 EQU 0x4001005d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG30 +CYDEV_UCFG_B0_P0_U0_CFG30 EQU 0x4001005e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG31 +CYDEV_UCFG_B0_P0_U0_CFG31 EQU 0x4001005f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG0 +CYDEV_UCFG_B0_P0_U0_DCFG0 EQU 0x40010060 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG1 +CYDEV_UCFG_B0_P0_U0_DCFG1 EQU 0x40010062 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG2 +CYDEV_UCFG_B0_P0_U0_DCFG2 EQU 0x40010064 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG3 +CYDEV_UCFG_B0_P0_U0_DCFG3 EQU 0x40010066 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG4 +CYDEV_UCFG_B0_P0_U0_DCFG4 EQU 0x40010068 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG5 +CYDEV_UCFG_B0_P0_U0_DCFG5 EQU 0x4001006a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG6 +CYDEV_UCFG_B0_P0_U0_DCFG6 EQU 0x4001006c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG7 +CYDEV_UCFG_B0_P0_U0_DCFG7 EQU 0x4001006e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_BASE +CYDEV_UCFG_B0_P0_U1_BASE EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_SIZE +CYDEV_UCFG_B0_P0_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT0 +CYDEV_UCFG_B0_P0_U1_PLD_IT0 EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT1 +CYDEV_UCFG_B0_P0_U1_PLD_IT1 EQU 0x40010084 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT2 +CYDEV_UCFG_B0_P0_U1_PLD_IT2 EQU 0x40010088 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT3 +CYDEV_UCFG_B0_P0_U1_PLD_IT3 EQU 0x4001008c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT4 +CYDEV_UCFG_B0_P0_U1_PLD_IT4 EQU 0x40010090 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT5 +CYDEV_UCFG_B0_P0_U1_PLD_IT5 EQU 0x40010094 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT6 +CYDEV_UCFG_B0_P0_U1_PLD_IT6 EQU 0x40010098 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT7 +CYDEV_UCFG_B0_P0_U1_PLD_IT7 EQU 0x4001009c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT8 +CYDEV_UCFG_B0_P0_U1_PLD_IT8 EQU 0x400100a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT9 +CYDEV_UCFG_B0_P0_U1_PLD_IT9 EQU 0x400100a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT10 +CYDEV_UCFG_B0_P0_U1_PLD_IT10 EQU 0x400100a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT11 +CYDEV_UCFG_B0_P0_U1_PLD_IT11 EQU 0x400100ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT0 +CYDEV_UCFG_B0_P0_U1_PLD_ORT0 EQU 0x400100b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT1 +CYDEV_UCFG_B0_P0_U1_PLD_ORT1 EQU 0x400100b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT2 +CYDEV_UCFG_B0_P0_U1_PLD_ORT2 EQU 0x400100b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT3 +CYDEV_UCFG_B0_P0_U1_PLD_ORT3 EQU 0x400100b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST EQU 0x400100b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB EQU 0x400100ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET EQU 0x400100bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS EQU 0x400100be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG0 +CYDEV_UCFG_B0_P0_U1_CFG0 EQU 0x400100c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG1 +CYDEV_UCFG_B0_P0_U1_CFG1 EQU 0x400100c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG2 +CYDEV_UCFG_B0_P0_U1_CFG2 EQU 0x400100c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG3 +CYDEV_UCFG_B0_P0_U1_CFG3 EQU 0x400100c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG4 +CYDEV_UCFG_B0_P0_U1_CFG4 EQU 0x400100c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG5 +CYDEV_UCFG_B0_P0_U1_CFG5 EQU 0x400100c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG6 +CYDEV_UCFG_B0_P0_U1_CFG6 EQU 0x400100c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG7 +CYDEV_UCFG_B0_P0_U1_CFG7 EQU 0x400100c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG8 +CYDEV_UCFG_B0_P0_U1_CFG8 EQU 0x400100c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG9 +CYDEV_UCFG_B0_P0_U1_CFG9 EQU 0x400100c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG10 +CYDEV_UCFG_B0_P0_U1_CFG10 EQU 0x400100ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG11 +CYDEV_UCFG_B0_P0_U1_CFG11 EQU 0x400100cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG12 +CYDEV_UCFG_B0_P0_U1_CFG12 EQU 0x400100cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG13 +CYDEV_UCFG_B0_P0_U1_CFG13 EQU 0x400100cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG14 +CYDEV_UCFG_B0_P0_U1_CFG14 EQU 0x400100ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG15 +CYDEV_UCFG_B0_P0_U1_CFG15 EQU 0x400100cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG16 +CYDEV_UCFG_B0_P0_U1_CFG16 EQU 0x400100d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG17 +CYDEV_UCFG_B0_P0_U1_CFG17 EQU 0x400100d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG18 +CYDEV_UCFG_B0_P0_U1_CFG18 EQU 0x400100d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG19 +CYDEV_UCFG_B0_P0_U1_CFG19 EQU 0x400100d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG20 +CYDEV_UCFG_B0_P0_U1_CFG20 EQU 0x400100d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG21 +CYDEV_UCFG_B0_P0_U1_CFG21 EQU 0x400100d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG22 +CYDEV_UCFG_B0_P0_U1_CFG22 EQU 0x400100d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG23 +CYDEV_UCFG_B0_P0_U1_CFG23 EQU 0x400100d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG24 +CYDEV_UCFG_B0_P0_U1_CFG24 EQU 0x400100d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG25 +CYDEV_UCFG_B0_P0_U1_CFG25 EQU 0x400100d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG26 +CYDEV_UCFG_B0_P0_U1_CFG26 EQU 0x400100da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG27 +CYDEV_UCFG_B0_P0_U1_CFG27 EQU 0x400100db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG28 +CYDEV_UCFG_B0_P0_U1_CFG28 EQU 0x400100dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG29 +CYDEV_UCFG_B0_P0_U1_CFG29 EQU 0x400100dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG30 +CYDEV_UCFG_B0_P0_U1_CFG30 EQU 0x400100de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG31 +CYDEV_UCFG_B0_P0_U1_CFG31 EQU 0x400100df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG0 +CYDEV_UCFG_B0_P0_U1_DCFG0 EQU 0x400100e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG1 +CYDEV_UCFG_B0_P0_U1_DCFG1 EQU 0x400100e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG2 +CYDEV_UCFG_B0_P0_U1_DCFG2 EQU 0x400100e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG3 +CYDEV_UCFG_B0_P0_U1_DCFG3 EQU 0x400100e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG4 +CYDEV_UCFG_B0_P0_U1_DCFG4 EQU 0x400100e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG5 +CYDEV_UCFG_B0_P0_U1_DCFG5 EQU 0x400100ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG6 +CYDEV_UCFG_B0_P0_U1_DCFG6 EQU 0x400100ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG7 +CYDEV_UCFG_B0_P0_U1_DCFG7 EQU 0x400100ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_BASE +CYDEV_UCFG_B0_P0_ROUTE_BASE EQU 0x40010100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_SIZE +CYDEV_UCFG_B0_P0_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_BASE +CYDEV_UCFG_B0_P1_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_SIZE +CYDEV_UCFG_B0_P1_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_BASE +CYDEV_UCFG_B0_P1_U0_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_SIZE +CYDEV_UCFG_B0_P1_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT0 +CYDEV_UCFG_B0_P1_U0_PLD_IT0 EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT1 +CYDEV_UCFG_B0_P1_U0_PLD_IT1 EQU 0x40010204 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT2 +CYDEV_UCFG_B0_P1_U0_PLD_IT2 EQU 0x40010208 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT3 +CYDEV_UCFG_B0_P1_U0_PLD_IT3 EQU 0x4001020c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT4 +CYDEV_UCFG_B0_P1_U0_PLD_IT4 EQU 0x40010210 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT5 +CYDEV_UCFG_B0_P1_U0_PLD_IT5 EQU 0x40010214 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT6 +CYDEV_UCFG_B0_P1_U0_PLD_IT6 EQU 0x40010218 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT7 +CYDEV_UCFG_B0_P1_U0_PLD_IT7 EQU 0x4001021c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT8 +CYDEV_UCFG_B0_P1_U0_PLD_IT8 EQU 0x40010220 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT9 +CYDEV_UCFG_B0_P1_U0_PLD_IT9 EQU 0x40010224 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT10 +CYDEV_UCFG_B0_P1_U0_PLD_IT10 EQU 0x40010228 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT11 +CYDEV_UCFG_B0_P1_U0_PLD_IT11 EQU 0x4001022c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT0 +CYDEV_UCFG_B0_P1_U0_PLD_ORT0 EQU 0x40010230 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT1 +CYDEV_UCFG_B0_P1_U0_PLD_ORT1 EQU 0x40010232 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT2 +CYDEV_UCFG_B0_P1_U0_PLD_ORT2 EQU 0x40010234 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT3 +CYDEV_UCFG_B0_P1_U0_PLD_ORT3 EQU 0x40010236 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST EQU 0x40010238 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB EQU 0x4001023a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET EQU 0x4001023c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS EQU 0x4001023e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG0 +CYDEV_UCFG_B0_P1_U0_CFG0 EQU 0x40010240 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG1 +CYDEV_UCFG_B0_P1_U0_CFG1 EQU 0x40010241 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG2 +CYDEV_UCFG_B0_P1_U0_CFG2 EQU 0x40010242 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG3 +CYDEV_UCFG_B0_P1_U0_CFG3 EQU 0x40010243 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG4 +CYDEV_UCFG_B0_P1_U0_CFG4 EQU 0x40010244 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG5 +CYDEV_UCFG_B0_P1_U0_CFG5 EQU 0x40010245 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG6 +CYDEV_UCFG_B0_P1_U0_CFG6 EQU 0x40010246 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG7 +CYDEV_UCFG_B0_P1_U0_CFG7 EQU 0x40010247 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG8 +CYDEV_UCFG_B0_P1_U0_CFG8 EQU 0x40010248 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG9 +CYDEV_UCFG_B0_P1_U0_CFG9 EQU 0x40010249 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG10 +CYDEV_UCFG_B0_P1_U0_CFG10 EQU 0x4001024a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG11 +CYDEV_UCFG_B0_P1_U0_CFG11 EQU 0x4001024b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG12 +CYDEV_UCFG_B0_P1_U0_CFG12 EQU 0x4001024c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG13 +CYDEV_UCFG_B0_P1_U0_CFG13 EQU 0x4001024d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG14 +CYDEV_UCFG_B0_P1_U0_CFG14 EQU 0x4001024e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG15 +CYDEV_UCFG_B0_P1_U0_CFG15 EQU 0x4001024f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG16 +CYDEV_UCFG_B0_P1_U0_CFG16 EQU 0x40010250 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG17 +CYDEV_UCFG_B0_P1_U0_CFG17 EQU 0x40010251 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG18 +CYDEV_UCFG_B0_P1_U0_CFG18 EQU 0x40010252 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG19 +CYDEV_UCFG_B0_P1_U0_CFG19 EQU 0x40010253 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG20 +CYDEV_UCFG_B0_P1_U0_CFG20 EQU 0x40010254 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG21 +CYDEV_UCFG_B0_P1_U0_CFG21 EQU 0x40010255 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG22 +CYDEV_UCFG_B0_P1_U0_CFG22 EQU 0x40010256 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG23 +CYDEV_UCFG_B0_P1_U0_CFG23 EQU 0x40010257 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG24 +CYDEV_UCFG_B0_P1_U0_CFG24 EQU 0x40010258 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG25 +CYDEV_UCFG_B0_P1_U0_CFG25 EQU 0x40010259 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG26 +CYDEV_UCFG_B0_P1_U0_CFG26 EQU 0x4001025a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG27 +CYDEV_UCFG_B0_P1_U0_CFG27 EQU 0x4001025b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG28 +CYDEV_UCFG_B0_P1_U0_CFG28 EQU 0x4001025c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG29 +CYDEV_UCFG_B0_P1_U0_CFG29 EQU 0x4001025d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG30 +CYDEV_UCFG_B0_P1_U0_CFG30 EQU 0x4001025e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG31 +CYDEV_UCFG_B0_P1_U0_CFG31 EQU 0x4001025f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG0 +CYDEV_UCFG_B0_P1_U0_DCFG0 EQU 0x40010260 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG1 +CYDEV_UCFG_B0_P1_U0_DCFG1 EQU 0x40010262 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG2 +CYDEV_UCFG_B0_P1_U0_DCFG2 EQU 0x40010264 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG3 +CYDEV_UCFG_B0_P1_U0_DCFG3 EQU 0x40010266 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG4 +CYDEV_UCFG_B0_P1_U0_DCFG4 EQU 0x40010268 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG5 +CYDEV_UCFG_B0_P1_U0_DCFG5 EQU 0x4001026a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG6 +CYDEV_UCFG_B0_P1_U0_DCFG6 EQU 0x4001026c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG7 +CYDEV_UCFG_B0_P1_U0_DCFG7 EQU 0x4001026e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_BASE +CYDEV_UCFG_B0_P1_U1_BASE EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_SIZE +CYDEV_UCFG_B0_P1_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT0 +CYDEV_UCFG_B0_P1_U1_PLD_IT0 EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT1 +CYDEV_UCFG_B0_P1_U1_PLD_IT1 EQU 0x40010284 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT2 +CYDEV_UCFG_B0_P1_U1_PLD_IT2 EQU 0x40010288 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT3 +CYDEV_UCFG_B0_P1_U1_PLD_IT3 EQU 0x4001028c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT4 +CYDEV_UCFG_B0_P1_U1_PLD_IT4 EQU 0x40010290 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT5 +CYDEV_UCFG_B0_P1_U1_PLD_IT5 EQU 0x40010294 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT6 +CYDEV_UCFG_B0_P1_U1_PLD_IT6 EQU 0x40010298 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT7 +CYDEV_UCFG_B0_P1_U1_PLD_IT7 EQU 0x4001029c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT8 +CYDEV_UCFG_B0_P1_U1_PLD_IT8 EQU 0x400102a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT9 +CYDEV_UCFG_B0_P1_U1_PLD_IT9 EQU 0x400102a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT10 +CYDEV_UCFG_B0_P1_U1_PLD_IT10 EQU 0x400102a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT11 +CYDEV_UCFG_B0_P1_U1_PLD_IT11 EQU 0x400102ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT0 +CYDEV_UCFG_B0_P1_U1_PLD_ORT0 EQU 0x400102b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT1 +CYDEV_UCFG_B0_P1_U1_PLD_ORT1 EQU 0x400102b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT2 +CYDEV_UCFG_B0_P1_U1_PLD_ORT2 EQU 0x400102b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT3 +CYDEV_UCFG_B0_P1_U1_PLD_ORT3 EQU 0x400102b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST EQU 0x400102b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB EQU 0x400102ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET EQU 0x400102bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS EQU 0x400102be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG0 +CYDEV_UCFG_B0_P1_U1_CFG0 EQU 0x400102c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG1 +CYDEV_UCFG_B0_P1_U1_CFG1 EQU 0x400102c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG2 +CYDEV_UCFG_B0_P1_U1_CFG2 EQU 0x400102c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG3 +CYDEV_UCFG_B0_P1_U1_CFG3 EQU 0x400102c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG4 +CYDEV_UCFG_B0_P1_U1_CFG4 EQU 0x400102c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG5 +CYDEV_UCFG_B0_P1_U1_CFG5 EQU 0x400102c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG6 +CYDEV_UCFG_B0_P1_U1_CFG6 EQU 0x400102c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG7 +CYDEV_UCFG_B0_P1_U1_CFG7 EQU 0x400102c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG8 +CYDEV_UCFG_B0_P1_U1_CFG8 EQU 0x400102c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG9 +CYDEV_UCFG_B0_P1_U1_CFG9 EQU 0x400102c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG10 +CYDEV_UCFG_B0_P1_U1_CFG10 EQU 0x400102ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG11 +CYDEV_UCFG_B0_P1_U1_CFG11 EQU 0x400102cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG12 +CYDEV_UCFG_B0_P1_U1_CFG12 EQU 0x400102cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG13 +CYDEV_UCFG_B0_P1_U1_CFG13 EQU 0x400102cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG14 +CYDEV_UCFG_B0_P1_U1_CFG14 EQU 0x400102ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG15 +CYDEV_UCFG_B0_P1_U1_CFG15 EQU 0x400102cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG16 +CYDEV_UCFG_B0_P1_U1_CFG16 EQU 0x400102d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG17 +CYDEV_UCFG_B0_P1_U1_CFG17 EQU 0x400102d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG18 +CYDEV_UCFG_B0_P1_U1_CFG18 EQU 0x400102d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG19 +CYDEV_UCFG_B0_P1_U1_CFG19 EQU 0x400102d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG20 +CYDEV_UCFG_B0_P1_U1_CFG20 EQU 0x400102d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG21 +CYDEV_UCFG_B0_P1_U1_CFG21 EQU 0x400102d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG22 +CYDEV_UCFG_B0_P1_U1_CFG22 EQU 0x400102d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG23 +CYDEV_UCFG_B0_P1_U1_CFG23 EQU 0x400102d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG24 +CYDEV_UCFG_B0_P1_U1_CFG24 EQU 0x400102d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG25 +CYDEV_UCFG_B0_P1_U1_CFG25 EQU 0x400102d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG26 +CYDEV_UCFG_B0_P1_U1_CFG26 EQU 0x400102da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG27 +CYDEV_UCFG_B0_P1_U1_CFG27 EQU 0x400102db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG28 +CYDEV_UCFG_B0_P1_U1_CFG28 EQU 0x400102dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG29 +CYDEV_UCFG_B0_P1_U1_CFG29 EQU 0x400102dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG30 +CYDEV_UCFG_B0_P1_U1_CFG30 EQU 0x400102de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG31 +CYDEV_UCFG_B0_P1_U1_CFG31 EQU 0x400102df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG0 +CYDEV_UCFG_B0_P1_U1_DCFG0 EQU 0x400102e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG1 +CYDEV_UCFG_B0_P1_U1_DCFG1 EQU 0x400102e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG2 +CYDEV_UCFG_B0_P1_U1_DCFG2 EQU 0x400102e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG3 +CYDEV_UCFG_B0_P1_U1_DCFG3 EQU 0x400102e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG4 +CYDEV_UCFG_B0_P1_U1_DCFG4 EQU 0x400102e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG5 +CYDEV_UCFG_B0_P1_U1_DCFG5 EQU 0x400102ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG6 +CYDEV_UCFG_B0_P1_U1_DCFG6 EQU 0x400102ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG7 +CYDEV_UCFG_B0_P1_U1_DCFG7 EQU 0x400102ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_BASE +CYDEV_UCFG_B0_P1_ROUTE_BASE EQU 0x40010300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_SIZE +CYDEV_UCFG_B0_P1_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_BASE +CYDEV_UCFG_B0_P2_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_SIZE +CYDEV_UCFG_B0_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_BASE +CYDEV_UCFG_B0_P2_U0_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_SIZE +CYDEV_UCFG_B0_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT0 +CYDEV_UCFG_B0_P2_U0_PLD_IT0 EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT1 +CYDEV_UCFG_B0_P2_U0_PLD_IT1 EQU 0x40010404 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT2 +CYDEV_UCFG_B0_P2_U0_PLD_IT2 EQU 0x40010408 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT3 +CYDEV_UCFG_B0_P2_U0_PLD_IT3 EQU 0x4001040c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT4 +CYDEV_UCFG_B0_P2_U0_PLD_IT4 EQU 0x40010410 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT5 +CYDEV_UCFG_B0_P2_U0_PLD_IT5 EQU 0x40010414 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT6 +CYDEV_UCFG_B0_P2_U0_PLD_IT6 EQU 0x40010418 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT7 +CYDEV_UCFG_B0_P2_U0_PLD_IT7 EQU 0x4001041c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT8 +CYDEV_UCFG_B0_P2_U0_PLD_IT8 EQU 0x40010420 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT9 +CYDEV_UCFG_B0_P2_U0_PLD_IT9 EQU 0x40010424 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT10 +CYDEV_UCFG_B0_P2_U0_PLD_IT10 EQU 0x40010428 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT11 +CYDEV_UCFG_B0_P2_U0_PLD_IT11 EQU 0x4001042c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT0 +CYDEV_UCFG_B0_P2_U0_PLD_ORT0 EQU 0x40010430 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT1 +CYDEV_UCFG_B0_P2_U0_PLD_ORT1 EQU 0x40010432 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT2 +CYDEV_UCFG_B0_P2_U0_PLD_ORT2 EQU 0x40010434 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT3 +CYDEV_UCFG_B0_P2_U0_PLD_ORT3 EQU 0x40010436 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST EQU 0x40010438 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB EQU 0x4001043a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET EQU 0x4001043c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS EQU 0x4001043e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG0 +CYDEV_UCFG_B0_P2_U0_CFG0 EQU 0x40010440 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG1 +CYDEV_UCFG_B0_P2_U0_CFG1 EQU 0x40010441 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG2 +CYDEV_UCFG_B0_P2_U0_CFG2 EQU 0x40010442 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG3 +CYDEV_UCFG_B0_P2_U0_CFG3 EQU 0x40010443 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG4 +CYDEV_UCFG_B0_P2_U0_CFG4 EQU 0x40010444 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG5 +CYDEV_UCFG_B0_P2_U0_CFG5 EQU 0x40010445 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG6 +CYDEV_UCFG_B0_P2_U0_CFG6 EQU 0x40010446 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG7 +CYDEV_UCFG_B0_P2_U0_CFG7 EQU 0x40010447 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG8 +CYDEV_UCFG_B0_P2_U0_CFG8 EQU 0x40010448 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG9 +CYDEV_UCFG_B0_P2_U0_CFG9 EQU 0x40010449 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG10 +CYDEV_UCFG_B0_P2_U0_CFG10 EQU 0x4001044a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG11 +CYDEV_UCFG_B0_P2_U0_CFG11 EQU 0x4001044b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG12 +CYDEV_UCFG_B0_P2_U0_CFG12 EQU 0x4001044c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG13 +CYDEV_UCFG_B0_P2_U0_CFG13 EQU 0x4001044d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG14 +CYDEV_UCFG_B0_P2_U0_CFG14 EQU 0x4001044e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG15 +CYDEV_UCFG_B0_P2_U0_CFG15 EQU 0x4001044f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG16 +CYDEV_UCFG_B0_P2_U0_CFG16 EQU 0x40010450 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG17 +CYDEV_UCFG_B0_P2_U0_CFG17 EQU 0x40010451 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG18 +CYDEV_UCFG_B0_P2_U0_CFG18 EQU 0x40010452 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG19 +CYDEV_UCFG_B0_P2_U0_CFG19 EQU 0x40010453 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG20 +CYDEV_UCFG_B0_P2_U0_CFG20 EQU 0x40010454 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG21 +CYDEV_UCFG_B0_P2_U0_CFG21 EQU 0x40010455 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG22 +CYDEV_UCFG_B0_P2_U0_CFG22 EQU 0x40010456 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG23 +CYDEV_UCFG_B0_P2_U0_CFG23 EQU 0x40010457 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG24 +CYDEV_UCFG_B0_P2_U0_CFG24 EQU 0x40010458 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG25 +CYDEV_UCFG_B0_P2_U0_CFG25 EQU 0x40010459 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG26 +CYDEV_UCFG_B0_P2_U0_CFG26 EQU 0x4001045a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG27 +CYDEV_UCFG_B0_P2_U0_CFG27 EQU 0x4001045b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG28 +CYDEV_UCFG_B0_P2_U0_CFG28 EQU 0x4001045c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG29 +CYDEV_UCFG_B0_P2_U0_CFG29 EQU 0x4001045d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG30 +CYDEV_UCFG_B0_P2_U0_CFG30 EQU 0x4001045e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG31 +CYDEV_UCFG_B0_P2_U0_CFG31 EQU 0x4001045f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG0 +CYDEV_UCFG_B0_P2_U0_DCFG0 EQU 0x40010460 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG1 +CYDEV_UCFG_B0_P2_U0_DCFG1 EQU 0x40010462 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG2 +CYDEV_UCFG_B0_P2_U0_DCFG2 EQU 0x40010464 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG3 +CYDEV_UCFG_B0_P2_U0_DCFG3 EQU 0x40010466 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG4 +CYDEV_UCFG_B0_P2_U0_DCFG4 EQU 0x40010468 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG5 +CYDEV_UCFG_B0_P2_U0_DCFG5 EQU 0x4001046a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG6 +CYDEV_UCFG_B0_P2_U0_DCFG6 EQU 0x4001046c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG7 +CYDEV_UCFG_B0_P2_U0_DCFG7 EQU 0x4001046e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_BASE +CYDEV_UCFG_B0_P2_U1_BASE EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_SIZE +CYDEV_UCFG_B0_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT0 +CYDEV_UCFG_B0_P2_U1_PLD_IT0 EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT1 +CYDEV_UCFG_B0_P2_U1_PLD_IT1 EQU 0x40010484 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT2 +CYDEV_UCFG_B0_P2_U1_PLD_IT2 EQU 0x40010488 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT3 +CYDEV_UCFG_B0_P2_U1_PLD_IT3 EQU 0x4001048c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT4 +CYDEV_UCFG_B0_P2_U1_PLD_IT4 EQU 0x40010490 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT5 +CYDEV_UCFG_B0_P2_U1_PLD_IT5 EQU 0x40010494 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT6 +CYDEV_UCFG_B0_P2_U1_PLD_IT6 EQU 0x40010498 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT7 +CYDEV_UCFG_B0_P2_U1_PLD_IT7 EQU 0x4001049c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT8 +CYDEV_UCFG_B0_P2_U1_PLD_IT8 EQU 0x400104a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT9 +CYDEV_UCFG_B0_P2_U1_PLD_IT9 EQU 0x400104a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT10 +CYDEV_UCFG_B0_P2_U1_PLD_IT10 EQU 0x400104a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT11 +CYDEV_UCFG_B0_P2_U1_PLD_IT11 EQU 0x400104ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT0 +CYDEV_UCFG_B0_P2_U1_PLD_ORT0 EQU 0x400104b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT1 +CYDEV_UCFG_B0_P2_U1_PLD_ORT1 EQU 0x400104b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT2 +CYDEV_UCFG_B0_P2_U1_PLD_ORT2 EQU 0x400104b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT3 +CYDEV_UCFG_B0_P2_U1_PLD_ORT3 EQU 0x400104b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST EQU 0x400104b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB EQU 0x400104ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET EQU 0x400104bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS EQU 0x400104be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG0 +CYDEV_UCFG_B0_P2_U1_CFG0 EQU 0x400104c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG1 +CYDEV_UCFG_B0_P2_U1_CFG1 EQU 0x400104c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG2 +CYDEV_UCFG_B0_P2_U1_CFG2 EQU 0x400104c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG3 +CYDEV_UCFG_B0_P2_U1_CFG3 EQU 0x400104c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG4 +CYDEV_UCFG_B0_P2_U1_CFG4 EQU 0x400104c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG5 +CYDEV_UCFG_B0_P2_U1_CFG5 EQU 0x400104c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG6 +CYDEV_UCFG_B0_P2_U1_CFG6 EQU 0x400104c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG7 +CYDEV_UCFG_B0_P2_U1_CFG7 EQU 0x400104c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG8 +CYDEV_UCFG_B0_P2_U1_CFG8 EQU 0x400104c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG9 +CYDEV_UCFG_B0_P2_U1_CFG9 EQU 0x400104c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG10 +CYDEV_UCFG_B0_P2_U1_CFG10 EQU 0x400104ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG11 +CYDEV_UCFG_B0_P2_U1_CFG11 EQU 0x400104cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG12 +CYDEV_UCFG_B0_P2_U1_CFG12 EQU 0x400104cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG13 +CYDEV_UCFG_B0_P2_U1_CFG13 EQU 0x400104cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG14 +CYDEV_UCFG_B0_P2_U1_CFG14 EQU 0x400104ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG15 +CYDEV_UCFG_B0_P2_U1_CFG15 EQU 0x400104cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG16 +CYDEV_UCFG_B0_P2_U1_CFG16 EQU 0x400104d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG17 +CYDEV_UCFG_B0_P2_U1_CFG17 EQU 0x400104d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG18 +CYDEV_UCFG_B0_P2_U1_CFG18 EQU 0x400104d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG19 +CYDEV_UCFG_B0_P2_U1_CFG19 EQU 0x400104d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG20 +CYDEV_UCFG_B0_P2_U1_CFG20 EQU 0x400104d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG21 +CYDEV_UCFG_B0_P2_U1_CFG21 EQU 0x400104d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG22 +CYDEV_UCFG_B0_P2_U1_CFG22 EQU 0x400104d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG23 +CYDEV_UCFG_B0_P2_U1_CFG23 EQU 0x400104d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG24 +CYDEV_UCFG_B0_P2_U1_CFG24 EQU 0x400104d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG25 +CYDEV_UCFG_B0_P2_U1_CFG25 EQU 0x400104d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG26 +CYDEV_UCFG_B0_P2_U1_CFG26 EQU 0x400104da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG27 +CYDEV_UCFG_B0_P2_U1_CFG27 EQU 0x400104db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG28 +CYDEV_UCFG_B0_P2_U1_CFG28 EQU 0x400104dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG29 +CYDEV_UCFG_B0_P2_U1_CFG29 EQU 0x400104dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG30 +CYDEV_UCFG_B0_P2_U1_CFG30 EQU 0x400104de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG31 +CYDEV_UCFG_B0_P2_U1_CFG31 EQU 0x400104df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG0 +CYDEV_UCFG_B0_P2_U1_DCFG0 EQU 0x400104e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG1 +CYDEV_UCFG_B0_P2_U1_DCFG1 EQU 0x400104e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG2 +CYDEV_UCFG_B0_P2_U1_DCFG2 EQU 0x400104e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG3 +CYDEV_UCFG_B0_P2_U1_DCFG3 EQU 0x400104e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG4 +CYDEV_UCFG_B0_P2_U1_DCFG4 EQU 0x400104e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG5 +CYDEV_UCFG_B0_P2_U1_DCFG5 EQU 0x400104ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG6 +CYDEV_UCFG_B0_P2_U1_DCFG6 EQU 0x400104ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG7 +CYDEV_UCFG_B0_P2_U1_DCFG7 EQU 0x400104ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_BASE +CYDEV_UCFG_B0_P2_ROUTE_BASE EQU 0x40010500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_SIZE +CYDEV_UCFG_B0_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_BASE +CYDEV_UCFG_B0_P3_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_SIZE +CYDEV_UCFG_B0_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_BASE +CYDEV_UCFG_B0_P3_U0_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_SIZE +CYDEV_UCFG_B0_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT0 +CYDEV_UCFG_B0_P3_U0_PLD_IT0 EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT1 +CYDEV_UCFG_B0_P3_U0_PLD_IT1 EQU 0x40010604 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT2 +CYDEV_UCFG_B0_P3_U0_PLD_IT2 EQU 0x40010608 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT3 +CYDEV_UCFG_B0_P3_U0_PLD_IT3 EQU 0x4001060c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT4 +CYDEV_UCFG_B0_P3_U0_PLD_IT4 EQU 0x40010610 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT5 +CYDEV_UCFG_B0_P3_U0_PLD_IT5 EQU 0x40010614 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT6 +CYDEV_UCFG_B0_P3_U0_PLD_IT6 EQU 0x40010618 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT7 +CYDEV_UCFG_B0_P3_U0_PLD_IT7 EQU 0x4001061c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT8 +CYDEV_UCFG_B0_P3_U0_PLD_IT8 EQU 0x40010620 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT9 +CYDEV_UCFG_B0_P3_U0_PLD_IT9 EQU 0x40010624 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT10 +CYDEV_UCFG_B0_P3_U0_PLD_IT10 EQU 0x40010628 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT11 +CYDEV_UCFG_B0_P3_U0_PLD_IT11 EQU 0x4001062c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT0 +CYDEV_UCFG_B0_P3_U0_PLD_ORT0 EQU 0x40010630 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT1 +CYDEV_UCFG_B0_P3_U0_PLD_ORT1 EQU 0x40010632 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT2 +CYDEV_UCFG_B0_P3_U0_PLD_ORT2 EQU 0x40010634 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT3 +CYDEV_UCFG_B0_P3_U0_PLD_ORT3 EQU 0x40010636 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST EQU 0x40010638 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB EQU 0x4001063a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET EQU 0x4001063c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS EQU 0x4001063e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG0 +CYDEV_UCFG_B0_P3_U0_CFG0 EQU 0x40010640 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG1 +CYDEV_UCFG_B0_P3_U0_CFG1 EQU 0x40010641 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG2 +CYDEV_UCFG_B0_P3_U0_CFG2 EQU 0x40010642 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG3 +CYDEV_UCFG_B0_P3_U0_CFG3 EQU 0x40010643 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG4 +CYDEV_UCFG_B0_P3_U0_CFG4 EQU 0x40010644 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG5 +CYDEV_UCFG_B0_P3_U0_CFG5 EQU 0x40010645 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG6 +CYDEV_UCFG_B0_P3_U0_CFG6 EQU 0x40010646 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG7 +CYDEV_UCFG_B0_P3_U0_CFG7 EQU 0x40010647 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG8 +CYDEV_UCFG_B0_P3_U0_CFG8 EQU 0x40010648 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG9 +CYDEV_UCFG_B0_P3_U0_CFG9 EQU 0x40010649 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG10 +CYDEV_UCFG_B0_P3_U0_CFG10 EQU 0x4001064a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG11 +CYDEV_UCFG_B0_P3_U0_CFG11 EQU 0x4001064b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG12 +CYDEV_UCFG_B0_P3_U0_CFG12 EQU 0x4001064c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG13 +CYDEV_UCFG_B0_P3_U0_CFG13 EQU 0x4001064d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG14 +CYDEV_UCFG_B0_P3_U0_CFG14 EQU 0x4001064e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG15 +CYDEV_UCFG_B0_P3_U0_CFG15 EQU 0x4001064f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG16 +CYDEV_UCFG_B0_P3_U0_CFG16 EQU 0x40010650 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG17 +CYDEV_UCFG_B0_P3_U0_CFG17 EQU 0x40010651 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG18 +CYDEV_UCFG_B0_P3_U0_CFG18 EQU 0x40010652 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG19 +CYDEV_UCFG_B0_P3_U0_CFG19 EQU 0x40010653 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG20 +CYDEV_UCFG_B0_P3_U0_CFG20 EQU 0x40010654 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG21 +CYDEV_UCFG_B0_P3_U0_CFG21 EQU 0x40010655 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG22 +CYDEV_UCFG_B0_P3_U0_CFG22 EQU 0x40010656 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG23 +CYDEV_UCFG_B0_P3_U0_CFG23 EQU 0x40010657 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG24 +CYDEV_UCFG_B0_P3_U0_CFG24 EQU 0x40010658 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG25 +CYDEV_UCFG_B0_P3_U0_CFG25 EQU 0x40010659 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG26 +CYDEV_UCFG_B0_P3_U0_CFG26 EQU 0x4001065a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG27 +CYDEV_UCFG_B0_P3_U0_CFG27 EQU 0x4001065b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG28 +CYDEV_UCFG_B0_P3_U0_CFG28 EQU 0x4001065c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG29 +CYDEV_UCFG_B0_P3_U0_CFG29 EQU 0x4001065d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG30 +CYDEV_UCFG_B0_P3_U0_CFG30 EQU 0x4001065e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG31 +CYDEV_UCFG_B0_P3_U0_CFG31 EQU 0x4001065f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG0 +CYDEV_UCFG_B0_P3_U0_DCFG0 EQU 0x40010660 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG1 +CYDEV_UCFG_B0_P3_U0_DCFG1 EQU 0x40010662 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG2 +CYDEV_UCFG_B0_P3_U0_DCFG2 EQU 0x40010664 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG3 +CYDEV_UCFG_B0_P3_U0_DCFG3 EQU 0x40010666 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG4 +CYDEV_UCFG_B0_P3_U0_DCFG4 EQU 0x40010668 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG5 +CYDEV_UCFG_B0_P3_U0_DCFG5 EQU 0x4001066a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG6 +CYDEV_UCFG_B0_P3_U0_DCFG6 EQU 0x4001066c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG7 +CYDEV_UCFG_B0_P3_U0_DCFG7 EQU 0x4001066e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_BASE +CYDEV_UCFG_B0_P3_U1_BASE EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_SIZE +CYDEV_UCFG_B0_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT0 +CYDEV_UCFG_B0_P3_U1_PLD_IT0 EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT1 +CYDEV_UCFG_B0_P3_U1_PLD_IT1 EQU 0x40010684 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT2 +CYDEV_UCFG_B0_P3_U1_PLD_IT2 EQU 0x40010688 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT3 +CYDEV_UCFG_B0_P3_U1_PLD_IT3 EQU 0x4001068c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT4 +CYDEV_UCFG_B0_P3_U1_PLD_IT4 EQU 0x40010690 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT5 +CYDEV_UCFG_B0_P3_U1_PLD_IT5 EQU 0x40010694 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT6 +CYDEV_UCFG_B0_P3_U1_PLD_IT6 EQU 0x40010698 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT7 +CYDEV_UCFG_B0_P3_U1_PLD_IT7 EQU 0x4001069c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT8 +CYDEV_UCFG_B0_P3_U1_PLD_IT8 EQU 0x400106a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT9 +CYDEV_UCFG_B0_P3_U1_PLD_IT9 EQU 0x400106a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT10 +CYDEV_UCFG_B0_P3_U1_PLD_IT10 EQU 0x400106a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT11 +CYDEV_UCFG_B0_P3_U1_PLD_IT11 EQU 0x400106ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT0 +CYDEV_UCFG_B0_P3_U1_PLD_ORT0 EQU 0x400106b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT1 +CYDEV_UCFG_B0_P3_U1_PLD_ORT1 EQU 0x400106b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT2 +CYDEV_UCFG_B0_P3_U1_PLD_ORT2 EQU 0x400106b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT3 +CYDEV_UCFG_B0_P3_U1_PLD_ORT3 EQU 0x400106b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST EQU 0x400106b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB EQU 0x400106ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET EQU 0x400106bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS EQU 0x400106be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG0 +CYDEV_UCFG_B0_P3_U1_CFG0 EQU 0x400106c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG1 +CYDEV_UCFG_B0_P3_U1_CFG1 EQU 0x400106c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG2 +CYDEV_UCFG_B0_P3_U1_CFG2 EQU 0x400106c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG3 +CYDEV_UCFG_B0_P3_U1_CFG3 EQU 0x400106c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG4 +CYDEV_UCFG_B0_P3_U1_CFG4 EQU 0x400106c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG5 +CYDEV_UCFG_B0_P3_U1_CFG5 EQU 0x400106c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG6 +CYDEV_UCFG_B0_P3_U1_CFG6 EQU 0x400106c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG7 +CYDEV_UCFG_B0_P3_U1_CFG7 EQU 0x400106c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG8 +CYDEV_UCFG_B0_P3_U1_CFG8 EQU 0x400106c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG9 +CYDEV_UCFG_B0_P3_U1_CFG9 EQU 0x400106c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG10 +CYDEV_UCFG_B0_P3_U1_CFG10 EQU 0x400106ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG11 +CYDEV_UCFG_B0_P3_U1_CFG11 EQU 0x400106cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG12 +CYDEV_UCFG_B0_P3_U1_CFG12 EQU 0x400106cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG13 +CYDEV_UCFG_B0_P3_U1_CFG13 EQU 0x400106cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG14 +CYDEV_UCFG_B0_P3_U1_CFG14 EQU 0x400106ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG15 +CYDEV_UCFG_B0_P3_U1_CFG15 EQU 0x400106cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG16 +CYDEV_UCFG_B0_P3_U1_CFG16 EQU 0x400106d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG17 +CYDEV_UCFG_B0_P3_U1_CFG17 EQU 0x400106d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG18 +CYDEV_UCFG_B0_P3_U1_CFG18 EQU 0x400106d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG19 +CYDEV_UCFG_B0_P3_U1_CFG19 EQU 0x400106d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG20 +CYDEV_UCFG_B0_P3_U1_CFG20 EQU 0x400106d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG21 +CYDEV_UCFG_B0_P3_U1_CFG21 EQU 0x400106d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG22 +CYDEV_UCFG_B0_P3_U1_CFG22 EQU 0x400106d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG23 +CYDEV_UCFG_B0_P3_U1_CFG23 EQU 0x400106d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG24 +CYDEV_UCFG_B0_P3_U1_CFG24 EQU 0x400106d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG25 +CYDEV_UCFG_B0_P3_U1_CFG25 EQU 0x400106d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG26 +CYDEV_UCFG_B0_P3_U1_CFG26 EQU 0x400106da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG27 +CYDEV_UCFG_B0_P3_U1_CFG27 EQU 0x400106db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG28 +CYDEV_UCFG_B0_P3_U1_CFG28 EQU 0x400106dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG29 +CYDEV_UCFG_B0_P3_U1_CFG29 EQU 0x400106dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG30 +CYDEV_UCFG_B0_P3_U1_CFG30 EQU 0x400106de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG31 +CYDEV_UCFG_B0_P3_U1_CFG31 EQU 0x400106df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG0 +CYDEV_UCFG_B0_P3_U1_DCFG0 EQU 0x400106e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG1 +CYDEV_UCFG_B0_P3_U1_DCFG1 EQU 0x400106e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG2 +CYDEV_UCFG_B0_P3_U1_DCFG2 EQU 0x400106e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG3 +CYDEV_UCFG_B0_P3_U1_DCFG3 EQU 0x400106e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG4 +CYDEV_UCFG_B0_P3_U1_DCFG4 EQU 0x400106e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG5 +CYDEV_UCFG_B0_P3_U1_DCFG5 EQU 0x400106ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG6 +CYDEV_UCFG_B0_P3_U1_DCFG6 EQU 0x400106ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG7 +CYDEV_UCFG_B0_P3_U1_DCFG7 EQU 0x400106ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_BASE +CYDEV_UCFG_B0_P3_ROUTE_BASE EQU 0x40010700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_SIZE +CYDEV_UCFG_B0_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_BASE +CYDEV_UCFG_B0_P4_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_SIZE +CYDEV_UCFG_B0_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_BASE +CYDEV_UCFG_B0_P4_U0_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_SIZE +CYDEV_UCFG_B0_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT0 +CYDEV_UCFG_B0_P4_U0_PLD_IT0 EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT1 +CYDEV_UCFG_B0_P4_U0_PLD_IT1 EQU 0x40010804 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT2 +CYDEV_UCFG_B0_P4_U0_PLD_IT2 EQU 0x40010808 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT3 +CYDEV_UCFG_B0_P4_U0_PLD_IT3 EQU 0x4001080c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT4 +CYDEV_UCFG_B0_P4_U0_PLD_IT4 EQU 0x40010810 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT5 +CYDEV_UCFG_B0_P4_U0_PLD_IT5 EQU 0x40010814 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT6 +CYDEV_UCFG_B0_P4_U0_PLD_IT6 EQU 0x40010818 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT7 +CYDEV_UCFG_B0_P4_U0_PLD_IT7 EQU 0x4001081c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT8 +CYDEV_UCFG_B0_P4_U0_PLD_IT8 EQU 0x40010820 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT9 +CYDEV_UCFG_B0_P4_U0_PLD_IT9 EQU 0x40010824 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT10 +CYDEV_UCFG_B0_P4_U0_PLD_IT10 EQU 0x40010828 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT11 +CYDEV_UCFG_B0_P4_U0_PLD_IT11 EQU 0x4001082c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT0 +CYDEV_UCFG_B0_P4_U0_PLD_ORT0 EQU 0x40010830 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT1 +CYDEV_UCFG_B0_P4_U0_PLD_ORT1 EQU 0x40010832 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT2 +CYDEV_UCFG_B0_P4_U0_PLD_ORT2 EQU 0x40010834 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT3 +CYDEV_UCFG_B0_P4_U0_PLD_ORT3 EQU 0x40010836 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST EQU 0x40010838 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB EQU 0x4001083a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET EQU 0x4001083c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS EQU 0x4001083e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG0 +CYDEV_UCFG_B0_P4_U0_CFG0 EQU 0x40010840 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG1 +CYDEV_UCFG_B0_P4_U0_CFG1 EQU 0x40010841 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG2 +CYDEV_UCFG_B0_P4_U0_CFG2 EQU 0x40010842 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG3 +CYDEV_UCFG_B0_P4_U0_CFG3 EQU 0x40010843 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG4 +CYDEV_UCFG_B0_P4_U0_CFG4 EQU 0x40010844 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG5 +CYDEV_UCFG_B0_P4_U0_CFG5 EQU 0x40010845 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG6 +CYDEV_UCFG_B0_P4_U0_CFG6 EQU 0x40010846 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG7 +CYDEV_UCFG_B0_P4_U0_CFG7 EQU 0x40010847 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG8 +CYDEV_UCFG_B0_P4_U0_CFG8 EQU 0x40010848 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG9 +CYDEV_UCFG_B0_P4_U0_CFG9 EQU 0x40010849 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG10 +CYDEV_UCFG_B0_P4_U0_CFG10 EQU 0x4001084a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG11 +CYDEV_UCFG_B0_P4_U0_CFG11 EQU 0x4001084b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG12 +CYDEV_UCFG_B0_P4_U0_CFG12 EQU 0x4001084c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG13 +CYDEV_UCFG_B0_P4_U0_CFG13 EQU 0x4001084d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG14 +CYDEV_UCFG_B0_P4_U0_CFG14 EQU 0x4001084e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG15 +CYDEV_UCFG_B0_P4_U0_CFG15 EQU 0x4001084f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG16 +CYDEV_UCFG_B0_P4_U0_CFG16 EQU 0x40010850 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG17 +CYDEV_UCFG_B0_P4_U0_CFG17 EQU 0x40010851 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG18 +CYDEV_UCFG_B0_P4_U0_CFG18 EQU 0x40010852 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG19 +CYDEV_UCFG_B0_P4_U0_CFG19 EQU 0x40010853 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG20 +CYDEV_UCFG_B0_P4_U0_CFG20 EQU 0x40010854 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG21 +CYDEV_UCFG_B0_P4_U0_CFG21 EQU 0x40010855 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG22 +CYDEV_UCFG_B0_P4_U0_CFG22 EQU 0x40010856 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG23 +CYDEV_UCFG_B0_P4_U0_CFG23 EQU 0x40010857 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG24 +CYDEV_UCFG_B0_P4_U0_CFG24 EQU 0x40010858 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG25 +CYDEV_UCFG_B0_P4_U0_CFG25 EQU 0x40010859 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG26 +CYDEV_UCFG_B0_P4_U0_CFG26 EQU 0x4001085a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG27 +CYDEV_UCFG_B0_P4_U0_CFG27 EQU 0x4001085b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG28 +CYDEV_UCFG_B0_P4_U0_CFG28 EQU 0x4001085c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG29 +CYDEV_UCFG_B0_P4_U0_CFG29 EQU 0x4001085d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG30 +CYDEV_UCFG_B0_P4_U0_CFG30 EQU 0x4001085e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG31 +CYDEV_UCFG_B0_P4_U0_CFG31 EQU 0x4001085f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG0 +CYDEV_UCFG_B0_P4_U0_DCFG0 EQU 0x40010860 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG1 +CYDEV_UCFG_B0_P4_U0_DCFG1 EQU 0x40010862 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG2 +CYDEV_UCFG_B0_P4_U0_DCFG2 EQU 0x40010864 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG3 +CYDEV_UCFG_B0_P4_U0_DCFG3 EQU 0x40010866 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG4 +CYDEV_UCFG_B0_P4_U0_DCFG4 EQU 0x40010868 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG5 +CYDEV_UCFG_B0_P4_U0_DCFG5 EQU 0x4001086a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG6 +CYDEV_UCFG_B0_P4_U0_DCFG6 EQU 0x4001086c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG7 +CYDEV_UCFG_B0_P4_U0_DCFG7 EQU 0x4001086e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_BASE +CYDEV_UCFG_B0_P4_U1_BASE EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_SIZE +CYDEV_UCFG_B0_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT0 +CYDEV_UCFG_B0_P4_U1_PLD_IT0 EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT1 +CYDEV_UCFG_B0_P4_U1_PLD_IT1 EQU 0x40010884 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT2 +CYDEV_UCFG_B0_P4_U1_PLD_IT2 EQU 0x40010888 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT3 +CYDEV_UCFG_B0_P4_U1_PLD_IT3 EQU 0x4001088c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT4 +CYDEV_UCFG_B0_P4_U1_PLD_IT4 EQU 0x40010890 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT5 +CYDEV_UCFG_B0_P4_U1_PLD_IT5 EQU 0x40010894 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT6 +CYDEV_UCFG_B0_P4_U1_PLD_IT6 EQU 0x40010898 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT7 +CYDEV_UCFG_B0_P4_U1_PLD_IT7 EQU 0x4001089c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT8 +CYDEV_UCFG_B0_P4_U1_PLD_IT8 EQU 0x400108a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT9 +CYDEV_UCFG_B0_P4_U1_PLD_IT9 EQU 0x400108a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT10 +CYDEV_UCFG_B0_P4_U1_PLD_IT10 EQU 0x400108a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT11 +CYDEV_UCFG_B0_P4_U1_PLD_IT11 EQU 0x400108ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT0 +CYDEV_UCFG_B0_P4_U1_PLD_ORT0 EQU 0x400108b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT1 +CYDEV_UCFG_B0_P4_U1_PLD_ORT1 EQU 0x400108b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT2 +CYDEV_UCFG_B0_P4_U1_PLD_ORT2 EQU 0x400108b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT3 +CYDEV_UCFG_B0_P4_U1_PLD_ORT3 EQU 0x400108b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST EQU 0x400108b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB EQU 0x400108ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET EQU 0x400108bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS EQU 0x400108be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG0 +CYDEV_UCFG_B0_P4_U1_CFG0 EQU 0x400108c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG1 +CYDEV_UCFG_B0_P4_U1_CFG1 EQU 0x400108c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG2 +CYDEV_UCFG_B0_P4_U1_CFG2 EQU 0x400108c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG3 +CYDEV_UCFG_B0_P4_U1_CFG3 EQU 0x400108c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG4 +CYDEV_UCFG_B0_P4_U1_CFG4 EQU 0x400108c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG5 +CYDEV_UCFG_B0_P4_U1_CFG5 EQU 0x400108c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG6 +CYDEV_UCFG_B0_P4_U1_CFG6 EQU 0x400108c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG7 +CYDEV_UCFG_B0_P4_U1_CFG7 EQU 0x400108c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG8 +CYDEV_UCFG_B0_P4_U1_CFG8 EQU 0x400108c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG9 +CYDEV_UCFG_B0_P4_U1_CFG9 EQU 0x400108c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG10 +CYDEV_UCFG_B0_P4_U1_CFG10 EQU 0x400108ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG11 +CYDEV_UCFG_B0_P4_U1_CFG11 EQU 0x400108cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG12 +CYDEV_UCFG_B0_P4_U1_CFG12 EQU 0x400108cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG13 +CYDEV_UCFG_B0_P4_U1_CFG13 EQU 0x400108cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG14 +CYDEV_UCFG_B0_P4_U1_CFG14 EQU 0x400108ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG15 +CYDEV_UCFG_B0_P4_U1_CFG15 EQU 0x400108cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG16 +CYDEV_UCFG_B0_P4_U1_CFG16 EQU 0x400108d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG17 +CYDEV_UCFG_B0_P4_U1_CFG17 EQU 0x400108d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG18 +CYDEV_UCFG_B0_P4_U1_CFG18 EQU 0x400108d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG19 +CYDEV_UCFG_B0_P4_U1_CFG19 EQU 0x400108d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG20 +CYDEV_UCFG_B0_P4_U1_CFG20 EQU 0x400108d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG21 +CYDEV_UCFG_B0_P4_U1_CFG21 EQU 0x400108d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG22 +CYDEV_UCFG_B0_P4_U1_CFG22 EQU 0x400108d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG23 +CYDEV_UCFG_B0_P4_U1_CFG23 EQU 0x400108d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG24 +CYDEV_UCFG_B0_P4_U1_CFG24 EQU 0x400108d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG25 +CYDEV_UCFG_B0_P4_U1_CFG25 EQU 0x400108d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG26 +CYDEV_UCFG_B0_P4_U1_CFG26 EQU 0x400108da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG27 +CYDEV_UCFG_B0_P4_U1_CFG27 EQU 0x400108db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG28 +CYDEV_UCFG_B0_P4_U1_CFG28 EQU 0x400108dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG29 +CYDEV_UCFG_B0_P4_U1_CFG29 EQU 0x400108dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG30 +CYDEV_UCFG_B0_P4_U1_CFG30 EQU 0x400108de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG31 +CYDEV_UCFG_B0_P4_U1_CFG31 EQU 0x400108df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG0 +CYDEV_UCFG_B0_P4_U1_DCFG0 EQU 0x400108e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG1 +CYDEV_UCFG_B0_P4_U1_DCFG1 EQU 0x400108e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG2 +CYDEV_UCFG_B0_P4_U1_DCFG2 EQU 0x400108e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG3 +CYDEV_UCFG_B0_P4_U1_DCFG3 EQU 0x400108e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG4 +CYDEV_UCFG_B0_P4_U1_DCFG4 EQU 0x400108e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG5 +CYDEV_UCFG_B0_P4_U1_DCFG5 EQU 0x400108ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG6 +CYDEV_UCFG_B0_P4_U1_DCFG6 EQU 0x400108ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG7 +CYDEV_UCFG_B0_P4_U1_DCFG7 EQU 0x400108ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_BASE +CYDEV_UCFG_B0_P4_ROUTE_BASE EQU 0x40010900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_SIZE +CYDEV_UCFG_B0_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_BASE +CYDEV_UCFG_B0_P5_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_SIZE +CYDEV_UCFG_B0_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_BASE +CYDEV_UCFG_B0_P5_U0_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_SIZE +CYDEV_UCFG_B0_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT0 +CYDEV_UCFG_B0_P5_U0_PLD_IT0 EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT1 +CYDEV_UCFG_B0_P5_U0_PLD_IT1 EQU 0x40010a04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT2 +CYDEV_UCFG_B0_P5_U0_PLD_IT2 EQU 0x40010a08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT3 +CYDEV_UCFG_B0_P5_U0_PLD_IT3 EQU 0x40010a0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT4 +CYDEV_UCFG_B0_P5_U0_PLD_IT4 EQU 0x40010a10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT5 +CYDEV_UCFG_B0_P5_U0_PLD_IT5 EQU 0x40010a14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT6 +CYDEV_UCFG_B0_P5_U0_PLD_IT6 EQU 0x40010a18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT7 +CYDEV_UCFG_B0_P5_U0_PLD_IT7 EQU 0x40010a1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT8 +CYDEV_UCFG_B0_P5_U0_PLD_IT8 EQU 0x40010a20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT9 +CYDEV_UCFG_B0_P5_U0_PLD_IT9 EQU 0x40010a24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT10 +CYDEV_UCFG_B0_P5_U0_PLD_IT10 EQU 0x40010a28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT11 +CYDEV_UCFG_B0_P5_U0_PLD_IT11 EQU 0x40010a2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT0 +CYDEV_UCFG_B0_P5_U0_PLD_ORT0 EQU 0x40010a30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT1 +CYDEV_UCFG_B0_P5_U0_PLD_ORT1 EQU 0x40010a32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT2 +CYDEV_UCFG_B0_P5_U0_PLD_ORT2 EQU 0x40010a34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT3 +CYDEV_UCFG_B0_P5_U0_PLD_ORT3 EQU 0x40010a36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST EQU 0x40010a38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB EQU 0x40010a3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET EQU 0x40010a3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS EQU 0x40010a3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG0 +CYDEV_UCFG_B0_P5_U0_CFG0 EQU 0x40010a40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG1 +CYDEV_UCFG_B0_P5_U0_CFG1 EQU 0x40010a41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG2 +CYDEV_UCFG_B0_P5_U0_CFG2 EQU 0x40010a42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG3 +CYDEV_UCFG_B0_P5_U0_CFG3 EQU 0x40010a43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG4 +CYDEV_UCFG_B0_P5_U0_CFG4 EQU 0x40010a44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG5 +CYDEV_UCFG_B0_P5_U0_CFG5 EQU 0x40010a45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG6 +CYDEV_UCFG_B0_P5_U0_CFG6 EQU 0x40010a46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG7 +CYDEV_UCFG_B0_P5_U0_CFG7 EQU 0x40010a47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG8 +CYDEV_UCFG_B0_P5_U0_CFG8 EQU 0x40010a48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG9 +CYDEV_UCFG_B0_P5_U0_CFG9 EQU 0x40010a49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG10 +CYDEV_UCFG_B0_P5_U0_CFG10 EQU 0x40010a4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG11 +CYDEV_UCFG_B0_P5_U0_CFG11 EQU 0x40010a4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG12 +CYDEV_UCFG_B0_P5_U0_CFG12 EQU 0x40010a4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG13 +CYDEV_UCFG_B0_P5_U0_CFG13 EQU 0x40010a4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG14 +CYDEV_UCFG_B0_P5_U0_CFG14 EQU 0x40010a4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG15 +CYDEV_UCFG_B0_P5_U0_CFG15 EQU 0x40010a4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG16 +CYDEV_UCFG_B0_P5_U0_CFG16 EQU 0x40010a50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG17 +CYDEV_UCFG_B0_P5_U0_CFG17 EQU 0x40010a51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG18 +CYDEV_UCFG_B0_P5_U0_CFG18 EQU 0x40010a52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG19 +CYDEV_UCFG_B0_P5_U0_CFG19 EQU 0x40010a53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG20 +CYDEV_UCFG_B0_P5_U0_CFG20 EQU 0x40010a54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG21 +CYDEV_UCFG_B0_P5_U0_CFG21 EQU 0x40010a55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG22 +CYDEV_UCFG_B0_P5_U0_CFG22 EQU 0x40010a56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG23 +CYDEV_UCFG_B0_P5_U0_CFG23 EQU 0x40010a57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG24 +CYDEV_UCFG_B0_P5_U0_CFG24 EQU 0x40010a58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG25 +CYDEV_UCFG_B0_P5_U0_CFG25 EQU 0x40010a59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG26 +CYDEV_UCFG_B0_P5_U0_CFG26 EQU 0x40010a5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG27 +CYDEV_UCFG_B0_P5_U0_CFG27 EQU 0x40010a5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG28 +CYDEV_UCFG_B0_P5_U0_CFG28 EQU 0x40010a5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG29 +CYDEV_UCFG_B0_P5_U0_CFG29 EQU 0x40010a5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG30 +CYDEV_UCFG_B0_P5_U0_CFG30 EQU 0x40010a5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG31 +CYDEV_UCFG_B0_P5_U0_CFG31 EQU 0x40010a5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG0 +CYDEV_UCFG_B0_P5_U0_DCFG0 EQU 0x40010a60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG1 +CYDEV_UCFG_B0_P5_U0_DCFG1 EQU 0x40010a62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG2 +CYDEV_UCFG_B0_P5_U0_DCFG2 EQU 0x40010a64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG3 +CYDEV_UCFG_B0_P5_U0_DCFG3 EQU 0x40010a66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG4 +CYDEV_UCFG_B0_P5_U0_DCFG4 EQU 0x40010a68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG5 +CYDEV_UCFG_B0_P5_U0_DCFG5 EQU 0x40010a6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG6 +CYDEV_UCFG_B0_P5_U0_DCFG6 EQU 0x40010a6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG7 +CYDEV_UCFG_B0_P5_U0_DCFG7 EQU 0x40010a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_BASE +CYDEV_UCFG_B0_P5_U1_BASE EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_SIZE +CYDEV_UCFG_B0_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT0 +CYDEV_UCFG_B0_P5_U1_PLD_IT0 EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT1 +CYDEV_UCFG_B0_P5_U1_PLD_IT1 EQU 0x40010a84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT2 +CYDEV_UCFG_B0_P5_U1_PLD_IT2 EQU 0x40010a88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT3 +CYDEV_UCFG_B0_P5_U1_PLD_IT3 EQU 0x40010a8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT4 +CYDEV_UCFG_B0_P5_U1_PLD_IT4 EQU 0x40010a90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT5 +CYDEV_UCFG_B0_P5_U1_PLD_IT5 EQU 0x40010a94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT6 +CYDEV_UCFG_B0_P5_U1_PLD_IT6 EQU 0x40010a98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT7 +CYDEV_UCFG_B0_P5_U1_PLD_IT7 EQU 0x40010a9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT8 +CYDEV_UCFG_B0_P5_U1_PLD_IT8 EQU 0x40010aa0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT9 +CYDEV_UCFG_B0_P5_U1_PLD_IT9 EQU 0x40010aa4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT10 +CYDEV_UCFG_B0_P5_U1_PLD_IT10 EQU 0x40010aa8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT11 +CYDEV_UCFG_B0_P5_U1_PLD_IT11 EQU 0x40010aac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT0 +CYDEV_UCFG_B0_P5_U1_PLD_ORT0 EQU 0x40010ab0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT1 +CYDEV_UCFG_B0_P5_U1_PLD_ORT1 EQU 0x40010ab2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT2 +CYDEV_UCFG_B0_P5_U1_PLD_ORT2 EQU 0x40010ab4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT3 +CYDEV_UCFG_B0_P5_U1_PLD_ORT3 EQU 0x40010ab6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST EQU 0x40010ab8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB EQU 0x40010aba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET EQU 0x40010abc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS EQU 0x40010abe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG0 +CYDEV_UCFG_B0_P5_U1_CFG0 EQU 0x40010ac0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG1 +CYDEV_UCFG_B0_P5_U1_CFG1 EQU 0x40010ac1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG2 +CYDEV_UCFG_B0_P5_U1_CFG2 EQU 0x40010ac2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG3 +CYDEV_UCFG_B0_P5_U1_CFG3 EQU 0x40010ac3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG4 +CYDEV_UCFG_B0_P5_U1_CFG4 EQU 0x40010ac4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG5 +CYDEV_UCFG_B0_P5_U1_CFG5 EQU 0x40010ac5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG6 +CYDEV_UCFG_B0_P5_U1_CFG6 EQU 0x40010ac6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG7 +CYDEV_UCFG_B0_P5_U1_CFG7 EQU 0x40010ac7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG8 +CYDEV_UCFG_B0_P5_U1_CFG8 EQU 0x40010ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG9 +CYDEV_UCFG_B0_P5_U1_CFG9 EQU 0x40010ac9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG10 +CYDEV_UCFG_B0_P5_U1_CFG10 EQU 0x40010aca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG11 +CYDEV_UCFG_B0_P5_U1_CFG11 EQU 0x40010acb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG12 +CYDEV_UCFG_B0_P5_U1_CFG12 EQU 0x40010acc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG13 +CYDEV_UCFG_B0_P5_U1_CFG13 EQU 0x40010acd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG14 +CYDEV_UCFG_B0_P5_U1_CFG14 EQU 0x40010ace + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG15 +CYDEV_UCFG_B0_P5_U1_CFG15 EQU 0x40010acf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG16 +CYDEV_UCFG_B0_P5_U1_CFG16 EQU 0x40010ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG17 +CYDEV_UCFG_B0_P5_U1_CFG17 EQU 0x40010ad1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG18 +CYDEV_UCFG_B0_P5_U1_CFG18 EQU 0x40010ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG19 +CYDEV_UCFG_B0_P5_U1_CFG19 EQU 0x40010ad3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG20 +CYDEV_UCFG_B0_P5_U1_CFG20 EQU 0x40010ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG21 +CYDEV_UCFG_B0_P5_U1_CFG21 EQU 0x40010ad5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG22 +CYDEV_UCFG_B0_P5_U1_CFG22 EQU 0x40010ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG23 +CYDEV_UCFG_B0_P5_U1_CFG23 EQU 0x40010ad7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG24 +CYDEV_UCFG_B0_P5_U1_CFG24 EQU 0x40010ad8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG25 +CYDEV_UCFG_B0_P5_U1_CFG25 EQU 0x40010ad9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG26 +CYDEV_UCFG_B0_P5_U1_CFG26 EQU 0x40010ada + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG27 +CYDEV_UCFG_B0_P5_U1_CFG27 EQU 0x40010adb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG28 +CYDEV_UCFG_B0_P5_U1_CFG28 EQU 0x40010adc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG29 +CYDEV_UCFG_B0_P5_U1_CFG29 EQU 0x40010add + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG30 +CYDEV_UCFG_B0_P5_U1_CFG30 EQU 0x40010ade + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG31 +CYDEV_UCFG_B0_P5_U1_CFG31 EQU 0x40010adf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG0 +CYDEV_UCFG_B0_P5_U1_DCFG0 EQU 0x40010ae0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG1 +CYDEV_UCFG_B0_P5_U1_DCFG1 EQU 0x40010ae2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG2 +CYDEV_UCFG_B0_P5_U1_DCFG2 EQU 0x40010ae4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG3 +CYDEV_UCFG_B0_P5_U1_DCFG3 EQU 0x40010ae6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG4 +CYDEV_UCFG_B0_P5_U1_DCFG4 EQU 0x40010ae8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG5 +CYDEV_UCFG_B0_P5_U1_DCFG5 EQU 0x40010aea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG6 +CYDEV_UCFG_B0_P5_U1_DCFG6 EQU 0x40010aec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG7 +CYDEV_UCFG_B0_P5_U1_DCFG7 EQU 0x40010aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_BASE +CYDEV_UCFG_B0_P5_ROUTE_BASE EQU 0x40010b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_SIZE +CYDEV_UCFG_B0_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_BASE +CYDEV_UCFG_B0_P6_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_SIZE +CYDEV_UCFG_B0_P6_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_BASE +CYDEV_UCFG_B0_P6_U0_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_SIZE +CYDEV_UCFG_B0_P6_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT0 +CYDEV_UCFG_B0_P6_U0_PLD_IT0 EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT1 +CYDEV_UCFG_B0_P6_U0_PLD_IT1 EQU 0x40010c04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT2 +CYDEV_UCFG_B0_P6_U0_PLD_IT2 EQU 0x40010c08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT3 +CYDEV_UCFG_B0_P6_U0_PLD_IT3 EQU 0x40010c0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT4 +CYDEV_UCFG_B0_P6_U0_PLD_IT4 EQU 0x40010c10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT5 +CYDEV_UCFG_B0_P6_U0_PLD_IT5 EQU 0x40010c14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT6 +CYDEV_UCFG_B0_P6_U0_PLD_IT6 EQU 0x40010c18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT7 +CYDEV_UCFG_B0_P6_U0_PLD_IT7 EQU 0x40010c1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT8 +CYDEV_UCFG_B0_P6_U0_PLD_IT8 EQU 0x40010c20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT9 +CYDEV_UCFG_B0_P6_U0_PLD_IT9 EQU 0x40010c24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT10 +CYDEV_UCFG_B0_P6_U0_PLD_IT10 EQU 0x40010c28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT11 +CYDEV_UCFG_B0_P6_U0_PLD_IT11 EQU 0x40010c2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT0 +CYDEV_UCFG_B0_P6_U0_PLD_ORT0 EQU 0x40010c30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT1 +CYDEV_UCFG_B0_P6_U0_PLD_ORT1 EQU 0x40010c32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT2 +CYDEV_UCFG_B0_P6_U0_PLD_ORT2 EQU 0x40010c34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT3 +CYDEV_UCFG_B0_P6_U0_PLD_ORT3 EQU 0x40010c36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST EQU 0x40010c38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB EQU 0x40010c3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET EQU 0x40010c3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS EQU 0x40010c3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG0 +CYDEV_UCFG_B0_P6_U0_CFG0 EQU 0x40010c40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG1 +CYDEV_UCFG_B0_P6_U0_CFG1 EQU 0x40010c41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG2 +CYDEV_UCFG_B0_P6_U0_CFG2 EQU 0x40010c42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG3 +CYDEV_UCFG_B0_P6_U0_CFG3 EQU 0x40010c43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG4 +CYDEV_UCFG_B0_P6_U0_CFG4 EQU 0x40010c44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG5 +CYDEV_UCFG_B0_P6_U0_CFG5 EQU 0x40010c45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG6 +CYDEV_UCFG_B0_P6_U0_CFG6 EQU 0x40010c46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG7 +CYDEV_UCFG_B0_P6_U0_CFG7 EQU 0x40010c47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG8 +CYDEV_UCFG_B0_P6_U0_CFG8 EQU 0x40010c48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG9 +CYDEV_UCFG_B0_P6_U0_CFG9 EQU 0x40010c49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG10 +CYDEV_UCFG_B0_P6_U0_CFG10 EQU 0x40010c4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG11 +CYDEV_UCFG_B0_P6_U0_CFG11 EQU 0x40010c4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG12 +CYDEV_UCFG_B0_P6_U0_CFG12 EQU 0x40010c4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG13 +CYDEV_UCFG_B0_P6_U0_CFG13 EQU 0x40010c4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG14 +CYDEV_UCFG_B0_P6_U0_CFG14 EQU 0x40010c4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG15 +CYDEV_UCFG_B0_P6_U0_CFG15 EQU 0x40010c4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG16 +CYDEV_UCFG_B0_P6_U0_CFG16 EQU 0x40010c50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG17 +CYDEV_UCFG_B0_P6_U0_CFG17 EQU 0x40010c51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG18 +CYDEV_UCFG_B0_P6_U0_CFG18 EQU 0x40010c52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG19 +CYDEV_UCFG_B0_P6_U0_CFG19 EQU 0x40010c53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG20 +CYDEV_UCFG_B0_P6_U0_CFG20 EQU 0x40010c54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG21 +CYDEV_UCFG_B0_P6_U0_CFG21 EQU 0x40010c55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG22 +CYDEV_UCFG_B0_P6_U0_CFG22 EQU 0x40010c56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG23 +CYDEV_UCFG_B0_P6_U0_CFG23 EQU 0x40010c57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG24 +CYDEV_UCFG_B0_P6_U0_CFG24 EQU 0x40010c58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG25 +CYDEV_UCFG_B0_P6_U0_CFG25 EQU 0x40010c59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG26 +CYDEV_UCFG_B0_P6_U0_CFG26 EQU 0x40010c5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG27 +CYDEV_UCFG_B0_P6_U0_CFG27 EQU 0x40010c5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG28 +CYDEV_UCFG_B0_P6_U0_CFG28 EQU 0x40010c5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG29 +CYDEV_UCFG_B0_P6_U0_CFG29 EQU 0x40010c5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG30 +CYDEV_UCFG_B0_P6_U0_CFG30 EQU 0x40010c5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG31 +CYDEV_UCFG_B0_P6_U0_CFG31 EQU 0x40010c5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG0 +CYDEV_UCFG_B0_P6_U0_DCFG0 EQU 0x40010c60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG1 +CYDEV_UCFG_B0_P6_U0_DCFG1 EQU 0x40010c62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG2 +CYDEV_UCFG_B0_P6_U0_DCFG2 EQU 0x40010c64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG3 +CYDEV_UCFG_B0_P6_U0_DCFG3 EQU 0x40010c66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG4 +CYDEV_UCFG_B0_P6_U0_DCFG4 EQU 0x40010c68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG5 +CYDEV_UCFG_B0_P6_U0_DCFG5 EQU 0x40010c6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG6 +CYDEV_UCFG_B0_P6_U0_DCFG6 EQU 0x40010c6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG7 +CYDEV_UCFG_B0_P6_U0_DCFG7 EQU 0x40010c6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_BASE +CYDEV_UCFG_B0_P6_U1_BASE EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_SIZE +CYDEV_UCFG_B0_P6_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT0 +CYDEV_UCFG_B0_P6_U1_PLD_IT0 EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT1 +CYDEV_UCFG_B0_P6_U1_PLD_IT1 EQU 0x40010c84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT2 +CYDEV_UCFG_B0_P6_U1_PLD_IT2 EQU 0x40010c88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT3 +CYDEV_UCFG_B0_P6_U1_PLD_IT3 EQU 0x40010c8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT4 +CYDEV_UCFG_B0_P6_U1_PLD_IT4 EQU 0x40010c90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT5 +CYDEV_UCFG_B0_P6_U1_PLD_IT5 EQU 0x40010c94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT6 +CYDEV_UCFG_B0_P6_U1_PLD_IT6 EQU 0x40010c98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT7 +CYDEV_UCFG_B0_P6_U1_PLD_IT7 EQU 0x40010c9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT8 +CYDEV_UCFG_B0_P6_U1_PLD_IT8 EQU 0x40010ca0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT9 +CYDEV_UCFG_B0_P6_U1_PLD_IT9 EQU 0x40010ca4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT10 +CYDEV_UCFG_B0_P6_U1_PLD_IT10 EQU 0x40010ca8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT11 +CYDEV_UCFG_B0_P6_U1_PLD_IT11 EQU 0x40010cac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT0 +CYDEV_UCFG_B0_P6_U1_PLD_ORT0 EQU 0x40010cb0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT1 +CYDEV_UCFG_B0_P6_U1_PLD_ORT1 EQU 0x40010cb2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT2 +CYDEV_UCFG_B0_P6_U1_PLD_ORT2 EQU 0x40010cb4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT3 +CYDEV_UCFG_B0_P6_U1_PLD_ORT3 EQU 0x40010cb6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST EQU 0x40010cb8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB EQU 0x40010cba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET EQU 0x40010cbc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS EQU 0x40010cbe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG0 +CYDEV_UCFG_B0_P6_U1_CFG0 EQU 0x40010cc0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG1 +CYDEV_UCFG_B0_P6_U1_CFG1 EQU 0x40010cc1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG2 +CYDEV_UCFG_B0_P6_U1_CFG2 EQU 0x40010cc2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG3 +CYDEV_UCFG_B0_P6_U1_CFG3 EQU 0x40010cc3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG4 +CYDEV_UCFG_B0_P6_U1_CFG4 EQU 0x40010cc4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG5 +CYDEV_UCFG_B0_P6_U1_CFG5 EQU 0x40010cc5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG6 +CYDEV_UCFG_B0_P6_U1_CFG6 EQU 0x40010cc6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG7 +CYDEV_UCFG_B0_P6_U1_CFG7 EQU 0x40010cc7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG8 +CYDEV_UCFG_B0_P6_U1_CFG8 EQU 0x40010cc8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG9 +CYDEV_UCFG_B0_P6_U1_CFG9 EQU 0x40010cc9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG10 +CYDEV_UCFG_B0_P6_U1_CFG10 EQU 0x40010cca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG11 +CYDEV_UCFG_B0_P6_U1_CFG11 EQU 0x40010ccb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG12 +CYDEV_UCFG_B0_P6_U1_CFG12 EQU 0x40010ccc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG13 +CYDEV_UCFG_B0_P6_U1_CFG13 EQU 0x40010ccd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG14 +CYDEV_UCFG_B0_P6_U1_CFG14 EQU 0x40010cce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG15 +CYDEV_UCFG_B0_P6_U1_CFG15 EQU 0x40010ccf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG16 +CYDEV_UCFG_B0_P6_U1_CFG16 EQU 0x40010cd0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG17 +CYDEV_UCFG_B0_P6_U1_CFG17 EQU 0x40010cd1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG18 +CYDEV_UCFG_B0_P6_U1_CFG18 EQU 0x40010cd2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG19 +CYDEV_UCFG_B0_P6_U1_CFG19 EQU 0x40010cd3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG20 +CYDEV_UCFG_B0_P6_U1_CFG20 EQU 0x40010cd4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG21 +CYDEV_UCFG_B0_P6_U1_CFG21 EQU 0x40010cd5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG22 +CYDEV_UCFG_B0_P6_U1_CFG22 EQU 0x40010cd6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG23 +CYDEV_UCFG_B0_P6_U1_CFG23 EQU 0x40010cd7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG24 +CYDEV_UCFG_B0_P6_U1_CFG24 EQU 0x40010cd8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG25 +CYDEV_UCFG_B0_P6_U1_CFG25 EQU 0x40010cd9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG26 +CYDEV_UCFG_B0_P6_U1_CFG26 EQU 0x40010cda + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG27 +CYDEV_UCFG_B0_P6_U1_CFG27 EQU 0x40010cdb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG28 +CYDEV_UCFG_B0_P6_U1_CFG28 EQU 0x40010cdc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG29 +CYDEV_UCFG_B0_P6_U1_CFG29 EQU 0x40010cdd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG30 +CYDEV_UCFG_B0_P6_U1_CFG30 EQU 0x40010cde + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG31 +CYDEV_UCFG_B0_P6_U1_CFG31 EQU 0x40010cdf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG0 +CYDEV_UCFG_B0_P6_U1_DCFG0 EQU 0x40010ce0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG1 +CYDEV_UCFG_B0_P6_U1_DCFG1 EQU 0x40010ce2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG2 +CYDEV_UCFG_B0_P6_U1_DCFG2 EQU 0x40010ce4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG3 +CYDEV_UCFG_B0_P6_U1_DCFG3 EQU 0x40010ce6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG4 +CYDEV_UCFG_B0_P6_U1_DCFG4 EQU 0x40010ce8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG5 +CYDEV_UCFG_B0_P6_U1_DCFG5 EQU 0x40010cea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG6 +CYDEV_UCFG_B0_P6_U1_DCFG6 EQU 0x40010cec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG7 +CYDEV_UCFG_B0_P6_U1_DCFG7 EQU 0x40010cee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_BASE +CYDEV_UCFG_B0_P6_ROUTE_BASE EQU 0x40010d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_SIZE +CYDEV_UCFG_B0_P6_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_BASE +CYDEV_UCFG_B0_P7_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_SIZE +CYDEV_UCFG_B0_P7_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_BASE +CYDEV_UCFG_B0_P7_U0_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_SIZE +CYDEV_UCFG_B0_P7_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT0 +CYDEV_UCFG_B0_P7_U0_PLD_IT0 EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT1 +CYDEV_UCFG_B0_P7_U0_PLD_IT1 EQU 0x40010e04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT2 +CYDEV_UCFG_B0_P7_U0_PLD_IT2 EQU 0x40010e08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT3 +CYDEV_UCFG_B0_P7_U0_PLD_IT3 EQU 0x40010e0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT4 +CYDEV_UCFG_B0_P7_U0_PLD_IT4 EQU 0x40010e10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT5 +CYDEV_UCFG_B0_P7_U0_PLD_IT5 EQU 0x40010e14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT6 +CYDEV_UCFG_B0_P7_U0_PLD_IT6 EQU 0x40010e18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT7 +CYDEV_UCFG_B0_P7_U0_PLD_IT7 EQU 0x40010e1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT8 +CYDEV_UCFG_B0_P7_U0_PLD_IT8 EQU 0x40010e20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT9 +CYDEV_UCFG_B0_P7_U0_PLD_IT9 EQU 0x40010e24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT10 +CYDEV_UCFG_B0_P7_U0_PLD_IT10 EQU 0x40010e28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT11 +CYDEV_UCFG_B0_P7_U0_PLD_IT11 EQU 0x40010e2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT0 +CYDEV_UCFG_B0_P7_U0_PLD_ORT0 EQU 0x40010e30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT1 +CYDEV_UCFG_B0_P7_U0_PLD_ORT1 EQU 0x40010e32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT2 +CYDEV_UCFG_B0_P7_U0_PLD_ORT2 EQU 0x40010e34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT3 +CYDEV_UCFG_B0_P7_U0_PLD_ORT3 EQU 0x40010e36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST EQU 0x40010e38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB EQU 0x40010e3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET EQU 0x40010e3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS EQU 0x40010e3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG0 +CYDEV_UCFG_B0_P7_U0_CFG0 EQU 0x40010e40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG1 +CYDEV_UCFG_B0_P7_U0_CFG1 EQU 0x40010e41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG2 +CYDEV_UCFG_B0_P7_U0_CFG2 EQU 0x40010e42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG3 +CYDEV_UCFG_B0_P7_U0_CFG3 EQU 0x40010e43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG4 +CYDEV_UCFG_B0_P7_U0_CFG4 EQU 0x40010e44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG5 +CYDEV_UCFG_B0_P7_U0_CFG5 EQU 0x40010e45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG6 +CYDEV_UCFG_B0_P7_U0_CFG6 EQU 0x40010e46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG7 +CYDEV_UCFG_B0_P7_U0_CFG7 EQU 0x40010e47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG8 +CYDEV_UCFG_B0_P7_U0_CFG8 EQU 0x40010e48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG9 +CYDEV_UCFG_B0_P7_U0_CFG9 EQU 0x40010e49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG10 +CYDEV_UCFG_B0_P7_U0_CFG10 EQU 0x40010e4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG11 +CYDEV_UCFG_B0_P7_U0_CFG11 EQU 0x40010e4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG12 +CYDEV_UCFG_B0_P7_U0_CFG12 EQU 0x40010e4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG13 +CYDEV_UCFG_B0_P7_U0_CFG13 EQU 0x40010e4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG14 +CYDEV_UCFG_B0_P7_U0_CFG14 EQU 0x40010e4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG15 +CYDEV_UCFG_B0_P7_U0_CFG15 EQU 0x40010e4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG16 +CYDEV_UCFG_B0_P7_U0_CFG16 EQU 0x40010e50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG17 +CYDEV_UCFG_B0_P7_U0_CFG17 EQU 0x40010e51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG18 +CYDEV_UCFG_B0_P7_U0_CFG18 EQU 0x40010e52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG19 +CYDEV_UCFG_B0_P7_U0_CFG19 EQU 0x40010e53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG20 +CYDEV_UCFG_B0_P7_U0_CFG20 EQU 0x40010e54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG21 +CYDEV_UCFG_B0_P7_U0_CFG21 EQU 0x40010e55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG22 +CYDEV_UCFG_B0_P7_U0_CFG22 EQU 0x40010e56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG23 +CYDEV_UCFG_B0_P7_U0_CFG23 EQU 0x40010e57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG24 +CYDEV_UCFG_B0_P7_U0_CFG24 EQU 0x40010e58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG25 +CYDEV_UCFG_B0_P7_U0_CFG25 EQU 0x40010e59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG26 +CYDEV_UCFG_B0_P7_U0_CFG26 EQU 0x40010e5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG27 +CYDEV_UCFG_B0_P7_U0_CFG27 EQU 0x40010e5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG28 +CYDEV_UCFG_B0_P7_U0_CFG28 EQU 0x40010e5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG29 +CYDEV_UCFG_B0_P7_U0_CFG29 EQU 0x40010e5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG30 +CYDEV_UCFG_B0_P7_U0_CFG30 EQU 0x40010e5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG31 +CYDEV_UCFG_B0_P7_U0_CFG31 EQU 0x40010e5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG0 +CYDEV_UCFG_B0_P7_U0_DCFG0 EQU 0x40010e60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG1 +CYDEV_UCFG_B0_P7_U0_DCFG1 EQU 0x40010e62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG2 +CYDEV_UCFG_B0_P7_U0_DCFG2 EQU 0x40010e64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG3 +CYDEV_UCFG_B0_P7_U0_DCFG3 EQU 0x40010e66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG4 +CYDEV_UCFG_B0_P7_U0_DCFG4 EQU 0x40010e68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG5 +CYDEV_UCFG_B0_P7_U0_DCFG5 EQU 0x40010e6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG6 +CYDEV_UCFG_B0_P7_U0_DCFG6 EQU 0x40010e6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG7 +CYDEV_UCFG_B0_P7_U0_DCFG7 EQU 0x40010e6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_BASE +CYDEV_UCFG_B0_P7_U1_BASE EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_SIZE +CYDEV_UCFG_B0_P7_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT0 +CYDEV_UCFG_B0_P7_U1_PLD_IT0 EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT1 +CYDEV_UCFG_B0_P7_U1_PLD_IT1 EQU 0x40010e84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT2 +CYDEV_UCFG_B0_P7_U1_PLD_IT2 EQU 0x40010e88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT3 +CYDEV_UCFG_B0_P7_U1_PLD_IT3 EQU 0x40010e8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT4 +CYDEV_UCFG_B0_P7_U1_PLD_IT4 EQU 0x40010e90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT5 +CYDEV_UCFG_B0_P7_U1_PLD_IT5 EQU 0x40010e94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT6 +CYDEV_UCFG_B0_P7_U1_PLD_IT6 EQU 0x40010e98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT7 +CYDEV_UCFG_B0_P7_U1_PLD_IT7 EQU 0x40010e9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT8 +CYDEV_UCFG_B0_P7_U1_PLD_IT8 EQU 0x40010ea0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT9 +CYDEV_UCFG_B0_P7_U1_PLD_IT9 EQU 0x40010ea4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT10 +CYDEV_UCFG_B0_P7_U1_PLD_IT10 EQU 0x40010ea8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT11 +CYDEV_UCFG_B0_P7_U1_PLD_IT11 EQU 0x40010eac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT0 +CYDEV_UCFG_B0_P7_U1_PLD_ORT0 EQU 0x40010eb0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT1 +CYDEV_UCFG_B0_P7_U1_PLD_ORT1 EQU 0x40010eb2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT2 +CYDEV_UCFG_B0_P7_U1_PLD_ORT2 EQU 0x40010eb4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT3 +CYDEV_UCFG_B0_P7_U1_PLD_ORT3 EQU 0x40010eb6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST EQU 0x40010eb8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB EQU 0x40010eba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET EQU 0x40010ebc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS EQU 0x40010ebe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG0 +CYDEV_UCFG_B0_P7_U1_CFG0 EQU 0x40010ec0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG1 +CYDEV_UCFG_B0_P7_U1_CFG1 EQU 0x40010ec1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG2 +CYDEV_UCFG_B0_P7_U1_CFG2 EQU 0x40010ec2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG3 +CYDEV_UCFG_B0_P7_U1_CFG3 EQU 0x40010ec3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG4 +CYDEV_UCFG_B0_P7_U1_CFG4 EQU 0x40010ec4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG5 +CYDEV_UCFG_B0_P7_U1_CFG5 EQU 0x40010ec5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG6 +CYDEV_UCFG_B0_P7_U1_CFG6 EQU 0x40010ec6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG7 +CYDEV_UCFG_B0_P7_U1_CFG7 EQU 0x40010ec7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG8 +CYDEV_UCFG_B0_P7_U1_CFG8 EQU 0x40010ec8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG9 +CYDEV_UCFG_B0_P7_U1_CFG9 EQU 0x40010ec9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG10 +CYDEV_UCFG_B0_P7_U1_CFG10 EQU 0x40010eca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG11 +CYDEV_UCFG_B0_P7_U1_CFG11 EQU 0x40010ecb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG12 +CYDEV_UCFG_B0_P7_U1_CFG12 EQU 0x40010ecc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG13 +CYDEV_UCFG_B0_P7_U1_CFG13 EQU 0x40010ecd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG14 +CYDEV_UCFG_B0_P7_U1_CFG14 EQU 0x40010ece + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG15 +CYDEV_UCFG_B0_P7_U1_CFG15 EQU 0x40010ecf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG16 +CYDEV_UCFG_B0_P7_U1_CFG16 EQU 0x40010ed0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG17 +CYDEV_UCFG_B0_P7_U1_CFG17 EQU 0x40010ed1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG18 +CYDEV_UCFG_B0_P7_U1_CFG18 EQU 0x40010ed2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG19 +CYDEV_UCFG_B0_P7_U1_CFG19 EQU 0x40010ed3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG20 +CYDEV_UCFG_B0_P7_U1_CFG20 EQU 0x40010ed4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG21 +CYDEV_UCFG_B0_P7_U1_CFG21 EQU 0x40010ed5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG22 +CYDEV_UCFG_B0_P7_U1_CFG22 EQU 0x40010ed6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG23 +CYDEV_UCFG_B0_P7_U1_CFG23 EQU 0x40010ed7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG24 +CYDEV_UCFG_B0_P7_U1_CFG24 EQU 0x40010ed8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG25 +CYDEV_UCFG_B0_P7_U1_CFG25 EQU 0x40010ed9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG26 +CYDEV_UCFG_B0_P7_U1_CFG26 EQU 0x40010eda + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG27 +CYDEV_UCFG_B0_P7_U1_CFG27 EQU 0x40010edb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG28 +CYDEV_UCFG_B0_P7_U1_CFG28 EQU 0x40010edc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG29 +CYDEV_UCFG_B0_P7_U1_CFG29 EQU 0x40010edd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG30 +CYDEV_UCFG_B0_P7_U1_CFG30 EQU 0x40010ede + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG31 +CYDEV_UCFG_B0_P7_U1_CFG31 EQU 0x40010edf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG0 +CYDEV_UCFG_B0_P7_U1_DCFG0 EQU 0x40010ee0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG1 +CYDEV_UCFG_B0_P7_U1_DCFG1 EQU 0x40010ee2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG2 +CYDEV_UCFG_B0_P7_U1_DCFG2 EQU 0x40010ee4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG3 +CYDEV_UCFG_B0_P7_U1_DCFG3 EQU 0x40010ee6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG4 +CYDEV_UCFG_B0_P7_U1_DCFG4 EQU 0x40010ee8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG5 +CYDEV_UCFG_B0_P7_U1_DCFG5 EQU 0x40010eea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG6 +CYDEV_UCFG_B0_P7_U1_DCFG6 EQU 0x40010eec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG7 +CYDEV_UCFG_B0_P7_U1_DCFG7 EQU 0x40010eee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_BASE +CYDEV_UCFG_B0_P7_ROUTE_BASE EQU 0x40010f00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_SIZE +CYDEV_UCFG_B0_P7_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_BASE +CYDEV_UCFG_B1_BASE EQU 0x40011000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_SIZE +CYDEV_UCFG_B1_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_BASE +CYDEV_UCFG_B1_P2_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_SIZE +CYDEV_UCFG_B1_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_BASE +CYDEV_UCFG_B1_P2_U0_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_SIZE +CYDEV_UCFG_B1_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT0 +CYDEV_UCFG_B1_P2_U0_PLD_IT0 EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT1 +CYDEV_UCFG_B1_P2_U0_PLD_IT1 EQU 0x40011404 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT2 +CYDEV_UCFG_B1_P2_U0_PLD_IT2 EQU 0x40011408 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT3 +CYDEV_UCFG_B1_P2_U0_PLD_IT3 EQU 0x4001140c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT4 +CYDEV_UCFG_B1_P2_U0_PLD_IT4 EQU 0x40011410 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT5 +CYDEV_UCFG_B1_P2_U0_PLD_IT5 EQU 0x40011414 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT6 +CYDEV_UCFG_B1_P2_U0_PLD_IT6 EQU 0x40011418 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT7 +CYDEV_UCFG_B1_P2_U0_PLD_IT7 EQU 0x4001141c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT8 +CYDEV_UCFG_B1_P2_U0_PLD_IT8 EQU 0x40011420 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT9 +CYDEV_UCFG_B1_P2_U0_PLD_IT9 EQU 0x40011424 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT10 +CYDEV_UCFG_B1_P2_U0_PLD_IT10 EQU 0x40011428 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT11 +CYDEV_UCFG_B1_P2_U0_PLD_IT11 EQU 0x4001142c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT0 +CYDEV_UCFG_B1_P2_U0_PLD_ORT0 EQU 0x40011430 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT1 +CYDEV_UCFG_B1_P2_U0_PLD_ORT1 EQU 0x40011432 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT2 +CYDEV_UCFG_B1_P2_U0_PLD_ORT2 EQU 0x40011434 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT3 +CYDEV_UCFG_B1_P2_U0_PLD_ORT3 EQU 0x40011436 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST EQU 0x40011438 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB EQU 0x4001143a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET EQU 0x4001143c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS EQU 0x4001143e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG0 +CYDEV_UCFG_B1_P2_U0_CFG0 EQU 0x40011440 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG1 +CYDEV_UCFG_B1_P2_U0_CFG1 EQU 0x40011441 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG2 +CYDEV_UCFG_B1_P2_U0_CFG2 EQU 0x40011442 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG3 +CYDEV_UCFG_B1_P2_U0_CFG3 EQU 0x40011443 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG4 +CYDEV_UCFG_B1_P2_U0_CFG4 EQU 0x40011444 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG5 +CYDEV_UCFG_B1_P2_U0_CFG5 EQU 0x40011445 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG6 +CYDEV_UCFG_B1_P2_U0_CFG6 EQU 0x40011446 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG7 +CYDEV_UCFG_B1_P2_U0_CFG7 EQU 0x40011447 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG8 +CYDEV_UCFG_B1_P2_U0_CFG8 EQU 0x40011448 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG9 +CYDEV_UCFG_B1_P2_U0_CFG9 EQU 0x40011449 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG10 +CYDEV_UCFG_B1_P2_U0_CFG10 EQU 0x4001144a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG11 +CYDEV_UCFG_B1_P2_U0_CFG11 EQU 0x4001144b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG12 +CYDEV_UCFG_B1_P2_U0_CFG12 EQU 0x4001144c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG13 +CYDEV_UCFG_B1_P2_U0_CFG13 EQU 0x4001144d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG14 +CYDEV_UCFG_B1_P2_U0_CFG14 EQU 0x4001144e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG15 +CYDEV_UCFG_B1_P2_U0_CFG15 EQU 0x4001144f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG16 +CYDEV_UCFG_B1_P2_U0_CFG16 EQU 0x40011450 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG17 +CYDEV_UCFG_B1_P2_U0_CFG17 EQU 0x40011451 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG18 +CYDEV_UCFG_B1_P2_U0_CFG18 EQU 0x40011452 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG19 +CYDEV_UCFG_B1_P2_U0_CFG19 EQU 0x40011453 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG20 +CYDEV_UCFG_B1_P2_U0_CFG20 EQU 0x40011454 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG21 +CYDEV_UCFG_B1_P2_U0_CFG21 EQU 0x40011455 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG22 +CYDEV_UCFG_B1_P2_U0_CFG22 EQU 0x40011456 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG23 +CYDEV_UCFG_B1_P2_U0_CFG23 EQU 0x40011457 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG24 +CYDEV_UCFG_B1_P2_U0_CFG24 EQU 0x40011458 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG25 +CYDEV_UCFG_B1_P2_U0_CFG25 EQU 0x40011459 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG26 +CYDEV_UCFG_B1_P2_U0_CFG26 EQU 0x4001145a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG27 +CYDEV_UCFG_B1_P2_U0_CFG27 EQU 0x4001145b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG28 +CYDEV_UCFG_B1_P2_U0_CFG28 EQU 0x4001145c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG29 +CYDEV_UCFG_B1_P2_U0_CFG29 EQU 0x4001145d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG30 +CYDEV_UCFG_B1_P2_U0_CFG30 EQU 0x4001145e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG31 +CYDEV_UCFG_B1_P2_U0_CFG31 EQU 0x4001145f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG0 +CYDEV_UCFG_B1_P2_U0_DCFG0 EQU 0x40011460 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG1 +CYDEV_UCFG_B1_P2_U0_DCFG1 EQU 0x40011462 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG2 +CYDEV_UCFG_B1_P2_U0_DCFG2 EQU 0x40011464 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG3 +CYDEV_UCFG_B1_P2_U0_DCFG3 EQU 0x40011466 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG4 +CYDEV_UCFG_B1_P2_U0_DCFG4 EQU 0x40011468 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG5 +CYDEV_UCFG_B1_P2_U0_DCFG5 EQU 0x4001146a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG6 +CYDEV_UCFG_B1_P2_U0_DCFG6 EQU 0x4001146c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG7 +CYDEV_UCFG_B1_P2_U0_DCFG7 EQU 0x4001146e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_BASE +CYDEV_UCFG_B1_P2_U1_BASE EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_SIZE +CYDEV_UCFG_B1_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT0 +CYDEV_UCFG_B1_P2_U1_PLD_IT0 EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT1 +CYDEV_UCFG_B1_P2_U1_PLD_IT1 EQU 0x40011484 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT2 +CYDEV_UCFG_B1_P2_U1_PLD_IT2 EQU 0x40011488 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT3 +CYDEV_UCFG_B1_P2_U1_PLD_IT3 EQU 0x4001148c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT4 +CYDEV_UCFG_B1_P2_U1_PLD_IT4 EQU 0x40011490 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT5 +CYDEV_UCFG_B1_P2_U1_PLD_IT5 EQU 0x40011494 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT6 +CYDEV_UCFG_B1_P2_U1_PLD_IT6 EQU 0x40011498 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT7 +CYDEV_UCFG_B1_P2_U1_PLD_IT7 EQU 0x4001149c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT8 +CYDEV_UCFG_B1_P2_U1_PLD_IT8 EQU 0x400114a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT9 +CYDEV_UCFG_B1_P2_U1_PLD_IT9 EQU 0x400114a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT10 +CYDEV_UCFG_B1_P2_U1_PLD_IT10 EQU 0x400114a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT11 +CYDEV_UCFG_B1_P2_U1_PLD_IT11 EQU 0x400114ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT0 +CYDEV_UCFG_B1_P2_U1_PLD_ORT0 EQU 0x400114b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT1 +CYDEV_UCFG_B1_P2_U1_PLD_ORT1 EQU 0x400114b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT2 +CYDEV_UCFG_B1_P2_U1_PLD_ORT2 EQU 0x400114b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT3 +CYDEV_UCFG_B1_P2_U1_PLD_ORT3 EQU 0x400114b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST EQU 0x400114b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB EQU 0x400114ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET EQU 0x400114bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS EQU 0x400114be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG0 +CYDEV_UCFG_B1_P2_U1_CFG0 EQU 0x400114c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG1 +CYDEV_UCFG_B1_P2_U1_CFG1 EQU 0x400114c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG2 +CYDEV_UCFG_B1_P2_U1_CFG2 EQU 0x400114c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG3 +CYDEV_UCFG_B1_P2_U1_CFG3 EQU 0x400114c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG4 +CYDEV_UCFG_B1_P2_U1_CFG4 EQU 0x400114c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG5 +CYDEV_UCFG_B1_P2_U1_CFG5 EQU 0x400114c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG6 +CYDEV_UCFG_B1_P2_U1_CFG6 EQU 0x400114c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG7 +CYDEV_UCFG_B1_P2_U1_CFG7 EQU 0x400114c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG8 +CYDEV_UCFG_B1_P2_U1_CFG8 EQU 0x400114c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG9 +CYDEV_UCFG_B1_P2_U1_CFG9 EQU 0x400114c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG10 +CYDEV_UCFG_B1_P2_U1_CFG10 EQU 0x400114ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG11 +CYDEV_UCFG_B1_P2_U1_CFG11 EQU 0x400114cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG12 +CYDEV_UCFG_B1_P2_U1_CFG12 EQU 0x400114cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG13 +CYDEV_UCFG_B1_P2_U1_CFG13 EQU 0x400114cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG14 +CYDEV_UCFG_B1_P2_U1_CFG14 EQU 0x400114ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG15 +CYDEV_UCFG_B1_P2_U1_CFG15 EQU 0x400114cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG16 +CYDEV_UCFG_B1_P2_U1_CFG16 EQU 0x400114d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG17 +CYDEV_UCFG_B1_P2_U1_CFG17 EQU 0x400114d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG18 +CYDEV_UCFG_B1_P2_U1_CFG18 EQU 0x400114d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG19 +CYDEV_UCFG_B1_P2_U1_CFG19 EQU 0x400114d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG20 +CYDEV_UCFG_B1_P2_U1_CFG20 EQU 0x400114d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG21 +CYDEV_UCFG_B1_P2_U1_CFG21 EQU 0x400114d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG22 +CYDEV_UCFG_B1_P2_U1_CFG22 EQU 0x400114d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG23 +CYDEV_UCFG_B1_P2_U1_CFG23 EQU 0x400114d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG24 +CYDEV_UCFG_B1_P2_U1_CFG24 EQU 0x400114d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG25 +CYDEV_UCFG_B1_P2_U1_CFG25 EQU 0x400114d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG26 +CYDEV_UCFG_B1_P2_U1_CFG26 EQU 0x400114da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG27 +CYDEV_UCFG_B1_P2_U1_CFG27 EQU 0x400114db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG28 +CYDEV_UCFG_B1_P2_U1_CFG28 EQU 0x400114dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG29 +CYDEV_UCFG_B1_P2_U1_CFG29 EQU 0x400114dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG30 +CYDEV_UCFG_B1_P2_U1_CFG30 EQU 0x400114de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG31 +CYDEV_UCFG_B1_P2_U1_CFG31 EQU 0x400114df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG0 +CYDEV_UCFG_B1_P2_U1_DCFG0 EQU 0x400114e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG1 +CYDEV_UCFG_B1_P2_U1_DCFG1 EQU 0x400114e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG2 +CYDEV_UCFG_B1_P2_U1_DCFG2 EQU 0x400114e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG3 +CYDEV_UCFG_B1_P2_U1_DCFG3 EQU 0x400114e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG4 +CYDEV_UCFG_B1_P2_U1_DCFG4 EQU 0x400114e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG5 +CYDEV_UCFG_B1_P2_U1_DCFG5 EQU 0x400114ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG6 +CYDEV_UCFG_B1_P2_U1_DCFG6 EQU 0x400114ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG7 +CYDEV_UCFG_B1_P2_U1_DCFG7 EQU 0x400114ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_BASE +CYDEV_UCFG_B1_P2_ROUTE_BASE EQU 0x40011500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_SIZE +CYDEV_UCFG_B1_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_BASE +CYDEV_UCFG_B1_P3_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_SIZE +CYDEV_UCFG_B1_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_BASE +CYDEV_UCFG_B1_P3_U0_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_SIZE +CYDEV_UCFG_B1_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT0 +CYDEV_UCFG_B1_P3_U0_PLD_IT0 EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT1 +CYDEV_UCFG_B1_P3_U0_PLD_IT1 EQU 0x40011604 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT2 +CYDEV_UCFG_B1_P3_U0_PLD_IT2 EQU 0x40011608 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT3 +CYDEV_UCFG_B1_P3_U0_PLD_IT3 EQU 0x4001160c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT4 +CYDEV_UCFG_B1_P3_U0_PLD_IT4 EQU 0x40011610 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT5 +CYDEV_UCFG_B1_P3_U0_PLD_IT5 EQU 0x40011614 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT6 +CYDEV_UCFG_B1_P3_U0_PLD_IT6 EQU 0x40011618 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT7 +CYDEV_UCFG_B1_P3_U0_PLD_IT7 EQU 0x4001161c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT8 +CYDEV_UCFG_B1_P3_U0_PLD_IT8 EQU 0x40011620 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT9 +CYDEV_UCFG_B1_P3_U0_PLD_IT9 EQU 0x40011624 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT10 +CYDEV_UCFG_B1_P3_U0_PLD_IT10 EQU 0x40011628 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT11 +CYDEV_UCFG_B1_P3_U0_PLD_IT11 EQU 0x4001162c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT0 +CYDEV_UCFG_B1_P3_U0_PLD_ORT0 EQU 0x40011630 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT1 +CYDEV_UCFG_B1_P3_U0_PLD_ORT1 EQU 0x40011632 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT2 +CYDEV_UCFG_B1_P3_U0_PLD_ORT2 EQU 0x40011634 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT3 +CYDEV_UCFG_B1_P3_U0_PLD_ORT3 EQU 0x40011636 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST EQU 0x40011638 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB EQU 0x4001163a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET EQU 0x4001163c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS EQU 0x4001163e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG0 +CYDEV_UCFG_B1_P3_U0_CFG0 EQU 0x40011640 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG1 +CYDEV_UCFG_B1_P3_U0_CFG1 EQU 0x40011641 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG2 +CYDEV_UCFG_B1_P3_U0_CFG2 EQU 0x40011642 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG3 +CYDEV_UCFG_B1_P3_U0_CFG3 EQU 0x40011643 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG4 +CYDEV_UCFG_B1_P3_U0_CFG4 EQU 0x40011644 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG5 +CYDEV_UCFG_B1_P3_U0_CFG5 EQU 0x40011645 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG6 +CYDEV_UCFG_B1_P3_U0_CFG6 EQU 0x40011646 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG7 +CYDEV_UCFG_B1_P3_U0_CFG7 EQU 0x40011647 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG8 +CYDEV_UCFG_B1_P3_U0_CFG8 EQU 0x40011648 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG9 +CYDEV_UCFG_B1_P3_U0_CFG9 EQU 0x40011649 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG10 +CYDEV_UCFG_B1_P3_U0_CFG10 EQU 0x4001164a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG11 +CYDEV_UCFG_B1_P3_U0_CFG11 EQU 0x4001164b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG12 +CYDEV_UCFG_B1_P3_U0_CFG12 EQU 0x4001164c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG13 +CYDEV_UCFG_B1_P3_U0_CFG13 EQU 0x4001164d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG14 +CYDEV_UCFG_B1_P3_U0_CFG14 EQU 0x4001164e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG15 +CYDEV_UCFG_B1_P3_U0_CFG15 EQU 0x4001164f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG16 +CYDEV_UCFG_B1_P3_U0_CFG16 EQU 0x40011650 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG17 +CYDEV_UCFG_B1_P3_U0_CFG17 EQU 0x40011651 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG18 +CYDEV_UCFG_B1_P3_U0_CFG18 EQU 0x40011652 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG19 +CYDEV_UCFG_B1_P3_U0_CFG19 EQU 0x40011653 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG20 +CYDEV_UCFG_B1_P3_U0_CFG20 EQU 0x40011654 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG21 +CYDEV_UCFG_B1_P3_U0_CFG21 EQU 0x40011655 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG22 +CYDEV_UCFG_B1_P3_U0_CFG22 EQU 0x40011656 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG23 +CYDEV_UCFG_B1_P3_U0_CFG23 EQU 0x40011657 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG24 +CYDEV_UCFG_B1_P3_U0_CFG24 EQU 0x40011658 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG25 +CYDEV_UCFG_B1_P3_U0_CFG25 EQU 0x40011659 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG26 +CYDEV_UCFG_B1_P3_U0_CFG26 EQU 0x4001165a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG27 +CYDEV_UCFG_B1_P3_U0_CFG27 EQU 0x4001165b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG28 +CYDEV_UCFG_B1_P3_U0_CFG28 EQU 0x4001165c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG29 +CYDEV_UCFG_B1_P3_U0_CFG29 EQU 0x4001165d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG30 +CYDEV_UCFG_B1_P3_U0_CFG30 EQU 0x4001165e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG31 +CYDEV_UCFG_B1_P3_U0_CFG31 EQU 0x4001165f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG0 +CYDEV_UCFG_B1_P3_U0_DCFG0 EQU 0x40011660 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG1 +CYDEV_UCFG_B1_P3_U0_DCFG1 EQU 0x40011662 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG2 +CYDEV_UCFG_B1_P3_U0_DCFG2 EQU 0x40011664 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG3 +CYDEV_UCFG_B1_P3_U0_DCFG3 EQU 0x40011666 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG4 +CYDEV_UCFG_B1_P3_U0_DCFG4 EQU 0x40011668 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG5 +CYDEV_UCFG_B1_P3_U0_DCFG5 EQU 0x4001166a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG6 +CYDEV_UCFG_B1_P3_U0_DCFG6 EQU 0x4001166c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG7 +CYDEV_UCFG_B1_P3_U0_DCFG7 EQU 0x4001166e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_BASE +CYDEV_UCFG_B1_P3_U1_BASE EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_SIZE +CYDEV_UCFG_B1_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT0 +CYDEV_UCFG_B1_P3_U1_PLD_IT0 EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT1 +CYDEV_UCFG_B1_P3_U1_PLD_IT1 EQU 0x40011684 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT2 +CYDEV_UCFG_B1_P3_U1_PLD_IT2 EQU 0x40011688 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT3 +CYDEV_UCFG_B1_P3_U1_PLD_IT3 EQU 0x4001168c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT4 +CYDEV_UCFG_B1_P3_U1_PLD_IT4 EQU 0x40011690 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT5 +CYDEV_UCFG_B1_P3_U1_PLD_IT5 EQU 0x40011694 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT6 +CYDEV_UCFG_B1_P3_U1_PLD_IT6 EQU 0x40011698 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT7 +CYDEV_UCFG_B1_P3_U1_PLD_IT7 EQU 0x4001169c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT8 +CYDEV_UCFG_B1_P3_U1_PLD_IT8 EQU 0x400116a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT9 +CYDEV_UCFG_B1_P3_U1_PLD_IT9 EQU 0x400116a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT10 +CYDEV_UCFG_B1_P3_U1_PLD_IT10 EQU 0x400116a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT11 +CYDEV_UCFG_B1_P3_U1_PLD_IT11 EQU 0x400116ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT0 +CYDEV_UCFG_B1_P3_U1_PLD_ORT0 EQU 0x400116b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT1 +CYDEV_UCFG_B1_P3_U1_PLD_ORT1 EQU 0x400116b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT2 +CYDEV_UCFG_B1_P3_U1_PLD_ORT2 EQU 0x400116b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT3 +CYDEV_UCFG_B1_P3_U1_PLD_ORT3 EQU 0x400116b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST EQU 0x400116b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB EQU 0x400116ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET EQU 0x400116bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS EQU 0x400116be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG0 +CYDEV_UCFG_B1_P3_U1_CFG0 EQU 0x400116c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG1 +CYDEV_UCFG_B1_P3_U1_CFG1 EQU 0x400116c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG2 +CYDEV_UCFG_B1_P3_U1_CFG2 EQU 0x400116c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG3 +CYDEV_UCFG_B1_P3_U1_CFG3 EQU 0x400116c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG4 +CYDEV_UCFG_B1_P3_U1_CFG4 EQU 0x400116c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG5 +CYDEV_UCFG_B1_P3_U1_CFG5 EQU 0x400116c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG6 +CYDEV_UCFG_B1_P3_U1_CFG6 EQU 0x400116c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG7 +CYDEV_UCFG_B1_P3_U1_CFG7 EQU 0x400116c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG8 +CYDEV_UCFG_B1_P3_U1_CFG8 EQU 0x400116c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG9 +CYDEV_UCFG_B1_P3_U1_CFG9 EQU 0x400116c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG10 +CYDEV_UCFG_B1_P3_U1_CFG10 EQU 0x400116ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG11 +CYDEV_UCFG_B1_P3_U1_CFG11 EQU 0x400116cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG12 +CYDEV_UCFG_B1_P3_U1_CFG12 EQU 0x400116cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG13 +CYDEV_UCFG_B1_P3_U1_CFG13 EQU 0x400116cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG14 +CYDEV_UCFG_B1_P3_U1_CFG14 EQU 0x400116ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG15 +CYDEV_UCFG_B1_P3_U1_CFG15 EQU 0x400116cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG16 +CYDEV_UCFG_B1_P3_U1_CFG16 EQU 0x400116d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG17 +CYDEV_UCFG_B1_P3_U1_CFG17 EQU 0x400116d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG18 +CYDEV_UCFG_B1_P3_U1_CFG18 EQU 0x400116d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG19 +CYDEV_UCFG_B1_P3_U1_CFG19 EQU 0x400116d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG20 +CYDEV_UCFG_B1_P3_U1_CFG20 EQU 0x400116d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG21 +CYDEV_UCFG_B1_P3_U1_CFG21 EQU 0x400116d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG22 +CYDEV_UCFG_B1_P3_U1_CFG22 EQU 0x400116d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG23 +CYDEV_UCFG_B1_P3_U1_CFG23 EQU 0x400116d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG24 +CYDEV_UCFG_B1_P3_U1_CFG24 EQU 0x400116d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG25 +CYDEV_UCFG_B1_P3_U1_CFG25 EQU 0x400116d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG26 +CYDEV_UCFG_B1_P3_U1_CFG26 EQU 0x400116da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG27 +CYDEV_UCFG_B1_P3_U1_CFG27 EQU 0x400116db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG28 +CYDEV_UCFG_B1_P3_U1_CFG28 EQU 0x400116dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG29 +CYDEV_UCFG_B1_P3_U1_CFG29 EQU 0x400116dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG30 +CYDEV_UCFG_B1_P3_U1_CFG30 EQU 0x400116de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG31 +CYDEV_UCFG_B1_P3_U1_CFG31 EQU 0x400116df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG0 +CYDEV_UCFG_B1_P3_U1_DCFG0 EQU 0x400116e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG1 +CYDEV_UCFG_B1_P3_U1_DCFG1 EQU 0x400116e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG2 +CYDEV_UCFG_B1_P3_U1_DCFG2 EQU 0x400116e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG3 +CYDEV_UCFG_B1_P3_U1_DCFG3 EQU 0x400116e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG4 +CYDEV_UCFG_B1_P3_U1_DCFG4 EQU 0x400116e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG5 +CYDEV_UCFG_B1_P3_U1_DCFG5 EQU 0x400116ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG6 +CYDEV_UCFG_B1_P3_U1_DCFG6 EQU 0x400116ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG7 +CYDEV_UCFG_B1_P3_U1_DCFG7 EQU 0x400116ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_BASE +CYDEV_UCFG_B1_P3_ROUTE_BASE EQU 0x40011700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_SIZE +CYDEV_UCFG_B1_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_BASE +CYDEV_UCFG_B1_P4_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_SIZE +CYDEV_UCFG_B1_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_BASE +CYDEV_UCFG_B1_P4_U0_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_SIZE +CYDEV_UCFG_B1_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT0 +CYDEV_UCFG_B1_P4_U0_PLD_IT0 EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT1 +CYDEV_UCFG_B1_P4_U0_PLD_IT1 EQU 0x40011804 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT2 +CYDEV_UCFG_B1_P4_U0_PLD_IT2 EQU 0x40011808 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT3 +CYDEV_UCFG_B1_P4_U0_PLD_IT3 EQU 0x4001180c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT4 +CYDEV_UCFG_B1_P4_U0_PLD_IT4 EQU 0x40011810 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT5 +CYDEV_UCFG_B1_P4_U0_PLD_IT5 EQU 0x40011814 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT6 +CYDEV_UCFG_B1_P4_U0_PLD_IT6 EQU 0x40011818 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT7 +CYDEV_UCFG_B1_P4_U0_PLD_IT7 EQU 0x4001181c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT8 +CYDEV_UCFG_B1_P4_U0_PLD_IT8 EQU 0x40011820 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT9 +CYDEV_UCFG_B1_P4_U0_PLD_IT9 EQU 0x40011824 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT10 +CYDEV_UCFG_B1_P4_U0_PLD_IT10 EQU 0x40011828 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT11 +CYDEV_UCFG_B1_P4_U0_PLD_IT11 EQU 0x4001182c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT0 +CYDEV_UCFG_B1_P4_U0_PLD_ORT0 EQU 0x40011830 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT1 +CYDEV_UCFG_B1_P4_U0_PLD_ORT1 EQU 0x40011832 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT2 +CYDEV_UCFG_B1_P4_U0_PLD_ORT2 EQU 0x40011834 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT3 +CYDEV_UCFG_B1_P4_U0_PLD_ORT3 EQU 0x40011836 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST EQU 0x40011838 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB EQU 0x4001183a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET EQU 0x4001183c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS EQU 0x4001183e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG0 +CYDEV_UCFG_B1_P4_U0_CFG0 EQU 0x40011840 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG1 +CYDEV_UCFG_B1_P4_U0_CFG1 EQU 0x40011841 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG2 +CYDEV_UCFG_B1_P4_U0_CFG2 EQU 0x40011842 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG3 +CYDEV_UCFG_B1_P4_U0_CFG3 EQU 0x40011843 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG4 +CYDEV_UCFG_B1_P4_U0_CFG4 EQU 0x40011844 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG5 +CYDEV_UCFG_B1_P4_U0_CFG5 EQU 0x40011845 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG6 +CYDEV_UCFG_B1_P4_U0_CFG6 EQU 0x40011846 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG7 +CYDEV_UCFG_B1_P4_U0_CFG7 EQU 0x40011847 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG8 +CYDEV_UCFG_B1_P4_U0_CFG8 EQU 0x40011848 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG9 +CYDEV_UCFG_B1_P4_U0_CFG9 EQU 0x40011849 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG10 +CYDEV_UCFG_B1_P4_U0_CFG10 EQU 0x4001184a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG11 +CYDEV_UCFG_B1_P4_U0_CFG11 EQU 0x4001184b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG12 +CYDEV_UCFG_B1_P4_U0_CFG12 EQU 0x4001184c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG13 +CYDEV_UCFG_B1_P4_U0_CFG13 EQU 0x4001184d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG14 +CYDEV_UCFG_B1_P4_U0_CFG14 EQU 0x4001184e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG15 +CYDEV_UCFG_B1_P4_U0_CFG15 EQU 0x4001184f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG16 +CYDEV_UCFG_B1_P4_U0_CFG16 EQU 0x40011850 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG17 +CYDEV_UCFG_B1_P4_U0_CFG17 EQU 0x40011851 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG18 +CYDEV_UCFG_B1_P4_U0_CFG18 EQU 0x40011852 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG19 +CYDEV_UCFG_B1_P4_U0_CFG19 EQU 0x40011853 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG20 +CYDEV_UCFG_B1_P4_U0_CFG20 EQU 0x40011854 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG21 +CYDEV_UCFG_B1_P4_U0_CFG21 EQU 0x40011855 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG22 +CYDEV_UCFG_B1_P4_U0_CFG22 EQU 0x40011856 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG23 +CYDEV_UCFG_B1_P4_U0_CFG23 EQU 0x40011857 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG24 +CYDEV_UCFG_B1_P4_U0_CFG24 EQU 0x40011858 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG25 +CYDEV_UCFG_B1_P4_U0_CFG25 EQU 0x40011859 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG26 +CYDEV_UCFG_B1_P4_U0_CFG26 EQU 0x4001185a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG27 +CYDEV_UCFG_B1_P4_U0_CFG27 EQU 0x4001185b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG28 +CYDEV_UCFG_B1_P4_U0_CFG28 EQU 0x4001185c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG29 +CYDEV_UCFG_B1_P4_U0_CFG29 EQU 0x4001185d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG30 +CYDEV_UCFG_B1_P4_U0_CFG30 EQU 0x4001185e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG31 +CYDEV_UCFG_B1_P4_U0_CFG31 EQU 0x4001185f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG0 +CYDEV_UCFG_B1_P4_U0_DCFG0 EQU 0x40011860 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG1 +CYDEV_UCFG_B1_P4_U0_DCFG1 EQU 0x40011862 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG2 +CYDEV_UCFG_B1_P4_U0_DCFG2 EQU 0x40011864 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG3 +CYDEV_UCFG_B1_P4_U0_DCFG3 EQU 0x40011866 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG4 +CYDEV_UCFG_B1_P4_U0_DCFG4 EQU 0x40011868 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG5 +CYDEV_UCFG_B1_P4_U0_DCFG5 EQU 0x4001186a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG6 +CYDEV_UCFG_B1_P4_U0_DCFG6 EQU 0x4001186c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG7 +CYDEV_UCFG_B1_P4_U0_DCFG7 EQU 0x4001186e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_BASE +CYDEV_UCFG_B1_P4_U1_BASE EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_SIZE +CYDEV_UCFG_B1_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT0 +CYDEV_UCFG_B1_P4_U1_PLD_IT0 EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT1 +CYDEV_UCFG_B1_P4_U1_PLD_IT1 EQU 0x40011884 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT2 +CYDEV_UCFG_B1_P4_U1_PLD_IT2 EQU 0x40011888 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT3 +CYDEV_UCFG_B1_P4_U1_PLD_IT3 EQU 0x4001188c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT4 +CYDEV_UCFG_B1_P4_U1_PLD_IT4 EQU 0x40011890 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT5 +CYDEV_UCFG_B1_P4_U1_PLD_IT5 EQU 0x40011894 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT6 +CYDEV_UCFG_B1_P4_U1_PLD_IT6 EQU 0x40011898 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT7 +CYDEV_UCFG_B1_P4_U1_PLD_IT7 EQU 0x4001189c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT8 +CYDEV_UCFG_B1_P4_U1_PLD_IT8 EQU 0x400118a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT9 +CYDEV_UCFG_B1_P4_U1_PLD_IT9 EQU 0x400118a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT10 +CYDEV_UCFG_B1_P4_U1_PLD_IT10 EQU 0x400118a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT11 +CYDEV_UCFG_B1_P4_U1_PLD_IT11 EQU 0x400118ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT0 +CYDEV_UCFG_B1_P4_U1_PLD_ORT0 EQU 0x400118b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT1 +CYDEV_UCFG_B1_P4_U1_PLD_ORT1 EQU 0x400118b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT2 +CYDEV_UCFG_B1_P4_U1_PLD_ORT2 EQU 0x400118b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT3 +CYDEV_UCFG_B1_P4_U1_PLD_ORT3 EQU 0x400118b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST EQU 0x400118b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB EQU 0x400118ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET EQU 0x400118bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS EQU 0x400118be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG0 +CYDEV_UCFG_B1_P4_U1_CFG0 EQU 0x400118c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG1 +CYDEV_UCFG_B1_P4_U1_CFG1 EQU 0x400118c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG2 +CYDEV_UCFG_B1_P4_U1_CFG2 EQU 0x400118c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG3 +CYDEV_UCFG_B1_P4_U1_CFG3 EQU 0x400118c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG4 +CYDEV_UCFG_B1_P4_U1_CFG4 EQU 0x400118c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG5 +CYDEV_UCFG_B1_P4_U1_CFG5 EQU 0x400118c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG6 +CYDEV_UCFG_B1_P4_U1_CFG6 EQU 0x400118c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG7 +CYDEV_UCFG_B1_P4_U1_CFG7 EQU 0x400118c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG8 +CYDEV_UCFG_B1_P4_U1_CFG8 EQU 0x400118c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG9 +CYDEV_UCFG_B1_P4_U1_CFG9 EQU 0x400118c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG10 +CYDEV_UCFG_B1_P4_U1_CFG10 EQU 0x400118ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG11 +CYDEV_UCFG_B1_P4_U1_CFG11 EQU 0x400118cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG12 +CYDEV_UCFG_B1_P4_U1_CFG12 EQU 0x400118cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG13 +CYDEV_UCFG_B1_P4_U1_CFG13 EQU 0x400118cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG14 +CYDEV_UCFG_B1_P4_U1_CFG14 EQU 0x400118ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG15 +CYDEV_UCFG_B1_P4_U1_CFG15 EQU 0x400118cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG16 +CYDEV_UCFG_B1_P4_U1_CFG16 EQU 0x400118d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG17 +CYDEV_UCFG_B1_P4_U1_CFG17 EQU 0x400118d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG18 +CYDEV_UCFG_B1_P4_U1_CFG18 EQU 0x400118d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG19 +CYDEV_UCFG_B1_P4_U1_CFG19 EQU 0x400118d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG20 +CYDEV_UCFG_B1_P4_U1_CFG20 EQU 0x400118d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG21 +CYDEV_UCFG_B1_P4_U1_CFG21 EQU 0x400118d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG22 +CYDEV_UCFG_B1_P4_U1_CFG22 EQU 0x400118d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG23 +CYDEV_UCFG_B1_P4_U1_CFG23 EQU 0x400118d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG24 +CYDEV_UCFG_B1_P4_U1_CFG24 EQU 0x400118d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG25 +CYDEV_UCFG_B1_P4_U1_CFG25 EQU 0x400118d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG26 +CYDEV_UCFG_B1_P4_U1_CFG26 EQU 0x400118da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG27 +CYDEV_UCFG_B1_P4_U1_CFG27 EQU 0x400118db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG28 +CYDEV_UCFG_B1_P4_U1_CFG28 EQU 0x400118dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG29 +CYDEV_UCFG_B1_P4_U1_CFG29 EQU 0x400118dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG30 +CYDEV_UCFG_B1_P4_U1_CFG30 EQU 0x400118de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG31 +CYDEV_UCFG_B1_P4_U1_CFG31 EQU 0x400118df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG0 +CYDEV_UCFG_B1_P4_U1_DCFG0 EQU 0x400118e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG1 +CYDEV_UCFG_B1_P4_U1_DCFG1 EQU 0x400118e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG2 +CYDEV_UCFG_B1_P4_U1_DCFG2 EQU 0x400118e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG3 +CYDEV_UCFG_B1_P4_U1_DCFG3 EQU 0x400118e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG4 +CYDEV_UCFG_B1_P4_U1_DCFG4 EQU 0x400118e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG5 +CYDEV_UCFG_B1_P4_U1_DCFG5 EQU 0x400118ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG6 +CYDEV_UCFG_B1_P4_U1_DCFG6 EQU 0x400118ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG7 +CYDEV_UCFG_B1_P4_U1_DCFG7 EQU 0x400118ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_BASE +CYDEV_UCFG_B1_P4_ROUTE_BASE EQU 0x40011900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_SIZE +CYDEV_UCFG_B1_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_BASE +CYDEV_UCFG_B1_P5_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_SIZE +CYDEV_UCFG_B1_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_BASE +CYDEV_UCFG_B1_P5_U0_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_SIZE +CYDEV_UCFG_B1_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT0 +CYDEV_UCFG_B1_P5_U0_PLD_IT0 EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT1 +CYDEV_UCFG_B1_P5_U0_PLD_IT1 EQU 0x40011a04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT2 +CYDEV_UCFG_B1_P5_U0_PLD_IT2 EQU 0x40011a08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT3 +CYDEV_UCFG_B1_P5_U0_PLD_IT3 EQU 0x40011a0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT4 +CYDEV_UCFG_B1_P5_U0_PLD_IT4 EQU 0x40011a10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT5 +CYDEV_UCFG_B1_P5_U0_PLD_IT5 EQU 0x40011a14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT6 +CYDEV_UCFG_B1_P5_U0_PLD_IT6 EQU 0x40011a18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT7 +CYDEV_UCFG_B1_P5_U0_PLD_IT7 EQU 0x40011a1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT8 +CYDEV_UCFG_B1_P5_U0_PLD_IT8 EQU 0x40011a20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT9 +CYDEV_UCFG_B1_P5_U0_PLD_IT9 EQU 0x40011a24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT10 +CYDEV_UCFG_B1_P5_U0_PLD_IT10 EQU 0x40011a28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT11 +CYDEV_UCFG_B1_P5_U0_PLD_IT11 EQU 0x40011a2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT0 +CYDEV_UCFG_B1_P5_U0_PLD_ORT0 EQU 0x40011a30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT1 +CYDEV_UCFG_B1_P5_U0_PLD_ORT1 EQU 0x40011a32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT2 +CYDEV_UCFG_B1_P5_U0_PLD_ORT2 EQU 0x40011a34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT3 +CYDEV_UCFG_B1_P5_U0_PLD_ORT3 EQU 0x40011a36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST EQU 0x40011a38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB EQU 0x40011a3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET EQU 0x40011a3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS EQU 0x40011a3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG0 +CYDEV_UCFG_B1_P5_U0_CFG0 EQU 0x40011a40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG1 +CYDEV_UCFG_B1_P5_U0_CFG1 EQU 0x40011a41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG2 +CYDEV_UCFG_B1_P5_U0_CFG2 EQU 0x40011a42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG3 +CYDEV_UCFG_B1_P5_U0_CFG3 EQU 0x40011a43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG4 +CYDEV_UCFG_B1_P5_U0_CFG4 EQU 0x40011a44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG5 +CYDEV_UCFG_B1_P5_U0_CFG5 EQU 0x40011a45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG6 +CYDEV_UCFG_B1_P5_U0_CFG6 EQU 0x40011a46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG7 +CYDEV_UCFG_B1_P5_U0_CFG7 EQU 0x40011a47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG8 +CYDEV_UCFG_B1_P5_U0_CFG8 EQU 0x40011a48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG9 +CYDEV_UCFG_B1_P5_U0_CFG9 EQU 0x40011a49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG10 +CYDEV_UCFG_B1_P5_U0_CFG10 EQU 0x40011a4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG11 +CYDEV_UCFG_B1_P5_U0_CFG11 EQU 0x40011a4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG12 +CYDEV_UCFG_B1_P5_U0_CFG12 EQU 0x40011a4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG13 +CYDEV_UCFG_B1_P5_U0_CFG13 EQU 0x40011a4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG14 +CYDEV_UCFG_B1_P5_U0_CFG14 EQU 0x40011a4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG15 +CYDEV_UCFG_B1_P5_U0_CFG15 EQU 0x40011a4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG16 +CYDEV_UCFG_B1_P5_U0_CFG16 EQU 0x40011a50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG17 +CYDEV_UCFG_B1_P5_U0_CFG17 EQU 0x40011a51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG18 +CYDEV_UCFG_B1_P5_U0_CFG18 EQU 0x40011a52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG19 +CYDEV_UCFG_B1_P5_U0_CFG19 EQU 0x40011a53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG20 +CYDEV_UCFG_B1_P5_U0_CFG20 EQU 0x40011a54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG21 +CYDEV_UCFG_B1_P5_U0_CFG21 EQU 0x40011a55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG22 +CYDEV_UCFG_B1_P5_U0_CFG22 EQU 0x40011a56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG23 +CYDEV_UCFG_B1_P5_U0_CFG23 EQU 0x40011a57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG24 +CYDEV_UCFG_B1_P5_U0_CFG24 EQU 0x40011a58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG25 +CYDEV_UCFG_B1_P5_U0_CFG25 EQU 0x40011a59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG26 +CYDEV_UCFG_B1_P5_U0_CFG26 EQU 0x40011a5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG27 +CYDEV_UCFG_B1_P5_U0_CFG27 EQU 0x40011a5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG28 +CYDEV_UCFG_B1_P5_U0_CFG28 EQU 0x40011a5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG29 +CYDEV_UCFG_B1_P5_U0_CFG29 EQU 0x40011a5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG30 +CYDEV_UCFG_B1_P5_U0_CFG30 EQU 0x40011a5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG31 +CYDEV_UCFG_B1_P5_U0_CFG31 EQU 0x40011a5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG0 +CYDEV_UCFG_B1_P5_U0_DCFG0 EQU 0x40011a60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG1 +CYDEV_UCFG_B1_P5_U0_DCFG1 EQU 0x40011a62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG2 +CYDEV_UCFG_B1_P5_U0_DCFG2 EQU 0x40011a64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG3 +CYDEV_UCFG_B1_P5_U0_DCFG3 EQU 0x40011a66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG4 +CYDEV_UCFG_B1_P5_U0_DCFG4 EQU 0x40011a68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG5 +CYDEV_UCFG_B1_P5_U0_DCFG5 EQU 0x40011a6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG6 +CYDEV_UCFG_B1_P5_U0_DCFG6 EQU 0x40011a6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG7 +CYDEV_UCFG_B1_P5_U0_DCFG7 EQU 0x40011a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_BASE +CYDEV_UCFG_B1_P5_U1_BASE EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_SIZE +CYDEV_UCFG_B1_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT0 +CYDEV_UCFG_B1_P5_U1_PLD_IT0 EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT1 +CYDEV_UCFG_B1_P5_U1_PLD_IT1 EQU 0x40011a84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT2 +CYDEV_UCFG_B1_P5_U1_PLD_IT2 EQU 0x40011a88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT3 +CYDEV_UCFG_B1_P5_U1_PLD_IT3 EQU 0x40011a8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT4 +CYDEV_UCFG_B1_P5_U1_PLD_IT4 EQU 0x40011a90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT5 +CYDEV_UCFG_B1_P5_U1_PLD_IT5 EQU 0x40011a94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT6 +CYDEV_UCFG_B1_P5_U1_PLD_IT6 EQU 0x40011a98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT7 +CYDEV_UCFG_B1_P5_U1_PLD_IT7 EQU 0x40011a9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT8 +CYDEV_UCFG_B1_P5_U1_PLD_IT8 EQU 0x40011aa0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT9 +CYDEV_UCFG_B1_P5_U1_PLD_IT9 EQU 0x40011aa4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT10 +CYDEV_UCFG_B1_P5_U1_PLD_IT10 EQU 0x40011aa8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT11 +CYDEV_UCFG_B1_P5_U1_PLD_IT11 EQU 0x40011aac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT0 +CYDEV_UCFG_B1_P5_U1_PLD_ORT0 EQU 0x40011ab0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT1 +CYDEV_UCFG_B1_P5_U1_PLD_ORT1 EQU 0x40011ab2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT2 +CYDEV_UCFG_B1_P5_U1_PLD_ORT2 EQU 0x40011ab4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT3 +CYDEV_UCFG_B1_P5_U1_PLD_ORT3 EQU 0x40011ab6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST EQU 0x40011ab8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB EQU 0x40011aba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET EQU 0x40011abc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS EQU 0x40011abe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG0 +CYDEV_UCFG_B1_P5_U1_CFG0 EQU 0x40011ac0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG1 +CYDEV_UCFG_B1_P5_U1_CFG1 EQU 0x40011ac1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG2 +CYDEV_UCFG_B1_P5_U1_CFG2 EQU 0x40011ac2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG3 +CYDEV_UCFG_B1_P5_U1_CFG3 EQU 0x40011ac3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG4 +CYDEV_UCFG_B1_P5_U1_CFG4 EQU 0x40011ac4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG5 +CYDEV_UCFG_B1_P5_U1_CFG5 EQU 0x40011ac5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG6 +CYDEV_UCFG_B1_P5_U1_CFG6 EQU 0x40011ac6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG7 +CYDEV_UCFG_B1_P5_U1_CFG7 EQU 0x40011ac7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG8 +CYDEV_UCFG_B1_P5_U1_CFG8 EQU 0x40011ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG9 +CYDEV_UCFG_B1_P5_U1_CFG9 EQU 0x40011ac9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG10 +CYDEV_UCFG_B1_P5_U1_CFG10 EQU 0x40011aca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG11 +CYDEV_UCFG_B1_P5_U1_CFG11 EQU 0x40011acb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG12 +CYDEV_UCFG_B1_P5_U1_CFG12 EQU 0x40011acc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG13 +CYDEV_UCFG_B1_P5_U1_CFG13 EQU 0x40011acd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG14 +CYDEV_UCFG_B1_P5_U1_CFG14 EQU 0x40011ace + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG15 +CYDEV_UCFG_B1_P5_U1_CFG15 EQU 0x40011acf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG16 +CYDEV_UCFG_B1_P5_U1_CFG16 EQU 0x40011ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG17 +CYDEV_UCFG_B1_P5_U1_CFG17 EQU 0x40011ad1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG18 +CYDEV_UCFG_B1_P5_U1_CFG18 EQU 0x40011ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG19 +CYDEV_UCFG_B1_P5_U1_CFG19 EQU 0x40011ad3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG20 +CYDEV_UCFG_B1_P5_U1_CFG20 EQU 0x40011ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG21 +CYDEV_UCFG_B1_P5_U1_CFG21 EQU 0x40011ad5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG22 +CYDEV_UCFG_B1_P5_U1_CFG22 EQU 0x40011ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG23 +CYDEV_UCFG_B1_P5_U1_CFG23 EQU 0x40011ad7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG24 +CYDEV_UCFG_B1_P5_U1_CFG24 EQU 0x40011ad8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG25 +CYDEV_UCFG_B1_P5_U1_CFG25 EQU 0x40011ad9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG26 +CYDEV_UCFG_B1_P5_U1_CFG26 EQU 0x40011ada + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG27 +CYDEV_UCFG_B1_P5_U1_CFG27 EQU 0x40011adb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG28 +CYDEV_UCFG_B1_P5_U1_CFG28 EQU 0x40011adc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG29 +CYDEV_UCFG_B1_P5_U1_CFG29 EQU 0x40011add + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG30 +CYDEV_UCFG_B1_P5_U1_CFG30 EQU 0x40011ade + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG31 +CYDEV_UCFG_B1_P5_U1_CFG31 EQU 0x40011adf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG0 +CYDEV_UCFG_B1_P5_U1_DCFG0 EQU 0x40011ae0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG1 +CYDEV_UCFG_B1_P5_U1_DCFG1 EQU 0x40011ae2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG2 +CYDEV_UCFG_B1_P5_U1_DCFG2 EQU 0x40011ae4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG3 +CYDEV_UCFG_B1_P5_U1_DCFG3 EQU 0x40011ae6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG4 +CYDEV_UCFG_B1_P5_U1_DCFG4 EQU 0x40011ae8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG5 +CYDEV_UCFG_B1_P5_U1_DCFG5 EQU 0x40011aea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG6 +CYDEV_UCFG_B1_P5_U1_DCFG6 EQU 0x40011aec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG7 +CYDEV_UCFG_B1_P5_U1_DCFG7 EQU 0x40011aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_BASE +CYDEV_UCFG_B1_P5_ROUTE_BASE EQU 0x40011b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_SIZE +CYDEV_UCFG_B1_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_BASE +CYDEV_UCFG_DSI0_BASE EQU 0x40014000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_SIZE +CYDEV_UCFG_DSI0_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_BASE +CYDEV_UCFG_DSI1_BASE EQU 0x40014100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_SIZE +CYDEV_UCFG_DSI1_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_BASE +CYDEV_UCFG_DSI2_BASE EQU 0x40014200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_SIZE +CYDEV_UCFG_DSI2_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_BASE +CYDEV_UCFG_DSI3_BASE EQU 0x40014300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_SIZE +CYDEV_UCFG_DSI3_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_BASE +CYDEV_UCFG_DSI4_BASE EQU 0x40014400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_SIZE +CYDEV_UCFG_DSI4_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_BASE +CYDEV_UCFG_DSI5_BASE EQU 0x40014500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_SIZE +CYDEV_UCFG_DSI5_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_BASE +CYDEV_UCFG_DSI6_BASE EQU 0x40014600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_SIZE +CYDEV_UCFG_DSI6_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_BASE +CYDEV_UCFG_DSI7_BASE EQU 0x40014700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_SIZE +CYDEV_UCFG_DSI7_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_BASE +CYDEV_UCFG_DSI8_BASE EQU 0x40014800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_SIZE +CYDEV_UCFG_DSI8_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_BASE +CYDEV_UCFG_DSI9_BASE EQU 0x40014900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_SIZE +CYDEV_UCFG_DSI9_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_BASE +CYDEV_UCFG_DSI12_BASE EQU 0x40014c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_SIZE +CYDEV_UCFG_DSI12_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_BASE +CYDEV_UCFG_DSI13_BASE EQU 0x40014d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_SIZE +CYDEV_UCFG_DSI13_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BASE +CYDEV_UCFG_BCTL0_BASE EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_SIZE +CYDEV_UCFG_BCTL0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_MDCLK_EN +CYDEV_UCFG_BCTL0_MDCLK_EN EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_MBCLK_EN +CYDEV_UCFG_BCTL0_MBCLK_EN EQU 0x40015001 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_WAIT_CFG +CYDEV_UCFG_BCTL0_WAIT_CFG EQU 0x40015002 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BANK_CTL +CYDEV_UCFG_BCTL0_BANK_CTL EQU 0x40015003 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_UDB_TEST_3 +CYDEV_UCFG_BCTL0_UDB_TEST_3 EQU 0x40015007 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN0 +CYDEV_UCFG_BCTL0_DCLK_EN0 EQU 0x40015008 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN0 +CYDEV_UCFG_BCTL0_BCLK_EN0 EQU 0x40015009 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN1 +CYDEV_UCFG_BCTL0_DCLK_EN1 EQU 0x4001500a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN1 +CYDEV_UCFG_BCTL0_BCLK_EN1 EQU 0x4001500b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN2 +CYDEV_UCFG_BCTL0_DCLK_EN2 EQU 0x4001500c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN2 +CYDEV_UCFG_BCTL0_BCLK_EN2 EQU 0x4001500d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN3 +CYDEV_UCFG_BCTL0_DCLK_EN3 EQU 0x4001500e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN3 +CYDEV_UCFG_BCTL0_BCLK_EN3 EQU 0x4001500f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BASE +CYDEV_UCFG_BCTL1_BASE EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_SIZE +CYDEV_UCFG_BCTL1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_MDCLK_EN +CYDEV_UCFG_BCTL1_MDCLK_EN EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_MBCLK_EN +CYDEV_UCFG_BCTL1_MBCLK_EN EQU 0x40015011 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_WAIT_CFG +CYDEV_UCFG_BCTL1_WAIT_CFG EQU 0x40015012 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BANK_CTL +CYDEV_UCFG_BCTL1_BANK_CTL EQU 0x40015013 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_UDB_TEST_3 +CYDEV_UCFG_BCTL1_UDB_TEST_3 EQU 0x40015017 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN0 +CYDEV_UCFG_BCTL1_DCLK_EN0 EQU 0x40015018 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN0 +CYDEV_UCFG_BCTL1_BCLK_EN0 EQU 0x40015019 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN1 +CYDEV_UCFG_BCTL1_DCLK_EN1 EQU 0x4001501a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN1 +CYDEV_UCFG_BCTL1_BCLK_EN1 EQU 0x4001501b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN2 +CYDEV_UCFG_BCTL1_DCLK_EN2 EQU 0x4001501c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN2 +CYDEV_UCFG_BCTL1_BCLK_EN2 EQU 0x4001501d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN3 +CYDEV_UCFG_BCTL1_DCLK_EN3 EQU 0x4001501e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN3 +CYDEV_UCFG_BCTL1_BCLK_EN3 EQU 0x4001501f + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_BASE +CYDEV_IDMUX_BASE EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_SIZE +CYDEV_IDMUX_SIZE EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL0 +CYDEV_IDMUX_IRQ_CTL0 EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL1 +CYDEV_IDMUX_IRQ_CTL1 EQU 0x40015101 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL2 +CYDEV_IDMUX_IRQ_CTL2 EQU 0x40015102 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL3 +CYDEV_IDMUX_IRQ_CTL3 EQU 0x40015103 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL4 +CYDEV_IDMUX_IRQ_CTL4 EQU 0x40015104 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL5 +CYDEV_IDMUX_IRQ_CTL5 EQU 0x40015105 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL6 +CYDEV_IDMUX_IRQ_CTL6 EQU 0x40015106 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL7 +CYDEV_IDMUX_IRQ_CTL7 EQU 0x40015107 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL0 +CYDEV_IDMUX_DRQ_CTL0 EQU 0x40015110 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL1 +CYDEV_IDMUX_DRQ_CTL1 EQU 0x40015111 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL2 +CYDEV_IDMUX_DRQ_CTL2 EQU 0x40015112 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL3 +CYDEV_IDMUX_DRQ_CTL3 EQU 0x40015113 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL4 +CYDEV_IDMUX_DRQ_CTL4 EQU 0x40015114 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL5 +CYDEV_IDMUX_DRQ_CTL5 EQU 0x40015115 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_BASE +CYDEV_CACHERAM_BASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_SIZE +CYDEV_CACHERAM_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_DATA_MBASE +CYDEV_CACHERAM_DATA_MBASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_DATA_MSIZE +CYDEV_CACHERAM_DATA_MSIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_BASE +CYDEV_SFR_BASE EQU 0x40050100 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_SIZE +CYDEV_SFR_SIZE EQU 0x000000fb + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO0 +CYDEV_SFR_GPIO0 EQU 0x40050180 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD0 +CYDEV_SFR_GPIRD0 EQU 0x40050189 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO0_SEL +CYDEV_SFR_GPIO0_SEL EQU 0x4005018a + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO1 +CYDEV_SFR_GPIO1 EQU 0x40050190 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD1 +CYDEV_SFR_GPIRD1 EQU 0x40050191 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO2 +CYDEV_SFR_GPIO2 EQU 0x40050198 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD2 +CYDEV_SFR_GPIRD2 EQU 0x40050199 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO2_SEL +CYDEV_SFR_GPIO2_SEL EQU 0x4005019a + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO1_SEL +CYDEV_SFR_GPIO1_SEL EQU 0x400501a2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO3 +CYDEV_SFR_GPIO3 EQU 0x400501b0 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD3 +CYDEV_SFR_GPIRD3 EQU 0x400501b1 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO3_SEL +CYDEV_SFR_GPIO3_SEL EQU 0x400501b2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO4 +CYDEV_SFR_GPIO4 EQU 0x400501c0 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD4 +CYDEV_SFR_GPIRD4 EQU 0x400501c1 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO4_SEL +CYDEV_SFR_GPIO4_SEL EQU 0x400501c2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO5 +CYDEV_SFR_GPIO5 EQU 0x400501c8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD5 +CYDEV_SFR_GPIRD5 EQU 0x400501c9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO5_SEL +CYDEV_SFR_GPIO5_SEL EQU 0x400501ca + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO6 +CYDEV_SFR_GPIO6 EQU 0x400501d8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD6 +CYDEV_SFR_GPIRD6 EQU 0x400501d9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO6_SEL +CYDEV_SFR_GPIO6_SEL EQU 0x400501da + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO12 +CYDEV_SFR_GPIO12 EQU 0x400501e8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD12 +CYDEV_SFR_GPIRD12 EQU 0x400501e9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO12_SEL +CYDEV_SFR_GPIO12_SEL EQU 0x400501f2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO15 +CYDEV_SFR_GPIO15 EQU 0x400501f8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD15 +CYDEV_SFR_GPIRD15 EQU 0x400501f9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO15_SEL +CYDEV_SFR_GPIO15_SEL EQU 0x400501fa + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_BASE +CYDEV_P3BA_BASE EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SIZE +CYDEV_P3BA_SIZE EQU 0x0000002b + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_Y_START +CYDEV_P3BA_Y_START EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_YROLL +CYDEV_P3BA_YROLL EQU 0x40050301 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_YCFG +CYDEV_P3BA_YCFG EQU 0x40050302 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_START1 +CYDEV_P3BA_X_START1 EQU 0x40050303 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_START2 +CYDEV_P3BA_X_START2 EQU 0x40050304 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XROLL1 +CYDEV_P3BA_XROLL1 EQU 0x40050305 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XROLL2 +CYDEV_P3BA_XROLL2 EQU 0x40050306 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XINC +CYDEV_P3BA_XINC EQU 0x40050307 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XCFG +CYDEV_P3BA_XCFG EQU 0x40050308 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR1 +CYDEV_P3BA_OFFSETADDR1 EQU 0x40050309 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR2 +CYDEV_P3BA_OFFSETADDR2 EQU 0x4005030a + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR3 +CYDEV_P3BA_OFFSETADDR3 EQU 0x4005030b + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR1 +CYDEV_P3BA_ABSADDR1 EQU 0x4005030c + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR2 +CYDEV_P3BA_ABSADDR2 EQU 0x4005030d + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR3 +CYDEV_P3BA_ABSADDR3 EQU 0x4005030e + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR4 +CYDEV_P3BA_ABSADDR4 EQU 0x4005030f + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATCFG1 +CYDEV_P3BA_DATCFG1 EQU 0x40050310 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATCFG2 +CYDEV_P3BA_DATCFG2 EQU 0x40050311 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT1 +CYDEV_P3BA_CMP_RSLT1 EQU 0x40050314 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT2 +CYDEV_P3BA_CMP_RSLT2 EQU 0x40050315 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT3 +CYDEV_P3BA_CMP_RSLT3 EQU 0x40050316 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT4 +CYDEV_P3BA_CMP_RSLT4 EQU 0x40050317 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG1 +CYDEV_P3BA_DATA_REG1 EQU 0x40050318 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG2 +CYDEV_P3BA_DATA_REG2 EQU 0x40050319 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG3 +CYDEV_P3BA_DATA_REG3 EQU 0x4005031a + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG4 +CYDEV_P3BA_DATA_REG4 EQU 0x4005031b + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA1 +CYDEV_P3BA_EXP_DATA1 EQU 0x4005031c + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA2 +CYDEV_P3BA_EXP_DATA2 EQU 0x4005031d + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA3 +CYDEV_P3BA_EXP_DATA3 EQU 0x4005031e + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA4 +CYDEV_P3BA_EXP_DATA4 EQU 0x4005031f + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA1 +CYDEV_P3BA_MSTR_HRDATA1 EQU 0x40050320 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA2 +CYDEV_P3BA_MSTR_HRDATA2 EQU 0x40050321 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA3 +CYDEV_P3BA_MSTR_HRDATA3 EQU 0x40050322 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA4 +CYDEV_P3BA_MSTR_HRDATA4 EQU 0x40050323 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_BIST_EN +CYDEV_P3BA_BIST_EN EQU 0x40050324 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_PHUB_MASTER_SSR +CYDEV_P3BA_PHUB_MASTER_SSR EQU 0x40050325 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SEQCFG1 +CYDEV_P3BA_SEQCFG1 EQU 0x40050326 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SEQCFG2 +CYDEV_P3BA_SEQCFG2 EQU 0x40050327 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_Y_CURR +CYDEV_P3BA_Y_CURR EQU 0x40050328 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_CURR1 +CYDEV_P3BA_X_CURR1 EQU 0x40050329 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_CURR2 +CYDEV_P3BA_X_CURR2 EQU 0x4005032a + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_BASE +CYDEV_PANTHER_BASE EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_SIZE +CYDEV_PANTHER_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_STCALIB_CFG +CYDEV_PANTHER_STCALIB_CFG EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_WAITPIPE +CYDEV_PANTHER_WAITPIPE EQU 0x40080004 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_TRACE_CFG +CYDEV_PANTHER_TRACE_CFG EQU 0x40080008 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_DBG_CFG +CYDEV_PANTHER_DBG_CFG EQU 0x4008000c + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_CM3_LCKRST_STAT +CYDEV_PANTHER_CM3_LCKRST_STAT EQU 0x40080018 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_DEVICE_ID +CYDEV_PANTHER_DEVICE_ID EQU 0x4008001c + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_BASE +CYDEV_FLSECC_BASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_SIZE +CYDEV_FLSECC_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_DATA_MBASE +CYDEV_FLSECC_DATA_MBASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_DATA_MSIZE +CYDEV_FLSECC_DATA_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_BASE +CYDEV_FLSHID_BASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_SIZE +CYDEV_FLSHID_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_RSVD_MBASE +CYDEV_FLSHID_RSVD_MBASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_RSVD_MSIZE +CYDEV_FLSHID_RSVD_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_MDATA_MBASE +CYDEV_FLSHID_CUST_MDATA_MBASE EQU 0x49000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_MDATA_MSIZE +CYDEV_FLSHID_CUST_MDATA_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_BASE +CYDEV_FLSHID_CUST_TABLES_BASE EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_SIZE +CYDEV_FLSHID_CUST_TABLES_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_Y_LOC +CYDEV_FLSHID_CUST_TABLES_Y_LOC EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_X_LOC +CYDEV_FLSHID_CUST_TABLES_X_LOC EQU 0x49000101 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_WAFER_NUM +CYDEV_FLSHID_CUST_TABLES_WAFER_NUM EQU 0x49000102 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_LOT_LSB +CYDEV_FLSHID_CUST_TABLES_LOT_LSB EQU 0x49000103 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_LOT_MSB +CYDEV_FLSHID_CUST_TABLES_LOT_MSB EQU 0x49000104 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_WRK_WK +CYDEV_FLSHID_CUST_TABLES_WRK_WK EQU 0x49000105 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_FAB_YR +CYDEV_FLSHID_CUST_TABLES_FAB_YR EQU 0x49000106 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_MINOR +CYDEV_FLSHID_CUST_TABLES_MINOR EQU 0x49000107 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ EQU 0x49000108 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ EQU 0x49000109 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ EQU 0x4900010a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ EQU 0x4900010b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ EQU 0x4900010c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ EQU 0x4900010d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ EQU 0x4900010e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_USB +CYDEV_FLSHID_CUST_TABLES_IMO_USB EQU 0x4900010f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS EQU 0x49000110 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS EQU 0x49000111 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS EQU 0x49000112 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS EQU 0x49000113 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS EQU 0x49000114 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS EQU 0x49000115 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS EQU 0x49000116 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS EQU 0x49000117 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M1 +CYDEV_FLSHID_CUST_TABLES_DEC_M1 EQU 0x49000118 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M2 +CYDEV_FLSHID_CUST_TABLES_DEC_M2 EQU 0x49000119 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M3 +CYDEV_FLSHID_CUST_TABLES_DEC_M3 EQU 0x4900011a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M4 +CYDEV_FLSHID_CUST_TABLES_DEC_M4 EQU 0x4900011b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M5 +CYDEV_FLSHID_CUST_TABLES_DEC_M5 EQU 0x4900011c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M6 +CYDEV_FLSHID_CUST_TABLES_DEC_M6 EQU 0x4900011d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M7 +CYDEV_FLSHID_CUST_TABLES_DEC_M7 EQU 0x4900011e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M8 +CYDEV_FLSHID_CUST_TABLES_DEC_M8 EQU 0x4900011f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M1 +CYDEV_FLSHID_CUST_TABLES_DAC0_M1 EQU 0x49000120 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M2 +CYDEV_FLSHID_CUST_TABLES_DAC0_M2 EQU 0x49000121 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M3 +CYDEV_FLSHID_CUST_TABLES_DAC0_M3 EQU 0x49000122 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M4 +CYDEV_FLSHID_CUST_TABLES_DAC0_M4 EQU 0x49000123 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M5 +CYDEV_FLSHID_CUST_TABLES_DAC0_M5 EQU 0x49000124 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M6 +CYDEV_FLSHID_CUST_TABLES_DAC0_M6 EQU 0x49000125 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M7 +CYDEV_FLSHID_CUST_TABLES_DAC0_M7 EQU 0x49000126 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M8 +CYDEV_FLSHID_CUST_TABLES_DAC0_M8 EQU 0x49000127 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M1 +CYDEV_FLSHID_CUST_TABLES_DAC2_M1 EQU 0x49000128 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M2 +CYDEV_FLSHID_CUST_TABLES_DAC2_M2 EQU 0x49000129 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M3 +CYDEV_FLSHID_CUST_TABLES_DAC2_M3 EQU 0x4900012a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M4 +CYDEV_FLSHID_CUST_TABLES_DAC2_M4 EQU 0x4900012b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M5 +CYDEV_FLSHID_CUST_TABLES_DAC2_M5 EQU 0x4900012c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M6 +CYDEV_FLSHID_CUST_TABLES_DAC2_M6 EQU 0x4900012d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M7 +CYDEV_FLSHID_CUST_TABLES_DAC2_M7 EQU 0x4900012e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M8 +CYDEV_FLSHID_CUST_TABLES_DAC2_M8 EQU 0x4900012f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M1 +CYDEV_FLSHID_CUST_TABLES_DAC1_M1 EQU 0x49000130 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M2 +CYDEV_FLSHID_CUST_TABLES_DAC1_M2 EQU 0x49000131 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M3 +CYDEV_FLSHID_CUST_TABLES_DAC1_M3 EQU 0x49000132 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M4 +CYDEV_FLSHID_CUST_TABLES_DAC1_M4 EQU 0x49000133 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M5 +CYDEV_FLSHID_CUST_TABLES_DAC1_M5 EQU 0x49000134 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M6 +CYDEV_FLSHID_CUST_TABLES_DAC1_M6 EQU 0x49000135 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M7 +CYDEV_FLSHID_CUST_TABLES_DAC1_M7 EQU 0x49000136 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M8 +CYDEV_FLSHID_CUST_TABLES_DAC1_M8 EQU 0x49000137 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M1 +CYDEV_FLSHID_CUST_TABLES_DAC3_M1 EQU 0x49000138 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M2 +CYDEV_FLSHID_CUST_TABLES_DAC3_M2 EQU 0x49000139 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M3 +CYDEV_FLSHID_CUST_TABLES_DAC3_M3 EQU 0x4900013a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M4 +CYDEV_FLSHID_CUST_TABLES_DAC3_M4 EQU 0x4900013b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M5 +CYDEV_FLSHID_CUST_TABLES_DAC3_M5 EQU 0x4900013c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M6 +CYDEV_FLSHID_CUST_TABLES_DAC3_M6 EQU 0x4900013d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M7 +CYDEV_FLSHID_CUST_TABLES_DAC3_M7 EQU 0x4900013e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M8 +CYDEV_FLSHID_CUST_TABLES_DAC3_M8 EQU 0x4900013f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BASE +CYDEV_FLSHID_MFG_CFG_BASE EQU 0x49000180 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_SIZE +CYDEV_FLSHID_MFG_CFG_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_IMO_TR1 +CYDEV_FLSHID_MFG_CFG_IMO_TR1 EQU 0x49000188 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP0_TR0 +CYDEV_FLSHID_MFG_CFG_CMP0_TR0 EQU 0x490001ac + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP1_TR0 +CYDEV_FLSHID_MFG_CFG_CMP1_TR0 EQU 0x490001ae + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP2_TR0 +CYDEV_FLSHID_MFG_CFG_CMP2_TR0 EQU 0x490001b0 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP3_TR0 +CYDEV_FLSHID_MFG_CFG_CMP3_TR0 EQU 0x490001b2 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP0_TR1 +CYDEV_FLSHID_MFG_CFG_CMP0_TR1 EQU 0x490001b4 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP1_TR1 +CYDEV_FLSHID_MFG_CFG_CMP1_TR1 EQU 0x490001b6 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP2_TR1 +CYDEV_FLSHID_MFG_CFG_CMP2_TR1 EQU 0x490001b8 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP3_TR1 +CYDEV_FLSHID_MFG_CFG_CMP3_TR1 EQU 0x490001ba + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM +CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM EQU 0x490001ce + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_BASE +CYDEV_EXTMEM_BASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_SIZE +CYDEV_EXTMEM_SIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_DATA_MBASE +CYDEV_EXTMEM_DATA_MBASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_DATA_MSIZE +CYDEV_EXTMEM_DATA_MSIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_BASE +CYDEV_ITM_BASE EQU 0xe0000000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_SIZE +CYDEV_ITM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_TRACE_EN +CYDEV_ITM_TRACE_EN EQU 0xe0000e00 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_TRACE_PRIVILEGE +CYDEV_ITM_TRACE_PRIVILEGE EQU 0xe0000e40 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_TRACE_CTRL +CYDEV_ITM_TRACE_CTRL EQU 0xe0000e80 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_LOCK_ACCESS +CYDEV_ITM_LOCK_ACCESS EQU 0xe0000fb0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_LOCK_STATUS +CYDEV_ITM_LOCK_STATUS EQU 0xe0000fb4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID4 +CYDEV_ITM_PID4 EQU 0xe0000fd0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID5 +CYDEV_ITM_PID5 EQU 0xe0000fd4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID6 +CYDEV_ITM_PID6 EQU 0xe0000fd8 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID7 +CYDEV_ITM_PID7 EQU 0xe0000fdc + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID0 +CYDEV_ITM_PID0 EQU 0xe0000fe0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID1 +CYDEV_ITM_PID1 EQU 0xe0000fe4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID2 +CYDEV_ITM_PID2 EQU 0xe0000fe8 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID3 +CYDEV_ITM_PID3 EQU 0xe0000fec + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID0 +CYDEV_ITM_CID0 EQU 0xe0000ff0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID1 +CYDEV_ITM_CID1 EQU 0xe0000ff4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID2 +CYDEV_ITM_CID2 EQU 0xe0000ff8 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID3 +CYDEV_ITM_CID3 EQU 0xe0000ffc + ENDIF + IF :LNOT::DEF:CYDEV_DWT_BASE +CYDEV_DWT_BASE EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_SIZE +CYDEV_DWT_SIZE EQU 0x0000005c + ENDIF + IF :LNOT::DEF:CYDEV_DWT_CTRL +CYDEV_DWT_CTRL EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_CYCLE_COUNT +CYDEV_DWT_CYCLE_COUNT EQU 0xe0001004 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_CPI_COUNT +CYDEV_DWT_CPI_COUNT EQU 0xe0001008 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_EXC_OVHD_COUNT +CYDEV_DWT_EXC_OVHD_COUNT EQU 0xe000100c + ENDIF + IF :LNOT::DEF:CYDEV_DWT_SLEEP_COUNT +CYDEV_DWT_SLEEP_COUNT EQU 0xe0001010 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_LSU_COUNT +CYDEV_DWT_LSU_COUNT EQU 0xe0001014 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FOLD_COUNT +CYDEV_DWT_FOLD_COUNT EQU 0xe0001018 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_PC_SAMPLE +CYDEV_DWT_PC_SAMPLE EQU 0xe000101c + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_0 +CYDEV_DWT_COMP_0 EQU 0xe0001020 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_0 +CYDEV_DWT_MASK_0 EQU 0xe0001024 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_0 +CYDEV_DWT_FUNCTION_0 EQU 0xe0001028 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_1 +CYDEV_DWT_COMP_1 EQU 0xe0001030 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_1 +CYDEV_DWT_MASK_1 EQU 0xe0001034 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_1 +CYDEV_DWT_FUNCTION_1 EQU 0xe0001038 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_2 +CYDEV_DWT_COMP_2 EQU 0xe0001040 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_2 +CYDEV_DWT_MASK_2 EQU 0xe0001044 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_2 +CYDEV_DWT_FUNCTION_2 EQU 0xe0001048 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_3 +CYDEV_DWT_COMP_3 EQU 0xe0001050 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_3 +CYDEV_DWT_MASK_3 EQU 0xe0001054 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_3 +CYDEV_DWT_FUNCTION_3 EQU 0xe0001058 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_BASE +CYDEV_FPB_BASE EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_SIZE +CYDEV_FPB_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CTRL +CYDEV_FPB_CTRL EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_REMAP +CYDEV_FPB_REMAP EQU 0xe0002004 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_0 +CYDEV_FPB_FP_COMP_0 EQU 0xe0002008 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_1 +CYDEV_FPB_FP_COMP_1 EQU 0xe000200c + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_2 +CYDEV_FPB_FP_COMP_2 EQU 0xe0002010 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_3 +CYDEV_FPB_FP_COMP_3 EQU 0xe0002014 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_4 +CYDEV_FPB_FP_COMP_4 EQU 0xe0002018 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_5 +CYDEV_FPB_FP_COMP_5 EQU 0xe000201c + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_6 +CYDEV_FPB_FP_COMP_6 EQU 0xe0002020 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_7 +CYDEV_FPB_FP_COMP_7 EQU 0xe0002024 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID4 +CYDEV_FPB_PID4 EQU 0xe0002fd0 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID5 +CYDEV_FPB_PID5 EQU 0xe0002fd4 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID6 +CYDEV_FPB_PID6 EQU 0xe0002fd8 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID7 +CYDEV_FPB_PID7 EQU 0xe0002fdc + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID0 +CYDEV_FPB_PID0 EQU 0xe0002fe0 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID1 +CYDEV_FPB_PID1 EQU 0xe0002fe4 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID2 +CYDEV_FPB_PID2 EQU 0xe0002fe8 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID3 +CYDEV_FPB_PID3 EQU 0xe0002fec + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID0 +CYDEV_FPB_CID0 EQU 0xe0002ff0 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID1 +CYDEV_FPB_CID1 EQU 0xe0002ff4 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID2 +CYDEV_FPB_CID2 EQU 0xe0002ff8 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID3 +CYDEV_FPB_CID3 EQU 0xe0002ffc + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BASE +CYDEV_NVIC_BASE EQU 0xe000e000 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SIZE +CYDEV_NVIC_SIZE EQU 0x00000d3c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_INT_CTL_TYPE +CYDEV_NVIC_INT_CTL_TYPE EQU 0xe000e004 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CTL +CYDEV_NVIC_SYSTICK_CTL EQU 0xe000e010 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_RELOAD +CYDEV_NVIC_SYSTICK_RELOAD EQU 0xe000e014 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CURRENT +CYDEV_NVIC_SYSTICK_CURRENT EQU 0xe000e018 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CAL +CYDEV_NVIC_SYSTICK_CAL EQU 0xe000e01c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SETENA0 +CYDEV_NVIC_SETENA0 EQU 0xe000e100 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CLRENA0 +CYDEV_NVIC_CLRENA0 EQU 0xe000e180 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SETPEND0 +CYDEV_NVIC_SETPEND0 EQU 0xe000e200 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CLRPEND0 +CYDEV_NVIC_CLRPEND0 EQU 0xe000e280 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_ACTIVE0 +CYDEV_NVIC_ACTIVE0 EQU 0xe000e300 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_0 +CYDEV_NVIC_PRI_0 EQU 0xe000e400 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_1 +CYDEV_NVIC_PRI_1 EQU 0xe000e401 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_2 +CYDEV_NVIC_PRI_2 EQU 0xe000e402 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_3 +CYDEV_NVIC_PRI_3 EQU 0xe000e403 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_4 +CYDEV_NVIC_PRI_4 EQU 0xe000e404 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_5 +CYDEV_NVIC_PRI_5 EQU 0xe000e405 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_6 +CYDEV_NVIC_PRI_6 EQU 0xe000e406 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_7 +CYDEV_NVIC_PRI_7 EQU 0xe000e407 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_8 +CYDEV_NVIC_PRI_8 EQU 0xe000e408 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_9 +CYDEV_NVIC_PRI_9 EQU 0xe000e409 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_10 +CYDEV_NVIC_PRI_10 EQU 0xe000e40a + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_11 +CYDEV_NVIC_PRI_11 EQU 0xe000e40b + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_12 +CYDEV_NVIC_PRI_12 EQU 0xe000e40c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_13 +CYDEV_NVIC_PRI_13 EQU 0xe000e40d + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_14 +CYDEV_NVIC_PRI_14 EQU 0xe000e40e + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_15 +CYDEV_NVIC_PRI_15 EQU 0xe000e40f + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_16 +CYDEV_NVIC_PRI_16 EQU 0xe000e410 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_17 +CYDEV_NVIC_PRI_17 EQU 0xe000e411 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_18 +CYDEV_NVIC_PRI_18 EQU 0xe000e412 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_19 +CYDEV_NVIC_PRI_19 EQU 0xe000e413 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_20 +CYDEV_NVIC_PRI_20 EQU 0xe000e414 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_21 +CYDEV_NVIC_PRI_21 EQU 0xe000e415 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_22 +CYDEV_NVIC_PRI_22 EQU 0xe000e416 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_23 +CYDEV_NVIC_PRI_23 EQU 0xe000e417 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_24 +CYDEV_NVIC_PRI_24 EQU 0xe000e418 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_25 +CYDEV_NVIC_PRI_25 EQU 0xe000e419 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_26 +CYDEV_NVIC_PRI_26 EQU 0xe000e41a + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_27 +CYDEV_NVIC_PRI_27 EQU 0xe000e41b + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_28 +CYDEV_NVIC_PRI_28 EQU 0xe000e41c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_29 +CYDEV_NVIC_PRI_29 EQU 0xe000e41d + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_30 +CYDEV_NVIC_PRI_30 EQU 0xe000e41e + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_31 +CYDEV_NVIC_PRI_31 EQU 0xe000e41f + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CPUID_BASE +CYDEV_NVIC_CPUID_BASE EQU 0xe000ed00 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_INTR_CTRL_STATE +CYDEV_NVIC_INTR_CTRL_STATE EQU 0xe000ed04 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_VECT_OFFSET +CYDEV_NVIC_VECT_OFFSET EQU 0xe000ed08 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_APPLN_INTR +CYDEV_NVIC_APPLN_INTR EQU 0xe000ed0c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTEM_CONTROL +CYDEV_NVIC_SYSTEM_CONTROL EQU 0xe000ed10 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CFG_CONTROL +CYDEV_NVIC_CFG_CONTROL EQU 0xe000ed14 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 +CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 EQU 0xe000ed18 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 +CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 EQU 0xe000ed1c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 +CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 EQU 0xe000ed20 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_HANDLER_CSR +CYDEV_NVIC_SYS_HANDLER_CSR EQU 0xe000ed24 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_MEMMAN_FAULT_STATUS +CYDEV_NVIC_MEMMAN_FAULT_STATUS EQU 0xe000ed28 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BUS_FAULT_STATUS +CYDEV_NVIC_BUS_FAULT_STATUS EQU 0xe000ed29 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_USAGE_FAULT_STATUS +CYDEV_NVIC_USAGE_FAULT_STATUS EQU 0xe000ed2a + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_HARD_FAULT_STATUS +CYDEV_NVIC_HARD_FAULT_STATUS EQU 0xe000ed2c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_DEBUG_FAULT_STATUS +CYDEV_NVIC_DEBUG_FAULT_STATUS EQU 0xe000ed30 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_MEMMAN_FAULT_ADD +CYDEV_NVIC_MEMMAN_FAULT_ADD EQU 0xe000ed34 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BUS_FAULT_ADD +CYDEV_NVIC_BUS_FAULT_ADD EQU 0xe000ed38 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_BASE +CYDEV_CORE_DBG_BASE EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_SIZE +CYDEV_CORE_DBG_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_HLT_CS +CYDEV_CORE_DBG_DBG_HLT_CS EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_REG_SEL +CYDEV_CORE_DBG_DBG_REG_SEL EQU 0xe000edf4 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_REG_DATA +CYDEV_CORE_DBG_DBG_REG_DATA EQU 0xe000edf8 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_EXC_MON_CTL +CYDEV_CORE_DBG_EXC_MON_CTL EQU 0xe000edfc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_BASE +CYDEV_TPIU_BASE EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_SIZE +CYDEV_TPIU_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ +CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CURRENT_SYNC_PRT_SZ +CYDEV_TPIU_CURRENT_SYNC_PRT_SZ EQU 0xe0040004 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ASYNC_CLK_PRESCALER +CYDEV_TPIU_ASYNC_CLK_PRESCALER EQU 0xe0040010 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PROTOCOL +CYDEV_TPIU_PROTOCOL EQU 0xe00400f0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_FORM_FLUSH_STAT +CYDEV_TPIU_FORM_FLUSH_STAT EQU 0xe0040300 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_FORM_FLUSH_CTRL +CYDEV_TPIU_FORM_FLUSH_CTRL EQU 0xe0040304 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_TRIGGER +CYDEV_TPIU_TRIGGER EQU 0xe0040ee8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITETMDATA +CYDEV_TPIU_ITETMDATA EQU 0xe0040eec + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITATBCTR2 +CYDEV_TPIU_ITATBCTR2 EQU 0xe0040ef0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITATBCTR0 +CYDEV_TPIU_ITATBCTR0 EQU 0xe0040ef8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITITMDATA +CYDEV_TPIU_ITITMDATA EQU 0xe0040efc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITCTRL +CYDEV_TPIU_ITCTRL EQU 0xe0040f00 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_DEVID +CYDEV_TPIU_DEVID EQU 0xe0040fc8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_DEVTYPE +CYDEV_TPIU_DEVTYPE EQU 0xe0040fcc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID4 +CYDEV_TPIU_PID4 EQU 0xe0040fd0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID5 +CYDEV_TPIU_PID5 EQU 0xe0040fd4 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID6 +CYDEV_TPIU_PID6 EQU 0xe0040fd8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID7 +CYDEV_TPIU_PID7 EQU 0xe0040fdc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID0 +CYDEV_TPIU_PID0 EQU 0xe0040fe0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID1 +CYDEV_TPIU_PID1 EQU 0xe0040fe4 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID2 +CYDEV_TPIU_PID2 EQU 0xe0040fe8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID3 +CYDEV_TPIU_PID3 EQU 0xe0040fec + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID0 +CYDEV_TPIU_CID0 EQU 0xe0040ff0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID1 +CYDEV_TPIU_CID1 EQU 0xe0040ff4 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID2 +CYDEV_TPIU_CID2 EQU 0xe0040ff8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID3 +CYDEV_TPIU_CID3 EQU 0xe0040ffc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_BASE +CYDEV_ETM_BASE EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SIZE +CYDEV_ETM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CTL +CYDEV_ETM_CTL EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CFG_CODE +CYDEV_ETM_CFG_CODE EQU 0xe0041004 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TRIG_EVENT +CYDEV_ETM_TRIG_EVENT EQU 0xe0041008 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_STATUS +CYDEV_ETM_STATUS EQU 0xe0041010 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SYS_CFG +CYDEV_ETM_SYS_CFG EQU 0xe0041014 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TRACE_ENB_EVENT +CYDEV_ETM_TRACE_ENB_EVENT EQU 0xe0041020 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TRACE_EN_CTRL1 +CYDEV_ETM_TRACE_EN_CTRL1 EQU 0xe0041024 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_FIFOFULL_LEVEL +CYDEV_ETM_FIFOFULL_LEVEL EQU 0xe004102c + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SYNC_FREQ +CYDEV_ETM_SYNC_FREQ EQU 0xe00411e0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ETM_ID +CYDEV_ETM_ETM_ID EQU 0xe00411e4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CFG_CODE_EXT +CYDEV_ETM_CFG_CODE_EXT EQU 0xe00411e8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TR_SS_EMBICE_CTRL +CYDEV_ETM_TR_SS_EMBICE_CTRL EQU 0xe00411f0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CS_TRACE_ID +CYDEV_ETM_CS_TRACE_ID EQU 0xe0041200 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_OS_LOCK_ACCESS +CYDEV_ETM_OS_LOCK_ACCESS EQU 0xe0041300 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_OS_LOCK_STATUS +CYDEV_ETM_OS_LOCK_STATUS EQU 0xe0041304 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PDSR +CYDEV_ETM_PDSR EQU 0xe0041314 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITMISCIN +CYDEV_ETM_ITMISCIN EQU 0xe0041ee0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITTRIGOUT +CYDEV_ETM_ITTRIGOUT EQU 0xe0041ee8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITATBCTR2 +CYDEV_ETM_ITATBCTR2 EQU 0xe0041ef0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITATBCTR0 +CYDEV_ETM_ITATBCTR0 EQU 0xe0041ef8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_INT_MODE_CTRL +CYDEV_ETM_INT_MODE_CTRL EQU 0xe0041f00 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CLM_TAG_SET +CYDEV_ETM_CLM_TAG_SET EQU 0xe0041fa0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CLM_TAG_CLR +CYDEV_ETM_CLM_TAG_CLR EQU 0xe0041fa4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_LOCK_ACCESS +CYDEV_ETM_LOCK_ACCESS EQU 0xe0041fb0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_LOCK_STATUS +CYDEV_ETM_LOCK_STATUS EQU 0xe0041fb4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_AUTH_STATUS +CYDEV_ETM_AUTH_STATUS EQU 0xe0041fb8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_DEV_TYPE +CYDEV_ETM_DEV_TYPE EQU 0xe0041fcc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID4 +CYDEV_ETM_PID4 EQU 0xe0041fd0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID5 +CYDEV_ETM_PID5 EQU 0xe0041fd4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID6 +CYDEV_ETM_PID6 EQU 0xe0041fd8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID7 +CYDEV_ETM_PID7 EQU 0xe0041fdc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID0 +CYDEV_ETM_PID0 EQU 0xe0041fe0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID1 +CYDEV_ETM_PID1 EQU 0xe0041fe4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID2 +CYDEV_ETM_PID2 EQU 0xe0041fe8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID3 +CYDEV_ETM_PID3 EQU 0xe0041fec + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID0 +CYDEV_ETM_CID0 EQU 0xe0041ff0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID1 +CYDEV_ETM_CID1 EQU 0xe0041ff4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID2 +CYDEV_ETM_CID2 EQU 0xe0041ff8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID3 +CYDEV_ETM_CID3 EQU 0xe0041ffc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_BASE +CYDEV_ROM_TABLE_BASE EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_SIZE +CYDEV_ROM_TABLE_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_NVIC +CYDEV_ROM_TABLE_NVIC EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_DWT +CYDEV_ROM_TABLE_DWT EQU 0xe00ff004 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_FPB +CYDEV_ROM_TABLE_FPB EQU 0xe00ff008 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_ITM +CYDEV_ROM_TABLE_ITM EQU 0xe00ff00c + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_TPIU +CYDEV_ROM_TABLE_TPIU EQU 0xe00ff010 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_ETM +CYDEV_ROM_TABLE_ETM EQU 0xe00ff014 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_END +CYDEV_ROM_TABLE_END EQU 0xe00ff018 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_MEMTYPE +CYDEV_ROM_TABLE_MEMTYPE EQU 0xe00fffcc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID4 +CYDEV_ROM_TABLE_PID4 EQU 0xe00fffd0 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID5 +CYDEV_ROM_TABLE_PID5 EQU 0xe00fffd4 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID6 +CYDEV_ROM_TABLE_PID6 EQU 0xe00fffd8 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID7 +CYDEV_ROM_TABLE_PID7 EQU 0xe00fffdc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID0 +CYDEV_ROM_TABLE_PID0 EQU 0xe00fffe0 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID1 +CYDEV_ROM_TABLE_PID1 EQU 0xe00fffe4 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID2 +CYDEV_ROM_TABLE_PID2 EQU 0xe00fffe8 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID3 +CYDEV_ROM_TABLE_PID3 EQU 0xe00fffec + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID0 +CYDEV_ROM_TABLE_CID0 EQU 0xe00ffff0 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID1 +CYDEV_ROM_TABLE_CID1 EQU 0xe00ffff4 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID2 +CYDEV_ROM_TABLE_CID2 EQU 0xe00ffff8 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID3 +CYDEV_ROM_TABLE_CID3 EQU 0xe00ffffc + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SIZE +CYDEV_FLS_SIZE EQU CYDEV_FLASH_SIZE + ENDIF + IF :LNOT::DEF:CYDEV_ECC_BASE +CYDEV_ECC_BASE EQU CYDEV_FLSECC_BASE + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE +CYDEV_FLS_SECTOR_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE +CYDEV_FLS_ROW_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE +CYDEV_ECC_SECTOR_SIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_ROW_SIZE +CYDEV_ECC_ROW_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_SECTOR_SIZE +CYDEV_EEPROM_SECTOR_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_ROW_SIZE +CYDEV_EEPROM_ROW_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PERIPH_BASE +CYDEV_PERIPH_BASE EQU CYDEV_CLKDIST_BASE + ENDIF + IF :LNOT::DEF:CYCLK_LD_DISABLE +CYCLK_LD_DISABLE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYCLK_LD_SYNC_EN +CYCLK_LD_SYNC_EN EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYCLK_LD_LOAD +CYCLK_LD_LOAD EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYCLK_PIPE +CYCLK_PIPE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYCLK_SSS +CYCLK_SSS EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYCLK_EARLY +CYCLK_EARLY EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYCLK_DUTY +CYCLK_DUTY EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYCLK_SYNC +CYCLK_SYNC EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_D +CYCLK_SRC_SEL_CLK_SYNC_D EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_SYNC_DIG +CYCLK_SRC_SEL_SYNC_DIG EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_IMO +CYCLK_SRC_SEL_IMO EQU 1 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_MHZ +CYCLK_SRC_SEL_XTAL_MHZ EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALM +CYCLK_SRC_SEL_XTALM EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_ILO +CYCLK_SRC_SEL_ILO EQU 3 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_PLL +CYCLK_SRC_SEL_PLL EQU 4 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_KHZ +CYCLK_SRC_SEL_XTAL_KHZ EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALK +CYCLK_SRC_SEL_XTALK EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_G +CYCLK_SRC_SEL_DSI_G EQU 6 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_D +CYCLK_SRC_SEL_DSI_D EQU 7 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_A +CYCLK_SRC_SEL_CLK_SYNC_A EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_A +CYCLK_SRC_SEL_DSI_A EQU 7 + ENDIF + END diff --git a/source/hic_hal/cypress/psoc5lp/armcc/cydevicerv_trm.inc b/source/hic_hal/cypress/psoc5lp/armcc/cydevicerv_trm.inc new file mode 100644 index 0000000000..56189078c9 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/armcc/cydevicerv_trm.inc @@ -0,0 +1,16045 @@ +; +; File Name: cydevicerv_trm.inc +; Description: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright (2019) Cypress Semiconductor Corporation +; or a subsidiary of Cypress Semiconductor Corporation. +; +; Licensed under the Apache License, Version 2.0 (the "License"); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +;------------------------------------------------------------------------------- + IF :LNOT::DEF:CYDEV_FLASH_BASE +CYDEV_FLASH_BASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_SIZE +CYDEV_FLASH_SIZE EQU 0x00040000 + ENDIF + IF :LNOT::DEF:CYREG_FLASH_DATA_MBASE +CYREG_FLASH_DATA_MBASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYREG_FLASH_DATA_MSIZE +CYREG_FLASH_DATA_MSIZE EQU 0x00040000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_BASE +CYDEV_SRAM_BASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_SIZE +CYDEV_SRAM_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE64K_MBASE +CYREG_SRAM_CODE64K_MBASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE64K_MSIZE +CYREG_SRAM_CODE64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE32K_MBASE +CYREG_SRAM_CODE32K_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE32K_MSIZE +CYREG_SRAM_CODE32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE16K_MBASE +CYREG_SRAM_CODE16K_MBASE EQU 0x1fffe000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE16K_MSIZE +CYREG_SRAM_CODE16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE_MBASE +CYREG_SRAM_CODE_MBASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE_MSIZE +CYREG_SRAM_CODE_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA_MBASE +CYREG_SRAM_DATA_MBASE EQU 0x20000000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA_MSIZE +CYREG_SRAM_DATA_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA16K_MBASE +CYREG_SRAM_DATA16K_MBASE EQU 0x20001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA16K_MSIZE +CYREG_SRAM_DATA16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA32K_MBASE +CYREG_SRAM_DATA32K_MBASE EQU 0x20002000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA32K_MSIZE +CYREG_SRAM_DATA32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA64K_MBASE +CYREG_SRAM_DATA64K_MBASE EQU 0x20004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA64K_MSIZE +CYREG_SRAM_DATA64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_BASE +CYDEV_DMA_BASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SIZE +CYDEV_DMA_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM64K_MBASE +CYREG_DMA_SRAM64K_MBASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM64K_MSIZE +CYREG_DMA_SRAM64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM32K_MBASE +CYREG_DMA_SRAM32K_MBASE EQU 0x2000c000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM32K_MSIZE +CYREG_DMA_SRAM32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM16K_MBASE +CYREG_DMA_SRAM16K_MBASE EQU 0x2000e000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM16K_MSIZE +CYREG_DMA_SRAM16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM_MBASE +CYREG_DMA_SRAM_MBASE EQU 0x2000f000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM_MSIZE +CYREG_DMA_SRAM_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BASE +CYDEV_CLKDIST_BASE EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_SIZE +CYDEV_CLKDIST_SIZE EQU 0x00000110 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_CR +CYREG_CLKDIST_CR EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_LD +CYREG_CLKDIST_LD EQU 0x40004001 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_WRK0 +CYREG_CLKDIST_WRK0 EQU 0x40004002 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_WRK1 +CYREG_CLKDIST_WRK1 EQU 0x40004003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_MSTR0 +CYREG_CLKDIST_MSTR0 EQU 0x40004004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_MSTR1 +CYREG_CLKDIST_MSTR1 EQU 0x40004005 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_BCFG0 +CYREG_CLKDIST_BCFG0 EQU 0x40004006 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_BCFG1 +CYREG_CLKDIST_BCFG1 EQU 0x40004007 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_BCFG2 +CYREG_CLKDIST_BCFG2 EQU 0x40004008 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_UCFG +CYREG_CLKDIST_UCFG EQU 0x40004009 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DLY0 +CYREG_CLKDIST_DLY0 EQU 0x4000400a + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DLY1 +CYREG_CLKDIST_DLY1 EQU 0x4000400b + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DMASK +CYREG_CLKDIST_DMASK EQU 0x40004010 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_AMASK +CYREG_CLKDIST_AMASK EQU 0x40004014 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_BASE +CYDEV_CLKDIST_DCFG0_BASE EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_SIZE +CYDEV_CLKDIST_DCFG0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG0 +CYREG_CLKDIST_DCFG0_CFG0 EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG1 +CYREG_CLKDIST_DCFG0_CFG1 EQU 0x40004081 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG2 +CYREG_CLKDIST_DCFG0_CFG2 EQU 0x40004082 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_BASE +CYDEV_CLKDIST_DCFG1_BASE EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_SIZE +CYDEV_CLKDIST_DCFG1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG0 +CYREG_CLKDIST_DCFG1_CFG0 EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG1 +CYREG_CLKDIST_DCFG1_CFG1 EQU 0x40004085 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG2 +CYREG_CLKDIST_DCFG1_CFG2 EQU 0x40004086 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_BASE +CYDEV_CLKDIST_DCFG2_BASE EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_SIZE +CYDEV_CLKDIST_DCFG2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG0 +CYREG_CLKDIST_DCFG2_CFG0 EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG1 +CYREG_CLKDIST_DCFG2_CFG1 EQU 0x40004089 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG2 +CYREG_CLKDIST_DCFG2_CFG2 EQU 0x4000408a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_BASE +CYDEV_CLKDIST_DCFG3_BASE EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_SIZE +CYDEV_CLKDIST_DCFG3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG0 +CYREG_CLKDIST_DCFG3_CFG0 EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG1 +CYREG_CLKDIST_DCFG3_CFG1 EQU 0x4000408d + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG2 +CYREG_CLKDIST_DCFG3_CFG2 EQU 0x4000408e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_BASE +CYDEV_CLKDIST_DCFG4_BASE EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_SIZE +CYDEV_CLKDIST_DCFG4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG0 +CYREG_CLKDIST_DCFG4_CFG0 EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG1 +CYREG_CLKDIST_DCFG4_CFG1 EQU 0x40004091 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG2 +CYREG_CLKDIST_DCFG4_CFG2 EQU 0x40004092 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_BASE +CYDEV_CLKDIST_DCFG5_BASE EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_SIZE +CYDEV_CLKDIST_DCFG5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG0 +CYREG_CLKDIST_DCFG5_CFG0 EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG1 +CYREG_CLKDIST_DCFG5_CFG1 EQU 0x40004095 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG2 +CYREG_CLKDIST_DCFG5_CFG2 EQU 0x40004096 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_BASE +CYDEV_CLKDIST_DCFG6_BASE EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_SIZE +CYDEV_CLKDIST_DCFG6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG0 +CYREG_CLKDIST_DCFG6_CFG0 EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG1 +CYREG_CLKDIST_DCFG6_CFG1 EQU 0x40004099 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG2 +CYREG_CLKDIST_DCFG6_CFG2 EQU 0x4000409a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_BASE +CYDEV_CLKDIST_DCFG7_BASE EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_SIZE +CYDEV_CLKDIST_DCFG7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG0 +CYREG_CLKDIST_DCFG7_CFG0 EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG1 +CYREG_CLKDIST_DCFG7_CFG1 EQU 0x4000409d + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG2 +CYREG_CLKDIST_DCFG7_CFG2 EQU 0x4000409e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_BASE +CYDEV_CLKDIST_ACFG0_BASE EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_SIZE +CYDEV_CLKDIST_ACFG0_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG0 +CYREG_CLKDIST_ACFG0_CFG0 EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG1 +CYREG_CLKDIST_ACFG0_CFG1 EQU 0x40004101 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG2 +CYREG_CLKDIST_ACFG0_CFG2 EQU 0x40004102 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG3 +CYREG_CLKDIST_ACFG0_CFG3 EQU 0x40004103 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_BASE +CYDEV_CLKDIST_ACFG1_BASE EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_SIZE +CYDEV_CLKDIST_ACFG1_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG0 +CYREG_CLKDIST_ACFG1_CFG0 EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG1 +CYREG_CLKDIST_ACFG1_CFG1 EQU 0x40004105 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG2 +CYREG_CLKDIST_ACFG1_CFG2 EQU 0x40004106 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG3 +CYREG_CLKDIST_ACFG1_CFG3 EQU 0x40004107 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_BASE +CYDEV_CLKDIST_ACFG2_BASE EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_SIZE +CYDEV_CLKDIST_ACFG2_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG0 +CYREG_CLKDIST_ACFG2_CFG0 EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG1 +CYREG_CLKDIST_ACFG2_CFG1 EQU 0x40004109 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG2 +CYREG_CLKDIST_ACFG2_CFG2 EQU 0x4000410a + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG3 +CYREG_CLKDIST_ACFG2_CFG3 EQU 0x4000410b + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_BASE +CYDEV_CLKDIST_ACFG3_BASE EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_SIZE +CYDEV_CLKDIST_ACFG3_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG0 +CYREG_CLKDIST_ACFG3_CFG0 EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG1 +CYREG_CLKDIST_ACFG3_CFG1 EQU 0x4000410d + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG2 +CYREG_CLKDIST_ACFG3_CFG2 EQU 0x4000410e + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG3 +CYREG_CLKDIST_ACFG3_CFG3 EQU 0x4000410f + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_BASE +CYDEV_FASTCLK_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_SIZE +CYDEV_FASTCLK_SIZE EQU 0x00000026 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_BASE +CYDEV_FASTCLK_IMO_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_SIZE +CYDEV_FASTCLK_IMO_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_IMO_CR +CYREG_FASTCLK_IMO_CR EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_BASE +CYDEV_FASTCLK_XMHZ_BASE EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_SIZE +CYDEV_FASTCLK_XMHZ_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CSR +CYREG_FASTCLK_XMHZ_CSR EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CFG0 +CYREG_FASTCLK_XMHZ_CFG0 EQU 0x40004212 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CFG1 +CYREG_FASTCLK_XMHZ_CFG1 EQU 0x40004213 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_BASE +CYDEV_FASTCLK_PLL_BASE EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SIZE +CYDEV_FASTCLK_PLL_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_CFG0 +CYREG_FASTCLK_PLL_CFG0 EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_CFG1 +CYREG_FASTCLK_PLL_CFG1 EQU 0x40004221 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_P +CYREG_FASTCLK_PLL_P EQU 0x40004222 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_Q +CYREG_FASTCLK_PLL_Q EQU 0x40004223 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_SR +CYREG_FASTCLK_PLL_SR EQU 0x40004225 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_BASE +CYDEV_SLOWCLK_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_SIZE +CYDEV_SLOWCLK_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_BASE +CYDEV_SLOWCLK_ILO_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_SIZE +CYDEV_SLOWCLK_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_ILO_CR0 +CYREG_SLOWCLK_ILO_CR0 EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_ILO_CR1 +CYREG_SLOWCLK_ILO_CR1 EQU 0x40004301 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_BASE +CYDEV_SLOWCLK_X32_BASE EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_SIZE +CYDEV_SLOWCLK_X32_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_X32_CR +CYREG_SLOWCLK_X32_CR EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_X32_CFG +CYREG_SLOWCLK_X32_CFG EQU 0x40004309 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_X32_TST +CYREG_SLOWCLK_X32_TST EQU 0x4000430a + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_BASE +CYDEV_BOOST_BASE EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SIZE +CYDEV_BOOST_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR0 +CYREG_BOOST_CR0 EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR1 +CYREG_BOOST_CR1 EQU 0x40004321 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR2 +CYREG_BOOST_CR2 EQU 0x40004322 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR3 +CYREG_BOOST_CR3 EQU 0x40004323 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_SR +CYREG_BOOST_SR EQU 0x40004324 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR4 +CYREG_BOOST_CR4 EQU 0x40004325 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_SR2 +CYREG_BOOST_SR2 EQU 0x40004326 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_BASE +CYDEV_PWRSYS_BASE EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_SIZE +CYDEV_PWRSYS_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_CR0 +CYREG_PWRSYS_CR0 EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_CR1 +CYREG_PWRSYS_CR1 EQU 0x40004331 + ENDIF + IF :LNOT::DEF:CYDEV_PM_BASE +CYDEV_PM_BASE EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYDEV_PM_SIZE +CYDEV_PM_SIZE EQU 0x00000057 + ENDIF + IF :LNOT::DEF:CYREG_PM_TW_CFG0 +CYREG_PM_TW_CFG0 EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYREG_PM_TW_CFG1 +CYREG_PM_TW_CFG1 EQU 0x40004381 + ENDIF + IF :LNOT::DEF:CYREG_PM_TW_CFG2 +CYREG_PM_TW_CFG2 EQU 0x40004382 + ENDIF + IF :LNOT::DEF:CYREG_PM_WDT_CFG +CYREG_PM_WDT_CFG EQU 0x40004383 + ENDIF + IF :LNOT::DEF:CYREG_PM_WDT_CR +CYREG_PM_WDT_CR EQU 0x40004384 + ENDIF + IF :LNOT::DEF:CYREG_PM_INT_SR +CYREG_PM_INT_SR EQU 0x40004390 + ENDIF + IF :LNOT::DEF:CYREG_PM_MODE_CFG0 +CYREG_PM_MODE_CFG0 EQU 0x40004391 + ENDIF + IF :LNOT::DEF:CYREG_PM_MODE_CFG1 +CYREG_PM_MODE_CFG1 EQU 0x40004392 + ENDIF + IF :LNOT::DEF:CYREG_PM_MODE_CSR +CYREG_PM_MODE_CSR EQU 0x40004393 + ENDIF + IF :LNOT::DEF:CYREG_PM_USB_CR0 +CYREG_PM_USB_CR0 EQU 0x40004394 + ENDIF + IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG0 +CYREG_PM_WAKEUP_CFG0 EQU 0x40004398 + ENDIF + IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG1 +CYREG_PM_WAKEUP_CFG1 EQU 0x40004399 + ENDIF + IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG2 +CYREG_PM_WAKEUP_CFG2 EQU 0x4000439a + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_BASE +CYDEV_PM_ACT_BASE EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_SIZE +CYDEV_PM_ACT_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG0 +CYREG_PM_ACT_CFG0 EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG1 +CYREG_PM_ACT_CFG1 EQU 0x400043a1 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG2 +CYREG_PM_ACT_CFG2 EQU 0x400043a2 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG3 +CYREG_PM_ACT_CFG3 EQU 0x400043a3 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG4 +CYREG_PM_ACT_CFG4 EQU 0x400043a4 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG5 +CYREG_PM_ACT_CFG5 EQU 0x400043a5 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG6 +CYREG_PM_ACT_CFG6 EQU 0x400043a6 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG7 +CYREG_PM_ACT_CFG7 EQU 0x400043a7 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG8 +CYREG_PM_ACT_CFG8 EQU 0x400043a8 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG9 +CYREG_PM_ACT_CFG9 EQU 0x400043a9 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG10 +CYREG_PM_ACT_CFG10 EQU 0x400043aa + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG11 +CYREG_PM_ACT_CFG11 EQU 0x400043ab + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG12 +CYREG_PM_ACT_CFG12 EQU 0x400043ac + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG13 +CYREG_PM_ACT_CFG13 EQU 0x400043ad + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_BASE +CYDEV_PM_STBY_BASE EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_SIZE +CYDEV_PM_STBY_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG0 +CYREG_PM_STBY_CFG0 EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG1 +CYREG_PM_STBY_CFG1 EQU 0x400043b1 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG2 +CYREG_PM_STBY_CFG2 EQU 0x400043b2 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG3 +CYREG_PM_STBY_CFG3 EQU 0x400043b3 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG4 +CYREG_PM_STBY_CFG4 EQU 0x400043b4 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG5 +CYREG_PM_STBY_CFG5 EQU 0x400043b5 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG6 +CYREG_PM_STBY_CFG6 EQU 0x400043b6 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG7 +CYREG_PM_STBY_CFG7 EQU 0x400043b7 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG8 +CYREG_PM_STBY_CFG8 EQU 0x400043b8 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG9 +CYREG_PM_STBY_CFG9 EQU 0x400043b9 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG10 +CYREG_PM_STBY_CFG10 EQU 0x400043ba + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG11 +CYREG_PM_STBY_CFG11 EQU 0x400043bb + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG12 +CYREG_PM_STBY_CFG12 EQU 0x400043bc + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG13 +CYREG_PM_STBY_CFG13 EQU 0x400043bd + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_BASE +CYDEV_PM_AVAIL_BASE EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SIZE +CYDEV_PM_AVAIL_SIZE EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR0 +CYREG_PM_AVAIL_CR0 EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR1 +CYREG_PM_AVAIL_CR1 EQU 0x400043c1 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR2 +CYREG_PM_AVAIL_CR2 EQU 0x400043c2 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR3 +CYREG_PM_AVAIL_CR3 EQU 0x400043c3 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR4 +CYREG_PM_AVAIL_CR4 EQU 0x400043c4 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR5 +CYREG_PM_AVAIL_CR5 EQU 0x400043c5 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR6 +CYREG_PM_AVAIL_CR6 EQU 0x400043c6 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR0 +CYREG_PM_AVAIL_SR0 EQU 0x400043d0 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR1 +CYREG_PM_AVAIL_SR1 EQU 0x400043d1 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR2 +CYREG_PM_AVAIL_SR2 EQU 0x400043d2 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR3 +CYREG_PM_AVAIL_SR3 EQU 0x400043d3 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR4 +CYREG_PM_AVAIL_SR4 EQU 0x400043d4 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR5 +CYREG_PM_AVAIL_SR5 EQU 0x400043d5 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR6 +CYREG_PM_AVAIL_SR6 EQU 0x400043d6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_BASE +CYDEV_PICU_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SIZE +CYDEV_PICU_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_BASE +CYDEV_PICU_INTTYPE_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_SIZE +CYDEV_PICU_INTTYPE_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_BASE +CYDEV_PICU_INTTYPE_PICU0_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_SIZE +CYDEV_PICU_INTTYPE_PICU0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE0 +CYREG_PICU0_INTTYPE0 EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE1 +CYREG_PICU0_INTTYPE1 EQU 0x40004501 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE2 +CYREG_PICU0_INTTYPE2 EQU 0x40004502 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE3 +CYREG_PICU0_INTTYPE3 EQU 0x40004503 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE4 +CYREG_PICU0_INTTYPE4 EQU 0x40004504 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE5 +CYREG_PICU0_INTTYPE5 EQU 0x40004505 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE6 +CYREG_PICU0_INTTYPE6 EQU 0x40004506 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE7 +CYREG_PICU0_INTTYPE7 EQU 0x40004507 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_BASE +CYDEV_PICU_INTTYPE_PICU1_BASE EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_SIZE +CYDEV_PICU_INTTYPE_PICU1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE0 +CYREG_PICU1_INTTYPE0 EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE1 +CYREG_PICU1_INTTYPE1 EQU 0x40004509 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE2 +CYREG_PICU1_INTTYPE2 EQU 0x4000450a + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE3 +CYREG_PICU1_INTTYPE3 EQU 0x4000450b + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE4 +CYREG_PICU1_INTTYPE4 EQU 0x4000450c + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE5 +CYREG_PICU1_INTTYPE5 EQU 0x4000450d + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE6 +CYREG_PICU1_INTTYPE6 EQU 0x4000450e + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE7 +CYREG_PICU1_INTTYPE7 EQU 0x4000450f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_BASE +CYDEV_PICU_INTTYPE_PICU2_BASE EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_SIZE +CYDEV_PICU_INTTYPE_PICU2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE0 +CYREG_PICU2_INTTYPE0 EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE1 +CYREG_PICU2_INTTYPE1 EQU 0x40004511 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE2 +CYREG_PICU2_INTTYPE2 EQU 0x40004512 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE3 +CYREG_PICU2_INTTYPE3 EQU 0x40004513 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE4 +CYREG_PICU2_INTTYPE4 EQU 0x40004514 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE5 +CYREG_PICU2_INTTYPE5 EQU 0x40004515 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE6 +CYREG_PICU2_INTTYPE6 EQU 0x40004516 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE7 +CYREG_PICU2_INTTYPE7 EQU 0x40004517 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_BASE +CYDEV_PICU_INTTYPE_PICU3_BASE EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_SIZE +CYDEV_PICU_INTTYPE_PICU3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE0 +CYREG_PICU3_INTTYPE0 EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE1 +CYREG_PICU3_INTTYPE1 EQU 0x40004519 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE2 +CYREG_PICU3_INTTYPE2 EQU 0x4000451a + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE3 +CYREG_PICU3_INTTYPE3 EQU 0x4000451b + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE4 +CYREG_PICU3_INTTYPE4 EQU 0x4000451c + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE5 +CYREG_PICU3_INTTYPE5 EQU 0x4000451d + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE6 +CYREG_PICU3_INTTYPE6 EQU 0x4000451e + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE7 +CYREG_PICU3_INTTYPE7 EQU 0x4000451f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_BASE +CYDEV_PICU_INTTYPE_PICU4_BASE EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_SIZE +CYDEV_PICU_INTTYPE_PICU4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE0 +CYREG_PICU4_INTTYPE0 EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE1 +CYREG_PICU4_INTTYPE1 EQU 0x40004521 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE2 +CYREG_PICU4_INTTYPE2 EQU 0x40004522 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE3 +CYREG_PICU4_INTTYPE3 EQU 0x40004523 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE4 +CYREG_PICU4_INTTYPE4 EQU 0x40004524 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE5 +CYREG_PICU4_INTTYPE5 EQU 0x40004525 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE6 +CYREG_PICU4_INTTYPE6 EQU 0x40004526 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE7 +CYREG_PICU4_INTTYPE7 EQU 0x40004527 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_BASE +CYDEV_PICU_INTTYPE_PICU5_BASE EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_SIZE +CYDEV_PICU_INTTYPE_PICU5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE0 +CYREG_PICU5_INTTYPE0 EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE1 +CYREG_PICU5_INTTYPE1 EQU 0x40004529 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE2 +CYREG_PICU5_INTTYPE2 EQU 0x4000452a + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE3 +CYREG_PICU5_INTTYPE3 EQU 0x4000452b + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE4 +CYREG_PICU5_INTTYPE4 EQU 0x4000452c + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE5 +CYREG_PICU5_INTTYPE5 EQU 0x4000452d + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE6 +CYREG_PICU5_INTTYPE6 EQU 0x4000452e + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE7 +CYREG_PICU5_INTTYPE7 EQU 0x4000452f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_BASE +CYDEV_PICU_INTTYPE_PICU6_BASE EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_SIZE +CYDEV_PICU_INTTYPE_PICU6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE0 +CYREG_PICU6_INTTYPE0 EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE1 +CYREG_PICU6_INTTYPE1 EQU 0x40004531 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE2 +CYREG_PICU6_INTTYPE2 EQU 0x40004532 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE3 +CYREG_PICU6_INTTYPE3 EQU 0x40004533 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE4 +CYREG_PICU6_INTTYPE4 EQU 0x40004534 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE5 +CYREG_PICU6_INTTYPE5 EQU 0x40004535 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE6 +CYREG_PICU6_INTTYPE6 EQU 0x40004536 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE7 +CYREG_PICU6_INTTYPE7 EQU 0x40004537 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_BASE +CYDEV_PICU_INTTYPE_PICU12_BASE EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_SIZE +CYDEV_PICU_INTTYPE_PICU12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE0 +CYREG_PICU12_INTTYPE0 EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE1 +CYREG_PICU12_INTTYPE1 EQU 0x40004561 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE2 +CYREG_PICU12_INTTYPE2 EQU 0x40004562 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE3 +CYREG_PICU12_INTTYPE3 EQU 0x40004563 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE4 +CYREG_PICU12_INTTYPE4 EQU 0x40004564 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE5 +CYREG_PICU12_INTTYPE5 EQU 0x40004565 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE6 +CYREG_PICU12_INTTYPE6 EQU 0x40004566 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE7 +CYREG_PICU12_INTTYPE7 EQU 0x40004567 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_BASE +CYDEV_PICU_INTTYPE_PICU15_BASE EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_SIZE +CYDEV_PICU_INTTYPE_PICU15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE0 +CYREG_PICU15_INTTYPE0 EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE1 +CYREG_PICU15_INTTYPE1 EQU 0x40004579 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE2 +CYREG_PICU15_INTTYPE2 EQU 0x4000457a + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE3 +CYREG_PICU15_INTTYPE3 EQU 0x4000457b + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE4 +CYREG_PICU15_INTTYPE4 EQU 0x4000457c + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE5 +CYREG_PICU15_INTTYPE5 EQU 0x4000457d + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE6 +CYREG_PICU15_INTTYPE6 EQU 0x4000457e + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE7 +CYREG_PICU15_INTTYPE7 EQU 0x4000457f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_BASE +CYDEV_PICU_STAT_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_SIZE +CYDEV_PICU_STAT_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_BASE +CYDEV_PICU_STAT_PICU0_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_SIZE +CYDEV_PICU_STAT_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTSTAT +CYREG_PICU0_INTSTAT EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_BASE +CYDEV_PICU_STAT_PICU1_BASE EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_SIZE +CYDEV_PICU_STAT_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTSTAT +CYREG_PICU1_INTSTAT EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_BASE +CYDEV_PICU_STAT_PICU2_BASE EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_SIZE +CYDEV_PICU_STAT_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTSTAT +CYREG_PICU2_INTSTAT EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_BASE +CYDEV_PICU_STAT_PICU3_BASE EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_SIZE +CYDEV_PICU_STAT_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTSTAT +CYREG_PICU3_INTSTAT EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_BASE +CYDEV_PICU_STAT_PICU4_BASE EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_SIZE +CYDEV_PICU_STAT_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTSTAT +CYREG_PICU4_INTSTAT EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_BASE +CYDEV_PICU_STAT_PICU5_BASE EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_SIZE +CYDEV_PICU_STAT_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTSTAT +CYREG_PICU5_INTSTAT EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_BASE +CYDEV_PICU_STAT_PICU6_BASE EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_SIZE +CYDEV_PICU_STAT_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTSTAT +CYREG_PICU6_INTSTAT EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_BASE +CYDEV_PICU_STAT_PICU12_BASE EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_SIZE +CYDEV_PICU_STAT_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTSTAT +CYREG_PICU12_INTSTAT EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_BASE +CYDEV_PICU_STAT_PICU15_BASE EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_SIZE +CYDEV_PICU_STAT_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTSTAT +CYREG_PICU15_INTSTAT EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_BASE +CYDEV_PICU_SNAP_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_SIZE +CYDEV_PICU_SNAP_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_BASE +CYDEV_PICU_SNAP_PICU0_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SIZE +CYDEV_PICU_SNAP_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_SNAP +CYREG_PICU0_SNAP EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_BASE +CYDEV_PICU_SNAP_PICU1_BASE EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SIZE +CYDEV_PICU_SNAP_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_SNAP +CYREG_PICU1_SNAP EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_BASE +CYDEV_PICU_SNAP_PICU2_BASE EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SIZE +CYDEV_PICU_SNAP_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_SNAP +CYREG_PICU2_SNAP EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_BASE +CYDEV_PICU_SNAP_PICU3_BASE EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SIZE +CYDEV_PICU_SNAP_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_SNAP +CYREG_PICU3_SNAP EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_BASE +CYDEV_PICU_SNAP_PICU4_BASE EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SIZE +CYDEV_PICU_SNAP_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_SNAP +CYREG_PICU4_SNAP EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_BASE +CYDEV_PICU_SNAP_PICU5_BASE EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SIZE +CYDEV_PICU_SNAP_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_SNAP +CYREG_PICU5_SNAP EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_BASE +CYDEV_PICU_SNAP_PICU6_BASE EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SIZE +CYDEV_PICU_SNAP_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_SNAP +CYREG_PICU6_SNAP EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_BASE +CYDEV_PICU_SNAP_PICU12_BASE EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SIZE +CYDEV_PICU_SNAP_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_SNAP +CYREG_PICU12_SNAP EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_BASE +CYDEV_PICU_SNAP_PICU_15_BASE EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SIZE +CYDEV_PICU_SNAP_PICU_15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU_15_SNAP_15 +CYREG_PICU_15_SNAP_15 EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_BASE +CYDEV_PICU_DISABLE_COR_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_SIZE +CYDEV_PICU_DISABLE_COR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_BASE +CYDEV_PICU_DISABLE_COR_PICU0_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_SIZE +CYDEV_PICU_DISABLE_COR_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_DISABLE_COR +CYREG_PICU0_DISABLE_COR EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_BASE +CYDEV_PICU_DISABLE_COR_PICU1_BASE EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_SIZE +CYDEV_PICU_DISABLE_COR_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_DISABLE_COR +CYREG_PICU1_DISABLE_COR EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_BASE +CYDEV_PICU_DISABLE_COR_PICU2_BASE EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_SIZE +CYDEV_PICU_DISABLE_COR_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_DISABLE_COR +CYREG_PICU2_DISABLE_COR EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_BASE +CYDEV_PICU_DISABLE_COR_PICU3_BASE EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_SIZE +CYDEV_PICU_DISABLE_COR_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_DISABLE_COR +CYREG_PICU3_DISABLE_COR EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_BASE +CYDEV_PICU_DISABLE_COR_PICU4_BASE EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_SIZE +CYDEV_PICU_DISABLE_COR_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_DISABLE_COR +CYREG_PICU4_DISABLE_COR EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_BASE +CYDEV_PICU_DISABLE_COR_PICU5_BASE EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_SIZE +CYDEV_PICU_DISABLE_COR_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_DISABLE_COR +CYREG_PICU5_DISABLE_COR EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_BASE +CYDEV_PICU_DISABLE_COR_PICU6_BASE EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_SIZE +CYDEV_PICU_DISABLE_COR_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_DISABLE_COR +CYREG_PICU6_DISABLE_COR EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_BASE +CYDEV_PICU_DISABLE_COR_PICU12_BASE EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_SIZE +CYDEV_PICU_DISABLE_COR_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_DISABLE_COR +CYREG_PICU12_DISABLE_COR EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_BASE +CYDEV_PICU_DISABLE_COR_PICU15_BASE EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_SIZE +CYDEV_PICU_DISABLE_COR_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_DISABLE_COR +CYREG_PICU15_DISABLE_COR EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_BASE +CYDEV_MFGCFG_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_SIZE +CYDEV_MFGCFG_SIZE EQU 0x000000ed + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_BASE +CYDEV_MFGCFG_ANAIF_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SIZE +CYDEV_MFGCFG_ANAIF_SIZE EQU 0x00000038 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_BASE +CYDEV_MFGCFG_ANAIF_DAC0_BASE EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_SIZE +CYDEV_MFGCFG_ANAIF_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_TR +CYREG_DAC0_TR EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_BASE +CYDEV_MFGCFG_ANAIF_DAC1_BASE EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_SIZE +CYDEV_MFGCFG_ANAIF_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_TR +CYREG_DAC1_TR EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_BASE +CYDEV_MFGCFG_ANAIF_DAC2_BASE EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_SIZE +CYDEV_MFGCFG_ANAIF_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_TR +CYREG_DAC2_TR EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_BASE +CYDEV_MFGCFG_ANAIF_DAC3_BASE EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_SIZE +CYDEV_MFGCFG_ANAIF_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_TR +CYREG_DAC3_TR EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_NPUMP_DSM_TR0 +CYREG_NPUMP_DSM_TR0 EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_NPUMP_SC_TR0 +CYREG_NPUMP_SC_TR0 EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_NPUMP_OPAMP_TR0 +CYREG_NPUMP_OPAMP_TR0 EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_BASE +CYDEV_MFGCFG_ANAIF_SAR0_BASE EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_SIZE +CYDEV_MFGCFG_ANAIF_SAR0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_TR0 +CYREG_SAR0_TR0 EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_BASE +CYDEV_MFGCFG_ANAIF_SAR1_BASE EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_SIZE +CYDEV_MFGCFG_ANAIF_SAR1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_TR0 +CYREG_SAR1_TR0 EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_BASE +CYDEV_MFGCFG_ANAIF_OPAMP0_BASE EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_TR0 +CYREG_OPAMP0_TR0 EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_TR1 +CYREG_OPAMP0_TR1 EQU 0x40004621 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_BASE +CYDEV_MFGCFG_ANAIF_OPAMP1_BASE EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_TR0 +CYREG_OPAMP1_TR0 EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_TR1 +CYREG_OPAMP1_TR1 EQU 0x40004623 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_BASE +CYDEV_MFGCFG_ANAIF_OPAMP2_BASE EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_TR0 +CYREG_OPAMP2_TR0 EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_TR1 +CYREG_OPAMP2_TR1 EQU 0x40004625 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_BASE +CYDEV_MFGCFG_ANAIF_OPAMP3_BASE EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_TR0 +CYREG_OPAMP3_TR0 EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_TR1 +CYREG_OPAMP3_TR1 EQU 0x40004627 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_BASE +CYDEV_MFGCFG_ANAIF_CMP0_BASE EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_SIZE +CYDEV_MFGCFG_ANAIF_CMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_TR0 +CYREG_CMP0_TR0 EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_TR1 +CYREG_CMP0_TR1 EQU 0x40004631 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_BASE +CYDEV_MFGCFG_ANAIF_CMP1_BASE EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_SIZE +CYDEV_MFGCFG_ANAIF_CMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_TR0 +CYREG_CMP1_TR0 EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_TR1 +CYREG_CMP1_TR1 EQU 0x40004633 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_BASE +CYDEV_MFGCFG_ANAIF_CMP2_BASE EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_SIZE +CYDEV_MFGCFG_ANAIF_CMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_TR0 +CYREG_CMP2_TR0 EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_TR1 +CYREG_CMP2_TR1 EQU 0x40004635 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_BASE +CYDEV_MFGCFG_ANAIF_CMP3_BASE EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_SIZE +CYDEV_MFGCFG_ANAIF_CMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_TR0 +CYREG_CMP3_TR0 EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_TR1 +CYREG_CMP3_TR1 EQU 0x40004637 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BASE +CYDEV_MFGCFG_PWRSYS_BASE EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SIZE +CYDEV_MFGCFG_PWRSYS_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_HIB_TR0 +CYREG_PWRSYS_HIB_TR0 EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_HIB_TR1 +CYREG_PWRSYS_HIB_TR1 EQU 0x40004681 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_I2C_TR +CYREG_PWRSYS_I2C_TR EQU 0x40004682 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_SLP_TR +CYREG_PWRSYS_SLP_TR EQU 0x40004683 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_BUZZ_TR +CYREG_PWRSYS_BUZZ_TR EQU 0x40004684 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR0 +CYREG_PWRSYS_WAKE_TR0 EQU 0x40004685 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR1 +CYREG_PWRSYS_WAKE_TR1 EQU 0x40004686 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_BREF_TR +CYREG_PWRSYS_BREF_TR EQU 0x40004687 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_BG_TR +CYREG_PWRSYS_BG_TR EQU 0x40004688 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR2 +CYREG_PWRSYS_WAKE_TR2 EQU 0x40004689 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR3 +CYREG_PWRSYS_WAKE_TR3 EQU 0x4000468a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_BASE +CYDEV_MFGCFG_ILO_BASE EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_SIZE +CYDEV_MFGCFG_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_ILO_TR0 +CYREG_ILO_TR0 EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYREG_ILO_TR1 +CYREG_ILO_TR1 EQU 0x40004691 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_BASE +CYDEV_MFGCFG_X32_BASE EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_SIZE +CYDEV_MFGCFG_X32_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_X32_TR +CYREG_X32_TR EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_BASE +CYDEV_MFGCFG_IMO_BASE EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_SIZE +CYDEV_MFGCFG_IMO_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_IMO_TR0 +CYREG_IMO_TR0 EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYREG_IMO_TR1 +CYREG_IMO_TR1 EQU 0x400046a1 + ENDIF + IF :LNOT::DEF:CYREG_IMO_GAIN +CYREG_IMO_GAIN EQU 0x400046a2 + ENDIF + IF :LNOT::DEF:CYREG_IMO_C36M +CYREG_IMO_C36M EQU 0x400046a3 + ENDIF + IF :LNOT::DEF:CYREG_IMO_TR2 +CYREG_IMO_TR2 EQU 0x400046a4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_BASE +CYDEV_MFGCFG_XMHZ_BASE EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_SIZE +CYDEV_MFGCFG_XMHZ_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_XMHZ_TR +CYREG_XMHZ_TR EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYREG_MFGCFG_DLY +CYREG_MFGCFG_DLY EQU 0x400046c0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_BASE +CYDEV_MFGCFG_MLOGIC_BASE EQU 0x400046e0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SIZE +CYDEV_MFGCFG_MLOGIC_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_DMPSTR +CYREG_MLOGIC_DMPSTR EQU 0x400046e2 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_BASE +CYDEV_MFGCFG_MLOGIC_SEG_BASE EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_SIZE +CYDEV_MFGCFG_MLOGIC_SEG_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_SEG_CR +CYREG_MLOGIC_SEG_CR EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_SEG_CFG0 +CYREG_MLOGIC_SEG_CFG0 EQU 0x400046e5 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_DEBUG +CYREG_MLOGIC_DEBUG EQU 0x400046e8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_CPU_SCR_CPU_SCR +CYREG_MLOGIC_CPU_SCR_CPU_SCR EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_REV_ID +CYREG_MLOGIC_REV_ID EQU 0x400046ec + ENDIF + IF :LNOT::DEF:CYDEV_RESET_BASE +CYDEV_RESET_BASE EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SIZE +CYDEV_RESET_SIZE EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR0 +CYREG_RESET_IPOR_CR0 EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR1 +CYREG_RESET_IPOR_CR1 EQU 0x400046f1 + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR2 +CYREG_RESET_IPOR_CR2 EQU 0x400046f2 + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR3 +CYREG_RESET_IPOR_CR3 EQU 0x400046f3 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR0 +CYREG_RESET_CR0 EQU 0x400046f4 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR1 +CYREG_RESET_CR1 EQU 0x400046f5 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR2 +CYREG_RESET_CR2 EQU 0x400046f6 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR3 +CYREG_RESET_CR3 EQU 0x400046f7 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR4 +CYREG_RESET_CR4 EQU 0x400046f8 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR5 +CYREG_RESET_CR5 EQU 0x400046f9 + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR0 +CYREG_RESET_SR0 EQU 0x400046fa + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR1 +CYREG_RESET_SR1 EQU 0x400046fb + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR2 +CYREG_RESET_SR2 EQU 0x400046fc + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR3 +CYREG_RESET_SR3 EQU 0x400046fd + ENDIF + IF :LNOT::DEF:CYREG_RESET_TR +CYREG_RESET_TR EQU 0x400046fe + ENDIF + IF :LNOT::DEF:CYDEV_SPC_BASE +CYDEV_SPC_BASE EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_SIZE +CYDEV_SPC_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_SPC_FM_EE_CR +CYREG_SPC_FM_EE_CR EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYREG_SPC_FM_EE_WAKE_CNT +CYREG_SPC_FM_EE_WAKE_CNT EQU 0x40004701 + ENDIF + IF :LNOT::DEF:CYREG_SPC_EE_SCR +CYREG_SPC_EE_SCR EQU 0x40004702 + ENDIF + IF :LNOT::DEF:CYREG_SPC_EE_ERR +CYREG_SPC_EE_ERR EQU 0x40004703 + ENDIF + IF :LNOT::DEF:CYREG_SPC_CPU_DATA +CYREG_SPC_CPU_DATA EQU 0x40004720 + ENDIF + IF :LNOT::DEF:CYREG_SPC_DMA_DATA +CYREG_SPC_DMA_DATA EQU 0x40004721 + ENDIF + IF :LNOT::DEF:CYREG_SPC_SR +CYREG_SPC_SR EQU 0x40004722 + ENDIF + IF :LNOT::DEF:CYREG_SPC_CR +CYREG_SPC_CR EQU 0x40004723 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_BASE +CYDEV_SPC_DMM_MAP_BASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SIZE +CYDEV_SPC_DMM_MAP_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_SPC_DMM_MAP_SRAM_MBASE +CYREG_SPC_DMM_MAP_SRAM_MBASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYREG_SPC_DMM_MAP_SRAM_MSIZE +CYREG_SPC_DMM_MAP_SRAM_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_BASE +CYDEV_CACHE_BASE EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_SIZE +CYDEV_CACHE_SIZE EQU 0x0000009c + ENDIF + IF :LNOT::DEF:CYREG_CACHE_CC_CTL +CYREG_CACHE_CC_CTL EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_ECC_CORR +CYREG_CACHE_ECC_CORR EQU 0x40004880 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_ECC_ERR +CYREG_CACHE_ECC_ERR EQU 0x40004888 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_FLASH_ERR +CYREG_CACHE_FLASH_ERR EQU 0x40004890 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_HITMISS +CYREG_CACHE_HITMISS EQU 0x40004898 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_BASE +CYDEV_I2C_BASE EQU 0x40004900 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_SIZE +CYDEV_I2C_SIZE EQU 0x000000e1 + ENDIF + IF :LNOT::DEF:CYREG_I2C_XCFG +CYREG_I2C_XCFG EQU 0x400049c8 + ENDIF + IF :LNOT::DEF:CYREG_I2C_ADR +CYREG_I2C_ADR EQU 0x400049ca + ENDIF + IF :LNOT::DEF:CYREG_I2C_CFG +CYREG_I2C_CFG EQU 0x400049d6 + ENDIF + IF :LNOT::DEF:CYREG_I2C_CSR +CYREG_I2C_CSR EQU 0x400049d7 + ENDIF + IF :LNOT::DEF:CYREG_I2C_D +CYREG_I2C_D EQU 0x400049d8 + ENDIF + IF :LNOT::DEF:CYREG_I2C_MCSR +CYREG_I2C_MCSR EQU 0x400049d9 + ENDIF + IF :LNOT::DEF:CYREG_I2C_CLK_DIV1 +CYREG_I2C_CLK_DIV1 EQU 0x400049db + ENDIF + IF :LNOT::DEF:CYREG_I2C_CLK_DIV2 +CYREG_I2C_CLK_DIV2 EQU 0x400049dc + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_CSR +CYREG_I2C_TMOUT_CSR EQU 0x400049dd + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_SR +CYREG_I2C_TMOUT_SR EQU 0x400049de + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_CFG0 +CYREG_I2C_TMOUT_CFG0 EQU 0x400049df + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_CFG1 +CYREG_I2C_TMOUT_CFG1 EQU 0x400049e0 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_BASE +CYDEV_DEC_BASE EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SIZE +CYDEV_DEC_SIZE EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYREG_DEC_CR +CYREG_DEC_CR EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYREG_DEC_SR +CYREG_DEC_SR EQU 0x40004e01 + ENDIF + IF :LNOT::DEF:CYREG_DEC_SHIFT1 +CYREG_DEC_SHIFT1 EQU 0x40004e02 + ENDIF + IF :LNOT::DEF:CYREG_DEC_SHIFT2 +CYREG_DEC_SHIFT2 EQU 0x40004e03 + ENDIF + IF :LNOT::DEF:CYREG_DEC_DR2 +CYREG_DEC_DR2 EQU 0x40004e04 + ENDIF + IF :LNOT::DEF:CYREG_DEC_DR2H +CYREG_DEC_DR2H EQU 0x40004e05 + ENDIF + IF :LNOT::DEF:CYREG_DEC_DR1 +CYREG_DEC_DR1 EQU 0x40004e06 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OCOR +CYREG_DEC_OCOR EQU 0x40004e08 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OCORM +CYREG_DEC_OCORM EQU 0x40004e09 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OCORH +CYREG_DEC_OCORH EQU 0x40004e0a + ENDIF + IF :LNOT::DEF:CYREG_DEC_GCOR +CYREG_DEC_GCOR EQU 0x40004e0c + ENDIF + IF :LNOT::DEF:CYREG_DEC_GCORH +CYREG_DEC_GCORH EQU 0x40004e0d + ENDIF + IF :LNOT::DEF:CYREG_DEC_GVAL +CYREG_DEC_GVAL EQU 0x40004e0e + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMP +CYREG_DEC_OUTSAMP EQU 0x40004e10 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMPM +CYREG_DEC_OUTSAMPM EQU 0x40004e11 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMPH +CYREG_DEC_OUTSAMPH EQU 0x40004e12 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMPS +CYREG_DEC_OUTSAMPS EQU 0x40004e13 + ENDIF + IF :LNOT::DEF:CYREG_DEC_COHER +CYREG_DEC_COHER EQU 0x40004e14 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_BASE +CYDEV_TMR0_BASE EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_SIZE +CYDEV_TMR0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CFG0 +CYREG_TMR0_CFG0 EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CFG1 +CYREG_TMR0_CFG1 EQU 0x40004f01 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CFG2 +CYREG_TMR0_CFG2 EQU 0x40004f02 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_SR0 +CYREG_TMR0_SR0 EQU 0x40004f03 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_PER0 +CYREG_TMR0_PER0 EQU 0x40004f04 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_PER1 +CYREG_TMR0_PER1 EQU 0x40004f05 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CNT_CMP0 +CYREG_TMR0_CNT_CMP0 EQU 0x40004f06 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CNT_CMP1 +CYREG_TMR0_CNT_CMP1 EQU 0x40004f07 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CAP0 +CYREG_TMR0_CAP0 EQU 0x40004f08 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CAP1 +CYREG_TMR0_CAP1 EQU 0x40004f09 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_RT0 +CYREG_TMR0_RT0 EQU 0x40004f0a + ENDIF + IF :LNOT::DEF:CYREG_TMR0_RT1 +CYREG_TMR0_RT1 EQU 0x40004f0b + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_BASE +CYDEV_TMR1_BASE EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_SIZE +CYDEV_TMR1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CFG0 +CYREG_TMR1_CFG0 EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CFG1 +CYREG_TMR1_CFG1 EQU 0x40004f0d + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CFG2 +CYREG_TMR1_CFG2 EQU 0x40004f0e + ENDIF + IF :LNOT::DEF:CYREG_TMR1_SR0 +CYREG_TMR1_SR0 EQU 0x40004f0f + ENDIF + IF :LNOT::DEF:CYREG_TMR1_PER0 +CYREG_TMR1_PER0 EQU 0x40004f10 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_PER1 +CYREG_TMR1_PER1 EQU 0x40004f11 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CNT_CMP0 +CYREG_TMR1_CNT_CMP0 EQU 0x40004f12 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CNT_CMP1 +CYREG_TMR1_CNT_CMP1 EQU 0x40004f13 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CAP0 +CYREG_TMR1_CAP0 EQU 0x40004f14 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CAP1 +CYREG_TMR1_CAP1 EQU 0x40004f15 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_RT0 +CYREG_TMR1_RT0 EQU 0x40004f16 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_RT1 +CYREG_TMR1_RT1 EQU 0x40004f17 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_BASE +CYDEV_TMR2_BASE EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_SIZE +CYDEV_TMR2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CFG0 +CYREG_TMR2_CFG0 EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CFG1 +CYREG_TMR2_CFG1 EQU 0x40004f19 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CFG2 +CYREG_TMR2_CFG2 EQU 0x40004f1a + ENDIF + IF :LNOT::DEF:CYREG_TMR2_SR0 +CYREG_TMR2_SR0 EQU 0x40004f1b + ENDIF + IF :LNOT::DEF:CYREG_TMR2_PER0 +CYREG_TMR2_PER0 EQU 0x40004f1c + ENDIF + IF :LNOT::DEF:CYREG_TMR2_PER1 +CYREG_TMR2_PER1 EQU 0x40004f1d + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CNT_CMP0 +CYREG_TMR2_CNT_CMP0 EQU 0x40004f1e + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CNT_CMP1 +CYREG_TMR2_CNT_CMP1 EQU 0x40004f1f + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CAP0 +CYREG_TMR2_CAP0 EQU 0x40004f20 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CAP1 +CYREG_TMR2_CAP1 EQU 0x40004f21 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_RT0 +CYREG_TMR2_RT0 EQU 0x40004f22 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_RT1 +CYREG_TMR2_RT1 EQU 0x40004f23 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_BASE +CYDEV_TMR3_BASE EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_SIZE +CYDEV_TMR3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CFG0 +CYREG_TMR3_CFG0 EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CFG1 +CYREG_TMR3_CFG1 EQU 0x40004f25 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CFG2 +CYREG_TMR3_CFG2 EQU 0x40004f26 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_SR0 +CYREG_TMR3_SR0 EQU 0x40004f27 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_PER0 +CYREG_TMR3_PER0 EQU 0x40004f28 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_PER1 +CYREG_TMR3_PER1 EQU 0x40004f29 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CNT_CMP0 +CYREG_TMR3_CNT_CMP0 EQU 0x40004f2a + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CNT_CMP1 +CYREG_TMR3_CNT_CMP1 EQU 0x40004f2b + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CAP0 +CYREG_TMR3_CAP0 EQU 0x40004f2c + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CAP1 +CYREG_TMR3_CAP1 EQU 0x40004f2d + ENDIF + IF :LNOT::DEF:CYREG_TMR3_RT0 +CYREG_TMR3_RT0 EQU 0x40004f2e + ENDIF + IF :LNOT::DEF:CYREG_TMR3_RT1 +CYREG_TMR3_RT1 EQU 0x40004f2f + ENDIF + IF :LNOT::DEF:CYDEV_IO_BASE +CYDEV_IO_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_SIZE +CYDEV_IO_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_BASE +CYDEV_IO_PC_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_SIZE +CYDEV_IO_PC_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_BASE +CYDEV_IO_PC_PRT0_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_SIZE +CYDEV_IO_PC_PRT0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC0 +CYREG_PRT0_PC0 EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC1 +CYREG_PRT0_PC1 EQU 0x40005001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC2 +CYREG_PRT0_PC2 EQU 0x40005002 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC3 +CYREG_PRT0_PC3 EQU 0x40005003 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC4 +CYREG_PRT0_PC4 EQU 0x40005004 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC5 +CYREG_PRT0_PC5 EQU 0x40005005 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC6 +CYREG_PRT0_PC6 EQU 0x40005006 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC7 +CYREG_PRT0_PC7 EQU 0x40005007 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_BASE +CYDEV_IO_PC_PRT1_BASE EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_SIZE +CYDEV_IO_PC_PRT1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC0 +CYREG_PRT1_PC0 EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC1 +CYREG_PRT1_PC1 EQU 0x40005009 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC2 +CYREG_PRT1_PC2 EQU 0x4000500a + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC3 +CYREG_PRT1_PC3 EQU 0x4000500b + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC4 +CYREG_PRT1_PC4 EQU 0x4000500c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC5 +CYREG_PRT1_PC5 EQU 0x4000500d + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC6 +CYREG_PRT1_PC6 EQU 0x4000500e + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC7 +CYREG_PRT1_PC7 EQU 0x4000500f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_BASE +CYDEV_IO_PC_PRT2_BASE EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_SIZE +CYDEV_IO_PC_PRT2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC0 +CYREG_PRT2_PC0 EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC1 +CYREG_PRT2_PC1 EQU 0x40005011 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC2 +CYREG_PRT2_PC2 EQU 0x40005012 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC3 +CYREG_PRT2_PC3 EQU 0x40005013 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC4 +CYREG_PRT2_PC4 EQU 0x40005014 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC5 +CYREG_PRT2_PC5 EQU 0x40005015 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC6 +CYREG_PRT2_PC6 EQU 0x40005016 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC7 +CYREG_PRT2_PC7 EQU 0x40005017 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_BASE +CYDEV_IO_PC_PRT3_BASE EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_SIZE +CYDEV_IO_PC_PRT3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC0 +CYREG_PRT3_PC0 EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC1 +CYREG_PRT3_PC1 EQU 0x40005019 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC2 +CYREG_PRT3_PC2 EQU 0x4000501a + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC3 +CYREG_PRT3_PC3 EQU 0x4000501b + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC4 +CYREG_PRT3_PC4 EQU 0x4000501c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC5 +CYREG_PRT3_PC5 EQU 0x4000501d + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC6 +CYREG_PRT3_PC6 EQU 0x4000501e + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC7 +CYREG_PRT3_PC7 EQU 0x4000501f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_BASE +CYDEV_IO_PC_PRT4_BASE EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_SIZE +CYDEV_IO_PC_PRT4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC0 +CYREG_PRT4_PC0 EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC1 +CYREG_PRT4_PC1 EQU 0x40005021 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC2 +CYREG_PRT4_PC2 EQU 0x40005022 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC3 +CYREG_PRT4_PC3 EQU 0x40005023 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC4 +CYREG_PRT4_PC4 EQU 0x40005024 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC5 +CYREG_PRT4_PC5 EQU 0x40005025 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC6 +CYREG_PRT4_PC6 EQU 0x40005026 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC7 +CYREG_PRT4_PC7 EQU 0x40005027 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_BASE +CYDEV_IO_PC_PRT5_BASE EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_SIZE +CYDEV_IO_PC_PRT5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC0 +CYREG_PRT5_PC0 EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC1 +CYREG_PRT5_PC1 EQU 0x40005029 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC2 +CYREG_PRT5_PC2 EQU 0x4000502a + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC3 +CYREG_PRT5_PC3 EQU 0x4000502b + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC4 +CYREG_PRT5_PC4 EQU 0x4000502c + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC5 +CYREG_PRT5_PC5 EQU 0x4000502d + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC6 +CYREG_PRT5_PC6 EQU 0x4000502e + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC7 +CYREG_PRT5_PC7 EQU 0x4000502f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_BASE +CYDEV_IO_PC_PRT6_BASE EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_SIZE +CYDEV_IO_PC_PRT6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC0 +CYREG_PRT6_PC0 EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC1 +CYREG_PRT6_PC1 EQU 0x40005031 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC2 +CYREG_PRT6_PC2 EQU 0x40005032 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC3 +CYREG_PRT6_PC3 EQU 0x40005033 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC4 +CYREG_PRT6_PC4 EQU 0x40005034 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC5 +CYREG_PRT6_PC5 EQU 0x40005035 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC6 +CYREG_PRT6_PC6 EQU 0x40005036 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC7 +CYREG_PRT6_PC7 EQU 0x40005037 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_BASE +CYDEV_IO_PC_PRT12_BASE EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_SIZE +CYDEV_IO_PC_PRT12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC0 +CYREG_PRT12_PC0 EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC1 +CYREG_PRT12_PC1 EQU 0x40005061 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC2 +CYREG_PRT12_PC2 EQU 0x40005062 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC3 +CYREG_PRT12_PC3 EQU 0x40005063 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC4 +CYREG_PRT12_PC4 EQU 0x40005064 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC5 +CYREG_PRT12_PC5 EQU 0x40005065 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC6 +CYREG_PRT12_PC6 EQU 0x40005066 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC7 +CYREG_PRT12_PC7 EQU 0x40005067 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_BASE +CYDEV_IO_PC_PRT15_BASE EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_SIZE +CYDEV_IO_PC_PRT15_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC0 +CYREG_IO_PC_PRT15_PC0 EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC1 +CYREG_IO_PC_PRT15_PC1 EQU 0x40005079 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC2 +CYREG_IO_PC_PRT15_PC2 EQU 0x4000507a + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC3 +CYREG_IO_PC_PRT15_PC3 EQU 0x4000507b + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC4 +CYREG_IO_PC_PRT15_PC4 EQU 0x4000507c + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC5 +CYREG_IO_PC_PRT15_PC5 EQU 0x4000507d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_BASE +CYDEV_IO_PC_PRT15_7_6_BASE EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_SIZE +CYDEV_IO_PC_PRT15_7_6_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_7_6_PC0 +CYREG_IO_PC_PRT15_7_6_PC0 EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_7_6_PC1 +CYREG_IO_PC_PRT15_7_6_PC1 EQU 0x4000507f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_BASE +CYDEV_IO_DR_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_SIZE +CYDEV_IO_DR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_BASE +CYDEV_IO_DR_PRT0_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_SIZE +CYDEV_IO_DR_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DR_ALIAS +CYREG_PRT0_DR_ALIAS EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_BASE +CYDEV_IO_DR_PRT1_BASE EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_SIZE +CYDEV_IO_DR_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DR_ALIAS +CYREG_PRT1_DR_ALIAS EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_BASE +CYDEV_IO_DR_PRT2_BASE EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_SIZE +CYDEV_IO_DR_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DR_ALIAS +CYREG_PRT2_DR_ALIAS EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_BASE +CYDEV_IO_DR_PRT3_BASE EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_SIZE +CYDEV_IO_DR_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DR_ALIAS +CYREG_PRT3_DR_ALIAS EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_BASE +CYDEV_IO_DR_PRT4_BASE EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_SIZE +CYDEV_IO_DR_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DR_ALIAS +CYREG_PRT4_DR_ALIAS EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_BASE +CYDEV_IO_DR_PRT5_BASE EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_SIZE +CYDEV_IO_DR_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DR_ALIAS +CYREG_PRT5_DR_ALIAS EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_BASE +CYDEV_IO_DR_PRT6_BASE EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_SIZE +CYDEV_IO_DR_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DR_ALIAS +CYREG_PRT6_DR_ALIAS EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_BASE +CYDEV_IO_DR_PRT12_BASE EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_SIZE +CYDEV_IO_DR_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DR_ALIAS +CYREG_PRT12_DR_ALIAS EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_BASE +CYDEV_IO_DR_PRT15_BASE EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_SIZE +CYDEV_IO_DR_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DR_15_ALIAS +CYREG_PRT15_DR_15_ALIAS EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_BASE +CYDEV_IO_PS_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_SIZE +CYDEV_IO_PS_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_BASE +CYDEV_IO_PS_PRT0_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_SIZE +CYDEV_IO_PS_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PS_ALIAS +CYREG_PRT0_PS_ALIAS EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_BASE +CYDEV_IO_PS_PRT1_BASE EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_SIZE +CYDEV_IO_PS_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PS_ALIAS +CYREG_PRT1_PS_ALIAS EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_BASE +CYDEV_IO_PS_PRT2_BASE EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_SIZE +CYDEV_IO_PS_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PS_ALIAS +CYREG_PRT2_PS_ALIAS EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_BASE +CYDEV_IO_PS_PRT3_BASE EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_SIZE +CYDEV_IO_PS_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PS_ALIAS +CYREG_PRT3_PS_ALIAS EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_BASE +CYDEV_IO_PS_PRT4_BASE EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_SIZE +CYDEV_IO_PS_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PS_ALIAS +CYREG_PRT4_PS_ALIAS EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_BASE +CYDEV_IO_PS_PRT5_BASE EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_SIZE +CYDEV_IO_PS_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PS_ALIAS +CYREG_PRT5_PS_ALIAS EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_BASE +CYDEV_IO_PS_PRT6_BASE EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_SIZE +CYDEV_IO_PS_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PS_ALIAS +CYREG_PRT6_PS_ALIAS EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_BASE +CYDEV_IO_PS_PRT12_BASE EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_SIZE +CYDEV_IO_PS_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PS_ALIAS +CYREG_PRT12_PS_ALIAS EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_BASE +CYDEV_IO_PS_PRT15_BASE EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_SIZE +CYDEV_IO_PS_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_PS15_ALIAS +CYREG_PRT15_PS15_ALIAS EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_BASE +CYDEV_IO_PRT_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_SIZE +CYDEV_IO_PRT_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BASE +CYDEV_IO_PRT_PRT0_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SIZE +CYDEV_IO_PRT_PRT0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DR +CYREG_PRT0_DR EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PS +CYREG_PRT0_PS EQU 0x40005101 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DM0 +CYREG_PRT0_DM0 EQU 0x40005102 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DM1 +CYREG_PRT0_DM1 EQU 0x40005103 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DM2 +CYREG_PRT0_DM2 EQU 0x40005104 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_SLW +CYREG_PRT0_SLW EQU 0x40005105 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_BYP +CYREG_PRT0_BYP EQU 0x40005106 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_BIE +CYREG_PRT0_BIE EQU 0x40005107 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_INP_DIS +CYREG_PRT0_INP_DIS EQU 0x40005108 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_CTL +CYREG_PRT0_CTL EQU 0x40005109 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PRT +CYREG_PRT0_PRT EQU 0x4000510a + ENDIF + IF :LNOT::DEF:CYREG_PRT0_BIT_MASK +CYREG_PRT0_BIT_MASK EQU 0x4000510b + ENDIF + IF :LNOT::DEF:CYREG_PRT0_AMUX +CYREG_PRT0_AMUX EQU 0x4000510c + ENDIF + IF :LNOT::DEF:CYREG_PRT0_AG +CYREG_PRT0_AG EQU 0x4000510d + ENDIF + IF :LNOT::DEF:CYREG_PRT0_LCD_COM_SEG +CYREG_PRT0_LCD_COM_SEG EQU 0x4000510e + ENDIF + IF :LNOT::DEF:CYREG_PRT0_LCD_EN +CYREG_PRT0_LCD_EN EQU 0x4000510f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BASE +CYDEV_IO_PRT_PRT1_BASE EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SIZE +CYDEV_IO_PRT_PRT1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DR +CYREG_PRT1_DR EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PS +CYREG_PRT1_PS EQU 0x40005111 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DM0 +CYREG_PRT1_DM0 EQU 0x40005112 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DM1 +CYREG_PRT1_DM1 EQU 0x40005113 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DM2 +CYREG_PRT1_DM2 EQU 0x40005114 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_SLW +CYREG_PRT1_SLW EQU 0x40005115 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_BYP +CYREG_PRT1_BYP EQU 0x40005116 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_BIE +CYREG_PRT1_BIE EQU 0x40005117 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_INP_DIS +CYREG_PRT1_INP_DIS EQU 0x40005118 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_CTL +CYREG_PRT1_CTL EQU 0x40005119 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PRT +CYREG_PRT1_PRT EQU 0x4000511a + ENDIF + IF :LNOT::DEF:CYREG_PRT1_BIT_MASK +CYREG_PRT1_BIT_MASK EQU 0x4000511b + ENDIF + IF :LNOT::DEF:CYREG_PRT1_AMUX +CYREG_PRT1_AMUX EQU 0x4000511c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_AG +CYREG_PRT1_AG EQU 0x4000511d + ENDIF + IF :LNOT::DEF:CYREG_PRT1_LCD_COM_SEG +CYREG_PRT1_LCD_COM_SEG EQU 0x4000511e + ENDIF + IF :LNOT::DEF:CYREG_PRT1_LCD_EN +CYREG_PRT1_LCD_EN EQU 0x4000511f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BASE +CYDEV_IO_PRT_PRT2_BASE EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SIZE +CYDEV_IO_PRT_PRT2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DR +CYREG_PRT2_DR EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PS +CYREG_PRT2_PS EQU 0x40005121 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DM0 +CYREG_PRT2_DM0 EQU 0x40005122 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DM1 +CYREG_PRT2_DM1 EQU 0x40005123 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DM2 +CYREG_PRT2_DM2 EQU 0x40005124 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_SLW +CYREG_PRT2_SLW EQU 0x40005125 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_BYP +CYREG_PRT2_BYP EQU 0x40005126 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_BIE +CYREG_PRT2_BIE EQU 0x40005127 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_INP_DIS +CYREG_PRT2_INP_DIS EQU 0x40005128 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_CTL +CYREG_PRT2_CTL EQU 0x40005129 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PRT +CYREG_PRT2_PRT EQU 0x4000512a + ENDIF + IF :LNOT::DEF:CYREG_PRT2_BIT_MASK +CYREG_PRT2_BIT_MASK EQU 0x4000512b + ENDIF + IF :LNOT::DEF:CYREG_PRT2_AMUX +CYREG_PRT2_AMUX EQU 0x4000512c + ENDIF + IF :LNOT::DEF:CYREG_PRT2_AG +CYREG_PRT2_AG EQU 0x4000512d + ENDIF + IF :LNOT::DEF:CYREG_PRT2_LCD_COM_SEG +CYREG_PRT2_LCD_COM_SEG EQU 0x4000512e + ENDIF + IF :LNOT::DEF:CYREG_PRT2_LCD_EN +CYREG_PRT2_LCD_EN EQU 0x4000512f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BASE +CYDEV_IO_PRT_PRT3_BASE EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SIZE +CYDEV_IO_PRT_PRT3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DR +CYREG_PRT3_DR EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PS +CYREG_PRT3_PS EQU 0x40005131 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DM0 +CYREG_PRT3_DM0 EQU 0x40005132 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DM1 +CYREG_PRT3_DM1 EQU 0x40005133 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DM2 +CYREG_PRT3_DM2 EQU 0x40005134 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_SLW +CYREG_PRT3_SLW EQU 0x40005135 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_BYP +CYREG_PRT3_BYP EQU 0x40005136 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_BIE +CYREG_PRT3_BIE EQU 0x40005137 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_INP_DIS +CYREG_PRT3_INP_DIS EQU 0x40005138 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_CTL +CYREG_PRT3_CTL EQU 0x40005139 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PRT +CYREG_PRT3_PRT EQU 0x4000513a + ENDIF + IF :LNOT::DEF:CYREG_PRT3_BIT_MASK +CYREG_PRT3_BIT_MASK EQU 0x4000513b + ENDIF + IF :LNOT::DEF:CYREG_PRT3_AMUX +CYREG_PRT3_AMUX EQU 0x4000513c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_AG +CYREG_PRT3_AG EQU 0x4000513d + ENDIF + IF :LNOT::DEF:CYREG_PRT3_LCD_COM_SEG +CYREG_PRT3_LCD_COM_SEG EQU 0x4000513e + ENDIF + IF :LNOT::DEF:CYREG_PRT3_LCD_EN +CYREG_PRT3_LCD_EN EQU 0x4000513f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BASE +CYDEV_IO_PRT_PRT4_BASE EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SIZE +CYDEV_IO_PRT_PRT4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DR +CYREG_PRT4_DR EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PS +CYREG_PRT4_PS EQU 0x40005141 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DM0 +CYREG_PRT4_DM0 EQU 0x40005142 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DM1 +CYREG_PRT4_DM1 EQU 0x40005143 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DM2 +CYREG_PRT4_DM2 EQU 0x40005144 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_SLW +CYREG_PRT4_SLW EQU 0x40005145 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_BYP +CYREG_PRT4_BYP EQU 0x40005146 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_BIE +CYREG_PRT4_BIE EQU 0x40005147 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_INP_DIS +CYREG_PRT4_INP_DIS EQU 0x40005148 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_CTL +CYREG_PRT4_CTL EQU 0x40005149 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PRT +CYREG_PRT4_PRT EQU 0x4000514a + ENDIF + IF :LNOT::DEF:CYREG_PRT4_BIT_MASK +CYREG_PRT4_BIT_MASK EQU 0x4000514b + ENDIF + IF :LNOT::DEF:CYREG_PRT4_AMUX +CYREG_PRT4_AMUX EQU 0x4000514c + ENDIF + IF :LNOT::DEF:CYREG_PRT4_AG +CYREG_PRT4_AG EQU 0x4000514d + ENDIF + IF :LNOT::DEF:CYREG_PRT4_LCD_COM_SEG +CYREG_PRT4_LCD_COM_SEG EQU 0x4000514e + ENDIF + IF :LNOT::DEF:CYREG_PRT4_LCD_EN +CYREG_PRT4_LCD_EN EQU 0x4000514f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BASE +CYDEV_IO_PRT_PRT5_BASE EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SIZE +CYDEV_IO_PRT_PRT5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DR +CYREG_PRT5_DR EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PS +CYREG_PRT5_PS EQU 0x40005151 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DM0 +CYREG_PRT5_DM0 EQU 0x40005152 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DM1 +CYREG_PRT5_DM1 EQU 0x40005153 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DM2 +CYREG_PRT5_DM2 EQU 0x40005154 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_SLW +CYREG_PRT5_SLW EQU 0x40005155 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_BYP +CYREG_PRT5_BYP EQU 0x40005156 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_BIE +CYREG_PRT5_BIE EQU 0x40005157 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_INP_DIS +CYREG_PRT5_INP_DIS EQU 0x40005158 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_CTL +CYREG_PRT5_CTL EQU 0x40005159 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PRT +CYREG_PRT5_PRT EQU 0x4000515a + ENDIF + IF :LNOT::DEF:CYREG_PRT5_BIT_MASK +CYREG_PRT5_BIT_MASK EQU 0x4000515b + ENDIF + IF :LNOT::DEF:CYREG_PRT5_AMUX +CYREG_PRT5_AMUX EQU 0x4000515c + ENDIF + IF :LNOT::DEF:CYREG_PRT5_AG +CYREG_PRT5_AG EQU 0x4000515d + ENDIF + IF :LNOT::DEF:CYREG_PRT5_LCD_COM_SEG +CYREG_PRT5_LCD_COM_SEG EQU 0x4000515e + ENDIF + IF :LNOT::DEF:CYREG_PRT5_LCD_EN +CYREG_PRT5_LCD_EN EQU 0x4000515f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BASE +CYDEV_IO_PRT_PRT6_BASE EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SIZE +CYDEV_IO_PRT_PRT6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DR +CYREG_PRT6_DR EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PS +CYREG_PRT6_PS EQU 0x40005161 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DM0 +CYREG_PRT6_DM0 EQU 0x40005162 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DM1 +CYREG_PRT6_DM1 EQU 0x40005163 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DM2 +CYREG_PRT6_DM2 EQU 0x40005164 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_SLW +CYREG_PRT6_SLW EQU 0x40005165 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_BYP +CYREG_PRT6_BYP EQU 0x40005166 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_BIE +CYREG_PRT6_BIE EQU 0x40005167 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_INP_DIS +CYREG_PRT6_INP_DIS EQU 0x40005168 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_CTL +CYREG_PRT6_CTL EQU 0x40005169 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PRT +CYREG_PRT6_PRT EQU 0x4000516a + ENDIF + IF :LNOT::DEF:CYREG_PRT6_BIT_MASK +CYREG_PRT6_BIT_MASK EQU 0x4000516b + ENDIF + IF :LNOT::DEF:CYREG_PRT6_AMUX +CYREG_PRT6_AMUX EQU 0x4000516c + ENDIF + IF :LNOT::DEF:CYREG_PRT6_AG +CYREG_PRT6_AG EQU 0x4000516d + ENDIF + IF :LNOT::DEF:CYREG_PRT6_LCD_COM_SEG +CYREG_PRT6_LCD_COM_SEG EQU 0x4000516e + ENDIF + IF :LNOT::DEF:CYREG_PRT6_LCD_EN +CYREG_PRT6_LCD_EN EQU 0x4000516f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BASE +CYDEV_IO_PRT_PRT12_BASE EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIZE +CYDEV_IO_PRT_PRT12_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DR +CYREG_PRT12_DR EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PS +CYREG_PRT12_PS EQU 0x400051c1 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DM0 +CYREG_PRT12_DM0 EQU 0x400051c2 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DM1 +CYREG_PRT12_DM1 EQU 0x400051c3 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DM2 +CYREG_PRT12_DM2 EQU 0x400051c4 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SLW +CYREG_PRT12_SLW EQU 0x400051c5 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_BYP +CYREG_PRT12_BYP EQU 0x400051c6 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_BIE +CYREG_PRT12_BIE EQU 0x400051c7 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_INP_DIS +CYREG_PRT12_INP_DIS EQU 0x400051c8 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_HYST_EN +CYREG_PRT12_SIO_HYST_EN EQU 0x400051c9 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PRT +CYREG_PRT12_PRT EQU 0x400051ca + ENDIF + IF :LNOT::DEF:CYREG_PRT12_BIT_MASK +CYREG_PRT12_BIT_MASK EQU 0x400051cb + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_REG_HIFREQ +CYREG_PRT12_SIO_REG_HIFREQ EQU 0x400051cc + ENDIF + IF :LNOT::DEF:CYREG_PRT12_AG +CYREG_PRT12_AG EQU 0x400051cd + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_CFG +CYREG_PRT12_SIO_CFG EQU 0x400051ce + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_DIFF +CYREG_PRT12_SIO_DIFF EQU 0x400051cf + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BASE +CYDEV_IO_PRT_PRT15_BASE EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SIZE +CYDEV_IO_PRT_PRT15_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DR +CYREG_PRT15_DR EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_PS +CYREG_PRT15_PS EQU 0x400051f1 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DM0 +CYREG_PRT15_DM0 EQU 0x400051f2 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DM1 +CYREG_PRT15_DM1 EQU 0x400051f3 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DM2 +CYREG_PRT15_DM2 EQU 0x400051f4 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_SLW +CYREG_PRT15_SLW EQU 0x400051f5 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_BYP +CYREG_PRT15_BYP EQU 0x400051f6 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_BIE +CYREG_PRT15_BIE EQU 0x400051f7 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_INP_DIS +CYREG_PRT15_INP_DIS EQU 0x400051f8 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_CTL +CYREG_PRT15_CTL EQU 0x400051f9 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_PRT +CYREG_PRT15_PRT EQU 0x400051fa + ENDIF + IF :LNOT::DEF:CYREG_PRT15_BIT_MASK +CYREG_PRT15_BIT_MASK EQU 0x400051fb + ENDIF + IF :LNOT::DEF:CYREG_PRT15_AMUX +CYREG_PRT15_AMUX EQU 0x400051fc + ENDIF + IF :LNOT::DEF:CYREG_PRT15_AG +CYREG_PRT15_AG EQU 0x400051fd + ENDIF + IF :LNOT::DEF:CYREG_PRT15_LCD_COM_SEG +CYREG_PRT15_LCD_COM_SEG EQU 0x400051fe + ENDIF + IF :LNOT::DEF:CYREG_PRT15_LCD_EN +CYREG_PRT15_LCD_EN EQU 0x400051ff + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_BASE +CYDEV_PRTDSI_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_SIZE +CYDEV_PRTDSI_SIZE EQU 0x0000007f + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_BASE +CYDEV_PRTDSI_PRT0_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SIZE +CYDEV_PRTDSI_PRT0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OUT_SEL0 +CYREG_PRT0_OUT_SEL0 EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OUT_SEL1 +CYREG_PRT0_OUT_SEL1 EQU 0x40005201 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OE_SEL0 +CYREG_PRT0_OE_SEL0 EQU 0x40005202 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OE_SEL1 +CYREG_PRT0_OE_SEL1 EQU 0x40005203 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DBL_SYNC_IN +CYREG_PRT0_DBL_SYNC_IN EQU 0x40005204 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_SYNC_OUT +CYREG_PRT0_SYNC_OUT EQU 0x40005205 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_CAPS_SEL +CYREG_PRT0_CAPS_SEL EQU 0x40005206 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_BASE +CYDEV_PRTDSI_PRT1_BASE EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SIZE +CYDEV_PRTDSI_PRT1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OUT_SEL0 +CYREG_PRT1_OUT_SEL0 EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OUT_SEL1 +CYREG_PRT1_OUT_SEL1 EQU 0x40005209 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OE_SEL0 +CYREG_PRT1_OE_SEL0 EQU 0x4000520a + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OE_SEL1 +CYREG_PRT1_OE_SEL1 EQU 0x4000520b + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DBL_SYNC_IN +CYREG_PRT1_DBL_SYNC_IN EQU 0x4000520c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_SYNC_OUT +CYREG_PRT1_SYNC_OUT EQU 0x4000520d + ENDIF + IF :LNOT::DEF:CYREG_PRT1_CAPS_SEL +CYREG_PRT1_CAPS_SEL EQU 0x4000520e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_BASE +CYDEV_PRTDSI_PRT2_BASE EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SIZE +CYDEV_PRTDSI_PRT2_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OUT_SEL0 +CYREG_PRT2_OUT_SEL0 EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OUT_SEL1 +CYREG_PRT2_OUT_SEL1 EQU 0x40005211 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OE_SEL0 +CYREG_PRT2_OE_SEL0 EQU 0x40005212 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OE_SEL1 +CYREG_PRT2_OE_SEL1 EQU 0x40005213 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DBL_SYNC_IN +CYREG_PRT2_DBL_SYNC_IN EQU 0x40005214 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_SYNC_OUT +CYREG_PRT2_SYNC_OUT EQU 0x40005215 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_CAPS_SEL +CYREG_PRT2_CAPS_SEL EQU 0x40005216 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_BASE +CYDEV_PRTDSI_PRT3_BASE EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SIZE +CYDEV_PRTDSI_PRT3_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OUT_SEL0 +CYREG_PRT3_OUT_SEL0 EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OUT_SEL1 +CYREG_PRT3_OUT_SEL1 EQU 0x40005219 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OE_SEL0 +CYREG_PRT3_OE_SEL0 EQU 0x4000521a + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OE_SEL1 +CYREG_PRT3_OE_SEL1 EQU 0x4000521b + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DBL_SYNC_IN +CYREG_PRT3_DBL_SYNC_IN EQU 0x4000521c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_SYNC_OUT +CYREG_PRT3_SYNC_OUT EQU 0x4000521d + ENDIF + IF :LNOT::DEF:CYREG_PRT3_CAPS_SEL +CYREG_PRT3_CAPS_SEL EQU 0x4000521e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_BASE +CYDEV_PRTDSI_PRT4_BASE EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SIZE +CYDEV_PRTDSI_PRT4_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OUT_SEL0 +CYREG_PRT4_OUT_SEL0 EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OUT_SEL1 +CYREG_PRT4_OUT_SEL1 EQU 0x40005221 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OE_SEL0 +CYREG_PRT4_OE_SEL0 EQU 0x40005222 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OE_SEL1 +CYREG_PRT4_OE_SEL1 EQU 0x40005223 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DBL_SYNC_IN +CYREG_PRT4_DBL_SYNC_IN EQU 0x40005224 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_SYNC_OUT +CYREG_PRT4_SYNC_OUT EQU 0x40005225 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_CAPS_SEL +CYREG_PRT4_CAPS_SEL EQU 0x40005226 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_BASE +CYDEV_PRTDSI_PRT5_BASE EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SIZE +CYDEV_PRTDSI_PRT5_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OUT_SEL0 +CYREG_PRT5_OUT_SEL0 EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OUT_SEL1 +CYREG_PRT5_OUT_SEL1 EQU 0x40005229 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OE_SEL0 +CYREG_PRT5_OE_SEL0 EQU 0x4000522a + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OE_SEL1 +CYREG_PRT5_OE_SEL1 EQU 0x4000522b + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DBL_SYNC_IN +CYREG_PRT5_DBL_SYNC_IN EQU 0x4000522c + ENDIF + IF :LNOT::DEF:CYREG_PRT5_SYNC_OUT +CYREG_PRT5_SYNC_OUT EQU 0x4000522d + ENDIF + IF :LNOT::DEF:CYREG_PRT5_CAPS_SEL +CYREG_PRT5_CAPS_SEL EQU 0x4000522e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_BASE +CYDEV_PRTDSI_PRT6_BASE EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SIZE +CYDEV_PRTDSI_PRT6_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OUT_SEL0 +CYREG_PRT6_OUT_SEL0 EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OUT_SEL1 +CYREG_PRT6_OUT_SEL1 EQU 0x40005231 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OE_SEL0 +CYREG_PRT6_OE_SEL0 EQU 0x40005232 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OE_SEL1 +CYREG_PRT6_OE_SEL1 EQU 0x40005233 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DBL_SYNC_IN +CYREG_PRT6_DBL_SYNC_IN EQU 0x40005234 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_SYNC_OUT +CYREG_PRT6_SYNC_OUT EQU 0x40005235 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_CAPS_SEL +CYREG_PRT6_CAPS_SEL EQU 0x40005236 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_BASE +CYDEV_PRTDSI_PRT12_BASE EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SIZE +CYDEV_PRTDSI_PRT12_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OUT_SEL0 +CYREG_PRT12_OUT_SEL0 EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OUT_SEL1 +CYREG_PRT12_OUT_SEL1 EQU 0x40005261 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OE_SEL0 +CYREG_PRT12_OE_SEL0 EQU 0x40005262 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OE_SEL1 +CYREG_PRT12_OE_SEL1 EQU 0x40005263 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DBL_SYNC_IN +CYREG_PRT12_DBL_SYNC_IN EQU 0x40005264 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SYNC_OUT +CYREG_PRT12_SYNC_OUT EQU 0x40005265 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_BASE +CYDEV_PRTDSI_PRT15_BASE EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SIZE +CYDEV_PRTDSI_PRT15_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OUT_SEL0 +CYREG_PRT15_OUT_SEL0 EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OUT_SEL1 +CYREG_PRT15_OUT_SEL1 EQU 0x40005279 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OE_SEL0 +CYREG_PRT15_OE_SEL0 EQU 0x4000527a + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OE_SEL1 +CYREG_PRT15_OE_SEL1 EQU 0x4000527b + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DBL_SYNC_IN +CYREG_PRT15_DBL_SYNC_IN EQU 0x4000527c + ENDIF + IF :LNOT::DEF:CYREG_PRT15_SYNC_OUT +CYREG_PRT15_SYNC_OUT EQU 0x4000527d + ENDIF + IF :LNOT::DEF:CYREG_PRT15_CAPS_SEL +CYREG_PRT15_CAPS_SEL EQU 0x4000527e + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_BASE +CYDEV_EMIF_BASE EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_SIZE +CYDEV_EMIF_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_NO_UDB +CYREG_EMIF_NO_UDB EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_RP_WAIT_STATES +CYREG_EMIF_RP_WAIT_STATES EQU 0x40005401 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_MEM_DWN +CYREG_EMIF_MEM_DWN EQU 0x40005402 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_MEMCLK_DIV +CYREG_EMIF_MEMCLK_DIV EQU 0x40005403 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_CLOCK_EN +CYREG_EMIF_CLOCK_EN EQU 0x40005404 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_EM_TYPE +CYREG_EMIF_EM_TYPE EQU 0x40005405 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_WP_WAIT_STATES +CYREG_EMIF_WP_WAIT_STATES EQU 0x40005406 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_BASE +CYDEV_ANAIF_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_SIZE +CYDEV_ANAIF_SIZE EQU 0x000003a9 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BASE +CYDEV_ANAIF_CFG_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SIZE +CYDEV_ANAIF_CFG_SIZE EQU 0x0000010f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_BASE +CYDEV_ANAIF_CFG_SC0_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_SIZE +CYDEV_ANAIF_CFG_SC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC0_CR0 +CYREG_SC0_CR0 EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYREG_SC0_CR1 +CYREG_SC0_CR1 EQU 0x40005801 + ENDIF + IF :LNOT::DEF:CYREG_SC0_CR2 +CYREG_SC0_CR2 EQU 0x40005802 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_BASE +CYDEV_ANAIF_CFG_SC1_BASE EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_SIZE +CYDEV_ANAIF_CFG_SC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC1_CR0 +CYREG_SC1_CR0 EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYREG_SC1_CR1 +CYREG_SC1_CR1 EQU 0x40005805 + ENDIF + IF :LNOT::DEF:CYREG_SC1_CR2 +CYREG_SC1_CR2 EQU 0x40005806 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_BASE +CYDEV_ANAIF_CFG_SC2_BASE EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_SIZE +CYDEV_ANAIF_CFG_SC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC2_CR0 +CYREG_SC2_CR0 EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYREG_SC2_CR1 +CYREG_SC2_CR1 EQU 0x40005809 + ENDIF + IF :LNOT::DEF:CYREG_SC2_CR2 +CYREG_SC2_CR2 EQU 0x4000580a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_BASE +CYDEV_ANAIF_CFG_SC3_BASE EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_SIZE +CYDEV_ANAIF_CFG_SC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC3_CR0 +CYREG_SC3_CR0 EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYREG_SC3_CR1 +CYREG_SC3_CR1 EQU 0x4000580d + ENDIF + IF :LNOT::DEF:CYREG_SC3_CR2 +CYREG_SC3_CR2 EQU 0x4000580e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_BASE +CYDEV_ANAIF_CFG_DAC0_BASE EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_SIZE +CYDEV_ANAIF_CFG_DAC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_CR0 +CYREG_DAC0_CR0 EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_CR1 +CYREG_DAC0_CR1 EQU 0x40005821 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_TST +CYREG_DAC0_TST EQU 0x40005822 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_BASE +CYDEV_ANAIF_CFG_DAC1_BASE EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_SIZE +CYDEV_ANAIF_CFG_DAC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_CR0 +CYREG_DAC1_CR0 EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_CR1 +CYREG_DAC1_CR1 EQU 0x40005825 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_TST +CYREG_DAC1_TST EQU 0x40005826 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_BASE +CYDEV_ANAIF_CFG_DAC2_BASE EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_SIZE +CYDEV_ANAIF_CFG_DAC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_CR0 +CYREG_DAC2_CR0 EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_CR1 +CYREG_DAC2_CR1 EQU 0x40005829 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_TST +CYREG_DAC2_TST EQU 0x4000582a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_BASE +CYDEV_ANAIF_CFG_DAC3_BASE EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_SIZE +CYDEV_ANAIF_CFG_DAC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_CR0 +CYREG_DAC3_CR0 EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYREG_DAC3_CR1 +CYREG_DAC3_CR1 EQU 0x4000582d + ENDIF + IF :LNOT::DEF:CYREG_DAC3_TST +CYREG_DAC3_TST EQU 0x4000582e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_BASE +CYDEV_ANAIF_CFG_CMP0_BASE EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_SIZE +CYDEV_ANAIF_CFG_CMP0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_CR +CYREG_CMP0_CR EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_BASE +CYDEV_ANAIF_CFG_CMP1_BASE EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_SIZE +CYDEV_ANAIF_CFG_CMP1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_CR +CYREG_CMP1_CR EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_BASE +CYDEV_ANAIF_CFG_CMP2_BASE EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_SIZE +CYDEV_ANAIF_CFG_CMP2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_CR +CYREG_CMP2_CR EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_BASE +CYDEV_ANAIF_CFG_CMP3_BASE EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_SIZE +CYDEV_ANAIF_CFG_CMP3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_CR +CYREG_CMP3_CR EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_BASE +CYDEV_ANAIF_CFG_LUT0_BASE EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_SIZE +CYDEV_ANAIF_CFG_LUT0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT0_CR +CYREG_LUT0_CR EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYREG_LUT0_MX +CYREG_LUT0_MX EQU 0x40005849 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_BASE +CYDEV_ANAIF_CFG_LUT1_BASE EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_SIZE +CYDEV_ANAIF_CFG_LUT1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT1_CR +CYREG_LUT1_CR EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYREG_LUT1_MX +CYREG_LUT1_MX EQU 0x4000584b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_BASE +CYDEV_ANAIF_CFG_LUT2_BASE EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_SIZE +CYDEV_ANAIF_CFG_LUT2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT2_CR +CYREG_LUT2_CR EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYREG_LUT2_MX +CYREG_LUT2_MX EQU 0x4000584d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_BASE +CYDEV_ANAIF_CFG_LUT3_BASE EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_SIZE +CYDEV_ANAIF_CFG_LUT3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT3_CR +CYREG_LUT3_CR EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYREG_LUT3_MX +CYREG_LUT3_MX EQU 0x4000584f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_BASE +CYDEV_ANAIF_CFG_OPAMP0_BASE EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_SIZE +CYDEV_ANAIF_CFG_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_CR +CYREG_OPAMP0_CR EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_RSVD +CYREG_OPAMP0_RSVD EQU 0x40005859 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_BASE +CYDEV_ANAIF_CFG_OPAMP1_BASE EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_SIZE +CYDEV_ANAIF_CFG_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_CR +CYREG_OPAMP1_CR EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_RSVD +CYREG_OPAMP1_RSVD EQU 0x4000585b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_BASE +CYDEV_ANAIF_CFG_OPAMP2_BASE EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_SIZE +CYDEV_ANAIF_CFG_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_CR +CYREG_OPAMP2_CR EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_RSVD +CYREG_OPAMP2_RSVD EQU 0x4000585d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_BASE +CYDEV_ANAIF_CFG_OPAMP3_BASE EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_SIZE +CYDEV_ANAIF_CFG_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_CR +CYREG_OPAMP3_CR EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_RSVD +CYREG_OPAMP3_RSVD EQU 0x4000585f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_BASE +CYDEV_ANAIF_CFG_LCDDAC_BASE EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_SIZE +CYDEV_ANAIF_CFG_LCDDAC_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_CR0 +CYREG_LCDDAC_CR0 EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_CR1 +CYREG_LCDDAC_CR1 EQU 0x40005869 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_BASE +CYDEV_ANAIF_CFG_LCDDRV_BASE EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_SIZE +CYDEV_ANAIF_CFG_LCDDRV_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LCDDRV_CR +CYREG_LCDDRV_CR EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_BASE +CYDEV_ANAIF_CFG_LCDTMR_BASE EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_SIZE +CYDEV_ANAIF_CFG_LCDTMR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LCDTMR_CFG +CYREG_LCDTMR_CFG EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_BASE +CYDEV_ANAIF_CFG_BG_BASE EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_SIZE +CYDEV_ANAIF_CFG_BG_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_BG_CR0 +CYREG_BG_CR0 EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYREG_BG_RSVD +CYREG_BG_RSVD EQU 0x4000586d + ENDIF + IF :LNOT::DEF:CYREG_BG_DFT0 +CYREG_BG_DFT0 EQU 0x4000586e + ENDIF + IF :LNOT::DEF:CYREG_BG_DFT1 +CYREG_BG_DFT1 EQU 0x4000586f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_BASE +CYDEV_ANAIF_CFG_CAPSL_BASE EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_SIZE +CYDEV_ANAIF_CFG_CAPSL_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CAPSL_CFG0 +CYREG_CAPSL_CFG0 EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYREG_CAPSL_CFG1 +CYREG_CAPSL_CFG1 EQU 0x40005871 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_BASE +CYDEV_ANAIF_CFG_CAPSR_BASE EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_SIZE +CYDEV_ANAIF_CFG_CAPSR_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CAPSR_CFG0 +CYREG_CAPSR_CFG0 EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYREG_CAPSR_CFG1 +CYREG_CAPSR_CFG1 EQU 0x40005873 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_BASE +CYDEV_ANAIF_CFG_PUMP_BASE EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_SIZE +CYDEV_ANAIF_CFG_PUMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_PUMP_CR0 +CYREG_PUMP_CR0 EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYREG_PUMP_CR1 +CYREG_PUMP_CR1 EQU 0x40005877 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_BASE +CYDEV_ANAIF_CFG_LPF0_BASE EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_SIZE +CYDEV_ANAIF_CFG_LPF0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LPF0_CR0 +CYREG_LPF0_CR0 EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYREG_LPF0_RSVD +CYREG_LPF0_RSVD EQU 0x40005879 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_BASE +CYDEV_ANAIF_CFG_LPF1_BASE EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_SIZE +CYDEV_ANAIF_CFG_LPF1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LPF1_CR0 +CYREG_LPF1_CR0 EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYREG_LPF1_RSVD +CYREG_LPF1_RSVD EQU 0x4000587b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_BASE +CYDEV_ANAIF_CFG_MISC_BASE EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_SIZE +CYDEV_ANAIF_CFG_MISC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_ANAIF_CFG_MISC_CR0 +CYREG_ANAIF_CFG_MISC_CR0 EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BASE +CYDEV_ANAIF_CFG_DSM0_BASE EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_SIZE +CYDEV_ANAIF_CFG_DSM0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR0 +CYREG_DSM0_CR0 EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR1 +CYREG_DSM0_CR1 EQU 0x40005881 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR2 +CYREG_DSM0_CR2 EQU 0x40005882 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR3 +CYREG_DSM0_CR3 EQU 0x40005883 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR4 +CYREG_DSM0_CR4 EQU 0x40005884 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR5 +CYREG_DSM0_CR5 EQU 0x40005885 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR6 +CYREG_DSM0_CR6 EQU 0x40005886 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR7 +CYREG_DSM0_CR7 EQU 0x40005887 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR8 +CYREG_DSM0_CR8 EQU 0x40005888 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR9 +CYREG_DSM0_CR9 EQU 0x40005889 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR10 +CYREG_DSM0_CR10 EQU 0x4000588a + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR11 +CYREG_DSM0_CR11 EQU 0x4000588b + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR12 +CYREG_DSM0_CR12 EQU 0x4000588c + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR13 +CYREG_DSM0_CR13 EQU 0x4000588d + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR14 +CYREG_DSM0_CR14 EQU 0x4000588e + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR15 +CYREG_DSM0_CR15 EQU 0x4000588f + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR16 +CYREG_DSM0_CR16 EQU 0x40005890 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR17 +CYREG_DSM0_CR17 EQU 0x40005891 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF0 +CYREG_DSM0_REF0 EQU 0x40005892 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF1 +CYREG_DSM0_REF1 EQU 0x40005893 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF2 +CYREG_DSM0_REF2 EQU 0x40005894 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF3 +CYREG_DSM0_REF3 EQU 0x40005895 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_DEM0 +CYREG_DSM0_DEM0 EQU 0x40005896 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_DEM1 +CYREG_DSM0_DEM1 EQU 0x40005897 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_TST0 +CYREG_DSM0_TST0 EQU 0x40005898 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_TST1 +CYREG_DSM0_TST1 EQU 0x40005899 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF0 +CYREG_DSM0_BUF0 EQU 0x4000589a + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF1 +CYREG_DSM0_BUF1 EQU 0x4000589b + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF2 +CYREG_DSM0_BUF2 EQU 0x4000589c + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF3 +CYREG_DSM0_BUF3 EQU 0x4000589d + ENDIF + IF :LNOT::DEF:CYREG_DSM0_MISC +CYREG_DSM0_MISC EQU 0x4000589e + ENDIF + IF :LNOT::DEF:CYREG_DSM0_RSVD1 +CYREG_DSM0_RSVD1 EQU 0x4000589f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_BASE +CYDEV_ANAIF_CFG_SAR0_BASE EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_SIZE +CYDEV_ANAIF_CFG_SAR0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR0 +CYREG_SAR0_CSR0 EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR1 +CYREG_SAR0_CSR1 EQU 0x40005901 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR2 +CYREG_SAR0_CSR2 EQU 0x40005902 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR3 +CYREG_SAR0_CSR3 EQU 0x40005903 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR4 +CYREG_SAR0_CSR4 EQU 0x40005904 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR5 +CYREG_SAR0_CSR5 EQU 0x40005905 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR6 +CYREG_SAR0_CSR6 EQU 0x40005906 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_BASE +CYDEV_ANAIF_CFG_SAR1_BASE EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_SIZE +CYDEV_ANAIF_CFG_SAR1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR0 +CYREG_SAR1_CSR0 EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR1 +CYREG_SAR1_CSR1 EQU 0x40005909 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR2 +CYREG_SAR1_CSR2 EQU 0x4000590a + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR3 +CYREG_SAR1_CSR3 EQU 0x4000590b + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR4 +CYREG_SAR1_CSR4 EQU 0x4000590c + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR5 +CYREG_SAR1_CSR5 EQU 0x4000590d + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR6 +CYREG_SAR1_CSR6 EQU 0x4000590e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BASE +CYDEV_ANAIF_RT_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SIZE +CYDEV_ANAIF_RT_SIZE EQU 0x00000162 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BASE +CYDEV_ANAIF_RT_SC0_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SIZE +CYDEV_ANAIF_RT_SC0_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW0 +CYREG_SC0_SW0 EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW2 +CYREG_SC0_SW2 EQU 0x40005a02 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW3 +CYREG_SC0_SW3 EQU 0x40005a03 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW4 +CYREG_SC0_SW4 EQU 0x40005a04 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW6 +CYREG_SC0_SW6 EQU 0x40005a06 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW7 +CYREG_SC0_SW7 EQU 0x40005a07 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW8 +CYREG_SC0_SW8 EQU 0x40005a08 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW10 +CYREG_SC0_SW10 EQU 0x40005a0a + ENDIF + IF :LNOT::DEF:CYREG_SC0_CLK +CYREG_SC0_CLK EQU 0x40005a0b + ENDIF + IF :LNOT::DEF:CYREG_SC0_BST +CYREG_SC0_BST EQU 0x40005a0c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BASE +CYDEV_ANAIF_RT_SC1_BASE EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SIZE +CYDEV_ANAIF_RT_SC1_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW0 +CYREG_SC1_SW0 EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW2 +CYREG_SC1_SW2 EQU 0x40005a12 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW3 +CYREG_SC1_SW3 EQU 0x40005a13 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW4 +CYREG_SC1_SW4 EQU 0x40005a14 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW6 +CYREG_SC1_SW6 EQU 0x40005a16 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW7 +CYREG_SC1_SW7 EQU 0x40005a17 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW8 +CYREG_SC1_SW8 EQU 0x40005a18 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW10 +CYREG_SC1_SW10 EQU 0x40005a1a + ENDIF + IF :LNOT::DEF:CYREG_SC1_CLK +CYREG_SC1_CLK EQU 0x40005a1b + ENDIF + IF :LNOT::DEF:CYREG_SC1_BST +CYREG_SC1_BST EQU 0x40005a1c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BASE +CYDEV_ANAIF_RT_SC2_BASE EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SIZE +CYDEV_ANAIF_RT_SC2_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW0 +CYREG_SC2_SW0 EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW2 +CYREG_SC2_SW2 EQU 0x40005a22 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW3 +CYREG_SC2_SW3 EQU 0x40005a23 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW4 +CYREG_SC2_SW4 EQU 0x40005a24 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW6 +CYREG_SC2_SW6 EQU 0x40005a26 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW7 +CYREG_SC2_SW7 EQU 0x40005a27 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW8 +CYREG_SC2_SW8 EQU 0x40005a28 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW10 +CYREG_SC2_SW10 EQU 0x40005a2a + ENDIF + IF :LNOT::DEF:CYREG_SC2_CLK +CYREG_SC2_CLK EQU 0x40005a2b + ENDIF + IF :LNOT::DEF:CYREG_SC2_BST +CYREG_SC2_BST EQU 0x40005a2c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BASE +CYDEV_ANAIF_RT_SC3_BASE EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SIZE +CYDEV_ANAIF_RT_SC3_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW0 +CYREG_SC3_SW0 EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW2 +CYREG_SC3_SW2 EQU 0x40005a32 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW3 +CYREG_SC3_SW3 EQU 0x40005a33 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW4 +CYREG_SC3_SW4 EQU 0x40005a34 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW6 +CYREG_SC3_SW6 EQU 0x40005a36 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW7 +CYREG_SC3_SW7 EQU 0x40005a37 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW8 +CYREG_SC3_SW8 EQU 0x40005a38 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW10 +CYREG_SC3_SW10 EQU 0x40005a3a + ENDIF + IF :LNOT::DEF:CYREG_SC3_CLK +CYREG_SC3_CLK EQU 0x40005a3b + ENDIF + IF :LNOT::DEF:CYREG_SC3_BST +CYREG_SC3_BST EQU 0x40005a3c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_BASE +CYDEV_ANAIF_RT_DAC0_BASE EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SIZE +CYDEV_ANAIF_RT_DAC0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW0 +CYREG_DAC0_SW0 EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW2 +CYREG_DAC0_SW2 EQU 0x40005a82 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW3 +CYREG_DAC0_SW3 EQU 0x40005a83 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW4 +CYREG_DAC0_SW4 EQU 0x40005a84 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_STROBE +CYREG_DAC0_STROBE EQU 0x40005a87 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_BASE +CYDEV_ANAIF_RT_DAC1_BASE EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SIZE +CYDEV_ANAIF_RT_DAC1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW0 +CYREG_DAC1_SW0 EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW2 +CYREG_DAC1_SW2 EQU 0x40005a8a + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW3 +CYREG_DAC1_SW3 EQU 0x40005a8b + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW4 +CYREG_DAC1_SW4 EQU 0x40005a8c + ENDIF + IF :LNOT::DEF:CYREG_DAC1_STROBE +CYREG_DAC1_STROBE EQU 0x40005a8f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_BASE +CYDEV_ANAIF_RT_DAC2_BASE EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SIZE +CYDEV_ANAIF_RT_DAC2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW0 +CYREG_DAC2_SW0 EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW2 +CYREG_DAC2_SW2 EQU 0x40005a92 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW3 +CYREG_DAC2_SW3 EQU 0x40005a93 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW4 +CYREG_DAC2_SW4 EQU 0x40005a94 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_STROBE +CYREG_DAC2_STROBE EQU 0x40005a97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_BASE +CYDEV_ANAIF_RT_DAC3_BASE EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SIZE +CYDEV_ANAIF_RT_DAC3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW0 +CYREG_DAC3_SW0 EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW2 +CYREG_DAC3_SW2 EQU 0x40005a9a + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW3 +CYREG_DAC3_SW3 EQU 0x40005a9b + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW4 +CYREG_DAC3_SW4 EQU 0x40005a9c + ENDIF + IF :LNOT::DEF:CYREG_DAC3_STROBE +CYREG_DAC3_STROBE EQU 0x40005a9f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_BASE +CYDEV_ANAIF_RT_CMP0_BASE EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SIZE +CYDEV_ANAIF_RT_CMP0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW0 +CYREG_CMP0_SW0 EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW2 +CYREG_CMP0_SW2 EQU 0x40005ac2 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW3 +CYREG_CMP0_SW3 EQU 0x40005ac3 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW4 +CYREG_CMP0_SW4 EQU 0x40005ac4 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW6 +CYREG_CMP0_SW6 EQU 0x40005ac6 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_CLK +CYREG_CMP0_CLK EQU 0x40005ac7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_BASE +CYDEV_ANAIF_RT_CMP1_BASE EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SIZE +CYDEV_ANAIF_RT_CMP1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW0 +CYREG_CMP1_SW0 EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW2 +CYREG_CMP1_SW2 EQU 0x40005aca + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW3 +CYREG_CMP1_SW3 EQU 0x40005acb + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW4 +CYREG_CMP1_SW4 EQU 0x40005acc + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW6 +CYREG_CMP1_SW6 EQU 0x40005ace + ENDIF + IF :LNOT::DEF:CYREG_CMP1_CLK +CYREG_CMP1_CLK EQU 0x40005acf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_BASE +CYDEV_ANAIF_RT_CMP2_BASE EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SIZE +CYDEV_ANAIF_RT_CMP2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW0 +CYREG_CMP2_SW0 EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW2 +CYREG_CMP2_SW2 EQU 0x40005ad2 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW3 +CYREG_CMP2_SW3 EQU 0x40005ad3 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW4 +CYREG_CMP2_SW4 EQU 0x40005ad4 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW6 +CYREG_CMP2_SW6 EQU 0x40005ad6 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_CLK +CYREG_CMP2_CLK EQU 0x40005ad7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_BASE +CYDEV_ANAIF_RT_CMP3_BASE EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SIZE +CYDEV_ANAIF_RT_CMP3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW0 +CYREG_CMP3_SW0 EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW2 +CYREG_CMP3_SW2 EQU 0x40005ada + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW3 +CYREG_CMP3_SW3 EQU 0x40005adb + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW4 +CYREG_CMP3_SW4 EQU 0x40005adc + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW6 +CYREG_CMP3_SW6 EQU 0x40005ade + ENDIF + IF :LNOT::DEF:CYREG_CMP3_CLK +CYREG_CMP3_CLK EQU 0x40005adf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_BASE +CYDEV_ANAIF_RT_DSM0_BASE EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SIZE +CYDEV_ANAIF_RT_DSM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW0 +CYREG_DSM0_SW0 EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW2 +CYREG_DSM0_SW2 EQU 0x40005b02 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW3 +CYREG_DSM0_SW3 EQU 0x40005b03 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW4 +CYREG_DSM0_SW4 EQU 0x40005b04 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW6 +CYREG_DSM0_SW6 EQU 0x40005b06 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CLK +CYREG_DSM0_CLK EQU 0x40005b07 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_BASE +CYDEV_ANAIF_RT_SAR0_BASE EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SIZE +CYDEV_ANAIF_RT_SAR0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW0 +CYREG_SAR0_SW0 EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW2 +CYREG_SAR0_SW2 EQU 0x40005b22 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW3 +CYREG_SAR0_SW3 EQU 0x40005b23 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW4 +CYREG_SAR0_SW4 EQU 0x40005b24 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW6 +CYREG_SAR0_SW6 EQU 0x40005b26 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CLK +CYREG_SAR0_CLK EQU 0x40005b27 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_BASE +CYDEV_ANAIF_RT_SAR1_BASE EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SIZE +CYDEV_ANAIF_RT_SAR1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW0 +CYREG_SAR1_SW0 EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW2 +CYREG_SAR1_SW2 EQU 0x40005b2a + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW3 +CYREG_SAR1_SW3 EQU 0x40005b2b + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW4 +CYREG_SAR1_SW4 EQU 0x40005b2c + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW6 +CYREG_SAR1_SW6 EQU 0x40005b2e + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CLK +CYREG_SAR1_CLK EQU 0x40005b2f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_BASE +CYDEV_ANAIF_RT_OPAMP0_BASE EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SIZE +CYDEV_ANAIF_RT_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_MX +CYREG_OPAMP0_MX EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_SW +CYREG_OPAMP0_SW EQU 0x40005b41 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_BASE +CYDEV_ANAIF_RT_OPAMP1_BASE EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SIZE +CYDEV_ANAIF_RT_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_MX +CYREG_OPAMP1_MX EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_SW +CYREG_OPAMP1_SW EQU 0x40005b43 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_BASE +CYDEV_ANAIF_RT_OPAMP2_BASE EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SIZE +CYDEV_ANAIF_RT_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_MX +CYREG_OPAMP2_MX EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_SW +CYREG_OPAMP2_SW EQU 0x40005b45 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_BASE +CYDEV_ANAIF_RT_OPAMP3_BASE EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SIZE +CYDEV_ANAIF_RT_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_MX +CYREG_OPAMP3_MX EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_SW +CYREG_OPAMP3_SW EQU 0x40005b47 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_BASE +CYDEV_ANAIF_RT_LCDDAC_BASE EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SIZE +CYDEV_ANAIF_RT_LCDDAC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW0 +CYREG_LCDDAC_SW0 EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW1 +CYREG_LCDDAC_SW1 EQU 0x40005b51 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW2 +CYREG_LCDDAC_SW2 EQU 0x40005b52 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW3 +CYREG_LCDDAC_SW3 EQU 0x40005b53 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW4 +CYREG_LCDDAC_SW4 EQU 0x40005b54 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_BASE +CYDEV_ANAIF_RT_SC_BASE EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_SIZE +CYDEV_ANAIF_RT_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SC_MISC +CYREG_SC_MISC EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_BASE +CYDEV_ANAIF_RT_BUS_BASE EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SIZE +CYDEV_ANAIF_RT_BUS_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_BUS_SW0 +CYREG_BUS_SW0 EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYREG_BUS_SW2 +CYREG_BUS_SW2 EQU 0x40005b5a + ENDIF + IF :LNOT::DEF:CYREG_BUS_SW3 +CYREG_BUS_SW3 EQU 0x40005b5b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_BASE +CYDEV_ANAIF_RT_DFT_BASE EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_SIZE +CYDEV_ANAIF_RT_DFT_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR0 +CYREG_DFT_CR0 EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR1 +CYREG_DFT_CR1 EQU 0x40005b5d + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR2 +CYREG_DFT_CR2 EQU 0x40005b5e + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR3 +CYREG_DFT_CR3 EQU 0x40005b5f + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR4 +CYREG_DFT_CR4 EQU 0x40005b60 + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR5 +CYREG_DFT_CR5 EQU 0x40005b61 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_BASE +CYDEV_ANAIF_WRK_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SIZE +CYDEV_ANAIF_WRK_SIZE EQU 0x00000029 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_BASE +CYDEV_ANAIF_WRK_DAC0_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_SIZE +CYDEV_ANAIF_WRK_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_D +CYREG_DAC0_D EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_BASE +CYDEV_ANAIF_WRK_DAC1_BASE EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_SIZE +CYDEV_ANAIF_WRK_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_D +CYREG_DAC1_D EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_BASE +CYDEV_ANAIF_WRK_DAC2_BASE EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_SIZE +CYDEV_ANAIF_WRK_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_D +CYREG_DAC2_D EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_BASE +CYDEV_ANAIF_WRK_DAC3_BASE EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_SIZE +CYDEV_ANAIF_WRK_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_D +CYREG_DAC3_D EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_BASE +CYDEV_ANAIF_WRK_DSM0_BASE EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_SIZE +CYDEV_ANAIF_WRK_DSM0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_OUT0 +CYREG_DSM0_OUT0 EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_OUT1 +CYREG_DSM0_OUT1 EQU 0x40005b89 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_BASE +CYDEV_ANAIF_WRK_LUT_BASE EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SIZE +CYDEV_ANAIF_WRK_LUT_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LUT_SR +CYREG_LUT_SR EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYREG_LUT_WRK1 +CYREG_LUT_WRK1 EQU 0x40005b91 + ENDIF + IF :LNOT::DEF:CYREG_LUT_MSK +CYREG_LUT_MSK EQU 0x40005b92 + ENDIF + IF :LNOT::DEF:CYREG_LUT_CLK +CYREG_LUT_CLK EQU 0x40005b93 + ENDIF + IF :LNOT::DEF:CYREG_LUT_CPTR +CYREG_LUT_CPTR EQU 0x40005b94 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_BASE +CYDEV_ANAIF_WRK_CMP_BASE EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_SIZE +CYDEV_ANAIF_WRK_CMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP_WRK +CYREG_CMP_WRK EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYREG_CMP_TST +CYREG_CMP_TST EQU 0x40005b97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_BASE +CYDEV_ANAIF_WRK_SC_BASE EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SIZE +CYDEV_ANAIF_WRK_SC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_SC_SR +CYREG_SC_SR EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYREG_SC_WRK1 +CYREG_SC_WRK1 EQU 0x40005b99 + ENDIF + IF :LNOT::DEF:CYREG_SC_MSK +CYREG_SC_MSK EQU 0x40005b9a + ENDIF + IF :LNOT::DEF:CYREG_SC_CMPINV +CYREG_SC_CMPINV EQU 0x40005b9b + ENDIF + IF :LNOT::DEF:CYREG_SC_CPTR +CYREG_SC_CPTR EQU 0x40005b9c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_BASE +CYDEV_ANAIF_WRK_SAR0_BASE EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_SIZE +CYDEV_ANAIF_WRK_SAR0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_WRK0 +CYREG_SAR0_WRK0 EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_WRK1 +CYREG_SAR0_WRK1 EQU 0x40005ba1 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_BASE +CYDEV_ANAIF_WRK_SAR1_BASE EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_SIZE +CYDEV_ANAIF_WRK_SAR1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_WRK0 +CYREG_SAR1_WRK0 EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_WRK1 +CYREG_SAR1_WRK1 EQU 0x40005ba3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_BASE +CYDEV_ANAIF_WRK_SARS_BASE EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SIZE +CYDEV_ANAIF_WRK_SARS_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_ANAIF_WRK_SARS_SOF +CYREG_ANAIF_WRK_SARS_SOF EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BASE +CYDEV_USB_BASE EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIZE +CYDEV_USB_SIZE EQU 0x00000300 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR0 +CYREG_USB_EP0_DR0 EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR1 +CYREG_USB_EP0_DR1 EQU 0x40006001 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR2 +CYREG_USB_EP0_DR2 EQU 0x40006002 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR3 +CYREG_USB_EP0_DR3 EQU 0x40006003 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR4 +CYREG_USB_EP0_DR4 EQU 0x40006004 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR5 +CYREG_USB_EP0_DR5 EQU 0x40006005 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR6 +CYREG_USB_EP0_DR6 EQU 0x40006006 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR7 +CYREG_USB_EP0_DR7 EQU 0x40006007 + ENDIF + IF :LNOT::DEF:CYREG_USB_CR0 +CYREG_USB_CR0 EQU 0x40006008 + ENDIF + IF :LNOT::DEF:CYREG_USB_CR1 +CYREG_USB_CR1 EQU 0x40006009 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP_INT_EN +CYREG_USB_SIE_EP_INT_EN EQU 0x4000600a + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP_INT_SR +CYREG_USB_SIE_EP_INT_SR EQU 0x4000600b + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_BASE +CYDEV_USB_SIE_EP1_BASE EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_SIZE +CYDEV_USB_SIE_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP1_CNT0 +CYREG_USB_SIE_EP1_CNT0 EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP1_CNT1 +CYREG_USB_SIE_EP1_CNT1 EQU 0x4000600d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP1_CR0 +CYREG_USB_SIE_EP1_CR0 EQU 0x4000600e + ENDIF + IF :LNOT::DEF:CYREG_USB_USBIO_CR0 +CYREG_USB_USBIO_CR0 EQU 0x40006010 + ENDIF + IF :LNOT::DEF:CYREG_USB_USBIO_CR1 +CYREG_USB_USBIO_CR1 EQU 0x40006012 + ENDIF + IF :LNOT::DEF:CYREG_USB_DYN_RECONFIG +CYREG_USB_DYN_RECONFIG EQU 0x40006014 + ENDIF + IF :LNOT::DEF:CYREG_USB_SOF0 +CYREG_USB_SOF0 EQU 0x40006018 + ENDIF + IF :LNOT::DEF:CYREG_USB_SOF1 +CYREG_USB_SOF1 EQU 0x40006019 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_BASE +CYDEV_USB_SIE_EP2_BASE EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_SIZE +CYDEV_USB_SIE_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP2_CNT0 +CYREG_USB_SIE_EP2_CNT0 EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP2_CNT1 +CYREG_USB_SIE_EP2_CNT1 EQU 0x4000601d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP2_CR0 +CYREG_USB_SIE_EP2_CR0 EQU 0x4000601e + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_CR +CYREG_USB_EP0_CR EQU 0x40006028 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_CNT +CYREG_USB_EP0_CNT EQU 0x40006029 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_BASE +CYDEV_USB_SIE_EP3_BASE EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_SIZE +CYDEV_USB_SIE_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP3_CNT0 +CYREG_USB_SIE_EP3_CNT0 EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP3_CNT1 +CYREG_USB_SIE_EP3_CNT1 EQU 0x4000602d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP3_CR0 +CYREG_USB_SIE_EP3_CR0 EQU 0x4000602e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_BASE +CYDEV_USB_SIE_EP4_BASE EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_SIZE +CYDEV_USB_SIE_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP4_CNT0 +CYREG_USB_SIE_EP4_CNT0 EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP4_CNT1 +CYREG_USB_SIE_EP4_CNT1 EQU 0x4000603d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP4_CR0 +CYREG_USB_SIE_EP4_CR0 EQU 0x4000603e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_BASE +CYDEV_USB_SIE_EP5_BASE EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_SIZE +CYDEV_USB_SIE_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP5_CNT0 +CYREG_USB_SIE_EP5_CNT0 EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP5_CNT1 +CYREG_USB_SIE_EP5_CNT1 EQU 0x4000604d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP5_CR0 +CYREG_USB_SIE_EP5_CR0 EQU 0x4000604e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_BASE +CYDEV_USB_SIE_EP6_BASE EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_SIZE +CYDEV_USB_SIE_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP6_CNT0 +CYREG_USB_SIE_EP6_CNT0 EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP6_CNT1 +CYREG_USB_SIE_EP6_CNT1 EQU 0x4000605d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP6_CR0 +CYREG_USB_SIE_EP6_CR0 EQU 0x4000605e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_BASE +CYDEV_USB_SIE_EP7_BASE EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_SIZE +CYDEV_USB_SIE_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP7_CNT0 +CYREG_USB_SIE_EP7_CNT0 EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP7_CNT1 +CYREG_USB_SIE_EP7_CNT1 EQU 0x4000606d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP7_CR0 +CYREG_USB_SIE_EP7_CR0 EQU 0x4000606e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_BASE +CYDEV_USB_SIE_EP8_BASE EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_SIZE +CYDEV_USB_SIE_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP8_CNT0 +CYREG_USB_SIE_EP8_CNT0 EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP8_CNT1 +CYREG_USB_SIE_EP8_CNT1 EQU 0x4000607d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP8_CR0 +CYREG_USB_SIE_EP8_CR0 EQU 0x4000607e + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_BASE +CYDEV_USB_ARB_EP1_BASE EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SIZE +CYDEV_USB_ARB_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP1_CFG +CYREG_USB_ARB_EP1_CFG EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP1_INT_EN +CYREG_USB_ARB_EP1_INT_EN EQU 0x40006081 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP1_SR +CYREG_USB_ARB_EP1_SR EQU 0x40006082 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_BASE +CYDEV_USB_ARB_RW1_BASE EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_SIZE +CYDEV_USB_ARB_RW1_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_WA +CYREG_USB_ARB_RW1_WA EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_WA_MSB +CYREG_USB_ARB_RW1_WA_MSB EQU 0x40006085 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_RA +CYREG_USB_ARB_RW1_RA EQU 0x40006086 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_RA_MSB +CYREG_USB_ARB_RW1_RA_MSB EQU 0x40006087 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_DR +CYREG_USB_ARB_RW1_DR EQU 0x40006088 + ENDIF + IF :LNOT::DEF:CYREG_USB_BUF_SIZE +CYREG_USB_BUF_SIZE EQU 0x4000608c + ENDIF + IF :LNOT::DEF:CYREG_USB_EP_ACTIVE +CYREG_USB_EP_ACTIVE EQU 0x4000608e + ENDIF + IF :LNOT::DEF:CYREG_USB_EP_TYPE +CYREG_USB_EP_TYPE EQU 0x4000608f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_BASE +CYDEV_USB_ARB_EP2_BASE EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SIZE +CYDEV_USB_ARB_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP2_CFG +CYREG_USB_ARB_EP2_CFG EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP2_INT_EN +CYREG_USB_ARB_EP2_INT_EN EQU 0x40006091 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP2_SR +CYREG_USB_ARB_EP2_SR EQU 0x40006092 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_BASE +CYDEV_USB_ARB_RW2_BASE EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_SIZE +CYDEV_USB_ARB_RW2_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_WA +CYREG_USB_ARB_RW2_WA EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_WA_MSB +CYREG_USB_ARB_RW2_WA_MSB EQU 0x40006095 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_RA +CYREG_USB_ARB_RW2_RA EQU 0x40006096 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_RA_MSB +CYREG_USB_ARB_RW2_RA_MSB EQU 0x40006097 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_DR +CYREG_USB_ARB_RW2_DR EQU 0x40006098 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_CFG +CYREG_USB_ARB_CFG EQU 0x4000609c + ENDIF + IF :LNOT::DEF:CYREG_USB_USB_CLK_EN +CYREG_USB_USB_CLK_EN EQU 0x4000609d + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_INT_EN +CYREG_USB_ARB_INT_EN EQU 0x4000609e + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_INT_SR +CYREG_USB_ARB_INT_SR EQU 0x4000609f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_BASE +CYDEV_USB_ARB_EP3_BASE EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SIZE +CYDEV_USB_ARB_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP3_CFG +CYREG_USB_ARB_EP3_CFG EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP3_INT_EN +CYREG_USB_ARB_EP3_INT_EN EQU 0x400060a1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP3_SR +CYREG_USB_ARB_EP3_SR EQU 0x400060a2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_BASE +CYDEV_USB_ARB_RW3_BASE EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_SIZE +CYDEV_USB_ARB_RW3_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_WA +CYREG_USB_ARB_RW3_WA EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_WA_MSB +CYREG_USB_ARB_RW3_WA_MSB EQU 0x400060a5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_RA +CYREG_USB_ARB_RW3_RA EQU 0x400060a6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_RA_MSB +CYREG_USB_ARB_RW3_RA_MSB EQU 0x400060a7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_DR +CYREG_USB_ARB_RW3_DR EQU 0x400060a8 + ENDIF + IF :LNOT::DEF:CYREG_USB_CWA +CYREG_USB_CWA EQU 0x400060ac + ENDIF + IF :LNOT::DEF:CYREG_USB_CWA_MSB +CYREG_USB_CWA_MSB EQU 0x400060ad + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_BASE +CYDEV_USB_ARB_EP4_BASE EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SIZE +CYDEV_USB_ARB_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP4_CFG +CYREG_USB_ARB_EP4_CFG EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP4_INT_EN +CYREG_USB_ARB_EP4_INT_EN EQU 0x400060b1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP4_SR +CYREG_USB_ARB_EP4_SR EQU 0x400060b2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_BASE +CYDEV_USB_ARB_RW4_BASE EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_SIZE +CYDEV_USB_ARB_RW4_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_WA +CYREG_USB_ARB_RW4_WA EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_WA_MSB +CYREG_USB_ARB_RW4_WA_MSB EQU 0x400060b5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_RA +CYREG_USB_ARB_RW4_RA EQU 0x400060b6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_RA_MSB +CYREG_USB_ARB_RW4_RA_MSB EQU 0x400060b7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_DR +CYREG_USB_ARB_RW4_DR EQU 0x400060b8 + ENDIF + IF :LNOT::DEF:CYREG_USB_DMA_THRES +CYREG_USB_DMA_THRES EQU 0x400060bc + ENDIF + IF :LNOT::DEF:CYREG_USB_DMA_THRES_MSB +CYREG_USB_DMA_THRES_MSB EQU 0x400060bd + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_BASE +CYDEV_USB_ARB_EP5_BASE EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SIZE +CYDEV_USB_ARB_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP5_CFG +CYREG_USB_ARB_EP5_CFG EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP5_INT_EN +CYREG_USB_ARB_EP5_INT_EN EQU 0x400060c1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP5_SR +CYREG_USB_ARB_EP5_SR EQU 0x400060c2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_BASE +CYDEV_USB_ARB_RW5_BASE EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_SIZE +CYDEV_USB_ARB_RW5_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_WA +CYREG_USB_ARB_RW5_WA EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_WA_MSB +CYREG_USB_ARB_RW5_WA_MSB EQU 0x400060c5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_RA +CYREG_USB_ARB_RW5_RA EQU 0x400060c6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_RA_MSB +CYREG_USB_ARB_RW5_RA_MSB EQU 0x400060c7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_DR +CYREG_USB_ARB_RW5_DR EQU 0x400060c8 + ENDIF + IF :LNOT::DEF:CYREG_USB_BUS_RST_CNT +CYREG_USB_BUS_RST_CNT EQU 0x400060cc + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_BASE +CYDEV_USB_ARB_EP6_BASE EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SIZE +CYDEV_USB_ARB_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP6_CFG +CYREG_USB_ARB_EP6_CFG EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP6_INT_EN +CYREG_USB_ARB_EP6_INT_EN EQU 0x400060d1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP6_SR +CYREG_USB_ARB_EP6_SR EQU 0x400060d2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_BASE +CYDEV_USB_ARB_RW6_BASE EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_SIZE +CYDEV_USB_ARB_RW6_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_WA +CYREG_USB_ARB_RW6_WA EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_WA_MSB +CYREG_USB_ARB_RW6_WA_MSB EQU 0x400060d5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_RA +CYREG_USB_ARB_RW6_RA EQU 0x400060d6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_RA_MSB +CYREG_USB_ARB_RW6_RA_MSB EQU 0x400060d7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_DR +CYREG_USB_ARB_RW6_DR EQU 0x400060d8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_BASE +CYDEV_USB_ARB_EP7_BASE EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SIZE +CYDEV_USB_ARB_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP7_CFG +CYREG_USB_ARB_EP7_CFG EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP7_INT_EN +CYREG_USB_ARB_EP7_INT_EN EQU 0x400060e1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP7_SR +CYREG_USB_ARB_EP7_SR EQU 0x400060e2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_BASE +CYDEV_USB_ARB_RW7_BASE EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_SIZE +CYDEV_USB_ARB_RW7_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_WA +CYREG_USB_ARB_RW7_WA EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_WA_MSB +CYREG_USB_ARB_RW7_WA_MSB EQU 0x400060e5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_RA +CYREG_USB_ARB_RW7_RA EQU 0x400060e6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_RA_MSB +CYREG_USB_ARB_RW7_RA_MSB EQU 0x400060e7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_DR +CYREG_USB_ARB_RW7_DR EQU 0x400060e8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_BASE +CYDEV_USB_ARB_EP8_BASE EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SIZE +CYDEV_USB_ARB_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP8_CFG +CYREG_USB_ARB_EP8_CFG EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP8_INT_EN +CYREG_USB_ARB_EP8_INT_EN EQU 0x400060f1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP8_SR +CYREG_USB_ARB_EP8_SR EQU 0x400060f2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_BASE +CYDEV_USB_ARB_RW8_BASE EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_SIZE +CYDEV_USB_ARB_RW8_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_WA +CYREG_USB_ARB_RW8_WA EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_WA_MSB +CYREG_USB_ARB_RW8_WA_MSB EQU 0x400060f5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_RA +CYREG_USB_ARB_RW8_RA EQU 0x400060f6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_RA_MSB +CYREG_USB_ARB_RW8_RA_MSB EQU 0x400060f7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_DR +CYREG_USB_ARB_RW8_DR EQU 0x400060f8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_BASE +CYDEV_USB_MEM_BASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_SIZE +CYDEV_USB_MEM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_USB_MEM_DATA_MBASE +CYREG_USB_MEM_DATA_MBASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYREG_USB_MEM_DATA_MSIZE +CYREG_USB_MEM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_BASE +CYDEV_UWRK_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_SIZE +CYDEV_UWRK_SIZE EQU 0x00000b60 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_BASE +CYDEV_UWRK_UWRK8_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_SIZE +CYDEV_UWRK_UWRK8_SIZE EQU 0x000003b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_BASE +CYDEV_UWRK_UWRK8_B0_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_SIZE +CYDEV_UWRK_UWRK8_B0_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_A0 +CYREG_B0_UDB00_A0 EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_A0 +CYREG_B0_UDB01_A0 EQU 0x40006401 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_A0 +CYREG_B0_UDB02_A0 EQU 0x40006402 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_A0 +CYREG_B0_UDB03_A0 EQU 0x40006403 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_A0 +CYREG_B0_UDB04_A0 EQU 0x40006404 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_A0 +CYREG_B0_UDB05_A0 EQU 0x40006405 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_A0 +CYREG_B0_UDB06_A0 EQU 0x40006406 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_A0 +CYREG_B0_UDB07_A0 EQU 0x40006407 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_A0 +CYREG_B0_UDB08_A0 EQU 0x40006408 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_A0 +CYREG_B0_UDB09_A0 EQU 0x40006409 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_A0 +CYREG_B0_UDB10_A0 EQU 0x4000640a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_A0 +CYREG_B0_UDB11_A0 EQU 0x4000640b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_A0 +CYREG_B0_UDB12_A0 EQU 0x4000640c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_A0 +CYREG_B0_UDB13_A0 EQU 0x4000640d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_A0 +CYREG_B0_UDB14_A0 EQU 0x4000640e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_A0 +CYREG_B0_UDB15_A0 EQU 0x4000640f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_A1 +CYREG_B0_UDB00_A1 EQU 0x40006410 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_A1 +CYREG_B0_UDB01_A1 EQU 0x40006411 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_A1 +CYREG_B0_UDB02_A1 EQU 0x40006412 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_A1 +CYREG_B0_UDB03_A1 EQU 0x40006413 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_A1 +CYREG_B0_UDB04_A1 EQU 0x40006414 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_A1 +CYREG_B0_UDB05_A1 EQU 0x40006415 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_A1 +CYREG_B0_UDB06_A1 EQU 0x40006416 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_A1 +CYREG_B0_UDB07_A1 EQU 0x40006417 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_A1 +CYREG_B0_UDB08_A1 EQU 0x40006418 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_A1 +CYREG_B0_UDB09_A1 EQU 0x40006419 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_A1 +CYREG_B0_UDB10_A1 EQU 0x4000641a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_A1 +CYREG_B0_UDB11_A1 EQU 0x4000641b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_A1 +CYREG_B0_UDB12_A1 EQU 0x4000641c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_A1 +CYREG_B0_UDB13_A1 EQU 0x4000641d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_A1 +CYREG_B0_UDB14_A1 EQU 0x4000641e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_A1 +CYREG_B0_UDB15_A1 EQU 0x4000641f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_D0 +CYREG_B0_UDB00_D0 EQU 0x40006420 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_D0 +CYREG_B0_UDB01_D0 EQU 0x40006421 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_D0 +CYREG_B0_UDB02_D0 EQU 0x40006422 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_D0 +CYREG_B0_UDB03_D0 EQU 0x40006423 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_D0 +CYREG_B0_UDB04_D0 EQU 0x40006424 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_D0 +CYREG_B0_UDB05_D0 EQU 0x40006425 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_D0 +CYREG_B0_UDB06_D0 EQU 0x40006426 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_D0 +CYREG_B0_UDB07_D0 EQU 0x40006427 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_D0 +CYREG_B0_UDB08_D0 EQU 0x40006428 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_D0 +CYREG_B0_UDB09_D0 EQU 0x40006429 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_D0 +CYREG_B0_UDB10_D0 EQU 0x4000642a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_D0 +CYREG_B0_UDB11_D0 EQU 0x4000642b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_D0 +CYREG_B0_UDB12_D0 EQU 0x4000642c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_D0 +CYREG_B0_UDB13_D0 EQU 0x4000642d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_D0 +CYREG_B0_UDB14_D0 EQU 0x4000642e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_D0 +CYREG_B0_UDB15_D0 EQU 0x4000642f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_D1 +CYREG_B0_UDB00_D1 EQU 0x40006430 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_D1 +CYREG_B0_UDB01_D1 EQU 0x40006431 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_D1 +CYREG_B0_UDB02_D1 EQU 0x40006432 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_D1 +CYREG_B0_UDB03_D1 EQU 0x40006433 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_D1 +CYREG_B0_UDB04_D1 EQU 0x40006434 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_D1 +CYREG_B0_UDB05_D1 EQU 0x40006435 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_D1 +CYREG_B0_UDB06_D1 EQU 0x40006436 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_D1 +CYREG_B0_UDB07_D1 EQU 0x40006437 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_D1 +CYREG_B0_UDB08_D1 EQU 0x40006438 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_D1 +CYREG_B0_UDB09_D1 EQU 0x40006439 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_D1 +CYREG_B0_UDB10_D1 EQU 0x4000643a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_D1 +CYREG_B0_UDB11_D1 EQU 0x4000643b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_D1 +CYREG_B0_UDB12_D1 EQU 0x4000643c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_D1 +CYREG_B0_UDB13_D1 EQU 0x4000643d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_D1 +CYREG_B0_UDB14_D1 EQU 0x4000643e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_D1 +CYREG_B0_UDB15_D1 EQU 0x4000643f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_F0 +CYREG_B0_UDB00_F0 EQU 0x40006440 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_F0 +CYREG_B0_UDB01_F0 EQU 0x40006441 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_F0 +CYREG_B0_UDB02_F0 EQU 0x40006442 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_F0 +CYREG_B0_UDB03_F0 EQU 0x40006443 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_F0 +CYREG_B0_UDB04_F0 EQU 0x40006444 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_F0 +CYREG_B0_UDB05_F0 EQU 0x40006445 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_F0 +CYREG_B0_UDB06_F0 EQU 0x40006446 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_F0 +CYREG_B0_UDB07_F0 EQU 0x40006447 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_F0 +CYREG_B0_UDB08_F0 EQU 0x40006448 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_F0 +CYREG_B0_UDB09_F0 EQU 0x40006449 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_F0 +CYREG_B0_UDB10_F0 EQU 0x4000644a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_F0 +CYREG_B0_UDB11_F0 EQU 0x4000644b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_F0 +CYREG_B0_UDB12_F0 EQU 0x4000644c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_F0 +CYREG_B0_UDB13_F0 EQU 0x4000644d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_F0 +CYREG_B0_UDB14_F0 EQU 0x4000644e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_F0 +CYREG_B0_UDB15_F0 EQU 0x4000644f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_F1 +CYREG_B0_UDB00_F1 EQU 0x40006450 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_F1 +CYREG_B0_UDB01_F1 EQU 0x40006451 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_F1 +CYREG_B0_UDB02_F1 EQU 0x40006452 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_F1 +CYREG_B0_UDB03_F1 EQU 0x40006453 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_F1 +CYREG_B0_UDB04_F1 EQU 0x40006454 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_F1 +CYREG_B0_UDB05_F1 EQU 0x40006455 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_F1 +CYREG_B0_UDB06_F1 EQU 0x40006456 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_F1 +CYREG_B0_UDB07_F1 EQU 0x40006457 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_F1 +CYREG_B0_UDB08_F1 EQU 0x40006458 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_F1 +CYREG_B0_UDB09_F1 EQU 0x40006459 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_F1 +CYREG_B0_UDB10_F1 EQU 0x4000645a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_F1 +CYREG_B0_UDB11_F1 EQU 0x4000645b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_F1 +CYREG_B0_UDB12_F1 EQU 0x4000645c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_F1 +CYREG_B0_UDB13_F1 EQU 0x4000645d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_F1 +CYREG_B0_UDB14_F1 EQU 0x4000645e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_F1 +CYREG_B0_UDB15_F1 EQU 0x4000645f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_ST +CYREG_B0_UDB00_ST EQU 0x40006460 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_ST +CYREG_B0_UDB01_ST EQU 0x40006461 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_ST +CYREG_B0_UDB02_ST EQU 0x40006462 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_ST +CYREG_B0_UDB03_ST EQU 0x40006463 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_ST +CYREG_B0_UDB04_ST EQU 0x40006464 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_ST +CYREG_B0_UDB05_ST EQU 0x40006465 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_ST +CYREG_B0_UDB06_ST EQU 0x40006466 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_ST +CYREG_B0_UDB07_ST EQU 0x40006467 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_ST +CYREG_B0_UDB08_ST EQU 0x40006468 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_ST +CYREG_B0_UDB09_ST EQU 0x40006469 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_ST +CYREG_B0_UDB10_ST EQU 0x4000646a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_ST +CYREG_B0_UDB11_ST EQU 0x4000646b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_ST +CYREG_B0_UDB12_ST EQU 0x4000646c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_ST +CYREG_B0_UDB13_ST EQU 0x4000646d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_ST +CYREG_B0_UDB14_ST EQU 0x4000646e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_ST +CYREG_B0_UDB15_ST EQU 0x4000646f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_CTL +CYREG_B0_UDB00_CTL EQU 0x40006470 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_CTL +CYREG_B0_UDB01_CTL EQU 0x40006471 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_CTL +CYREG_B0_UDB02_CTL EQU 0x40006472 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_CTL +CYREG_B0_UDB03_CTL EQU 0x40006473 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_CTL +CYREG_B0_UDB04_CTL EQU 0x40006474 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_CTL +CYREG_B0_UDB05_CTL EQU 0x40006475 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_CTL +CYREG_B0_UDB06_CTL EQU 0x40006476 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_CTL +CYREG_B0_UDB07_CTL EQU 0x40006477 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_CTL +CYREG_B0_UDB08_CTL EQU 0x40006478 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_CTL +CYREG_B0_UDB09_CTL EQU 0x40006479 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_CTL +CYREG_B0_UDB10_CTL EQU 0x4000647a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_CTL +CYREG_B0_UDB11_CTL EQU 0x4000647b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_CTL +CYREG_B0_UDB12_CTL EQU 0x4000647c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_CTL +CYREG_B0_UDB13_CTL EQU 0x4000647d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_CTL +CYREG_B0_UDB14_CTL EQU 0x4000647e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_CTL +CYREG_B0_UDB15_CTL EQU 0x4000647f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MSK +CYREG_B0_UDB00_MSK EQU 0x40006480 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MSK +CYREG_B0_UDB01_MSK EQU 0x40006481 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MSK +CYREG_B0_UDB02_MSK EQU 0x40006482 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MSK +CYREG_B0_UDB03_MSK EQU 0x40006483 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MSK +CYREG_B0_UDB04_MSK EQU 0x40006484 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MSK +CYREG_B0_UDB05_MSK EQU 0x40006485 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MSK +CYREG_B0_UDB06_MSK EQU 0x40006486 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MSK +CYREG_B0_UDB07_MSK EQU 0x40006487 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MSK +CYREG_B0_UDB08_MSK EQU 0x40006488 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MSK +CYREG_B0_UDB09_MSK EQU 0x40006489 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MSK +CYREG_B0_UDB10_MSK EQU 0x4000648a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MSK +CYREG_B0_UDB11_MSK EQU 0x4000648b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MSK +CYREG_B0_UDB12_MSK EQU 0x4000648c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MSK +CYREG_B0_UDB13_MSK EQU 0x4000648d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MSK +CYREG_B0_UDB14_MSK EQU 0x4000648e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MSK +CYREG_B0_UDB15_MSK EQU 0x4000648f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_ACTL +CYREG_B0_UDB00_ACTL EQU 0x40006490 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_ACTL +CYREG_B0_UDB01_ACTL EQU 0x40006491 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_ACTL +CYREG_B0_UDB02_ACTL EQU 0x40006492 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_ACTL +CYREG_B0_UDB03_ACTL EQU 0x40006493 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_ACTL +CYREG_B0_UDB04_ACTL EQU 0x40006494 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_ACTL +CYREG_B0_UDB05_ACTL EQU 0x40006495 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_ACTL +CYREG_B0_UDB06_ACTL EQU 0x40006496 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_ACTL +CYREG_B0_UDB07_ACTL EQU 0x40006497 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_ACTL +CYREG_B0_UDB08_ACTL EQU 0x40006498 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_ACTL +CYREG_B0_UDB09_ACTL EQU 0x40006499 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_ACTL +CYREG_B0_UDB10_ACTL EQU 0x4000649a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_ACTL +CYREG_B0_UDB11_ACTL EQU 0x4000649b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_ACTL +CYREG_B0_UDB12_ACTL EQU 0x4000649c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_ACTL +CYREG_B0_UDB13_ACTL EQU 0x4000649d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_ACTL +CYREG_B0_UDB14_ACTL EQU 0x4000649e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_ACTL +CYREG_B0_UDB15_ACTL EQU 0x4000649f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MC +CYREG_B0_UDB00_MC EQU 0x400064a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MC +CYREG_B0_UDB01_MC EQU 0x400064a1 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MC +CYREG_B0_UDB02_MC EQU 0x400064a2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MC +CYREG_B0_UDB03_MC EQU 0x400064a3 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MC +CYREG_B0_UDB04_MC EQU 0x400064a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MC +CYREG_B0_UDB05_MC EQU 0x400064a5 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MC +CYREG_B0_UDB06_MC EQU 0x400064a6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MC +CYREG_B0_UDB07_MC EQU 0x400064a7 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MC +CYREG_B0_UDB08_MC EQU 0x400064a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MC +CYREG_B0_UDB09_MC EQU 0x400064a9 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MC +CYREG_B0_UDB10_MC EQU 0x400064aa + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MC +CYREG_B0_UDB11_MC EQU 0x400064ab + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MC +CYREG_B0_UDB12_MC EQU 0x400064ac + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MC +CYREG_B0_UDB13_MC EQU 0x400064ad + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MC +CYREG_B0_UDB14_MC EQU 0x400064ae + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MC +CYREG_B0_UDB15_MC EQU 0x400064af + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_BASE +CYDEV_UWRK_UWRK8_B1_BASE EQU 0x40006500 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_SIZE +CYDEV_UWRK_UWRK8_B1_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_A0 +CYREG_B1_UDB04_A0 EQU 0x40006504 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_A0 +CYREG_B1_UDB05_A0 EQU 0x40006505 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_A0 +CYREG_B1_UDB06_A0 EQU 0x40006506 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_A0 +CYREG_B1_UDB07_A0 EQU 0x40006507 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_A0 +CYREG_B1_UDB08_A0 EQU 0x40006508 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_A0 +CYREG_B1_UDB09_A0 EQU 0x40006509 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_A0 +CYREG_B1_UDB10_A0 EQU 0x4000650a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_A0 +CYREG_B1_UDB11_A0 EQU 0x4000650b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_A1 +CYREG_B1_UDB04_A1 EQU 0x40006514 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_A1 +CYREG_B1_UDB05_A1 EQU 0x40006515 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_A1 +CYREG_B1_UDB06_A1 EQU 0x40006516 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_A1 +CYREG_B1_UDB07_A1 EQU 0x40006517 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_A1 +CYREG_B1_UDB08_A1 EQU 0x40006518 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_A1 +CYREG_B1_UDB09_A1 EQU 0x40006519 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_A1 +CYREG_B1_UDB10_A1 EQU 0x4000651a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_A1 +CYREG_B1_UDB11_A1 EQU 0x4000651b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_D0 +CYREG_B1_UDB04_D0 EQU 0x40006524 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_D0 +CYREG_B1_UDB05_D0 EQU 0x40006525 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_D0 +CYREG_B1_UDB06_D0 EQU 0x40006526 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_D0 +CYREG_B1_UDB07_D0 EQU 0x40006527 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_D0 +CYREG_B1_UDB08_D0 EQU 0x40006528 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_D0 +CYREG_B1_UDB09_D0 EQU 0x40006529 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_D0 +CYREG_B1_UDB10_D0 EQU 0x4000652a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_D0 +CYREG_B1_UDB11_D0 EQU 0x4000652b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_D1 +CYREG_B1_UDB04_D1 EQU 0x40006534 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_D1 +CYREG_B1_UDB05_D1 EQU 0x40006535 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_D1 +CYREG_B1_UDB06_D1 EQU 0x40006536 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_D1 +CYREG_B1_UDB07_D1 EQU 0x40006537 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_D1 +CYREG_B1_UDB08_D1 EQU 0x40006538 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_D1 +CYREG_B1_UDB09_D1 EQU 0x40006539 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_D1 +CYREG_B1_UDB10_D1 EQU 0x4000653a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_D1 +CYREG_B1_UDB11_D1 EQU 0x4000653b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_F0 +CYREG_B1_UDB04_F0 EQU 0x40006544 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_F0 +CYREG_B1_UDB05_F0 EQU 0x40006545 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_F0 +CYREG_B1_UDB06_F0 EQU 0x40006546 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_F0 +CYREG_B1_UDB07_F0 EQU 0x40006547 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_F0 +CYREG_B1_UDB08_F0 EQU 0x40006548 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_F0 +CYREG_B1_UDB09_F0 EQU 0x40006549 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_F0 +CYREG_B1_UDB10_F0 EQU 0x4000654a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_F0 +CYREG_B1_UDB11_F0 EQU 0x4000654b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_F1 +CYREG_B1_UDB04_F1 EQU 0x40006554 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_F1 +CYREG_B1_UDB05_F1 EQU 0x40006555 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_F1 +CYREG_B1_UDB06_F1 EQU 0x40006556 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_F1 +CYREG_B1_UDB07_F1 EQU 0x40006557 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_F1 +CYREG_B1_UDB08_F1 EQU 0x40006558 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_F1 +CYREG_B1_UDB09_F1 EQU 0x40006559 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_F1 +CYREG_B1_UDB10_F1 EQU 0x4000655a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_F1 +CYREG_B1_UDB11_F1 EQU 0x4000655b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_ST +CYREG_B1_UDB04_ST EQU 0x40006564 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_ST +CYREG_B1_UDB05_ST EQU 0x40006565 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_ST +CYREG_B1_UDB06_ST EQU 0x40006566 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_ST +CYREG_B1_UDB07_ST EQU 0x40006567 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_ST +CYREG_B1_UDB08_ST EQU 0x40006568 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_ST +CYREG_B1_UDB09_ST EQU 0x40006569 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_ST +CYREG_B1_UDB10_ST EQU 0x4000656a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_ST +CYREG_B1_UDB11_ST EQU 0x4000656b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_CTL +CYREG_B1_UDB04_CTL EQU 0x40006574 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_CTL +CYREG_B1_UDB05_CTL EQU 0x40006575 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_CTL +CYREG_B1_UDB06_CTL EQU 0x40006576 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_CTL +CYREG_B1_UDB07_CTL EQU 0x40006577 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_CTL +CYREG_B1_UDB08_CTL EQU 0x40006578 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_CTL +CYREG_B1_UDB09_CTL EQU 0x40006579 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_CTL +CYREG_B1_UDB10_CTL EQU 0x4000657a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_CTL +CYREG_B1_UDB11_CTL EQU 0x4000657b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MSK +CYREG_B1_UDB04_MSK EQU 0x40006584 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MSK +CYREG_B1_UDB05_MSK EQU 0x40006585 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MSK +CYREG_B1_UDB06_MSK EQU 0x40006586 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MSK +CYREG_B1_UDB07_MSK EQU 0x40006587 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MSK +CYREG_B1_UDB08_MSK EQU 0x40006588 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MSK +CYREG_B1_UDB09_MSK EQU 0x40006589 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MSK +CYREG_B1_UDB10_MSK EQU 0x4000658a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MSK +CYREG_B1_UDB11_MSK EQU 0x4000658b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_ACTL +CYREG_B1_UDB04_ACTL EQU 0x40006594 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_ACTL +CYREG_B1_UDB05_ACTL EQU 0x40006595 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_ACTL +CYREG_B1_UDB06_ACTL EQU 0x40006596 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_ACTL +CYREG_B1_UDB07_ACTL EQU 0x40006597 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_ACTL +CYREG_B1_UDB08_ACTL EQU 0x40006598 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_ACTL +CYREG_B1_UDB09_ACTL EQU 0x40006599 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_ACTL +CYREG_B1_UDB10_ACTL EQU 0x4000659a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_ACTL +CYREG_B1_UDB11_ACTL EQU 0x4000659b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MC +CYREG_B1_UDB04_MC EQU 0x400065a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MC +CYREG_B1_UDB05_MC EQU 0x400065a5 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MC +CYREG_B1_UDB06_MC EQU 0x400065a6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MC +CYREG_B1_UDB07_MC EQU 0x400065a7 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MC +CYREG_B1_UDB08_MC EQU 0x400065a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MC +CYREG_B1_UDB09_MC EQU 0x400065a9 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MC +CYREG_B1_UDB10_MC EQU 0x400065aa + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MC +CYREG_B1_UDB11_MC EQU 0x400065ab + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_BASE +CYDEV_UWRK_UWRK16_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_SIZE +CYDEV_UWRK_UWRK16_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_BASE +CYDEV_UWRK_UWRK16_CAT_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_SIZE +CYDEV_UWRK_UWRK16_CAT_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_BASE +CYDEV_UWRK_UWRK16_CAT_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_SIZE +CYDEV_UWRK_UWRK16_CAT_B0_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_A0_A1 +CYREG_B0_UDB00_A0_A1 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_A0_A1 +CYREG_B0_UDB01_A0_A1 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_A0_A1 +CYREG_B0_UDB02_A0_A1 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_A0_A1 +CYREG_B0_UDB03_A0_A1 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_A0_A1 +CYREG_B0_UDB04_A0_A1 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_A0_A1 +CYREG_B0_UDB05_A0_A1 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_A0_A1 +CYREG_B0_UDB06_A0_A1 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_A0_A1 +CYREG_B0_UDB07_A0_A1 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_A0_A1 +CYREG_B0_UDB08_A0_A1 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_A0_A1 +CYREG_B0_UDB09_A0_A1 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_A0_A1 +CYREG_B0_UDB10_A0_A1 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_A0_A1 +CYREG_B0_UDB11_A0_A1 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_A0_A1 +CYREG_B0_UDB12_A0_A1 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_A0_A1 +CYREG_B0_UDB13_A0_A1 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_A0_A1 +CYREG_B0_UDB14_A0_A1 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_A0_A1 +CYREG_B0_UDB15_A0_A1 EQU 0x4000681e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_D0_D1 +CYREG_B0_UDB00_D0_D1 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_D0_D1 +CYREG_B0_UDB01_D0_D1 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_D0_D1 +CYREG_B0_UDB02_D0_D1 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_D0_D1 +CYREG_B0_UDB03_D0_D1 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_D0_D1 +CYREG_B0_UDB04_D0_D1 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_D0_D1 +CYREG_B0_UDB05_D0_D1 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_D0_D1 +CYREG_B0_UDB06_D0_D1 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_D0_D1 +CYREG_B0_UDB07_D0_D1 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_D0_D1 +CYREG_B0_UDB08_D0_D1 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_D0_D1 +CYREG_B0_UDB09_D0_D1 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_D0_D1 +CYREG_B0_UDB10_D0_D1 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_D0_D1 +CYREG_B0_UDB11_D0_D1 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_D0_D1 +CYREG_B0_UDB12_D0_D1 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_D0_D1 +CYREG_B0_UDB13_D0_D1 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_D0_D1 +CYREG_B0_UDB14_D0_D1 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_D0_D1 +CYREG_B0_UDB15_D0_D1 EQU 0x4000685e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_F0_F1 +CYREG_B0_UDB00_F0_F1 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_F0_F1 +CYREG_B0_UDB01_F0_F1 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_F0_F1 +CYREG_B0_UDB02_F0_F1 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_F0_F1 +CYREG_B0_UDB03_F0_F1 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_F0_F1 +CYREG_B0_UDB04_F0_F1 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_F0_F1 +CYREG_B0_UDB05_F0_F1 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_F0_F1 +CYREG_B0_UDB06_F0_F1 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_F0_F1 +CYREG_B0_UDB07_F0_F1 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_F0_F1 +CYREG_B0_UDB08_F0_F1 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_F0_F1 +CYREG_B0_UDB09_F0_F1 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_F0_F1 +CYREG_B0_UDB10_F0_F1 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_F0_F1 +CYREG_B0_UDB11_F0_F1 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_F0_F1 +CYREG_B0_UDB12_F0_F1 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_F0_F1 +CYREG_B0_UDB13_F0_F1 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_F0_F1 +CYREG_B0_UDB14_F0_F1 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_F0_F1 +CYREG_B0_UDB15_F0_F1 EQU 0x4000689e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_ST_CTL +CYREG_B0_UDB00_ST_CTL EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_ST_CTL +CYREG_B0_UDB01_ST_CTL EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_ST_CTL +CYREG_B0_UDB02_ST_CTL EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_ST_CTL +CYREG_B0_UDB03_ST_CTL EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_ST_CTL +CYREG_B0_UDB04_ST_CTL EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_ST_CTL +CYREG_B0_UDB05_ST_CTL EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_ST_CTL +CYREG_B0_UDB06_ST_CTL EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_ST_CTL +CYREG_B0_UDB07_ST_CTL EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_ST_CTL +CYREG_B0_UDB08_ST_CTL EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_ST_CTL +CYREG_B0_UDB09_ST_CTL EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_ST_CTL +CYREG_B0_UDB10_ST_CTL EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_ST_CTL +CYREG_B0_UDB11_ST_CTL EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_ST_CTL +CYREG_B0_UDB12_ST_CTL EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_ST_CTL +CYREG_B0_UDB13_ST_CTL EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_ST_CTL +CYREG_B0_UDB14_ST_CTL EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_ST_CTL +CYREG_B0_UDB15_ST_CTL EQU 0x400068de + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MSK_ACTL +CYREG_B0_UDB00_MSK_ACTL EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MSK_ACTL +CYREG_B0_UDB01_MSK_ACTL EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MSK_ACTL +CYREG_B0_UDB02_MSK_ACTL EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MSK_ACTL +CYREG_B0_UDB03_MSK_ACTL EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MSK_ACTL +CYREG_B0_UDB04_MSK_ACTL EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MSK_ACTL +CYREG_B0_UDB05_MSK_ACTL EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MSK_ACTL +CYREG_B0_UDB06_MSK_ACTL EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MSK_ACTL +CYREG_B0_UDB07_MSK_ACTL EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MSK_ACTL +CYREG_B0_UDB08_MSK_ACTL EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MSK_ACTL +CYREG_B0_UDB09_MSK_ACTL EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MSK_ACTL +CYREG_B0_UDB10_MSK_ACTL EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MSK_ACTL +CYREG_B0_UDB11_MSK_ACTL EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MSK_ACTL +CYREG_B0_UDB12_MSK_ACTL EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MSK_ACTL +CYREG_B0_UDB13_MSK_ACTL EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MSK_ACTL +CYREG_B0_UDB14_MSK_ACTL EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MSK_ACTL +CYREG_B0_UDB15_MSK_ACTL EQU 0x4000691e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MC_00 +CYREG_B0_UDB00_MC_00 EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MC_00 +CYREG_B0_UDB01_MC_00 EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MC_00 +CYREG_B0_UDB02_MC_00 EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MC_00 +CYREG_B0_UDB03_MC_00 EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MC_00 +CYREG_B0_UDB04_MC_00 EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MC_00 +CYREG_B0_UDB05_MC_00 EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MC_00 +CYREG_B0_UDB06_MC_00 EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MC_00 +CYREG_B0_UDB07_MC_00 EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MC_00 +CYREG_B0_UDB08_MC_00 EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MC_00 +CYREG_B0_UDB09_MC_00 EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MC_00 +CYREG_B0_UDB10_MC_00 EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MC_00 +CYREG_B0_UDB11_MC_00 EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MC_00 +CYREG_B0_UDB12_MC_00 EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MC_00 +CYREG_B0_UDB13_MC_00 EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MC_00 +CYREG_B0_UDB14_MC_00 EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MC_00 +CYREG_B0_UDB15_MC_00 EQU 0x4000695e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_BASE +CYDEV_UWRK_UWRK16_CAT_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_SIZE +CYDEV_UWRK_UWRK16_CAT_B1_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_A0_A1 +CYREG_B1_UDB04_A0_A1 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_A0_A1 +CYREG_B1_UDB05_A0_A1 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_A0_A1 +CYREG_B1_UDB06_A0_A1 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_A0_A1 +CYREG_B1_UDB07_A0_A1 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_A0_A1 +CYREG_B1_UDB08_A0_A1 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_A0_A1 +CYREG_B1_UDB09_A0_A1 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_A0_A1 +CYREG_B1_UDB10_A0_A1 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_A0_A1 +CYREG_B1_UDB11_A0_A1 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_D0_D1 +CYREG_B1_UDB04_D0_D1 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_D0_D1 +CYREG_B1_UDB05_D0_D1 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_D0_D1 +CYREG_B1_UDB06_D0_D1 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_D0_D1 +CYREG_B1_UDB07_D0_D1 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_D0_D1 +CYREG_B1_UDB08_D0_D1 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_D0_D1 +CYREG_B1_UDB09_D0_D1 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_D0_D1 +CYREG_B1_UDB10_D0_D1 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_D0_D1 +CYREG_B1_UDB11_D0_D1 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_F0_F1 +CYREG_B1_UDB04_F0_F1 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_F0_F1 +CYREG_B1_UDB05_F0_F1 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_F0_F1 +CYREG_B1_UDB06_F0_F1 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_F0_F1 +CYREG_B1_UDB07_F0_F1 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_F0_F1 +CYREG_B1_UDB08_F0_F1 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_F0_F1 +CYREG_B1_UDB09_F0_F1 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_F0_F1 +CYREG_B1_UDB10_F0_F1 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_F0_F1 +CYREG_B1_UDB11_F0_F1 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_ST_CTL +CYREG_B1_UDB04_ST_CTL EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_ST_CTL +CYREG_B1_UDB05_ST_CTL EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_ST_CTL +CYREG_B1_UDB06_ST_CTL EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_ST_CTL +CYREG_B1_UDB07_ST_CTL EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_ST_CTL +CYREG_B1_UDB08_ST_CTL EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_ST_CTL +CYREG_B1_UDB09_ST_CTL EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_ST_CTL +CYREG_B1_UDB10_ST_CTL EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_ST_CTL +CYREG_B1_UDB11_ST_CTL EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MSK_ACTL +CYREG_B1_UDB04_MSK_ACTL EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MSK_ACTL +CYREG_B1_UDB05_MSK_ACTL EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MSK_ACTL +CYREG_B1_UDB06_MSK_ACTL EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MSK_ACTL +CYREG_B1_UDB07_MSK_ACTL EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MSK_ACTL +CYREG_B1_UDB08_MSK_ACTL EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MSK_ACTL +CYREG_B1_UDB09_MSK_ACTL EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MSK_ACTL +CYREG_B1_UDB10_MSK_ACTL EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MSK_ACTL +CYREG_B1_UDB11_MSK_ACTL EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MC_00 +CYREG_B1_UDB04_MC_00 EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MC_00 +CYREG_B1_UDB05_MC_00 EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MC_00 +CYREG_B1_UDB06_MC_00 EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MC_00 +CYREG_B1_UDB07_MC_00 EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MC_00 +CYREG_B1_UDB08_MC_00 EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MC_00 +CYREG_B1_UDB09_MC_00 EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MC_00 +CYREG_B1_UDB10_MC_00 EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MC_00 +CYREG_B1_UDB11_MC_00 EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_BASE +CYDEV_UWRK_UWRK16_DEF_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_SIZE +CYDEV_UWRK_UWRK16_DEF_SIZE EQU 0x0000075e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_BASE +CYDEV_UWRK_UWRK16_DEF_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_SIZE +CYDEV_UWRK_UWRK16_DEF_B0_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_A0 +CYREG_B0_UDB00_01_A0 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_A0 +CYREG_B0_UDB01_02_A0 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_A0 +CYREG_B0_UDB02_03_A0 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_A0 +CYREG_B0_UDB03_04_A0 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_A0 +CYREG_B0_UDB04_05_A0 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_A0 +CYREG_B0_UDB05_06_A0 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_A0 +CYREG_B0_UDB06_07_A0 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_A0 +CYREG_B0_UDB07_08_A0 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_A0 +CYREG_B0_UDB08_09_A0 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_A0 +CYREG_B0_UDB09_10_A0 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_A0 +CYREG_B0_UDB10_11_A0 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_A0 +CYREG_B0_UDB11_12_A0 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_A0 +CYREG_B0_UDB12_13_A0 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_A0 +CYREG_B0_UDB13_14_A0 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_A0 +CYREG_B0_UDB14_15_A0 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_A1 +CYREG_B0_UDB00_01_A1 EQU 0x40006820 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_A1 +CYREG_B0_UDB01_02_A1 EQU 0x40006822 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_A1 +CYREG_B0_UDB02_03_A1 EQU 0x40006824 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_A1 +CYREG_B0_UDB03_04_A1 EQU 0x40006826 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_A1 +CYREG_B0_UDB04_05_A1 EQU 0x40006828 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_A1 +CYREG_B0_UDB05_06_A1 EQU 0x4000682a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_A1 +CYREG_B0_UDB06_07_A1 EQU 0x4000682c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_A1 +CYREG_B0_UDB07_08_A1 EQU 0x4000682e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_A1 +CYREG_B0_UDB08_09_A1 EQU 0x40006830 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_A1 +CYREG_B0_UDB09_10_A1 EQU 0x40006832 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_A1 +CYREG_B0_UDB10_11_A1 EQU 0x40006834 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_A1 +CYREG_B0_UDB11_12_A1 EQU 0x40006836 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_A1 +CYREG_B0_UDB12_13_A1 EQU 0x40006838 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_A1 +CYREG_B0_UDB13_14_A1 EQU 0x4000683a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_A1 +CYREG_B0_UDB14_15_A1 EQU 0x4000683c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_D0 +CYREG_B0_UDB00_01_D0 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_D0 +CYREG_B0_UDB01_02_D0 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_D0 +CYREG_B0_UDB02_03_D0 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_D0 +CYREG_B0_UDB03_04_D0 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_D0 +CYREG_B0_UDB04_05_D0 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_D0 +CYREG_B0_UDB05_06_D0 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_D0 +CYREG_B0_UDB06_07_D0 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_D0 +CYREG_B0_UDB07_08_D0 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_D0 +CYREG_B0_UDB08_09_D0 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_D0 +CYREG_B0_UDB09_10_D0 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_D0 +CYREG_B0_UDB10_11_D0 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_D0 +CYREG_B0_UDB11_12_D0 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_D0 +CYREG_B0_UDB12_13_D0 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_D0 +CYREG_B0_UDB13_14_D0 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_D0 +CYREG_B0_UDB14_15_D0 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_D1 +CYREG_B0_UDB00_01_D1 EQU 0x40006860 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_D1 +CYREG_B0_UDB01_02_D1 EQU 0x40006862 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_D1 +CYREG_B0_UDB02_03_D1 EQU 0x40006864 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_D1 +CYREG_B0_UDB03_04_D1 EQU 0x40006866 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_D1 +CYREG_B0_UDB04_05_D1 EQU 0x40006868 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_D1 +CYREG_B0_UDB05_06_D1 EQU 0x4000686a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_D1 +CYREG_B0_UDB06_07_D1 EQU 0x4000686c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_D1 +CYREG_B0_UDB07_08_D1 EQU 0x4000686e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_D1 +CYREG_B0_UDB08_09_D1 EQU 0x40006870 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_D1 +CYREG_B0_UDB09_10_D1 EQU 0x40006872 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_D1 +CYREG_B0_UDB10_11_D1 EQU 0x40006874 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_D1 +CYREG_B0_UDB11_12_D1 EQU 0x40006876 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_D1 +CYREG_B0_UDB12_13_D1 EQU 0x40006878 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_D1 +CYREG_B0_UDB13_14_D1 EQU 0x4000687a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_D1 +CYREG_B0_UDB14_15_D1 EQU 0x4000687c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_F0 +CYREG_B0_UDB00_01_F0 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_F0 +CYREG_B0_UDB01_02_F0 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_F0 +CYREG_B0_UDB02_03_F0 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_F0 +CYREG_B0_UDB03_04_F0 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_F0 +CYREG_B0_UDB04_05_F0 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_F0 +CYREG_B0_UDB05_06_F0 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_F0 +CYREG_B0_UDB06_07_F0 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_F0 +CYREG_B0_UDB07_08_F0 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_F0 +CYREG_B0_UDB08_09_F0 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_F0 +CYREG_B0_UDB09_10_F0 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_F0 +CYREG_B0_UDB10_11_F0 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_F0 +CYREG_B0_UDB11_12_F0 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_F0 +CYREG_B0_UDB12_13_F0 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_F0 +CYREG_B0_UDB13_14_F0 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_F0 +CYREG_B0_UDB14_15_F0 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_F1 +CYREG_B0_UDB00_01_F1 EQU 0x400068a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_F1 +CYREG_B0_UDB01_02_F1 EQU 0x400068a2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_F1 +CYREG_B0_UDB02_03_F1 EQU 0x400068a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_F1 +CYREG_B0_UDB03_04_F1 EQU 0x400068a6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_F1 +CYREG_B0_UDB04_05_F1 EQU 0x400068a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_F1 +CYREG_B0_UDB05_06_F1 EQU 0x400068aa + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_F1 +CYREG_B0_UDB06_07_F1 EQU 0x400068ac + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_F1 +CYREG_B0_UDB07_08_F1 EQU 0x400068ae + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_F1 +CYREG_B0_UDB08_09_F1 EQU 0x400068b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_F1 +CYREG_B0_UDB09_10_F1 EQU 0x400068b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_F1 +CYREG_B0_UDB10_11_F1 EQU 0x400068b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_F1 +CYREG_B0_UDB11_12_F1 EQU 0x400068b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_F1 +CYREG_B0_UDB12_13_F1 EQU 0x400068b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_F1 +CYREG_B0_UDB13_14_F1 EQU 0x400068ba + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_F1 +CYREG_B0_UDB14_15_F1 EQU 0x400068bc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_ST +CYREG_B0_UDB00_01_ST EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_ST +CYREG_B0_UDB01_02_ST EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_ST +CYREG_B0_UDB02_03_ST EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_ST +CYREG_B0_UDB03_04_ST EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_ST +CYREG_B0_UDB04_05_ST EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_ST +CYREG_B0_UDB05_06_ST EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_ST +CYREG_B0_UDB06_07_ST EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_ST +CYREG_B0_UDB07_08_ST EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_ST +CYREG_B0_UDB08_09_ST EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_ST +CYREG_B0_UDB09_10_ST EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_ST +CYREG_B0_UDB10_11_ST EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_ST +CYREG_B0_UDB11_12_ST EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_ST +CYREG_B0_UDB12_13_ST EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_ST +CYREG_B0_UDB13_14_ST EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_ST +CYREG_B0_UDB14_15_ST EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_CTL +CYREG_B0_UDB00_01_CTL EQU 0x400068e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_CTL +CYREG_B0_UDB01_02_CTL EQU 0x400068e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_CTL +CYREG_B0_UDB02_03_CTL EQU 0x400068e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_CTL +CYREG_B0_UDB03_04_CTL EQU 0x400068e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_CTL +CYREG_B0_UDB04_05_CTL EQU 0x400068e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_CTL +CYREG_B0_UDB05_06_CTL EQU 0x400068ea + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_CTL +CYREG_B0_UDB06_07_CTL EQU 0x400068ec + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_CTL +CYREG_B0_UDB07_08_CTL EQU 0x400068ee + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_CTL +CYREG_B0_UDB08_09_CTL EQU 0x400068f0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_CTL +CYREG_B0_UDB09_10_CTL EQU 0x400068f2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_CTL +CYREG_B0_UDB10_11_CTL EQU 0x400068f4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_CTL +CYREG_B0_UDB11_12_CTL EQU 0x400068f6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_CTL +CYREG_B0_UDB12_13_CTL EQU 0x400068f8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_CTL +CYREG_B0_UDB13_14_CTL EQU 0x400068fa + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_CTL +CYREG_B0_UDB14_15_CTL EQU 0x400068fc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_MSK +CYREG_B0_UDB00_01_MSK EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_MSK +CYREG_B0_UDB01_02_MSK EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_MSK +CYREG_B0_UDB02_03_MSK EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_MSK +CYREG_B0_UDB03_04_MSK EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_MSK +CYREG_B0_UDB04_05_MSK EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_MSK +CYREG_B0_UDB05_06_MSK EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_MSK +CYREG_B0_UDB06_07_MSK EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_MSK +CYREG_B0_UDB07_08_MSK EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_MSK +CYREG_B0_UDB08_09_MSK EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_MSK +CYREG_B0_UDB09_10_MSK EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_MSK +CYREG_B0_UDB10_11_MSK EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_MSK +CYREG_B0_UDB11_12_MSK EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_MSK +CYREG_B0_UDB12_13_MSK EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_MSK +CYREG_B0_UDB13_14_MSK EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_MSK +CYREG_B0_UDB14_15_MSK EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_ACTL +CYREG_B0_UDB00_01_ACTL EQU 0x40006920 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_ACTL +CYREG_B0_UDB01_02_ACTL EQU 0x40006922 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_ACTL +CYREG_B0_UDB02_03_ACTL EQU 0x40006924 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_ACTL +CYREG_B0_UDB03_04_ACTL EQU 0x40006926 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_ACTL +CYREG_B0_UDB04_05_ACTL EQU 0x40006928 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_ACTL +CYREG_B0_UDB05_06_ACTL EQU 0x4000692a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_ACTL +CYREG_B0_UDB06_07_ACTL EQU 0x4000692c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_ACTL +CYREG_B0_UDB07_08_ACTL EQU 0x4000692e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_ACTL +CYREG_B0_UDB08_09_ACTL EQU 0x40006930 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_ACTL +CYREG_B0_UDB09_10_ACTL EQU 0x40006932 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_ACTL +CYREG_B0_UDB10_11_ACTL EQU 0x40006934 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_ACTL +CYREG_B0_UDB11_12_ACTL EQU 0x40006936 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_ACTL +CYREG_B0_UDB12_13_ACTL EQU 0x40006938 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_ACTL +CYREG_B0_UDB13_14_ACTL EQU 0x4000693a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_ACTL +CYREG_B0_UDB14_15_ACTL EQU 0x4000693c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_MC +CYREG_B0_UDB00_01_MC EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_MC +CYREG_B0_UDB01_02_MC EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_MC +CYREG_B0_UDB02_03_MC EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_MC +CYREG_B0_UDB03_04_MC EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_MC +CYREG_B0_UDB04_05_MC EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_MC +CYREG_B0_UDB05_06_MC EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_MC +CYREG_B0_UDB06_07_MC EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_MC +CYREG_B0_UDB07_08_MC EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_MC +CYREG_B0_UDB08_09_MC EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_MC +CYREG_B0_UDB09_10_MC EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_MC +CYREG_B0_UDB10_11_MC EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_MC +CYREG_B0_UDB11_12_MC EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_MC +CYREG_B0_UDB12_13_MC EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_MC +CYREG_B0_UDB13_14_MC EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_MC +CYREG_B0_UDB14_15_MC EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_BASE +CYDEV_UWRK_UWRK16_DEF_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_SIZE +CYDEV_UWRK_UWRK16_DEF_B1_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_A0 +CYREG_B1_UDB04_05_A0 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_A0 +CYREG_B1_UDB05_06_A0 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_A0 +CYREG_B1_UDB06_07_A0 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_A0 +CYREG_B1_UDB07_08_A0 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_A0 +CYREG_B1_UDB08_09_A0 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_A0 +CYREG_B1_UDB09_10_A0 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_A0 +CYREG_B1_UDB10_11_A0 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_A0 +CYREG_B1_UDB11_12_A0 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_A1 +CYREG_B1_UDB04_05_A1 EQU 0x40006a28 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_A1 +CYREG_B1_UDB05_06_A1 EQU 0x40006a2a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_A1 +CYREG_B1_UDB06_07_A1 EQU 0x40006a2c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_A1 +CYREG_B1_UDB07_08_A1 EQU 0x40006a2e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_A1 +CYREG_B1_UDB08_09_A1 EQU 0x40006a30 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_A1 +CYREG_B1_UDB09_10_A1 EQU 0x40006a32 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_A1 +CYREG_B1_UDB10_11_A1 EQU 0x40006a34 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_A1 +CYREG_B1_UDB11_12_A1 EQU 0x40006a36 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_D0 +CYREG_B1_UDB04_05_D0 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_D0 +CYREG_B1_UDB05_06_D0 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_D0 +CYREG_B1_UDB06_07_D0 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_D0 +CYREG_B1_UDB07_08_D0 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_D0 +CYREG_B1_UDB08_09_D0 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_D0 +CYREG_B1_UDB09_10_D0 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_D0 +CYREG_B1_UDB10_11_D0 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_D0 +CYREG_B1_UDB11_12_D0 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_D1 +CYREG_B1_UDB04_05_D1 EQU 0x40006a68 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_D1 +CYREG_B1_UDB05_06_D1 EQU 0x40006a6a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_D1 +CYREG_B1_UDB06_07_D1 EQU 0x40006a6c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_D1 +CYREG_B1_UDB07_08_D1 EQU 0x40006a6e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_D1 +CYREG_B1_UDB08_09_D1 EQU 0x40006a70 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_D1 +CYREG_B1_UDB09_10_D1 EQU 0x40006a72 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_D1 +CYREG_B1_UDB10_11_D1 EQU 0x40006a74 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_D1 +CYREG_B1_UDB11_12_D1 EQU 0x40006a76 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_F0 +CYREG_B1_UDB04_05_F0 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_F0 +CYREG_B1_UDB05_06_F0 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_F0 +CYREG_B1_UDB06_07_F0 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_F0 +CYREG_B1_UDB07_08_F0 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_F0 +CYREG_B1_UDB08_09_F0 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_F0 +CYREG_B1_UDB09_10_F0 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_F0 +CYREG_B1_UDB10_11_F0 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_F0 +CYREG_B1_UDB11_12_F0 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_F1 +CYREG_B1_UDB04_05_F1 EQU 0x40006aa8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_F1 +CYREG_B1_UDB05_06_F1 EQU 0x40006aaa + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_F1 +CYREG_B1_UDB06_07_F1 EQU 0x40006aac + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_F1 +CYREG_B1_UDB07_08_F1 EQU 0x40006aae + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_F1 +CYREG_B1_UDB08_09_F1 EQU 0x40006ab0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_F1 +CYREG_B1_UDB09_10_F1 EQU 0x40006ab2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_F1 +CYREG_B1_UDB10_11_F1 EQU 0x40006ab4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_F1 +CYREG_B1_UDB11_12_F1 EQU 0x40006ab6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_ST +CYREG_B1_UDB04_05_ST EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_ST +CYREG_B1_UDB05_06_ST EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_ST +CYREG_B1_UDB06_07_ST EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_ST +CYREG_B1_UDB07_08_ST EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_ST +CYREG_B1_UDB08_09_ST EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_ST +CYREG_B1_UDB09_10_ST EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_ST +CYREG_B1_UDB10_11_ST EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_ST +CYREG_B1_UDB11_12_ST EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_CTL +CYREG_B1_UDB04_05_CTL EQU 0x40006ae8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_CTL +CYREG_B1_UDB05_06_CTL EQU 0x40006aea + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_CTL +CYREG_B1_UDB06_07_CTL EQU 0x40006aec + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_CTL +CYREG_B1_UDB07_08_CTL EQU 0x40006aee + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_CTL +CYREG_B1_UDB08_09_CTL EQU 0x40006af0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_CTL +CYREG_B1_UDB09_10_CTL EQU 0x40006af2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_CTL +CYREG_B1_UDB10_11_CTL EQU 0x40006af4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_CTL +CYREG_B1_UDB11_12_CTL EQU 0x40006af6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_MSK +CYREG_B1_UDB04_05_MSK EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_MSK +CYREG_B1_UDB05_06_MSK EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_MSK +CYREG_B1_UDB06_07_MSK EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_MSK +CYREG_B1_UDB07_08_MSK EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_MSK +CYREG_B1_UDB08_09_MSK EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_MSK +CYREG_B1_UDB09_10_MSK EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_MSK +CYREG_B1_UDB10_11_MSK EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_MSK +CYREG_B1_UDB11_12_MSK EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_ACTL +CYREG_B1_UDB04_05_ACTL EQU 0x40006b28 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_ACTL +CYREG_B1_UDB05_06_ACTL EQU 0x40006b2a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_ACTL +CYREG_B1_UDB06_07_ACTL EQU 0x40006b2c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_ACTL +CYREG_B1_UDB07_08_ACTL EQU 0x40006b2e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_ACTL +CYREG_B1_UDB08_09_ACTL EQU 0x40006b30 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_ACTL +CYREG_B1_UDB09_10_ACTL EQU 0x40006b32 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_ACTL +CYREG_B1_UDB10_11_ACTL EQU 0x40006b34 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_ACTL +CYREG_B1_UDB11_12_ACTL EQU 0x40006b36 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_MC +CYREG_B1_UDB04_05_MC EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_MC +CYREG_B1_UDB05_06_MC EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_MC +CYREG_B1_UDB06_07_MC EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_MC +CYREG_B1_UDB07_08_MC EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_MC +CYREG_B1_UDB08_09_MC EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_MC +CYREG_B1_UDB09_10_MC EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_MC +CYREG_B1_UDB10_11_MC EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_MC +CYREG_B1_UDB11_12_MC EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_BASE +CYDEV_PHUB_BASE EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_SIZE +CYDEV_PHUB_SIZE EQU 0x00000c00 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFG +CYREG_PHUB_CFG EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_ERR +CYREG_PHUB_ERR EQU 0x40007004 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_ERR_ADR +CYREG_PHUB_ERR_ADR EQU 0x40007008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASE +CYDEV_PHUB_CH0_BASE EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_SIZE +CYDEV_PHUB_CH0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH0_BASIC_CFG +CYREG_PHUB_CH0_BASIC_CFG EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH0_ACTION +CYREG_PHUB_CH0_ACTION EQU 0x40007014 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH0_BASIC_STATUS +CYREG_PHUB_CH0_BASIC_STATUS EQU 0x40007018 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASE +CYDEV_PHUB_CH1_BASE EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_SIZE +CYDEV_PHUB_CH1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH1_BASIC_CFG +CYREG_PHUB_CH1_BASIC_CFG EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH1_ACTION +CYREG_PHUB_CH1_ACTION EQU 0x40007024 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH1_BASIC_STATUS +CYREG_PHUB_CH1_BASIC_STATUS EQU 0x40007028 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASE +CYDEV_PHUB_CH2_BASE EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_SIZE +CYDEV_PHUB_CH2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH2_BASIC_CFG +CYREG_PHUB_CH2_BASIC_CFG EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH2_ACTION +CYREG_PHUB_CH2_ACTION EQU 0x40007034 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH2_BASIC_STATUS +CYREG_PHUB_CH2_BASIC_STATUS EQU 0x40007038 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASE +CYDEV_PHUB_CH3_BASE EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_SIZE +CYDEV_PHUB_CH3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH3_BASIC_CFG +CYREG_PHUB_CH3_BASIC_CFG EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH3_ACTION +CYREG_PHUB_CH3_ACTION EQU 0x40007044 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH3_BASIC_STATUS +CYREG_PHUB_CH3_BASIC_STATUS EQU 0x40007048 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASE +CYDEV_PHUB_CH4_BASE EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_SIZE +CYDEV_PHUB_CH4_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH4_BASIC_CFG +CYREG_PHUB_CH4_BASIC_CFG EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH4_ACTION +CYREG_PHUB_CH4_ACTION EQU 0x40007054 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH4_BASIC_STATUS +CYREG_PHUB_CH4_BASIC_STATUS EQU 0x40007058 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASE +CYDEV_PHUB_CH5_BASE EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_SIZE +CYDEV_PHUB_CH5_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH5_BASIC_CFG +CYREG_PHUB_CH5_BASIC_CFG EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH5_ACTION +CYREG_PHUB_CH5_ACTION EQU 0x40007064 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH5_BASIC_STATUS +CYREG_PHUB_CH5_BASIC_STATUS EQU 0x40007068 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASE +CYDEV_PHUB_CH6_BASE EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_SIZE +CYDEV_PHUB_CH6_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH6_BASIC_CFG +CYREG_PHUB_CH6_BASIC_CFG EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH6_ACTION +CYREG_PHUB_CH6_ACTION EQU 0x40007074 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH6_BASIC_STATUS +CYREG_PHUB_CH6_BASIC_STATUS EQU 0x40007078 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASE +CYDEV_PHUB_CH7_BASE EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_SIZE +CYDEV_PHUB_CH7_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH7_BASIC_CFG +CYREG_PHUB_CH7_BASIC_CFG EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH7_ACTION +CYREG_PHUB_CH7_ACTION EQU 0x40007084 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH7_BASIC_STATUS +CYREG_PHUB_CH7_BASIC_STATUS EQU 0x40007088 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASE +CYDEV_PHUB_CH8_BASE EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_SIZE +CYDEV_PHUB_CH8_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH8_BASIC_CFG +CYREG_PHUB_CH8_BASIC_CFG EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH8_ACTION +CYREG_PHUB_CH8_ACTION EQU 0x40007094 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH8_BASIC_STATUS +CYREG_PHUB_CH8_BASIC_STATUS EQU 0x40007098 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASE +CYDEV_PHUB_CH9_BASE EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_SIZE +CYDEV_PHUB_CH9_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH9_BASIC_CFG +CYREG_PHUB_CH9_BASIC_CFG EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH9_ACTION +CYREG_PHUB_CH9_ACTION EQU 0x400070a4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH9_BASIC_STATUS +CYREG_PHUB_CH9_BASIC_STATUS EQU 0x400070a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASE +CYDEV_PHUB_CH10_BASE EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_SIZE +CYDEV_PHUB_CH10_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH10_BASIC_CFG +CYREG_PHUB_CH10_BASIC_CFG EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH10_ACTION +CYREG_PHUB_CH10_ACTION EQU 0x400070b4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH10_BASIC_STATUS +CYREG_PHUB_CH10_BASIC_STATUS EQU 0x400070b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASE +CYDEV_PHUB_CH11_BASE EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_SIZE +CYDEV_PHUB_CH11_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH11_BASIC_CFG +CYREG_PHUB_CH11_BASIC_CFG EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH11_ACTION +CYREG_PHUB_CH11_ACTION EQU 0x400070c4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH11_BASIC_STATUS +CYREG_PHUB_CH11_BASIC_STATUS EQU 0x400070c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASE +CYDEV_PHUB_CH12_BASE EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_SIZE +CYDEV_PHUB_CH12_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH12_BASIC_CFG +CYREG_PHUB_CH12_BASIC_CFG EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH12_ACTION +CYREG_PHUB_CH12_ACTION EQU 0x400070d4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH12_BASIC_STATUS +CYREG_PHUB_CH12_BASIC_STATUS EQU 0x400070d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASE +CYDEV_PHUB_CH13_BASE EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_SIZE +CYDEV_PHUB_CH13_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH13_BASIC_CFG +CYREG_PHUB_CH13_BASIC_CFG EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH13_ACTION +CYREG_PHUB_CH13_ACTION EQU 0x400070e4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH13_BASIC_STATUS +CYREG_PHUB_CH13_BASIC_STATUS EQU 0x400070e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASE +CYDEV_PHUB_CH14_BASE EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_SIZE +CYDEV_PHUB_CH14_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH14_BASIC_CFG +CYREG_PHUB_CH14_BASIC_CFG EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH14_ACTION +CYREG_PHUB_CH14_ACTION EQU 0x400070f4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH14_BASIC_STATUS +CYREG_PHUB_CH14_BASIC_STATUS EQU 0x400070f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASE +CYDEV_PHUB_CH15_BASE EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_SIZE +CYDEV_PHUB_CH15_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH15_BASIC_CFG +CYREG_PHUB_CH15_BASIC_CFG EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH15_ACTION +CYREG_PHUB_CH15_ACTION EQU 0x40007104 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH15_BASIC_STATUS +CYREG_PHUB_CH15_BASIC_STATUS EQU 0x40007108 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASE +CYDEV_PHUB_CH16_BASE EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_SIZE +CYDEV_PHUB_CH16_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH16_BASIC_CFG +CYREG_PHUB_CH16_BASIC_CFG EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH16_ACTION +CYREG_PHUB_CH16_ACTION EQU 0x40007114 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH16_BASIC_STATUS +CYREG_PHUB_CH16_BASIC_STATUS EQU 0x40007118 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASE +CYDEV_PHUB_CH17_BASE EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_SIZE +CYDEV_PHUB_CH17_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH17_BASIC_CFG +CYREG_PHUB_CH17_BASIC_CFG EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH17_ACTION +CYREG_PHUB_CH17_ACTION EQU 0x40007124 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH17_BASIC_STATUS +CYREG_PHUB_CH17_BASIC_STATUS EQU 0x40007128 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASE +CYDEV_PHUB_CH18_BASE EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_SIZE +CYDEV_PHUB_CH18_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH18_BASIC_CFG +CYREG_PHUB_CH18_BASIC_CFG EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH18_ACTION +CYREG_PHUB_CH18_ACTION EQU 0x40007134 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH18_BASIC_STATUS +CYREG_PHUB_CH18_BASIC_STATUS EQU 0x40007138 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASE +CYDEV_PHUB_CH19_BASE EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_SIZE +CYDEV_PHUB_CH19_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH19_BASIC_CFG +CYREG_PHUB_CH19_BASIC_CFG EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH19_ACTION +CYREG_PHUB_CH19_ACTION EQU 0x40007144 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH19_BASIC_STATUS +CYREG_PHUB_CH19_BASIC_STATUS EQU 0x40007148 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASE +CYDEV_PHUB_CH20_BASE EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_SIZE +CYDEV_PHUB_CH20_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH20_BASIC_CFG +CYREG_PHUB_CH20_BASIC_CFG EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH20_ACTION +CYREG_PHUB_CH20_ACTION EQU 0x40007154 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH20_BASIC_STATUS +CYREG_PHUB_CH20_BASIC_STATUS EQU 0x40007158 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASE +CYDEV_PHUB_CH21_BASE EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_SIZE +CYDEV_PHUB_CH21_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH21_BASIC_CFG +CYREG_PHUB_CH21_BASIC_CFG EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH21_ACTION +CYREG_PHUB_CH21_ACTION EQU 0x40007164 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH21_BASIC_STATUS +CYREG_PHUB_CH21_BASIC_STATUS EQU 0x40007168 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASE +CYDEV_PHUB_CH22_BASE EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_SIZE +CYDEV_PHUB_CH22_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH22_BASIC_CFG +CYREG_PHUB_CH22_BASIC_CFG EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH22_ACTION +CYREG_PHUB_CH22_ACTION EQU 0x40007174 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH22_BASIC_STATUS +CYREG_PHUB_CH22_BASIC_STATUS EQU 0x40007178 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASE +CYDEV_PHUB_CH23_BASE EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_SIZE +CYDEV_PHUB_CH23_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH23_BASIC_CFG +CYREG_PHUB_CH23_BASIC_CFG EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH23_ACTION +CYREG_PHUB_CH23_ACTION EQU 0x40007184 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH23_BASIC_STATUS +CYREG_PHUB_CH23_BASIC_STATUS EQU 0x40007188 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_BASE +CYDEV_PHUB_CFGMEM0_BASE EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_SIZE +CYDEV_PHUB_CFGMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM0_CFG0 +CYREG_PHUB_CFGMEM0_CFG0 EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM0_CFG1 +CYREG_PHUB_CFGMEM0_CFG1 EQU 0x40007604 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_BASE +CYDEV_PHUB_CFGMEM1_BASE EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_SIZE +CYDEV_PHUB_CFGMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM1_CFG0 +CYREG_PHUB_CFGMEM1_CFG0 EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM1_CFG1 +CYREG_PHUB_CFGMEM1_CFG1 EQU 0x4000760c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_BASE +CYDEV_PHUB_CFGMEM2_BASE EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_SIZE +CYDEV_PHUB_CFGMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM2_CFG0 +CYREG_PHUB_CFGMEM2_CFG0 EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM2_CFG1 +CYREG_PHUB_CFGMEM2_CFG1 EQU 0x40007614 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_BASE +CYDEV_PHUB_CFGMEM3_BASE EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_SIZE +CYDEV_PHUB_CFGMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM3_CFG0 +CYREG_PHUB_CFGMEM3_CFG0 EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM3_CFG1 +CYREG_PHUB_CFGMEM3_CFG1 EQU 0x4000761c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_BASE +CYDEV_PHUB_CFGMEM4_BASE EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_SIZE +CYDEV_PHUB_CFGMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM4_CFG0 +CYREG_PHUB_CFGMEM4_CFG0 EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM4_CFG1 +CYREG_PHUB_CFGMEM4_CFG1 EQU 0x40007624 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_BASE +CYDEV_PHUB_CFGMEM5_BASE EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_SIZE +CYDEV_PHUB_CFGMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM5_CFG0 +CYREG_PHUB_CFGMEM5_CFG0 EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM5_CFG1 +CYREG_PHUB_CFGMEM5_CFG1 EQU 0x4000762c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_BASE +CYDEV_PHUB_CFGMEM6_BASE EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_SIZE +CYDEV_PHUB_CFGMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM6_CFG0 +CYREG_PHUB_CFGMEM6_CFG0 EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM6_CFG1 +CYREG_PHUB_CFGMEM6_CFG1 EQU 0x40007634 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_BASE +CYDEV_PHUB_CFGMEM7_BASE EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_SIZE +CYDEV_PHUB_CFGMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM7_CFG0 +CYREG_PHUB_CFGMEM7_CFG0 EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM7_CFG1 +CYREG_PHUB_CFGMEM7_CFG1 EQU 0x4000763c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_BASE +CYDEV_PHUB_CFGMEM8_BASE EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_SIZE +CYDEV_PHUB_CFGMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM8_CFG0 +CYREG_PHUB_CFGMEM8_CFG0 EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM8_CFG1 +CYREG_PHUB_CFGMEM8_CFG1 EQU 0x40007644 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_BASE +CYDEV_PHUB_CFGMEM9_BASE EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_SIZE +CYDEV_PHUB_CFGMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM9_CFG0 +CYREG_PHUB_CFGMEM9_CFG0 EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM9_CFG1 +CYREG_PHUB_CFGMEM9_CFG1 EQU 0x4000764c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_BASE +CYDEV_PHUB_CFGMEM10_BASE EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_SIZE +CYDEV_PHUB_CFGMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM10_CFG0 +CYREG_PHUB_CFGMEM10_CFG0 EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM10_CFG1 +CYREG_PHUB_CFGMEM10_CFG1 EQU 0x40007654 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_BASE +CYDEV_PHUB_CFGMEM11_BASE EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_SIZE +CYDEV_PHUB_CFGMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM11_CFG0 +CYREG_PHUB_CFGMEM11_CFG0 EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM11_CFG1 +CYREG_PHUB_CFGMEM11_CFG1 EQU 0x4000765c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_BASE +CYDEV_PHUB_CFGMEM12_BASE EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_SIZE +CYDEV_PHUB_CFGMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM12_CFG0 +CYREG_PHUB_CFGMEM12_CFG0 EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM12_CFG1 +CYREG_PHUB_CFGMEM12_CFG1 EQU 0x40007664 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_BASE +CYDEV_PHUB_CFGMEM13_BASE EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_SIZE +CYDEV_PHUB_CFGMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM13_CFG0 +CYREG_PHUB_CFGMEM13_CFG0 EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM13_CFG1 +CYREG_PHUB_CFGMEM13_CFG1 EQU 0x4000766c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_BASE +CYDEV_PHUB_CFGMEM14_BASE EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_SIZE +CYDEV_PHUB_CFGMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM14_CFG0 +CYREG_PHUB_CFGMEM14_CFG0 EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM14_CFG1 +CYREG_PHUB_CFGMEM14_CFG1 EQU 0x40007674 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_BASE +CYDEV_PHUB_CFGMEM15_BASE EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_SIZE +CYDEV_PHUB_CFGMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM15_CFG0 +CYREG_PHUB_CFGMEM15_CFG0 EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM15_CFG1 +CYREG_PHUB_CFGMEM15_CFG1 EQU 0x4000767c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_BASE +CYDEV_PHUB_CFGMEM16_BASE EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_SIZE +CYDEV_PHUB_CFGMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM16_CFG0 +CYREG_PHUB_CFGMEM16_CFG0 EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM16_CFG1 +CYREG_PHUB_CFGMEM16_CFG1 EQU 0x40007684 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_BASE +CYDEV_PHUB_CFGMEM17_BASE EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_SIZE +CYDEV_PHUB_CFGMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM17_CFG0 +CYREG_PHUB_CFGMEM17_CFG0 EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM17_CFG1 +CYREG_PHUB_CFGMEM17_CFG1 EQU 0x4000768c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_BASE +CYDEV_PHUB_CFGMEM18_BASE EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_SIZE +CYDEV_PHUB_CFGMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM18_CFG0 +CYREG_PHUB_CFGMEM18_CFG0 EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM18_CFG1 +CYREG_PHUB_CFGMEM18_CFG1 EQU 0x40007694 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_BASE +CYDEV_PHUB_CFGMEM19_BASE EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_SIZE +CYDEV_PHUB_CFGMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM19_CFG0 +CYREG_PHUB_CFGMEM19_CFG0 EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM19_CFG1 +CYREG_PHUB_CFGMEM19_CFG1 EQU 0x4000769c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_BASE +CYDEV_PHUB_CFGMEM20_BASE EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_SIZE +CYDEV_PHUB_CFGMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM20_CFG0 +CYREG_PHUB_CFGMEM20_CFG0 EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM20_CFG1 +CYREG_PHUB_CFGMEM20_CFG1 EQU 0x400076a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_BASE +CYDEV_PHUB_CFGMEM21_BASE EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_SIZE +CYDEV_PHUB_CFGMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM21_CFG0 +CYREG_PHUB_CFGMEM21_CFG0 EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM21_CFG1 +CYREG_PHUB_CFGMEM21_CFG1 EQU 0x400076ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_BASE +CYDEV_PHUB_CFGMEM22_BASE EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_SIZE +CYDEV_PHUB_CFGMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM22_CFG0 +CYREG_PHUB_CFGMEM22_CFG0 EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM22_CFG1 +CYREG_PHUB_CFGMEM22_CFG1 EQU 0x400076b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_BASE +CYDEV_PHUB_CFGMEM23_BASE EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_SIZE +CYDEV_PHUB_CFGMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM23_CFG0 +CYREG_PHUB_CFGMEM23_CFG0 EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM23_CFG1 +CYREG_PHUB_CFGMEM23_CFG1 EQU 0x400076bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_BASE +CYDEV_PHUB_TDMEM0_BASE EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_SIZE +CYDEV_PHUB_TDMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM0_ORIG_TD0 +CYREG_PHUB_TDMEM0_ORIG_TD0 EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM0_ORIG_TD1 +CYREG_PHUB_TDMEM0_ORIG_TD1 EQU 0x40007804 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_BASE +CYDEV_PHUB_TDMEM1_BASE EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_SIZE +CYDEV_PHUB_TDMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM1_ORIG_TD0 +CYREG_PHUB_TDMEM1_ORIG_TD0 EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM1_ORIG_TD1 +CYREG_PHUB_TDMEM1_ORIG_TD1 EQU 0x4000780c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_BASE +CYDEV_PHUB_TDMEM2_BASE EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_SIZE +CYDEV_PHUB_TDMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM2_ORIG_TD0 +CYREG_PHUB_TDMEM2_ORIG_TD0 EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM2_ORIG_TD1 +CYREG_PHUB_TDMEM2_ORIG_TD1 EQU 0x40007814 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_BASE +CYDEV_PHUB_TDMEM3_BASE EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_SIZE +CYDEV_PHUB_TDMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM3_ORIG_TD0 +CYREG_PHUB_TDMEM3_ORIG_TD0 EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM3_ORIG_TD1 +CYREG_PHUB_TDMEM3_ORIG_TD1 EQU 0x4000781c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_BASE +CYDEV_PHUB_TDMEM4_BASE EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_SIZE +CYDEV_PHUB_TDMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM4_ORIG_TD0 +CYREG_PHUB_TDMEM4_ORIG_TD0 EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM4_ORIG_TD1 +CYREG_PHUB_TDMEM4_ORIG_TD1 EQU 0x40007824 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_BASE +CYDEV_PHUB_TDMEM5_BASE EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_SIZE +CYDEV_PHUB_TDMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM5_ORIG_TD0 +CYREG_PHUB_TDMEM5_ORIG_TD0 EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM5_ORIG_TD1 +CYREG_PHUB_TDMEM5_ORIG_TD1 EQU 0x4000782c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_BASE +CYDEV_PHUB_TDMEM6_BASE EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_SIZE +CYDEV_PHUB_TDMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM6_ORIG_TD0 +CYREG_PHUB_TDMEM6_ORIG_TD0 EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM6_ORIG_TD1 +CYREG_PHUB_TDMEM6_ORIG_TD1 EQU 0x40007834 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_BASE +CYDEV_PHUB_TDMEM7_BASE EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_SIZE +CYDEV_PHUB_TDMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM7_ORIG_TD0 +CYREG_PHUB_TDMEM7_ORIG_TD0 EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM7_ORIG_TD1 +CYREG_PHUB_TDMEM7_ORIG_TD1 EQU 0x4000783c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_BASE +CYDEV_PHUB_TDMEM8_BASE EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_SIZE +CYDEV_PHUB_TDMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM8_ORIG_TD0 +CYREG_PHUB_TDMEM8_ORIG_TD0 EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM8_ORIG_TD1 +CYREG_PHUB_TDMEM8_ORIG_TD1 EQU 0x40007844 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_BASE +CYDEV_PHUB_TDMEM9_BASE EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_SIZE +CYDEV_PHUB_TDMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM9_ORIG_TD0 +CYREG_PHUB_TDMEM9_ORIG_TD0 EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM9_ORIG_TD1 +CYREG_PHUB_TDMEM9_ORIG_TD1 EQU 0x4000784c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_BASE +CYDEV_PHUB_TDMEM10_BASE EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_SIZE +CYDEV_PHUB_TDMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM10_ORIG_TD0 +CYREG_PHUB_TDMEM10_ORIG_TD0 EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM10_ORIG_TD1 +CYREG_PHUB_TDMEM10_ORIG_TD1 EQU 0x40007854 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_BASE +CYDEV_PHUB_TDMEM11_BASE EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_SIZE +CYDEV_PHUB_TDMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM11_ORIG_TD0 +CYREG_PHUB_TDMEM11_ORIG_TD0 EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM11_ORIG_TD1 +CYREG_PHUB_TDMEM11_ORIG_TD1 EQU 0x4000785c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_BASE +CYDEV_PHUB_TDMEM12_BASE EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_SIZE +CYDEV_PHUB_TDMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM12_ORIG_TD0 +CYREG_PHUB_TDMEM12_ORIG_TD0 EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM12_ORIG_TD1 +CYREG_PHUB_TDMEM12_ORIG_TD1 EQU 0x40007864 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_BASE +CYDEV_PHUB_TDMEM13_BASE EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_SIZE +CYDEV_PHUB_TDMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM13_ORIG_TD0 +CYREG_PHUB_TDMEM13_ORIG_TD0 EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM13_ORIG_TD1 +CYREG_PHUB_TDMEM13_ORIG_TD1 EQU 0x4000786c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_BASE +CYDEV_PHUB_TDMEM14_BASE EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_SIZE +CYDEV_PHUB_TDMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM14_ORIG_TD0 +CYREG_PHUB_TDMEM14_ORIG_TD0 EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM14_ORIG_TD1 +CYREG_PHUB_TDMEM14_ORIG_TD1 EQU 0x40007874 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_BASE +CYDEV_PHUB_TDMEM15_BASE EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_SIZE +CYDEV_PHUB_TDMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM15_ORIG_TD0 +CYREG_PHUB_TDMEM15_ORIG_TD0 EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM15_ORIG_TD1 +CYREG_PHUB_TDMEM15_ORIG_TD1 EQU 0x4000787c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_BASE +CYDEV_PHUB_TDMEM16_BASE EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_SIZE +CYDEV_PHUB_TDMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM16_ORIG_TD0 +CYREG_PHUB_TDMEM16_ORIG_TD0 EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM16_ORIG_TD1 +CYREG_PHUB_TDMEM16_ORIG_TD1 EQU 0x40007884 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_BASE +CYDEV_PHUB_TDMEM17_BASE EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_SIZE +CYDEV_PHUB_TDMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM17_ORIG_TD0 +CYREG_PHUB_TDMEM17_ORIG_TD0 EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM17_ORIG_TD1 +CYREG_PHUB_TDMEM17_ORIG_TD1 EQU 0x4000788c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_BASE +CYDEV_PHUB_TDMEM18_BASE EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_SIZE +CYDEV_PHUB_TDMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM18_ORIG_TD0 +CYREG_PHUB_TDMEM18_ORIG_TD0 EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM18_ORIG_TD1 +CYREG_PHUB_TDMEM18_ORIG_TD1 EQU 0x40007894 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_BASE +CYDEV_PHUB_TDMEM19_BASE EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_SIZE +CYDEV_PHUB_TDMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM19_ORIG_TD0 +CYREG_PHUB_TDMEM19_ORIG_TD0 EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM19_ORIG_TD1 +CYREG_PHUB_TDMEM19_ORIG_TD1 EQU 0x4000789c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_BASE +CYDEV_PHUB_TDMEM20_BASE EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_SIZE +CYDEV_PHUB_TDMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM20_ORIG_TD0 +CYREG_PHUB_TDMEM20_ORIG_TD0 EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM20_ORIG_TD1 +CYREG_PHUB_TDMEM20_ORIG_TD1 EQU 0x400078a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_BASE +CYDEV_PHUB_TDMEM21_BASE EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_SIZE +CYDEV_PHUB_TDMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM21_ORIG_TD0 +CYREG_PHUB_TDMEM21_ORIG_TD0 EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM21_ORIG_TD1 +CYREG_PHUB_TDMEM21_ORIG_TD1 EQU 0x400078ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_BASE +CYDEV_PHUB_TDMEM22_BASE EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_SIZE +CYDEV_PHUB_TDMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM22_ORIG_TD0 +CYREG_PHUB_TDMEM22_ORIG_TD0 EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM22_ORIG_TD1 +CYREG_PHUB_TDMEM22_ORIG_TD1 EQU 0x400078b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_BASE +CYDEV_PHUB_TDMEM23_BASE EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_SIZE +CYDEV_PHUB_TDMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM23_ORIG_TD0 +CYREG_PHUB_TDMEM23_ORIG_TD0 EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM23_ORIG_TD1 +CYREG_PHUB_TDMEM23_ORIG_TD1 EQU 0x400078bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_BASE +CYDEV_PHUB_TDMEM24_BASE EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_SIZE +CYDEV_PHUB_TDMEM24_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM24_ORIG_TD0 +CYREG_PHUB_TDMEM24_ORIG_TD0 EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM24_ORIG_TD1 +CYREG_PHUB_TDMEM24_ORIG_TD1 EQU 0x400078c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_BASE +CYDEV_PHUB_TDMEM25_BASE EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_SIZE +CYDEV_PHUB_TDMEM25_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM25_ORIG_TD0 +CYREG_PHUB_TDMEM25_ORIG_TD0 EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM25_ORIG_TD1 +CYREG_PHUB_TDMEM25_ORIG_TD1 EQU 0x400078cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_BASE +CYDEV_PHUB_TDMEM26_BASE EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_SIZE +CYDEV_PHUB_TDMEM26_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM26_ORIG_TD0 +CYREG_PHUB_TDMEM26_ORIG_TD0 EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM26_ORIG_TD1 +CYREG_PHUB_TDMEM26_ORIG_TD1 EQU 0x400078d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_BASE +CYDEV_PHUB_TDMEM27_BASE EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_SIZE +CYDEV_PHUB_TDMEM27_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM27_ORIG_TD0 +CYREG_PHUB_TDMEM27_ORIG_TD0 EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM27_ORIG_TD1 +CYREG_PHUB_TDMEM27_ORIG_TD1 EQU 0x400078dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_BASE +CYDEV_PHUB_TDMEM28_BASE EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_SIZE +CYDEV_PHUB_TDMEM28_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM28_ORIG_TD0 +CYREG_PHUB_TDMEM28_ORIG_TD0 EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM28_ORIG_TD1 +CYREG_PHUB_TDMEM28_ORIG_TD1 EQU 0x400078e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_BASE +CYDEV_PHUB_TDMEM29_BASE EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_SIZE +CYDEV_PHUB_TDMEM29_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM29_ORIG_TD0 +CYREG_PHUB_TDMEM29_ORIG_TD0 EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM29_ORIG_TD1 +CYREG_PHUB_TDMEM29_ORIG_TD1 EQU 0x400078ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_BASE +CYDEV_PHUB_TDMEM30_BASE EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_SIZE +CYDEV_PHUB_TDMEM30_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM30_ORIG_TD0 +CYREG_PHUB_TDMEM30_ORIG_TD0 EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM30_ORIG_TD1 +CYREG_PHUB_TDMEM30_ORIG_TD1 EQU 0x400078f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_BASE +CYDEV_PHUB_TDMEM31_BASE EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_SIZE +CYDEV_PHUB_TDMEM31_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM31_ORIG_TD0 +CYREG_PHUB_TDMEM31_ORIG_TD0 EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM31_ORIG_TD1 +CYREG_PHUB_TDMEM31_ORIG_TD1 EQU 0x400078fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_BASE +CYDEV_PHUB_TDMEM32_BASE EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_SIZE +CYDEV_PHUB_TDMEM32_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM32_ORIG_TD0 +CYREG_PHUB_TDMEM32_ORIG_TD0 EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM32_ORIG_TD1 +CYREG_PHUB_TDMEM32_ORIG_TD1 EQU 0x40007904 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_BASE +CYDEV_PHUB_TDMEM33_BASE EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_SIZE +CYDEV_PHUB_TDMEM33_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM33_ORIG_TD0 +CYREG_PHUB_TDMEM33_ORIG_TD0 EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM33_ORIG_TD1 +CYREG_PHUB_TDMEM33_ORIG_TD1 EQU 0x4000790c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_BASE +CYDEV_PHUB_TDMEM34_BASE EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_SIZE +CYDEV_PHUB_TDMEM34_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM34_ORIG_TD0 +CYREG_PHUB_TDMEM34_ORIG_TD0 EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM34_ORIG_TD1 +CYREG_PHUB_TDMEM34_ORIG_TD1 EQU 0x40007914 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_BASE +CYDEV_PHUB_TDMEM35_BASE EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_SIZE +CYDEV_PHUB_TDMEM35_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM35_ORIG_TD0 +CYREG_PHUB_TDMEM35_ORIG_TD0 EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM35_ORIG_TD1 +CYREG_PHUB_TDMEM35_ORIG_TD1 EQU 0x4000791c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_BASE +CYDEV_PHUB_TDMEM36_BASE EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_SIZE +CYDEV_PHUB_TDMEM36_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM36_ORIG_TD0 +CYREG_PHUB_TDMEM36_ORIG_TD0 EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM36_ORIG_TD1 +CYREG_PHUB_TDMEM36_ORIG_TD1 EQU 0x40007924 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_BASE +CYDEV_PHUB_TDMEM37_BASE EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_SIZE +CYDEV_PHUB_TDMEM37_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM37_ORIG_TD0 +CYREG_PHUB_TDMEM37_ORIG_TD0 EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM37_ORIG_TD1 +CYREG_PHUB_TDMEM37_ORIG_TD1 EQU 0x4000792c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_BASE +CYDEV_PHUB_TDMEM38_BASE EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_SIZE +CYDEV_PHUB_TDMEM38_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM38_ORIG_TD0 +CYREG_PHUB_TDMEM38_ORIG_TD0 EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM38_ORIG_TD1 +CYREG_PHUB_TDMEM38_ORIG_TD1 EQU 0x40007934 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_BASE +CYDEV_PHUB_TDMEM39_BASE EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_SIZE +CYDEV_PHUB_TDMEM39_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM39_ORIG_TD0 +CYREG_PHUB_TDMEM39_ORIG_TD0 EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM39_ORIG_TD1 +CYREG_PHUB_TDMEM39_ORIG_TD1 EQU 0x4000793c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_BASE +CYDEV_PHUB_TDMEM40_BASE EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_SIZE +CYDEV_PHUB_TDMEM40_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM40_ORIG_TD0 +CYREG_PHUB_TDMEM40_ORIG_TD0 EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM40_ORIG_TD1 +CYREG_PHUB_TDMEM40_ORIG_TD1 EQU 0x40007944 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_BASE +CYDEV_PHUB_TDMEM41_BASE EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_SIZE +CYDEV_PHUB_TDMEM41_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM41_ORIG_TD0 +CYREG_PHUB_TDMEM41_ORIG_TD0 EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM41_ORIG_TD1 +CYREG_PHUB_TDMEM41_ORIG_TD1 EQU 0x4000794c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_BASE +CYDEV_PHUB_TDMEM42_BASE EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_SIZE +CYDEV_PHUB_TDMEM42_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM42_ORIG_TD0 +CYREG_PHUB_TDMEM42_ORIG_TD0 EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM42_ORIG_TD1 +CYREG_PHUB_TDMEM42_ORIG_TD1 EQU 0x40007954 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_BASE +CYDEV_PHUB_TDMEM43_BASE EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_SIZE +CYDEV_PHUB_TDMEM43_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM43_ORIG_TD0 +CYREG_PHUB_TDMEM43_ORIG_TD0 EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM43_ORIG_TD1 +CYREG_PHUB_TDMEM43_ORIG_TD1 EQU 0x4000795c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_BASE +CYDEV_PHUB_TDMEM44_BASE EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_SIZE +CYDEV_PHUB_TDMEM44_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM44_ORIG_TD0 +CYREG_PHUB_TDMEM44_ORIG_TD0 EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM44_ORIG_TD1 +CYREG_PHUB_TDMEM44_ORIG_TD1 EQU 0x40007964 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_BASE +CYDEV_PHUB_TDMEM45_BASE EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_SIZE +CYDEV_PHUB_TDMEM45_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM45_ORIG_TD0 +CYREG_PHUB_TDMEM45_ORIG_TD0 EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM45_ORIG_TD1 +CYREG_PHUB_TDMEM45_ORIG_TD1 EQU 0x4000796c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_BASE +CYDEV_PHUB_TDMEM46_BASE EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_SIZE +CYDEV_PHUB_TDMEM46_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM46_ORIG_TD0 +CYREG_PHUB_TDMEM46_ORIG_TD0 EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM46_ORIG_TD1 +CYREG_PHUB_TDMEM46_ORIG_TD1 EQU 0x40007974 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_BASE +CYDEV_PHUB_TDMEM47_BASE EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_SIZE +CYDEV_PHUB_TDMEM47_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM47_ORIG_TD0 +CYREG_PHUB_TDMEM47_ORIG_TD0 EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM47_ORIG_TD1 +CYREG_PHUB_TDMEM47_ORIG_TD1 EQU 0x4000797c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_BASE +CYDEV_PHUB_TDMEM48_BASE EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_SIZE +CYDEV_PHUB_TDMEM48_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM48_ORIG_TD0 +CYREG_PHUB_TDMEM48_ORIG_TD0 EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM48_ORIG_TD1 +CYREG_PHUB_TDMEM48_ORIG_TD1 EQU 0x40007984 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_BASE +CYDEV_PHUB_TDMEM49_BASE EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_SIZE +CYDEV_PHUB_TDMEM49_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM49_ORIG_TD0 +CYREG_PHUB_TDMEM49_ORIG_TD0 EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM49_ORIG_TD1 +CYREG_PHUB_TDMEM49_ORIG_TD1 EQU 0x4000798c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_BASE +CYDEV_PHUB_TDMEM50_BASE EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_SIZE +CYDEV_PHUB_TDMEM50_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM50_ORIG_TD0 +CYREG_PHUB_TDMEM50_ORIG_TD0 EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM50_ORIG_TD1 +CYREG_PHUB_TDMEM50_ORIG_TD1 EQU 0x40007994 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_BASE +CYDEV_PHUB_TDMEM51_BASE EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_SIZE +CYDEV_PHUB_TDMEM51_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM51_ORIG_TD0 +CYREG_PHUB_TDMEM51_ORIG_TD0 EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM51_ORIG_TD1 +CYREG_PHUB_TDMEM51_ORIG_TD1 EQU 0x4000799c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_BASE +CYDEV_PHUB_TDMEM52_BASE EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_SIZE +CYDEV_PHUB_TDMEM52_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM52_ORIG_TD0 +CYREG_PHUB_TDMEM52_ORIG_TD0 EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM52_ORIG_TD1 +CYREG_PHUB_TDMEM52_ORIG_TD1 EQU 0x400079a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_BASE +CYDEV_PHUB_TDMEM53_BASE EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_SIZE +CYDEV_PHUB_TDMEM53_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM53_ORIG_TD0 +CYREG_PHUB_TDMEM53_ORIG_TD0 EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM53_ORIG_TD1 +CYREG_PHUB_TDMEM53_ORIG_TD1 EQU 0x400079ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_BASE +CYDEV_PHUB_TDMEM54_BASE EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_SIZE +CYDEV_PHUB_TDMEM54_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM54_ORIG_TD0 +CYREG_PHUB_TDMEM54_ORIG_TD0 EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM54_ORIG_TD1 +CYREG_PHUB_TDMEM54_ORIG_TD1 EQU 0x400079b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_BASE +CYDEV_PHUB_TDMEM55_BASE EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_SIZE +CYDEV_PHUB_TDMEM55_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM55_ORIG_TD0 +CYREG_PHUB_TDMEM55_ORIG_TD0 EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM55_ORIG_TD1 +CYREG_PHUB_TDMEM55_ORIG_TD1 EQU 0x400079bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_BASE +CYDEV_PHUB_TDMEM56_BASE EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_SIZE +CYDEV_PHUB_TDMEM56_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM56_ORIG_TD0 +CYREG_PHUB_TDMEM56_ORIG_TD0 EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM56_ORIG_TD1 +CYREG_PHUB_TDMEM56_ORIG_TD1 EQU 0x400079c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_BASE +CYDEV_PHUB_TDMEM57_BASE EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_SIZE +CYDEV_PHUB_TDMEM57_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM57_ORIG_TD0 +CYREG_PHUB_TDMEM57_ORIG_TD0 EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM57_ORIG_TD1 +CYREG_PHUB_TDMEM57_ORIG_TD1 EQU 0x400079cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_BASE +CYDEV_PHUB_TDMEM58_BASE EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_SIZE +CYDEV_PHUB_TDMEM58_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM58_ORIG_TD0 +CYREG_PHUB_TDMEM58_ORIG_TD0 EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM58_ORIG_TD1 +CYREG_PHUB_TDMEM58_ORIG_TD1 EQU 0x400079d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_BASE +CYDEV_PHUB_TDMEM59_BASE EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_SIZE +CYDEV_PHUB_TDMEM59_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM59_ORIG_TD0 +CYREG_PHUB_TDMEM59_ORIG_TD0 EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM59_ORIG_TD1 +CYREG_PHUB_TDMEM59_ORIG_TD1 EQU 0x400079dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_BASE +CYDEV_PHUB_TDMEM60_BASE EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_SIZE +CYDEV_PHUB_TDMEM60_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM60_ORIG_TD0 +CYREG_PHUB_TDMEM60_ORIG_TD0 EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM60_ORIG_TD1 +CYREG_PHUB_TDMEM60_ORIG_TD1 EQU 0x400079e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_BASE +CYDEV_PHUB_TDMEM61_BASE EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_SIZE +CYDEV_PHUB_TDMEM61_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM61_ORIG_TD0 +CYREG_PHUB_TDMEM61_ORIG_TD0 EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM61_ORIG_TD1 +CYREG_PHUB_TDMEM61_ORIG_TD1 EQU 0x400079ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_BASE +CYDEV_PHUB_TDMEM62_BASE EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_SIZE +CYDEV_PHUB_TDMEM62_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM62_ORIG_TD0 +CYREG_PHUB_TDMEM62_ORIG_TD0 EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM62_ORIG_TD1 +CYREG_PHUB_TDMEM62_ORIG_TD1 EQU 0x400079f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_BASE +CYDEV_PHUB_TDMEM63_BASE EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_SIZE +CYDEV_PHUB_TDMEM63_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM63_ORIG_TD0 +CYREG_PHUB_TDMEM63_ORIG_TD0 EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM63_ORIG_TD1 +CYREG_PHUB_TDMEM63_ORIG_TD1 EQU 0x400079fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_BASE +CYDEV_PHUB_TDMEM64_BASE EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_SIZE +CYDEV_PHUB_TDMEM64_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM64_ORIG_TD0 +CYREG_PHUB_TDMEM64_ORIG_TD0 EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM64_ORIG_TD1 +CYREG_PHUB_TDMEM64_ORIG_TD1 EQU 0x40007a04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_BASE +CYDEV_PHUB_TDMEM65_BASE EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_SIZE +CYDEV_PHUB_TDMEM65_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM65_ORIG_TD0 +CYREG_PHUB_TDMEM65_ORIG_TD0 EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM65_ORIG_TD1 +CYREG_PHUB_TDMEM65_ORIG_TD1 EQU 0x40007a0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_BASE +CYDEV_PHUB_TDMEM66_BASE EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_SIZE +CYDEV_PHUB_TDMEM66_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM66_ORIG_TD0 +CYREG_PHUB_TDMEM66_ORIG_TD0 EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM66_ORIG_TD1 +CYREG_PHUB_TDMEM66_ORIG_TD1 EQU 0x40007a14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_BASE +CYDEV_PHUB_TDMEM67_BASE EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_SIZE +CYDEV_PHUB_TDMEM67_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM67_ORIG_TD0 +CYREG_PHUB_TDMEM67_ORIG_TD0 EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM67_ORIG_TD1 +CYREG_PHUB_TDMEM67_ORIG_TD1 EQU 0x40007a1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_BASE +CYDEV_PHUB_TDMEM68_BASE EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_SIZE +CYDEV_PHUB_TDMEM68_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM68_ORIG_TD0 +CYREG_PHUB_TDMEM68_ORIG_TD0 EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM68_ORIG_TD1 +CYREG_PHUB_TDMEM68_ORIG_TD1 EQU 0x40007a24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_BASE +CYDEV_PHUB_TDMEM69_BASE EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_SIZE +CYDEV_PHUB_TDMEM69_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM69_ORIG_TD0 +CYREG_PHUB_TDMEM69_ORIG_TD0 EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM69_ORIG_TD1 +CYREG_PHUB_TDMEM69_ORIG_TD1 EQU 0x40007a2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_BASE +CYDEV_PHUB_TDMEM70_BASE EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_SIZE +CYDEV_PHUB_TDMEM70_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM70_ORIG_TD0 +CYREG_PHUB_TDMEM70_ORIG_TD0 EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM70_ORIG_TD1 +CYREG_PHUB_TDMEM70_ORIG_TD1 EQU 0x40007a34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_BASE +CYDEV_PHUB_TDMEM71_BASE EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_SIZE +CYDEV_PHUB_TDMEM71_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM71_ORIG_TD0 +CYREG_PHUB_TDMEM71_ORIG_TD0 EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM71_ORIG_TD1 +CYREG_PHUB_TDMEM71_ORIG_TD1 EQU 0x40007a3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_BASE +CYDEV_PHUB_TDMEM72_BASE EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_SIZE +CYDEV_PHUB_TDMEM72_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM72_ORIG_TD0 +CYREG_PHUB_TDMEM72_ORIG_TD0 EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM72_ORIG_TD1 +CYREG_PHUB_TDMEM72_ORIG_TD1 EQU 0x40007a44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_BASE +CYDEV_PHUB_TDMEM73_BASE EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_SIZE +CYDEV_PHUB_TDMEM73_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM73_ORIG_TD0 +CYREG_PHUB_TDMEM73_ORIG_TD0 EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM73_ORIG_TD1 +CYREG_PHUB_TDMEM73_ORIG_TD1 EQU 0x40007a4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_BASE +CYDEV_PHUB_TDMEM74_BASE EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_SIZE +CYDEV_PHUB_TDMEM74_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM74_ORIG_TD0 +CYREG_PHUB_TDMEM74_ORIG_TD0 EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM74_ORIG_TD1 +CYREG_PHUB_TDMEM74_ORIG_TD1 EQU 0x40007a54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_BASE +CYDEV_PHUB_TDMEM75_BASE EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_SIZE +CYDEV_PHUB_TDMEM75_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM75_ORIG_TD0 +CYREG_PHUB_TDMEM75_ORIG_TD0 EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM75_ORIG_TD1 +CYREG_PHUB_TDMEM75_ORIG_TD1 EQU 0x40007a5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_BASE +CYDEV_PHUB_TDMEM76_BASE EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_SIZE +CYDEV_PHUB_TDMEM76_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM76_ORIG_TD0 +CYREG_PHUB_TDMEM76_ORIG_TD0 EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM76_ORIG_TD1 +CYREG_PHUB_TDMEM76_ORIG_TD1 EQU 0x40007a64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_BASE +CYDEV_PHUB_TDMEM77_BASE EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_SIZE +CYDEV_PHUB_TDMEM77_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM77_ORIG_TD0 +CYREG_PHUB_TDMEM77_ORIG_TD0 EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM77_ORIG_TD1 +CYREG_PHUB_TDMEM77_ORIG_TD1 EQU 0x40007a6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_BASE +CYDEV_PHUB_TDMEM78_BASE EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_SIZE +CYDEV_PHUB_TDMEM78_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM78_ORIG_TD0 +CYREG_PHUB_TDMEM78_ORIG_TD0 EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM78_ORIG_TD1 +CYREG_PHUB_TDMEM78_ORIG_TD1 EQU 0x40007a74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_BASE +CYDEV_PHUB_TDMEM79_BASE EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_SIZE +CYDEV_PHUB_TDMEM79_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM79_ORIG_TD0 +CYREG_PHUB_TDMEM79_ORIG_TD0 EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM79_ORIG_TD1 +CYREG_PHUB_TDMEM79_ORIG_TD1 EQU 0x40007a7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_BASE +CYDEV_PHUB_TDMEM80_BASE EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_SIZE +CYDEV_PHUB_TDMEM80_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM80_ORIG_TD0 +CYREG_PHUB_TDMEM80_ORIG_TD0 EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM80_ORIG_TD1 +CYREG_PHUB_TDMEM80_ORIG_TD1 EQU 0x40007a84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_BASE +CYDEV_PHUB_TDMEM81_BASE EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_SIZE +CYDEV_PHUB_TDMEM81_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM81_ORIG_TD0 +CYREG_PHUB_TDMEM81_ORIG_TD0 EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM81_ORIG_TD1 +CYREG_PHUB_TDMEM81_ORIG_TD1 EQU 0x40007a8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_BASE +CYDEV_PHUB_TDMEM82_BASE EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_SIZE +CYDEV_PHUB_TDMEM82_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM82_ORIG_TD0 +CYREG_PHUB_TDMEM82_ORIG_TD0 EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM82_ORIG_TD1 +CYREG_PHUB_TDMEM82_ORIG_TD1 EQU 0x40007a94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_BASE +CYDEV_PHUB_TDMEM83_BASE EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_SIZE +CYDEV_PHUB_TDMEM83_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM83_ORIG_TD0 +CYREG_PHUB_TDMEM83_ORIG_TD0 EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM83_ORIG_TD1 +CYREG_PHUB_TDMEM83_ORIG_TD1 EQU 0x40007a9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_BASE +CYDEV_PHUB_TDMEM84_BASE EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_SIZE +CYDEV_PHUB_TDMEM84_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM84_ORIG_TD0 +CYREG_PHUB_TDMEM84_ORIG_TD0 EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM84_ORIG_TD1 +CYREG_PHUB_TDMEM84_ORIG_TD1 EQU 0x40007aa4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_BASE +CYDEV_PHUB_TDMEM85_BASE EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_SIZE +CYDEV_PHUB_TDMEM85_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM85_ORIG_TD0 +CYREG_PHUB_TDMEM85_ORIG_TD0 EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM85_ORIG_TD1 +CYREG_PHUB_TDMEM85_ORIG_TD1 EQU 0x40007aac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_BASE +CYDEV_PHUB_TDMEM86_BASE EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_SIZE +CYDEV_PHUB_TDMEM86_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM86_ORIG_TD0 +CYREG_PHUB_TDMEM86_ORIG_TD0 EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM86_ORIG_TD1 +CYREG_PHUB_TDMEM86_ORIG_TD1 EQU 0x40007ab4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_BASE +CYDEV_PHUB_TDMEM87_BASE EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_SIZE +CYDEV_PHUB_TDMEM87_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM87_ORIG_TD0 +CYREG_PHUB_TDMEM87_ORIG_TD0 EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM87_ORIG_TD1 +CYREG_PHUB_TDMEM87_ORIG_TD1 EQU 0x40007abc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_BASE +CYDEV_PHUB_TDMEM88_BASE EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_SIZE +CYDEV_PHUB_TDMEM88_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM88_ORIG_TD0 +CYREG_PHUB_TDMEM88_ORIG_TD0 EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM88_ORIG_TD1 +CYREG_PHUB_TDMEM88_ORIG_TD1 EQU 0x40007ac4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_BASE +CYDEV_PHUB_TDMEM89_BASE EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_SIZE +CYDEV_PHUB_TDMEM89_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM89_ORIG_TD0 +CYREG_PHUB_TDMEM89_ORIG_TD0 EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM89_ORIG_TD1 +CYREG_PHUB_TDMEM89_ORIG_TD1 EQU 0x40007acc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_BASE +CYDEV_PHUB_TDMEM90_BASE EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_SIZE +CYDEV_PHUB_TDMEM90_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM90_ORIG_TD0 +CYREG_PHUB_TDMEM90_ORIG_TD0 EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM90_ORIG_TD1 +CYREG_PHUB_TDMEM90_ORIG_TD1 EQU 0x40007ad4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_BASE +CYDEV_PHUB_TDMEM91_BASE EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_SIZE +CYDEV_PHUB_TDMEM91_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM91_ORIG_TD0 +CYREG_PHUB_TDMEM91_ORIG_TD0 EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM91_ORIG_TD1 +CYREG_PHUB_TDMEM91_ORIG_TD1 EQU 0x40007adc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_BASE +CYDEV_PHUB_TDMEM92_BASE EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_SIZE +CYDEV_PHUB_TDMEM92_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM92_ORIG_TD0 +CYREG_PHUB_TDMEM92_ORIG_TD0 EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM92_ORIG_TD1 +CYREG_PHUB_TDMEM92_ORIG_TD1 EQU 0x40007ae4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_BASE +CYDEV_PHUB_TDMEM93_BASE EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_SIZE +CYDEV_PHUB_TDMEM93_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM93_ORIG_TD0 +CYREG_PHUB_TDMEM93_ORIG_TD0 EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM93_ORIG_TD1 +CYREG_PHUB_TDMEM93_ORIG_TD1 EQU 0x40007aec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_BASE +CYDEV_PHUB_TDMEM94_BASE EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_SIZE +CYDEV_PHUB_TDMEM94_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM94_ORIG_TD0 +CYREG_PHUB_TDMEM94_ORIG_TD0 EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM94_ORIG_TD1 +CYREG_PHUB_TDMEM94_ORIG_TD1 EQU 0x40007af4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_BASE +CYDEV_PHUB_TDMEM95_BASE EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_SIZE +CYDEV_PHUB_TDMEM95_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM95_ORIG_TD0 +CYREG_PHUB_TDMEM95_ORIG_TD0 EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM95_ORIG_TD1 +CYREG_PHUB_TDMEM95_ORIG_TD1 EQU 0x40007afc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_BASE +CYDEV_PHUB_TDMEM96_BASE EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_SIZE +CYDEV_PHUB_TDMEM96_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM96_ORIG_TD0 +CYREG_PHUB_TDMEM96_ORIG_TD0 EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM96_ORIG_TD1 +CYREG_PHUB_TDMEM96_ORIG_TD1 EQU 0x40007b04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_BASE +CYDEV_PHUB_TDMEM97_BASE EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_SIZE +CYDEV_PHUB_TDMEM97_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM97_ORIG_TD0 +CYREG_PHUB_TDMEM97_ORIG_TD0 EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM97_ORIG_TD1 +CYREG_PHUB_TDMEM97_ORIG_TD1 EQU 0x40007b0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_BASE +CYDEV_PHUB_TDMEM98_BASE EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_SIZE +CYDEV_PHUB_TDMEM98_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM98_ORIG_TD0 +CYREG_PHUB_TDMEM98_ORIG_TD0 EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM98_ORIG_TD1 +CYREG_PHUB_TDMEM98_ORIG_TD1 EQU 0x40007b14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_BASE +CYDEV_PHUB_TDMEM99_BASE EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_SIZE +CYDEV_PHUB_TDMEM99_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM99_ORIG_TD0 +CYREG_PHUB_TDMEM99_ORIG_TD0 EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM99_ORIG_TD1 +CYREG_PHUB_TDMEM99_ORIG_TD1 EQU 0x40007b1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_BASE +CYDEV_PHUB_TDMEM100_BASE EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_SIZE +CYDEV_PHUB_TDMEM100_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM100_ORIG_TD0 +CYREG_PHUB_TDMEM100_ORIG_TD0 EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM100_ORIG_TD1 +CYREG_PHUB_TDMEM100_ORIG_TD1 EQU 0x40007b24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_BASE +CYDEV_PHUB_TDMEM101_BASE EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_SIZE +CYDEV_PHUB_TDMEM101_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM101_ORIG_TD0 +CYREG_PHUB_TDMEM101_ORIG_TD0 EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM101_ORIG_TD1 +CYREG_PHUB_TDMEM101_ORIG_TD1 EQU 0x40007b2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_BASE +CYDEV_PHUB_TDMEM102_BASE EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_SIZE +CYDEV_PHUB_TDMEM102_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM102_ORIG_TD0 +CYREG_PHUB_TDMEM102_ORIG_TD0 EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM102_ORIG_TD1 +CYREG_PHUB_TDMEM102_ORIG_TD1 EQU 0x40007b34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_BASE +CYDEV_PHUB_TDMEM103_BASE EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_SIZE +CYDEV_PHUB_TDMEM103_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM103_ORIG_TD0 +CYREG_PHUB_TDMEM103_ORIG_TD0 EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM103_ORIG_TD1 +CYREG_PHUB_TDMEM103_ORIG_TD1 EQU 0x40007b3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_BASE +CYDEV_PHUB_TDMEM104_BASE EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_SIZE +CYDEV_PHUB_TDMEM104_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM104_ORIG_TD0 +CYREG_PHUB_TDMEM104_ORIG_TD0 EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM104_ORIG_TD1 +CYREG_PHUB_TDMEM104_ORIG_TD1 EQU 0x40007b44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_BASE +CYDEV_PHUB_TDMEM105_BASE EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_SIZE +CYDEV_PHUB_TDMEM105_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM105_ORIG_TD0 +CYREG_PHUB_TDMEM105_ORIG_TD0 EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM105_ORIG_TD1 +CYREG_PHUB_TDMEM105_ORIG_TD1 EQU 0x40007b4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_BASE +CYDEV_PHUB_TDMEM106_BASE EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_SIZE +CYDEV_PHUB_TDMEM106_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM106_ORIG_TD0 +CYREG_PHUB_TDMEM106_ORIG_TD0 EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM106_ORIG_TD1 +CYREG_PHUB_TDMEM106_ORIG_TD1 EQU 0x40007b54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_BASE +CYDEV_PHUB_TDMEM107_BASE EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_SIZE +CYDEV_PHUB_TDMEM107_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM107_ORIG_TD0 +CYREG_PHUB_TDMEM107_ORIG_TD0 EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM107_ORIG_TD1 +CYREG_PHUB_TDMEM107_ORIG_TD1 EQU 0x40007b5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_BASE +CYDEV_PHUB_TDMEM108_BASE EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_SIZE +CYDEV_PHUB_TDMEM108_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM108_ORIG_TD0 +CYREG_PHUB_TDMEM108_ORIG_TD0 EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM108_ORIG_TD1 +CYREG_PHUB_TDMEM108_ORIG_TD1 EQU 0x40007b64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_BASE +CYDEV_PHUB_TDMEM109_BASE EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_SIZE +CYDEV_PHUB_TDMEM109_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM109_ORIG_TD0 +CYREG_PHUB_TDMEM109_ORIG_TD0 EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM109_ORIG_TD1 +CYREG_PHUB_TDMEM109_ORIG_TD1 EQU 0x40007b6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_BASE +CYDEV_PHUB_TDMEM110_BASE EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_SIZE +CYDEV_PHUB_TDMEM110_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM110_ORIG_TD0 +CYREG_PHUB_TDMEM110_ORIG_TD0 EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM110_ORIG_TD1 +CYREG_PHUB_TDMEM110_ORIG_TD1 EQU 0x40007b74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_BASE +CYDEV_PHUB_TDMEM111_BASE EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_SIZE +CYDEV_PHUB_TDMEM111_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM111_ORIG_TD0 +CYREG_PHUB_TDMEM111_ORIG_TD0 EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM111_ORIG_TD1 +CYREG_PHUB_TDMEM111_ORIG_TD1 EQU 0x40007b7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_BASE +CYDEV_PHUB_TDMEM112_BASE EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_SIZE +CYDEV_PHUB_TDMEM112_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM112_ORIG_TD0 +CYREG_PHUB_TDMEM112_ORIG_TD0 EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM112_ORIG_TD1 +CYREG_PHUB_TDMEM112_ORIG_TD1 EQU 0x40007b84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_BASE +CYDEV_PHUB_TDMEM113_BASE EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_SIZE +CYDEV_PHUB_TDMEM113_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM113_ORIG_TD0 +CYREG_PHUB_TDMEM113_ORIG_TD0 EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM113_ORIG_TD1 +CYREG_PHUB_TDMEM113_ORIG_TD1 EQU 0x40007b8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_BASE +CYDEV_PHUB_TDMEM114_BASE EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_SIZE +CYDEV_PHUB_TDMEM114_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM114_ORIG_TD0 +CYREG_PHUB_TDMEM114_ORIG_TD0 EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM114_ORIG_TD1 +CYREG_PHUB_TDMEM114_ORIG_TD1 EQU 0x40007b94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_BASE +CYDEV_PHUB_TDMEM115_BASE EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_SIZE +CYDEV_PHUB_TDMEM115_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM115_ORIG_TD0 +CYREG_PHUB_TDMEM115_ORIG_TD0 EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM115_ORIG_TD1 +CYREG_PHUB_TDMEM115_ORIG_TD1 EQU 0x40007b9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_BASE +CYDEV_PHUB_TDMEM116_BASE EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_SIZE +CYDEV_PHUB_TDMEM116_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM116_ORIG_TD0 +CYREG_PHUB_TDMEM116_ORIG_TD0 EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM116_ORIG_TD1 +CYREG_PHUB_TDMEM116_ORIG_TD1 EQU 0x40007ba4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_BASE +CYDEV_PHUB_TDMEM117_BASE EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_SIZE +CYDEV_PHUB_TDMEM117_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM117_ORIG_TD0 +CYREG_PHUB_TDMEM117_ORIG_TD0 EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM117_ORIG_TD1 +CYREG_PHUB_TDMEM117_ORIG_TD1 EQU 0x40007bac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_BASE +CYDEV_PHUB_TDMEM118_BASE EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_SIZE +CYDEV_PHUB_TDMEM118_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM118_ORIG_TD0 +CYREG_PHUB_TDMEM118_ORIG_TD0 EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM118_ORIG_TD1 +CYREG_PHUB_TDMEM118_ORIG_TD1 EQU 0x40007bb4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_BASE +CYDEV_PHUB_TDMEM119_BASE EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_SIZE +CYDEV_PHUB_TDMEM119_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM119_ORIG_TD0 +CYREG_PHUB_TDMEM119_ORIG_TD0 EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM119_ORIG_TD1 +CYREG_PHUB_TDMEM119_ORIG_TD1 EQU 0x40007bbc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_BASE +CYDEV_PHUB_TDMEM120_BASE EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_SIZE +CYDEV_PHUB_TDMEM120_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM120_ORIG_TD0 +CYREG_PHUB_TDMEM120_ORIG_TD0 EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM120_ORIG_TD1 +CYREG_PHUB_TDMEM120_ORIG_TD1 EQU 0x40007bc4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_BASE +CYDEV_PHUB_TDMEM121_BASE EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_SIZE +CYDEV_PHUB_TDMEM121_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM121_ORIG_TD0 +CYREG_PHUB_TDMEM121_ORIG_TD0 EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM121_ORIG_TD1 +CYREG_PHUB_TDMEM121_ORIG_TD1 EQU 0x40007bcc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_BASE +CYDEV_PHUB_TDMEM122_BASE EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_SIZE +CYDEV_PHUB_TDMEM122_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM122_ORIG_TD0 +CYREG_PHUB_TDMEM122_ORIG_TD0 EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM122_ORIG_TD1 +CYREG_PHUB_TDMEM122_ORIG_TD1 EQU 0x40007bd4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_BASE +CYDEV_PHUB_TDMEM123_BASE EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_SIZE +CYDEV_PHUB_TDMEM123_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM123_ORIG_TD0 +CYREG_PHUB_TDMEM123_ORIG_TD0 EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM123_ORIG_TD1 +CYREG_PHUB_TDMEM123_ORIG_TD1 EQU 0x40007bdc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_BASE +CYDEV_PHUB_TDMEM124_BASE EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_SIZE +CYDEV_PHUB_TDMEM124_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM124_ORIG_TD0 +CYREG_PHUB_TDMEM124_ORIG_TD0 EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM124_ORIG_TD1 +CYREG_PHUB_TDMEM124_ORIG_TD1 EQU 0x40007be4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_BASE +CYDEV_PHUB_TDMEM125_BASE EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_SIZE +CYDEV_PHUB_TDMEM125_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM125_ORIG_TD0 +CYREG_PHUB_TDMEM125_ORIG_TD0 EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM125_ORIG_TD1 +CYREG_PHUB_TDMEM125_ORIG_TD1 EQU 0x40007bec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_BASE +CYDEV_PHUB_TDMEM126_BASE EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_SIZE +CYDEV_PHUB_TDMEM126_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM126_ORIG_TD0 +CYREG_PHUB_TDMEM126_ORIG_TD0 EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM126_ORIG_TD1 +CYREG_PHUB_TDMEM126_ORIG_TD1 EQU 0x40007bf4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_BASE +CYDEV_PHUB_TDMEM127_BASE EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_SIZE +CYDEV_PHUB_TDMEM127_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM127_ORIG_TD0 +CYREG_PHUB_TDMEM127_ORIG_TD0 EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM127_ORIG_TD1 +CYREG_PHUB_TDMEM127_ORIG_TD1 EQU 0x40007bfc + ENDIF + IF :LNOT::DEF:CYDEV_EE_BASE +CYDEV_EE_BASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYDEV_EE_SIZE +CYDEV_EE_SIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYREG_EE_DATA_MBASE +CYREG_EE_DATA_MBASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYREG_EE_DATA_MSIZE +CYREG_EE_DATA_MSIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_BASE +CYDEV_CAN0_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_SIZE +CYDEV_CAN0_SIZE EQU 0x000002a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_BASE +CYDEV_CAN0_CSR_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_SIZE +CYDEV_CAN0_CSR_SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_INT_SR +CYREG_CAN0_CSR_INT_SR EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_INT_EN +CYREG_CAN0_CSR_INT_EN EQU 0x4000a004 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_BUF_SR +CYREG_CAN0_CSR_BUF_SR EQU 0x4000a008 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_ERR_SR +CYREG_CAN0_CSR_ERR_SR EQU 0x4000a00c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_CMD +CYREG_CAN0_CSR_CMD EQU 0x4000a010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_CFG +CYREG_CAN0_CSR_CFG EQU 0x4000a014 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_BASE +CYDEV_CAN0_TX0_BASE EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_SIZE +CYDEV_CAN0_TX0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_CMD +CYREG_CAN0_TX0_CMD EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_ID +CYREG_CAN0_TX0_ID EQU 0x4000a024 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_DH +CYREG_CAN0_TX0_DH EQU 0x4000a028 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_DL +CYREG_CAN0_TX0_DL EQU 0x4000a02c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_BASE +CYDEV_CAN0_TX1_BASE EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_SIZE +CYDEV_CAN0_TX1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_CMD +CYREG_CAN0_TX1_CMD EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_ID +CYREG_CAN0_TX1_ID EQU 0x4000a034 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_DH +CYREG_CAN0_TX1_DH EQU 0x4000a038 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_DL +CYREG_CAN0_TX1_DL EQU 0x4000a03c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_BASE +CYDEV_CAN0_TX2_BASE EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_SIZE +CYDEV_CAN0_TX2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_CMD +CYREG_CAN0_TX2_CMD EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_ID +CYREG_CAN0_TX2_ID EQU 0x4000a044 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_DH +CYREG_CAN0_TX2_DH EQU 0x4000a048 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_DL +CYREG_CAN0_TX2_DL EQU 0x4000a04c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_BASE +CYDEV_CAN0_TX3_BASE EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_SIZE +CYDEV_CAN0_TX3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_CMD +CYREG_CAN0_TX3_CMD EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_ID +CYREG_CAN0_TX3_ID EQU 0x4000a054 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_DH +CYREG_CAN0_TX3_DH EQU 0x4000a058 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_DL +CYREG_CAN0_TX3_DL EQU 0x4000a05c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_BASE +CYDEV_CAN0_TX4_BASE EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_SIZE +CYDEV_CAN0_TX4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_CMD +CYREG_CAN0_TX4_CMD EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_ID +CYREG_CAN0_TX4_ID EQU 0x4000a064 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_DH +CYREG_CAN0_TX4_DH EQU 0x4000a068 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_DL +CYREG_CAN0_TX4_DL EQU 0x4000a06c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_BASE +CYDEV_CAN0_TX5_BASE EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_SIZE +CYDEV_CAN0_TX5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_CMD +CYREG_CAN0_TX5_CMD EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_ID +CYREG_CAN0_TX5_ID EQU 0x4000a074 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_DH +CYREG_CAN0_TX5_DH EQU 0x4000a078 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_DL +CYREG_CAN0_TX5_DL EQU 0x4000a07c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_BASE +CYDEV_CAN0_TX6_BASE EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_SIZE +CYDEV_CAN0_TX6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_CMD +CYREG_CAN0_TX6_CMD EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_ID +CYREG_CAN0_TX6_ID EQU 0x4000a084 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_DH +CYREG_CAN0_TX6_DH EQU 0x4000a088 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_DL +CYREG_CAN0_TX6_DL EQU 0x4000a08c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_BASE +CYDEV_CAN0_TX7_BASE EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_SIZE +CYDEV_CAN0_TX7_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_CMD +CYREG_CAN0_TX7_CMD EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_ID +CYREG_CAN0_TX7_ID EQU 0x4000a094 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_DH +CYREG_CAN0_TX7_DH EQU 0x4000a098 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_DL +CYREG_CAN0_TX7_DL EQU 0x4000a09c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_BASE +CYDEV_CAN0_RX0_BASE EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_SIZE +CYDEV_CAN0_RX0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_CMD +CYREG_CAN0_RX0_CMD EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_ID +CYREG_CAN0_RX0_ID EQU 0x4000a0a4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_DH +CYREG_CAN0_RX0_DH EQU 0x4000a0a8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_DL +CYREG_CAN0_RX0_DL EQU 0x4000a0ac + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_AMR +CYREG_CAN0_RX0_AMR EQU 0x4000a0b0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_ACR +CYREG_CAN0_RX0_ACR EQU 0x4000a0b4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_AMRD +CYREG_CAN0_RX0_AMRD EQU 0x4000a0b8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_ACRD +CYREG_CAN0_RX0_ACRD EQU 0x4000a0bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_BASE +CYDEV_CAN0_RX1_BASE EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_SIZE +CYDEV_CAN0_RX1_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_CMD +CYREG_CAN0_RX1_CMD EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_ID +CYREG_CAN0_RX1_ID EQU 0x4000a0c4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_DH +CYREG_CAN0_RX1_DH EQU 0x4000a0c8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_DL +CYREG_CAN0_RX1_DL EQU 0x4000a0cc + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_AMR +CYREG_CAN0_RX1_AMR EQU 0x4000a0d0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_ACR +CYREG_CAN0_RX1_ACR EQU 0x4000a0d4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_AMRD +CYREG_CAN0_RX1_AMRD EQU 0x4000a0d8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_ACRD +CYREG_CAN0_RX1_ACRD EQU 0x4000a0dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_BASE +CYDEV_CAN0_RX2_BASE EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_SIZE +CYDEV_CAN0_RX2_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_CMD +CYREG_CAN0_RX2_CMD EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_ID +CYREG_CAN0_RX2_ID EQU 0x4000a0e4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_DH +CYREG_CAN0_RX2_DH EQU 0x4000a0e8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_DL +CYREG_CAN0_RX2_DL EQU 0x4000a0ec + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_AMR +CYREG_CAN0_RX2_AMR EQU 0x4000a0f0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_ACR +CYREG_CAN0_RX2_ACR EQU 0x4000a0f4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_AMRD +CYREG_CAN0_RX2_AMRD EQU 0x4000a0f8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_ACRD +CYREG_CAN0_RX2_ACRD EQU 0x4000a0fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_BASE +CYDEV_CAN0_RX3_BASE EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_SIZE +CYDEV_CAN0_RX3_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_CMD +CYREG_CAN0_RX3_CMD EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_ID +CYREG_CAN0_RX3_ID EQU 0x4000a104 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_DH +CYREG_CAN0_RX3_DH EQU 0x4000a108 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_DL +CYREG_CAN0_RX3_DL EQU 0x4000a10c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_AMR +CYREG_CAN0_RX3_AMR EQU 0x4000a110 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_ACR +CYREG_CAN0_RX3_ACR EQU 0x4000a114 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_AMRD +CYREG_CAN0_RX3_AMRD EQU 0x4000a118 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_ACRD +CYREG_CAN0_RX3_ACRD EQU 0x4000a11c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_BASE +CYDEV_CAN0_RX4_BASE EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_SIZE +CYDEV_CAN0_RX4_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_CMD +CYREG_CAN0_RX4_CMD EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_ID +CYREG_CAN0_RX4_ID EQU 0x4000a124 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_DH +CYREG_CAN0_RX4_DH EQU 0x4000a128 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_DL +CYREG_CAN0_RX4_DL EQU 0x4000a12c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_AMR +CYREG_CAN0_RX4_AMR EQU 0x4000a130 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_ACR +CYREG_CAN0_RX4_ACR EQU 0x4000a134 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_AMRD +CYREG_CAN0_RX4_AMRD EQU 0x4000a138 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_ACRD +CYREG_CAN0_RX4_ACRD EQU 0x4000a13c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_BASE +CYDEV_CAN0_RX5_BASE EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_SIZE +CYDEV_CAN0_RX5_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_CMD +CYREG_CAN0_RX5_CMD EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_ID +CYREG_CAN0_RX5_ID EQU 0x4000a144 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_DH +CYREG_CAN0_RX5_DH EQU 0x4000a148 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_DL +CYREG_CAN0_RX5_DL EQU 0x4000a14c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_AMR +CYREG_CAN0_RX5_AMR EQU 0x4000a150 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_ACR +CYREG_CAN0_RX5_ACR EQU 0x4000a154 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_AMRD +CYREG_CAN0_RX5_AMRD EQU 0x4000a158 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_ACRD +CYREG_CAN0_RX5_ACRD EQU 0x4000a15c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_BASE +CYDEV_CAN0_RX6_BASE EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_SIZE +CYDEV_CAN0_RX6_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_CMD +CYREG_CAN0_RX6_CMD EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_ID +CYREG_CAN0_RX6_ID EQU 0x4000a164 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_DH +CYREG_CAN0_RX6_DH EQU 0x4000a168 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_DL +CYREG_CAN0_RX6_DL EQU 0x4000a16c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_AMR +CYREG_CAN0_RX6_AMR EQU 0x4000a170 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_ACR +CYREG_CAN0_RX6_ACR EQU 0x4000a174 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_AMRD +CYREG_CAN0_RX6_AMRD EQU 0x4000a178 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_ACRD +CYREG_CAN0_RX6_ACRD EQU 0x4000a17c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_BASE +CYDEV_CAN0_RX7_BASE EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_SIZE +CYDEV_CAN0_RX7_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_CMD +CYREG_CAN0_RX7_CMD EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_ID +CYREG_CAN0_RX7_ID EQU 0x4000a184 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_DH +CYREG_CAN0_RX7_DH EQU 0x4000a188 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_DL +CYREG_CAN0_RX7_DL EQU 0x4000a18c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_AMR +CYREG_CAN0_RX7_AMR EQU 0x4000a190 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_ACR +CYREG_CAN0_RX7_ACR EQU 0x4000a194 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_AMRD +CYREG_CAN0_RX7_AMRD EQU 0x4000a198 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_ACRD +CYREG_CAN0_RX7_ACRD EQU 0x4000a19c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_BASE +CYDEV_CAN0_RX8_BASE EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_SIZE +CYDEV_CAN0_RX8_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_CMD +CYREG_CAN0_RX8_CMD EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_ID +CYREG_CAN0_RX8_ID EQU 0x4000a1a4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_DH +CYREG_CAN0_RX8_DH EQU 0x4000a1a8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_DL +CYREG_CAN0_RX8_DL EQU 0x4000a1ac + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_AMR +CYREG_CAN0_RX8_AMR EQU 0x4000a1b0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_ACR +CYREG_CAN0_RX8_ACR EQU 0x4000a1b4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_AMRD +CYREG_CAN0_RX8_AMRD EQU 0x4000a1b8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_ACRD +CYREG_CAN0_RX8_ACRD EQU 0x4000a1bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_BASE +CYDEV_CAN0_RX9_BASE EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_SIZE +CYDEV_CAN0_RX9_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_CMD +CYREG_CAN0_RX9_CMD EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_ID +CYREG_CAN0_RX9_ID EQU 0x4000a1c4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_DH +CYREG_CAN0_RX9_DH EQU 0x4000a1c8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_DL +CYREG_CAN0_RX9_DL EQU 0x4000a1cc + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_AMR +CYREG_CAN0_RX9_AMR EQU 0x4000a1d0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_ACR +CYREG_CAN0_RX9_ACR EQU 0x4000a1d4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_AMRD +CYREG_CAN0_RX9_AMRD EQU 0x4000a1d8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_ACRD +CYREG_CAN0_RX9_ACRD EQU 0x4000a1dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_BASE +CYDEV_CAN0_RX10_BASE EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_SIZE +CYDEV_CAN0_RX10_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_CMD +CYREG_CAN0_RX10_CMD EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_ID +CYREG_CAN0_RX10_ID EQU 0x4000a1e4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_DH +CYREG_CAN0_RX10_DH EQU 0x4000a1e8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_DL +CYREG_CAN0_RX10_DL EQU 0x4000a1ec + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_AMR +CYREG_CAN0_RX10_AMR EQU 0x4000a1f0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_ACR +CYREG_CAN0_RX10_ACR EQU 0x4000a1f4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_AMRD +CYREG_CAN0_RX10_AMRD EQU 0x4000a1f8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_ACRD +CYREG_CAN0_RX10_ACRD EQU 0x4000a1fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_BASE +CYDEV_CAN0_RX11_BASE EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_SIZE +CYDEV_CAN0_RX11_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_CMD +CYREG_CAN0_RX11_CMD EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_ID +CYREG_CAN0_RX11_ID EQU 0x4000a204 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_DH +CYREG_CAN0_RX11_DH EQU 0x4000a208 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_DL +CYREG_CAN0_RX11_DL EQU 0x4000a20c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_AMR +CYREG_CAN0_RX11_AMR EQU 0x4000a210 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_ACR +CYREG_CAN0_RX11_ACR EQU 0x4000a214 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_AMRD +CYREG_CAN0_RX11_AMRD EQU 0x4000a218 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_ACRD +CYREG_CAN0_RX11_ACRD EQU 0x4000a21c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_BASE +CYDEV_CAN0_RX12_BASE EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_SIZE +CYDEV_CAN0_RX12_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_CMD +CYREG_CAN0_RX12_CMD EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_ID +CYREG_CAN0_RX12_ID EQU 0x4000a224 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_DH +CYREG_CAN0_RX12_DH EQU 0x4000a228 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_DL +CYREG_CAN0_RX12_DL EQU 0x4000a22c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_AMR +CYREG_CAN0_RX12_AMR EQU 0x4000a230 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_ACR +CYREG_CAN0_RX12_ACR EQU 0x4000a234 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_AMRD +CYREG_CAN0_RX12_AMRD EQU 0x4000a238 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_ACRD +CYREG_CAN0_RX12_ACRD EQU 0x4000a23c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_BASE +CYDEV_CAN0_RX13_BASE EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_SIZE +CYDEV_CAN0_RX13_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_CMD +CYREG_CAN0_RX13_CMD EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_ID +CYREG_CAN0_RX13_ID EQU 0x4000a244 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_DH +CYREG_CAN0_RX13_DH EQU 0x4000a248 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_DL +CYREG_CAN0_RX13_DL EQU 0x4000a24c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_AMR +CYREG_CAN0_RX13_AMR EQU 0x4000a250 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_ACR +CYREG_CAN0_RX13_ACR EQU 0x4000a254 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_AMRD +CYREG_CAN0_RX13_AMRD EQU 0x4000a258 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_ACRD +CYREG_CAN0_RX13_ACRD EQU 0x4000a25c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_BASE +CYDEV_CAN0_RX14_BASE EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_SIZE +CYDEV_CAN0_RX14_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_CMD +CYREG_CAN0_RX14_CMD EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_ID +CYREG_CAN0_RX14_ID EQU 0x4000a264 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_DH +CYREG_CAN0_RX14_DH EQU 0x4000a268 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_DL +CYREG_CAN0_RX14_DL EQU 0x4000a26c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_AMR +CYREG_CAN0_RX14_AMR EQU 0x4000a270 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_ACR +CYREG_CAN0_RX14_ACR EQU 0x4000a274 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_AMRD +CYREG_CAN0_RX14_AMRD EQU 0x4000a278 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_ACRD +CYREG_CAN0_RX14_ACRD EQU 0x4000a27c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_BASE +CYDEV_CAN0_RX15_BASE EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_SIZE +CYDEV_CAN0_RX15_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_CMD +CYREG_CAN0_RX15_CMD EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_ID +CYREG_CAN0_RX15_ID EQU 0x4000a284 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_DH +CYREG_CAN0_RX15_DH EQU 0x4000a288 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_DL +CYREG_CAN0_RX15_DL EQU 0x4000a28c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_AMR +CYREG_CAN0_RX15_AMR EQU 0x4000a290 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_ACR +CYREG_CAN0_RX15_ACR EQU 0x4000a294 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_AMRD +CYREG_CAN0_RX15_AMRD EQU 0x4000a298 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_ACRD +CYREG_CAN0_RX15_ACRD EQU 0x4000a29c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_BASE +CYDEV_DFB0_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SIZE +CYDEV_DFB0_SIZE EQU 0x000007b5 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_BASE +CYDEV_DFB0_DPA_SRAM_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_SIZE +CYDEV_DFB0_DPA_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPA_SRAM_DATA_MBASE +CYREG_DFB0_DPA_SRAM_DATA_MBASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPA_SRAM_DATA_MSIZE +CYREG_DFB0_DPA_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_BASE +CYDEV_DFB0_DPB_SRAM_BASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_SIZE +CYDEV_DFB0_DPB_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPB_SRAM_DATA_MBASE +CYREG_DFB0_DPB_SRAM_DATA_MBASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPB_SRAM_DATA_MSIZE +CYREG_DFB0_DPB_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_BASE +CYDEV_DFB0_CSA_SRAM_BASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_SIZE +CYDEV_DFB0_CSA_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSA_SRAM_DATA_MBASE +CYREG_DFB0_CSA_SRAM_DATA_MBASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSA_SRAM_DATA_MSIZE +CYREG_DFB0_CSA_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_BASE +CYDEV_DFB0_CSB_SRAM_BASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_SIZE +CYDEV_DFB0_CSB_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSB_SRAM_DATA_MBASE +CYREG_DFB0_CSB_SRAM_DATA_MBASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSB_SRAM_DATA_MSIZE +CYREG_DFB0_CSB_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_BASE +CYDEV_DFB0_FSM_SRAM_BASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_SIZE +CYDEV_DFB0_FSM_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_FSM_SRAM_DATA_MBASE +CYREG_DFB0_FSM_SRAM_DATA_MBASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_FSM_SRAM_DATA_MSIZE +CYREG_DFB0_FSM_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_BASE +CYDEV_DFB0_ACU_SRAM_BASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_SIZE +CYDEV_DFB0_ACU_SRAM_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_ACU_SRAM_DATA_MBASE +CYREG_DFB0_ACU_SRAM_DATA_MBASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_ACU_SRAM_DATA_MSIZE +CYREG_DFB0_ACU_SRAM_DATA_MSIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CR +CYREG_DFB0_CR EQU 0x4000c780 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_SR +CYREG_DFB0_SR EQU 0x4000c784 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_RAM_EN +CYREG_DFB0_RAM_EN EQU 0x4000c788 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_RAM_DIR +CYREG_DFB0_RAM_DIR EQU 0x4000c78c + ENDIF + IF :LNOT::DEF:CYREG_DFB0_SEMA +CYREG_DFB0_SEMA EQU 0x4000c790 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DSI_CTRL +CYREG_DFB0_DSI_CTRL EQU 0x4000c794 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_INT_CTRL +CYREG_DFB0_INT_CTRL EQU 0x4000c798 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DMA_CTRL +CYREG_DFB0_DMA_CTRL EQU 0x4000c79c + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEA +CYREG_DFB0_STAGEA EQU 0x4000c7a0 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEAM +CYREG_DFB0_STAGEAM EQU 0x4000c7a1 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEAH +CYREG_DFB0_STAGEAH EQU 0x4000c7a2 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEB +CYREG_DFB0_STAGEB EQU 0x4000c7a4 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEBM +CYREG_DFB0_STAGEBM EQU 0x4000c7a5 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEBH +CYREG_DFB0_STAGEBH EQU 0x4000c7a6 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDA +CYREG_DFB0_HOLDA EQU 0x4000c7a8 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDAM +CYREG_DFB0_HOLDAM EQU 0x4000c7a9 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDAH +CYREG_DFB0_HOLDAH EQU 0x4000c7aa + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDAS +CYREG_DFB0_HOLDAS EQU 0x4000c7ab + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDB +CYREG_DFB0_HOLDB EQU 0x4000c7ac + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDBM +CYREG_DFB0_HOLDBM EQU 0x4000c7ad + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDBH +CYREG_DFB0_HOLDBH EQU 0x4000c7ae + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDBS +CYREG_DFB0_HOLDBS EQU 0x4000c7af + ENDIF + IF :LNOT::DEF:CYREG_DFB0_COHER +CYREG_DFB0_COHER EQU 0x4000c7b0 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DALIGN +CYREG_DFB0_DALIGN EQU 0x4000c7b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BASE +CYDEV_UCFG_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_SIZE +CYDEV_UCFG_SIZE EQU 0x00005040 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_BASE +CYDEV_UCFG_B0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_SIZE +CYDEV_UCFG_B0_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_BASE +CYDEV_UCFG_B0_P0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_SIZE +CYDEV_UCFG_B0_P0_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_BASE +CYDEV_UCFG_B0_P0_U0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_SIZE +CYDEV_UCFG_B0_P0_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT0 +CYREG_B0_P0_U0_PLD_IT0 EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT1 +CYREG_B0_P0_U0_PLD_IT1 EQU 0x40010004 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT2 +CYREG_B0_P0_U0_PLD_IT2 EQU 0x40010008 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT3 +CYREG_B0_P0_U0_PLD_IT3 EQU 0x4001000c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT4 +CYREG_B0_P0_U0_PLD_IT4 EQU 0x40010010 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT5 +CYREG_B0_P0_U0_PLD_IT5 EQU 0x40010014 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT6 +CYREG_B0_P0_U0_PLD_IT6 EQU 0x40010018 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT7 +CYREG_B0_P0_U0_PLD_IT7 EQU 0x4001001c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT8 +CYREG_B0_P0_U0_PLD_IT8 EQU 0x40010020 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT9 +CYREG_B0_P0_U0_PLD_IT9 EQU 0x40010024 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT10 +CYREG_B0_P0_U0_PLD_IT10 EQU 0x40010028 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT11 +CYREG_B0_P0_U0_PLD_IT11 EQU 0x4001002c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT0 +CYREG_B0_P0_U0_PLD_ORT0 EQU 0x40010030 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT1 +CYREG_B0_P0_U0_PLD_ORT1 EQU 0x40010032 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT2 +CYREG_B0_P0_U0_PLD_ORT2 EQU 0x40010034 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT3 +CYREG_B0_P0_U0_PLD_ORT3 EQU 0x40010036 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_CEN_CONST +CYREG_B0_P0_U0_MC_CFG_CEN_CONST EQU 0x40010038 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_XORFB +CYREG_B0_P0_U0_MC_CFG_XORFB EQU 0x4001003a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_SET_RESET +CYREG_B0_P0_U0_MC_CFG_SET_RESET EQU 0x4001003c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_BYPASS +CYREG_B0_P0_U0_MC_CFG_BYPASS EQU 0x4001003e + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG0 +CYREG_B0_P0_U0_CFG0 EQU 0x40010040 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG1 +CYREG_B0_P0_U0_CFG1 EQU 0x40010041 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG2 +CYREG_B0_P0_U0_CFG2 EQU 0x40010042 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG3 +CYREG_B0_P0_U0_CFG3 EQU 0x40010043 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG4 +CYREG_B0_P0_U0_CFG4 EQU 0x40010044 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG5 +CYREG_B0_P0_U0_CFG5 EQU 0x40010045 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG6 +CYREG_B0_P0_U0_CFG6 EQU 0x40010046 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG7 +CYREG_B0_P0_U0_CFG7 EQU 0x40010047 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG8 +CYREG_B0_P0_U0_CFG8 EQU 0x40010048 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG9 +CYREG_B0_P0_U0_CFG9 EQU 0x40010049 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG10 +CYREG_B0_P0_U0_CFG10 EQU 0x4001004a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG11 +CYREG_B0_P0_U0_CFG11 EQU 0x4001004b + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG12 +CYREG_B0_P0_U0_CFG12 EQU 0x4001004c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG13 +CYREG_B0_P0_U0_CFG13 EQU 0x4001004d + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG14 +CYREG_B0_P0_U0_CFG14 EQU 0x4001004e + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG15 +CYREG_B0_P0_U0_CFG15 EQU 0x4001004f + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG16 +CYREG_B0_P0_U0_CFG16 EQU 0x40010050 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG17 +CYREG_B0_P0_U0_CFG17 EQU 0x40010051 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG18 +CYREG_B0_P0_U0_CFG18 EQU 0x40010052 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG19 +CYREG_B0_P0_U0_CFG19 EQU 0x40010053 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG20 +CYREG_B0_P0_U0_CFG20 EQU 0x40010054 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG21 +CYREG_B0_P0_U0_CFG21 EQU 0x40010055 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG22 +CYREG_B0_P0_U0_CFG22 EQU 0x40010056 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG23 +CYREG_B0_P0_U0_CFG23 EQU 0x40010057 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG24 +CYREG_B0_P0_U0_CFG24 EQU 0x40010058 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG25 +CYREG_B0_P0_U0_CFG25 EQU 0x40010059 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG26 +CYREG_B0_P0_U0_CFG26 EQU 0x4001005a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG27 +CYREG_B0_P0_U0_CFG27 EQU 0x4001005b + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG28 +CYREG_B0_P0_U0_CFG28 EQU 0x4001005c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG29 +CYREG_B0_P0_U0_CFG29 EQU 0x4001005d + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG30 +CYREG_B0_P0_U0_CFG30 EQU 0x4001005e + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG31 +CYREG_B0_P0_U0_CFG31 EQU 0x4001005f + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG0 +CYREG_B0_P0_U0_DCFG0 EQU 0x40010060 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG1 +CYREG_B0_P0_U0_DCFG1 EQU 0x40010062 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG2 +CYREG_B0_P0_U0_DCFG2 EQU 0x40010064 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG3 +CYREG_B0_P0_U0_DCFG3 EQU 0x40010066 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG4 +CYREG_B0_P0_U0_DCFG4 EQU 0x40010068 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG5 +CYREG_B0_P0_U0_DCFG5 EQU 0x4001006a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG6 +CYREG_B0_P0_U0_DCFG6 EQU 0x4001006c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG7 +CYREG_B0_P0_U0_DCFG7 EQU 0x4001006e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_BASE +CYDEV_UCFG_B0_P0_U1_BASE EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_SIZE +CYDEV_UCFG_B0_P0_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT0 +CYREG_B0_P0_U1_PLD_IT0 EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT1 +CYREG_B0_P0_U1_PLD_IT1 EQU 0x40010084 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT2 +CYREG_B0_P0_U1_PLD_IT2 EQU 0x40010088 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT3 +CYREG_B0_P0_U1_PLD_IT3 EQU 0x4001008c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT4 +CYREG_B0_P0_U1_PLD_IT4 EQU 0x40010090 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT5 +CYREG_B0_P0_U1_PLD_IT5 EQU 0x40010094 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT6 +CYREG_B0_P0_U1_PLD_IT6 EQU 0x40010098 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT7 +CYREG_B0_P0_U1_PLD_IT7 EQU 0x4001009c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT8 +CYREG_B0_P0_U1_PLD_IT8 EQU 0x400100a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT9 +CYREG_B0_P0_U1_PLD_IT9 EQU 0x400100a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT10 +CYREG_B0_P0_U1_PLD_IT10 EQU 0x400100a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT11 +CYREG_B0_P0_U1_PLD_IT11 EQU 0x400100ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT0 +CYREG_B0_P0_U1_PLD_ORT0 EQU 0x400100b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT1 +CYREG_B0_P0_U1_PLD_ORT1 EQU 0x400100b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT2 +CYREG_B0_P0_U1_PLD_ORT2 EQU 0x400100b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT3 +CYREG_B0_P0_U1_PLD_ORT3 EQU 0x400100b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_CEN_CONST +CYREG_B0_P0_U1_MC_CFG_CEN_CONST EQU 0x400100b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_XORFB +CYREG_B0_P0_U1_MC_CFG_XORFB EQU 0x400100ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_SET_RESET +CYREG_B0_P0_U1_MC_CFG_SET_RESET EQU 0x400100bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_BYPASS +CYREG_B0_P0_U1_MC_CFG_BYPASS EQU 0x400100be + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG0 +CYREG_B0_P0_U1_CFG0 EQU 0x400100c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG1 +CYREG_B0_P0_U1_CFG1 EQU 0x400100c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG2 +CYREG_B0_P0_U1_CFG2 EQU 0x400100c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG3 +CYREG_B0_P0_U1_CFG3 EQU 0x400100c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG4 +CYREG_B0_P0_U1_CFG4 EQU 0x400100c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG5 +CYREG_B0_P0_U1_CFG5 EQU 0x400100c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG6 +CYREG_B0_P0_U1_CFG6 EQU 0x400100c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG7 +CYREG_B0_P0_U1_CFG7 EQU 0x400100c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG8 +CYREG_B0_P0_U1_CFG8 EQU 0x400100c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG9 +CYREG_B0_P0_U1_CFG9 EQU 0x400100c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG10 +CYREG_B0_P0_U1_CFG10 EQU 0x400100ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG11 +CYREG_B0_P0_U1_CFG11 EQU 0x400100cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG12 +CYREG_B0_P0_U1_CFG12 EQU 0x400100cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG13 +CYREG_B0_P0_U1_CFG13 EQU 0x400100cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG14 +CYREG_B0_P0_U1_CFG14 EQU 0x400100ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG15 +CYREG_B0_P0_U1_CFG15 EQU 0x400100cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG16 +CYREG_B0_P0_U1_CFG16 EQU 0x400100d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG17 +CYREG_B0_P0_U1_CFG17 EQU 0x400100d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG18 +CYREG_B0_P0_U1_CFG18 EQU 0x400100d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG19 +CYREG_B0_P0_U1_CFG19 EQU 0x400100d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG20 +CYREG_B0_P0_U1_CFG20 EQU 0x400100d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG21 +CYREG_B0_P0_U1_CFG21 EQU 0x400100d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG22 +CYREG_B0_P0_U1_CFG22 EQU 0x400100d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG23 +CYREG_B0_P0_U1_CFG23 EQU 0x400100d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG24 +CYREG_B0_P0_U1_CFG24 EQU 0x400100d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG25 +CYREG_B0_P0_U1_CFG25 EQU 0x400100d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG26 +CYREG_B0_P0_U1_CFG26 EQU 0x400100da + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG27 +CYREG_B0_P0_U1_CFG27 EQU 0x400100db + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG28 +CYREG_B0_P0_U1_CFG28 EQU 0x400100dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG29 +CYREG_B0_P0_U1_CFG29 EQU 0x400100dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG30 +CYREG_B0_P0_U1_CFG30 EQU 0x400100de + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG31 +CYREG_B0_P0_U1_CFG31 EQU 0x400100df + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG0 +CYREG_B0_P0_U1_DCFG0 EQU 0x400100e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG1 +CYREG_B0_P0_U1_DCFG1 EQU 0x400100e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG2 +CYREG_B0_P0_U1_DCFG2 EQU 0x400100e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG3 +CYREG_B0_P0_U1_DCFG3 EQU 0x400100e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG4 +CYREG_B0_P0_U1_DCFG4 EQU 0x400100e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG5 +CYREG_B0_P0_U1_DCFG5 EQU 0x400100ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG6 +CYREG_B0_P0_U1_DCFG6 EQU 0x400100ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG7 +CYREG_B0_P0_U1_DCFG7 EQU 0x400100ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_BASE +CYDEV_UCFG_B0_P0_ROUTE_BASE EQU 0x40010100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_SIZE +CYDEV_UCFG_B0_P0_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_BASE +CYDEV_UCFG_B0_P1_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_SIZE +CYDEV_UCFG_B0_P1_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_BASE +CYDEV_UCFG_B0_P1_U0_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_SIZE +CYDEV_UCFG_B0_P1_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT0 +CYREG_B0_P1_U0_PLD_IT0 EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT1 +CYREG_B0_P1_U0_PLD_IT1 EQU 0x40010204 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT2 +CYREG_B0_P1_U0_PLD_IT2 EQU 0x40010208 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT3 +CYREG_B0_P1_U0_PLD_IT3 EQU 0x4001020c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT4 +CYREG_B0_P1_U0_PLD_IT4 EQU 0x40010210 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT5 +CYREG_B0_P1_U0_PLD_IT5 EQU 0x40010214 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT6 +CYREG_B0_P1_U0_PLD_IT6 EQU 0x40010218 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT7 +CYREG_B0_P1_U0_PLD_IT7 EQU 0x4001021c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT8 +CYREG_B0_P1_U0_PLD_IT8 EQU 0x40010220 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT9 +CYREG_B0_P1_U0_PLD_IT9 EQU 0x40010224 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT10 +CYREG_B0_P1_U0_PLD_IT10 EQU 0x40010228 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT11 +CYREG_B0_P1_U0_PLD_IT11 EQU 0x4001022c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT0 +CYREG_B0_P1_U0_PLD_ORT0 EQU 0x40010230 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT1 +CYREG_B0_P1_U0_PLD_ORT1 EQU 0x40010232 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT2 +CYREG_B0_P1_U0_PLD_ORT2 EQU 0x40010234 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT3 +CYREG_B0_P1_U0_PLD_ORT3 EQU 0x40010236 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_CEN_CONST +CYREG_B0_P1_U0_MC_CFG_CEN_CONST EQU 0x40010238 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_XORFB +CYREG_B0_P1_U0_MC_CFG_XORFB EQU 0x4001023a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_SET_RESET +CYREG_B0_P1_U0_MC_CFG_SET_RESET EQU 0x4001023c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_BYPASS +CYREG_B0_P1_U0_MC_CFG_BYPASS EQU 0x4001023e + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG0 +CYREG_B0_P1_U0_CFG0 EQU 0x40010240 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG1 +CYREG_B0_P1_U0_CFG1 EQU 0x40010241 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG2 +CYREG_B0_P1_U0_CFG2 EQU 0x40010242 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG3 +CYREG_B0_P1_U0_CFG3 EQU 0x40010243 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG4 +CYREG_B0_P1_U0_CFG4 EQU 0x40010244 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG5 +CYREG_B0_P1_U0_CFG5 EQU 0x40010245 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG6 +CYREG_B0_P1_U0_CFG6 EQU 0x40010246 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG7 +CYREG_B0_P1_U0_CFG7 EQU 0x40010247 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG8 +CYREG_B0_P1_U0_CFG8 EQU 0x40010248 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG9 +CYREG_B0_P1_U0_CFG9 EQU 0x40010249 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG10 +CYREG_B0_P1_U0_CFG10 EQU 0x4001024a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG11 +CYREG_B0_P1_U0_CFG11 EQU 0x4001024b + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG12 +CYREG_B0_P1_U0_CFG12 EQU 0x4001024c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG13 +CYREG_B0_P1_U0_CFG13 EQU 0x4001024d + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG14 +CYREG_B0_P1_U0_CFG14 EQU 0x4001024e + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG15 +CYREG_B0_P1_U0_CFG15 EQU 0x4001024f + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG16 +CYREG_B0_P1_U0_CFG16 EQU 0x40010250 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG17 +CYREG_B0_P1_U0_CFG17 EQU 0x40010251 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG18 +CYREG_B0_P1_U0_CFG18 EQU 0x40010252 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG19 +CYREG_B0_P1_U0_CFG19 EQU 0x40010253 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG20 +CYREG_B0_P1_U0_CFG20 EQU 0x40010254 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG21 +CYREG_B0_P1_U0_CFG21 EQU 0x40010255 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG22 +CYREG_B0_P1_U0_CFG22 EQU 0x40010256 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG23 +CYREG_B0_P1_U0_CFG23 EQU 0x40010257 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG24 +CYREG_B0_P1_U0_CFG24 EQU 0x40010258 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG25 +CYREG_B0_P1_U0_CFG25 EQU 0x40010259 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG26 +CYREG_B0_P1_U0_CFG26 EQU 0x4001025a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG27 +CYREG_B0_P1_U0_CFG27 EQU 0x4001025b + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG28 +CYREG_B0_P1_U0_CFG28 EQU 0x4001025c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG29 +CYREG_B0_P1_U0_CFG29 EQU 0x4001025d + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG30 +CYREG_B0_P1_U0_CFG30 EQU 0x4001025e + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG31 +CYREG_B0_P1_U0_CFG31 EQU 0x4001025f + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG0 +CYREG_B0_P1_U0_DCFG0 EQU 0x40010260 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG1 +CYREG_B0_P1_U0_DCFG1 EQU 0x40010262 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG2 +CYREG_B0_P1_U0_DCFG2 EQU 0x40010264 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG3 +CYREG_B0_P1_U0_DCFG3 EQU 0x40010266 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG4 +CYREG_B0_P1_U0_DCFG4 EQU 0x40010268 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG5 +CYREG_B0_P1_U0_DCFG5 EQU 0x4001026a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG6 +CYREG_B0_P1_U0_DCFG6 EQU 0x4001026c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG7 +CYREG_B0_P1_U0_DCFG7 EQU 0x4001026e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_BASE +CYDEV_UCFG_B0_P1_U1_BASE EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_SIZE +CYDEV_UCFG_B0_P1_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT0 +CYREG_B0_P1_U1_PLD_IT0 EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT1 +CYREG_B0_P1_U1_PLD_IT1 EQU 0x40010284 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT2 +CYREG_B0_P1_U1_PLD_IT2 EQU 0x40010288 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT3 +CYREG_B0_P1_U1_PLD_IT3 EQU 0x4001028c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT4 +CYREG_B0_P1_U1_PLD_IT4 EQU 0x40010290 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT5 +CYREG_B0_P1_U1_PLD_IT5 EQU 0x40010294 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT6 +CYREG_B0_P1_U1_PLD_IT6 EQU 0x40010298 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT7 +CYREG_B0_P1_U1_PLD_IT7 EQU 0x4001029c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT8 +CYREG_B0_P1_U1_PLD_IT8 EQU 0x400102a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT9 +CYREG_B0_P1_U1_PLD_IT9 EQU 0x400102a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT10 +CYREG_B0_P1_U1_PLD_IT10 EQU 0x400102a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT11 +CYREG_B0_P1_U1_PLD_IT11 EQU 0x400102ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT0 +CYREG_B0_P1_U1_PLD_ORT0 EQU 0x400102b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT1 +CYREG_B0_P1_U1_PLD_ORT1 EQU 0x400102b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT2 +CYREG_B0_P1_U1_PLD_ORT2 EQU 0x400102b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT3 +CYREG_B0_P1_U1_PLD_ORT3 EQU 0x400102b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_CEN_CONST +CYREG_B0_P1_U1_MC_CFG_CEN_CONST EQU 0x400102b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_XORFB +CYREG_B0_P1_U1_MC_CFG_XORFB EQU 0x400102ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_SET_RESET +CYREG_B0_P1_U1_MC_CFG_SET_RESET EQU 0x400102bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_BYPASS +CYREG_B0_P1_U1_MC_CFG_BYPASS EQU 0x400102be + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG0 +CYREG_B0_P1_U1_CFG0 EQU 0x400102c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG1 +CYREG_B0_P1_U1_CFG1 EQU 0x400102c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG2 +CYREG_B0_P1_U1_CFG2 EQU 0x400102c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG3 +CYREG_B0_P1_U1_CFG3 EQU 0x400102c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG4 +CYREG_B0_P1_U1_CFG4 EQU 0x400102c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG5 +CYREG_B0_P1_U1_CFG5 EQU 0x400102c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG6 +CYREG_B0_P1_U1_CFG6 EQU 0x400102c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG7 +CYREG_B0_P1_U1_CFG7 EQU 0x400102c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG8 +CYREG_B0_P1_U1_CFG8 EQU 0x400102c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG9 +CYREG_B0_P1_U1_CFG9 EQU 0x400102c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG10 +CYREG_B0_P1_U1_CFG10 EQU 0x400102ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG11 +CYREG_B0_P1_U1_CFG11 EQU 0x400102cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG12 +CYREG_B0_P1_U1_CFG12 EQU 0x400102cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG13 +CYREG_B0_P1_U1_CFG13 EQU 0x400102cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG14 +CYREG_B0_P1_U1_CFG14 EQU 0x400102ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG15 +CYREG_B0_P1_U1_CFG15 EQU 0x400102cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG16 +CYREG_B0_P1_U1_CFG16 EQU 0x400102d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG17 +CYREG_B0_P1_U1_CFG17 EQU 0x400102d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG18 +CYREG_B0_P1_U1_CFG18 EQU 0x400102d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG19 +CYREG_B0_P1_U1_CFG19 EQU 0x400102d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG20 +CYREG_B0_P1_U1_CFG20 EQU 0x400102d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG21 +CYREG_B0_P1_U1_CFG21 EQU 0x400102d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG22 +CYREG_B0_P1_U1_CFG22 EQU 0x400102d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG23 +CYREG_B0_P1_U1_CFG23 EQU 0x400102d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG24 +CYREG_B0_P1_U1_CFG24 EQU 0x400102d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG25 +CYREG_B0_P1_U1_CFG25 EQU 0x400102d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG26 +CYREG_B0_P1_U1_CFG26 EQU 0x400102da + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG27 +CYREG_B0_P1_U1_CFG27 EQU 0x400102db + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG28 +CYREG_B0_P1_U1_CFG28 EQU 0x400102dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG29 +CYREG_B0_P1_U1_CFG29 EQU 0x400102dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG30 +CYREG_B0_P1_U1_CFG30 EQU 0x400102de + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG31 +CYREG_B0_P1_U1_CFG31 EQU 0x400102df + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG0 +CYREG_B0_P1_U1_DCFG0 EQU 0x400102e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG1 +CYREG_B0_P1_U1_DCFG1 EQU 0x400102e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG2 +CYREG_B0_P1_U1_DCFG2 EQU 0x400102e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG3 +CYREG_B0_P1_U1_DCFG3 EQU 0x400102e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG4 +CYREG_B0_P1_U1_DCFG4 EQU 0x400102e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG5 +CYREG_B0_P1_U1_DCFG5 EQU 0x400102ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG6 +CYREG_B0_P1_U1_DCFG6 EQU 0x400102ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG7 +CYREG_B0_P1_U1_DCFG7 EQU 0x400102ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_BASE +CYDEV_UCFG_B0_P1_ROUTE_BASE EQU 0x40010300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_SIZE +CYDEV_UCFG_B0_P1_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_BASE +CYDEV_UCFG_B0_P2_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_SIZE +CYDEV_UCFG_B0_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_BASE +CYDEV_UCFG_B0_P2_U0_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_SIZE +CYDEV_UCFG_B0_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT0 +CYREG_B0_P2_U0_PLD_IT0 EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT1 +CYREG_B0_P2_U0_PLD_IT1 EQU 0x40010404 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT2 +CYREG_B0_P2_U0_PLD_IT2 EQU 0x40010408 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT3 +CYREG_B0_P2_U0_PLD_IT3 EQU 0x4001040c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT4 +CYREG_B0_P2_U0_PLD_IT4 EQU 0x40010410 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT5 +CYREG_B0_P2_U0_PLD_IT5 EQU 0x40010414 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT6 +CYREG_B0_P2_U0_PLD_IT6 EQU 0x40010418 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT7 +CYREG_B0_P2_U0_PLD_IT7 EQU 0x4001041c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT8 +CYREG_B0_P2_U0_PLD_IT8 EQU 0x40010420 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT9 +CYREG_B0_P2_U0_PLD_IT9 EQU 0x40010424 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT10 +CYREG_B0_P2_U0_PLD_IT10 EQU 0x40010428 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT11 +CYREG_B0_P2_U0_PLD_IT11 EQU 0x4001042c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT0 +CYREG_B0_P2_U0_PLD_ORT0 EQU 0x40010430 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT1 +CYREG_B0_P2_U0_PLD_ORT1 EQU 0x40010432 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT2 +CYREG_B0_P2_U0_PLD_ORT2 EQU 0x40010434 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT3 +CYREG_B0_P2_U0_PLD_ORT3 EQU 0x40010436 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_CEN_CONST +CYREG_B0_P2_U0_MC_CFG_CEN_CONST EQU 0x40010438 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_XORFB +CYREG_B0_P2_U0_MC_CFG_XORFB EQU 0x4001043a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_SET_RESET +CYREG_B0_P2_U0_MC_CFG_SET_RESET EQU 0x4001043c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_BYPASS +CYREG_B0_P2_U0_MC_CFG_BYPASS EQU 0x4001043e + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG0 +CYREG_B0_P2_U0_CFG0 EQU 0x40010440 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG1 +CYREG_B0_P2_U0_CFG1 EQU 0x40010441 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG2 +CYREG_B0_P2_U0_CFG2 EQU 0x40010442 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG3 +CYREG_B0_P2_U0_CFG3 EQU 0x40010443 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG4 +CYREG_B0_P2_U0_CFG4 EQU 0x40010444 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG5 +CYREG_B0_P2_U0_CFG5 EQU 0x40010445 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG6 +CYREG_B0_P2_U0_CFG6 EQU 0x40010446 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG7 +CYREG_B0_P2_U0_CFG7 EQU 0x40010447 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG8 +CYREG_B0_P2_U0_CFG8 EQU 0x40010448 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG9 +CYREG_B0_P2_U0_CFG9 EQU 0x40010449 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG10 +CYREG_B0_P2_U0_CFG10 EQU 0x4001044a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG11 +CYREG_B0_P2_U0_CFG11 EQU 0x4001044b + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG12 +CYREG_B0_P2_U0_CFG12 EQU 0x4001044c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG13 +CYREG_B0_P2_U0_CFG13 EQU 0x4001044d + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG14 +CYREG_B0_P2_U0_CFG14 EQU 0x4001044e + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG15 +CYREG_B0_P2_U0_CFG15 EQU 0x4001044f + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG16 +CYREG_B0_P2_U0_CFG16 EQU 0x40010450 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG17 +CYREG_B0_P2_U0_CFG17 EQU 0x40010451 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG18 +CYREG_B0_P2_U0_CFG18 EQU 0x40010452 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG19 +CYREG_B0_P2_U0_CFG19 EQU 0x40010453 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG20 +CYREG_B0_P2_U0_CFG20 EQU 0x40010454 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG21 +CYREG_B0_P2_U0_CFG21 EQU 0x40010455 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG22 +CYREG_B0_P2_U0_CFG22 EQU 0x40010456 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG23 +CYREG_B0_P2_U0_CFG23 EQU 0x40010457 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG24 +CYREG_B0_P2_U0_CFG24 EQU 0x40010458 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG25 +CYREG_B0_P2_U0_CFG25 EQU 0x40010459 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG26 +CYREG_B0_P2_U0_CFG26 EQU 0x4001045a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG27 +CYREG_B0_P2_U0_CFG27 EQU 0x4001045b + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG28 +CYREG_B0_P2_U0_CFG28 EQU 0x4001045c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG29 +CYREG_B0_P2_U0_CFG29 EQU 0x4001045d + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG30 +CYREG_B0_P2_U0_CFG30 EQU 0x4001045e + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG31 +CYREG_B0_P2_U0_CFG31 EQU 0x4001045f + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG0 +CYREG_B0_P2_U0_DCFG0 EQU 0x40010460 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG1 +CYREG_B0_P2_U0_DCFG1 EQU 0x40010462 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG2 +CYREG_B0_P2_U0_DCFG2 EQU 0x40010464 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG3 +CYREG_B0_P2_U0_DCFG3 EQU 0x40010466 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG4 +CYREG_B0_P2_U0_DCFG4 EQU 0x40010468 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG5 +CYREG_B0_P2_U0_DCFG5 EQU 0x4001046a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG6 +CYREG_B0_P2_U0_DCFG6 EQU 0x4001046c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG7 +CYREG_B0_P2_U0_DCFG7 EQU 0x4001046e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_BASE +CYDEV_UCFG_B0_P2_U1_BASE EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_SIZE +CYDEV_UCFG_B0_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT0 +CYREG_B0_P2_U1_PLD_IT0 EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT1 +CYREG_B0_P2_U1_PLD_IT1 EQU 0x40010484 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT2 +CYREG_B0_P2_U1_PLD_IT2 EQU 0x40010488 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT3 +CYREG_B0_P2_U1_PLD_IT3 EQU 0x4001048c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT4 +CYREG_B0_P2_U1_PLD_IT4 EQU 0x40010490 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT5 +CYREG_B0_P2_U1_PLD_IT5 EQU 0x40010494 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT6 +CYREG_B0_P2_U1_PLD_IT6 EQU 0x40010498 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT7 +CYREG_B0_P2_U1_PLD_IT7 EQU 0x4001049c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT8 +CYREG_B0_P2_U1_PLD_IT8 EQU 0x400104a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT9 +CYREG_B0_P2_U1_PLD_IT9 EQU 0x400104a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT10 +CYREG_B0_P2_U1_PLD_IT10 EQU 0x400104a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT11 +CYREG_B0_P2_U1_PLD_IT11 EQU 0x400104ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT0 +CYREG_B0_P2_U1_PLD_ORT0 EQU 0x400104b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT1 +CYREG_B0_P2_U1_PLD_ORT1 EQU 0x400104b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT2 +CYREG_B0_P2_U1_PLD_ORT2 EQU 0x400104b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT3 +CYREG_B0_P2_U1_PLD_ORT3 EQU 0x400104b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_CEN_CONST +CYREG_B0_P2_U1_MC_CFG_CEN_CONST EQU 0x400104b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_XORFB +CYREG_B0_P2_U1_MC_CFG_XORFB EQU 0x400104ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_SET_RESET +CYREG_B0_P2_U1_MC_CFG_SET_RESET EQU 0x400104bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_BYPASS +CYREG_B0_P2_U1_MC_CFG_BYPASS EQU 0x400104be + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG0 +CYREG_B0_P2_U1_CFG0 EQU 0x400104c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG1 +CYREG_B0_P2_U1_CFG1 EQU 0x400104c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG2 +CYREG_B0_P2_U1_CFG2 EQU 0x400104c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG3 +CYREG_B0_P2_U1_CFG3 EQU 0x400104c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG4 +CYREG_B0_P2_U1_CFG4 EQU 0x400104c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG5 +CYREG_B0_P2_U1_CFG5 EQU 0x400104c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG6 +CYREG_B0_P2_U1_CFG6 EQU 0x400104c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG7 +CYREG_B0_P2_U1_CFG7 EQU 0x400104c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG8 +CYREG_B0_P2_U1_CFG8 EQU 0x400104c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG9 +CYREG_B0_P2_U1_CFG9 EQU 0x400104c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG10 +CYREG_B0_P2_U1_CFG10 EQU 0x400104ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG11 +CYREG_B0_P2_U1_CFG11 EQU 0x400104cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG12 +CYREG_B0_P2_U1_CFG12 EQU 0x400104cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG13 +CYREG_B0_P2_U1_CFG13 EQU 0x400104cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG14 +CYREG_B0_P2_U1_CFG14 EQU 0x400104ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG15 +CYREG_B0_P2_U1_CFG15 EQU 0x400104cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG16 +CYREG_B0_P2_U1_CFG16 EQU 0x400104d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG17 +CYREG_B0_P2_U1_CFG17 EQU 0x400104d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG18 +CYREG_B0_P2_U1_CFG18 EQU 0x400104d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG19 +CYREG_B0_P2_U1_CFG19 EQU 0x400104d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG20 +CYREG_B0_P2_U1_CFG20 EQU 0x400104d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG21 +CYREG_B0_P2_U1_CFG21 EQU 0x400104d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG22 +CYREG_B0_P2_U1_CFG22 EQU 0x400104d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG23 +CYREG_B0_P2_U1_CFG23 EQU 0x400104d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG24 +CYREG_B0_P2_U1_CFG24 EQU 0x400104d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG25 +CYREG_B0_P2_U1_CFG25 EQU 0x400104d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG26 +CYREG_B0_P2_U1_CFG26 EQU 0x400104da + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG27 +CYREG_B0_P2_U1_CFG27 EQU 0x400104db + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG28 +CYREG_B0_P2_U1_CFG28 EQU 0x400104dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG29 +CYREG_B0_P2_U1_CFG29 EQU 0x400104dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG30 +CYREG_B0_P2_U1_CFG30 EQU 0x400104de + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG31 +CYREG_B0_P2_U1_CFG31 EQU 0x400104df + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG0 +CYREG_B0_P2_U1_DCFG0 EQU 0x400104e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG1 +CYREG_B0_P2_U1_DCFG1 EQU 0x400104e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG2 +CYREG_B0_P2_U1_DCFG2 EQU 0x400104e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG3 +CYREG_B0_P2_U1_DCFG3 EQU 0x400104e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG4 +CYREG_B0_P2_U1_DCFG4 EQU 0x400104e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG5 +CYREG_B0_P2_U1_DCFG5 EQU 0x400104ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG6 +CYREG_B0_P2_U1_DCFG6 EQU 0x400104ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG7 +CYREG_B0_P2_U1_DCFG7 EQU 0x400104ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_BASE +CYDEV_UCFG_B0_P2_ROUTE_BASE EQU 0x40010500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_SIZE +CYDEV_UCFG_B0_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_BASE +CYDEV_UCFG_B0_P3_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_SIZE +CYDEV_UCFG_B0_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_BASE +CYDEV_UCFG_B0_P3_U0_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_SIZE +CYDEV_UCFG_B0_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT0 +CYREG_B0_P3_U0_PLD_IT0 EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT1 +CYREG_B0_P3_U0_PLD_IT1 EQU 0x40010604 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT2 +CYREG_B0_P3_U0_PLD_IT2 EQU 0x40010608 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT3 +CYREG_B0_P3_U0_PLD_IT3 EQU 0x4001060c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT4 +CYREG_B0_P3_U0_PLD_IT4 EQU 0x40010610 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT5 +CYREG_B0_P3_U0_PLD_IT5 EQU 0x40010614 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT6 +CYREG_B0_P3_U0_PLD_IT6 EQU 0x40010618 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT7 +CYREG_B0_P3_U0_PLD_IT7 EQU 0x4001061c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT8 +CYREG_B0_P3_U0_PLD_IT8 EQU 0x40010620 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT9 +CYREG_B0_P3_U0_PLD_IT9 EQU 0x40010624 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT10 +CYREG_B0_P3_U0_PLD_IT10 EQU 0x40010628 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT11 +CYREG_B0_P3_U0_PLD_IT11 EQU 0x4001062c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT0 +CYREG_B0_P3_U0_PLD_ORT0 EQU 0x40010630 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT1 +CYREG_B0_P3_U0_PLD_ORT1 EQU 0x40010632 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT2 +CYREG_B0_P3_U0_PLD_ORT2 EQU 0x40010634 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT3 +CYREG_B0_P3_U0_PLD_ORT3 EQU 0x40010636 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_CEN_CONST +CYREG_B0_P3_U0_MC_CFG_CEN_CONST EQU 0x40010638 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_XORFB +CYREG_B0_P3_U0_MC_CFG_XORFB EQU 0x4001063a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_SET_RESET +CYREG_B0_P3_U0_MC_CFG_SET_RESET EQU 0x4001063c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_BYPASS +CYREG_B0_P3_U0_MC_CFG_BYPASS EQU 0x4001063e + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG0 +CYREG_B0_P3_U0_CFG0 EQU 0x40010640 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG1 +CYREG_B0_P3_U0_CFG1 EQU 0x40010641 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG2 +CYREG_B0_P3_U0_CFG2 EQU 0x40010642 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG3 +CYREG_B0_P3_U0_CFG3 EQU 0x40010643 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG4 +CYREG_B0_P3_U0_CFG4 EQU 0x40010644 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG5 +CYREG_B0_P3_U0_CFG5 EQU 0x40010645 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG6 +CYREG_B0_P3_U0_CFG6 EQU 0x40010646 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG7 +CYREG_B0_P3_U0_CFG7 EQU 0x40010647 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG8 +CYREG_B0_P3_U0_CFG8 EQU 0x40010648 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG9 +CYREG_B0_P3_U0_CFG9 EQU 0x40010649 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG10 +CYREG_B0_P3_U0_CFG10 EQU 0x4001064a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG11 +CYREG_B0_P3_U0_CFG11 EQU 0x4001064b + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG12 +CYREG_B0_P3_U0_CFG12 EQU 0x4001064c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG13 +CYREG_B0_P3_U0_CFG13 EQU 0x4001064d + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG14 +CYREG_B0_P3_U0_CFG14 EQU 0x4001064e + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG15 +CYREG_B0_P3_U0_CFG15 EQU 0x4001064f + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG16 +CYREG_B0_P3_U0_CFG16 EQU 0x40010650 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG17 +CYREG_B0_P3_U0_CFG17 EQU 0x40010651 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG18 +CYREG_B0_P3_U0_CFG18 EQU 0x40010652 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG19 +CYREG_B0_P3_U0_CFG19 EQU 0x40010653 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG20 +CYREG_B0_P3_U0_CFG20 EQU 0x40010654 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG21 +CYREG_B0_P3_U0_CFG21 EQU 0x40010655 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG22 +CYREG_B0_P3_U0_CFG22 EQU 0x40010656 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG23 +CYREG_B0_P3_U0_CFG23 EQU 0x40010657 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG24 +CYREG_B0_P3_U0_CFG24 EQU 0x40010658 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG25 +CYREG_B0_P3_U0_CFG25 EQU 0x40010659 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG26 +CYREG_B0_P3_U0_CFG26 EQU 0x4001065a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG27 +CYREG_B0_P3_U0_CFG27 EQU 0x4001065b + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG28 +CYREG_B0_P3_U0_CFG28 EQU 0x4001065c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG29 +CYREG_B0_P3_U0_CFG29 EQU 0x4001065d + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG30 +CYREG_B0_P3_U0_CFG30 EQU 0x4001065e + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG31 +CYREG_B0_P3_U0_CFG31 EQU 0x4001065f + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG0 +CYREG_B0_P3_U0_DCFG0 EQU 0x40010660 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG1 +CYREG_B0_P3_U0_DCFG1 EQU 0x40010662 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG2 +CYREG_B0_P3_U0_DCFG2 EQU 0x40010664 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG3 +CYREG_B0_P3_U0_DCFG3 EQU 0x40010666 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG4 +CYREG_B0_P3_U0_DCFG4 EQU 0x40010668 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG5 +CYREG_B0_P3_U0_DCFG5 EQU 0x4001066a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG6 +CYREG_B0_P3_U0_DCFG6 EQU 0x4001066c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG7 +CYREG_B0_P3_U0_DCFG7 EQU 0x4001066e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_BASE +CYDEV_UCFG_B0_P3_U1_BASE EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_SIZE +CYDEV_UCFG_B0_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT0 +CYREG_B0_P3_U1_PLD_IT0 EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT1 +CYREG_B0_P3_U1_PLD_IT1 EQU 0x40010684 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT2 +CYREG_B0_P3_U1_PLD_IT2 EQU 0x40010688 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT3 +CYREG_B0_P3_U1_PLD_IT3 EQU 0x4001068c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT4 +CYREG_B0_P3_U1_PLD_IT4 EQU 0x40010690 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT5 +CYREG_B0_P3_U1_PLD_IT5 EQU 0x40010694 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT6 +CYREG_B0_P3_U1_PLD_IT6 EQU 0x40010698 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT7 +CYREG_B0_P3_U1_PLD_IT7 EQU 0x4001069c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT8 +CYREG_B0_P3_U1_PLD_IT8 EQU 0x400106a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT9 +CYREG_B0_P3_U1_PLD_IT9 EQU 0x400106a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT10 +CYREG_B0_P3_U1_PLD_IT10 EQU 0x400106a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT11 +CYREG_B0_P3_U1_PLD_IT11 EQU 0x400106ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT0 +CYREG_B0_P3_U1_PLD_ORT0 EQU 0x400106b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT1 +CYREG_B0_P3_U1_PLD_ORT1 EQU 0x400106b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT2 +CYREG_B0_P3_U1_PLD_ORT2 EQU 0x400106b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT3 +CYREG_B0_P3_U1_PLD_ORT3 EQU 0x400106b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_CEN_CONST +CYREG_B0_P3_U1_MC_CFG_CEN_CONST EQU 0x400106b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_XORFB +CYREG_B0_P3_U1_MC_CFG_XORFB EQU 0x400106ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_SET_RESET +CYREG_B0_P3_U1_MC_CFG_SET_RESET EQU 0x400106bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_BYPASS +CYREG_B0_P3_U1_MC_CFG_BYPASS EQU 0x400106be + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG0 +CYREG_B0_P3_U1_CFG0 EQU 0x400106c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG1 +CYREG_B0_P3_U1_CFG1 EQU 0x400106c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG2 +CYREG_B0_P3_U1_CFG2 EQU 0x400106c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG3 +CYREG_B0_P3_U1_CFG3 EQU 0x400106c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG4 +CYREG_B0_P3_U1_CFG4 EQU 0x400106c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG5 +CYREG_B0_P3_U1_CFG5 EQU 0x400106c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG6 +CYREG_B0_P3_U1_CFG6 EQU 0x400106c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG7 +CYREG_B0_P3_U1_CFG7 EQU 0x400106c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG8 +CYREG_B0_P3_U1_CFG8 EQU 0x400106c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG9 +CYREG_B0_P3_U1_CFG9 EQU 0x400106c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG10 +CYREG_B0_P3_U1_CFG10 EQU 0x400106ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG11 +CYREG_B0_P3_U1_CFG11 EQU 0x400106cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG12 +CYREG_B0_P3_U1_CFG12 EQU 0x400106cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG13 +CYREG_B0_P3_U1_CFG13 EQU 0x400106cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG14 +CYREG_B0_P3_U1_CFG14 EQU 0x400106ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG15 +CYREG_B0_P3_U1_CFG15 EQU 0x400106cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG16 +CYREG_B0_P3_U1_CFG16 EQU 0x400106d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG17 +CYREG_B0_P3_U1_CFG17 EQU 0x400106d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG18 +CYREG_B0_P3_U1_CFG18 EQU 0x400106d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG19 +CYREG_B0_P3_U1_CFG19 EQU 0x400106d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG20 +CYREG_B0_P3_U1_CFG20 EQU 0x400106d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG21 +CYREG_B0_P3_U1_CFG21 EQU 0x400106d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG22 +CYREG_B0_P3_U1_CFG22 EQU 0x400106d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG23 +CYREG_B0_P3_U1_CFG23 EQU 0x400106d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG24 +CYREG_B0_P3_U1_CFG24 EQU 0x400106d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG25 +CYREG_B0_P3_U1_CFG25 EQU 0x400106d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG26 +CYREG_B0_P3_U1_CFG26 EQU 0x400106da + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG27 +CYREG_B0_P3_U1_CFG27 EQU 0x400106db + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG28 +CYREG_B0_P3_U1_CFG28 EQU 0x400106dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG29 +CYREG_B0_P3_U1_CFG29 EQU 0x400106dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG30 +CYREG_B0_P3_U1_CFG30 EQU 0x400106de + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG31 +CYREG_B0_P3_U1_CFG31 EQU 0x400106df + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG0 +CYREG_B0_P3_U1_DCFG0 EQU 0x400106e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG1 +CYREG_B0_P3_U1_DCFG1 EQU 0x400106e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG2 +CYREG_B0_P3_U1_DCFG2 EQU 0x400106e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG3 +CYREG_B0_P3_U1_DCFG3 EQU 0x400106e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG4 +CYREG_B0_P3_U1_DCFG4 EQU 0x400106e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG5 +CYREG_B0_P3_U1_DCFG5 EQU 0x400106ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG6 +CYREG_B0_P3_U1_DCFG6 EQU 0x400106ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG7 +CYREG_B0_P3_U1_DCFG7 EQU 0x400106ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_BASE +CYDEV_UCFG_B0_P3_ROUTE_BASE EQU 0x40010700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_SIZE +CYDEV_UCFG_B0_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_BASE +CYDEV_UCFG_B0_P4_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_SIZE +CYDEV_UCFG_B0_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_BASE +CYDEV_UCFG_B0_P4_U0_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_SIZE +CYDEV_UCFG_B0_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT0 +CYREG_B0_P4_U0_PLD_IT0 EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT1 +CYREG_B0_P4_U0_PLD_IT1 EQU 0x40010804 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT2 +CYREG_B0_P4_U0_PLD_IT2 EQU 0x40010808 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT3 +CYREG_B0_P4_U0_PLD_IT3 EQU 0x4001080c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT4 +CYREG_B0_P4_U0_PLD_IT4 EQU 0x40010810 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT5 +CYREG_B0_P4_U0_PLD_IT5 EQU 0x40010814 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT6 +CYREG_B0_P4_U0_PLD_IT6 EQU 0x40010818 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT7 +CYREG_B0_P4_U0_PLD_IT7 EQU 0x4001081c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT8 +CYREG_B0_P4_U0_PLD_IT8 EQU 0x40010820 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT9 +CYREG_B0_P4_U0_PLD_IT9 EQU 0x40010824 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT10 +CYREG_B0_P4_U0_PLD_IT10 EQU 0x40010828 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT11 +CYREG_B0_P4_U0_PLD_IT11 EQU 0x4001082c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT0 +CYREG_B0_P4_U0_PLD_ORT0 EQU 0x40010830 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT1 +CYREG_B0_P4_U0_PLD_ORT1 EQU 0x40010832 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT2 +CYREG_B0_P4_U0_PLD_ORT2 EQU 0x40010834 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT3 +CYREG_B0_P4_U0_PLD_ORT3 EQU 0x40010836 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_CEN_CONST +CYREG_B0_P4_U0_MC_CFG_CEN_CONST EQU 0x40010838 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_XORFB +CYREG_B0_P4_U0_MC_CFG_XORFB EQU 0x4001083a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_SET_RESET +CYREG_B0_P4_U0_MC_CFG_SET_RESET EQU 0x4001083c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_BYPASS +CYREG_B0_P4_U0_MC_CFG_BYPASS EQU 0x4001083e + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG0 +CYREG_B0_P4_U0_CFG0 EQU 0x40010840 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG1 +CYREG_B0_P4_U0_CFG1 EQU 0x40010841 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG2 +CYREG_B0_P4_U0_CFG2 EQU 0x40010842 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG3 +CYREG_B0_P4_U0_CFG3 EQU 0x40010843 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG4 +CYREG_B0_P4_U0_CFG4 EQU 0x40010844 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG5 +CYREG_B0_P4_U0_CFG5 EQU 0x40010845 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG6 +CYREG_B0_P4_U0_CFG6 EQU 0x40010846 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG7 +CYREG_B0_P4_U0_CFG7 EQU 0x40010847 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG8 +CYREG_B0_P4_U0_CFG8 EQU 0x40010848 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG9 +CYREG_B0_P4_U0_CFG9 EQU 0x40010849 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG10 +CYREG_B0_P4_U0_CFG10 EQU 0x4001084a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG11 +CYREG_B0_P4_U0_CFG11 EQU 0x4001084b + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG12 +CYREG_B0_P4_U0_CFG12 EQU 0x4001084c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG13 +CYREG_B0_P4_U0_CFG13 EQU 0x4001084d + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG14 +CYREG_B0_P4_U0_CFG14 EQU 0x4001084e + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG15 +CYREG_B0_P4_U0_CFG15 EQU 0x4001084f + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG16 +CYREG_B0_P4_U0_CFG16 EQU 0x40010850 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG17 +CYREG_B0_P4_U0_CFG17 EQU 0x40010851 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG18 +CYREG_B0_P4_U0_CFG18 EQU 0x40010852 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG19 +CYREG_B0_P4_U0_CFG19 EQU 0x40010853 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG20 +CYREG_B0_P4_U0_CFG20 EQU 0x40010854 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG21 +CYREG_B0_P4_U0_CFG21 EQU 0x40010855 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG22 +CYREG_B0_P4_U0_CFG22 EQU 0x40010856 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG23 +CYREG_B0_P4_U0_CFG23 EQU 0x40010857 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG24 +CYREG_B0_P4_U0_CFG24 EQU 0x40010858 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG25 +CYREG_B0_P4_U0_CFG25 EQU 0x40010859 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG26 +CYREG_B0_P4_U0_CFG26 EQU 0x4001085a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG27 +CYREG_B0_P4_U0_CFG27 EQU 0x4001085b + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG28 +CYREG_B0_P4_U0_CFG28 EQU 0x4001085c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG29 +CYREG_B0_P4_U0_CFG29 EQU 0x4001085d + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG30 +CYREG_B0_P4_U0_CFG30 EQU 0x4001085e + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG31 +CYREG_B0_P4_U0_CFG31 EQU 0x4001085f + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG0 +CYREG_B0_P4_U0_DCFG0 EQU 0x40010860 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG1 +CYREG_B0_P4_U0_DCFG1 EQU 0x40010862 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG2 +CYREG_B0_P4_U0_DCFG2 EQU 0x40010864 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG3 +CYREG_B0_P4_U0_DCFG3 EQU 0x40010866 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG4 +CYREG_B0_P4_U0_DCFG4 EQU 0x40010868 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG5 +CYREG_B0_P4_U0_DCFG5 EQU 0x4001086a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG6 +CYREG_B0_P4_U0_DCFG6 EQU 0x4001086c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG7 +CYREG_B0_P4_U0_DCFG7 EQU 0x4001086e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_BASE +CYDEV_UCFG_B0_P4_U1_BASE EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_SIZE +CYDEV_UCFG_B0_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT0 +CYREG_B0_P4_U1_PLD_IT0 EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT1 +CYREG_B0_P4_U1_PLD_IT1 EQU 0x40010884 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT2 +CYREG_B0_P4_U1_PLD_IT2 EQU 0x40010888 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT3 +CYREG_B0_P4_U1_PLD_IT3 EQU 0x4001088c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT4 +CYREG_B0_P4_U1_PLD_IT4 EQU 0x40010890 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT5 +CYREG_B0_P4_U1_PLD_IT5 EQU 0x40010894 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT6 +CYREG_B0_P4_U1_PLD_IT6 EQU 0x40010898 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT7 +CYREG_B0_P4_U1_PLD_IT7 EQU 0x4001089c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT8 +CYREG_B0_P4_U1_PLD_IT8 EQU 0x400108a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT9 +CYREG_B0_P4_U1_PLD_IT9 EQU 0x400108a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT10 +CYREG_B0_P4_U1_PLD_IT10 EQU 0x400108a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT11 +CYREG_B0_P4_U1_PLD_IT11 EQU 0x400108ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT0 +CYREG_B0_P4_U1_PLD_ORT0 EQU 0x400108b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT1 +CYREG_B0_P4_U1_PLD_ORT1 EQU 0x400108b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT2 +CYREG_B0_P4_U1_PLD_ORT2 EQU 0x400108b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT3 +CYREG_B0_P4_U1_PLD_ORT3 EQU 0x400108b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_CEN_CONST +CYREG_B0_P4_U1_MC_CFG_CEN_CONST EQU 0x400108b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_XORFB +CYREG_B0_P4_U1_MC_CFG_XORFB EQU 0x400108ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_SET_RESET +CYREG_B0_P4_U1_MC_CFG_SET_RESET EQU 0x400108bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_BYPASS +CYREG_B0_P4_U1_MC_CFG_BYPASS EQU 0x400108be + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG0 +CYREG_B0_P4_U1_CFG0 EQU 0x400108c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG1 +CYREG_B0_P4_U1_CFG1 EQU 0x400108c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG2 +CYREG_B0_P4_U1_CFG2 EQU 0x400108c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG3 +CYREG_B0_P4_U1_CFG3 EQU 0x400108c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG4 +CYREG_B0_P4_U1_CFG4 EQU 0x400108c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG5 +CYREG_B0_P4_U1_CFG5 EQU 0x400108c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG6 +CYREG_B0_P4_U1_CFG6 EQU 0x400108c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG7 +CYREG_B0_P4_U1_CFG7 EQU 0x400108c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG8 +CYREG_B0_P4_U1_CFG8 EQU 0x400108c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG9 +CYREG_B0_P4_U1_CFG9 EQU 0x400108c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG10 +CYREG_B0_P4_U1_CFG10 EQU 0x400108ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG11 +CYREG_B0_P4_U1_CFG11 EQU 0x400108cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG12 +CYREG_B0_P4_U1_CFG12 EQU 0x400108cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG13 +CYREG_B0_P4_U1_CFG13 EQU 0x400108cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG14 +CYREG_B0_P4_U1_CFG14 EQU 0x400108ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG15 +CYREG_B0_P4_U1_CFG15 EQU 0x400108cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG16 +CYREG_B0_P4_U1_CFG16 EQU 0x400108d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG17 +CYREG_B0_P4_U1_CFG17 EQU 0x400108d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG18 +CYREG_B0_P4_U1_CFG18 EQU 0x400108d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG19 +CYREG_B0_P4_U1_CFG19 EQU 0x400108d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG20 +CYREG_B0_P4_U1_CFG20 EQU 0x400108d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG21 +CYREG_B0_P4_U1_CFG21 EQU 0x400108d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG22 +CYREG_B0_P4_U1_CFG22 EQU 0x400108d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG23 +CYREG_B0_P4_U1_CFG23 EQU 0x400108d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG24 +CYREG_B0_P4_U1_CFG24 EQU 0x400108d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG25 +CYREG_B0_P4_U1_CFG25 EQU 0x400108d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG26 +CYREG_B0_P4_U1_CFG26 EQU 0x400108da + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG27 +CYREG_B0_P4_U1_CFG27 EQU 0x400108db + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG28 +CYREG_B0_P4_U1_CFG28 EQU 0x400108dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG29 +CYREG_B0_P4_U1_CFG29 EQU 0x400108dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG30 +CYREG_B0_P4_U1_CFG30 EQU 0x400108de + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG31 +CYREG_B0_P4_U1_CFG31 EQU 0x400108df + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG0 +CYREG_B0_P4_U1_DCFG0 EQU 0x400108e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG1 +CYREG_B0_P4_U1_DCFG1 EQU 0x400108e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG2 +CYREG_B0_P4_U1_DCFG2 EQU 0x400108e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG3 +CYREG_B0_P4_U1_DCFG3 EQU 0x400108e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG4 +CYREG_B0_P4_U1_DCFG4 EQU 0x400108e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG5 +CYREG_B0_P4_U1_DCFG5 EQU 0x400108ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG6 +CYREG_B0_P4_U1_DCFG6 EQU 0x400108ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG7 +CYREG_B0_P4_U1_DCFG7 EQU 0x400108ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_BASE +CYDEV_UCFG_B0_P4_ROUTE_BASE EQU 0x40010900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_SIZE +CYDEV_UCFG_B0_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_BASE +CYDEV_UCFG_B0_P5_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_SIZE +CYDEV_UCFG_B0_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_BASE +CYDEV_UCFG_B0_P5_U0_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_SIZE +CYDEV_UCFG_B0_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT0 +CYREG_B0_P5_U0_PLD_IT0 EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT1 +CYREG_B0_P5_U0_PLD_IT1 EQU 0x40010a04 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT2 +CYREG_B0_P5_U0_PLD_IT2 EQU 0x40010a08 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT3 +CYREG_B0_P5_U0_PLD_IT3 EQU 0x40010a0c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT4 +CYREG_B0_P5_U0_PLD_IT4 EQU 0x40010a10 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT5 +CYREG_B0_P5_U0_PLD_IT5 EQU 0x40010a14 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT6 +CYREG_B0_P5_U0_PLD_IT6 EQU 0x40010a18 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT7 +CYREG_B0_P5_U0_PLD_IT7 EQU 0x40010a1c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT8 +CYREG_B0_P5_U0_PLD_IT8 EQU 0x40010a20 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT9 +CYREG_B0_P5_U0_PLD_IT9 EQU 0x40010a24 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT10 +CYREG_B0_P5_U0_PLD_IT10 EQU 0x40010a28 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT11 +CYREG_B0_P5_U0_PLD_IT11 EQU 0x40010a2c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT0 +CYREG_B0_P5_U0_PLD_ORT0 EQU 0x40010a30 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT1 +CYREG_B0_P5_U0_PLD_ORT1 EQU 0x40010a32 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT2 +CYREG_B0_P5_U0_PLD_ORT2 EQU 0x40010a34 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT3 +CYREG_B0_P5_U0_PLD_ORT3 EQU 0x40010a36 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_CEN_CONST +CYREG_B0_P5_U0_MC_CFG_CEN_CONST EQU 0x40010a38 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_XORFB +CYREG_B0_P5_U0_MC_CFG_XORFB EQU 0x40010a3a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_SET_RESET +CYREG_B0_P5_U0_MC_CFG_SET_RESET EQU 0x40010a3c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_BYPASS +CYREG_B0_P5_U0_MC_CFG_BYPASS EQU 0x40010a3e + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG0 +CYREG_B0_P5_U0_CFG0 EQU 0x40010a40 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG1 +CYREG_B0_P5_U0_CFG1 EQU 0x40010a41 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG2 +CYREG_B0_P5_U0_CFG2 EQU 0x40010a42 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG3 +CYREG_B0_P5_U0_CFG3 EQU 0x40010a43 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG4 +CYREG_B0_P5_U0_CFG4 EQU 0x40010a44 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG5 +CYREG_B0_P5_U0_CFG5 EQU 0x40010a45 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG6 +CYREG_B0_P5_U0_CFG6 EQU 0x40010a46 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG7 +CYREG_B0_P5_U0_CFG7 EQU 0x40010a47 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG8 +CYREG_B0_P5_U0_CFG8 EQU 0x40010a48 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG9 +CYREG_B0_P5_U0_CFG9 EQU 0x40010a49 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG10 +CYREG_B0_P5_U0_CFG10 EQU 0x40010a4a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG11 +CYREG_B0_P5_U0_CFG11 EQU 0x40010a4b + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG12 +CYREG_B0_P5_U0_CFG12 EQU 0x40010a4c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG13 +CYREG_B0_P5_U0_CFG13 EQU 0x40010a4d + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG14 +CYREG_B0_P5_U0_CFG14 EQU 0x40010a4e + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG15 +CYREG_B0_P5_U0_CFG15 EQU 0x40010a4f + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG16 +CYREG_B0_P5_U0_CFG16 EQU 0x40010a50 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG17 +CYREG_B0_P5_U0_CFG17 EQU 0x40010a51 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG18 +CYREG_B0_P5_U0_CFG18 EQU 0x40010a52 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG19 +CYREG_B0_P5_U0_CFG19 EQU 0x40010a53 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG20 +CYREG_B0_P5_U0_CFG20 EQU 0x40010a54 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG21 +CYREG_B0_P5_U0_CFG21 EQU 0x40010a55 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG22 +CYREG_B0_P5_U0_CFG22 EQU 0x40010a56 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG23 +CYREG_B0_P5_U0_CFG23 EQU 0x40010a57 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG24 +CYREG_B0_P5_U0_CFG24 EQU 0x40010a58 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG25 +CYREG_B0_P5_U0_CFG25 EQU 0x40010a59 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG26 +CYREG_B0_P5_U0_CFG26 EQU 0x40010a5a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG27 +CYREG_B0_P5_U0_CFG27 EQU 0x40010a5b + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG28 +CYREG_B0_P5_U0_CFG28 EQU 0x40010a5c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG29 +CYREG_B0_P5_U0_CFG29 EQU 0x40010a5d + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG30 +CYREG_B0_P5_U0_CFG30 EQU 0x40010a5e + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG31 +CYREG_B0_P5_U0_CFG31 EQU 0x40010a5f + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG0 +CYREG_B0_P5_U0_DCFG0 EQU 0x40010a60 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG1 +CYREG_B0_P5_U0_DCFG1 EQU 0x40010a62 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG2 +CYREG_B0_P5_U0_DCFG2 EQU 0x40010a64 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG3 +CYREG_B0_P5_U0_DCFG3 EQU 0x40010a66 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG4 +CYREG_B0_P5_U0_DCFG4 EQU 0x40010a68 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG5 +CYREG_B0_P5_U0_DCFG5 EQU 0x40010a6a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG6 +CYREG_B0_P5_U0_DCFG6 EQU 0x40010a6c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG7 +CYREG_B0_P5_U0_DCFG7 EQU 0x40010a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_BASE +CYDEV_UCFG_B0_P5_U1_BASE EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_SIZE +CYDEV_UCFG_B0_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT0 +CYREG_B0_P5_U1_PLD_IT0 EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT1 +CYREG_B0_P5_U1_PLD_IT1 EQU 0x40010a84 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT2 +CYREG_B0_P5_U1_PLD_IT2 EQU 0x40010a88 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT3 +CYREG_B0_P5_U1_PLD_IT3 EQU 0x40010a8c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT4 +CYREG_B0_P5_U1_PLD_IT4 EQU 0x40010a90 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT5 +CYREG_B0_P5_U1_PLD_IT5 EQU 0x40010a94 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT6 +CYREG_B0_P5_U1_PLD_IT6 EQU 0x40010a98 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT7 +CYREG_B0_P5_U1_PLD_IT7 EQU 0x40010a9c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT8 +CYREG_B0_P5_U1_PLD_IT8 EQU 0x40010aa0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT9 +CYREG_B0_P5_U1_PLD_IT9 EQU 0x40010aa4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT10 +CYREG_B0_P5_U1_PLD_IT10 EQU 0x40010aa8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT11 +CYREG_B0_P5_U1_PLD_IT11 EQU 0x40010aac + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT0 +CYREG_B0_P5_U1_PLD_ORT0 EQU 0x40010ab0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT1 +CYREG_B0_P5_U1_PLD_ORT1 EQU 0x40010ab2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT2 +CYREG_B0_P5_U1_PLD_ORT2 EQU 0x40010ab4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT3 +CYREG_B0_P5_U1_PLD_ORT3 EQU 0x40010ab6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_CEN_CONST +CYREG_B0_P5_U1_MC_CFG_CEN_CONST EQU 0x40010ab8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_XORFB +CYREG_B0_P5_U1_MC_CFG_XORFB EQU 0x40010aba + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_SET_RESET +CYREG_B0_P5_U1_MC_CFG_SET_RESET EQU 0x40010abc + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_BYPASS +CYREG_B0_P5_U1_MC_CFG_BYPASS EQU 0x40010abe + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG0 +CYREG_B0_P5_U1_CFG0 EQU 0x40010ac0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG1 +CYREG_B0_P5_U1_CFG1 EQU 0x40010ac1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG2 +CYREG_B0_P5_U1_CFG2 EQU 0x40010ac2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG3 +CYREG_B0_P5_U1_CFG3 EQU 0x40010ac3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG4 +CYREG_B0_P5_U1_CFG4 EQU 0x40010ac4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG5 +CYREG_B0_P5_U1_CFG5 EQU 0x40010ac5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG6 +CYREG_B0_P5_U1_CFG6 EQU 0x40010ac6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG7 +CYREG_B0_P5_U1_CFG7 EQU 0x40010ac7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG8 +CYREG_B0_P5_U1_CFG8 EQU 0x40010ac8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG9 +CYREG_B0_P5_U1_CFG9 EQU 0x40010ac9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG10 +CYREG_B0_P5_U1_CFG10 EQU 0x40010aca + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG11 +CYREG_B0_P5_U1_CFG11 EQU 0x40010acb + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG12 +CYREG_B0_P5_U1_CFG12 EQU 0x40010acc + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG13 +CYREG_B0_P5_U1_CFG13 EQU 0x40010acd + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG14 +CYREG_B0_P5_U1_CFG14 EQU 0x40010ace + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG15 +CYREG_B0_P5_U1_CFG15 EQU 0x40010acf + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG16 +CYREG_B0_P5_U1_CFG16 EQU 0x40010ad0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG17 +CYREG_B0_P5_U1_CFG17 EQU 0x40010ad1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG18 +CYREG_B0_P5_U1_CFG18 EQU 0x40010ad2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG19 +CYREG_B0_P5_U1_CFG19 EQU 0x40010ad3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG20 +CYREG_B0_P5_U1_CFG20 EQU 0x40010ad4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG21 +CYREG_B0_P5_U1_CFG21 EQU 0x40010ad5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG22 +CYREG_B0_P5_U1_CFG22 EQU 0x40010ad6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG23 +CYREG_B0_P5_U1_CFG23 EQU 0x40010ad7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG24 +CYREG_B0_P5_U1_CFG24 EQU 0x40010ad8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG25 +CYREG_B0_P5_U1_CFG25 EQU 0x40010ad9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG26 +CYREG_B0_P5_U1_CFG26 EQU 0x40010ada + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG27 +CYREG_B0_P5_U1_CFG27 EQU 0x40010adb + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG28 +CYREG_B0_P5_U1_CFG28 EQU 0x40010adc + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG29 +CYREG_B0_P5_U1_CFG29 EQU 0x40010add + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG30 +CYREG_B0_P5_U1_CFG30 EQU 0x40010ade + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG31 +CYREG_B0_P5_U1_CFG31 EQU 0x40010adf + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG0 +CYREG_B0_P5_U1_DCFG0 EQU 0x40010ae0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG1 +CYREG_B0_P5_U1_DCFG1 EQU 0x40010ae2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG2 +CYREG_B0_P5_U1_DCFG2 EQU 0x40010ae4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG3 +CYREG_B0_P5_U1_DCFG3 EQU 0x40010ae6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG4 +CYREG_B0_P5_U1_DCFG4 EQU 0x40010ae8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG5 +CYREG_B0_P5_U1_DCFG5 EQU 0x40010aea + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG6 +CYREG_B0_P5_U1_DCFG6 EQU 0x40010aec + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG7 +CYREG_B0_P5_U1_DCFG7 EQU 0x40010aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_BASE +CYDEV_UCFG_B0_P5_ROUTE_BASE EQU 0x40010b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_SIZE +CYDEV_UCFG_B0_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_BASE +CYDEV_UCFG_B0_P6_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_SIZE +CYDEV_UCFG_B0_P6_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_BASE +CYDEV_UCFG_B0_P6_U0_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_SIZE +CYDEV_UCFG_B0_P6_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT0 +CYREG_B0_P6_U0_PLD_IT0 EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT1 +CYREG_B0_P6_U0_PLD_IT1 EQU 0x40010c04 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT2 +CYREG_B0_P6_U0_PLD_IT2 EQU 0x40010c08 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT3 +CYREG_B0_P6_U0_PLD_IT3 EQU 0x40010c0c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT4 +CYREG_B0_P6_U0_PLD_IT4 EQU 0x40010c10 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT5 +CYREG_B0_P6_U0_PLD_IT5 EQU 0x40010c14 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT6 +CYREG_B0_P6_U0_PLD_IT6 EQU 0x40010c18 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT7 +CYREG_B0_P6_U0_PLD_IT7 EQU 0x40010c1c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT8 +CYREG_B0_P6_U0_PLD_IT8 EQU 0x40010c20 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT9 +CYREG_B0_P6_U0_PLD_IT9 EQU 0x40010c24 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT10 +CYREG_B0_P6_U0_PLD_IT10 EQU 0x40010c28 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT11 +CYREG_B0_P6_U0_PLD_IT11 EQU 0x40010c2c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT0 +CYREG_B0_P6_U0_PLD_ORT0 EQU 0x40010c30 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT1 +CYREG_B0_P6_U0_PLD_ORT1 EQU 0x40010c32 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT2 +CYREG_B0_P6_U0_PLD_ORT2 EQU 0x40010c34 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT3 +CYREG_B0_P6_U0_PLD_ORT3 EQU 0x40010c36 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_CEN_CONST +CYREG_B0_P6_U0_MC_CFG_CEN_CONST EQU 0x40010c38 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_XORFB +CYREG_B0_P6_U0_MC_CFG_XORFB EQU 0x40010c3a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_SET_RESET +CYREG_B0_P6_U0_MC_CFG_SET_RESET EQU 0x40010c3c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_BYPASS +CYREG_B0_P6_U0_MC_CFG_BYPASS EQU 0x40010c3e + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG0 +CYREG_B0_P6_U0_CFG0 EQU 0x40010c40 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG1 +CYREG_B0_P6_U0_CFG1 EQU 0x40010c41 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG2 +CYREG_B0_P6_U0_CFG2 EQU 0x40010c42 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG3 +CYREG_B0_P6_U0_CFG3 EQU 0x40010c43 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG4 +CYREG_B0_P6_U0_CFG4 EQU 0x40010c44 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG5 +CYREG_B0_P6_U0_CFG5 EQU 0x40010c45 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG6 +CYREG_B0_P6_U0_CFG6 EQU 0x40010c46 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG7 +CYREG_B0_P6_U0_CFG7 EQU 0x40010c47 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG8 +CYREG_B0_P6_U0_CFG8 EQU 0x40010c48 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG9 +CYREG_B0_P6_U0_CFG9 EQU 0x40010c49 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG10 +CYREG_B0_P6_U0_CFG10 EQU 0x40010c4a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG11 +CYREG_B0_P6_U0_CFG11 EQU 0x40010c4b + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG12 +CYREG_B0_P6_U0_CFG12 EQU 0x40010c4c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG13 +CYREG_B0_P6_U0_CFG13 EQU 0x40010c4d + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG14 +CYREG_B0_P6_U0_CFG14 EQU 0x40010c4e + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG15 +CYREG_B0_P6_U0_CFG15 EQU 0x40010c4f + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG16 +CYREG_B0_P6_U0_CFG16 EQU 0x40010c50 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG17 +CYREG_B0_P6_U0_CFG17 EQU 0x40010c51 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG18 +CYREG_B0_P6_U0_CFG18 EQU 0x40010c52 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG19 +CYREG_B0_P6_U0_CFG19 EQU 0x40010c53 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG20 +CYREG_B0_P6_U0_CFG20 EQU 0x40010c54 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG21 +CYREG_B0_P6_U0_CFG21 EQU 0x40010c55 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG22 +CYREG_B0_P6_U0_CFG22 EQU 0x40010c56 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG23 +CYREG_B0_P6_U0_CFG23 EQU 0x40010c57 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG24 +CYREG_B0_P6_U0_CFG24 EQU 0x40010c58 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG25 +CYREG_B0_P6_U0_CFG25 EQU 0x40010c59 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG26 +CYREG_B0_P6_U0_CFG26 EQU 0x40010c5a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG27 +CYREG_B0_P6_U0_CFG27 EQU 0x40010c5b + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG28 +CYREG_B0_P6_U0_CFG28 EQU 0x40010c5c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG29 +CYREG_B0_P6_U0_CFG29 EQU 0x40010c5d + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG30 +CYREG_B0_P6_U0_CFG30 EQU 0x40010c5e + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG31 +CYREG_B0_P6_U0_CFG31 EQU 0x40010c5f + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG0 +CYREG_B0_P6_U0_DCFG0 EQU 0x40010c60 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG1 +CYREG_B0_P6_U0_DCFG1 EQU 0x40010c62 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG2 +CYREG_B0_P6_U0_DCFG2 EQU 0x40010c64 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG3 +CYREG_B0_P6_U0_DCFG3 EQU 0x40010c66 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG4 +CYREG_B0_P6_U0_DCFG4 EQU 0x40010c68 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG5 +CYREG_B0_P6_U0_DCFG5 EQU 0x40010c6a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG6 +CYREG_B0_P6_U0_DCFG6 EQU 0x40010c6c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG7 +CYREG_B0_P6_U0_DCFG7 EQU 0x40010c6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_BASE +CYDEV_UCFG_B0_P6_U1_BASE EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_SIZE +CYDEV_UCFG_B0_P6_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT0 +CYREG_B0_P6_U1_PLD_IT0 EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT1 +CYREG_B0_P6_U1_PLD_IT1 EQU 0x40010c84 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT2 +CYREG_B0_P6_U1_PLD_IT2 EQU 0x40010c88 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT3 +CYREG_B0_P6_U1_PLD_IT3 EQU 0x40010c8c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT4 +CYREG_B0_P6_U1_PLD_IT4 EQU 0x40010c90 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT5 +CYREG_B0_P6_U1_PLD_IT5 EQU 0x40010c94 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT6 +CYREG_B0_P6_U1_PLD_IT6 EQU 0x40010c98 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT7 +CYREG_B0_P6_U1_PLD_IT7 EQU 0x40010c9c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT8 +CYREG_B0_P6_U1_PLD_IT8 EQU 0x40010ca0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT9 +CYREG_B0_P6_U1_PLD_IT9 EQU 0x40010ca4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT10 +CYREG_B0_P6_U1_PLD_IT10 EQU 0x40010ca8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT11 +CYREG_B0_P6_U1_PLD_IT11 EQU 0x40010cac + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT0 +CYREG_B0_P6_U1_PLD_ORT0 EQU 0x40010cb0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT1 +CYREG_B0_P6_U1_PLD_ORT1 EQU 0x40010cb2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT2 +CYREG_B0_P6_U1_PLD_ORT2 EQU 0x40010cb4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT3 +CYREG_B0_P6_U1_PLD_ORT3 EQU 0x40010cb6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_CEN_CONST +CYREG_B0_P6_U1_MC_CFG_CEN_CONST EQU 0x40010cb8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_XORFB +CYREG_B0_P6_U1_MC_CFG_XORFB EQU 0x40010cba + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_SET_RESET +CYREG_B0_P6_U1_MC_CFG_SET_RESET EQU 0x40010cbc + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_BYPASS +CYREG_B0_P6_U1_MC_CFG_BYPASS EQU 0x40010cbe + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG0 +CYREG_B0_P6_U1_CFG0 EQU 0x40010cc0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG1 +CYREG_B0_P6_U1_CFG1 EQU 0x40010cc1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG2 +CYREG_B0_P6_U1_CFG2 EQU 0x40010cc2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG3 +CYREG_B0_P6_U1_CFG3 EQU 0x40010cc3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG4 +CYREG_B0_P6_U1_CFG4 EQU 0x40010cc4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG5 +CYREG_B0_P6_U1_CFG5 EQU 0x40010cc5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG6 +CYREG_B0_P6_U1_CFG6 EQU 0x40010cc6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG7 +CYREG_B0_P6_U1_CFG7 EQU 0x40010cc7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG8 +CYREG_B0_P6_U1_CFG8 EQU 0x40010cc8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG9 +CYREG_B0_P6_U1_CFG9 EQU 0x40010cc9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG10 +CYREG_B0_P6_U1_CFG10 EQU 0x40010cca + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG11 +CYREG_B0_P6_U1_CFG11 EQU 0x40010ccb + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG12 +CYREG_B0_P6_U1_CFG12 EQU 0x40010ccc + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG13 +CYREG_B0_P6_U1_CFG13 EQU 0x40010ccd + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG14 +CYREG_B0_P6_U1_CFG14 EQU 0x40010cce + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG15 +CYREG_B0_P6_U1_CFG15 EQU 0x40010ccf + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG16 +CYREG_B0_P6_U1_CFG16 EQU 0x40010cd0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG17 +CYREG_B0_P6_U1_CFG17 EQU 0x40010cd1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG18 +CYREG_B0_P6_U1_CFG18 EQU 0x40010cd2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG19 +CYREG_B0_P6_U1_CFG19 EQU 0x40010cd3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG20 +CYREG_B0_P6_U1_CFG20 EQU 0x40010cd4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG21 +CYREG_B0_P6_U1_CFG21 EQU 0x40010cd5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG22 +CYREG_B0_P6_U1_CFG22 EQU 0x40010cd6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG23 +CYREG_B0_P6_U1_CFG23 EQU 0x40010cd7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG24 +CYREG_B0_P6_U1_CFG24 EQU 0x40010cd8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG25 +CYREG_B0_P6_U1_CFG25 EQU 0x40010cd9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG26 +CYREG_B0_P6_U1_CFG26 EQU 0x40010cda + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG27 +CYREG_B0_P6_U1_CFG27 EQU 0x40010cdb + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG28 +CYREG_B0_P6_U1_CFG28 EQU 0x40010cdc + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG29 +CYREG_B0_P6_U1_CFG29 EQU 0x40010cdd + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG30 +CYREG_B0_P6_U1_CFG30 EQU 0x40010cde + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG31 +CYREG_B0_P6_U1_CFG31 EQU 0x40010cdf + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG0 +CYREG_B0_P6_U1_DCFG0 EQU 0x40010ce0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG1 +CYREG_B0_P6_U1_DCFG1 EQU 0x40010ce2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG2 +CYREG_B0_P6_U1_DCFG2 EQU 0x40010ce4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG3 +CYREG_B0_P6_U1_DCFG3 EQU 0x40010ce6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG4 +CYREG_B0_P6_U1_DCFG4 EQU 0x40010ce8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG5 +CYREG_B0_P6_U1_DCFG5 EQU 0x40010cea + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG6 +CYREG_B0_P6_U1_DCFG6 EQU 0x40010cec + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG7 +CYREG_B0_P6_U1_DCFG7 EQU 0x40010cee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_BASE +CYDEV_UCFG_B0_P6_ROUTE_BASE EQU 0x40010d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_SIZE +CYDEV_UCFG_B0_P6_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_BASE +CYDEV_UCFG_B0_P7_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_SIZE +CYDEV_UCFG_B0_P7_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_BASE +CYDEV_UCFG_B0_P7_U0_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_SIZE +CYDEV_UCFG_B0_P7_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT0 +CYREG_B0_P7_U0_PLD_IT0 EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT1 +CYREG_B0_P7_U0_PLD_IT1 EQU 0x40010e04 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT2 +CYREG_B0_P7_U0_PLD_IT2 EQU 0x40010e08 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT3 +CYREG_B0_P7_U0_PLD_IT3 EQU 0x40010e0c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT4 +CYREG_B0_P7_U0_PLD_IT4 EQU 0x40010e10 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT5 +CYREG_B0_P7_U0_PLD_IT5 EQU 0x40010e14 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT6 +CYREG_B0_P7_U0_PLD_IT6 EQU 0x40010e18 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT7 +CYREG_B0_P7_U0_PLD_IT7 EQU 0x40010e1c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT8 +CYREG_B0_P7_U0_PLD_IT8 EQU 0x40010e20 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT9 +CYREG_B0_P7_U0_PLD_IT9 EQU 0x40010e24 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT10 +CYREG_B0_P7_U0_PLD_IT10 EQU 0x40010e28 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT11 +CYREG_B0_P7_U0_PLD_IT11 EQU 0x40010e2c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT0 +CYREG_B0_P7_U0_PLD_ORT0 EQU 0x40010e30 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT1 +CYREG_B0_P7_U0_PLD_ORT1 EQU 0x40010e32 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT2 +CYREG_B0_P7_U0_PLD_ORT2 EQU 0x40010e34 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT3 +CYREG_B0_P7_U0_PLD_ORT3 EQU 0x40010e36 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_CEN_CONST +CYREG_B0_P7_U0_MC_CFG_CEN_CONST EQU 0x40010e38 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_XORFB +CYREG_B0_P7_U0_MC_CFG_XORFB EQU 0x40010e3a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_SET_RESET +CYREG_B0_P7_U0_MC_CFG_SET_RESET EQU 0x40010e3c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_BYPASS +CYREG_B0_P7_U0_MC_CFG_BYPASS EQU 0x40010e3e + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG0 +CYREG_B0_P7_U0_CFG0 EQU 0x40010e40 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG1 +CYREG_B0_P7_U0_CFG1 EQU 0x40010e41 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG2 +CYREG_B0_P7_U0_CFG2 EQU 0x40010e42 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG3 +CYREG_B0_P7_U0_CFG3 EQU 0x40010e43 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG4 +CYREG_B0_P7_U0_CFG4 EQU 0x40010e44 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG5 +CYREG_B0_P7_U0_CFG5 EQU 0x40010e45 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG6 +CYREG_B0_P7_U0_CFG6 EQU 0x40010e46 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG7 +CYREG_B0_P7_U0_CFG7 EQU 0x40010e47 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG8 +CYREG_B0_P7_U0_CFG8 EQU 0x40010e48 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG9 +CYREG_B0_P7_U0_CFG9 EQU 0x40010e49 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG10 +CYREG_B0_P7_U0_CFG10 EQU 0x40010e4a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG11 +CYREG_B0_P7_U0_CFG11 EQU 0x40010e4b + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG12 +CYREG_B0_P7_U0_CFG12 EQU 0x40010e4c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG13 +CYREG_B0_P7_U0_CFG13 EQU 0x40010e4d + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG14 +CYREG_B0_P7_U0_CFG14 EQU 0x40010e4e + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG15 +CYREG_B0_P7_U0_CFG15 EQU 0x40010e4f + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG16 +CYREG_B0_P7_U0_CFG16 EQU 0x40010e50 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG17 +CYREG_B0_P7_U0_CFG17 EQU 0x40010e51 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG18 +CYREG_B0_P7_U0_CFG18 EQU 0x40010e52 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG19 +CYREG_B0_P7_U0_CFG19 EQU 0x40010e53 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG20 +CYREG_B0_P7_U0_CFG20 EQU 0x40010e54 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG21 +CYREG_B0_P7_U0_CFG21 EQU 0x40010e55 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG22 +CYREG_B0_P7_U0_CFG22 EQU 0x40010e56 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG23 +CYREG_B0_P7_U0_CFG23 EQU 0x40010e57 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG24 +CYREG_B0_P7_U0_CFG24 EQU 0x40010e58 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG25 +CYREG_B0_P7_U0_CFG25 EQU 0x40010e59 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG26 +CYREG_B0_P7_U0_CFG26 EQU 0x40010e5a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG27 +CYREG_B0_P7_U0_CFG27 EQU 0x40010e5b + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG28 +CYREG_B0_P7_U0_CFG28 EQU 0x40010e5c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG29 +CYREG_B0_P7_U0_CFG29 EQU 0x40010e5d + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG30 +CYREG_B0_P7_U0_CFG30 EQU 0x40010e5e + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG31 +CYREG_B0_P7_U0_CFG31 EQU 0x40010e5f + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG0 +CYREG_B0_P7_U0_DCFG0 EQU 0x40010e60 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG1 +CYREG_B0_P7_U0_DCFG1 EQU 0x40010e62 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG2 +CYREG_B0_P7_U0_DCFG2 EQU 0x40010e64 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG3 +CYREG_B0_P7_U0_DCFG3 EQU 0x40010e66 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG4 +CYREG_B0_P7_U0_DCFG4 EQU 0x40010e68 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG5 +CYREG_B0_P7_U0_DCFG5 EQU 0x40010e6a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG6 +CYREG_B0_P7_U0_DCFG6 EQU 0x40010e6c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG7 +CYREG_B0_P7_U0_DCFG7 EQU 0x40010e6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_BASE +CYDEV_UCFG_B0_P7_U1_BASE EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_SIZE +CYDEV_UCFG_B0_P7_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT0 +CYREG_B0_P7_U1_PLD_IT0 EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT1 +CYREG_B0_P7_U1_PLD_IT1 EQU 0x40010e84 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT2 +CYREG_B0_P7_U1_PLD_IT2 EQU 0x40010e88 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT3 +CYREG_B0_P7_U1_PLD_IT3 EQU 0x40010e8c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT4 +CYREG_B0_P7_U1_PLD_IT4 EQU 0x40010e90 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT5 +CYREG_B0_P7_U1_PLD_IT5 EQU 0x40010e94 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT6 +CYREG_B0_P7_U1_PLD_IT6 EQU 0x40010e98 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT7 +CYREG_B0_P7_U1_PLD_IT7 EQU 0x40010e9c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT8 +CYREG_B0_P7_U1_PLD_IT8 EQU 0x40010ea0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT9 +CYREG_B0_P7_U1_PLD_IT9 EQU 0x40010ea4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT10 +CYREG_B0_P7_U1_PLD_IT10 EQU 0x40010ea8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT11 +CYREG_B0_P7_U1_PLD_IT11 EQU 0x40010eac + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT0 +CYREG_B0_P7_U1_PLD_ORT0 EQU 0x40010eb0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT1 +CYREG_B0_P7_U1_PLD_ORT1 EQU 0x40010eb2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT2 +CYREG_B0_P7_U1_PLD_ORT2 EQU 0x40010eb4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT3 +CYREG_B0_P7_U1_PLD_ORT3 EQU 0x40010eb6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_CEN_CONST +CYREG_B0_P7_U1_MC_CFG_CEN_CONST EQU 0x40010eb8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_XORFB +CYREG_B0_P7_U1_MC_CFG_XORFB EQU 0x40010eba + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_SET_RESET +CYREG_B0_P7_U1_MC_CFG_SET_RESET EQU 0x40010ebc + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_BYPASS +CYREG_B0_P7_U1_MC_CFG_BYPASS EQU 0x40010ebe + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG0 +CYREG_B0_P7_U1_CFG0 EQU 0x40010ec0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG1 +CYREG_B0_P7_U1_CFG1 EQU 0x40010ec1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG2 +CYREG_B0_P7_U1_CFG2 EQU 0x40010ec2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG3 +CYREG_B0_P7_U1_CFG3 EQU 0x40010ec3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG4 +CYREG_B0_P7_U1_CFG4 EQU 0x40010ec4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG5 +CYREG_B0_P7_U1_CFG5 EQU 0x40010ec5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG6 +CYREG_B0_P7_U1_CFG6 EQU 0x40010ec6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG7 +CYREG_B0_P7_U1_CFG7 EQU 0x40010ec7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG8 +CYREG_B0_P7_U1_CFG8 EQU 0x40010ec8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG9 +CYREG_B0_P7_U1_CFG9 EQU 0x40010ec9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG10 +CYREG_B0_P7_U1_CFG10 EQU 0x40010eca + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG11 +CYREG_B0_P7_U1_CFG11 EQU 0x40010ecb + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG12 +CYREG_B0_P7_U1_CFG12 EQU 0x40010ecc + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG13 +CYREG_B0_P7_U1_CFG13 EQU 0x40010ecd + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG14 +CYREG_B0_P7_U1_CFG14 EQU 0x40010ece + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG15 +CYREG_B0_P7_U1_CFG15 EQU 0x40010ecf + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG16 +CYREG_B0_P7_U1_CFG16 EQU 0x40010ed0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG17 +CYREG_B0_P7_U1_CFG17 EQU 0x40010ed1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG18 +CYREG_B0_P7_U1_CFG18 EQU 0x40010ed2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG19 +CYREG_B0_P7_U1_CFG19 EQU 0x40010ed3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG20 +CYREG_B0_P7_U1_CFG20 EQU 0x40010ed4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG21 +CYREG_B0_P7_U1_CFG21 EQU 0x40010ed5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG22 +CYREG_B0_P7_U1_CFG22 EQU 0x40010ed6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG23 +CYREG_B0_P7_U1_CFG23 EQU 0x40010ed7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG24 +CYREG_B0_P7_U1_CFG24 EQU 0x40010ed8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG25 +CYREG_B0_P7_U1_CFG25 EQU 0x40010ed9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG26 +CYREG_B0_P7_U1_CFG26 EQU 0x40010eda + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG27 +CYREG_B0_P7_U1_CFG27 EQU 0x40010edb + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG28 +CYREG_B0_P7_U1_CFG28 EQU 0x40010edc + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG29 +CYREG_B0_P7_U1_CFG29 EQU 0x40010edd + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG30 +CYREG_B0_P7_U1_CFG30 EQU 0x40010ede + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG31 +CYREG_B0_P7_U1_CFG31 EQU 0x40010edf + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG0 +CYREG_B0_P7_U1_DCFG0 EQU 0x40010ee0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG1 +CYREG_B0_P7_U1_DCFG1 EQU 0x40010ee2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG2 +CYREG_B0_P7_U1_DCFG2 EQU 0x40010ee4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG3 +CYREG_B0_P7_U1_DCFG3 EQU 0x40010ee6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG4 +CYREG_B0_P7_U1_DCFG4 EQU 0x40010ee8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG5 +CYREG_B0_P7_U1_DCFG5 EQU 0x40010eea + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG6 +CYREG_B0_P7_U1_DCFG6 EQU 0x40010eec + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG7 +CYREG_B0_P7_U1_DCFG7 EQU 0x40010eee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_BASE +CYDEV_UCFG_B0_P7_ROUTE_BASE EQU 0x40010f00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_SIZE +CYDEV_UCFG_B0_P7_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_BASE +CYDEV_UCFG_B1_BASE EQU 0x40011000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_SIZE +CYDEV_UCFG_B1_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_BASE +CYDEV_UCFG_B1_P2_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_SIZE +CYDEV_UCFG_B1_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_BASE +CYDEV_UCFG_B1_P2_U0_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_SIZE +CYDEV_UCFG_B1_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT0 +CYREG_B1_P2_U0_PLD_IT0 EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT1 +CYREG_B1_P2_U0_PLD_IT1 EQU 0x40011404 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT2 +CYREG_B1_P2_U0_PLD_IT2 EQU 0x40011408 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT3 +CYREG_B1_P2_U0_PLD_IT3 EQU 0x4001140c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT4 +CYREG_B1_P2_U0_PLD_IT4 EQU 0x40011410 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT5 +CYREG_B1_P2_U0_PLD_IT5 EQU 0x40011414 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT6 +CYREG_B1_P2_U0_PLD_IT6 EQU 0x40011418 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT7 +CYREG_B1_P2_U0_PLD_IT7 EQU 0x4001141c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT8 +CYREG_B1_P2_U0_PLD_IT8 EQU 0x40011420 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT9 +CYREG_B1_P2_U0_PLD_IT9 EQU 0x40011424 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT10 +CYREG_B1_P2_U0_PLD_IT10 EQU 0x40011428 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT11 +CYREG_B1_P2_U0_PLD_IT11 EQU 0x4001142c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT0 +CYREG_B1_P2_U0_PLD_ORT0 EQU 0x40011430 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT1 +CYREG_B1_P2_U0_PLD_ORT1 EQU 0x40011432 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT2 +CYREG_B1_P2_U0_PLD_ORT2 EQU 0x40011434 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT3 +CYREG_B1_P2_U0_PLD_ORT3 EQU 0x40011436 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_CEN_CONST +CYREG_B1_P2_U0_MC_CFG_CEN_CONST EQU 0x40011438 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_XORFB +CYREG_B1_P2_U0_MC_CFG_XORFB EQU 0x4001143a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_SET_RESET +CYREG_B1_P2_U0_MC_CFG_SET_RESET EQU 0x4001143c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_BYPASS +CYREG_B1_P2_U0_MC_CFG_BYPASS EQU 0x4001143e + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG0 +CYREG_B1_P2_U0_CFG0 EQU 0x40011440 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG1 +CYREG_B1_P2_U0_CFG1 EQU 0x40011441 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG2 +CYREG_B1_P2_U0_CFG2 EQU 0x40011442 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG3 +CYREG_B1_P2_U0_CFG3 EQU 0x40011443 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG4 +CYREG_B1_P2_U0_CFG4 EQU 0x40011444 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG5 +CYREG_B1_P2_U0_CFG5 EQU 0x40011445 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG6 +CYREG_B1_P2_U0_CFG6 EQU 0x40011446 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG7 +CYREG_B1_P2_U0_CFG7 EQU 0x40011447 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG8 +CYREG_B1_P2_U0_CFG8 EQU 0x40011448 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG9 +CYREG_B1_P2_U0_CFG9 EQU 0x40011449 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG10 +CYREG_B1_P2_U0_CFG10 EQU 0x4001144a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG11 +CYREG_B1_P2_U0_CFG11 EQU 0x4001144b + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG12 +CYREG_B1_P2_U0_CFG12 EQU 0x4001144c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG13 +CYREG_B1_P2_U0_CFG13 EQU 0x4001144d + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG14 +CYREG_B1_P2_U0_CFG14 EQU 0x4001144e + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG15 +CYREG_B1_P2_U0_CFG15 EQU 0x4001144f + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG16 +CYREG_B1_P2_U0_CFG16 EQU 0x40011450 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG17 +CYREG_B1_P2_U0_CFG17 EQU 0x40011451 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG18 +CYREG_B1_P2_U0_CFG18 EQU 0x40011452 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG19 +CYREG_B1_P2_U0_CFG19 EQU 0x40011453 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG20 +CYREG_B1_P2_U0_CFG20 EQU 0x40011454 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG21 +CYREG_B1_P2_U0_CFG21 EQU 0x40011455 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG22 +CYREG_B1_P2_U0_CFG22 EQU 0x40011456 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG23 +CYREG_B1_P2_U0_CFG23 EQU 0x40011457 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG24 +CYREG_B1_P2_U0_CFG24 EQU 0x40011458 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG25 +CYREG_B1_P2_U0_CFG25 EQU 0x40011459 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG26 +CYREG_B1_P2_U0_CFG26 EQU 0x4001145a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG27 +CYREG_B1_P2_U0_CFG27 EQU 0x4001145b + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG28 +CYREG_B1_P2_U0_CFG28 EQU 0x4001145c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG29 +CYREG_B1_P2_U0_CFG29 EQU 0x4001145d + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG30 +CYREG_B1_P2_U0_CFG30 EQU 0x4001145e + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG31 +CYREG_B1_P2_U0_CFG31 EQU 0x4001145f + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG0 +CYREG_B1_P2_U0_DCFG0 EQU 0x40011460 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG1 +CYREG_B1_P2_U0_DCFG1 EQU 0x40011462 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG2 +CYREG_B1_P2_U0_DCFG2 EQU 0x40011464 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG3 +CYREG_B1_P2_U0_DCFG3 EQU 0x40011466 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG4 +CYREG_B1_P2_U0_DCFG4 EQU 0x40011468 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG5 +CYREG_B1_P2_U0_DCFG5 EQU 0x4001146a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG6 +CYREG_B1_P2_U0_DCFG6 EQU 0x4001146c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG7 +CYREG_B1_P2_U0_DCFG7 EQU 0x4001146e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_BASE +CYDEV_UCFG_B1_P2_U1_BASE EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_SIZE +CYDEV_UCFG_B1_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT0 +CYREG_B1_P2_U1_PLD_IT0 EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT1 +CYREG_B1_P2_U1_PLD_IT1 EQU 0x40011484 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT2 +CYREG_B1_P2_U1_PLD_IT2 EQU 0x40011488 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT3 +CYREG_B1_P2_U1_PLD_IT3 EQU 0x4001148c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT4 +CYREG_B1_P2_U1_PLD_IT4 EQU 0x40011490 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT5 +CYREG_B1_P2_U1_PLD_IT5 EQU 0x40011494 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT6 +CYREG_B1_P2_U1_PLD_IT6 EQU 0x40011498 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT7 +CYREG_B1_P2_U1_PLD_IT7 EQU 0x4001149c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT8 +CYREG_B1_P2_U1_PLD_IT8 EQU 0x400114a0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT9 +CYREG_B1_P2_U1_PLD_IT9 EQU 0x400114a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT10 +CYREG_B1_P2_U1_PLD_IT10 EQU 0x400114a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT11 +CYREG_B1_P2_U1_PLD_IT11 EQU 0x400114ac + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT0 +CYREG_B1_P2_U1_PLD_ORT0 EQU 0x400114b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT1 +CYREG_B1_P2_U1_PLD_ORT1 EQU 0x400114b2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT2 +CYREG_B1_P2_U1_PLD_ORT2 EQU 0x400114b4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT3 +CYREG_B1_P2_U1_PLD_ORT3 EQU 0x400114b6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_CEN_CONST +CYREG_B1_P2_U1_MC_CFG_CEN_CONST EQU 0x400114b8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_XORFB +CYREG_B1_P2_U1_MC_CFG_XORFB EQU 0x400114ba + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_SET_RESET +CYREG_B1_P2_U1_MC_CFG_SET_RESET EQU 0x400114bc + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_BYPASS +CYREG_B1_P2_U1_MC_CFG_BYPASS EQU 0x400114be + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG0 +CYREG_B1_P2_U1_CFG0 EQU 0x400114c0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG1 +CYREG_B1_P2_U1_CFG1 EQU 0x400114c1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG2 +CYREG_B1_P2_U1_CFG2 EQU 0x400114c2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG3 +CYREG_B1_P2_U1_CFG3 EQU 0x400114c3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG4 +CYREG_B1_P2_U1_CFG4 EQU 0x400114c4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG5 +CYREG_B1_P2_U1_CFG5 EQU 0x400114c5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG6 +CYREG_B1_P2_U1_CFG6 EQU 0x400114c6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG7 +CYREG_B1_P2_U1_CFG7 EQU 0x400114c7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG8 +CYREG_B1_P2_U1_CFG8 EQU 0x400114c8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG9 +CYREG_B1_P2_U1_CFG9 EQU 0x400114c9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG10 +CYREG_B1_P2_U1_CFG10 EQU 0x400114ca + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG11 +CYREG_B1_P2_U1_CFG11 EQU 0x400114cb + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG12 +CYREG_B1_P2_U1_CFG12 EQU 0x400114cc + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG13 +CYREG_B1_P2_U1_CFG13 EQU 0x400114cd + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG14 +CYREG_B1_P2_U1_CFG14 EQU 0x400114ce + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG15 +CYREG_B1_P2_U1_CFG15 EQU 0x400114cf + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG16 +CYREG_B1_P2_U1_CFG16 EQU 0x400114d0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG17 +CYREG_B1_P2_U1_CFG17 EQU 0x400114d1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG18 +CYREG_B1_P2_U1_CFG18 EQU 0x400114d2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG19 +CYREG_B1_P2_U1_CFG19 EQU 0x400114d3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG20 +CYREG_B1_P2_U1_CFG20 EQU 0x400114d4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG21 +CYREG_B1_P2_U1_CFG21 EQU 0x400114d5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG22 +CYREG_B1_P2_U1_CFG22 EQU 0x400114d6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG23 +CYREG_B1_P2_U1_CFG23 EQU 0x400114d7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG24 +CYREG_B1_P2_U1_CFG24 EQU 0x400114d8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG25 +CYREG_B1_P2_U1_CFG25 EQU 0x400114d9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG26 +CYREG_B1_P2_U1_CFG26 EQU 0x400114da + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG27 +CYREG_B1_P2_U1_CFG27 EQU 0x400114db + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG28 +CYREG_B1_P2_U1_CFG28 EQU 0x400114dc + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG29 +CYREG_B1_P2_U1_CFG29 EQU 0x400114dd + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG30 +CYREG_B1_P2_U1_CFG30 EQU 0x400114de + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG31 +CYREG_B1_P2_U1_CFG31 EQU 0x400114df + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG0 +CYREG_B1_P2_U1_DCFG0 EQU 0x400114e0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG1 +CYREG_B1_P2_U1_DCFG1 EQU 0x400114e2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG2 +CYREG_B1_P2_U1_DCFG2 EQU 0x400114e4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG3 +CYREG_B1_P2_U1_DCFG3 EQU 0x400114e6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG4 +CYREG_B1_P2_U1_DCFG4 EQU 0x400114e8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG5 +CYREG_B1_P2_U1_DCFG5 EQU 0x400114ea + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG6 +CYREG_B1_P2_U1_DCFG6 EQU 0x400114ec + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG7 +CYREG_B1_P2_U1_DCFG7 EQU 0x400114ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_BASE +CYDEV_UCFG_B1_P2_ROUTE_BASE EQU 0x40011500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_SIZE +CYDEV_UCFG_B1_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_BASE +CYDEV_UCFG_B1_P3_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_SIZE +CYDEV_UCFG_B1_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_BASE +CYDEV_UCFG_B1_P3_U0_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_SIZE +CYDEV_UCFG_B1_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT0 +CYREG_B1_P3_U0_PLD_IT0 EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT1 +CYREG_B1_P3_U0_PLD_IT1 EQU 0x40011604 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT2 +CYREG_B1_P3_U0_PLD_IT2 EQU 0x40011608 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT3 +CYREG_B1_P3_U0_PLD_IT3 EQU 0x4001160c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT4 +CYREG_B1_P3_U0_PLD_IT4 EQU 0x40011610 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT5 +CYREG_B1_P3_U0_PLD_IT5 EQU 0x40011614 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT6 +CYREG_B1_P3_U0_PLD_IT6 EQU 0x40011618 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT7 +CYREG_B1_P3_U0_PLD_IT7 EQU 0x4001161c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT8 +CYREG_B1_P3_U0_PLD_IT8 EQU 0x40011620 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT9 +CYREG_B1_P3_U0_PLD_IT9 EQU 0x40011624 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT10 +CYREG_B1_P3_U0_PLD_IT10 EQU 0x40011628 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT11 +CYREG_B1_P3_U0_PLD_IT11 EQU 0x4001162c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT0 +CYREG_B1_P3_U0_PLD_ORT0 EQU 0x40011630 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT1 +CYREG_B1_P3_U0_PLD_ORT1 EQU 0x40011632 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT2 +CYREG_B1_P3_U0_PLD_ORT2 EQU 0x40011634 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT3 +CYREG_B1_P3_U0_PLD_ORT3 EQU 0x40011636 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_CEN_CONST +CYREG_B1_P3_U0_MC_CFG_CEN_CONST EQU 0x40011638 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_XORFB +CYREG_B1_P3_U0_MC_CFG_XORFB EQU 0x4001163a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_SET_RESET +CYREG_B1_P3_U0_MC_CFG_SET_RESET EQU 0x4001163c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_BYPASS +CYREG_B1_P3_U0_MC_CFG_BYPASS EQU 0x4001163e + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG0 +CYREG_B1_P3_U0_CFG0 EQU 0x40011640 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG1 +CYREG_B1_P3_U0_CFG1 EQU 0x40011641 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG2 +CYREG_B1_P3_U0_CFG2 EQU 0x40011642 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG3 +CYREG_B1_P3_U0_CFG3 EQU 0x40011643 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG4 +CYREG_B1_P3_U0_CFG4 EQU 0x40011644 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG5 +CYREG_B1_P3_U0_CFG5 EQU 0x40011645 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG6 +CYREG_B1_P3_U0_CFG6 EQU 0x40011646 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG7 +CYREG_B1_P3_U0_CFG7 EQU 0x40011647 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG8 +CYREG_B1_P3_U0_CFG8 EQU 0x40011648 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG9 +CYREG_B1_P3_U0_CFG9 EQU 0x40011649 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG10 +CYREG_B1_P3_U0_CFG10 EQU 0x4001164a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG11 +CYREG_B1_P3_U0_CFG11 EQU 0x4001164b + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG12 +CYREG_B1_P3_U0_CFG12 EQU 0x4001164c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG13 +CYREG_B1_P3_U0_CFG13 EQU 0x4001164d + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG14 +CYREG_B1_P3_U0_CFG14 EQU 0x4001164e + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG15 +CYREG_B1_P3_U0_CFG15 EQU 0x4001164f + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG16 +CYREG_B1_P3_U0_CFG16 EQU 0x40011650 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG17 +CYREG_B1_P3_U0_CFG17 EQU 0x40011651 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG18 +CYREG_B1_P3_U0_CFG18 EQU 0x40011652 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG19 +CYREG_B1_P3_U0_CFG19 EQU 0x40011653 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG20 +CYREG_B1_P3_U0_CFG20 EQU 0x40011654 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG21 +CYREG_B1_P3_U0_CFG21 EQU 0x40011655 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG22 +CYREG_B1_P3_U0_CFG22 EQU 0x40011656 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG23 +CYREG_B1_P3_U0_CFG23 EQU 0x40011657 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG24 +CYREG_B1_P3_U0_CFG24 EQU 0x40011658 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG25 +CYREG_B1_P3_U0_CFG25 EQU 0x40011659 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG26 +CYREG_B1_P3_U0_CFG26 EQU 0x4001165a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG27 +CYREG_B1_P3_U0_CFG27 EQU 0x4001165b + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG28 +CYREG_B1_P3_U0_CFG28 EQU 0x4001165c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG29 +CYREG_B1_P3_U0_CFG29 EQU 0x4001165d + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG30 +CYREG_B1_P3_U0_CFG30 EQU 0x4001165e + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG31 +CYREG_B1_P3_U0_CFG31 EQU 0x4001165f + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG0 +CYREG_B1_P3_U0_DCFG0 EQU 0x40011660 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG1 +CYREG_B1_P3_U0_DCFG1 EQU 0x40011662 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG2 +CYREG_B1_P3_U0_DCFG2 EQU 0x40011664 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG3 +CYREG_B1_P3_U0_DCFG3 EQU 0x40011666 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG4 +CYREG_B1_P3_U0_DCFG4 EQU 0x40011668 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG5 +CYREG_B1_P3_U0_DCFG5 EQU 0x4001166a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG6 +CYREG_B1_P3_U0_DCFG6 EQU 0x4001166c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG7 +CYREG_B1_P3_U0_DCFG7 EQU 0x4001166e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_BASE +CYDEV_UCFG_B1_P3_U1_BASE EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_SIZE +CYDEV_UCFG_B1_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT0 +CYREG_B1_P3_U1_PLD_IT0 EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT1 +CYREG_B1_P3_U1_PLD_IT1 EQU 0x40011684 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT2 +CYREG_B1_P3_U1_PLD_IT2 EQU 0x40011688 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT3 +CYREG_B1_P3_U1_PLD_IT3 EQU 0x4001168c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT4 +CYREG_B1_P3_U1_PLD_IT4 EQU 0x40011690 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT5 +CYREG_B1_P3_U1_PLD_IT5 EQU 0x40011694 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT6 +CYREG_B1_P3_U1_PLD_IT6 EQU 0x40011698 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT7 +CYREG_B1_P3_U1_PLD_IT7 EQU 0x4001169c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT8 +CYREG_B1_P3_U1_PLD_IT8 EQU 0x400116a0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT9 +CYREG_B1_P3_U1_PLD_IT9 EQU 0x400116a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT10 +CYREG_B1_P3_U1_PLD_IT10 EQU 0x400116a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT11 +CYREG_B1_P3_U1_PLD_IT11 EQU 0x400116ac + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT0 +CYREG_B1_P3_U1_PLD_ORT0 EQU 0x400116b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT1 +CYREG_B1_P3_U1_PLD_ORT1 EQU 0x400116b2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT2 +CYREG_B1_P3_U1_PLD_ORT2 EQU 0x400116b4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT3 +CYREG_B1_P3_U1_PLD_ORT3 EQU 0x400116b6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_CEN_CONST +CYREG_B1_P3_U1_MC_CFG_CEN_CONST EQU 0x400116b8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_XORFB +CYREG_B1_P3_U1_MC_CFG_XORFB EQU 0x400116ba + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_SET_RESET +CYREG_B1_P3_U1_MC_CFG_SET_RESET EQU 0x400116bc + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_BYPASS +CYREG_B1_P3_U1_MC_CFG_BYPASS EQU 0x400116be + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG0 +CYREG_B1_P3_U1_CFG0 EQU 0x400116c0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG1 +CYREG_B1_P3_U1_CFG1 EQU 0x400116c1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG2 +CYREG_B1_P3_U1_CFG2 EQU 0x400116c2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG3 +CYREG_B1_P3_U1_CFG3 EQU 0x400116c3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG4 +CYREG_B1_P3_U1_CFG4 EQU 0x400116c4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG5 +CYREG_B1_P3_U1_CFG5 EQU 0x400116c5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG6 +CYREG_B1_P3_U1_CFG6 EQU 0x400116c6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG7 +CYREG_B1_P3_U1_CFG7 EQU 0x400116c7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG8 +CYREG_B1_P3_U1_CFG8 EQU 0x400116c8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG9 +CYREG_B1_P3_U1_CFG9 EQU 0x400116c9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG10 +CYREG_B1_P3_U1_CFG10 EQU 0x400116ca + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG11 +CYREG_B1_P3_U1_CFG11 EQU 0x400116cb + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG12 +CYREG_B1_P3_U1_CFG12 EQU 0x400116cc + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG13 +CYREG_B1_P3_U1_CFG13 EQU 0x400116cd + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG14 +CYREG_B1_P3_U1_CFG14 EQU 0x400116ce + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG15 +CYREG_B1_P3_U1_CFG15 EQU 0x400116cf + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG16 +CYREG_B1_P3_U1_CFG16 EQU 0x400116d0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG17 +CYREG_B1_P3_U1_CFG17 EQU 0x400116d1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG18 +CYREG_B1_P3_U1_CFG18 EQU 0x400116d2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG19 +CYREG_B1_P3_U1_CFG19 EQU 0x400116d3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG20 +CYREG_B1_P3_U1_CFG20 EQU 0x400116d4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG21 +CYREG_B1_P3_U1_CFG21 EQU 0x400116d5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG22 +CYREG_B1_P3_U1_CFG22 EQU 0x400116d6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG23 +CYREG_B1_P3_U1_CFG23 EQU 0x400116d7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG24 +CYREG_B1_P3_U1_CFG24 EQU 0x400116d8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG25 +CYREG_B1_P3_U1_CFG25 EQU 0x400116d9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG26 +CYREG_B1_P3_U1_CFG26 EQU 0x400116da + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG27 +CYREG_B1_P3_U1_CFG27 EQU 0x400116db + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG28 +CYREG_B1_P3_U1_CFG28 EQU 0x400116dc + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG29 +CYREG_B1_P3_U1_CFG29 EQU 0x400116dd + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG30 +CYREG_B1_P3_U1_CFG30 EQU 0x400116de + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG31 +CYREG_B1_P3_U1_CFG31 EQU 0x400116df + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG0 +CYREG_B1_P3_U1_DCFG0 EQU 0x400116e0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG1 +CYREG_B1_P3_U1_DCFG1 EQU 0x400116e2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG2 +CYREG_B1_P3_U1_DCFG2 EQU 0x400116e4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG3 +CYREG_B1_P3_U1_DCFG3 EQU 0x400116e6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG4 +CYREG_B1_P3_U1_DCFG4 EQU 0x400116e8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG5 +CYREG_B1_P3_U1_DCFG5 EQU 0x400116ea + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG6 +CYREG_B1_P3_U1_DCFG6 EQU 0x400116ec + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG7 +CYREG_B1_P3_U1_DCFG7 EQU 0x400116ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_BASE +CYDEV_UCFG_B1_P3_ROUTE_BASE EQU 0x40011700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_SIZE +CYDEV_UCFG_B1_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_BASE +CYDEV_UCFG_B1_P4_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_SIZE +CYDEV_UCFG_B1_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_BASE +CYDEV_UCFG_B1_P4_U0_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_SIZE +CYDEV_UCFG_B1_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT0 +CYREG_B1_P4_U0_PLD_IT0 EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT1 +CYREG_B1_P4_U0_PLD_IT1 EQU 0x40011804 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT2 +CYREG_B1_P4_U0_PLD_IT2 EQU 0x40011808 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT3 +CYREG_B1_P4_U0_PLD_IT3 EQU 0x4001180c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT4 +CYREG_B1_P4_U0_PLD_IT4 EQU 0x40011810 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT5 +CYREG_B1_P4_U0_PLD_IT5 EQU 0x40011814 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT6 +CYREG_B1_P4_U0_PLD_IT6 EQU 0x40011818 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT7 +CYREG_B1_P4_U0_PLD_IT7 EQU 0x4001181c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT8 +CYREG_B1_P4_U0_PLD_IT8 EQU 0x40011820 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT9 +CYREG_B1_P4_U0_PLD_IT9 EQU 0x40011824 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT10 +CYREG_B1_P4_U0_PLD_IT10 EQU 0x40011828 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT11 +CYREG_B1_P4_U0_PLD_IT11 EQU 0x4001182c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT0 +CYREG_B1_P4_U0_PLD_ORT0 EQU 0x40011830 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT1 +CYREG_B1_P4_U0_PLD_ORT1 EQU 0x40011832 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT2 +CYREG_B1_P4_U0_PLD_ORT2 EQU 0x40011834 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT3 +CYREG_B1_P4_U0_PLD_ORT3 EQU 0x40011836 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_CEN_CONST +CYREG_B1_P4_U0_MC_CFG_CEN_CONST EQU 0x40011838 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_XORFB +CYREG_B1_P4_U0_MC_CFG_XORFB EQU 0x4001183a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_SET_RESET +CYREG_B1_P4_U0_MC_CFG_SET_RESET EQU 0x4001183c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_BYPASS +CYREG_B1_P4_U0_MC_CFG_BYPASS EQU 0x4001183e + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG0 +CYREG_B1_P4_U0_CFG0 EQU 0x40011840 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG1 +CYREG_B1_P4_U0_CFG1 EQU 0x40011841 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG2 +CYREG_B1_P4_U0_CFG2 EQU 0x40011842 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG3 +CYREG_B1_P4_U0_CFG3 EQU 0x40011843 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG4 +CYREG_B1_P4_U0_CFG4 EQU 0x40011844 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG5 +CYREG_B1_P4_U0_CFG5 EQU 0x40011845 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG6 +CYREG_B1_P4_U0_CFG6 EQU 0x40011846 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG7 +CYREG_B1_P4_U0_CFG7 EQU 0x40011847 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG8 +CYREG_B1_P4_U0_CFG8 EQU 0x40011848 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG9 +CYREG_B1_P4_U0_CFG9 EQU 0x40011849 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG10 +CYREG_B1_P4_U0_CFG10 EQU 0x4001184a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG11 +CYREG_B1_P4_U0_CFG11 EQU 0x4001184b + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG12 +CYREG_B1_P4_U0_CFG12 EQU 0x4001184c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG13 +CYREG_B1_P4_U0_CFG13 EQU 0x4001184d + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG14 +CYREG_B1_P4_U0_CFG14 EQU 0x4001184e + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG15 +CYREG_B1_P4_U0_CFG15 EQU 0x4001184f + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG16 +CYREG_B1_P4_U0_CFG16 EQU 0x40011850 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG17 +CYREG_B1_P4_U0_CFG17 EQU 0x40011851 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG18 +CYREG_B1_P4_U0_CFG18 EQU 0x40011852 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG19 +CYREG_B1_P4_U0_CFG19 EQU 0x40011853 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG20 +CYREG_B1_P4_U0_CFG20 EQU 0x40011854 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG21 +CYREG_B1_P4_U0_CFG21 EQU 0x40011855 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG22 +CYREG_B1_P4_U0_CFG22 EQU 0x40011856 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG23 +CYREG_B1_P4_U0_CFG23 EQU 0x40011857 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG24 +CYREG_B1_P4_U0_CFG24 EQU 0x40011858 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG25 +CYREG_B1_P4_U0_CFG25 EQU 0x40011859 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG26 +CYREG_B1_P4_U0_CFG26 EQU 0x4001185a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG27 +CYREG_B1_P4_U0_CFG27 EQU 0x4001185b + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG28 +CYREG_B1_P4_U0_CFG28 EQU 0x4001185c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG29 +CYREG_B1_P4_U0_CFG29 EQU 0x4001185d + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG30 +CYREG_B1_P4_U0_CFG30 EQU 0x4001185e + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG31 +CYREG_B1_P4_U0_CFG31 EQU 0x4001185f + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG0 +CYREG_B1_P4_U0_DCFG0 EQU 0x40011860 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG1 +CYREG_B1_P4_U0_DCFG1 EQU 0x40011862 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG2 +CYREG_B1_P4_U0_DCFG2 EQU 0x40011864 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG3 +CYREG_B1_P4_U0_DCFG3 EQU 0x40011866 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG4 +CYREG_B1_P4_U0_DCFG4 EQU 0x40011868 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG5 +CYREG_B1_P4_U0_DCFG5 EQU 0x4001186a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG6 +CYREG_B1_P4_U0_DCFG6 EQU 0x4001186c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG7 +CYREG_B1_P4_U0_DCFG7 EQU 0x4001186e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_BASE +CYDEV_UCFG_B1_P4_U1_BASE EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_SIZE +CYDEV_UCFG_B1_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT0 +CYREG_B1_P4_U1_PLD_IT0 EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT1 +CYREG_B1_P4_U1_PLD_IT1 EQU 0x40011884 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT2 +CYREG_B1_P4_U1_PLD_IT2 EQU 0x40011888 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT3 +CYREG_B1_P4_U1_PLD_IT3 EQU 0x4001188c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT4 +CYREG_B1_P4_U1_PLD_IT4 EQU 0x40011890 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT5 +CYREG_B1_P4_U1_PLD_IT5 EQU 0x40011894 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT6 +CYREG_B1_P4_U1_PLD_IT6 EQU 0x40011898 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT7 +CYREG_B1_P4_U1_PLD_IT7 EQU 0x4001189c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT8 +CYREG_B1_P4_U1_PLD_IT8 EQU 0x400118a0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT9 +CYREG_B1_P4_U1_PLD_IT9 EQU 0x400118a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT10 +CYREG_B1_P4_U1_PLD_IT10 EQU 0x400118a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT11 +CYREG_B1_P4_U1_PLD_IT11 EQU 0x400118ac + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT0 +CYREG_B1_P4_U1_PLD_ORT0 EQU 0x400118b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT1 +CYREG_B1_P4_U1_PLD_ORT1 EQU 0x400118b2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT2 +CYREG_B1_P4_U1_PLD_ORT2 EQU 0x400118b4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT3 +CYREG_B1_P4_U1_PLD_ORT3 EQU 0x400118b6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_CEN_CONST +CYREG_B1_P4_U1_MC_CFG_CEN_CONST EQU 0x400118b8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_XORFB +CYREG_B1_P4_U1_MC_CFG_XORFB EQU 0x400118ba + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_SET_RESET +CYREG_B1_P4_U1_MC_CFG_SET_RESET EQU 0x400118bc + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_BYPASS +CYREG_B1_P4_U1_MC_CFG_BYPASS EQU 0x400118be + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG0 +CYREG_B1_P4_U1_CFG0 EQU 0x400118c0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG1 +CYREG_B1_P4_U1_CFG1 EQU 0x400118c1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG2 +CYREG_B1_P4_U1_CFG2 EQU 0x400118c2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG3 +CYREG_B1_P4_U1_CFG3 EQU 0x400118c3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG4 +CYREG_B1_P4_U1_CFG4 EQU 0x400118c4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG5 +CYREG_B1_P4_U1_CFG5 EQU 0x400118c5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG6 +CYREG_B1_P4_U1_CFG6 EQU 0x400118c6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG7 +CYREG_B1_P4_U1_CFG7 EQU 0x400118c7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG8 +CYREG_B1_P4_U1_CFG8 EQU 0x400118c8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG9 +CYREG_B1_P4_U1_CFG9 EQU 0x400118c9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG10 +CYREG_B1_P4_U1_CFG10 EQU 0x400118ca + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG11 +CYREG_B1_P4_U1_CFG11 EQU 0x400118cb + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG12 +CYREG_B1_P4_U1_CFG12 EQU 0x400118cc + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG13 +CYREG_B1_P4_U1_CFG13 EQU 0x400118cd + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG14 +CYREG_B1_P4_U1_CFG14 EQU 0x400118ce + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG15 +CYREG_B1_P4_U1_CFG15 EQU 0x400118cf + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG16 +CYREG_B1_P4_U1_CFG16 EQU 0x400118d0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG17 +CYREG_B1_P4_U1_CFG17 EQU 0x400118d1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG18 +CYREG_B1_P4_U1_CFG18 EQU 0x400118d2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG19 +CYREG_B1_P4_U1_CFG19 EQU 0x400118d3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG20 +CYREG_B1_P4_U1_CFG20 EQU 0x400118d4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG21 +CYREG_B1_P4_U1_CFG21 EQU 0x400118d5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG22 +CYREG_B1_P4_U1_CFG22 EQU 0x400118d6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG23 +CYREG_B1_P4_U1_CFG23 EQU 0x400118d7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG24 +CYREG_B1_P4_U1_CFG24 EQU 0x400118d8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG25 +CYREG_B1_P4_U1_CFG25 EQU 0x400118d9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG26 +CYREG_B1_P4_U1_CFG26 EQU 0x400118da + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG27 +CYREG_B1_P4_U1_CFG27 EQU 0x400118db + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG28 +CYREG_B1_P4_U1_CFG28 EQU 0x400118dc + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG29 +CYREG_B1_P4_U1_CFG29 EQU 0x400118dd + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG30 +CYREG_B1_P4_U1_CFG30 EQU 0x400118de + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG31 +CYREG_B1_P4_U1_CFG31 EQU 0x400118df + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG0 +CYREG_B1_P4_U1_DCFG0 EQU 0x400118e0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG1 +CYREG_B1_P4_U1_DCFG1 EQU 0x400118e2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG2 +CYREG_B1_P4_U1_DCFG2 EQU 0x400118e4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG3 +CYREG_B1_P4_U1_DCFG3 EQU 0x400118e6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG4 +CYREG_B1_P4_U1_DCFG4 EQU 0x400118e8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG5 +CYREG_B1_P4_U1_DCFG5 EQU 0x400118ea + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG6 +CYREG_B1_P4_U1_DCFG6 EQU 0x400118ec + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG7 +CYREG_B1_P4_U1_DCFG7 EQU 0x400118ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_BASE +CYDEV_UCFG_B1_P4_ROUTE_BASE EQU 0x40011900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_SIZE +CYDEV_UCFG_B1_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_BASE +CYDEV_UCFG_B1_P5_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_SIZE +CYDEV_UCFG_B1_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_BASE +CYDEV_UCFG_B1_P5_U0_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_SIZE +CYDEV_UCFG_B1_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT0 +CYREG_B1_P5_U0_PLD_IT0 EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT1 +CYREG_B1_P5_U0_PLD_IT1 EQU 0x40011a04 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT2 +CYREG_B1_P5_U0_PLD_IT2 EQU 0x40011a08 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT3 +CYREG_B1_P5_U0_PLD_IT3 EQU 0x40011a0c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT4 +CYREG_B1_P5_U0_PLD_IT4 EQU 0x40011a10 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT5 +CYREG_B1_P5_U0_PLD_IT5 EQU 0x40011a14 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT6 +CYREG_B1_P5_U0_PLD_IT6 EQU 0x40011a18 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT7 +CYREG_B1_P5_U0_PLD_IT7 EQU 0x40011a1c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT8 +CYREG_B1_P5_U0_PLD_IT8 EQU 0x40011a20 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT9 +CYREG_B1_P5_U0_PLD_IT9 EQU 0x40011a24 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT10 +CYREG_B1_P5_U0_PLD_IT10 EQU 0x40011a28 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT11 +CYREG_B1_P5_U0_PLD_IT11 EQU 0x40011a2c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT0 +CYREG_B1_P5_U0_PLD_ORT0 EQU 0x40011a30 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT1 +CYREG_B1_P5_U0_PLD_ORT1 EQU 0x40011a32 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT2 +CYREG_B1_P5_U0_PLD_ORT2 EQU 0x40011a34 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT3 +CYREG_B1_P5_U0_PLD_ORT3 EQU 0x40011a36 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_CEN_CONST +CYREG_B1_P5_U0_MC_CFG_CEN_CONST EQU 0x40011a38 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_XORFB +CYREG_B1_P5_U0_MC_CFG_XORFB EQU 0x40011a3a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_SET_RESET +CYREG_B1_P5_U0_MC_CFG_SET_RESET EQU 0x40011a3c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_BYPASS +CYREG_B1_P5_U0_MC_CFG_BYPASS EQU 0x40011a3e + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG0 +CYREG_B1_P5_U0_CFG0 EQU 0x40011a40 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG1 +CYREG_B1_P5_U0_CFG1 EQU 0x40011a41 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG2 +CYREG_B1_P5_U0_CFG2 EQU 0x40011a42 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG3 +CYREG_B1_P5_U0_CFG3 EQU 0x40011a43 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG4 +CYREG_B1_P5_U0_CFG4 EQU 0x40011a44 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG5 +CYREG_B1_P5_U0_CFG5 EQU 0x40011a45 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG6 +CYREG_B1_P5_U0_CFG6 EQU 0x40011a46 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG7 +CYREG_B1_P5_U0_CFG7 EQU 0x40011a47 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG8 +CYREG_B1_P5_U0_CFG8 EQU 0x40011a48 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG9 +CYREG_B1_P5_U0_CFG9 EQU 0x40011a49 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG10 +CYREG_B1_P5_U0_CFG10 EQU 0x40011a4a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG11 +CYREG_B1_P5_U0_CFG11 EQU 0x40011a4b + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG12 +CYREG_B1_P5_U0_CFG12 EQU 0x40011a4c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG13 +CYREG_B1_P5_U0_CFG13 EQU 0x40011a4d + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG14 +CYREG_B1_P5_U0_CFG14 EQU 0x40011a4e + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG15 +CYREG_B1_P5_U0_CFG15 EQU 0x40011a4f + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG16 +CYREG_B1_P5_U0_CFG16 EQU 0x40011a50 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG17 +CYREG_B1_P5_U0_CFG17 EQU 0x40011a51 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG18 +CYREG_B1_P5_U0_CFG18 EQU 0x40011a52 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG19 +CYREG_B1_P5_U0_CFG19 EQU 0x40011a53 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG20 +CYREG_B1_P5_U0_CFG20 EQU 0x40011a54 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG21 +CYREG_B1_P5_U0_CFG21 EQU 0x40011a55 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG22 +CYREG_B1_P5_U0_CFG22 EQU 0x40011a56 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG23 +CYREG_B1_P5_U0_CFG23 EQU 0x40011a57 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG24 +CYREG_B1_P5_U0_CFG24 EQU 0x40011a58 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG25 +CYREG_B1_P5_U0_CFG25 EQU 0x40011a59 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG26 +CYREG_B1_P5_U0_CFG26 EQU 0x40011a5a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG27 +CYREG_B1_P5_U0_CFG27 EQU 0x40011a5b + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG28 +CYREG_B1_P5_U0_CFG28 EQU 0x40011a5c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG29 +CYREG_B1_P5_U0_CFG29 EQU 0x40011a5d + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG30 +CYREG_B1_P5_U0_CFG30 EQU 0x40011a5e + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG31 +CYREG_B1_P5_U0_CFG31 EQU 0x40011a5f + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG0 +CYREG_B1_P5_U0_DCFG0 EQU 0x40011a60 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG1 +CYREG_B1_P5_U0_DCFG1 EQU 0x40011a62 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG2 +CYREG_B1_P5_U0_DCFG2 EQU 0x40011a64 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG3 +CYREG_B1_P5_U0_DCFG3 EQU 0x40011a66 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG4 +CYREG_B1_P5_U0_DCFG4 EQU 0x40011a68 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG5 +CYREG_B1_P5_U0_DCFG5 EQU 0x40011a6a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG6 +CYREG_B1_P5_U0_DCFG6 EQU 0x40011a6c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG7 +CYREG_B1_P5_U0_DCFG7 EQU 0x40011a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_BASE +CYDEV_UCFG_B1_P5_U1_BASE EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_SIZE +CYDEV_UCFG_B1_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT0 +CYREG_B1_P5_U1_PLD_IT0 EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT1 +CYREG_B1_P5_U1_PLD_IT1 EQU 0x40011a84 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT2 +CYREG_B1_P5_U1_PLD_IT2 EQU 0x40011a88 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT3 +CYREG_B1_P5_U1_PLD_IT3 EQU 0x40011a8c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT4 +CYREG_B1_P5_U1_PLD_IT4 EQU 0x40011a90 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT5 +CYREG_B1_P5_U1_PLD_IT5 EQU 0x40011a94 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT6 +CYREG_B1_P5_U1_PLD_IT6 EQU 0x40011a98 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT7 +CYREG_B1_P5_U1_PLD_IT7 EQU 0x40011a9c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT8 +CYREG_B1_P5_U1_PLD_IT8 EQU 0x40011aa0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT9 +CYREG_B1_P5_U1_PLD_IT9 EQU 0x40011aa4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT10 +CYREG_B1_P5_U1_PLD_IT10 EQU 0x40011aa8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT11 +CYREG_B1_P5_U1_PLD_IT11 EQU 0x40011aac + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT0 +CYREG_B1_P5_U1_PLD_ORT0 EQU 0x40011ab0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT1 +CYREG_B1_P5_U1_PLD_ORT1 EQU 0x40011ab2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT2 +CYREG_B1_P5_U1_PLD_ORT2 EQU 0x40011ab4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT3 +CYREG_B1_P5_U1_PLD_ORT3 EQU 0x40011ab6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_CEN_CONST +CYREG_B1_P5_U1_MC_CFG_CEN_CONST EQU 0x40011ab8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_XORFB +CYREG_B1_P5_U1_MC_CFG_XORFB EQU 0x40011aba + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_SET_RESET +CYREG_B1_P5_U1_MC_CFG_SET_RESET EQU 0x40011abc + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_BYPASS +CYREG_B1_P5_U1_MC_CFG_BYPASS EQU 0x40011abe + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG0 +CYREG_B1_P5_U1_CFG0 EQU 0x40011ac0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG1 +CYREG_B1_P5_U1_CFG1 EQU 0x40011ac1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG2 +CYREG_B1_P5_U1_CFG2 EQU 0x40011ac2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG3 +CYREG_B1_P5_U1_CFG3 EQU 0x40011ac3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG4 +CYREG_B1_P5_U1_CFG4 EQU 0x40011ac4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG5 +CYREG_B1_P5_U1_CFG5 EQU 0x40011ac5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG6 +CYREG_B1_P5_U1_CFG6 EQU 0x40011ac6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG7 +CYREG_B1_P5_U1_CFG7 EQU 0x40011ac7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG8 +CYREG_B1_P5_U1_CFG8 EQU 0x40011ac8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG9 +CYREG_B1_P5_U1_CFG9 EQU 0x40011ac9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG10 +CYREG_B1_P5_U1_CFG10 EQU 0x40011aca + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG11 +CYREG_B1_P5_U1_CFG11 EQU 0x40011acb + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG12 +CYREG_B1_P5_U1_CFG12 EQU 0x40011acc + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG13 +CYREG_B1_P5_U1_CFG13 EQU 0x40011acd + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG14 +CYREG_B1_P5_U1_CFG14 EQU 0x40011ace + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG15 +CYREG_B1_P5_U1_CFG15 EQU 0x40011acf + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG16 +CYREG_B1_P5_U1_CFG16 EQU 0x40011ad0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG17 +CYREG_B1_P5_U1_CFG17 EQU 0x40011ad1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG18 +CYREG_B1_P5_U1_CFG18 EQU 0x40011ad2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG19 +CYREG_B1_P5_U1_CFG19 EQU 0x40011ad3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG20 +CYREG_B1_P5_U1_CFG20 EQU 0x40011ad4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG21 +CYREG_B1_P5_U1_CFG21 EQU 0x40011ad5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG22 +CYREG_B1_P5_U1_CFG22 EQU 0x40011ad6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG23 +CYREG_B1_P5_U1_CFG23 EQU 0x40011ad7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG24 +CYREG_B1_P5_U1_CFG24 EQU 0x40011ad8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG25 +CYREG_B1_P5_U1_CFG25 EQU 0x40011ad9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG26 +CYREG_B1_P5_U1_CFG26 EQU 0x40011ada + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG27 +CYREG_B1_P5_U1_CFG27 EQU 0x40011adb + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG28 +CYREG_B1_P5_U1_CFG28 EQU 0x40011adc + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG29 +CYREG_B1_P5_U1_CFG29 EQU 0x40011add + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG30 +CYREG_B1_P5_U1_CFG30 EQU 0x40011ade + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG31 +CYREG_B1_P5_U1_CFG31 EQU 0x40011adf + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG0 +CYREG_B1_P5_U1_DCFG0 EQU 0x40011ae0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG1 +CYREG_B1_P5_U1_DCFG1 EQU 0x40011ae2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG2 +CYREG_B1_P5_U1_DCFG2 EQU 0x40011ae4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG3 +CYREG_B1_P5_U1_DCFG3 EQU 0x40011ae6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG4 +CYREG_B1_P5_U1_DCFG4 EQU 0x40011ae8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG5 +CYREG_B1_P5_U1_DCFG5 EQU 0x40011aea + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG6 +CYREG_B1_P5_U1_DCFG6 EQU 0x40011aec + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG7 +CYREG_B1_P5_U1_DCFG7 EQU 0x40011aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_BASE +CYDEV_UCFG_B1_P5_ROUTE_BASE EQU 0x40011b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_SIZE +CYDEV_UCFG_B1_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_BASE +CYDEV_UCFG_DSI0_BASE EQU 0x40014000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_SIZE +CYDEV_UCFG_DSI0_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_BASE +CYDEV_UCFG_DSI1_BASE EQU 0x40014100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_SIZE +CYDEV_UCFG_DSI1_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_BASE +CYDEV_UCFG_DSI2_BASE EQU 0x40014200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_SIZE +CYDEV_UCFG_DSI2_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_BASE +CYDEV_UCFG_DSI3_BASE EQU 0x40014300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_SIZE +CYDEV_UCFG_DSI3_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_BASE +CYDEV_UCFG_DSI4_BASE EQU 0x40014400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_SIZE +CYDEV_UCFG_DSI4_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_BASE +CYDEV_UCFG_DSI5_BASE EQU 0x40014500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_SIZE +CYDEV_UCFG_DSI5_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_BASE +CYDEV_UCFG_DSI6_BASE EQU 0x40014600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_SIZE +CYDEV_UCFG_DSI6_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_BASE +CYDEV_UCFG_DSI7_BASE EQU 0x40014700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_SIZE +CYDEV_UCFG_DSI7_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_BASE +CYDEV_UCFG_DSI8_BASE EQU 0x40014800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_SIZE +CYDEV_UCFG_DSI8_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_BASE +CYDEV_UCFG_DSI9_BASE EQU 0x40014900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_SIZE +CYDEV_UCFG_DSI9_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_BASE +CYDEV_UCFG_DSI12_BASE EQU 0x40014c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_SIZE +CYDEV_UCFG_DSI12_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_BASE +CYDEV_UCFG_DSI13_BASE EQU 0x40014d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_SIZE +CYDEV_UCFG_DSI13_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BASE +CYDEV_UCFG_BCTL0_BASE EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_SIZE +CYDEV_UCFG_BCTL0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_MDCLK_EN +CYREG_BCTL0_MDCLK_EN EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_MBCLK_EN +CYREG_BCTL0_MBCLK_EN EQU 0x40015001 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_WAIT_CFG +CYREG_BCTL0_WAIT_CFG EQU 0x40015002 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BANK_CTL +CYREG_BCTL0_BANK_CTL EQU 0x40015003 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_UDB_TEST_3 +CYREG_BCTL0_UDB_TEST_3 EQU 0x40015007 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN0 +CYREG_BCTL0_DCLK_EN0 EQU 0x40015008 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN0 +CYREG_BCTL0_BCLK_EN0 EQU 0x40015009 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN1 +CYREG_BCTL0_DCLK_EN1 EQU 0x4001500a + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN1 +CYREG_BCTL0_BCLK_EN1 EQU 0x4001500b + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN2 +CYREG_BCTL0_DCLK_EN2 EQU 0x4001500c + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN2 +CYREG_BCTL0_BCLK_EN2 EQU 0x4001500d + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN3 +CYREG_BCTL0_DCLK_EN3 EQU 0x4001500e + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN3 +CYREG_BCTL0_BCLK_EN3 EQU 0x4001500f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BASE +CYDEV_UCFG_BCTL1_BASE EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_SIZE +CYDEV_UCFG_BCTL1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_MDCLK_EN +CYREG_BCTL1_MDCLK_EN EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_MBCLK_EN +CYREG_BCTL1_MBCLK_EN EQU 0x40015011 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_WAIT_CFG +CYREG_BCTL1_WAIT_CFG EQU 0x40015012 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BANK_CTL +CYREG_BCTL1_BANK_CTL EQU 0x40015013 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_UDB_TEST_3 +CYREG_BCTL1_UDB_TEST_3 EQU 0x40015017 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN0 +CYREG_BCTL1_DCLK_EN0 EQU 0x40015018 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN0 +CYREG_BCTL1_BCLK_EN0 EQU 0x40015019 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN1 +CYREG_BCTL1_DCLK_EN1 EQU 0x4001501a + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN1 +CYREG_BCTL1_BCLK_EN1 EQU 0x4001501b + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN2 +CYREG_BCTL1_DCLK_EN2 EQU 0x4001501c + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN2 +CYREG_BCTL1_BCLK_EN2 EQU 0x4001501d + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN3 +CYREG_BCTL1_DCLK_EN3 EQU 0x4001501e + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN3 +CYREG_BCTL1_BCLK_EN3 EQU 0x4001501f + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_BASE +CYDEV_IDMUX_BASE EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_SIZE +CYDEV_IDMUX_SIZE EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL0 +CYREG_IDMUX_IRQ_CTL0 EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL1 +CYREG_IDMUX_IRQ_CTL1 EQU 0x40015101 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL2 +CYREG_IDMUX_IRQ_CTL2 EQU 0x40015102 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL3 +CYREG_IDMUX_IRQ_CTL3 EQU 0x40015103 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL4 +CYREG_IDMUX_IRQ_CTL4 EQU 0x40015104 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL5 +CYREG_IDMUX_IRQ_CTL5 EQU 0x40015105 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL6 +CYREG_IDMUX_IRQ_CTL6 EQU 0x40015106 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL7 +CYREG_IDMUX_IRQ_CTL7 EQU 0x40015107 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL0 +CYREG_IDMUX_DRQ_CTL0 EQU 0x40015110 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL1 +CYREG_IDMUX_DRQ_CTL1 EQU 0x40015111 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL2 +CYREG_IDMUX_DRQ_CTL2 EQU 0x40015112 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL3 +CYREG_IDMUX_DRQ_CTL3 EQU 0x40015113 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL4 +CYREG_IDMUX_DRQ_CTL4 EQU 0x40015114 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL5 +CYREG_IDMUX_DRQ_CTL5 EQU 0x40015115 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_BASE +CYDEV_CACHERAM_BASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_SIZE +CYDEV_CACHERAM_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYREG_CACHERAM_DATA_MBASE +CYREG_CACHERAM_DATA_MBASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYREG_CACHERAM_DATA_MSIZE +CYREG_CACHERAM_DATA_MSIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_BASE +CYDEV_SFR_BASE EQU 0x40050100 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_SIZE +CYDEV_SFR_SIZE EQU 0x000000fb + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO0 +CYREG_SFR_GPIO0 EQU 0x40050180 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD0 +CYREG_SFR_GPIRD0 EQU 0x40050189 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO0_SEL +CYREG_SFR_GPIO0_SEL EQU 0x4005018a + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO1 +CYREG_SFR_GPIO1 EQU 0x40050190 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD1 +CYREG_SFR_GPIRD1 EQU 0x40050191 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO2 +CYREG_SFR_GPIO2 EQU 0x40050198 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD2 +CYREG_SFR_GPIRD2 EQU 0x40050199 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO2_SEL +CYREG_SFR_GPIO2_SEL EQU 0x4005019a + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO1_SEL +CYREG_SFR_GPIO1_SEL EQU 0x400501a2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO3 +CYREG_SFR_GPIO3 EQU 0x400501b0 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD3 +CYREG_SFR_GPIRD3 EQU 0x400501b1 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO3_SEL +CYREG_SFR_GPIO3_SEL EQU 0x400501b2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO4 +CYREG_SFR_GPIO4 EQU 0x400501c0 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD4 +CYREG_SFR_GPIRD4 EQU 0x400501c1 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO4_SEL +CYREG_SFR_GPIO4_SEL EQU 0x400501c2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO5 +CYREG_SFR_GPIO5 EQU 0x400501c8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD5 +CYREG_SFR_GPIRD5 EQU 0x400501c9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO5_SEL +CYREG_SFR_GPIO5_SEL EQU 0x400501ca + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO6 +CYREG_SFR_GPIO6 EQU 0x400501d8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD6 +CYREG_SFR_GPIRD6 EQU 0x400501d9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO6_SEL +CYREG_SFR_GPIO6_SEL EQU 0x400501da + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO12 +CYREG_SFR_GPIO12 EQU 0x400501e8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD12 +CYREG_SFR_GPIRD12 EQU 0x400501e9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO12_SEL +CYREG_SFR_GPIO12_SEL EQU 0x400501f2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO15 +CYREG_SFR_GPIO15 EQU 0x400501f8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD15 +CYREG_SFR_GPIRD15 EQU 0x400501f9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO15_SEL +CYREG_SFR_GPIO15_SEL EQU 0x400501fa + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_BASE +CYDEV_P3BA_BASE EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SIZE +CYDEV_P3BA_SIZE EQU 0x0000002b + ENDIF + IF :LNOT::DEF:CYREG_P3BA_Y_START +CYREG_P3BA_Y_START EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_YROLL +CYREG_P3BA_YROLL EQU 0x40050301 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_YCFG +CYREG_P3BA_YCFG EQU 0x40050302 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_START1 +CYREG_P3BA_X_START1 EQU 0x40050303 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_START2 +CYREG_P3BA_X_START2 EQU 0x40050304 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XROLL1 +CYREG_P3BA_XROLL1 EQU 0x40050305 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XROLL2 +CYREG_P3BA_XROLL2 EQU 0x40050306 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XINC +CYREG_P3BA_XINC EQU 0x40050307 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XCFG +CYREG_P3BA_XCFG EQU 0x40050308 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR1 +CYREG_P3BA_OFFSETADDR1 EQU 0x40050309 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR2 +CYREG_P3BA_OFFSETADDR2 EQU 0x4005030a + ENDIF + IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR3 +CYREG_P3BA_OFFSETADDR3 EQU 0x4005030b + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR1 +CYREG_P3BA_ABSADDR1 EQU 0x4005030c + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR2 +CYREG_P3BA_ABSADDR2 EQU 0x4005030d + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR3 +CYREG_P3BA_ABSADDR3 EQU 0x4005030e + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR4 +CYREG_P3BA_ABSADDR4 EQU 0x4005030f + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATCFG1 +CYREG_P3BA_DATCFG1 EQU 0x40050310 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATCFG2 +CYREG_P3BA_DATCFG2 EQU 0x40050311 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT1 +CYREG_P3BA_CMP_RSLT1 EQU 0x40050314 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT2 +CYREG_P3BA_CMP_RSLT2 EQU 0x40050315 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT3 +CYREG_P3BA_CMP_RSLT3 EQU 0x40050316 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT4 +CYREG_P3BA_CMP_RSLT4 EQU 0x40050317 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG1 +CYREG_P3BA_DATA_REG1 EQU 0x40050318 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG2 +CYREG_P3BA_DATA_REG2 EQU 0x40050319 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG3 +CYREG_P3BA_DATA_REG3 EQU 0x4005031a + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG4 +CYREG_P3BA_DATA_REG4 EQU 0x4005031b + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA1 +CYREG_P3BA_EXP_DATA1 EQU 0x4005031c + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA2 +CYREG_P3BA_EXP_DATA2 EQU 0x4005031d + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA3 +CYREG_P3BA_EXP_DATA3 EQU 0x4005031e + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA4 +CYREG_P3BA_EXP_DATA4 EQU 0x4005031f + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA1 +CYREG_P3BA_MSTR_HRDATA1 EQU 0x40050320 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA2 +CYREG_P3BA_MSTR_HRDATA2 EQU 0x40050321 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA3 +CYREG_P3BA_MSTR_HRDATA3 EQU 0x40050322 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA4 +CYREG_P3BA_MSTR_HRDATA4 EQU 0x40050323 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_BIST_EN +CYREG_P3BA_BIST_EN EQU 0x40050324 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_PHUB_MASTER_SSR +CYREG_P3BA_PHUB_MASTER_SSR EQU 0x40050325 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_SEQCFG1 +CYREG_P3BA_SEQCFG1 EQU 0x40050326 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_SEQCFG2 +CYREG_P3BA_SEQCFG2 EQU 0x40050327 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_Y_CURR +CYREG_P3BA_Y_CURR EQU 0x40050328 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_CURR1 +CYREG_P3BA_X_CURR1 EQU 0x40050329 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_CURR2 +CYREG_P3BA_X_CURR2 EQU 0x4005032a + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_BASE +CYDEV_PANTHER_BASE EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_SIZE +CYDEV_PANTHER_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_STCALIB_CFG +CYREG_PANTHER_STCALIB_CFG EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_WAITPIPE +CYREG_PANTHER_WAITPIPE EQU 0x40080004 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_TRACE_CFG +CYREG_PANTHER_TRACE_CFG EQU 0x40080008 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_DBG_CFG +CYREG_PANTHER_DBG_CFG EQU 0x4008000c + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_CM3_LCKRST_STAT +CYREG_PANTHER_CM3_LCKRST_STAT EQU 0x40080018 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_DEVICE_ID +CYREG_PANTHER_DEVICE_ID EQU 0x4008001c + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_BASE +CYDEV_FLSECC_BASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_SIZE +CYDEV_FLSECC_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_FLSECC_DATA_MBASE +CYREG_FLSECC_DATA_MBASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYREG_FLSECC_DATA_MSIZE +CYREG_FLSECC_DATA_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_BASE +CYDEV_FLSHID_BASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_SIZE +CYDEV_FLSHID_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_RSVD_MBASE +CYREG_FLSHID_RSVD_MBASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_RSVD_MSIZE +CYREG_FLSHID_RSVD_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_MDATA_MBASE +CYREG_FLSHID_CUST_MDATA_MBASE EQU 0x49000080 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_MDATA_MSIZE +CYREG_FLSHID_CUST_MDATA_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_BASE +CYDEV_FLSHID_CUST_TABLES_BASE EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_SIZE +CYDEV_FLSHID_CUST_TABLES_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_Y_LOC +CYREG_FLSHID_CUST_TABLES_Y_LOC EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_X_LOC +CYREG_FLSHID_CUST_TABLES_X_LOC EQU 0x49000101 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_WAFER_NUM +CYREG_FLSHID_CUST_TABLES_WAFER_NUM EQU 0x49000102 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_LOT_LSB +CYREG_FLSHID_CUST_TABLES_LOT_LSB EQU 0x49000103 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_LOT_MSB +CYREG_FLSHID_CUST_TABLES_LOT_MSB EQU 0x49000104 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_WRK_WK +CYREG_FLSHID_CUST_TABLES_WRK_WK EQU 0x49000105 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_FAB_YR +CYREG_FLSHID_CUST_TABLES_FAB_YR EQU 0x49000106 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_MINOR +CYREG_FLSHID_CUST_TABLES_MINOR EQU 0x49000107 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_3MHZ +CYREG_FLSHID_CUST_TABLES_IMO_3MHZ EQU 0x49000108 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_6MHZ +CYREG_FLSHID_CUST_TABLES_IMO_6MHZ EQU 0x49000109 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_12MHZ +CYREG_FLSHID_CUST_TABLES_IMO_12MHZ EQU 0x4900010a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_24MHZ +CYREG_FLSHID_CUST_TABLES_IMO_24MHZ EQU 0x4900010b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_67MHZ +CYREG_FLSHID_CUST_TABLES_IMO_67MHZ EQU 0x4900010c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_80MHZ +CYREG_FLSHID_CUST_TABLES_IMO_80MHZ EQU 0x4900010d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_92MHZ +CYREG_FLSHID_CUST_TABLES_IMO_92MHZ EQU 0x4900010e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_USB +CYREG_FLSHID_CUST_TABLES_IMO_USB EQU 0x4900010f + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS EQU 0x49000110 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS EQU 0x49000111 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS EQU 0x49000112 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS EQU 0x49000113 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS EQU 0x49000114 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS EQU 0x49000115 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS EQU 0x49000116 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS EQU 0x49000117 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M1 +CYREG_FLSHID_CUST_TABLES_DEC_M1 EQU 0x49000118 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M2 +CYREG_FLSHID_CUST_TABLES_DEC_M2 EQU 0x49000119 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M3 +CYREG_FLSHID_CUST_TABLES_DEC_M3 EQU 0x4900011a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M4 +CYREG_FLSHID_CUST_TABLES_DEC_M4 EQU 0x4900011b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M5 +CYREG_FLSHID_CUST_TABLES_DEC_M5 EQU 0x4900011c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M6 +CYREG_FLSHID_CUST_TABLES_DEC_M6 EQU 0x4900011d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M7 +CYREG_FLSHID_CUST_TABLES_DEC_M7 EQU 0x4900011e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M8 +CYREG_FLSHID_CUST_TABLES_DEC_M8 EQU 0x4900011f + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M1 +CYREG_FLSHID_CUST_TABLES_DAC0_M1 EQU 0x49000120 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M2 +CYREG_FLSHID_CUST_TABLES_DAC0_M2 EQU 0x49000121 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M3 +CYREG_FLSHID_CUST_TABLES_DAC0_M3 EQU 0x49000122 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M4 +CYREG_FLSHID_CUST_TABLES_DAC0_M4 EQU 0x49000123 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M5 +CYREG_FLSHID_CUST_TABLES_DAC0_M5 EQU 0x49000124 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M6 +CYREG_FLSHID_CUST_TABLES_DAC0_M6 EQU 0x49000125 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M7 +CYREG_FLSHID_CUST_TABLES_DAC0_M7 EQU 0x49000126 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M8 +CYREG_FLSHID_CUST_TABLES_DAC0_M8 EQU 0x49000127 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M1 +CYREG_FLSHID_CUST_TABLES_DAC2_M1 EQU 0x49000128 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M2 +CYREG_FLSHID_CUST_TABLES_DAC2_M2 EQU 0x49000129 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M3 +CYREG_FLSHID_CUST_TABLES_DAC2_M3 EQU 0x4900012a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M4 +CYREG_FLSHID_CUST_TABLES_DAC2_M4 EQU 0x4900012b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M5 +CYREG_FLSHID_CUST_TABLES_DAC2_M5 EQU 0x4900012c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M6 +CYREG_FLSHID_CUST_TABLES_DAC2_M6 EQU 0x4900012d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M7 +CYREG_FLSHID_CUST_TABLES_DAC2_M7 EQU 0x4900012e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M8 +CYREG_FLSHID_CUST_TABLES_DAC2_M8 EQU 0x4900012f + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M1 +CYREG_FLSHID_CUST_TABLES_DAC1_M1 EQU 0x49000130 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M2 +CYREG_FLSHID_CUST_TABLES_DAC1_M2 EQU 0x49000131 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M3 +CYREG_FLSHID_CUST_TABLES_DAC1_M3 EQU 0x49000132 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M4 +CYREG_FLSHID_CUST_TABLES_DAC1_M4 EQU 0x49000133 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M5 +CYREG_FLSHID_CUST_TABLES_DAC1_M5 EQU 0x49000134 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M6 +CYREG_FLSHID_CUST_TABLES_DAC1_M6 EQU 0x49000135 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M7 +CYREG_FLSHID_CUST_TABLES_DAC1_M7 EQU 0x49000136 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M8 +CYREG_FLSHID_CUST_TABLES_DAC1_M8 EQU 0x49000137 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M1 +CYREG_FLSHID_CUST_TABLES_DAC3_M1 EQU 0x49000138 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M2 +CYREG_FLSHID_CUST_TABLES_DAC3_M2 EQU 0x49000139 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M3 +CYREG_FLSHID_CUST_TABLES_DAC3_M3 EQU 0x4900013a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M4 +CYREG_FLSHID_CUST_TABLES_DAC3_M4 EQU 0x4900013b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M5 +CYREG_FLSHID_CUST_TABLES_DAC3_M5 EQU 0x4900013c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M6 +CYREG_FLSHID_CUST_TABLES_DAC3_M6 EQU 0x4900013d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M7 +CYREG_FLSHID_CUST_TABLES_DAC3_M7 EQU 0x4900013e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M8 +CYREG_FLSHID_CUST_TABLES_DAC3_M8 EQU 0x4900013f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BASE +CYDEV_FLSHID_MFG_CFG_BASE EQU 0x49000180 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_SIZE +CYDEV_FLSHID_MFG_CFG_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_IMO_TR1 +CYREG_FLSHID_MFG_CFG_IMO_TR1 EQU 0x49000188 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP0_TR0 +CYREG_FLSHID_MFG_CFG_CMP0_TR0 EQU 0x490001ac + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP1_TR0 +CYREG_FLSHID_MFG_CFG_CMP1_TR0 EQU 0x490001ae + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP2_TR0 +CYREG_FLSHID_MFG_CFG_CMP2_TR0 EQU 0x490001b0 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP3_TR0 +CYREG_FLSHID_MFG_CFG_CMP3_TR0 EQU 0x490001b2 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP0_TR1 +CYREG_FLSHID_MFG_CFG_CMP0_TR1 EQU 0x490001b4 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP1_TR1 +CYREG_FLSHID_MFG_CFG_CMP1_TR1 EQU 0x490001b6 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP2_TR1 +CYREG_FLSHID_MFG_CFG_CMP2_TR1 EQU 0x490001b8 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP3_TR1 +CYREG_FLSHID_MFG_CFG_CMP3_TR1 EQU 0x490001ba + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM +CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM EQU 0x490001ce + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_BASE +CYDEV_EXTMEM_BASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_SIZE +CYDEV_EXTMEM_SIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYREG_EXTMEM_DATA_MBASE +CYREG_EXTMEM_DATA_MBASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYREG_EXTMEM_DATA_MSIZE +CYREG_EXTMEM_DATA_MSIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_BASE +CYDEV_ITM_BASE EQU 0xe0000000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_SIZE +CYDEV_ITM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ITM_TRACE_EN +CYREG_ITM_TRACE_EN EQU 0xe0000e00 + ENDIF + IF :LNOT::DEF:CYREG_ITM_TRACE_PRIVILEGE +CYREG_ITM_TRACE_PRIVILEGE EQU 0xe0000e40 + ENDIF + IF :LNOT::DEF:CYREG_ITM_TRACE_CTRL +CYREG_ITM_TRACE_CTRL EQU 0xe0000e80 + ENDIF + IF :LNOT::DEF:CYREG_ITM_LOCK_ACCESS +CYREG_ITM_LOCK_ACCESS EQU 0xe0000fb0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_LOCK_STATUS +CYREG_ITM_LOCK_STATUS EQU 0xe0000fb4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID4 +CYREG_ITM_PID4 EQU 0xe0000fd0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID5 +CYREG_ITM_PID5 EQU 0xe0000fd4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID6 +CYREG_ITM_PID6 EQU 0xe0000fd8 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID7 +CYREG_ITM_PID7 EQU 0xe0000fdc + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID0 +CYREG_ITM_PID0 EQU 0xe0000fe0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID1 +CYREG_ITM_PID1 EQU 0xe0000fe4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID2 +CYREG_ITM_PID2 EQU 0xe0000fe8 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID3 +CYREG_ITM_PID3 EQU 0xe0000fec + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID0 +CYREG_ITM_CID0 EQU 0xe0000ff0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID1 +CYREG_ITM_CID1 EQU 0xe0000ff4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID2 +CYREG_ITM_CID2 EQU 0xe0000ff8 + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID3 +CYREG_ITM_CID3 EQU 0xe0000ffc + ENDIF + IF :LNOT::DEF:CYDEV_DWT_BASE +CYDEV_DWT_BASE EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_SIZE +CYDEV_DWT_SIZE EQU 0x0000005c + ENDIF + IF :LNOT::DEF:CYREG_DWT_CTRL +CYREG_DWT_CTRL EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYREG_DWT_CYCLE_COUNT +CYREG_DWT_CYCLE_COUNT EQU 0xe0001004 + ENDIF + IF :LNOT::DEF:CYREG_DWT_CPI_COUNT +CYREG_DWT_CPI_COUNT EQU 0xe0001008 + ENDIF + IF :LNOT::DEF:CYREG_DWT_EXC_OVHD_COUNT +CYREG_DWT_EXC_OVHD_COUNT EQU 0xe000100c + ENDIF + IF :LNOT::DEF:CYREG_DWT_SLEEP_COUNT +CYREG_DWT_SLEEP_COUNT EQU 0xe0001010 + ENDIF + IF :LNOT::DEF:CYREG_DWT_LSU_COUNT +CYREG_DWT_LSU_COUNT EQU 0xe0001014 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FOLD_COUNT +CYREG_DWT_FOLD_COUNT EQU 0xe0001018 + ENDIF + IF :LNOT::DEF:CYREG_DWT_PC_SAMPLE +CYREG_DWT_PC_SAMPLE EQU 0xe000101c + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_0 +CYREG_DWT_COMP_0 EQU 0xe0001020 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_0 +CYREG_DWT_MASK_0 EQU 0xe0001024 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_0 +CYREG_DWT_FUNCTION_0 EQU 0xe0001028 + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_1 +CYREG_DWT_COMP_1 EQU 0xe0001030 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_1 +CYREG_DWT_MASK_1 EQU 0xe0001034 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_1 +CYREG_DWT_FUNCTION_1 EQU 0xe0001038 + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_2 +CYREG_DWT_COMP_2 EQU 0xe0001040 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_2 +CYREG_DWT_MASK_2 EQU 0xe0001044 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_2 +CYREG_DWT_FUNCTION_2 EQU 0xe0001048 + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_3 +CYREG_DWT_COMP_3 EQU 0xe0001050 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_3 +CYREG_DWT_MASK_3 EQU 0xe0001054 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_3 +CYREG_DWT_FUNCTION_3 EQU 0xe0001058 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_BASE +CYDEV_FPB_BASE EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_SIZE +CYDEV_FPB_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CTRL +CYREG_FPB_CTRL EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYREG_FPB_REMAP +CYREG_FPB_REMAP EQU 0xe0002004 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_0 +CYREG_FPB_FP_COMP_0 EQU 0xe0002008 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_1 +CYREG_FPB_FP_COMP_1 EQU 0xe000200c + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_2 +CYREG_FPB_FP_COMP_2 EQU 0xe0002010 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_3 +CYREG_FPB_FP_COMP_3 EQU 0xe0002014 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_4 +CYREG_FPB_FP_COMP_4 EQU 0xe0002018 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_5 +CYREG_FPB_FP_COMP_5 EQU 0xe000201c + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_6 +CYREG_FPB_FP_COMP_6 EQU 0xe0002020 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_7 +CYREG_FPB_FP_COMP_7 EQU 0xe0002024 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID4 +CYREG_FPB_PID4 EQU 0xe0002fd0 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID5 +CYREG_FPB_PID5 EQU 0xe0002fd4 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID6 +CYREG_FPB_PID6 EQU 0xe0002fd8 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID7 +CYREG_FPB_PID7 EQU 0xe0002fdc + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID0 +CYREG_FPB_PID0 EQU 0xe0002fe0 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID1 +CYREG_FPB_PID1 EQU 0xe0002fe4 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID2 +CYREG_FPB_PID2 EQU 0xe0002fe8 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID3 +CYREG_FPB_PID3 EQU 0xe0002fec + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID0 +CYREG_FPB_CID0 EQU 0xe0002ff0 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID1 +CYREG_FPB_CID1 EQU 0xe0002ff4 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID2 +CYREG_FPB_CID2 EQU 0xe0002ff8 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID3 +CYREG_FPB_CID3 EQU 0xe0002ffc + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BASE +CYDEV_NVIC_BASE EQU 0xe000e000 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SIZE +CYDEV_NVIC_SIZE EQU 0x00000d3c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_INT_CTL_TYPE +CYREG_NVIC_INT_CTL_TYPE EQU 0xe000e004 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CTL +CYREG_NVIC_SYSTICK_CTL EQU 0xe000e010 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_RELOAD +CYREG_NVIC_SYSTICK_RELOAD EQU 0xe000e014 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CURRENT +CYREG_NVIC_SYSTICK_CURRENT EQU 0xe000e018 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CAL +CYREG_NVIC_SYSTICK_CAL EQU 0xe000e01c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SETENA0 +CYREG_NVIC_SETENA0 EQU 0xe000e100 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CLRENA0 +CYREG_NVIC_CLRENA0 EQU 0xe000e180 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SETPEND0 +CYREG_NVIC_SETPEND0 EQU 0xe000e200 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CLRPEND0 +CYREG_NVIC_CLRPEND0 EQU 0xe000e280 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_ACTIVE0 +CYREG_NVIC_ACTIVE0 EQU 0xe000e300 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_0 +CYREG_NVIC_PRI_0 EQU 0xe000e400 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_1 +CYREG_NVIC_PRI_1 EQU 0xe000e401 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_2 +CYREG_NVIC_PRI_2 EQU 0xe000e402 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_3 +CYREG_NVIC_PRI_3 EQU 0xe000e403 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_4 +CYREG_NVIC_PRI_4 EQU 0xe000e404 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_5 +CYREG_NVIC_PRI_5 EQU 0xe000e405 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_6 +CYREG_NVIC_PRI_6 EQU 0xe000e406 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_7 +CYREG_NVIC_PRI_7 EQU 0xe000e407 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_8 +CYREG_NVIC_PRI_8 EQU 0xe000e408 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_9 +CYREG_NVIC_PRI_9 EQU 0xe000e409 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_10 +CYREG_NVIC_PRI_10 EQU 0xe000e40a + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_11 +CYREG_NVIC_PRI_11 EQU 0xe000e40b + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_12 +CYREG_NVIC_PRI_12 EQU 0xe000e40c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_13 +CYREG_NVIC_PRI_13 EQU 0xe000e40d + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_14 +CYREG_NVIC_PRI_14 EQU 0xe000e40e + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_15 +CYREG_NVIC_PRI_15 EQU 0xe000e40f + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_16 +CYREG_NVIC_PRI_16 EQU 0xe000e410 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_17 +CYREG_NVIC_PRI_17 EQU 0xe000e411 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_18 +CYREG_NVIC_PRI_18 EQU 0xe000e412 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_19 +CYREG_NVIC_PRI_19 EQU 0xe000e413 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_20 +CYREG_NVIC_PRI_20 EQU 0xe000e414 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_21 +CYREG_NVIC_PRI_21 EQU 0xe000e415 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_22 +CYREG_NVIC_PRI_22 EQU 0xe000e416 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_23 +CYREG_NVIC_PRI_23 EQU 0xe000e417 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_24 +CYREG_NVIC_PRI_24 EQU 0xe000e418 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_25 +CYREG_NVIC_PRI_25 EQU 0xe000e419 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_26 +CYREG_NVIC_PRI_26 EQU 0xe000e41a + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_27 +CYREG_NVIC_PRI_27 EQU 0xe000e41b + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_28 +CYREG_NVIC_PRI_28 EQU 0xe000e41c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_29 +CYREG_NVIC_PRI_29 EQU 0xe000e41d + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_30 +CYREG_NVIC_PRI_30 EQU 0xe000e41e + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_31 +CYREG_NVIC_PRI_31 EQU 0xe000e41f + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CPUID_BASE +CYREG_NVIC_CPUID_BASE EQU 0xe000ed00 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_INTR_CTRL_STATE +CYREG_NVIC_INTR_CTRL_STATE EQU 0xe000ed04 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_VECT_OFFSET +CYREG_NVIC_VECT_OFFSET EQU 0xe000ed08 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_APPLN_INTR +CYREG_NVIC_APPLN_INTR EQU 0xe000ed0c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTEM_CONTROL +CYREG_NVIC_SYSTEM_CONTROL EQU 0xe000ed10 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CFG_CONTROL +CYREG_NVIC_CFG_CONTROL EQU 0xe000ed14 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_4_7 +CYREG_NVIC_SYS_PRIO_HANDLER_4_7 EQU 0xe000ed18 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_8_11 +CYREG_NVIC_SYS_PRIO_HANDLER_8_11 EQU 0xe000ed1c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_12_15 +CYREG_NVIC_SYS_PRIO_HANDLER_12_15 EQU 0xe000ed20 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_HANDLER_CSR +CYREG_NVIC_SYS_HANDLER_CSR EQU 0xe000ed24 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_MEMMAN_FAULT_STATUS +CYREG_NVIC_MEMMAN_FAULT_STATUS EQU 0xe000ed28 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_BUS_FAULT_STATUS +CYREG_NVIC_BUS_FAULT_STATUS EQU 0xe000ed29 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_USAGE_FAULT_STATUS +CYREG_NVIC_USAGE_FAULT_STATUS EQU 0xe000ed2a + ENDIF + IF :LNOT::DEF:CYREG_NVIC_HARD_FAULT_STATUS +CYREG_NVIC_HARD_FAULT_STATUS EQU 0xe000ed2c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_DEBUG_FAULT_STATUS +CYREG_NVIC_DEBUG_FAULT_STATUS EQU 0xe000ed30 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_MEMMAN_FAULT_ADD +CYREG_NVIC_MEMMAN_FAULT_ADD EQU 0xe000ed34 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_BUS_FAULT_ADD +CYREG_NVIC_BUS_FAULT_ADD EQU 0xe000ed38 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_BASE +CYDEV_CORE_DBG_BASE EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_SIZE +CYDEV_CORE_DBG_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_DBG_HLT_CS +CYREG_CORE_DBG_DBG_HLT_CS EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_DBG_REG_SEL +CYREG_CORE_DBG_DBG_REG_SEL EQU 0xe000edf4 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_DBG_REG_DATA +CYREG_CORE_DBG_DBG_REG_DATA EQU 0xe000edf8 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_EXC_MON_CTL +CYREG_CORE_DBG_EXC_MON_CTL EQU 0xe000edfc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_BASE +CYDEV_TPIU_BASE EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_SIZE +CYDEV_TPIU_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ +CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CURRENT_SYNC_PRT_SZ +CYREG_TPIU_CURRENT_SYNC_PRT_SZ EQU 0xe0040004 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ASYNC_CLK_PRESCALER +CYREG_TPIU_ASYNC_CLK_PRESCALER EQU 0xe0040010 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PROTOCOL +CYREG_TPIU_PROTOCOL EQU 0xe00400f0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_FORM_FLUSH_STAT +CYREG_TPIU_FORM_FLUSH_STAT EQU 0xe0040300 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_FORM_FLUSH_CTRL +CYREG_TPIU_FORM_FLUSH_CTRL EQU 0xe0040304 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_TRIGGER +CYREG_TPIU_TRIGGER EQU 0xe0040ee8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITETMDATA +CYREG_TPIU_ITETMDATA EQU 0xe0040eec + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITATBCTR2 +CYREG_TPIU_ITATBCTR2 EQU 0xe0040ef0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITATBCTR0 +CYREG_TPIU_ITATBCTR0 EQU 0xe0040ef8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITITMDATA +CYREG_TPIU_ITITMDATA EQU 0xe0040efc + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITCTRL +CYREG_TPIU_ITCTRL EQU 0xe0040f00 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_DEVID +CYREG_TPIU_DEVID EQU 0xe0040fc8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_DEVTYPE +CYREG_TPIU_DEVTYPE EQU 0xe0040fcc + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID4 +CYREG_TPIU_PID4 EQU 0xe0040fd0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID5 +CYREG_TPIU_PID5 EQU 0xe0040fd4 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID6 +CYREG_TPIU_PID6 EQU 0xe0040fd8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID7 +CYREG_TPIU_PID7 EQU 0xe0040fdc + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID0 +CYREG_TPIU_PID0 EQU 0xe0040fe0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID1 +CYREG_TPIU_PID1 EQU 0xe0040fe4 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID2 +CYREG_TPIU_PID2 EQU 0xe0040fe8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID3 +CYREG_TPIU_PID3 EQU 0xe0040fec + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID0 +CYREG_TPIU_CID0 EQU 0xe0040ff0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID1 +CYREG_TPIU_CID1 EQU 0xe0040ff4 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID2 +CYREG_TPIU_CID2 EQU 0xe0040ff8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID3 +CYREG_TPIU_CID3 EQU 0xe0040ffc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_BASE +CYDEV_ETM_BASE EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SIZE +CYDEV_ETM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CTL +CYREG_ETM_CTL EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CFG_CODE +CYREG_ETM_CFG_CODE EQU 0xe0041004 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TRIG_EVENT +CYREG_ETM_TRIG_EVENT EQU 0xe0041008 + ENDIF + IF :LNOT::DEF:CYREG_ETM_STATUS +CYREG_ETM_STATUS EQU 0xe0041010 + ENDIF + IF :LNOT::DEF:CYREG_ETM_SYS_CFG +CYREG_ETM_SYS_CFG EQU 0xe0041014 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TRACE_ENB_EVENT +CYREG_ETM_TRACE_ENB_EVENT EQU 0xe0041020 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TRACE_EN_CTRL1 +CYREG_ETM_TRACE_EN_CTRL1 EQU 0xe0041024 + ENDIF + IF :LNOT::DEF:CYREG_ETM_FIFOFULL_LEVEL +CYREG_ETM_FIFOFULL_LEVEL EQU 0xe004102c + ENDIF + IF :LNOT::DEF:CYREG_ETM_SYNC_FREQ +CYREG_ETM_SYNC_FREQ EQU 0xe00411e0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ETM_ID +CYREG_ETM_ETM_ID EQU 0xe00411e4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CFG_CODE_EXT +CYREG_ETM_CFG_CODE_EXT EQU 0xe00411e8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TR_SS_EMBICE_CTRL +CYREG_ETM_TR_SS_EMBICE_CTRL EQU 0xe00411f0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CS_TRACE_ID +CYREG_ETM_CS_TRACE_ID EQU 0xe0041200 + ENDIF + IF :LNOT::DEF:CYREG_ETM_OS_LOCK_ACCESS +CYREG_ETM_OS_LOCK_ACCESS EQU 0xe0041300 + ENDIF + IF :LNOT::DEF:CYREG_ETM_OS_LOCK_STATUS +CYREG_ETM_OS_LOCK_STATUS EQU 0xe0041304 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PDSR +CYREG_ETM_PDSR EQU 0xe0041314 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITMISCIN +CYREG_ETM_ITMISCIN EQU 0xe0041ee0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITTRIGOUT +CYREG_ETM_ITTRIGOUT EQU 0xe0041ee8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITATBCTR2 +CYREG_ETM_ITATBCTR2 EQU 0xe0041ef0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITATBCTR0 +CYREG_ETM_ITATBCTR0 EQU 0xe0041ef8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_INT_MODE_CTRL +CYREG_ETM_INT_MODE_CTRL EQU 0xe0041f00 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CLM_TAG_SET +CYREG_ETM_CLM_TAG_SET EQU 0xe0041fa0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CLM_TAG_CLR +CYREG_ETM_CLM_TAG_CLR EQU 0xe0041fa4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_LOCK_ACCESS +CYREG_ETM_LOCK_ACCESS EQU 0xe0041fb0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_LOCK_STATUS +CYREG_ETM_LOCK_STATUS EQU 0xe0041fb4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_AUTH_STATUS +CYREG_ETM_AUTH_STATUS EQU 0xe0041fb8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_DEV_TYPE +CYREG_ETM_DEV_TYPE EQU 0xe0041fcc + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID4 +CYREG_ETM_PID4 EQU 0xe0041fd0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID5 +CYREG_ETM_PID5 EQU 0xe0041fd4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID6 +CYREG_ETM_PID6 EQU 0xe0041fd8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID7 +CYREG_ETM_PID7 EQU 0xe0041fdc + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID0 +CYREG_ETM_PID0 EQU 0xe0041fe0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID1 +CYREG_ETM_PID1 EQU 0xe0041fe4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID2 +CYREG_ETM_PID2 EQU 0xe0041fe8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID3 +CYREG_ETM_PID3 EQU 0xe0041fec + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID0 +CYREG_ETM_CID0 EQU 0xe0041ff0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID1 +CYREG_ETM_CID1 EQU 0xe0041ff4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID2 +CYREG_ETM_CID2 EQU 0xe0041ff8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID3 +CYREG_ETM_CID3 EQU 0xe0041ffc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_BASE +CYDEV_ROM_TABLE_BASE EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_SIZE +CYDEV_ROM_TABLE_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_NVIC +CYREG_ROM_TABLE_NVIC EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_DWT +CYREG_ROM_TABLE_DWT EQU 0xe00ff004 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_FPB +CYREG_ROM_TABLE_FPB EQU 0xe00ff008 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_ITM +CYREG_ROM_TABLE_ITM EQU 0xe00ff00c + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_TPIU +CYREG_ROM_TABLE_TPIU EQU 0xe00ff010 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_ETM +CYREG_ROM_TABLE_ETM EQU 0xe00ff014 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_END +CYREG_ROM_TABLE_END EQU 0xe00ff018 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_MEMTYPE +CYREG_ROM_TABLE_MEMTYPE EQU 0xe00fffcc + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID4 +CYREG_ROM_TABLE_PID4 EQU 0xe00fffd0 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID5 +CYREG_ROM_TABLE_PID5 EQU 0xe00fffd4 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID6 +CYREG_ROM_TABLE_PID6 EQU 0xe00fffd8 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID7 +CYREG_ROM_TABLE_PID7 EQU 0xe00fffdc + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID0 +CYREG_ROM_TABLE_PID0 EQU 0xe00fffe0 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID1 +CYREG_ROM_TABLE_PID1 EQU 0xe00fffe4 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID2 +CYREG_ROM_TABLE_PID2 EQU 0xe00fffe8 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID3 +CYREG_ROM_TABLE_PID3 EQU 0xe00fffec + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID0 +CYREG_ROM_TABLE_CID0 EQU 0xe00ffff0 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID1 +CYREG_ROM_TABLE_CID1 EQU 0xe00ffff4 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID2 +CYREG_ROM_TABLE_CID2 EQU 0xe00ffff8 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID3 +CYREG_ROM_TABLE_CID3 EQU 0xe00ffffc + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SIZE +CYDEV_FLS_SIZE EQU CYDEV_FLASH_SIZE + ENDIF + IF :LNOT::DEF:CYDEV_ECC_BASE +CYDEV_ECC_BASE EQU CYDEV_FLSECC_BASE + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE +CYDEV_FLS_SECTOR_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE +CYDEV_FLS_ROW_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE +CYDEV_ECC_SECTOR_SIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_ROW_SIZE +CYDEV_ECC_ROW_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_SECTOR_SIZE +CYDEV_EEPROM_SECTOR_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_ROW_SIZE +CYDEV_EEPROM_ROW_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PERIPH_BASE +CYDEV_PERIPH_BASE EQU CYDEV_CLKDIST_BASE + ENDIF + IF :LNOT::DEF:CYCLK_LD_DISABLE +CYCLK_LD_DISABLE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYCLK_LD_SYNC_EN +CYCLK_LD_SYNC_EN EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYCLK_LD_LOAD +CYCLK_LD_LOAD EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYCLK_PIPE +CYCLK_PIPE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYCLK_SSS +CYCLK_SSS EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYCLK_EARLY +CYCLK_EARLY EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYCLK_DUTY +CYCLK_DUTY EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYCLK_SYNC +CYCLK_SYNC EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_D +CYCLK_SRC_SEL_CLK_SYNC_D EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_SYNC_DIG +CYCLK_SRC_SEL_SYNC_DIG EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_IMO +CYCLK_SRC_SEL_IMO EQU 1 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_MHZ +CYCLK_SRC_SEL_XTAL_MHZ EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALM +CYCLK_SRC_SEL_XTALM EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_ILO +CYCLK_SRC_SEL_ILO EQU 3 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_PLL +CYCLK_SRC_SEL_PLL EQU 4 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_KHZ +CYCLK_SRC_SEL_XTAL_KHZ EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALK +CYCLK_SRC_SEL_XTALK EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_G +CYCLK_SRC_SEL_DSI_G EQU 6 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_D +CYCLK_SRC_SEL_DSI_D EQU 7 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_A +CYCLK_SRC_SEL_CLK_SYNC_A EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_A +CYCLK_SRC_SEL_DSI_A EQU 7 + ENDIF + END diff --git a/source/hic_hal/cypress/psoc5lp/armcc/cyfitterrv.inc b/source/hic_hal/cypress/psoc5lp/armcc/cyfitterrv.inc new file mode 100644 index 0000000000..07a20c3718 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/armcc/cyfitterrv.inc @@ -0,0 +1,2521 @@ +; +; File Name: cyfitterrv.inc +; Description: +; +; +;------------------------------------------------------------------------------- +; Copyright (2019) Cypress Semiconductor Corporation +; or a subsidiary of Cypress Semiconductor Corporation. +; +; Licensed under the Apache License, Version 2.0 (the "License"); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +;------------------------------------------------------------------------------- + IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC +INCLUDED_CYFITTERRV_INC EQU 1 + GET cydevicerv.inc + GET cydevicerv_trm.inc + +; Pin_1 +Pin_1__0__INTTYPE EQU CYREG_PICU0_INTTYPE5 +Pin_1__0__MASK EQU 0x20 +Pin_1__0__PC EQU CYREG_PRT0_PC5 +Pin_1__0__PORT EQU 0 +Pin_1__0__SHIFT EQU 5 +Pin_1__AG EQU CYREG_PRT0_AG +Pin_1__AMUX EQU CYREG_PRT0_AMUX +Pin_1__BIE EQU CYREG_PRT0_BIE +Pin_1__BIT_MASK EQU CYREG_PRT0_BIT_MASK +Pin_1__BYP EQU CYREG_PRT0_BYP +Pin_1__CTL EQU CYREG_PRT0_CTL +Pin_1__DM0 EQU CYREG_PRT0_DM0 +Pin_1__DM1 EQU CYREG_PRT0_DM1 +Pin_1__DM2 EQU CYREG_PRT0_DM2 +Pin_1__DR EQU CYREG_PRT0_DR +Pin_1__INP_DIS EQU CYREG_PRT0_INP_DIS +Pin_1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE +Pin_1__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +Pin_1__LCD_EN EQU CYREG_PRT0_LCD_EN +Pin_1__MASK EQU 0x20 +Pin_1__PORT EQU 0 +Pin_1__PRT EQU CYREG_PRT0_PRT +Pin_1__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +Pin_1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +Pin_1__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +Pin_1__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +Pin_1__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +Pin_1__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +Pin_1__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +Pin_1__PS EQU CYREG_PRT0_PS +Pin_1__SHIFT EQU 5 +Pin_1__SLW EQU CYREG_PRT0_SLW + +; Pin_2 +Pin_2__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 +Pin_2__0__MASK EQU 0x02 +Pin_2__0__PC EQU CYREG_PRT3_PC1 +Pin_2__0__PORT EQU 3 +Pin_2__0__SHIFT EQU 1 +Pin_2__AG EQU CYREG_PRT3_AG +Pin_2__AMUX EQU CYREG_PRT3_AMUX +Pin_2__BIE EQU CYREG_PRT3_BIE +Pin_2__BIT_MASK EQU CYREG_PRT3_BIT_MASK +Pin_2__BYP EQU CYREG_PRT3_BYP +Pin_2__CTL EQU CYREG_PRT3_CTL +Pin_2__DM0 EQU CYREG_PRT3_DM0 +Pin_2__DM1 EQU CYREG_PRT3_DM1 +Pin_2__DM2 EQU CYREG_PRT3_DM2 +Pin_2__DR EQU CYREG_PRT3_DR +Pin_2__INP_DIS EQU CYREG_PRT3_INP_DIS +Pin_2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +Pin_2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +Pin_2__LCD_EN EQU CYREG_PRT3_LCD_EN +Pin_2__MASK EQU 0x02 +Pin_2__PORT EQU 3 +Pin_2__PRT EQU CYREG_PRT3_PRT +Pin_2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +Pin_2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +Pin_2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +Pin_2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +Pin_2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +Pin_2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +Pin_2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +Pin_2__PS EQU CYREG_PRT3_PS +Pin_2__SHIFT EQU 1 +Pin_2__SLW EQU CYREG_PRT3_SLW + +; Pin_3 +Pin_3__0__INTTYPE EQU CYREG_PICU0_INTTYPE6 +Pin_3__0__MASK EQU 0x40 +Pin_3__0__PC EQU CYREG_PRT0_PC6 +Pin_3__0__PORT EQU 0 +Pin_3__0__SHIFT EQU 6 +Pin_3__AG EQU CYREG_PRT0_AG +Pin_3__AMUX EQU CYREG_PRT0_AMUX +Pin_3__BIE EQU CYREG_PRT0_BIE +Pin_3__BIT_MASK EQU CYREG_PRT0_BIT_MASK +Pin_3__BYP EQU CYREG_PRT0_BYP +Pin_3__CTL EQU CYREG_PRT0_CTL +Pin_3__DM0 EQU CYREG_PRT0_DM0 +Pin_3__DM1 EQU CYREG_PRT0_DM1 +Pin_3__DM2 EQU CYREG_PRT0_DM2 +Pin_3__DR EQU CYREG_PRT0_DR +Pin_3__INP_DIS EQU CYREG_PRT0_INP_DIS +Pin_3__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE +Pin_3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +Pin_3__LCD_EN EQU CYREG_PRT0_LCD_EN +Pin_3__MASK EQU 0x40 +Pin_3__PORT EQU 0 +Pin_3__PRT EQU CYREG_PRT0_PRT +Pin_3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +Pin_3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +Pin_3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +Pin_3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +Pin_3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +Pin_3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +Pin_3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +Pin_3__PS EQU CYREG_PRT0_PS +Pin_3__SHIFT EQU 6 +Pin_3__SLW EQU CYREG_PRT0_SLW + +; Pin_4 +Pin_4__0__INTTYPE EQU CYREG_PICU3_INTTYPE7 +Pin_4__0__MASK EQU 0x80 +Pin_4__0__PC EQU CYREG_PRT3_PC7 +Pin_4__0__PORT EQU 3 +Pin_4__0__SHIFT EQU 7 +Pin_4__AG EQU CYREG_PRT3_AG +Pin_4__AMUX EQU CYREG_PRT3_AMUX +Pin_4__BIE EQU CYREG_PRT3_BIE +Pin_4__BIT_MASK EQU CYREG_PRT3_BIT_MASK +Pin_4__BYP EQU CYREG_PRT3_BYP +Pin_4__CTL EQU CYREG_PRT3_CTL +Pin_4__DM0 EQU CYREG_PRT3_DM0 +Pin_4__DM1 EQU CYREG_PRT3_DM1 +Pin_4__DM2 EQU CYREG_PRT3_DM2 +Pin_4__DR EQU CYREG_PRT3_DR +Pin_4__INP_DIS EQU CYREG_PRT3_INP_DIS +Pin_4__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +Pin_4__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +Pin_4__LCD_EN EQU CYREG_PRT3_LCD_EN +Pin_4__MASK EQU 0x80 +Pin_4__PORT EQU 3 +Pin_4__PRT EQU CYREG_PRT3_PRT +Pin_4__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +Pin_4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +Pin_4__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +Pin_4__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +Pin_4__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +Pin_4__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +Pin_4__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +Pin_4__PS EQU CYREG_PRT3_PS +Pin_4__SHIFT EQU 7 +Pin_4__SLW EQU CYREG_PRT3_SLW + +; Pin_5 +Pin_5__0__INTTYPE EQU CYREG_PICU0_INTTYPE0 +Pin_5__0__MASK EQU 0x01 +Pin_5__0__PC EQU CYREG_PRT0_PC0 +Pin_5__0__PORT EQU 0 +Pin_5__0__SHIFT EQU 0 +Pin_5__AG EQU CYREG_PRT0_AG +Pin_5__AMUX EQU CYREG_PRT0_AMUX +Pin_5__BIE EQU CYREG_PRT0_BIE +Pin_5__BIT_MASK EQU CYREG_PRT0_BIT_MASK +Pin_5__BYP EQU CYREG_PRT0_BYP +Pin_5__CTL EQU CYREG_PRT0_CTL +Pin_5__DM0 EQU CYREG_PRT0_DM0 +Pin_5__DM1 EQU CYREG_PRT0_DM1 +Pin_5__DM2 EQU CYREG_PRT0_DM2 +Pin_5__DR EQU CYREG_PRT0_DR +Pin_5__INP_DIS EQU CYREG_PRT0_INP_DIS +Pin_5__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE +Pin_5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +Pin_5__LCD_EN EQU CYREG_PRT0_LCD_EN +Pin_5__MASK EQU 0x01 +Pin_5__PORT EQU 0 +Pin_5__PRT EQU CYREG_PRT0_PRT +Pin_5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +Pin_5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +Pin_5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +Pin_5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +Pin_5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +Pin_5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +Pin_5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +Pin_5__PS EQU CYREG_PRT0_PS +Pin_5__SHIFT EQU 0 +Pin_5__SLW EQU CYREG_PRT0_SLW + +; SWDIO +SWDIO__0__INTTYPE EQU CYREG_PICU12_INTTYPE2 +SWDIO__0__MASK EQU 0x04 +SWDIO__0__PC EQU CYREG_PRT12_PC2 +SWDIO__0__PORT EQU 12 +SWDIO__0__SHIFT EQU 2 +SWDIO__AG EQU CYREG_PRT12_AG +SWDIO__BIE EQU CYREG_PRT12_BIE +SWDIO__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SWDIO__BYP EQU CYREG_PRT12_BYP +SWDIO__DM0 EQU CYREG_PRT12_DM0 +SWDIO__DM1 EQU CYREG_PRT12_DM1 +SWDIO__DM2 EQU CYREG_PRT12_DM2 +SWDIO__DR EQU CYREG_PRT12_DR +SWDIO__INP_DIS EQU CYREG_PRT12_INP_DIS +SWDIO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE +SWDIO__MASK EQU 0x04 +SWDIO__PORT EQU 12 +SWDIO__PRT EQU CYREG_PRT12_PRT +SWDIO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SWDIO__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SWDIO__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SWDIO__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SWDIO__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SWDIO__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SWDIO__PS EQU CYREG_PRT12_PS +SWDIO__SHIFT EQU 2 +SWDIO__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SWDIO__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SWDIO__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SWDIO__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SWDIO__SLW EQU CYREG_PRT12_SLW + +; USBFS +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 6 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 6 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 6 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 6 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x10 +USBFS_ep_1__INTC_NUMBER EQU 4 +USBFS_ep_1__INTC_PRIOR_NUM EQU 6 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x20 +USBFS_ep_2__INTC_NUMBER EQU 5 +USBFS_ep_2__INTC_PRIOR_NUM EQU 6 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_3__INTC_MASK EQU 0x40 +USBFS_ep_3__INTC_NUMBER EQU 6 +USBFS_ep_3__INTC_PRIOR_NUM EQU 6 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 +USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_4__INTC_MASK EQU 0x80 +USBFS_ep_4__INTC_NUMBER EQU 7 +USBFS_ep_4__INTC_PRIOR_NUM EQU 6 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_5__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_5__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_5__INTC_MASK EQU 0x100 +USBFS_ep_5__INTC_NUMBER EQU 8 +USBFS_ep_5__INTC_PRIOR_NUM EQU 7 +USBFS_ep_5__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_5__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_5__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_6__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_6__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_6__INTC_MASK EQU 0x200 +USBFS_ep_6__INTC_NUMBER EQU 9 +USBFS_ep_6__INTC_PRIOR_NUM EQU 6 +USBFS_ep_6__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_6__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_6__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_7__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_7__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_7__INTC_MASK EQU 0x400 +USBFS_ep_7__INTC_NUMBER EQU 10 +USBFS_ep_7__INTC_PRIOR_NUM EQU 6 +USBFS_ep_7__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +USBFS_ep_7__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_7__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ord_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ord_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ord_int__INTC_MASK EQU 0x2000000 +USBFS_ord_int__INTC_NUMBER EQU 25 +USBFS_ord_int__INTC_PRIOR_NUM EQU 6 +USBFS_ord_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_25 +USBFS_ord_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ord_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 6 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 +USBFS_VBUS__0__INTTYPE EQU CYREG_PICU1_INTTYPE7 +USBFS_VBUS__0__MASK EQU 0x80 +USBFS_VBUS__0__PC EQU CYREG_PRT1_PC7 +USBFS_VBUS__0__PORT EQU 1 +USBFS_VBUS__0__SHIFT EQU 7 +USBFS_VBUS__AG EQU CYREG_PRT1_AG +USBFS_VBUS__AMUX EQU CYREG_PRT1_AMUX +USBFS_VBUS__BIE EQU CYREG_PRT1_BIE +USBFS_VBUS__BIT_MASK EQU CYREG_PRT1_BIT_MASK +USBFS_VBUS__BYP EQU CYREG_PRT1_BYP +USBFS_VBUS__CTL EQU CYREG_PRT1_CTL +USBFS_VBUS__DM0 EQU CYREG_PRT1_DM0 +USBFS_VBUS__DM1 EQU CYREG_PRT1_DM1 +USBFS_VBUS__DM2 EQU CYREG_PRT1_DM2 +USBFS_VBUS__DR EQU CYREG_PRT1_DR +USBFS_VBUS__INP_DIS EQU CYREG_PRT1_INP_DIS +USBFS_VBUS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU1_BASE +USBFS_VBUS__LCD_COM_SEG EQU CYREG_PRT1_LCD_COM_SEG +USBFS_VBUS__LCD_EN EQU CYREG_PRT1_LCD_EN +USBFS_VBUS__MASK EQU 0x80 +USBFS_VBUS__PORT EQU 1 +USBFS_VBUS__PRT EQU CYREG_PRT1_PRT +USBFS_VBUS__PRTDSI__CAPS_SEL EQU CYREG_PRT1_CAPS_SEL +USBFS_VBUS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT1_DBL_SYNC_IN +USBFS_VBUS__PRTDSI__OE_SEL0 EQU CYREG_PRT1_OE_SEL0 +USBFS_VBUS__PRTDSI__OE_SEL1 EQU CYREG_PRT1_OE_SEL1 +USBFS_VBUS__PRTDSI__OUT_SEL0 EQU CYREG_PRT1_OUT_SEL0 +USBFS_VBUS__PRTDSI__OUT_SEL1 EQU CYREG_PRT1_OUT_SEL1 +USBFS_VBUS__PRTDSI__SYNC_OUT EQU CYREG_PRT1_SYNC_OUT +USBFS_VBUS__PS EQU CYREG_PRT1_PS +USBFS_VBUS__SHIFT EQU 7 +USBFS_VBUS__SLW EQU CYREG_PRT1_SLW + +; SWDCLK +SWDCLK__0__INTTYPE EQU CYREG_PICU12_INTTYPE3 +SWDCLK__0__MASK EQU 0x08 +SWDCLK__0__PC EQU CYREG_PRT12_PC3 +SWDCLK__0__PORT EQU 12 +SWDCLK__0__SHIFT EQU 3 +SWDCLK__AG EQU CYREG_PRT12_AG +SWDCLK__BIE EQU CYREG_PRT12_BIE +SWDCLK__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SWDCLK__BYP EQU CYREG_PRT12_BYP +SWDCLK__DM0 EQU CYREG_PRT12_DM0 +SWDCLK__DM1 EQU CYREG_PRT12_DM1 +SWDCLK__DM2 EQU CYREG_PRT12_DM2 +SWDCLK__DR EQU CYREG_PRT12_DR +SWDCLK__INP_DIS EQU CYREG_PRT12_INP_DIS +SWDCLK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE +SWDCLK__MASK EQU 0x08 +SWDCLK__PORT EQU 12 +SWDCLK__PRT EQU CYREG_PRT12_PRT +SWDCLK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SWDCLK__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SWDCLK__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SWDCLK__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SWDCLK__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SWDCLK__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SWDCLK__PS EQU CYREG_PRT12_PS +SWDCLK__SHIFT EQU 3 +SWDCLK__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SWDCLK__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SWDCLK__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SWDCLK__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SWDCLK__SLW EQU CYREG_PRT12_SLW + +; ADC_SAR +ADC_SAR_ADC_SAR__CLK EQU CYREG_SAR0_CLK +ADC_SAR_ADC_SAR__CSR0 EQU CYREG_SAR0_CSR0 +ADC_SAR_ADC_SAR__CSR1 EQU CYREG_SAR0_CSR1 +ADC_SAR_ADC_SAR__CSR2 EQU CYREG_SAR0_CSR2 +ADC_SAR_ADC_SAR__CSR3 EQU CYREG_SAR0_CSR3 +ADC_SAR_ADC_SAR__CSR4 EQU CYREG_SAR0_CSR4 +ADC_SAR_ADC_SAR__CSR5 EQU CYREG_SAR0_CSR5 +ADC_SAR_ADC_SAR__CSR6 EQU CYREG_SAR0_CSR6 +ADC_SAR_ADC_SAR__PM_ACT_CFG EQU CYREG_PM_ACT_CFG11 +ADC_SAR_ADC_SAR__PM_ACT_MSK EQU 0x01 +ADC_SAR_ADC_SAR__PM_STBY_CFG EQU CYREG_PM_STBY_CFG11 +ADC_SAR_ADC_SAR__PM_STBY_MSK EQU 0x01 +ADC_SAR_ADC_SAR__SW0 EQU CYREG_SAR0_SW0 +ADC_SAR_ADC_SAR__SW2 EQU CYREG_SAR0_SW2 +ADC_SAR_ADC_SAR__SW3 EQU CYREG_SAR0_SW3 +ADC_SAR_ADC_SAR__SW4 EQU CYREG_SAR0_SW4 +ADC_SAR_ADC_SAR__SW6 EQU CYREG_SAR0_SW6 +ADC_SAR_ADC_SAR__TR0 EQU CYREG_SAR0_TR0 +ADC_SAR_ADC_SAR__WRK0 EQU CYREG_SAR0_WRK0 +ADC_SAR_ADC_SAR__WRK1 EQU CYREG_SAR0_WRK1 +ADC_SAR_Bypass__0__INTTYPE EQU CYREG_PICU0_INTTYPE4 +ADC_SAR_Bypass__0__MASK EQU 0x10 +ADC_SAR_Bypass__0__PC EQU CYREG_PRT0_PC4 +ADC_SAR_Bypass__0__PORT EQU 0 +ADC_SAR_Bypass__0__SHIFT EQU 4 +ADC_SAR_Bypass__AG EQU CYREG_PRT0_AG +ADC_SAR_Bypass__AMUX EQU CYREG_PRT0_AMUX +ADC_SAR_Bypass__BIE EQU CYREG_PRT0_BIE +ADC_SAR_Bypass__BIT_MASK EQU CYREG_PRT0_BIT_MASK +ADC_SAR_Bypass__BYP EQU CYREG_PRT0_BYP +ADC_SAR_Bypass__CTL EQU CYREG_PRT0_CTL +ADC_SAR_Bypass__DM0 EQU CYREG_PRT0_DM0 +ADC_SAR_Bypass__DM1 EQU CYREG_PRT0_DM1 +ADC_SAR_Bypass__DM2 EQU CYREG_PRT0_DM2 +ADC_SAR_Bypass__DR EQU CYREG_PRT0_DR +ADC_SAR_Bypass__INP_DIS EQU CYREG_PRT0_INP_DIS +ADC_SAR_Bypass__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE +ADC_SAR_Bypass__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +ADC_SAR_Bypass__LCD_EN EQU CYREG_PRT0_LCD_EN +ADC_SAR_Bypass__MASK EQU 0x10 +ADC_SAR_Bypass__PORT EQU 0 +ADC_SAR_Bypass__PRT EQU CYREG_PRT0_PRT +ADC_SAR_Bypass__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +ADC_SAR_Bypass__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +ADC_SAR_Bypass__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +ADC_SAR_Bypass__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +ADC_SAR_Bypass__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +ADC_SAR_Bypass__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +ADC_SAR_Bypass__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +ADC_SAR_Bypass__PS EQU CYREG_PRT0_PS +ADC_SAR_Bypass__SHIFT EQU 4 +ADC_SAR_Bypass__SLW EQU CYREG_PRT0_SLW +ADC_SAR_IRQ__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +ADC_SAR_IRQ__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +ADC_SAR_IRQ__INTC_MASK EQU 0x01 +ADC_SAR_IRQ__INTC_NUMBER EQU 0 +ADC_SAR_IRQ__INTC_PRIOR_NUM EQU 7 +ADC_SAR_IRQ__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +ADC_SAR_IRQ__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +ADC_SAR_IRQ__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; Clock_1 +Clock_1__CFG0 EQU CYREG_CLKDIST_ACFG0_CFG0 +Clock_1__CFG1 EQU CYREG_CLKDIST_ACFG0_CFG1 +Clock_1__CFG2 EQU CYREG_CLKDIST_ACFG0_CFG2 +Clock_1__CFG2_SRC_SEL_MASK EQU 0x07 +Clock_1__CFG3 EQU CYREG_CLKDIST_ACFG0_CFG3 +Clock_1__CFG3_PHASE_DLY_MASK EQU 0x0F +Clock_1__INDEX EQU 0x00 +Clock_1__PM_ACT_CFG EQU CYREG_PM_ACT_CFG1 +Clock_1__PM_ACT_MSK EQU 0x01 +Clock_1__PM_STBY_CFG EQU CYREG_PM_STBY_CFG1 +Clock_1__PM_STBY_MSK EQU 0x01 + +; I2C_POT +I2C_POT_I2C_FF__ADR EQU CYREG_I2C_ADR +I2C_POT_I2C_FF__CFG EQU CYREG_I2C_CFG +I2C_POT_I2C_FF__CLK_DIV1 EQU CYREG_I2C_CLK_DIV1 +I2C_POT_I2C_FF__CLK_DIV2 EQU CYREG_I2C_CLK_DIV2 +I2C_POT_I2C_FF__CSR EQU CYREG_I2C_CSR +I2C_POT_I2C_FF__D EQU CYREG_I2C_D +I2C_POT_I2C_FF__MCSR EQU CYREG_I2C_MCSR +I2C_POT_I2C_FF__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +I2C_POT_I2C_FF__PM_ACT_MSK EQU 0x04 +I2C_POT_I2C_FF__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +I2C_POT_I2C_FF__PM_STBY_MSK EQU 0x04 +I2C_POT_I2C_FF__TMOUT_CFG0 EQU CYREG_I2C_TMOUT_CFG0 +I2C_POT_I2C_FF__TMOUT_CFG1 EQU CYREG_I2C_TMOUT_CFG1 +I2C_POT_I2C_FF__TMOUT_CSR EQU CYREG_I2C_TMOUT_CSR +I2C_POT_I2C_FF__TMOUT_SR EQU CYREG_I2C_TMOUT_SR +I2C_POT_I2C_FF__XCFG EQU CYREG_I2C_XCFG +I2C_POT_I2C_IRQ__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +I2C_POT_I2C_IRQ__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +I2C_POT_I2C_IRQ__INTC_MASK EQU 0x8000 +I2C_POT_I2C_IRQ__INTC_NUMBER EQU 15 +I2C_POT_I2C_IRQ__INTC_PRIOR_NUM EQU 7 +I2C_POT_I2C_IRQ__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_15 +I2C_POT_I2C_IRQ__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +I2C_POT_I2C_IRQ__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; I2C_UDB +I2C_UDB_bI2C_UDB_Master_ClkGen_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0 +I2C_UDB_bI2C_UDB_Master_ClkGen_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1 +I2C_UDB_bI2C_UDB_Master_ClkGen_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0 +I2C_UDB_bI2C_UDB_Master_ClkGen_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1 +I2C_UDB_bI2C_UDB_Master_ClkGen_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +I2C_UDB_bI2C_UDB_Master_ClkGen_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0 +I2C_UDB_bI2C_UDB_Master_ClkGen_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1 +I2C_UDB_bI2C_UDB_Master_ClkGen_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1 +I2C_UDB_bI2C_UDB_Master_ClkGen_u0__A0_REG EQU CYREG_B0_UDB06_A0 +I2C_UDB_bI2C_UDB_Master_ClkGen_u0__A1_REG EQU CYREG_B0_UDB06_A1 +I2C_UDB_bI2C_UDB_Master_ClkGen_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1 +I2C_UDB_bI2C_UDB_Master_ClkGen_u0__D0_REG EQU CYREG_B0_UDB06_D0 +I2C_UDB_bI2C_UDB_Master_ClkGen_u0__D1_REG EQU CYREG_B0_UDB06_D1 +I2C_UDB_bI2C_UDB_Master_ClkGen_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +I2C_UDB_bI2C_UDB_Master_ClkGen_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1 +I2C_UDB_bI2C_UDB_Master_ClkGen_u0__F0_REG EQU CYREG_B0_UDB06_F0 +I2C_UDB_bI2C_UDB_Master_ClkGen_u0__F1_REG EQU CYREG_B0_UDB06_F1 +I2C_UDB_bI2C_UDB_Shifter_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +I2C_UDB_bI2C_UDB_Shifter_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +I2C_UDB_bI2C_UDB_Shifter_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +I2C_UDB_bI2C_UDB_Shifter_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +I2C_UDB_bI2C_UDB_Shifter_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +I2C_UDB_bI2C_UDB_Shifter_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +I2C_UDB_bI2C_UDB_Shifter_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +I2C_UDB_bI2C_UDB_Shifter_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +I2C_UDB_bI2C_UDB_Shifter_u0__A0_REG EQU CYREG_B1_UDB04_A0 +I2C_UDB_bI2C_UDB_Shifter_u0__A1_REG EQU CYREG_B1_UDB04_A1 +I2C_UDB_bI2C_UDB_Shifter_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +I2C_UDB_bI2C_UDB_Shifter_u0__D0_REG EQU CYREG_B1_UDB04_D0 +I2C_UDB_bI2C_UDB_Shifter_u0__D1_REG EQU CYREG_B1_UDB04_D1 +I2C_UDB_bI2C_UDB_Shifter_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +I2C_UDB_bI2C_UDB_Shifter_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +I2C_UDB_bI2C_UDB_Shifter_u0__F0_REG EQU CYREG_B1_UDB04_F0 +I2C_UDB_bI2C_UDB_Shifter_u0__F1_REG EQU CYREG_B1_UDB04_F1 +I2C_UDB_bI2C_UDB_StsReg__0__MASK EQU 0x01 +I2C_UDB_bI2C_UDB_StsReg__0__POS EQU 0 +I2C_UDB_bI2C_UDB_StsReg__1__MASK EQU 0x02 +I2C_UDB_bI2C_UDB_StsReg__1__POS EQU 1 +I2C_UDB_bI2C_UDB_StsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +I2C_UDB_bI2C_UDB_StsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +I2C_UDB_bI2C_UDB_StsReg__2__MASK EQU 0x04 +I2C_UDB_bI2C_UDB_StsReg__2__POS EQU 2 +I2C_UDB_bI2C_UDB_StsReg__3__MASK EQU 0x08 +I2C_UDB_bI2C_UDB_StsReg__3__POS EQU 3 +I2C_UDB_bI2C_UDB_StsReg__4__MASK EQU 0x10 +I2C_UDB_bI2C_UDB_StsReg__4__POS EQU 4 +I2C_UDB_bI2C_UDB_StsReg__5__MASK EQU 0x20 +I2C_UDB_bI2C_UDB_StsReg__5__POS EQU 5 +I2C_UDB_bI2C_UDB_StsReg__6__MASK EQU 0x40 +I2C_UDB_bI2C_UDB_StsReg__6__POS EQU 6 +I2C_UDB_bI2C_UDB_StsReg__MASK EQU 0x7F +I2C_UDB_bI2C_UDB_StsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +I2C_UDB_bI2C_UDB_StsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +I2C_UDB_bI2C_UDB_StsReg__STATUS_REG EQU CYREG_B1_UDB07_ST +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__1__MASK EQU 0x02 +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__1__POS EQU 1 +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__2__MASK EQU 0x04 +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__2__POS EQU 2 +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__4__MASK EQU 0x10 +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__4__POS EQU 4 +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__5__MASK EQU 0x20 +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__5__POS EQU 5 +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__6__MASK EQU 0x40 +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__6__POS EQU 6 +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__7__MASK EQU 0x80 +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__7__POS EQU 7 +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__CONTROL_REG EQU CYREG_B0_UDB03_CTL +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__COUNT_REG EQU CYREG_B0_UDB03_CTL +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__MASK EQU 0xF6 +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +I2C_UDB_bI2C_UDB_SyncCtl_CtrlReg__PERIOD_REG EQU CYREG_B0_UDB03_MSK +I2C_UDB_I2C_IRQ__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +I2C_UDB_I2C_IRQ__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +I2C_UDB_I2C_IRQ__INTC_MASK EQU 0x02 +I2C_UDB_I2C_IRQ__INTC_NUMBER EQU 1 +I2C_UDB_I2C_IRQ__INTC_PRIOR_NUM EQU 5 +I2C_UDB_I2C_IRQ__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +I2C_UDB_I2C_IRQ__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +I2C_UDB_I2C_IRQ__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; LED_8Hz +LED_8Hz__CFG0 EQU CYREG_CLKDIST_DCFG7_CFG0 +LED_8Hz__CFG1 EQU CYREG_CLKDIST_DCFG7_CFG1 +LED_8Hz__CFG2 EQU CYREG_CLKDIST_DCFG7_CFG2 +LED_8Hz__CFG2_SRC_SEL_MASK EQU 0x07 +LED_8Hz__INDEX EQU 0x07 +LED_8Hz__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +LED_8Hz__PM_ACT_MSK EQU 0x80 +LED_8Hz__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +LED_8Hz__PM_STBY_MSK EQU 0x80 + +; LED_Red +LED_Red__0__INTTYPE EQU CYREG_PICU1_INTTYPE3 +LED_Red__0__MASK EQU 0x08 +LED_Red__0__PC EQU CYREG_PRT1_PC3 +LED_Red__0__PORT EQU 1 +LED_Red__0__SHIFT EQU 3 +LED_Red__AG EQU CYREG_PRT1_AG +LED_Red__AMUX EQU CYREG_PRT1_AMUX +LED_Red__BIE EQU CYREG_PRT1_BIE +LED_Red__BIT_MASK EQU CYREG_PRT1_BIT_MASK +LED_Red__BYP EQU CYREG_PRT1_BYP +LED_Red__CTL EQU CYREG_PRT1_CTL +LED_Red__DM0 EQU CYREG_PRT1_DM0 +LED_Red__DM1 EQU CYREG_PRT1_DM1 +LED_Red__DM2 EQU CYREG_PRT1_DM2 +LED_Red__DR EQU CYREG_PRT1_DR +LED_Red__INP_DIS EQU CYREG_PRT1_INP_DIS +LED_Red__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU1_BASE +LED_Red__LCD_COM_SEG EQU CYREG_PRT1_LCD_COM_SEG +LED_Red__LCD_EN EQU CYREG_PRT1_LCD_EN +LED_Red__MASK EQU 0x08 +LED_Red__PORT EQU 1 +LED_Red__PRT EQU CYREG_PRT1_PRT +LED_Red__PRTDSI__CAPS_SEL EQU CYREG_PRT1_CAPS_SEL +LED_Red__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT1_DBL_SYNC_IN +LED_Red__PRTDSI__OE_SEL0 EQU CYREG_PRT1_OE_SEL0 +LED_Red__PRTDSI__OE_SEL1 EQU CYREG_PRT1_OE_SEL1 +LED_Red__PRTDSI__OUT_SEL0 EQU CYREG_PRT1_OUT_SEL0 +LED_Red__PRTDSI__OUT_SEL1 EQU CYREG_PRT1_OUT_SEL1 +LED_Red__PRTDSI__SYNC_OUT EQU CYREG_PRT1_SYNC_OUT +LED_Red__PS EQU CYREG_PRT1_PS +LED_Red__SHIFT EQU 3 +LED_Red__SLW EQU CYREG_PRT1_SLW + +; SPIM_HW +SPIM_HW_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SPIM_HW_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SPIM_HW_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SPIM_HW_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SPIM_HW_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SPIM_HW_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SPIM_HW_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SPIM_HW_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SPIM_HW_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SPIM_HW_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SPIM_HW_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL +SPIM_HW_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SPIM_HW_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL +SPIM_HW_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SPIM_HW_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SPIM_HW_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SPIM_HW_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK +SPIM_HW_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SPIM_HW_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SPIM_HW_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK +SPIM_HW_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SPIM_HW_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SPIM_HW_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SPIM_HW_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL +SPIM_HW_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL +SPIM_HW_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST +SPIM_HW_BSPIM_CtrlReg__1__MASK EQU 0x02 +SPIM_HW_BSPIM_CtrlReg__1__POS EQU 1 +SPIM_HW_BSPIM_CtrlReg__2__MASK EQU 0x04 +SPIM_HW_BSPIM_CtrlReg__2__POS EQU 2 +SPIM_HW_BSPIM_CtrlReg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL +SPIM_HW_BSPIM_CtrlReg__CONTROL_REG EQU CYREG_B1_UDB11_CTL +SPIM_HW_BSPIM_CtrlReg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL +SPIM_HW_BSPIM_CtrlReg__COUNT_REG EQU CYREG_B1_UDB11_CTL +SPIM_HW_BSPIM_CtrlReg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL +SPIM_HW_BSPIM_CtrlReg__MASK EQU 0x06 +SPIM_HW_BSPIM_CtrlReg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SPIM_HW_BSPIM_CtrlReg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SPIM_HW_BSPIM_CtrlReg__PERIOD_REG EQU CYREG_B1_UDB11_MSK +SPIM_HW_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SPIM_HW_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SPIM_HW_BSPIM_RxStsReg__4__MASK EQU 0x10 +SPIM_HW_BSPIM_RxStsReg__4__POS EQU 4 +SPIM_HW_BSPIM_RxStsReg__5__MASK EQU 0x20 +SPIM_HW_BSPIM_RxStsReg__5__POS EQU 5 +SPIM_HW_BSPIM_RxStsReg__6__MASK EQU 0x40 +SPIM_HW_BSPIM_RxStsReg__6__POS EQU 6 +SPIM_HW_BSPIM_RxStsReg__MASK EQU 0x70 +SPIM_HW_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK +SPIM_HW_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SPIM_HW_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST +SPIM_HW_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0 +SPIM_HW_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1 +SPIM_HW_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0 +SPIM_HW_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1 +SPIM_HW_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SPIM_HW_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0 +SPIM_HW_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1 +SPIM_HW_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1 +SPIM_HW_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB11_A0 +SPIM_HW_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB11_A1 +SPIM_HW_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1 +SPIM_HW_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB11_D0 +SPIM_HW_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB11_D1 +SPIM_HW_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SPIM_HW_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1 +SPIM_HW_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB11_F0 +SPIM_HW_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB11_F1 +SPIM_HW_BSPIM_TxStsReg__0__MASK EQU 0x01 +SPIM_HW_BSPIM_TxStsReg__0__POS EQU 0 +SPIM_HW_BSPIM_TxStsReg__1__MASK EQU 0x02 +SPIM_HW_BSPIM_TxStsReg__1__POS EQU 1 +SPIM_HW_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SPIM_HW_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +SPIM_HW_BSPIM_TxStsReg__2__MASK EQU 0x04 +SPIM_HW_BSPIM_TxStsReg__2__POS EQU 2 +SPIM_HW_BSPIM_TxStsReg__3__MASK EQU 0x08 +SPIM_HW_BSPIM_TxStsReg__3__POS EQU 3 +SPIM_HW_BSPIM_TxStsReg__4__MASK EQU 0x10 +SPIM_HW_BSPIM_TxStsReg__4__POS EQU 4 +SPIM_HW_BSPIM_TxStsReg__MASK EQU 0x1F +SPIM_HW_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK +SPIM_HW_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SPIM_HW_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST + +; SWDXRES +SWDXRES__0__INTTYPE EQU CYREG_PICU12_INTTYPE4 +SWDXRES__0__MASK EQU 0x10 +SWDXRES__0__PC EQU CYREG_PRT12_PC4 +SWDXRES__0__PORT EQU 12 +SWDXRES__0__SHIFT EQU 4 +SWDXRES__AG EQU CYREG_PRT12_AG +SWDXRES__BIE EQU CYREG_PRT12_BIE +SWDXRES__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SWDXRES__BYP EQU CYREG_PRT12_BYP +SWDXRES__DM0 EQU CYREG_PRT12_DM0 +SWDXRES__DM1 EQU CYREG_PRT12_DM1 +SWDXRES__DM2 EQU CYREG_PRT12_DM2 +SWDXRES__DR EQU CYREG_PRT12_DR +SWDXRES__INP_DIS EQU CYREG_PRT12_INP_DIS +SWDXRES__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE +SWDXRES__MASK EQU 0x10 +SWDXRES__PORT EQU 12 +SWDXRES__PRT EQU CYREG_PRT12_PRT +SWDXRES__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SWDXRES__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SWDXRES__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SWDXRES__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SWDXRES__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SWDXRES__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SWDXRES__PS EQU CYREG_PRT12_PS +SWDXRES__SHIFT EQU 4 +SWDXRES__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SWDXRES__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SWDXRES__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SWDXRES__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SWDXRES__SLW EQU CYREG_PRT12_SLW + +; VDAC8_1 +VDAC8_1_viDAC8__CR0 EQU CYREG_DAC0_CR0 +VDAC8_1_viDAC8__CR1 EQU CYREG_DAC0_CR1 +VDAC8_1_viDAC8__D EQU CYREG_DAC0_D +VDAC8_1_viDAC8__PM_ACT_CFG EQU CYREG_PM_ACT_CFG8 +VDAC8_1_viDAC8__PM_ACT_MSK EQU 0x01 +VDAC8_1_viDAC8__PM_STBY_CFG EQU CYREG_PM_STBY_CFG8 +VDAC8_1_viDAC8__PM_STBY_MSK EQU 0x01 +VDAC8_1_viDAC8__STROBE EQU CYREG_DAC0_STROBE +VDAC8_1_viDAC8__SW0 EQU CYREG_DAC0_SW0 +VDAC8_1_viDAC8__SW2 EQU CYREG_DAC0_SW2 +VDAC8_1_viDAC8__SW3 EQU CYREG_DAC0_SW3 +VDAC8_1_viDAC8__SW4 EQU CYREG_DAC0_SW4 +VDAC8_1_viDAC8__TR EQU CYREG_DAC0_TR +VDAC8_1_viDAC8__TRIM__M1 EQU CYREG_FLSHID_CUST_TABLES_DAC0_M1 +VDAC8_1_viDAC8__TRIM__M2 EQU CYREG_FLSHID_CUST_TABLES_DAC0_M2 +VDAC8_1_viDAC8__TRIM__M3 EQU CYREG_FLSHID_CUST_TABLES_DAC0_M3 +VDAC8_1_viDAC8__TRIM__M4 EQU CYREG_FLSHID_CUST_TABLES_DAC0_M4 +VDAC8_1_viDAC8__TRIM__M5 EQU CYREG_FLSHID_CUST_TABLES_DAC0_M5 +VDAC8_1_viDAC8__TRIM__M6 EQU CYREG_FLSHID_CUST_TABLES_DAC0_M6 +VDAC8_1_viDAC8__TRIM__M7 EQU CYREG_FLSHID_CUST_TABLES_DAC0_M7 +VDAC8_1_viDAC8__TRIM__M8 EQU CYREG_FLSHID_CUST_TABLES_DAC0_M8 +VDAC8_1_viDAC8__TST EQU CYREG_DAC0_TST + +; VDAC8_2 +VDAC8_2_viDAC8__CR0 EQU CYREG_DAC1_CR0 +VDAC8_2_viDAC8__CR1 EQU CYREG_DAC1_CR1 +VDAC8_2_viDAC8__D EQU CYREG_DAC1_D +VDAC8_2_viDAC8__PM_ACT_CFG EQU CYREG_PM_ACT_CFG8 +VDAC8_2_viDAC8__PM_ACT_MSK EQU 0x02 +VDAC8_2_viDAC8__PM_STBY_CFG EQU CYREG_PM_STBY_CFG8 +VDAC8_2_viDAC8__PM_STBY_MSK EQU 0x02 +VDAC8_2_viDAC8__STROBE EQU CYREG_DAC1_STROBE +VDAC8_2_viDAC8__SW0 EQU CYREG_DAC1_SW0 +VDAC8_2_viDAC8__SW2 EQU CYREG_DAC1_SW2 +VDAC8_2_viDAC8__SW3 EQU CYREG_DAC1_SW3 +VDAC8_2_viDAC8__SW4 EQU CYREG_DAC1_SW4 +VDAC8_2_viDAC8__TR EQU CYREG_DAC1_TR +VDAC8_2_viDAC8__TRIM__M1 EQU CYREG_FLSHID_CUST_TABLES_DAC1_M1 +VDAC8_2_viDAC8__TRIM__M2 EQU CYREG_FLSHID_CUST_TABLES_DAC1_M2 +VDAC8_2_viDAC8__TRIM__M3 EQU CYREG_FLSHID_CUST_TABLES_DAC1_M3 +VDAC8_2_viDAC8__TRIM__M4 EQU CYREG_FLSHID_CUST_TABLES_DAC1_M4 +VDAC8_2_viDAC8__TRIM__M5 EQU CYREG_FLSHID_CUST_TABLES_DAC1_M5 +VDAC8_2_viDAC8__TRIM__M6 EQU CYREG_FLSHID_CUST_TABLES_DAC1_M6 +VDAC8_2_viDAC8__TRIM__M7 EQU CYREG_FLSHID_CUST_TABLES_DAC1_M7 +VDAC8_2_viDAC8__TRIM__M8 EQU CYREG_FLSHID_CUST_TABLES_DAC1_M8 +VDAC8_2_viDAC8__TST EQU CYREG_DAC1_TST + +; SPI_MISO +SPI_MISO__0__INTTYPE EQU CYREG_PICU12_INTTYPE5 +SPI_MISO__0__MASK EQU 0x20 +SPI_MISO__0__PC EQU CYREG_PRT12_PC5 +SPI_MISO__0__PORT EQU 12 +SPI_MISO__0__SHIFT EQU 5 +SPI_MISO__AG EQU CYREG_PRT12_AG +SPI_MISO__BIE EQU CYREG_PRT12_BIE +SPI_MISO__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SPI_MISO__BYP EQU CYREG_PRT12_BYP +SPI_MISO__DM0 EQU CYREG_PRT12_DM0 +SPI_MISO__DM1 EQU CYREG_PRT12_DM1 +SPI_MISO__DM2 EQU CYREG_PRT12_DM2 +SPI_MISO__DR EQU CYREG_PRT12_DR +SPI_MISO__INP_DIS EQU CYREG_PRT12_INP_DIS +SPI_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE +SPI_MISO__MASK EQU 0x20 +SPI_MISO__PORT EQU 12 +SPI_MISO__PRT EQU CYREG_PRT12_PRT +SPI_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SPI_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SPI_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SPI_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SPI_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SPI_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SPI_MISO__PS EQU CYREG_PRT12_PS +SPI_MISO__SHIFT EQU 5 +SPI_MISO__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SPI_MISO__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SPI_MISO__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SPI_MISO__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SPI_MISO__SLW EQU CYREG_PRT12_SLW + +; SPI_MOSI +SPI_MOSI__0__INTTYPE EQU CYREG_PICU15_INTTYPE1 +SPI_MOSI__0__MASK EQU 0x02 +SPI_MOSI__0__PC EQU CYREG_IO_PC_PRT15_PC1 +SPI_MOSI__0__PORT EQU 15 +SPI_MOSI__0__SHIFT EQU 1 +SPI_MOSI__AG EQU CYREG_PRT15_AG +SPI_MOSI__AMUX EQU CYREG_PRT15_AMUX +SPI_MOSI__BIE EQU CYREG_PRT15_BIE +SPI_MOSI__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SPI_MOSI__BYP EQU CYREG_PRT15_BYP +SPI_MOSI__CTL EQU CYREG_PRT15_CTL +SPI_MOSI__DM0 EQU CYREG_PRT15_DM0 +SPI_MOSI__DM1 EQU CYREG_PRT15_DM1 +SPI_MOSI__DM2 EQU CYREG_PRT15_DM2 +SPI_MOSI__DR EQU CYREG_PRT15_DR +SPI_MOSI__INP_DIS EQU CYREG_PRT15_INP_DIS +SPI_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +SPI_MOSI__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SPI_MOSI__LCD_EN EQU CYREG_PRT15_LCD_EN +SPI_MOSI__MASK EQU 0x02 +SPI_MOSI__PORT EQU 15 +SPI_MOSI__PRT EQU CYREG_PRT15_PRT +SPI_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SPI_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SPI_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SPI_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SPI_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SPI_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SPI_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SPI_MOSI__PS EQU CYREG_PRT15_PS +SPI_MOSI__SHIFT EQU 1 +SPI_MOSI__SLW EQU CYREG_PRT15_SLW + +; SPI_SCLK +SPI_SCLK__0__INTTYPE EQU CYREG_PICU15_INTTYPE2 +SPI_SCLK__0__MASK EQU 0x04 +SPI_SCLK__0__PC EQU CYREG_IO_PC_PRT15_PC2 +SPI_SCLK__0__PORT EQU 15 +SPI_SCLK__0__SHIFT EQU 2 +SPI_SCLK__AG EQU CYREG_PRT15_AG +SPI_SCLK__AMUX EQU CYREG_PRT15_AMUX +SPI_SCLK__BIE EQU CYREG_PRT15_BIE +SPI_SCLK__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SPI_SCLK__BYP EQU CYREG_PRT15_BYP +SPI_SCLK__CTL EQU CYREG_PRT15_CTL +SPI_SCLK__DM0 EQU CYREG_PRT15_DM0 +SPI_SCLK__DM1 EQU CYREG_PRT15_DM1 +SPI_SCLK__DM2 EQU CYREG_PRT15_DM2 +SPI_SCLK__DR EQU CYREG_PRT15_DR +SPI_SCLK__INP_DIS EQU CYREG_PRT15_INP_DIS +SPI_SCLK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +SPI_SCLK__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SPI_SCLK__LCD_EN EQU CYREG_PRT15_LCD_EN +SPI_SCLK__MASK EQU 0x04 +SPI_SCLK__PORT EQU 15 +SPI_SCLK__PRT EQU CYREG_PRT15_PRT +SPI_SCLK__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SPI_SCLK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SPI_SCLK__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SPI_SCLK__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SPI_SCLK__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SPI_SCLK__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SPI_SCLK__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SPI_SCLK__PS EQU CYREG_PRT15_PS +SPI_SCLK__SHIFT EQU 2 +SPI_SCLK__SLW EQU CYREG_PRT15_SLW + +; SPI_SS_0 +SPI_SS_0__0__INTTYPE EQU CYREG_PICU15_INTTYPE3 +SPI_SS_0__0__MASK EQU 0x08 +SPI_SS_0__0__PC EQU CYREG_IO_PC_PRT15_PC3 +SPI_SS_0__0__PORT EQU 15 +SPI_SS_0__0__SHIFT EQU 3 +SPI_SS_0__AG EQU CYREG_PRT15_AG +SPI_SS_0__AMUX EQU CYREG_PRT15_AMUX +SPI_SS_0__BIE EQU CYREG_PRT15_BIE +SPI_SS_0__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SPI_SS_0__BYP EQU CYREG_PRT15_BYP +SPI_SS_0__CTL EQU CYREG_PRT15_CTL +SPI_SS_0__DM0 EQU CYREG_PRT15_DM0 +SPI_SS_0__DM1 EQU CYREG_PRT15_DM1 +SPI_SS_0__DM2 EQU CYREG_PRT15_DM2 +SPI_SS_0__DR EQU CYREG_PRT15_DR +SPI_SS_0__INP_DIS EQU CYREG_PRT15_INP_DIS +SPI_SS_0__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +SPI_SS_0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SPI_SS_0__LCD_EN EQU CYREG_PRT15_LCD_EN +SPI_SS_0__MASK EQU 0x08 +SPI_SS_0__PORT EQU 15 +SPI_SS_0__PRT EQU CYREG_PRT15_PRT +SPI_SS_0__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SPI_SS_0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SPI_SS_0__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SPI_SS_0__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SPI_SS_0__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SPI_SS_0__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SPI_SS_0__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SPI_SS_0__PS EQU CYREG_PRT15_PS +SPI_SS_0__SHIFT EQU 3 +SPI_SS_0__SLW EQU CYREG_PRT15_SLW + +; SPI_SS_1 +SPI_SS_1__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 +SPI_SS_1__0__MASK EQU 0x10 +SPI_SS_1__0__PC EQU CYREG_PRT3_PC4 +SPI_SS_1__0__PORT EQU 3 +SPI_SS_1__0__SHIFT EQU 4 +SPI_SS_1__AG EQU CYREG_PRT3_AG +SPI_SS_1__AMUX EQU CYREG_PRT3_AMUX +SPI_SS_1__BIE EQU CYREG_PRT3_BIE +SPI_SS_1__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SPI_SS_1__BYP EQU CYREG_PRT3_BYP +SPI_SS_1__CTL EQU CYREG_PRT3_CTL +SPI_SS_1__DM0 EQU CYREG_PRT3_DM0 +SPI_SS_1__DM1 EQU CYREG_PRT3_DM1 +SPI_SS_1__DM2 EQU CYREG_PRT3_DM2 +SPI_SS_1__DR EQU CYREG_PRT3_DR +SPI_SS_1__INP_DIS EQU CYREG_PRT3_INP_DIS +SPI_SS_1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SPI_SS_1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SPI_SS_1__LCD_EN EQU CYREG_PRT3_LCD_EN +SPI_SS_1__MASK EQU 0x10 +SPI_SS_1__PORT EQU 3 +SPI_SS_1__PRT EQU CYREG_PRT3_PRT +SPI_SS_1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SPI_SS_1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SPI_SS_1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SPI_SS_1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SPI_SS_1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SPI_SS_1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SPI_SS_1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SPI_SS_1__PS EQU CYREG_PRT3_PS +SPI_SS_1__SHIFT EQU 4 +SPI_SS_1__SLW EQU CYREG_PRT3_SLW + +; SPI_SS_2 +SPI_SS_2__0__INTTYPE EQU CYREG_PICU3_INTTYPE6 +SPI_SS_2__0__MASK EQU 0x40 +SPI_SS_2__0__PC EQU CYREG_PRT3_PC6 +SPI_SS_2__0__PORT EQU 3 +SPI_SS_2__0__SHIFT EQU 6 +SPI_SS_2__AG EQU CYREG_PRT3_AG +SPI_SS_2__AMUX EQU CYREG_PRT3_AMUX +SPI_SS_2__BIE EQU CYREG_PRT3_BIE +SPI_SS_2__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SPI_SS_2__BYP EQU CYREG_PRT3_BYP +SPI_SS_2__CTL EQU CYREG_PRT3_CTL +SPI_SS_2__DM0 EQU CYREG_PRT3_DM0 +SPI_SS_2__DM1 EQU CYREG_PRT3_DM1 +SPI_SS_2__DM2 EQU CYREG_PRT3_DM2 +SPI_SS_2__DR EQU CYREG_PRT3_DR +SPI_SS_2__INP_DIS EQU CYREG_PRT3_INP_DIS +SPI_SS_2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SPI_SS_2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SPI_SS_2__LCD_EN EQU CYREG_PRT3_LCD_EN +SPI_SS_2__MASK EQU 0x40 +SPI_SS_2__PORT EQU 3 +SPI_SS_2__PRT EQU CYREG_PRT3_PRT +SPI_SS_2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SPI_SS_2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SPI_SS_2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SPI_SS_2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SPI_SS_2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SPI_SS_2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SPI_SS_2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SPI_SS_2__PS EQU CYREG_PRT3_PS +SPI_SS_2__SHIFT EQU 6 +SPI_SS_2__SLW EQU CYREG_PRT3_SLW + +; UART_CTS +UART_CTS__0__INTTYPE EQU CYREG_PICU15_INTTYPE5 +UART_CTS__0__MASK EQU 0x20 +UART_CTS__0__PC EQU CYREG_IO_PC_PRT15_PC5 +UART_CTS__0__PORT EQU 15 +UART_CTS__0__SHIFT EQU 5 +UART_CTS__AG EQU CYREG_PRT15_AG +UART_CTS__AMUX EQU CYREG_PRT15_AMUX +UART_CTS__BIE EQU CYREG_PRT15_BIE +UART_CTS__BIT_MASK EQU CYREG_PRT15_BIT_MASK +UART_CTS__BYP EQU CYREG_PRT15_BYP +UART_CTS__CTL EQU CYREG_PRT15_CTL +UART_CTS__DM0 EQU CYREG_PRT15_DM0 +UART_CTS__DM1 EQU CYREG_PRT15_DM1 +UART_CTS__DM2 EQU CYREG_PRT15_DM2 +UART_CTS__DR EQU CYREG_PRT15_DR +UART_CTS__INP_DIS EQU CYREG_PRT15_INP_DIS +UART_CTS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +UART_CTS__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +UART_CTS__LCD_EN EQU CYREG_PRT15_LCD_EN +UART_CTS__MASK EQU 0x20 +UART_CTS__PORT EQU 15 +UART_CTS__PRT EQU CYREG_PRT15_PRT +UART_CTS__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +UART_CTS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +UART_CTS__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +UART_CTS__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +UART_CTS__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +UART_CTS__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +UART_CTS__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +UART_CTS__PS EQU CYREG_PRT15_PS +UART_CTS__SHIFT EQU 5 +UART_CTS__SLW EQU CYREG_PRT15_SLW + +; UART_RTS +UART_RTS__0__INTTYPE EQU CYREG_PICU1_INTTYPE6 +UART_RTS__0__MASK EQU 0x40 +UART_RTS__0__PC EQU CYREG_PRT1_PC6 +UART_RTS__0__PORT EQU 1 +UART_RTS__0__SHIFT EQU 6 +UART_RTS__AG EQU CYREG_PRT1_AG +UART_RTS__AMUX EQU CYREG_PRT1_AMUX +UART_RTS__BIE EQU CYREG_PRT1_BIE +UART_RTS__BIT_MASK EQU CYREG_PRT1_BIT_MASK +UART_RTS__BYP EQU CYREG_PRT1_BYP +UART_RTS__CTL EQU CYREG_PRT1_CTL +UART_RTS__DM0 EQU CYREG_PRT1_DM0 +UART_RTS__DM1 EQU CYREG_PRT1_DM1 +UART_RTS__DM2 EQU CYREG_PRT1_DM2 +UART_RTS__DR EQU CYREG_PRT1_DR +UART_RTS__INP_DIS EQU CYREG_PRT1_INP_DIS +UART_RTS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU1_BASE +UART_RTS__LCD_COM_SEG EQU CYREG_PRT1_LCD_COM_SEG +UART_RTS__LCD_EN EQU CYREG_PRT1_LCD_EN +UART_RTS__MASK EQU 0x40 +UART_RTS__PORT EQU 1 +UART_RTS__PRT EQU CYREG_PRT1_PRT +UART_RTS__PRTDSI__CAPS_SEL EQU CYREG_PRT1_CAPS_SEL +UART_RTS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT1_DBL_SYNC_IN +UART_RTS__PRTDSI__OE_SEL0 EQU CYREG_PRT1_OE_SEL0 +UART_RTS__PRTDSI__OE_SEL1 EQU CYREG_PRT1_OE_SEL1 +UART_RTS__PRTDSI__OUT_SEL0 EQU CYREG_PRT1_OUT_SEL0 +UART_RTS__PRTDSI__OUT_SEL1 EQU CYREG_PRT1_OUT_SEL1 +UART_RTS__PRTDSI__SYNC_OUT EQU CYREG_PRT1_SYNC_OUT +UART_RTS__PS EQU CYREG_PRT1_PS +UART_RTS__SHIFT EQU 6 +UART_RTS__SLW EQU CYREG_PRT1_SLW + +; Clk_Brea1 +Clk_Brea1__CFG0 EQU CYREG_CLKDIST_DCFG6_CFG0 +Clk_Brea1__CFG1 EQU CYREG_CLKDIST_DCFG6_CFG1 +Clk_Brea1__CFG2 EQU CYREG_CLKDIST_DCFG6_CFG2 +Clk_Brea1__CFG2_SRC_SEL_MASK EQU 0x07 +Clk_Brea1__INDEX EQU 0x06 +Clk_Brea1__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +Clk_Brea1__PM_ACT_MSK EQU 0x40 +Clk_Brea1__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +Clk_Brea1__PM_STBY_MSK EQU 0x40 + +; Clk_Brea2 +Clk_Brea2__CFG0 EQU CYREG_CLKDIST_DCFG5_CFG0 +Clk_Brea2__CFG1 EQU CYREG_CLKDIST_DCFG5_CFG1 +Clk_Brea2__CFG2 EQU CYREG_CLKDIST_DCFG5_CFG2 +Clk_Brea2__CFG2_SRC_SEL_MASK EQU 0x07 +Clk_Brea2__INDEX EQU 0x05 +Clk_Brea2__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +Clk_Brea2__PM_ACT_MSK EQU 0x20 +Clk_Brea2__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +Clk_Brea2__PM_STBY_MSK EQU 0x20 + +; Clock_I2C +Clock_I2C__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 +Clock_I2C__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 +Clock_I2C__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +Clock_I2C__CFG2_SRC_SEL_MASK EQU 0x07 +Clock_I2C__INDEX EQU 0x00 +Clock_I2C__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +Clock_I2C__PM_ACT_MSK EQU 0x01 +Clock_I2C__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +Clock_I2C__PM_STBY_MSK EQU 0x01 + +; Clock_SPI +Clock_SPI__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +Clock_SPI__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +Clock_SPI__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +Clock_SPI__CFG2_SRC_SEL_MASK EQU 0x07 +Clock_SPI__INDEX EQU 0x01 +Clock_SPI__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +Clock_SPI__PM_ACT_MSK EQU 0x02 +Clock_SPI__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +Clock_SPI__PM_STBY_MSK EQU 0x02 + +; LED_Amber +LED_Amber__0__INTTYPE EQU CYREG_PICU1_INTTYPE4 +LED_Amber__0__MASK EQU 0x10 +LED_Amber__0__PC EQU CYREG_PRT1_PC4 +LED_Amber__0__PORT EQU 1 +LED_Amber__0__SHIFT EQU 4 +LED_Amber__AG EQU CYREG_PRT1_AG +LED_Amber__AMUX EQU CYREG_PRT1_AMUX +LED_Amber__BIE EQU CYREG_PRT1_BIE +LED_Amber__BIT_MASK EQU CYREG_PRT1_BIT_MASK +LED_Amber__BYP EQU CYREG_PRT1_BYP +LED_Amber__CTL EQU CYREG_PRT1_CTL +LED_Amber__DM0 EQU CYREG_PRT1_DM0 +LED_Amber__DM1 EQU CYREG_PRT1_DM1 +LED_Amber__DM2 EQU CYREG_PRT1_DM2 +LED_Amber__DR EQU CYREG_PRT1_DR +LED_Amber__INP_DIS EQU CYREG_PRT1_INP_DIS +LED_Amber__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU1_BASE +LED_Amber__LCD_COM_SEG EQU CYREG_PRT1_LCD_COM_SEG +LED_Amber__LCD_EN EQU CYREG_PRT1_LCD_EN +LED_Amber__MASK EQU 0x10 +LED_Amber__PORT EQU 1 +LED_Amber__PRT EQU CYREG_PRT1_PRT +LED_Amber__PRTDSI__CAPS_SEL EQU CYREG_PRT1_CAPS_SEL +LED_Amber__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT1_DBL_SYNC_IN +LED_Amber__PRTDSI__OE_SEL0 EQU CYREG_PRT1_OE_SEL0 +LED_Amber__PRTDSI__OE_SEL1 EQU CYREG_PRT1_OE_SEL1 +LED_Amber__PRTDSI__OUT_SEL0 EQU CYREG_PRT1_OUT_SEL0 +LED_Amber__PRTDSI__OUT_SEL1 EQU CYREG_PRT1_OUT_SEL1 +LED_Amber__PRTDSI__SYNC_OUT EQU CYREG_PRT1_SYNC_OUT +LED_Amber__PS EQU CYREG_PRT1_PS +LED_Amber__SHIFT EQU 4 +LED_Amber__SLW EQU CYREG_PRT1_SLW + +; LED_Green +LED_Green__0__INTTYPE EQU CYREG_PICU1_INTTYPE5 +LED_Green__0__MASK EQU 0x20 +LED_Green__0__PC EQU CYREG_PRT1_PC5 +LED_Green__0__PORT EQU 1 +LED_Green__0__SHIFT EQU 5 +LED_Green__AG EQU CYREG_PRT1_AG +LED_Green__AMUX EQU CYREG_PRT1_AMUX +LED_Green__BIE EQU CYREG_PRT1_BIE +LED_Green__BIT_MASK EQU CYREG_PRT1_BIT_MASK +LED_Green__BYP EQU CYREG_PRT1_BYP +LED_Green__CTL EQU CYREG_PRT1_CTL +LED_Green__DM0 EQU CYREG_PRT1_DM0 +LED_Green__DM1 EQU CYREG_PRT1_DM1 +LED_Green__DM2 EQU CYREG_PRT1_DM2 +LED_Green__DR EQU CYREG_PRT1_DR +LED_Green__INP_DIS EQU CYREG_PRT1_INP_DIS +LED_Green__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU1_BASE +LED_Green__LCD_COM_SEG EQU CYREG_PRT1_LCD_COM_SEG +LED_Green__LCD_EN EQU CYREG_PRT1_LCD_EN +LED_Green__MASK EQU 0x20 +LED_Green__PORT EQU 1 +LED_Green__PRT EQU CYREG_PRT1_PRT +LED_Green__PRTDSI__CAPS_SEL EQU CYREG_PRT1_CAPS_SEL +LED_Green__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT1_DBL_SYNC_IN +LED_Green__PRTDSI__OE_SEL0 EQU CYREG_PRT1_OE_SEL0 +LED_Green__PRTDSI__OE_SEL1 EQU CYREG_PRT1_OE_SEL1 +LED_Green__PRTDSI__OUT_SEL0 EQU CYREG_PRT1_OUT_SEL0 +LED_Green__PRTDSI__OUT_SEL1 EQU CYREG_PRT1_OUT_SEL1 +LED_Green__PRTDSI__SYNC_OUT EQU CYREG_PRT1_SYNC_OUT +LED_Green__PS EQU CYREG_PRT1_PS +LED_Green__SHIFT EQU 5 +LED_Green__SLW EQU CYREG_PRT1_SLW + +; ADC_DelSig +ADC_DelSig_DEC__COHER EQU CYREG_DEC_COHER +ADC_DelSig_DEC__CR EQU CYREG_DEC_CR +ADC_DelSig_DEC__DR1 EQU CYREG_DEC_DR1 +ADC_DelSig_DEC__DR2 EQU CYREG_DEC_DR2 +ADC_DelSig_DEC__DR2H EQU CYREG_DEC_DR2H +ADC_DelSig_DEC__GCOR EQU CYREG_DEC_GCOR +ADC_DelSig_DEC__GCORH EQU CYREG_DEC_GCORH +ADC_DelSig_DEC__GVAL EQU CYREG_DEC_GVAL +ADC_DelSig_DEC__OCOR EQU CYREG_DEC_OCOR +ADC_DelSig_DEC__OCORH EQU CYREG_DEC_OCORH +ADC_DelSig_DEC__OCORM EQU CYREG_DEC_OCORM +ADC_DelSig_DEC__OUTSAMP EQU CYREG_DEC_OUTSAMP +ADC_DelSig_DEC__OUTSAMPH EQU CYREG_DEC_OUTSAMPH +ADC_DelSig_DEC__OUTSAMPM EQU CYREG_DEC_OUTSAMPM +ADC_DelSig_DEC__OUTSAMPS EQU CYREG_DEC_OUTSAMPS +ADC_DelSig_DEC__PM_ACT_CFG EQU CYREG_PM_ACT_CFG10 +ADC_DelSig_DEC__PM_ACT_MSK EQU 0x01 +ADC_DelSig_DEC__PM_STBY_CFG EQU CYREG_PM_STBY_CFG10 +ADC_DelSig_DEC__PM_STBY_MSK EQU 0x01 +ADC_DelSig_DEC__SHIFT1 EQU CYREG_DEC_SHIFT1 +ADC_DelSig_DEC__SHIFT2 EQU CYREG_DEC_SHIFT2 +ADC_DelSig_DEC__SR EQU CYREG_DEC_SR +ADC_DelSig_DEC__TRIM__M1 EQU CYREG_FLSHID_CUST_TABLES_DEC_M1 +ADC_DelSig_DEC__TRIM__M2 EQU CYREG_FLSHID_CUST_TABLES_DEC_M2 +ADC_DelSig_DEC__TRIM__M3 EQU CYREG_FLSHID_CUST_TABLES_DEC_M3 +ADC_DelSig_DEC__TRIM__M4 EQU CYREG_FLSHID_CUST_TABLES_DEC_M4 +ADC_DelSig_DEC__TRIM__M5 EQU CYREG_FLSHID_CUST_TABLES_DEC_M5 +ADC_DelSig_DEC__TRIM__M6 EQU CYREG_FLSHID_CUST_TABLES_DEC_M6 +ADC_DelSig_DEC__TRIM__M7 EQU CYREG_FLSHID_CUST_TABLES_DEC_M7 +ADC_DelSig_DEC__TRIM__M8 EQU CYREG_FLSHID_CUST_TABLES_DEC_M8 +ADC_DelSig_DSM__BUF0 EQU CYREG_DSM0_BUF0 +ADC_DelSig_DSM__BUF1 EQU CYREG_DSM0_BUF1 +ADC_DelSig_DSM__BUF2 EQU CYREG_DSM0_BUF2 +ADC_DelSig_DSM__BUF3 EQU CYREG_DSM0_BUF3 +ADC_DelSig_DSM__CLK EQU CYREG_DSM0_CLK +ADC_DelSig_DSM__CR0 EQU CYREG_DSM0_CR0 +ADC_DelSig_DSM__CR1 EQU CYREG_DSM0_CR1 +ADC_DelSig_DSM__CR10 EQU CYREG_DSM0_CR10 +ADC_DelSig_DSM__CR11 EQU CYREG_DSM0_CR11 +ADC_DelSig_DSM__CR12 EQU CYREG_DSM0_CR12 +ADC_DelSig_DSM__CR13 EQU CYREG_DSM0_CR13 +ADC_DelSig_DSM__CR14 EQU CYREG_DSM0_CR14 +ADC_DelSig_DSM__CR15 EQU CYREG_DSM0_CR15 +ADC_DelSig_DSM__CR16 EQU CYREG_DSM0_CR16 +ADC_DelSig_DSM__CR17 EQU CYREG_DSM0_CR17 +ADC_DelSig_DSM__CR2 EQU CYREG_DSM0_CR2 +ADC_DelSig_DSM__CR3 EQU CYREG_DSM0_CR3 +ADC_DelSig_DSM__CR4 EQU CYREG_DSM0_CR4 +ADC_DelSig_DSM__CR5 EQU CYREG_DSM0_CR5 +ADC_DelSig_DSM__CR6 EQU CYREG_DSM0_CR6 +ADC_DelSig_DSM__CR7 EQU CYREG_DSM0_CR7 +ADC_DelSig_DSM__CR8 EQU CYREG_DSM0_CR8 +ADC_DelSig_DSM__CR9 EQU CYREG_DSM0_CR9 +ADC_DelSig_DSM__DEM0 EQU CYREG_DSM0_DEM0 +ADC_DelSig_DSM__DEM1 EQU CYREG_DSM0_DEM1 +ADC_DelSig_DSM__MISC EQU CYREG_DSM0_MISC +ADC_DelSig_DSM__OUT0 EQU CYREG_DSM0_OUT0 +ADC_DelSig_DSM__OUT1 EQU CYREG_DSM0_OUT1 +ADC_DelSig_DSM__REF0 EQU CYREG_DSM0_REF0 +ADC_DelSig_DSM__REF1 EQU CYREG_DSM0_REF1 +ADC_DelSig_DSM__REF2 EQU CYREG_DSM0_REF2 +ADC_DelSig_DSM__REF3 EQU CYREG_DSM0_REF3 +ADC_DelSig_DSM__RSVD1 EQU CYREG_DSM0_RSVD1 +ADC_DelSig_DSM__SW0 EQU CYREG_DSM0_SW0 +ADC_DelSig_DSM__SW2 EQU CYREG_DSM0_SW2 +ADC_DelSig_DSM__SW3 EQU CYREG_DSM0_SW3 +ADC_DelSig_DSM__SW4 EQU CYREG_DSM0_SW4 +ADC_DelSig_DSM__SW6 EQU CYREG_DSM0_SW6 +ADC_DelSig_DSM__TR0 EQU CYREG_NPUMP_DSM_TR0 +ADC_DelSig_DSM__TST0 EQU CYREG_DSM0_TST0 +ADC_DelSig_DSM__TST1 EQU CYREG_DSM0_TST1 +ADC_DelSig_Ext_CP_Clk__CFG0 EQU CYREG_CLKDIST_DCFG3_CFG0 +ADC_DelSig_Ext_CP_Clk__CFG1 EQU CYREG_CLKDIST_DCFG3_CFG1 +ADC_DelSig_Ext_CP_Clk__CFG2 EQU CYREG_CLKDIST_DCFG3_CFG2 +ADC_DelSig_Ext_CP_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +ADC_DelSig_Ext_CP_Clk__INDEX EQU 0x03 +ADC_DelSig_Ext_CP_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +ADC_DelSig_Ext_CP_Clk__PM_ACT_MSK EQU 0x08 +ADC_DelSig_Ext_CP_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +ADC_DelSig_Ext_CP_Clk__PM_STBY_MSK EQU 0x08 +ADC_DelSig_IRQ__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +ADC_DelSig_IRQ__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +ADC_DelSig_IRQ__INTC_MASK EQU 0x20000000 +ADC_DelSig_IRQ__INTC_NUMBER EQU 29 +ADC_DelSig_IRQ__INTC_PRIOR_NUM EQU 6 +ADC_DelSig_IRQ__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_29 +ADC_DelSig_IRQ__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +ADC_DelSig_IRQ__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; Clock_UART +Clock_UART__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 +Clock_UART__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 +Clock_UART__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2 +Clock_UART__CFG2_SRC_SEL_MASK EQU 0x07 +Clock_UART__INDEX EQU 0x02 +Clock_UART__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +Clock_UART__PM_ACT_MSK EQU 0x04 +Clock_UART__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +Clock_UART__PM_STBY_MSK EQU 0x04 + +; DIGPOT_SCL +DIGPOT_SCL__0__INTTYPE EQU CYREG_PICU2_INTTYPE5 +DIGPOT_SCL__0__MASK EQU 0x20 +DIGPOT_SCL__0__PC EQU CYREG_PRT2_PC5 +DIGPOT_SCL__0__PORT EQU 2 +DIGPOT_SCL__0__SHIFT EQU 5 +DIGPOT_SCL__AG EQU CYREG_PRT2_AG +DIGPOT_SCL__AMUX EQU CYREG_PRT2_AMUX +DIGPOT_SCL__BIE EQU CYREG_PRT2_BIE +DIGPOT_SCL__BIT_MASK EQU CYREG_PRT2_BIT_MASK +DIGPOT_SCL__BYP EQU CYREG_PRT2_BYP +DIGPOT_SCL__CTL EQU CYREG_PRT2_CTL +DIGPOT_SCL__DM0 EQU CYREG_PRT2_DM0 +DIGPOT_SCL__DM1 EQU CYREG_PRT2_DM1 +DIGPOT_SCL__DM2 EQU CYREG_PRT2_DM2 +DIGPOT_SCL__DR EQU CYREG_PRT2_DR +DIGPOT_SCL__INP_DIS EQU CYREG_PRT2_INP_DIS +DIGPOT_SCL__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU2_BASE +DIGPOT_SCL__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +DIGPOT_SCL__LCD_EN EQU CYREG_PRT2_LCD_EN +DIGPOT_SCL__MASK EQU 0x20 +DIGPOT_SCL__PORT EQU 2 +DIGPOT_SCL__PRT EQU CYREG_PRT2_PRT +DIGPOT_SCL__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +DIGPOT_SCL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +DIGPOT_SCL__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +DIGPOT_SCL__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +DIGPOT_SCL__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +DIGPOT_SCL__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +DIGPOT_SCL__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +DIGPOT_SCL__PS EQU CYREG_PRT2_PS +DIGPOT_SCL__SHIFT EQU 5 +DIGPOT_SCL__SLW EQU CYREG_PRT2_SLW + +; DIGPOT_SDA +DIGPOT_SDA__0__INTTYPE EQU CYREG_PICU2_INTTYPE6 +DIGPOT_SDA__0__MASK EQU 0x40 +DIGPOT_SDA__0__PC EQU CYREG_PRT2_PC6 +DIGPOT_SDA__0__PORT EQU 2 +DIGPOT_SDA__0__SHIFT EQU 6 +DIGPOT_SDA__AG EQU CYREG_PRT2_AG +DIGPOT_SDA__AMUX EQU CYREG_PRT2_AMUX +DIGPOT_SDA__BIE EQU CYREG_PRT2_BIE +DIGPOT_SDA__BIT_MASK EQU CYREG_PRT2_BIT_MASK +DIGPOT_SDA__BYP EQU CYREG_PRT2_BYP +DIGPOT_SDA__CTL EQU CYREG_PRT2_CTL +DIGPOT_SDA__DM0 EQU CYREG_PRT2_DM0 +DIGPOT_SDA__DM1 EQU CYREG_PRT2_DM1 +DIGPOT_SDA__DM2 EQU CYREG_PRT2_DM2 +DIGPOT_SDA__DR EQU CYREG_PRT2_DR +DIGPOT_SDA__INP_DIS EQU CYREG_PRT2_INP_DIS +DIGPOT_SDA__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU2_BASE +DIGPOT_SDA__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +DIGPOT_SDA__LCD_EN EQU CYREG_PRT2_LCD_EN +DIGPOT_SDA__MASK EQU 0x40 +DIGPOT_SDA__PORT EQU 2 +DIGPOT_SDA__PRT EQU CYREG_PRT2_PRT +DIGPOT_SDA__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +DIGPOT_SDA__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +DIGPOT_SDA__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +DIGPOT_SDA__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +DIGPOT_SDA__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +DIGPOT_SDA__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +DIGPOT_SDA__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +DIGPOT_SDA__PS EQU CYREG_PRT2_PS +DIGPOT_SDA__SHIFT EQU 6 +DIGPOT_SDA__SLW EQU CYREG_PRT2_SLW + +; Pin_I2C_SCL +Pin_I2C_SCL__0__INTTYPE EQU CYREG_PICU12_INTTYPE0 +Pin_I2C_SCL__0__MASK EQU 0x01 +Pin_I2C_SCL__0__PC EQU CYREG_PRT12_PC0 +Pin_I2C_SCL__0__PORT EQU 12 +Pin_I2C_SCL__0__SHIFT EQU 0 +Pin_I2C_SCL__AG EQU CYREG_PRT12_AG +Pin_I2C_SCL__BIE EQU CYREG_PRT12_BIE +Pin_I2C_SCL__BIT_MASK EQU CYREG_PRT12_BIT_MASK +Pin_I2C_SCL__BYP EQU CYREG_PRT12_BYP +Pin_I2C_SCL__DM0 EQU CYREG_PRT12_DM0 +Pin_I2C_SCL__DM1 EQU CYREG_PRT12_DM1 +Pin_I2C_SCL__DM2 EQU CYREG_PRT12_DM2 +Pin_I2C_SCL__DR EQU CYREG_PRT12_DR +Pin_I2C_SCL__INP_DIS EQU CYREG_PRT12_INP_DIS +Pin_I2C_SCL__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE +Pin_I2C_SCL__MASK EQU 0x01 +Pin_I2C_SCL__PORT EQU 12 +Pin_I2C_SCL__PRT EQU CYREG_PRT12_PRT +Pin_I2C_SCL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +Pin_I2C_SCL__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +Pin_I2C_SCL__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +Pin_I2C_SCL__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +Pin_I2C_SCL__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +Pin_I2C_SCL__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +Pin_I2C_SCL__PS EQU CYREG_PRT12_PS +Pin_I2C_SCL__SHIFT EQU 0 +Pin_I2C_SCL__SIO_CFG EQU CYREG_PRT12_SIO_CFG +Pin_I2C_SCL__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +Pin_I2C_SCL__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +Pin_I2C_SCL__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +Pin_I2C_SCL__SLW EQU CYREG_PRT12_SLW + +; Pin_I2C_SDA +Pin_I2C_SDA__0__INTTYPE EQU CYREG_PICU12_INTTYPE1 +Pin_I2C_SDA__0__MASK EQU 0x02 +Pin_I2C_SDA__0__PC EQU CYREG_PRT12_PC1 +Pin_I2C_SDA__0__PORT EQU 12 +Pin_I2C_SDA__0__SHIFT EQU 1 +Pin_I2C_SDA__AG EQU CYREG_PRT12_AG +Pin_I2C_SDA__BIE EQU CYREG_PRT12_BIE +Pin_I2C_SDA__BIT_MASK EQU CYREG_PRT12_BIT_MASK +Pin_I2C_SDA__BYP EQU CYREG_PRT12_BYP +Pin_I2C_SDA__DM0 EQU CYREG_PRT12_DM0 +Pin_I2C_SDA__DM1 EQU CYREG_PRT12_DM1 +Pin_I2C_SDA__DM2 EQU CYREG_PRT12_DM2 +Pin_I2C_SDA__DR EQU CYREG_PRT12_DR +Pin_I2C_SDA__INP_DIS EQU CYREG_PRT12_INP_DIS +Pin_I2C_SDA__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE +Pin_I2C_SDA__MASK EQU 0x02 +Pin_I2C_SDA__PORT EQU 12 +Pin_I2C_SDA__PRT EQU CYREG_PRT12_PRT +Pin_I2C_SDA__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +Pin_I2C_SDA__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +Pin_I2C_SDA__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +Pin_I2C_SDA__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +Pin_I2C_SDA__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +Pin_I2C_SDA__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +Pin_I2C_SDA__PS EQU CYREG_PRT12_PS +Pin_I2C_SDA__SHIFT EQU 1 +Pin_I2C_SDA__SIO_CFG EQU CYREG_PRT12_SIO_CFG +Pin_I2C_SDA__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +Pin_I2C_SDA__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +Pin_I2C_SDA__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +Pin_I2C_SDA__SLW EQU CYREG_PRT12_SLW + +; Pin_UART_Rx +Pin_UART_Rx__0__INTTYPE EQU CYREG_PICU12_INTTYPE7 +Pin_UART_Rx__0__MASK EQU 0x80 +Pin_UART_Rx__0__PC EQU CYREG_PRT12_PC7 +Pin_UART_Rx__0__PORT EQU 12 +Pin_UART_Rx__0__SHIFT EQU 7 +Pin_UART_Rx__AG EQU CYREG_PRT12_AG +Pin_UART_Rx__BIE EQU CYREG_PRT12_BIE +Pin_UART_Rx__BIT_MASK EQU CYREG_PRT12_BIT_MASK +Pin_UART_Rx__BYP EQU CYREG_PRT12_BYP +Pin_UART_Rx__DM0 EQU CYREG_PRT12_DM0 +Pin_UART_Rx__DM1 EQU CYREG_PRT12_DM1 +Pin_UART_Rx__DM2 EQU CYREG_PRT12_DM2 +Pin_UART_Rx__DR EQU CYREG_PRT12_DR +Pin_UART_Rx__INP_DIS EQU CYREG_PRT12_INP_DIS +Pin_UART_Rx__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE +Pin_UART_Rx__MASK EQU 0x80 +Pin_UART_Rx__PORT EQU 12 +Pin_UART_Rx__PRT EQU CYREG_PRT12_PRT +Pin_UART_Rx__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +Pin_UART_Rx__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +Pin_UART_Rx__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +Pin_UART_Rx__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +Pin_UART_Rx__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +Pin_UART_Rx__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +Pin_UART_Rx__PS EQU CYREG_PRT12_PS +Pin_UART_Rx__SHIFT EQU 7 +Pin_UART_Rx__SIO_CFG EQU CYREG_PRT12_SIO_CFG +Pin_UART_Rx__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +Pin_UART_Rx__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +Pin_UART_Rx__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +Pin_UART_Rx__SLW EQU CYREG_PRT12_SLW + +; Pin_UART_Tx +Pin_UART_Tx__0__INTTYPE EQU CYREG_PICU12_INTTYPE6 +Pin_UART_Tx__0__MASK EQU 0x40 +Pin_UART_Tx__0__PC EQU CYREG_PRT12_PC6 +Pin_UART_Tx__0__PORT EQU 12 +Pin_UART_Tx__0__SHIFT EQU 6 +Pin_UART_Tx__AG EQU CYREG_PRT12_AG +Pin_UART_Tx__BIE EQU CYREG_PRT12_BIE +Pin_UART_Tx__BIT_MASK EQU CYREG_PRT12_BIT_MASK +Pin_UART_Tx__BYP EQU CYREG_PRT12_BYP +Pin_UART_Tx__DM0 EQU CYREG_PRT12_DM0 +Pin_UART_Tx__DM1 EQU CYREG_PRT12_DM1 +Pin_UART_Tx__DM2 EQU CYREG_PRT12_DM2 +Pin_UART_Tx__DR EQU CYREG_PRT12_DR +Pin_UART_Tx__INP_DIS EQU CYREG_PRT12_INP_DIS +Pin_UART_Tx__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE +Pin_UART_Tx__MASK EQU 0x40 +Pin_UART_Tx__PORT EQU 12 +Pin_UART_Tx__PRT EQU CYREG_PRT12_PRT +Pin_UART_Tx__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +Pin_UART_Tx__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +Pin_UART_Tx__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +Pin_UART_Tx__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +Pin_UART_Tx__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +Pin_UART_Tx__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +Pin_UART_Tx__PS EQU CYREG_PRT12_PS +Pin_UART_Tx__SHIFT EQU 6 +Pin_UART_Tx__SIO_CFG EQU CYREG_PRT12_SIO_CFG +Pin_UART_Tx__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +Pin_UART_Tx__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +Pin_UART_Tx__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +Pin_UART_Tx__SLW EQU CYREG_PRT12_SLW + +; Pin_VTarget +Pin_VTarget__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 +Pin_VTarget__0__MASK EQU 0x08 +Pin_VTarget__0__PC EQU CYREG_PRT3_PC3 +Pin_VTarget__0__PORT EQU 3 +Pin_VTarget__0__SHIFT EQU 3 +Pin_VTarget__AG EQU CYREG_PRT3_AG +Pin_VTarget__AMUX EQU CYREG_PRT3_AMUX +Pin_VTarget__BIE EQU CYREG_PRT3_BIE +Pin_VTarget__BIT_MASK EQU CYREG_PRT3_BIT_MASK +Pin_VTarget__BYP EQU CYREG_PRT3_BYP +Pin_VTarget__CTL EQU CYREG_PRT3_CTL +Pin_VTarget__DM0 EQU CYREG_PRT3_DM0 +Pin_VTarget__DM1 EQU CYREG_PRT3_DM1 +Pin_VTarget__DM2 EQU CYREG_PRT3_DM2 +Pin_VTarget__DR EQU CYREG_PRT3_DR +Pin_VTarget__INP_DIS EQU CYREG_PRT3_INP_DIS +Pin_VTarget__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +Pin_VTarget__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +Pin_VTarget__LCD_EN EQU CYREG_PRT3_LCD_EN +Pin_VTarget__MASK EQU 0x08 +Pin_VTarget__PORT EQU 3 +Pin_VTarget__PRT EQU CYREG_PRT3_PRT +Pin_VTarget__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +Pin_VTarget__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +Pin_VTarget__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +Pin_VTarget__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +Pin_VTarget__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +Pin_VTarget__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +Pin_VTarget__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +Pin_VTarget__PS EQU CYREG_PRT3_PS +Pin_VTarget__SHIFT EQU 3 +Pin_VTarget__SLW EQU CYREG_PRT3_SLW + +; SPI_SS_CTRL +SPI_SS_CTRL_Sync_ctrl_reg__0__MASK EQU 0x01 +SPI_SS_CTRL_Sync_ctrl_reg__0__POS EQU 0 +SPI_SS_CTRL_Sync_ctrl_reg__1__MASK EQU 0x02 +SPI_SS_CTRL_Sync_ctrl_reg__1__POS EQU 1 +SPI_SS_CTRL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SPI_SS_CTRL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SPI_SS_CTRL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SPI_SS_CTRL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SPI_SS_CTRL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SPI_SS_CTRL_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SPI_SS_CTRL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SPI_SS_CTRL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SPI_SS_CTRL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SPI_SS_CTRL_Sync_ctrl_reg__2__MASK EQU 0x04 +SPI_SS_CTRL_Sync_ctrl_reg__2__POS EQU 2 +SPI_SS_CTRL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SPI_SS_CTRL_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB05_CTL +SPI_SS_CTRL_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SPI_SS_CTRL_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB05_CTL +SPI_SS_CTRL_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SPI_SS_CTRL_Sync_ctrl_reg__MASK EQU 0x07 +SPI_SS_CTRL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SPI_SS_CTRL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SPI_SS_CTRL_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB05_MSK + +; UART_Bridge +UART_Bridge_BUART_sRX_RxBitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL +UART_Bridge_BUART_sRX_RxBitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL +UART_Bridge_BUART_sRX_RxBitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL +UART_Bridge_BUART_sRX_RxBitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL +UART_Bridge_BUART_sRX_RxBitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL +UART_Bridge_BUART_sRX_RxBitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK +UART_Bridge_BUART_sRX_RxBitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK +UART_Bridge_BUART_sRX_RxBitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK +UART_Bridge_BUART_sRX_RxBitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK +UART_Bridge_BUART_sRX_RxBitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL +UART_Bridge_BUART_sRX_RxBitCounter__CONTROL_REG EQU CYREG_B0_UDB09_CTL +UART_Bridge_BUART_sRX_RxBitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL +UART_Bridge_BUART_sRX_RxBitCounter__COUNT_REG EQU CYREG_B0_UDB09_CTL +UART_Bridge_BUART_sRX_RxBitCounter__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL +UART_Bridge_BUART_sRX_RxBitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +UART_Bridge_BUART_sRX_RxBitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +UART_Bridge_BUART_sRX_RxBitCounter__PERIOD_REG EQU CYREG_B0_UDB09_MSK +UART_Bridge_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL +UART_Bridge_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST +UART_Bridge_BUART_sRX_RxBitCounter_ST__MASK_REG EQU CYREG_B0_UDB09_MSK +UART_Bridge_BUART_sRX_RxBitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +UART_Bridge_BUART_sRX_RxBitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +UART_Bridge_BUART_sRX_RxBitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL +UART_Bridge_BUART_sRX_RxBitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB09_ST_CTL +UART_Bridge_BUART_sRX_RxBitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB09_ST_CTL +UART_Bridge_BUART_sRX_RxBitCounter_ST__STATUS_REG EQU CYREG_B0_UDB09_ST +UART_Bridge_BUART_sRX_RxShifter_u0__16BIT_A0_REG EQU CYREG_B1_UDB09_10_A0 +UART_Bridge_BUART_sRX_RxShifter_u0__16BIT_A1_REG EQU CYREG_B1_UDB09_10_A1 +UART_Bridge_BUART_sRX_RxShifter_u0__16BIT_D0_REG EQU CYREG_B1_UDB09_10_D0 +UART_Bridge_BUART_sRX_RxShifter_u0__16BIT_D1_REG EQU CYREG_B1_UDB09_10_D1 +UART_Bridge_BUART_sRX_RxShifter_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL +UART_Bridge_BUART_sRX_RxShifter_u0__16BIT_F0_REG EQU CYREG_B1_UDB09_10_F0 +UART_Bridge_BUART_sRX_RxShifter_u0__16BIT_F1_REG EQU CYREG_B1_UDB09_10_F1 +UART_Bridge_BUART_sRX_RxShifter_u0__A0_A1_REG EQU CYREG_B1_UDB09_A0_A1 +UART_Bridge_BUART_sRX_RxShifter_u0__A0_REG EQU CYREG_B1_UDB09_A0 +UART_Bridge_BUART_sRX_RxShifter_u0__A1_REG EQU CYREG_B1_UDB09_A1 +UART_Bridge_BUART_sRX_RxShifter_u0__D0_D1_REG EQU CYREG_B1_UDB09_D0_D1 +UART_Bridge_BUART_sRX_RxShifter_u0__D0_REG EQU CYREG_B1_UDB09_D0 +UART_Bridge_BUART_sRX_RxShifter_u0__D1_REG EQU CYREG_B1_UDB09_D1 +UART_Bridge_BUART_sRX_RxShifter_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL +UART_Bridge_BUART_sRX_RxShifter_u0__F0_F1_REG EQU CYREG_B1_UDB09_F0_F1 +UART_Bridge_BUART_sRX_RxShifter_u0__F0_REG EQU CYREG_B1_UDB09_F0 +UART_Bridge_BUART_sRX_RxShifter_u0__F1_REG EQU CYREG_B1_UDB09_F1 +UART_Bridge_BUART_sRX_RxSts__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL +UART_Bridge_BUART_sRX_RxSts__16BIT_STATUS_REG EQU CYREG_B1_UDB09_10_ST +UART_Bridge_BUART_sRX_RxSts__3__MASK EQU 0x08 +UART_Bridge_BUART_sRX_RxSts__3__POS EQU 3 +UART_Bridge_BUART_sRX_RxSts__4__MASK EQU 0x10 +UART_Bridge_BUART_sRX_RxSts__4__POS EQU 4 +UART_Bridge_BUART_sRX_RxSts__5__MASK EQU 0x20 +UART_Bridge_BUART_sRX_RxSts__5__POS EQU 5 +UART_Bridge_BUART_sRX_RxSts__MASK EQU 0x38 +UART_Bridge_BUART_sRX_RxSts__MASK_REG EQU CYREG_B1_UDB09_MSK +UART_Bridge_BUART_sRX_RxSts__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL +UART_Bridge_BUART_sRX_RxSts__STATUS_REG EQU CYREG_B1_UDB09_ST +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG EQU CYREG_B0_UDB10_11_A0 +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG EQU CYREG_B0_UDB10_11_A1 +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG EQU CYREG_B0_UDB10_11_D0 +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG EQU CYREG_B0_UDB10_11_D1 +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG EQU CYREG_B0_UDB10_11_F0 +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG EQU CYREG_B0_UDB10_11_F1 +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG EQU CYREG_B0_UDB10_A0_A1 +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG EQU CYREG_B0_UDB10_A0 +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG EQU CYREG_B0_UDB10_A1 +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG EQU CYREG_B0_UDB10_D0_D1 +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG EQU CYREG_B0_UDB10_D0 +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG EQU CYREG_B0_UDB10_D1 +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG EQU CYREG_B0_UDB10_F0_F1 +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG EQU CYREG_B0_UDB10_F0 +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG EQU CYREG_B0_UDB10_F1 +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +UART_Bridge_BUART_sTX_sCLOCK_TxBitClkGen__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +UART_Bridge_BUART_sTX_TxShifter_u0__16BIT_A0_REG EQU CYREG_B0_UDB12_13_A0 +UART_Bridge_BUART_sTX_TxShifter_u0__16BIT_A1_REG EQU CYREG_B0_UDB12_13_A1 +UART_Bridge_BUART_sTX_TxShifter_u0__16BIT_D0_REG EQU CYREG_B0_UDB12_13_D0 +UART_Bridge_BUART_sTX_TxShifter_u0__16BIT_D1_REG EQU CYREG_B0_UDB12_13_D1 +UART_Bridge_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +UART_Bridge_BUART_sTX_TxShifter_u0__16BIT_F0_REG EQU CYREG_B0_UDB12_13_F0 +UART_Bridge_BUART_sTX_TxShifter_u0__16BIT_F1_REG EQU CYREG_B0_UDB12_13_F1 +UART_Bridge_BUART_sTX_TxShifter_u0__A0_A1_REG EQU CYREG_B0_UDB12_A0_A1 +UART_Bridge_BUART_sTX_TxShifter_u0__A0_REG EQU CYREG_B0_UDB12_A0 +UART_Bridge_BUART_sTX_TxShifter_u0__A1_REG EQU CYREG_B0_UDB12_A1 +UART_Bridge_BUART_sTX_TxShifter_u0__D0_D1_REG EQU CYREG_B0_UDB12_D0_D1 +UART_Bridge_BUART_sTX_TxShifter_u0__D0_REG EQU CYREG_B0_UDB12_D0 +UART_Bridge_BUART_sTX_TxShifter_u0__D1_REG EQU CYREG_B0_UDB12_D1 +UART_Bridge_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +UART_Bridge_BUART_sTX_TxShifter_u0__F0_F1_REG EQU CYREG_B0_UDB12_F0_F1 +UART_Bridge_BUART_sTX_TxShifter_u0__F0_REG EQU CYREG_B0_UDB12_F0 +UART_Bridge_BUART_sTX_TxShifter_u0__F1_REG EQU CYREG_B0_UDB12_F1 +UART_Bridge_BUART_sTX_TxSts__0__MASK EQU 0x01 +UART_Bridge_BUART_sTX_TxSts__0__POS EQU 0 +UART_Bridge_BUART_sTX_TxSts__1__MASK EQU 0x02 +UART_Bridge_BUART_sTX_TxSts__1__POS EQU 1 +UART_Bridge_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +UART_Bridge_BUART_sTX_TxSts__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST +UART_Bridge_BUART_sTX_TxSts__2__MASK EQU 0x04 +UART_Bridge_BUART_sTX_TxSts__2__POS EQU 2 +UART_Bridge_BUART_sTX_TxSts__3__MASK EQU 0x08 +UART_Bridge_BUART_sTX_TxSts__3__POS EQU 3 +UART_Bridge_BUART_sTX_TxSts__MASK EQU 0x0F +UART_Bridge_BUART_sTX_TxSts__MASK_REG EQU CYREG_B0_UDB12_MSK +UART_Bridge_BUART_sTX_TxSts__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +UART_Bridge_BUART_sTX_TxSts__STATUS_REG EQU CYREG_B0_UDB12_ST +UART_Bridge_RXInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +UART_Bridge_RXInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +UART_Bridge_RXInternalInterrupt__INTC_MASK EQU 0x04 +UART_Bridge_RXInternalInterrupt__INTC_NUMBER EQU 2 +UART_Bridge_RXInternalInterrupt__INTC_PRIOR_NUM EQU 4 +UART_Bridge_RXInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +UART_Bridge_RXInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +UART_Bridge_RXInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +UART_Bridge_TXInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +UART_Bridge_TXInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +UART_Bridge_TXInternalInterrupt__INTC_MASK EQU 0x08 +UART_Bridge_TXInternalInterrupt__INTC_NUMBER EQU 3 +UART_Bridge_TXInternalInterrupt__INTC_PRIOR_NUM EQU 4 +UART_Bridge_TXInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +UART_Bridge_TXInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +UART_Bridge_TXInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; Timer_CSTick +Timer_CSTick_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 +Timer_CSTick_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 +Timer_CSTick_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 +Timer_CSTick_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 +Timer_CSTick_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 +Timer_CSTick_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 +Timer_CSTick_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 +Timer_CSTick_TimerHW__PER0 EQU CYREG_TMR0_PER0 +Timer_CSTick_TimerHW__PER1 EQU CYREG_TMR0_PER1 +Timer_CSTick_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 +Timer_CSTick_TimerHW__PM_ACT_MSK EQU 0x01 +Timer_CSTick_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 +Timer_CSTick_TimerHW__PM_STBY_MSK EQU 0x01 +Timer_CSTick_TimerHW__RT0 EQU CYREG_TMR0_RT0 +Timer_CSTick_TimerHW__RT1 EQU CYREG_TMR0_RT1 +Timer_CSTick_TimerHW__SR0 EQU CYREG_TMR0_SR0 + +; LedControlReg +LedControlReg_Sync_ctrl_reg__0__MASK EQU 0x01 +LedControlReg_Sync_ctrl_reg__0__POS EQU 0 +LedControlReg_Sync_ctrl_reg__1__MASK EQU 0x02 +LedControlReg_Sync_ctrl_reg__1__POS EQU 1 +LedControlReg_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +LedControlReg_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +LedControlReg_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +LedControlReg_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +LedControlReg_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +LedControlReg_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK +LedControlReg_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +LedControlReg_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK +LedControlReg_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +LedControlReg_Sync_ctrl_reg__2__MASK EQU 0x04 +LedControlReg_Sync_ctrl_reg__2__POS EQU 2 +LedControlReg_Sync_ctrl_reg__3__MASK EQU 0x08 +LedControlReg_Sync_ctrl_reg__3__POS EQU 3 +LedControlReg_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +LedControlReg_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL +LedControlReg_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL +LedControlReg_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL +LedControlReg_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL +LedControlReg_Sync_ctrl_reg__MASK EQU 0x0F +LedControlReg_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +LedControlReg_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +LedControlReg_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK + +; Pin_BLE_Extra +Pin_BLE_Extra__0__INTTYPE EQU CYREG_PICU15_INTTYPE4 +Pin_BLE_Extra__0__MASK EQU 0x10 +Pin_BLE_Extra__0__PC EQU CYREG_IO_PC_PRT15_PC4 +Pin_BLE_Extra__0__PORT EQU 15 +Pin_BLE_Extra__0__SHIFT EQU 4 +Pin_BLE_Extra__AG EQU CYREG_PRT15_AG +Pin_BLE_Extra__AMUX EQU CYREG_PRT15_AMUX +Pin_BLE_Extra__BIE EQU CYREG_PRT15_BIE +Pin_BLE_Extra__BIT_MASK EQU CYREG_PRT15_BIT_MASK +Pin_BLE_Extra__BYP EQU CYREG_PRT15_BYP +Pin_BLE_Extra__CTL EQU CYREG_PRT15_CTL +Pin_BLE_Extra__DM0 EQU CYREG_PRT15_DM0 +Pin_BLE_Extra__DM1 EQU CYREG_PRT15_DM1 +Pin_BLE_Extra__DM2 EQU CYREG_PRT15_DM2 +Pin_BLE_Extra__DR EQU CYREG_PRT15_DR +Pin_BLE_Extra__INP_DIS EQU CYREG_PRT15_INP_DIS +Pin_BLE_Extra__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +Pin_BLE_Extra__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +Pin_BLE_Extra__LCD_EN EQU CYREG_PRT15_LCD_EN +Pin_BLE_Extra__MASK EQU 0x10 +Pin_BLE_Extra__PORT EQU 15 +Pin_BLE_Extra__PRT EQU CYREG_PRT15_PRT +Pin_BLE_Extra__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +Pin_BLE_Extra__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +Pin_BLE_Extra__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +Pin_BLE_Extra__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +Pin_BLE_Extra__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +Pin_BLE_Extra__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +Pin_BLE_Extra__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +Pin_BLE_Extra__PS EQU CYREG_PRT15_PS +Pin_BLE_Extra__SHIFT EQU 4 +Pin_BLE_Extra__SLW EQU CYREG_PRT15_SLW + +; Pin_VoltageEn +Pin_VoltageEn__0__INTTYPE EQU CYREG_PICU2_INTTYPE7 +Pin_VoltageEn__0__MASK EQU 0x80 +Pin_VoltageEn__0__PC EQU CYREG_PRT2_PC7 +Pin_VoltageEn__0__PORT EQU 2 +Pin_VoltageEn__0__SHIFT EQU 7 +Pin_VoltageEn__AG EQU CYREG_PRT2_AG +Pin_VoltageEn__AMUX EQU CYREG_PRT2_AMUX +Pin_VoltageEn__BIE EQU CYREG_PRT2_BIE +Pin_VoltageEn__BIT_MASK EQU CYREG_PRT2_BIT_MASK +Pin_VoltageEn__BYP EQU CYREG_PRT2_BYP +Pin_VoltageEn__CTL EQU CYREG_PRT2_CTL +Pin_VoltageEn__DM0 EQU CYREG_PRT2_DM0 +Pin_VoltageEn__DM1 EQU CYREG_PRT2_DM1 +Pin_VoltageEn__DM2 EQU CYREG_PRT2_DM2 +Pin_VoltageEn__DR EQU CYREG_PRT2_DR +Pin_VoltageEn__INP_DIS EQU CYREG_PRT2_INP_DIS +Pin_VoltageEn__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU2_BASE +Pin_VoltageEn__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +Pin_VoltageEn__LCD_EN EQU CYREG_PRT2_LCD_EN +Pin_VoltageEn__MASK EQU 0x80 +Pin_VoltageEn__PORT EQU 2 +Pin_VoltageEn__PRT EQU CYREG_PRT2_PRT +Pin_VoltageEn__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +Pin_VoltageEn__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +Pin_VoltageEn__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +Pin_VoltageEn__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +Pin_VoltageEn__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +Pin_VoltageEn__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +Pin_VoltageEn__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +Pin_VoltageEn__PS EQU CYREG_PRT2_PS +Pin_VoltageEn__SHIFT EQU 7 +Pin_VoltageEn__SLW EQU CYREG_PRT2_SLW + +; KitProg_Button +KitProg_Button__0__INTTYPE EQU CYREG_PICU1_INTTYPE2 +KitProg_Button__0__MASK EQU 0x04 +KitProg_Button__0__PC EQU CYREG_PRT1_PC2 +KitProg_Button__0__PORT EQU 1 +KitProg_Button__0__SHIFT EQU 2 +KitProg_Button__AG EQU CYREG_PRT1_AG +KitProg_Button__AMUX EQU CYREG_PRT1_AMUX +KitProg_Button__BIE EQU CYREG_PRT1_BIE +KitProg_Button__BIT_MASK EQU CYREG_PRT1_BIT_MASK +KitProg_Button__BYP EQU CYREG_PRT1_BYP +KitProg_Button__CTL EQU CYREG_PRT1_CTL +KitProg_Button__DM0 EQU CYREG_PRT1_DM0 +KitProg_Button__DM1 EQU CYREG_PRT1_DM1 +KitProg_Button__DM2 EQU CYREG_PRT1_DM2 +KitProg_Button__DR EQU CYREG_PRT1_DR +KitProg_Button__INP_DIS EQU CYREG_PRT1_INP_DIS +KitProg_Button__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU1_BASE +KitProg_Button__LCD_COM_SEG EQU CYREG_PRT1_LCD_COM_SEG +KitProg_Button__LCD_EN EQU CYREG_PRT1_LCD_EN +KitProg_Button__MASK EQU 0x04 +KitProg_Button__PORT EQU 1 +KitProg_Button__PRT EQU CYREG_PRT1_PRT +KitProg_Button__PRTDSI__CAPS_SEL EQU CYREG_PRT1_CAPS_SEL +KitProg_Button__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT1_DBL_SYNC_IN +KitProg_Button__PRTDSI__OE_SEL0 EQU CYREG_PRT1_OE_SEL0 +KitProg_Button__PRTDSI__OE_SEL1 EQU CYREG_PRT1_OE_SEL1 +KitProg_Button__PRTDSI__OUT_SEL0 EQU CYREG_PRT1_OUT_SEL0 +KitProg_Button__PRTDSI__OUT_SEL1 EQU CYREG_PRT1_OUT_SEL1 +KitProg_Button__PRTDSI__SYNC_OUT EQU CYREG_PRT1_SYNC_OUT +KitProg_Button__PS EQU CYREG_PRT1_PS +KitProg_Button__SHIFT EQU 2 +KitProg_Button__SLW EQU CYREG_PRT1_SLW + +; Pin_HWVersionA +Pin_HWVersionA__0__INTTYPE EQU CYREG_PICU2_INTTYPE0 +Pin_HWVersionA__0__MASK EQU 0x01 +Pin_HWVersionA__0__PC EQU CYREG_PRT2_PC0 +Pin_HWVersionA__0__PORT EQU 2 +Pin_HWVersionA__0__SHIFT EQU 0 +Pin_HWVersionA__AG EQU CYREG_PRT2_AG +Pin_HWVersionA__AMUX EQU CYREG_PRT2_AMUX +Pin_HWVersionA__BIE EQU CYREG_PRT2_BIE +Pin_HWVersionA__BIT_MASK EQU CYREG_PRT2_BIT_MASK +Pin_HWVersionA__BYP EQU CYREG_PRT2_BYP +Pin_HWVersionA__CTL EQU CYREG_PRT2_CTL +Pin_HWVersionA__DM0 EQU CYREG_PRT2_DM0 +Pin_HWVersionA__DM1 EQU CYREG_PRT2_DM1 +Pin_HWVersionA__DM2 EQU CYREG_PRT2_DM2 +Pin_HWVersionA__DR EQU CYREG_PRT2_DR +Pin_HWVersionA__INP_DIS EQU CYREG_PRT2_INP_DIS +Pin_HWVersionA__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU2_BASE +Pin_HWVersionA__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +Pin_HWVersionA__LCD_EN EQU CYREG_PRT2_LCD_EN +Pin_HWVersionA__MASK EQU 0x01 +Pin_HWVersionA__PORT EQU 2 +Pin_HWVersionA__PRT EQU CYREG_PRT2_PRT +Pin_HWVersionA__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +Pin_HWVersionA__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +Pin_HWVersionA__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +Pin_HWVersionA__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +Pin_HWVersionA__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +Pin_HWVersionA__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +Pin_HWVersionA__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +Pin_HWVersionA__PS EQU CYREG_PRT2_PS +Pin_HWVersionA__SHIFT EQU 0 +Pin_HWVersionA__SLW EQU CYREG_PRT2_SLW + +; Pin_HWVersionB +Pin_HWVersionB__0__INTTYPE EQU CYREG_PICU2_INTTYPE1 +Pin_HWVersionB__0__MASK EQU 0x02 +Pin_HWVersionB__0__PC EQU CYREG_PRT2_PC1 +Pin_HWVersionB__0__PORT EQU 2 +Pin_HWVersionB__0__SHIFT EQU 1 +Pin_HWVersionB__AG EQU CYREG_PRT2_AG +Pin_HWVersionB__AMUX EQU CYREG_PRT2_AMUX +Pin_HWVersionB__BIE EQU CYREG_PRT2_BIE +Pin_HWVersionB__BIT_MASK EQU CYREG_PRT2_BIT_MASK +Pin_HWVersionB__BYP EQU CYREG_PRT2_BYP +Pin_HWVersionB__CTL EQU CYREG_PRT2_CTL +Pin_HWVersionB__DM0 EQU CYREG_PRT2_DM0 +Pin_HWVersionB__DM1 EQU CYREG_PRT2_DM1 +Pin_HWVersionB__DM2 EQU CYREG_PRT2_DM2 +Pin_HWVersionB__DR EQU CYREG_PRT2_DR +Pin_HWVersionB__INP_DIS EQU CYREG_PRT2_INP_DIS +Pin_HWVersionB__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU2_BASE +Pin_HWVersionB__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +Pin_HWVersionB__LCD_EN EQU CYREG_PRT2_LCD_EN +Pin_HWVersionB__MASK EQU 0x02 +Pin_HWVersionB__PORT EQU 2 +Pin_HWVersionB__PRT EQU CYREG_PRT2_PRT +Pin_HWVersionB__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +Pin_HWVersionB__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +Pin_HWVersionB__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +Pin_HWVersionB__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +Pin_HWVersionB__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +Pin_HWVersionB__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +Pin_HWVersionB__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +Pin_HWVersionB__PS EQU CYREG_PRT2_PS +Pin_HWVersionB__SHIFT EQU 1 +Pin_HWVersionB__SLW EQU CYREG_PRT2_SLW + +; Pin_HWVersionC +Pin_HWVersionC__0__INTTYPE EQU CYREG_PICU2_INTTYPE2 +Pin_HWVersionC__0__MASK EQU 0x04 +Pin_HWVersionC__0__PC EQU CYREG_PRT2_PC2 +Pin_HWVersionC__0__PORT EQU 2 +Pin_HWVersionC__0__SHIFT EQU 2 +Pin_HWVersionC__AG EQU CYREG_PRT2_AG +Pin_HWVersionC__AMUX EQU CYREG_PRT2_AMUX +Pin_HWVersionC__BIE EQU CYREG_PRT2_BIE +Pin_HWVersionC__BIT_MASK EQU CYREG_PRT2_BIT_MASK +Pin_HWVersionC__BYP EQU CYREG_PRT2_BYP +Pin_HWVersionC__CTL EQU CYREG_PRT2_CTL +Pin_HWVersionC__DM0 EQU CYREG_PRT2_DM0 +Pin_HWVersionC__DM1 EQU CYREG_PRT2_DM1 +Pin_HWVersionC__DM2 EQU CYREG_PRT2_DM2 +Pin_HWVersionC__DR EQU CYREG_PRT2_DR +Pin_HWVersionC__INP_DIS EQU CYREG_PRT2_INP_DIS +Pin_HWVersionC__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU2_BASE +Pin_HWVersionC__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +Pin_HWVersionC__LCD_EN EQU CYREG_PRT2_LCD_EN +Pin_HWVersionC__MASK EQU 0x04 +Pin_HWVersionC__PORT EQU 2 +Pin_HWVersionC__PRT EQU CYREG_PRT2_PRT +Pin_HWVersionC__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +Pin_HWVersionC__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +Pin_HWVersionC__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +Pin_HWVersionC__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +Pin_HWVersionC__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +Pin_HWVersionC__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +Pin_HWVersionC__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +Pin_HWVersionC__PS EQU CYREG_PRT2_PS +Pin_HWVersionC__SHIFT EQU 2 +Pin_HWVersionC__SLW EQU CYREG_PRT2_SLW + +; Pin_HWVersionD +Pin_HWVersionD__0__INTTYPE EQU CYREG_PICU2_INTTYPE3 +Pin_HWVersionD__0__MASK EQU 0x08 +Pin_HWVersionD__0__PC EQU CYREG_PRT2_PC3 +Pin_HWVersionD__0__PORT EQU 2 +Pin_HWVersionD__0__SHIFT EQU 3 +Pin_HWVersionD__AG EQU CYREG_PRT2_AG +Pin_HWVersionD__AMUX EQU CYREG_PRT2_AMUX +Pin_HWVersionD__BIE EQU CYREG_PRT2_BIE +Pin_HWVersionD__BIT_MASK EQU CYREG_PRT2_BIT_MASK +Pin_HWVersionD__BYP EQU CYREG_PRT2_BYP +Pin_HWVersionD__CTL EQU CYREG_PRT2_CTL +Pin_HWVersionD__DM0 EQU CYREG_PRT2_DM0 +Pin_HWVersionD__DM1 EQU CYREG_PRT2_DM1 +Pin_HWVersionD__DM2 EQU CYREG_PRT2_DM2 +Pin_HWVersionD__DR EQU CYREG_PRT2_DR +Pin_HWVersionD__INP_DIS EQU CYREG_PRT2_INP_DIS +Pin_HWVersionD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU2_BASE +Pin_HWVersionD__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +Pin_HWVersionD__LCD_EN EQU CYREG_PRT2_LCD_EN +Pin_HWVersionD__MASK EQU 0x08 +Pin_HWVersionD__PORT EQU 2 +Pin_HWVersionD__PRT EQU CYREG_PRT2_PRT +Pin_HWVersionD__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +Pin_HWVersionD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +Pin_HWVersionD__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +Pin_HWVersionD__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +Pin_HWVersionD__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +Pin_HWVersionD__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +Pin_HWVersionD__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +Pin_HWVersionD__PS EQU CYREG_PRT2_PS +Pin_HWVersionD__SHIFT EQU 3 +Pin_HWVersionD__SLW EQU CYREG_PRT2_SLW + +; Pin_HWVersionE +Pin_HWVersionE__0__INTTYPE EQU CYREG_PICU2_INTTYPE4 +Pin_HWVersionE__0__MASK EQU 0x10 +Pin_HWVersionE__0__PC EQU CYREG_PRT2_PC4 +Pin_HWVersionE__0__PORT EQU 2 +Pin_HWVersionE__0__SHIFT EQU 4 +Pin_HWVersionE__AG EQU CYREG_PRT2_AG +Pin_HWVersionE__AMUX EQU CYREG_PRT2_AMUX +Pin_HWVersionE__BIE EQU CYREG_PRT2_BIE +Pin_HWVersionE__BIT_MASK EQU CYREG_PRT2_BIT_MASK +Pin_HWVersionE__BYP EQU CYREG_PRT2_BYP +Pin_HWVersionE__CTL EQU CYREG_PRT2_CTL +Pin_HWVersionE__DM0 EQU CYREG_PRT2_DM0 +Pin_HWVersionE__DM1 EQU CYREG_PRT2_DM1 +Pin_HWVersionE__DM2 EQU CYREG_PRT2_DM2 +Pin_HWVersionE__DR EQU CYREG_PRT2_DR +Pin_HWVersionE__INP_DIS EQU CYREG_PRT2_INP_DIS +Pin_HWVersionE__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU2_BASE +Pin_HWVersionE__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +Pin_HWVersionE__LCD_EN EQU CYREG_PRT2_LCD_EN +Pin_HWVersionE__MASK EQU 0x10 +Pin_HWVersionE__PORT EQU 2 +Pin_HWVersionE__PRT EQU CYREG_PRT2_PRT +Pin_HWVersionE__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +Pin_HWVersionE__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +Pin_HWVersionE__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +Pin_HWVersionE__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +Pin_HWVersionE__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +Pin_HWVersionE__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +Pin_HWVersionE__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +Pin_HWVersionE__PS EQU CYREG_PRT2_PS +Pin_HWVersionE__SHIFT EQU 4 +Pin_HWVersionE__SLW EQU CYREG_PRT2_SLW + +; isr_UsbSuspend +isr_UsbSuspend__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +isr_UsbSuspend__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +isr_UsbSuspend__INTC_MASK EQU 0x40000 +isr_UsbSuspend__INTC_NUMBER EQU 18 +isr_UsbSuspend__INTC_PRIOR_NUM EQU 7 +isr_UsbSuspend__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_18 +isr_UsbSuspend__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +isr_UsbSuspend__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; isr_UsbTimeout +isr_UsbTimeout__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +isr_UsbTimeout__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +isr_UsbTimeout__INTC_MASK EQU 0x80000 +isr_UsbTimeout__INTC_NUMBER EQU 19 +isr_UsbTimeout__INTC_PRIOR_NUM EQU 7 +isr_UsbTimeout__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_19 +isr_UsbTimeout__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +isr_UsbTimeout__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; Control_Flow_En +Control_Flow_En_Sync_ctrl_reg__0__MASK EQU 0x01 +Control_Flow_En_Sync_ctrl_reg__0__POS EQU 0 +Control_Flow_En_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +Control_Flow_En_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +Control_Flow_En_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +Control_Flow_En_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +Control_Flow_En_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +Control_Flow_En_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK +Control_Flow_En_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +Control_Flow_En_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK +Control_Flow_En_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +Control_Flow_En_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +Control_Flow_En_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL +Control_Flow_En_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL +Control_Flow_En_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL +Control_Flow_En_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL +Control_Flow_En_Sync_ctrl_reg__MASK EQU 0x01 +Control_Flow_En_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +Control_Flow_En_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +Control_Flow_En_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK + +; Clock_UsbSuspend +Clock_UsbSuspend__CFG0 EQU CYREG_CLKDIST_DCFG4_CFG0 +Clock_UsbSuspend__CFG1 EQU CYREG_CLKDIST_DCFG4_CFG1 +Clock_UsbSuspend__CFG2 EQU CYREG_CLKDIST_DCFG4_CFG2 +Clock_UsbSuspend__CFG2_SRC_SEL_MASK EQU 0x07 +Clock_UsbSuspend__INDEX EQU 0x04 +Clock_UsbSuspend__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +Clock_UsbSuspend__PM_ACT_MSK EQU 0x10 +Clock_UsbSuspend__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +Clock_UsbSuspend__PM_STBY_MSK EQU 0x10 + +; Timer_UsbSuspend +Timer_UsbSuspend_Reset_Sync_ctrl_reg__0__MASK EQU 0x01 +Timer_UsbSuspend_Reset_Sync_ctrl_reg__0__POS EQU 0 +Timer_UsbSuspend_Reset_Sync_ctrl_reg__1__MASK EQU 0x02 +Timer_UsbSuspend_Reset_Sync_ctrl_reg__1__POS EQU 1 +Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK +Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK +Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +Timer_UsbSuspend_Reset_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +Timer_UsbSuspend_Reset_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL +Timer_UsbSuspend_Reset_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL +Timer_UsbSuspend_Reset_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL +Timer_UsbSuspend_Reset_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL +Timer_UsbSuspend_Reset_Sync_ctrl_reg__MASK EQU 0x03 +Timer_UsbSuspend_Reset_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +Timer_UsbSuspend_Reset_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +Timer_UsbSuspend_Reset_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK +Timer_UsbSuspend_TimerHW__CAP0 EQU CYREG_TMR1_CAP0 +Timer_UsbSuspend_TimerHW__CAP1 EQU CYREG_TMR1_CAP1 +Timer_UsbSuspend_TimerHW__CFG0 EQU CYREG_TMR1_CFG0 +Timer_UsbSuspend_TimerHW__CFG1 EQU CYREG_TMR1_CFG1 +Timer_UsbSuspend_TimerHW__CFG2 EQU CYREG_TMR1_CFG2 +Timer_UsbSuspend_TimerHW__CNT_CMP0 EQU CYREG_TMR1_CNT_CMP0 +Timer_UsbSuspend_TimerHW__CNT_CMP1 EQU CYREG_TMR1_CNT_CMP1 +Timer_UsbSuspend_TimerHW__PER0 EQU CYREG_TMR1_PER0 +Timer_UsbSuspend_TimerHW__PER1 EQU CYREG_TMR1_PER1 +Timer_UsbSuspend_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 +Timer_UsbSuspend_TimerHW__PM_ACT_MSK EQU 0x02 +Timer_UsbSuspend_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 +Timer_UsbSuspend_TimerHW__PM_STBY_MSK EQU 0x02 +Timer_UsbSuspend_TimerHW__RT0 EQU CYREG_TMR1_RT0 +Timer_UsbSuspend_TimerHW__RT1 EQU CYREG_TMR1_RT1 +Timer_UsbSuspend_TimerHW__SR0 EQU CYREG_TMR1_SR0 + +; Timer_UsbTimeout +Timer_UsbTimeout_TimerHW__CAP0 EQU CYREG_TMR2_CAP0 +Timer_UsbTimeout_TimerHW__CAP1 EQU CYREG_TMR2_CAP1 +Timer_UsbTimeout_TimerHW__CFG0 EQU CYREG_TMR2_CFG0 +Timer_UsbTimeout_TimerHW__CFG1 EQU CYREG_TMR2_CFG1 +Timer_UsbTimeout_TimerHW__CFG2 EQU CYREG_TMR2_CFG2 +Timer_UsbTimeout_TimerHW__CNT_CMP0 EQU CYREG_TMR2_CNT_CMP0 +Timer_UsbTimeout_TimerHW__CNT_CMP1 EQU CYREG_TMR2_CNT_CMP1 +Timer_UsbTimeout_TimerHW__PER0 EQU CYREG_TMR2_PER0 +Timer_UsbTimeout_TimerHW__PER1 EQU CYREG_TMR2_PER1 +Timer_UsbTimeout_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 +Timer_UsbTimeout_TimerHW__PM_ACT_MSK EQU 0x04 +Timer_UsbTimeout_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 +Timer_UsbTimeout_TimerHW__PM_STBY_MSK EQU 0x04 +Timer_UsbTimeout_TimerHW__RT0 EQU CYREG_TMR2_RT0 +Timer_UsbTimeout_TimerHW__RT1 EQU CYREG_TMR2_RT1 +Timer_UsbTimeout_TimerHW__SR0 EQU CYREG_TMR2_SR0 + +; Pin_PullUp_Enable +Pin_PullUp_Enable__0__INTTYPE EQU CYREG_PICU15_INTTYPE0 +Pin_PullUp_Enable__0__MASK EQU 0x01 +Pin_PullUp_Enable__0__PC EQU CYREG_IO_PC_PRT15_PC0 +Pin_PullUp_Enable__0__PORT EQU 15 +Pin_PullUp_Enable__0__SHIFT EQU 0 +Pin_PullUp_Enable__AG EQU CYREG_PRT15_AG +Pin_PullUp_Enable__AMUX EQU CYREG_PRT15_AMUX +Pin_PullUp_Enable__BIE EQU CYREG_PRT15_BIE +Pin_PullUp_Enable__BIT_MASK EQU CYREG_PRT15_BIT_MASK +Pin_PullUp_Enable__BYP EQU CYREG_PRT15_BYP +Pin_PullUp_Enable__CTL EQU CYREG_PRT15_CTL +Pin_PullUp_Enable__DM0 EQU CYREG_PRT15_DM0 +Pin_PullUp_Enable__DM1 EQU CYREG_PRT15_DM1 +Pin_PullUp_Enable__DM2 EQU CYREG_PRT15_DM2 +Pin_PullUp_Enable__DR EQU CYREG_PRT15_DR +Pin_PullUp_Enable__INP_DIS EQU CYREG_PRT15_INP_DIS +Pin_PullUp_Enable__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +Pin_PullUp_Enable__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +Pin_PullUp_Enable__LCD_EN EQU CYREG_PRT15_LCD_EN +Pin_PullUp_Enable__MASK EQU 0x01 +Pin_PullUp_Enable__PORT EQU 15 +Pin_PullUp_Enable__PRT EQU CYREG_PRT15_PRT +Pin_PullUp_Enable__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +Pin_PullUp_Enable__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +Pin_PullUp_Enable__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +Pin_PullUp_Enable__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +Pin_PullUp_Enable__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +Pin_PullUp_Enable__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +Pin_PullUp_Enable__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +Pin_PullUp_Enable__PS EQU CYREG_PRT15_PS +Pin_PullUp_Enable__SHIFT EQU 0 +Pin_PullUp_Enable__SLW EQU CYREG_PRT15_SLW + +; Miscellaneous +BCLK__BUS_CLK__HZ EQU 64000000 +BCLK__BUS_CLK__KHZ EQU 64000 +BCLK__BUS_CLK__MHZ EQU 64 +CYDEV_CHIP_DIE_LEOPARD EQU 1 +CYDEV_CHIP_DIE_PSOC4A EQU 18 +CYDEV_CHIP_DIE_PSOC5LP EQU 2 +CYDEV_CHIP_DIE_PSOC5TM EQU 3 +CYDEV_CHIP_DIE_TMA4 EQU 4 +CYDEV_CHIP_DIE_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_FM0P EQU 5 +CYDEV_CHIP_FAMILY_FM3 EQU 6 +CYDEV_CHIP_FAMILY_FM4 EQU 7 +CYDEV_CHIP_FAMILY_PSOC3 EQU 1 +CYDEV_CHIP_FAMILY_PSOC4 EQU 2 +CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_FAMILY_PSOC6 EQU 4 +CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 +CYDEV_CHIP_JTAG_ID EQU 0x2E127069 +CYDEV_CHIP_MEMBER_3A EQU 1 +CYDEV_CHIP_MEMBER_4A EQU 18 +CYDEV_CHIP_MEMBER_4D EQU 13 +CYDEV_CHIP_MEMBER_4E EQU 6 +CYDEV_CHIP_MEMBER_4F EQU 19 +CYDEV_CHIP_MEMBER_4G EQU 4 +CYDEV_CHIP_MEMBER_4H EQU 17 +CYDEV_CHIP_MEMBER_4I EQU 23 +CYDEV_CHIP_MEMBER_4J EQU 14 +CYDEV_CHIP_MEMBER_4K EQU 15 +CYDEV_CHIP_MEMBER_4L EQU 22 +CYDEV_CHIP_MEMBER_4M EQU 21 +CYDEV_CHIP_MEMBER_4N EQU 10 +CYDEV_CHIP_MEMBER_4O EQU 7 +CYDEV_CHIP_MEMBER_4P EQU 20 +CYDEV_CHIP_MEMBER_4Q EQU 12 +CYDEV_CHIP_MEMBER_4R EQU 8 +CYDEV_CHIP_MEMBER_4S EQU 11 +CYDEV_CHIP_MEMBER_4T EQU 9 +CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_4V EQU 16 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_5B EQU 2 +CYDEV_CHIP_MEMBER_6A EQU 24 +CYDEV_CHIP_MEMBER_FM3 EQU 28 +CYDEV_CHIP_MEMBER_FM4 EQU 29 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 +CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 +CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B +CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED +CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT +CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 +CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 +CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 +CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 +CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 +CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 +CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1 +CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1 +CYDEV_CHIP_REV_TMA4_ES EQU 17 +CYDEV_CHIP_REV_TMA4_ES2 EQU 33 +CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_3A_ES1 EQU 0 +CYDEV_CHIP_REVISION_3A_ES2 EQU 1 +CYDEV_CHIP_REVISION_3A_ES3 EQU 3 +CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 +CYDEV_CHIP_REVISION_4A_ES0 EQU 17 +CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 +CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0 +CYDEV_CHIP_REVISION_4G_ES EQU 17 +CYDEV_CHIP_REVISION_4G_ES2 EQU 33 +CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_5A_ES0 EQU 0 +CYDEV_CHIP_REVISION_5A_ES1 EQU 1 +CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 +CYDEV_CHIP_REVISION_5B_ES0 EQU 0 +CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_ES EQU 17 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33 +CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION +CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED +CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1 +CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 +CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1 +CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2 +CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_Disallowed +CYDEV_CONFIGURATION_COMPRESSED EQU 1 +CYDEV_CONFIGURATION_DMA EQU 0 +CYDEV_CONFIGURATION_ECC EQU 0 +CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED +CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0 +CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED +CYDEV_CONFIGURATION_MODE_DMA EQU 2 +CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1 +CYDEV_DEBUG_ENABLE_MASK EQU 0x20 +CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG +CYDEV_DEBUGGING_DPS_Disable EQU 3 +CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_Disable +CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1 +CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0 +CYDEV_DEBUGGING_DPS_SWD EQU 2 +CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6 +CYDEV_DEBUGGING_ENABLE EQU 1 +CYDEV_DEBUGGING_XRES EQU 0 +CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 +CYDEV_ECC_ENABLE EQU 0 +CYDEV_HEAP_SIZE EQU 0x1000 +CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 +CYDEV_INTR_RISING EQU 0x0000800F +CYDEV_IS_EXPORTING_CODE EQU 0 +CYDEV_IS_IMPORTING_CODE EQU 0 +CYDEV_PROJ_TYPE EQU 2 +CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 +CYDEV_PROJ_TYPE_LAUNCHER EQU 5 +CYDEV_PROJ_TYPE_LOADABLE EQU 2 +CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4 +CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3 +CYDEV_PROJ_TYPE_STANDARD EQU 0 +CYDEV_PROTECTION_ENABLE EQU 0 +CYDEV_STACK_SIZE EQU 0x4000 +CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1 +CYDEV_USE_BUNDLED_CMSIS EQU 1 +CYDEV_VARIABLE_VDDA EQU 0 +CYDEV_VDDA_MV EQU 5000 +CYDEV_VDDD_MV EQU 5000 +CYDEV_VDDIO0_MV EQU 5000 +CYDEV_VDDIO1_MV EQU 5000 +CYDEV_VDDIO2_MV EQU 5000 +CYDEV_VDDIO3_MV EQU 5000 +CYDEV_VIO0_MV EQU 5000 +CYDEV_VIO1_MV EQU 5000 +CYDEV_VIO2_MV EQU 5000 +CYDEV_VIO3_MV EQU 5000 +CYIPBLOCK_ARM_CM3_VERSION EQU 0 +CYIPBLOCK_P3_ANAIF_VERSION EQU 0 +CYIPBLOCK_P3_CAN_VERSION EQU 0 +CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0 +CYIPBLOCK_P3_COMP_VERSION EQU 0 +CYIPBLOCK_P3_DECIMATOR_VERSION EQU 0 +CYIPBLOCK_P3_DFB_VERSION EQU 0 +CYIPBLOCK_P3_DMA_VERSION EQU 0 +CYIPBLOCK_P3_DRQ_VERSION EQU 0 +CYIPBLOCK_P3_DSM_VERSION EQU 0 +CYIPBLOCK_P3_EMIF_VERSION EQU 0 +CYIPBLOCK_P3_I2C_VERSION EQU 0 +CYIPBLOCK_P3_LCD_VERSION EQU 0 +CYIPBLOCK_P3_LPF_VERSION EQU 0 +CYIPBLOCK_P3_OPAMP_VERSION EQU 0 +CYIPBLOCK_P3_PM_VERSION EQU 0 +CYIPBLOCK_P3_SCCT_VERSION EQU 0 +CYIPBLOCK_P3_TIMER_VERSION EQU 0 +CYIPBLOCK_P3_USB_VERSION EQU 0 +CYIPBLOCK_P3_VIDAC_VERSION EQU 0 +CYIPBLOCK_P3_VREF_VERSION EQU 0 +CYIPBLOCK_S8_GPIO_VERSION EQU 0 +CYIPBLOCK_S8_IRQ_VERSION EQU 0 +CYIPBLOCK_S8_SAR_VERSION EQU 0 +CYIPBLOCK_S8_SIO_VERSION EQU 0 +CYIPBLOCK_S8_UDB_VERSION EQU 0 +DMA_CHANNELS_USED__MASK0 EQU 0x00000000 +CYDEV_BOOTLOADER_ENABLE EQU 0 + ENDIF + END diff --git a/source/hic_hal/cypress/psoc5lp/armcc/startup_CY8C5LP.s b/source/hic_hal/cypress/psoc5lp/armcc/startup_CY8C5LP.s new file mode 100644 index 0000000000..16298ca81d --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/armcc/startup_CY8C5LP.s @@ -0,0 +1,1647 @@ +;------------------------------------------------------------------------------- +; * @file: startup_CY8C5LP.s +; * @purpose: CMSIS Cortex-M3 Core Device Startup File +; * for the Cypress CY8C5xxxLP +; * @version: V1.01 +;------------------------------------------------------------------------------- +; Copyright (2019) Cypress Semiconductor Corporation +; or a subsidiary of Cypress Semiconductor Corporation. +; +; Licensed under the Apache License, Version 2.0 (the "License"); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +;------------------------------------------------------------------------------- + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000100 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + +; Non-Volatile Configuration +; Flash Protection Data +FP_DATA EQU 0 +; Rows 0..255 +FP_R0 EQU 1 +; Row 0 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 2 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 3 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B0 EQU 0x00 +; Row 4 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 5 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 6 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 7 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B1 EQU 0x00 +; Row 8 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 9 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 10 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 11 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B2 EQU 0x00 +; Row 12 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 13 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 14 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 15 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B3 EQU 0x00 +; Row 16 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 17 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 18 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 19 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B4 EQU 0x00 +; Row 20 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 21 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 22 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 23 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B5 EQU 0x00 +; Row 24 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 25 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 26 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 27 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B6 EQU 0x00 +; Row 28 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 29 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 30 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 31 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B7 EQU 0x00 +; Row 32 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 33 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 34 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 35 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B8 EQU 0x00 +; Row 36 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 37 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 38 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 39 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B9 EQU 0x00 +; Row 40 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 41 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 42 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 43 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B10 EQU 0x00 +; Row 44 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 45 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 46 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 47 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B11 EQU 0x00 +; Row 48 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 49 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 50 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 51 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B12 EQU 0x00 +; Row 52 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 53 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 54 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 55 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B13 EQU 0x00 +; Row 56 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 57 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 58 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 59 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B14 EQU 0x00 +; Row 60 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 61 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 62 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 63 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B15 EQU 0x00 +; Row 64 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 65 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 66 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 67 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B16 EQU 0x00 +; Row 68 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 69 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 70 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 71 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B17 EQU 0x00 +; Row 72 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 73 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 74 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 75 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B18 EQU 0x00 +; Row 76 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 77 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 78 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 79 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B19 EQU 0x00 +; Row 80 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 81 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 82 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 83 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B20 EQU 0x00 +; Row 84 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 85 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 86 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 87 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B21 EQU 0x00 +; Row 88 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 89 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 90 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 91 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B22 EQU 0x00 +; Row 92 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 93 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 94 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 95 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B23 EQU 0x00 +; Row 96 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 97 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 98 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 99 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B24 EQU 0x00 +; Row 100 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 101 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 102 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 103 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B25 EQU 0x00 +; Row 104 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 105 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 106 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 107 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B26 EQU 0x00 +; Row 108 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 109 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 110 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 111 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B27 EQU 0x00 +; Row 112 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 113 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 114 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 115 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B28 EQU 0x00 +; Row 116 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 117 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 118 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 119 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B29 EQU 0x00 +; Row 120 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 121 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 122 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 123 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B30 EQU 0x00 +; Row 124 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 125 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 126 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 127 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B31 EQU 0x00 +; Row 128 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 129 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 130 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 131 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B32 EQU 0x00 +; Row 132 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 133 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 134 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 135 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B33 EQU 0x00 +; Row 136 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 137 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 138 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 139 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B34 EQU 0x00 +; Row 140 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 141 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 142 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 143 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B35 EQU 0x00 +; Row 144 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 145 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 146 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 147 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B36 EQU 0x00 +; Row 148 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 149 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 150 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 151 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B37 EQU 0x00 +; Row 152 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 153 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 154 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 155 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B38 EQU 0x00 +; Row 156 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 157 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 158 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 159 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B39 EQU 0x00 +; Row 160 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 161 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 162 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 163 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B40 EQU 0x00 +; Row 164 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 165 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 166 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 167 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B41 EQU 0x00 +; Row 168 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 169 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 170 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 171 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B42 EQU 0x00 +; Row 172 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 173 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 174 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 175 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B43 EQU 0x00 +; Row 176 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 177 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 178 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 179 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B44 EQU 0x00 +; Row 180 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 181 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 182 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 183 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B45 EQU 0x00 +; Row 184 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 185 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 186 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 187 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B46 EQU 0x00 +; Row 188 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 189 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 190 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 191 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B47 EQU 0x00 +; Row 192 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 193 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 194 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 195 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B48 EQU 0x00 +; Row 196 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 197 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 198 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 199 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B49 EQU 0x00 +; Row 200 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 201 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 202 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 203 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B50 EQU 0x00 +; Row 204 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 205 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 206 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 207 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B51 EQU 0x00 +; Row 208 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 209 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 210 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 211 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B52 EQU 0x00 +; Row 212 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 213 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 214 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 215 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B53 EQU 0x00 +; Row 216 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 217 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 218 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 219 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B54 EQU 0x00 +; Row 220 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 221 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 222 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 223 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B55 EQU 0x00 +; Row 224 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 225 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 226 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 227 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B56 EQU 0x00 +; Row 228 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 229 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 230 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 231 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B57 EQU 0x00 +; Row 232 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 233 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 234 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 235 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B58 EQU 0x00 +; Row 236 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 237 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 238 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 239 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B59 EQU 0x00 +; Row 240 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 241 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 242 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 243 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B60 EQU 0x00 +; Row 244 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 245 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 246 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 247 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B61 EQU 0x00 +; Row 248 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 249 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 250 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 251 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B62 EQU 0x00 +; Row 252 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 253 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 254 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 255 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B63 EQU 0x00 +; +; Rows 256..511 +FP_R1 EQU 1 +; Row 256 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 257 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 258 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 259 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B64 EQU 0x00 +; Row 260 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 261 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 262 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 263 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B65 EQU 0x00 +; Row 264 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 265 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 266 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 267 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B66 EQU 0x00 +; Row 268 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 269 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 270 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 271 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B67 EQU 0x00 +; Row 272 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 273 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 274 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 275 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B68 EQU 0x00 +; Row 276 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 277 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 278 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 279 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B69 EQU 0x00 +; Row 280 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 281 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 282 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 283 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B70 EQU 0x00 +; Row 284 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 285 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 286 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 287 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B71 EQU 0x00 +; Row 288 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 289 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 290 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 291 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B72 EQU 0x00 +; Row 292 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 293 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 294 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 295 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B73 EQU 0x00 +; Row 296 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 297 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 298 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 299 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B74 EQU 0x00 +; Row 300 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 301 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 302 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 303 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B75 EQU 0x00 +; Row 304 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 305 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 306 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 307 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B76 EQU 0x00 +; Row 308 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 309 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 310 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 311 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B77 EQU 0x00 +; Row 312 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 313 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 314 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 315 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B78 EQU 0x00 +; Row 316 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 317 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 318 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 319 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B79 EQU 0x00 +; Row 320 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 321 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 322 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 323 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B80 EQU 0x00 +; Row 324 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 325 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 326 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 327 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B81 EQU 0x00 +; Row 328 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 329 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 330 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 331 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B82 EQU 0x00 +; Row 332 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 333 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 334 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 335 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B83 EQU 0x00 +; Row 336 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 337 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 338 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 339 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B84 EQU 0x00 +; Row 340 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 341 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 342 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 343 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B85 EQU 0x00 +; Row 344 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 345 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 346 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 347 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B86 EQU 0x00 +; Row 348 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 349 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 350 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 351 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B87 EQU 0x00 +; Row 352 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 353 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 354 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 355 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B88 EQU 0x00 +; Row 356 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 357 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 358 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 359 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B89 EQU 0x00 +; Row 360 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 361 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 362 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 363 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B90 EQU 0x00 +; Row 364 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 365 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 366 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 367 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B91 EQU 0x00 +; Row 368 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 369 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 370 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 371 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B92 EQU 0x00 +; Row 372 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 373 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 374 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 375 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B93 EQU 0x00 +; Row 376 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 377 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 378 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 379 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B94 EQU 0x00 +; Row 380 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 381 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 382 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 383 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B95 EQU 0x00 +; Row 384 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 385 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 386 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 387 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B96 EQU 0x00 +; Row 388 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 389 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 390 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 391 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B97 EQU 0x00 +; Row 392 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 393 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 394 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 395 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B98 EQU 0x00 +; Row 396 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 397 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 398 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 399 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B99 EQU 0x00 +; Row 400 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 401 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 402 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 403 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B100 EQU 0x00 +; Row 404 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 405 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 406 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 407 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B101 EQU 0x00 +; Row 408 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 409 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 410 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 411 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B102 EQU 0x00 +; Row 412 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 413 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 414 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 415 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B103 EQU 0x00 +; Row 416 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 417 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 418 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 419 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B104 EQU 0x00 +; Row 420 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 421 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 422 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 423 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B105 EQU 0x00 +; Row 424 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 425 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 426 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 427 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B106 EQU 0x00 +; Row 428 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 429 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 430 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 431 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B107 EQU 0x00 +; Row 432 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 433 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 434 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 435 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B108 EQU 0x00 +; Row 436 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 437 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 438 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 439 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B109 EQU 0x00 +; Row 440 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 441 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 442 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 443 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B110 EQU 0x00 +; Row 444 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 445 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 446 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 447 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B111 EQU 0x00 +; Row 448 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 449 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 450 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 451 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B112 EQU 0x00 +; Row 452 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 453 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 454 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 455 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B113 EQU 0x00 +; Row 456 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 457 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 458 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 459 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B114 EQU 0x00 +; Row 460 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 461 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 462 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 463 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B115 EQU 0x00 +; Row 464 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 465 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 466 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 467 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B116 EQU 0x00 +; Row 468 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 469 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 470 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 471 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B117 EQU 0x00 +; Row 472 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 473 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 474 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 475 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B118 EQU 0x00 +; Row 476 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 477 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 478 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 479 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B119 EQU 0x00 +; Row 480 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 481 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 482 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 483 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B120 EQU 0x00 +; Row 484 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 485 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 486 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 487 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B121 EQU 0x00 +; Row 488 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 489 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 490 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 491 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B122 EQU 0x00 +; Row 492 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 493 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 494 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 495 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B123 EQU 0x00 +; Row 496 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 497 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 498 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 499 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B124 EQU 0x00 +; Row 500 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 501 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 502 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 503 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B125 EQU 0x00 +; Row 504 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 505 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 506 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 507 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B126 EQU 0x00 +; Row 508 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 509 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 510 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 511 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B127 EQU 0x00 +; +; Rows 512..767 +FP_R2 EQU 1 +; Row 512 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 513 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 514 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 515 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B128 EQU 0x00 +; Row 516 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 517 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 518 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 519 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B129 EQU 0x00 +; Row 520 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 521 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 522 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 523 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B130 EQU 0x00 +; Row 524 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 525 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 526 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 527 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B131 EQU 0x00 +; Row 528 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 529 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 530 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 531 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B132 EQU 0x00 +; Row 532 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 533 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 534 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 535 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B133 EQU 0x00 +; Row 536 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 537 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 538 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 539 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B134 EQU 0x00 +; Row 540 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 541 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 542 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 543 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B135 EQU 0x00 +; Row 544 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 545 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 546 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 547 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B136 EQU 0x00 +; Row 548 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 549 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 550 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 551 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B137 EQU 0x00 +; Row 552 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 553 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 554 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 555 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B138 EQU 0x00 +; Row 556 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 557 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 558 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 559 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B139 EQU 0x00 +; Row 560 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 561 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 562 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 563 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B140 EQU 0x00 +; Row 564 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 565 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 566 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 567 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B141 EQU 0x00 +; Row 568 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 569 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 570 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 571 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B142 EQU 0x00 +; Row 572 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 573 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 574 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 575 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B143 EQU 0x00 +; Row 576 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 577 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 578 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 579 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B144 EQU 0x00 +; Row 580 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 581 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 582 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 583 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B145 EQU 0x00 +; Row 584 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 585 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 586 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 587 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B146 EQU 0x00 +; Row 588 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 589 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 590 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 591 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B147 EQU 0x00 +; Row 592 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 593 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 594 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 595 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B148 EQU 0x00 +; Row 596 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 597 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 598 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 599 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B149 EQU 0x00 +; Row 600 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 601 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 602 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 603 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B150 EQU 0x00 +; Row 604 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 605 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 606 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 607 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B151 EQU 0x00 +; Row 608 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 609 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 610 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 611 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B152 EQU 0x00 +; Row 612 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 613 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 614 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 615 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B153 EQU 0x00 +; Row 616 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 617 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 618 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 619 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B154 EQU 0x00 +; Row 620 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 621 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 622 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 623 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B155 EQU 0x00 +; Row 624 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 625 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 626 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 627 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B156 EQU 0x00 +; Row 628 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 629 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 630 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 631 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B157 EQU 0x00 +; Row 632 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 633 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 634 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 635 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B158 EQU 0x00 +; Row 636 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 637 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 638 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 639 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B159 EQU 0x00 +; Row 640 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 641 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 642 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 643 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B160 EQU 0x00 +; Row 644 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 645 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 646 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 647 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B161 EQU 0x00 +; Row 648 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 649 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 650 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 651 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B162 EQU 0x00 +; Row 652 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 653 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 654 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 655 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B163 EQU 0x00 +; Row 656 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 657 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 658 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 659 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B164 EQU 0x00 +; Row 660 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 661 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 662 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 663 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B165 EQU 0x00 +; Row 664 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 665 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 666 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 667 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B166 EQU 0x00 +; Row 668 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 669 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 670 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 671 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B167 EQU 0x00 +; Row 672 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 673 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 674 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 675 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B168 EQU 0x00 +; Row 676 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 677 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 678 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 679 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B169 EQU 0x00 +; Row 680 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 681 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 682 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 683 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B170 EQU 0x00 +; Row 684 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 685 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 686 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 687 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B171 EQU 0x00 +; Row 688 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 689 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 690 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 691 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B172 EQU 0x00 +; Row 692 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 693 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 694 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 695 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B173 EQU 0x00 +; Row 696 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 697 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 698 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 699 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B174 EQU 0x00 +; Row 700 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 701 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 702 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 703 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B175 EQU 0x00 +; Row 704 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 705 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 706 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 707 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B176 EQU 0x00 +; Row 708 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 709 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 710 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 711 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B177 EQU 0x00 +; Row 712 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 713 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 714 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 715 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B178 EQU 0x00 +; Row 716 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 717 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 718 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 719 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B179 EQU 0x00 +; Row 720 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 721 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 722 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 723 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B180 EQU 0x00 +; Row 724 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 725 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 726 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 727 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B181 EQU 0x00 +; Row 728 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 729 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 730 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 731 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B182 EQU 0x00 +; Row 732 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 733 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 734 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 735 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B183 EQU 0x00 +; Row 736 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 737 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 738 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 739 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B184 EQU 0x00 +; Row 740 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 741 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 742 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 743 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B185 EQU 0x00 +; Row 744 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 745 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 746 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 747 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B186 EQU 0x00 +; Row 748 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 749 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 750 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 751 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B187 EQU 0x00 +; Row 752 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 753 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 754 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 755 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B188 EQU 0x00 +; Row 756 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 757 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 758 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 759 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B189 EQU 0x00 +; Row 760 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 761 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 762 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 763 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B190 EQU 0x00 +; Row 764 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 765 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 766 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 767 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B191 EQU 0x00 +; +; Rows 768..1023 +FP_R3 EQU 1 +; Row 768 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 769 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 770 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 771 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B192 EQU 0x00 +; Row 772 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 773 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 774 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 775 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B193 EQU 0x00 +; Row 776 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 777 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 778 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 779 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B194 EQU 0x00 +; Row 780 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 781 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 782 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 783 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B195 EQU 0x00 +; Row 784 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 785 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 786 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 787 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B196 EQU 0x00 +; Row 788 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 789 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 790 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 791 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B197 EQU 0x00 +; Row 792 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 793 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 794 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 795 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B198 EQU 0x00 +; Row 796 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 797 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 798 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 799 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B199 EQU 0x00 +; Row 800 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 801 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 802 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 803 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B200 EQU 0x00 +; Row 804 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 805 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 806 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 807 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B201 EQU 0x00 +; Row 808 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 809 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 810 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 811 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B202 EQU 0x00 +; Row 812 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 813 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 814 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 815 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B203 EQU 0x00 +; Row 816 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 817 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 818 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 819 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B204 EQU 0x00 +; Row 820 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 821 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 822 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 823 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B205 EQU 0x00 +; Row 824 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 825 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 826 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 827 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B206 EQU 0x00 +; Row 828 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 829 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 830 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 831 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B207 EQU 0x00 +; Row 832 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 833 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 834 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 835 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B208 EQU 0x00 +; Row 836 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 837 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 838 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 839 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B209 EQU 0x00 +; Row 840 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 841 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 842 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 843 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B210 EQU 0x00 +; Row 844 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 845 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 846 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 847 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B211 EQU 0x00 +; Row 848 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 849 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 850 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 851 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B212 EQU 0x00 +; Row 852 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 853 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 854 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 855 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B213 EQU 0x00 +; Row 856 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 857 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 858 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 859 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B214 EQU 0x00 +; Row 860 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 861 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 862 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 863 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B215 EQU 0x00 +; Row 864 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 865 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 866 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 867 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B216 EQU 0x00 +; Row 868 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 869 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 870 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 871 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B217 EQU 0x00 +; Row 872 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 873 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 874 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 875 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B218 EQU 0x00 +; Row 876 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 877 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 878 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 879 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B219 EQU 0x00 +; Row 880 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 881 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 882 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 883 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B220 EQU 0x00 +; Row 884 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 885 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 886 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 887 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B221 EQU 0x00 +; Row 888 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 889 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 890 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 891 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B222 EQU 0x00 +; Row 892 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 893 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 894 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 895 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B223 EQU 0x00 +; Row 896 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 897 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 898 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 899 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B224 EQU 0x00 +; Row 900 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 901 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 902 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 903 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B225 EQU 0x00 +; Row 904 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 905 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 906 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 907 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B226 EQU 0x00 +; Row 908 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 909 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 910 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 911 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B227 EQU 0x00 +; Row 912 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 913 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 914 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 915 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B228 EQU 0x00 +; Row 916 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 917 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 918 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 919 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B229 EQU 0x00 +; Row 920 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 921 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 922 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 923 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B230 EQU 0x00 +; Row 924 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 925 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 926 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 927 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B231 EQU 0x00 +; Row 928 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 929 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 930 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 931 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B232 EQU 0x00 +; Row 932 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 933 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 934 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 935 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B233 EQU 0x00 +; Row 936 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 937 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 938 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 939 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B234 EQU 0x00 +; Row 940 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 941 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 942 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 943 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B235 EQU 0x00 +; Row 944 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 945 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 946 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 947 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B236 EQU 0x00 +; Row 948 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 949 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 950 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 951 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B237 EQU 0x00 +; Row 952 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 953 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 954 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 955 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B238 EQU 0x00 +; Row 956 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 957 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 958 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 959 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B239 EQU 0x00 +; Row 960 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 961 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 962 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 963 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B240 EQU 0x00 +; Row 964 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 965 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 966 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 967 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B241 EQU 0x00 +; Row 968 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 969 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 970 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 971 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B242 EQU 0x00 +; Row 972 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 973 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 974 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 975 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B243 EQU 0x00 +; Row 976 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 977 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 978 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 979 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B244 EQU 0x00 +; Row 980 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 981 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 982 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 983 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B245 EQU 0x00 +; Row 984 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 985 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 986 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 987 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B246 EQU 0x00 +; Row 988 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 989 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 990 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 991 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B247 EQU 0x00 +; Row 992 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 993 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 994 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 995 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B248 EQU 0x00 +; Row 996 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 997 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 998 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 999 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B249 EQU 0x00 +; Row 1000 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1001 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1002 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1003 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B250 EQU 0x00 +; Row 1004 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1005 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1006 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1007 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B251 EQU 0x00 +; Row 1008 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1009 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1010 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1011 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B252 EQU 0x00 +; Row 1012 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1013 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1014 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1015 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B253 EQU 0x00 +; Row 1016 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1017 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1018 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1019 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B254 EQU 0x00 +; Row 1020 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1021 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1022 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +; Row 1023 <0=> Unprotected <1=> Read Protect <2=> Disable External Write <3=> Disable Internal Write +FP_B255 EQU 0x00 +; +; +; Device Configuration Nonvolatile Latch (NVL) +CFG_NVL EQU 0 +; Byte 0 +; PRT0RDM[1:0] <0x0-0x3> +; PRT1RDM[1:0] <0x0-0x3> +; PRT2RDM[1:0] <0x0-0x3> +; PRT3RDM[1:0] <0x0-0x3> +CFG_NVL0 EQU 0x00 +; +; Byte 1 +; PRT4RDM[1:0] <0x0-0x3> +; PRT5RDM[1:0] <0x0-0x3> +; PRT6RDM[1:0] <0x0-0x3> +; PRT12RDM[1:0] <0x0-0x3> +CFG_NVL1 EQU 0x00 +; +; Byte 2 +; PRT15RDM[1:0] <0x0-0x3> +; RESERVED <0x0-0xF> +; DEBUG_EN +; XRESMEN +CFG_NVL2 EQU 0x40 +; +; Byte 3 +; CFGSPEED +; DPS <0=> 5-wire JTAG <1=> 4-wire JTAG <2=> SWD <3=> Debug Ports Disabled +; ECCEN +; DIG_PHS_DLY <0x0-0xF> +CFG_NVL3 EQU 0x05 +; +; +; Write-once Nonvolatile Latch (WO NVL) +; Enables device security +; WARNING: Programming the WO NVL with correct 32-bit key locks the device! +WO_NVL EQU 0 +; Byte 0 <0x0-0xFF> +; Byte 1 <0x0-0xFF> +; Byte 2 <0x0-0xFF> +; Byte 3 <0x0-0xFF> +WO_NVL0 EQU 0x00 +WO_NVL1 EQU 0x00 +WO_NVL2 EQU 0x00 +WO_NVL3 EQU 0x00 +; +; + + IF FP_DATA <> 0 + IF FP_R0 <> 0 + AREA |.ARM.__at_0x90400000|, CODE, READONLY + DCB FP_B0, FP_B1, FP_B2, FP_B3, FP_B4, FP_B5, FP_B6, FP_B7 + DCB FP_B8, FP_B9, FP_B10, FP_B11, FP_B12, FP_B13, FP_B14, FP_B15 + DCB FP_B16, FP_B17, FP_B18, FP_B19, FP_B20, FP_B21, FP_B22, FP_B23 + DCB FP_B24, FP_B25, FP_B26, FP_B27, FP_B28, FP_B29, FP_B30, FP_B31 + DCB FP_B32, FP_B33, FP_B34, FP_B35, FP_B36, FP_B37, FP_B38, FP_B39 + DCB FP_B40, FP_B41, FP_B42, FP_B43, FP_B44, FP_B45, FP_B46, FP_B47 + DCB FP_B48, FP_B49, FP_B50, FP_B51, FP_B52, FP_B53, FP_B54, FP_B55 + DCB FP_B56, FP_B57, FP_B58, FP_B59, FP_B60, FP_B61, FP_B62, FP_B63 + ENDIF + IF FP_R1 <> 0 + AREA |.ARM.__at_0x90400040|, CODE, READONLY + DCB FP_B64, FP_B65, FP_B66, FP_B67, FP_B68, FP_B69, FP_B70, FP_B71 + DCB FP_B72, FP_B73, FP_B74, FP_B75, FP_B76, FP_B77, FP_B78, FP_B79 + DCB FP_B80, FP_B81, FP_B82, FP_B83, FP_B84, FP_B85, FP_B86, FP_B87 + DCB FP_B88, FP_B89, FP_B90, FP_B91, FP_B92, FP_B93, FP_B94, FP_B95 + DCB FP_B96, FP_B97, FP_B98, FP_B99, FP_B100, FP_B101, FP_B102, FP_B103 + DCB FP_B104, FP_B105, FP_B106, FP_B107, FP_B108, FP_B109, FP_B110, FP_B111 + DCB FP_B112, FP_B113, FP_B114, FP_B115, FP_B116, FP_B117, FP_B118, FP_B119 + DCB FP_B120, FP_B121, FP_B122, FP_B123, FP_B124, FP_B125, FP_B126, FP_B127 + ENDIF + IF FP_R2 <> 0 + AREA |.ARM.__at_0x90400080|, CODE, READONLY + DCB FP_B128, FP_B129, FP_B130, FP_B131, FP_B132, FP_B133, FP_B134, FP_B135 + DCB FP_B136, FP_B137, FP_B138, FP_B139, FP_B140, FP_B141, FP_B142, FP_B143 + DCB FP_B144, FP_B145, FP_B146, FP_B147, FP_B148, FP_B149, FP_B150, FP_B151 + DCB FP_B152, FP_B153, FP_B154, FP_B155, FP_B156, FP_B157, FP_B158, FP_B159 + DCB FP_B160, FP_B161, FP_B162, FP_B163, FP_B164, FP_B165, FP_B166, FP_B167 + DCB FP_B168, FP_B169, FP_B170, FP_B171, FP_B172, FP_B173, FP_B174, FP_B175 + DCB FP_B176, FP_B177, FP_B178, FP_B179, FP_B180, FP_B181, FP_B182, FP_B183 + DCB FP_B184, FP_B185, FP_B186, FP_B187, FP_B188, FP_B189, FP_B190, FP_B191 + ENDIF + IF FP_R3 <> 0 + AREA |.ARM.__at_0x904000C0|, CODE, READONLY + DCB FP_B192, FP_B193, FP_B194, FP_B195, FP_B196, FP_B197, FP_B198, FP_B199 + DCB FP_B200, FP_B201, FP_B202, FP_B203, FP_B204, FP_B205, FP_B206, FP_B207 + DCB FP_B208, FP_B209, FP_B210, FP_B211, FP_B212, FP_B213, FP_B214, FP_B215 + DCB FP_B216, FP_B217, FP_B218, FP_B219, FP_B220, FP_B221, FP_B222, FP_B223 + DCB FP_B224, FP_B225, FP_B226, FP_B227, FP_B228, FP_B229, FP_B230, FP_B231 + DCB FP_B232, FP_B233, FP_B234, FP_B235, FP_B236, FP_B237, FP_B238, FP_B239 + DCB FP_B240, FP_B241, FP_B242, FP_B243, FP_B244, FP_B245, FP_B246, FP_B247 + DCB FP_B248, FP_B249, FP_B250, FP_B251, FP_B252, FP_B253, FP_B254, FP_B255 + ENDIF + ENDIF + + IF CFG_NVL <> 0 + AREA |.ARM.__at_0x90000000|, CODE, READONLY + DCB CFG_NVL0, CFG_NVL1, CFG_NVL2, CFG_NVL3 + ENDIF + + IF WO_NVL <> 0 + AREA |.ARM.__at_0x90100000|, CODE, READONLY + DCB WO_NVL0, WO_NVL1, WO_NVL2, WO_NVL3 + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + IMPORT g_board_info +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD DAPLINK_BUILD_KEY ; 8: Build type - BL/IF + DCD DAPLINK_HIC_ID ; 9: Compatibility + DCD DAPLINK_VERSION ; 10:Version + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD g_board_info ; Ptr to Board info, family info other target details + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/source/hic_hal/cypress/psoc5lp/daplink_addr.h b/source/hic_hal/cypress/psoc5lp/daplink_addr.h new file mode 100644 index 0000000000..b12f61d440 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/daplink_addr.h @@ -0,0 +1,89 @@ +/** + * @file daplink_addr.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Copyright 2019, Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +*****************************************************************************/ + +#ifndef DAPLINK_ADDR_H +#define DAPLINK_ADDR_H + +/* Device sizes */ + +#define DAPLINK_ROM_START 0x00021800 +#define DAPLINK_ROM_SIZE 0x0001E600 + +#define DAPLINK_RAM_START 0x1FFF8000 +#define DAPLINK_RAM_SIZE 0x00010000 + + +/* ROM sizes */ + +#define DAPLINK_ROM_BL_START 0x00021800 +#define DAPLINK_ROM_BL_SIZE 0x00000000 + +#define DAPLINK_ROM_CONFIG_ADMIN_START 0x00021800 +#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00000000 + +// For custom app start addr should be 0x00021800 +#define DAPLINK_ROM_IF_START 0x00021800 +#define DAPLINK_ROM_IF_SIZE 0x0001E500 + +#define DAPLINK_ROM_CONFIG_USER_START 0x0003FD00 +#define DAPLINK_ROM_CONFIG_USER_SIZE 0x00000100 + +/* RAM sizes */ + +#define DAPLINK_RAM_APP_START 0x1FFF8000 +#define DAPLINK_RAM_APP_SIZE 0x00010000 + +#define DAPLINK_RAM_SHARED_START 0x20008000 +#define DAPLINK_RAM_SHARED_SIZE 0x00000000 + +/* Flash Programming Info */ + +#define DAPLINK_SECTOR_SIZE 0x00000100 +#define DAPLINK_MIN_WRITE_SIZE 0x00000100 + +/* Current build */ + +#if defined(DAPLINK_BL) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_BL_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_IF_SIZE + +#elif defined(DAPLINK_IF) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_IF_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_BL_SIZE + +#else + +#error "Build must be either bootloader or interface" + +#endif + +#endif diff --git a/source/hic_hal/cypress/psoc5lp/gpio.c b/source/hic_hal/cypress/psoc5lp/gpio.c new file mode 100644 index 0000000000..f5abb2b888 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/gpio.c @@ -0,0 +1,209 @@ +/******************************************************************************* + +* @file gpio.c +* @brief Implementation of GPIO api for the PSoC5LP +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ +#include "gpio.h" +#include "compiler.h" +#include "IO_Config.h" +#include "daplink.h" +#include "cypins.h" +#include "LED_Amber.h" +#include "LED_Green.h" +#include "LED_Red.h" +#include "ApplicationButton.h" +#include "ModeButton.h" +#include "Bootloadable.h" +#include "EEPROM_ModeStorage.h" + + +// This GPIO configuration is only valid for the PSoC5LP +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_PSOC5LP); + +#define APP_SWITCH_TIMEOUT_SINGLE_BTN (2000u/30u) +#define APP_SWITCH_TIMEOUT (100u/30u) + +#define APP_INACTIVE (0u) +#define APP_ACTIVE (1u) + +#define MODE_BULK (0x00u) +#define MODE_HID (0x01u) + +/* Addresses of activity bytes in bootloader metadata */ +#define MD_SIZEOF (64u) +#define ACTIVE_OFFSET (16u) +#define KIT_PROG_ACTIVE_ADDR (CYDEV_FLASH_BASE + (CYDEV_FLASH_SIZE - (0u * CYDEV_FLS_ROW_SIZE) - MD_SIZEOF) + ACTIVE_OFFSET) +#define CUSTOM_APP_ACTIVE_ADDR (CYDEV_FLASH_BASE + (CYDEV_FLASH_SIZE - (1u * CYDEV_FLS_ROW_SIZE) - MD_SIZEOF) + ACTIVE_OFFSET) + +uint32_t app_switch_counter = 0; +uint32_t app_switch_counter_last = 0; + + +/****************************************************************************** +* WriteFlashByte +***************************************************************************//** +* This API writes to flash the specified data. +* +* @param[in] address The address in flash. +* @param[in] inputValue The one-byte data to write +* +******************************************************************************/ +static void WriteFlashByte(uint32_t address, uint8_t inputValue) +{ + uint32_t flsAddr = address - CYDEV_FLASH_BASE; + uint8_t rowData[CYDEV_FLS_ROW_SIZE]; + + uint8_t arrayId = (uint8_t) (flsAddr / CYDEV_FLS_SECTOR_SIZE); + uint16_t rowNum = (uint16_t) ((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE); + uint32_t baseAddr = address - (address % CYDEV_FLS_ROW_SIZE); + + for (uint32_t idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++) + { + rowData[idx] = (uint8_t) Bootloadable_GET_CODE_DATA(baseAddr + idx); + } + + rowData[address % CYDEV_FLS_ROW_SIZE] = inputValue; + + (void) CyWriteRowData(arrayId, rowNum, rowData); + + /* + * When writing to flash, data in the instruction cache can become stale + * A call to CyFlushCache() is required to invalidate the data in the + * cache and force fresh information to be loaded. + */ + CyFlushCache(); +} + + +/****************************************************************************** +* SetKitProgActiveApp +***************************************************************************//** +* Sets the KitProg as active application. +* Active application is application which will be loaded after a next reset event. +* +* @note +* The active application number is not set directly, but the boolean +* mark instead means that the application is active or not for the relative +* metadata. Both metadata sections are updated. For example, if the second +* application is to be set active, then in the metadata section for the first +* application there will be a "0" written, which means that it is not active, +* and for the second metadata section there will be a "1" written, which means +* that it is active. +* +******************************************************************************/ +static void SetKitProgActiveApp(void) +{ + uint8 buff[CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE]; + + /* + * Use CySetTemp API to initialize SPC. + * This step enables writing to flash memory. + */ + if ( CySetTemp() != CYRET_SUCCESS ) + { + CyHalt(0x00u); + } + + CySetFlashEEBuffer(buff); + + /* Mark KitProg as active application */ + WriteFlashByte( KIT_PROG_ACTIVE_ADDR, APP_ACTIVE ); + + /* Mark Custom Application as inactive application */ + WriteFlashByte( CUSTOM_APP_ACTIVE_ADDR, APP_INACTIVE ); + + EEPROM_ModeStorage_Start(); + /* Provide a 10us delay for EEPROM data to stabilize. */ + CyDelayUs(10u); + + /* Write the MODE_BULK as current mode setting to the EEPROM. */ + if (CySetTemp() == CYRET_SUCCESS) + { + EEPROM_ModeStorage_ByteWrite(MODE_BULK, 0u, 0u); + } + + CySoftwareReset(); +} + +/****************************************************************************** +* HW_CheckAppSwitch +***************************************************************************//** +* Check on-board buttons and perform switch to KitProg application if user +* requested that action by pressing buttons. +* +******************************************************************************/ +void HW_CheckAppSwitch(void) +{ + /* Check that button is pressed */ + if (ModeButton_Read() == 0) + { + app_switch_counter++; + } + else + { + /* button released */ + app_switch_counter_last = app_switch_counter; + app_switch_counter = 0; + } + + /* Check that button is pressed for required duration and release */ + if (app_switch_counter_last > APP_SWITCH_TIMEOUT) + { + SetKitProgActiveApp(); + } +} + +uint8_t gpio_get_reset_btn_fwrd() +{ + HW_CheckAppSwitch(); + return 0; +} + +uint8_t gpio_get_reset_btn_no_fwrd(void) +{ + return 0; +} + +void gpio_init(void) +{ +} + +void gpio_set_cdc_led(gpio_led_state_t state) +{ + if (kit_has_three_led()) + { + LED_Red_Write(state); + } +} + +void gpio_set_hid_led(gpio_led_state_t state) +{ +} + +void gpio_set_msc_led(gpio_led_state_t state) +{ + if (kit_has_three_led()) + { + LED_Green_Write(state); + } +} + +void gpio_set_board_power(bool powerEnabled) +{ +} diff --git a/source/hic_hal/cypress/psoc5lp/psoc5lp.h b/source/hic_hal/cypress/psoc5lp/psoc5lp.h new file mode 100644 index 0000000000..7449c51a5e --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/psoc5lp.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* @file psoc5lp.h +* @brief CMSIS Peripheral Access Layer for PSOC5LP +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#ifndef _PSOC5LP_H_ +#define _PSOC5LP_H_ /**< Symbol preventing repeated inclusion */ + +/* + * \brief CMSIS includes + */ + +#include "core_cm3_psoc5.h" + + +#endif diff --git a/source/hic_hal/cypress/psoc5lp/read_uid.c b/source/hic_hal/cypress/psoc5lp/read_uid.c new file mode 100644 index 0000000000..c776982c83 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/read_uid.c @@ -0,0 +1,32 @@ +/******************************************************************************* +* @file read_uid.c +* @brief Read unique id from PSoC5LP +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "read_uid.h" +#include "cydevice.h" + +void read_unique_id(uint32_t *id) +{ + + id[0] = *(uint32_t*) (CYDEV_FLSHID_CUST_TABLES_BASE); + id[1] = *(uint32_t*) (CYDEV_FLSHID_CUST_TABLES_BASE + 1); + id[3] = 0; + id[4] = 0; +} diff --git a/source/hic_hal/cypress/psoc5lp/sdk.c b/source/hic_hal/cypress/psoc5lp/sdk.c new file mode 100644 index 0000000000..937bb46c10 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/sdk.c @@ -0,0 +1,47 @@ +/******************************************************************************* +* @file sdk.c +* @brief PSoC5LP specific initialization +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "cyfitter_cfg.h" +#include "CyLib.h" +#include "LED_Amber.h" +#include "LED_Green.h" +#include "LED_Red.h" +#include "Timer_CSTick.h" +#include "Clk_Brea1.h" +#include "Clk_Brea2.h" + +extern void initialize_psoc(void); + +void sdk_init() +{ + CyGlobalIntEnable + ; + + /* Start Time source timer as soon as possible */ + Timer_CSTick_Start(); + + LED_Amber_SetDriveMode(CY_PINS_DM_OD_HI); + LED_Green_SetDriveMode(CY_PINS_DM_OD_HI); + LED_Red_SetDriveMode(CY_PINS_DM_OD_HI); + + Clk_Brea1_Enable(); + Clk_Brea2_Enable(); +} diff --git a/source/hic_hal/cypress/psoc5lp/swd.h b/source/hic_hal/cypress/psoc5lp/swd.h new file mode 100644 index 0000000000..301795d193 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/swd.h @@ -0,0 +1,174 @@ +/******************************************************************************* +* @file swd.h +* @brief This file contains the function prototypes and constants used in +* the swd.c +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ +#if !defined(SWD_H) +#define SWD_H + +#include +#include "cypins.h" +#include "SWDCLK.h" +#include "SWDIO.h" +#include "SWDXRES.h" + + +/***************************************************************************** +* MACRO Definition +*****************************************************************************/ +#define BIT0 (0x01u) +#define BIT1 (0x02u) +#define BIT2 (0x04u) +#define BIT3 (0x08u) +#define BIT4 (0x10u) +#define BIT5 (0x20u) +#define BIT6 (0x40u) +#define BIT7 (0x80u) + +/* Programming pin drive modes */ +#define SWD_SET_SDA_OUT CyPins_SetPinDriveMode(SWDIO_0, SWDIO_DM_STRONG) +#define SWD_SET_SDA_IN CyPins_SetPinDriveMode(SWDIO_0, SWDIO_DM_DIG_HIZ) +#define SWD_SET_SCK_OUT CyPins_SetPinDriveMode(SWDCLK_0, SWDCLK_DM_STRONG) +#define SWD_SET_SCK_IN CyPins_SetPinDriveMode(SWDCLK_0, SWDCLK_DM_DIG_HIZ) +#define SWD_SET_XRES_OUT CyPins_SetPinDriveMode(SWDXRES_0, SWDXRES_DM_STRONG) +#define SWD_SET_XRES_IN CyPins_SetPinDriveMode(SWDXRES_0, SWDXRES_DM_DIG_HIZ) + +/* SWD line communication macros */ +#define SWD_XFER_SIZE (0x04u) +#define SWD_OFLOW BIT7 +#define SWD_UFLOW BIT6 +#define SWD_DONE BIT5 +#define SWD_PERR BIT3 +#define SWD_FAULT BIT2 +#define SWD_WAIT BIT1 +#define SWD_ACK BIT0 +#define SWD_ACK_BITS (SWD_FAULT | SWD_WAIT | SWD_ACK) +#define SWD_ERROR SWD_ACK_BITS + +/* Acquire result macros */ +#define ACQUIRE_PASS (0x01u) +#define ACQUIRE_FAIL (0x00u) + +/* Bit banding of the SRAM addresses in order to address each bit of a byte separately. */ +#define BIT_ADDRESS (0x20000100u) +#define SWD_BYTE (*((volatile uint8_t *)BIT_ADDRESS)) + +/* Convert SRAM address to SRAM bit map region */ +#define BITBAND_SRAM_REF (CYREG_SRAM_DATA_MBASE) +#define BITBAND_SRAM_BASE (CYREG_SRAM_DATA_MBASE + 0x2000000u) + +#define SWD_DATA_BIT_B0 (*((volatile uint8_t *)((BITBAND_SRAM_BASE + (BIT_ADDRESS-BITBAND_SRAM_REF)*32u + (0u*4u))))) +#define SWD_DATA_BIT_B1 (*((volatile uint8_t *)((BITBAND_SRAM_BASE + (BIT_ADDRESS-BITBAND_SRAM_REF)*32u + (1u*4u))))) +#define SWD_DATA_BIT_B2 (*((volatile uint8_t *)((BITBAND_SRAM_BASE + (BIT_ADDRESS-BITBAND_SRAM_REF)*32u + (2u*4u))))) +#define SWD_DATA_BIT_B3 (*((volatile uint8_t *)((BITBAND_SRAM_BASE + (BIT_ADDRESS-BITBAND_SRAM_REF)*32u + (3u*4u))))) +#define SWD_DATA_BIT_B4 (*((volatile uint8_t *)((BITBAND_SRAM_BASE + (BIT_ADDRESS-BITBAND_SRAM_REF)*32u + (4u*4u))))) +#define SWD_DATA_BIT_B5 (*((volatile uint8_t *)((BITBAND_SRAM_BASE + (BIT_ADDRESS-BITBAND_SRAM_REF)*32u + (5u*4u))))) +#define SWD_DATA_BIT_B6 (*((volatile uint8_t *)((BITBAND_SRAM_BASE + (BIT_ADDRESS-BITBAND_SRAM_REF)*32u + (6u*4u))))) +#define SWD_DATA_BIT_B7 (*((volatile uint8_t *)((BITBAND_SRAM_BASE + (BIT_ADDRESS-BITBAND_SRAM_REF)*32u + (7u*4u))))) + +/* Bit banding of the peripheral addresses for flexibility in addressing SWDIO and SWDCLK */ +/* Convert Peripheral address to peripheral bit map region */ +#define BITBAND_PERI_REF (0x40000000u) +#define BITBAND_PERI_BASE (0x42000000u) + +#define SWD_BITS (SWDCLK__DR) +#define SWD_SDA (*((volatile uint8_t *)((BITBAND_PERI_BASE + (SWD_BITS-BITBAND_PERI_REF)*32u + (SWDIO_SHIFT*4u))))) +#define SWD_SCK (*((volatile uint8_t *)((BITBAND_PERI_BASE + (SWD_BITS-BITBAND_PERI_REF)*32u + (SWDCLK_SHIFT*4u))))) +#define SDA_PS (*((volatile uint8_t *)((BITBAND_PERI_BASE + (SWDIO__PS-BITBAND_PERI_REF)*32u + (SWDIO_SHIFT*4u))))) +#define SCL_PS (*((volatile uint8_t *)(((BITBAND_PERI_BASE + (SWDCLK__PS-BITBAND_PERI_REF)*32u + (SWDCLK_SHIFT*4u)))))) +#define XRES_PS (*((volatile uint8_t *)(((BITBAND_PERI_BASE + (SWDXRES__PS-BITBAND_PERI_REF)*32u + (SWDXRES_SHIFT*4u)))))) + +#define SWD_SET_SCK_LO (SWD_SCK = 0u) +#define SWD_SET_SCK_HI (SWD_SCK = 1u) +#define SWD_SET_SDA_LO (SWD_SDA = 0u) +#define SWD_SET_SDA_HI (SWD_SDA = 1u) +#define SWD_SET_XRES_HI CyPins_SetPin(SWDXRES_0) +#define SWD_SET_XRES_LO CyPins_ClearPin(SWDXRES_0) + +#define SWD_GET_SDA (SDA_PS) +#define SWD_GET_SCL (SCL_PS) +#define SWD_GET_XRES (XRES_PS) + +/* One Clock on the SWDCLK line */ +#define SWD_CLOCK_BIT ({SWD_SET_SCK_LO;CY_NOP;CY_NOP;CY_NOP;SWD_SET_SCK_HI;CY_NOP;CY_NOP;CY_NOP;}) + +/* Acquire target*/ +#define ACQUIRE_PSoC4 (0x00u) +#define ACQUIRE_PSoC5_ES2 (0x01u) +#define ACQUIRE_PSoC6_BLE (0x02u) +#define ACQUIRE_TVII (0x03u) + +/* SWD data macros */ +#define SWD_DATA_SIZE (5u) +#define ONE_VOLT (1000u) + +/* Test mode register mask */ +#define SRSS_TST_MODE_TEST_MODE_MSK (0x80000000u) + +/* DHCSR register masks */ +#define ARM_DHCSR_S_LOCKUP_MSK (0x00080000u) +#define ARM_DHCSR_S_HALT_MSK (0x00020000u) + +/* Macro Definitions for Debug and Access Port registers read and write Commands + used in the functions defined in UpperPacketLayer.c */ +#define DPACC_DP_CTRLSTAT_READ (0x8Du) +#define DPACC_DP_IDCODE_READ (0xA5u) +#define DPACC_AP_CSW_READ (0x87u) +#define DPACC_AP_TAR_READ (0xAFu) +#define DPACC_AP_DRW_READ (0x9Fu) + +#define DPACC_DP_CTRLSTAT_WRITE (0xA9u) +#define DPACC_DP_SELECT_WRITE (0xB1u) +#define DPACC_AP_CSW_WRITE (0xA3u) +#define DPACC_AP_TAR_WRITE (0x8Bu) +#define DPACC_AP_DRW_WRITE (0xBBu) +#define DPACC_DP_ABORT_WRITE (0x81u) + + +/***************************************************************************** +* Function Prototypes +*****************************************************************************/ + +/****************************************************************************** +* SWDInit +***************************************************************************//** +* Initializes SWD side of communication. +* +******************************************************************************/ +void SWDInit(void); + +/****************************************************************************** +* SWDAcquire +***************************************************************************//** +* Performs Acquire procedure . +* +* @param[in] dut Target chip to acquire. +* @param[in] acquireMode Acquiring mode (0 - Reset, 1- Power Cycle) +* @param[in] attempts Number of attempts +* +* @return Device acquiring status +* +******************************************************************************/ +uint32_t SWDAcquire(uint32_t dut, uint32_t acquireMode, uint32_t attempts); + + +#endif /* SWD_H */ + + +/* [] END OF FILE */ diff --git a/source/hic_hal/cypress/psoc5lp/uart.c b/source/hic_hal/cypress/psoc5lp/uart.c new file mode 100644 index 0000000000..19a941f1c7 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/uart.c @@ -0,0 +1,144 @@ +/******************************************************************************* + +* @file uart.c +* @brief PSoC5LP HW uart API +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "string.h" + +#include "uart.h" +#include "util.h" +#include "cortex_m.h" +#include "circ_buf.h" +#include "settings.h" // for config_get_overflow_detect + +#include "RTL.h" +#include "rl_usb.h" +#include "usb_for_lib.h" + +#include "UART_Bridge.h" +#include "Pin_UART_Tx.h" +#include "Clock_UART.h" +#include "usbd_PSoC5LP.h" + +/* USB IN EndPoint Packet size */ +#define USBINPACKETSIZE 64 + +int32_t uart_read_data(uint8_t *data, uint16_t size) +{ + uint32_t wCount; + uint32_t bIndex; + + uint8_t status = UART_Bridge_ReadRxStatus(); + if (status & UART_Bridge_RX_STS_SOFT_BUFF_OVER) + { + UART_Bridge_ClearRxBuffer(); + } + + if (status == (UART_Bridge_RX_STS_OVERRUN | UART_Bridge_RX_STS_FIFO_NOTEMPTY)) + { + // restart UART component to force clear overrun condition + UART_Bridge_Stop(); + UART_Bridge_initVar = 0; + UART_Bridge_Start(); + } + + wCount = UART_Bridge_GetRxBufferSize(); + wCount = wCount < USBINPACKETSIZE ? wCount : USBINPACKETSIZE; + + /* Choose the lesser of the evils */ + if (size < wCount) + { + wCount = size; + } + + /* Check if Rx has data */ + if (wCount != 0) + { + for (bIndex = 0; bIndex < wCount; bIndex++) + { + /* Load from UART RX Buffer to USB */ + data[bIndex] = UART_Bridge_ReadRxData(); + } + } + return wCount; +} + +int32_t uart_write_data(uint8_t *data, uint16_t size) +{ + /* Send to UART Tx */ + UART_Bridge_PutArray(data, size); + /* release pointer to the receive intermediate buffer to the received unread data */ + if (ptr_data_read == ptr_data_received) + { + USBD_CDC_ACM_SOF_Event(); + } + return size; +} + +int32_t uart_initialize(void) +{ + uint16_t wDivider = DIVIDER115200; + UART_Bridge_Stop(); + + /* Select clock source (PLL) */ + Clock_UART_Stop(); + Clock_UART_SetSourceRegister(CYCLK_SRC_SEL_PLL); + Clock_UART_Start(); + + /* Set new Clock Frequency divider */ + Clock_UART_SetDivider(wDivider - 1u); + + UART_Bridge_Start(); + + /* Initialize CDC Interface for USB-UART Bridge */ + //USBFS_CDC_Init(); + Pin_UART_Tx_SetDriveMode(Pin_UART_Tx_DM_STRONG); + return 0; +} + +int32_t uart_reset(void) +{ + return 0; +} + +int32_t uart_set_configuration(UART_Configuration *config) +{ + return 0; +} + +int32_t uart_uninitialize(void) +{ + return 0; +} + +int32_t uart_write_free(void) +{ + uint32_t size_to_write = UART_Bridge_TX_BUFFER_SIZE - UART_Bridge_GetTxBufferSize(); + uint32_t size_to_send = data_to_send_wr - data_to_send_rd; + if ((size_to_send > 0) && (usb_state == USB_CONNECTED)) + { + if (data_send_active == 0) + { + USBD_CDC_ACM_SOF_Event(); + } + } + + return size_to_write; +} diff --git a/source/hic_hal/cypress/psoc5lp/usb_buf.h b/source/hic_hal/cypress/psoc5lp/usb_buf.h new file mode 100644 index 0000000000..534785dcd0 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/usb_buf.h @@ -0,0 +1,31 @@ +/******************************************************************************* +* @file usb_buf.h +* @brief USB MSC buffer definition +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#ifndef USB_BUF_H +#define USB_BUF_H + + +#include "stdint.h" + +#define USB_MSC_BUF_SIZE (512) +uint32_t usb_buffer[USB_MSC_BUF_SIZE / sizeof(uint32_t)]; + +#endif diff --git a/source/hic_hal/cypress/psoc5lp/usb_config.c b/source/hic_hal/cypress/psoc5lp/usb_config.c new file mode 100644 index 0000000000..a4507a212c --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/usb_config.c @@ -0,0 +1,531 @@ +/******************************************************************************* +* @file usb_config.h +* @brief USB configuration contants +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +// USB Device +// Enable the USB Device functionality +#define USBD_ENABLE 1 +#define USBD_RTX_CORE_STACK 0 +#define USBD_RTX_DEVICE_STACK 0 +#define USBD_RTX_ENDPOINT0_STACK 0 + +// High-speed +// Enable high-speed functionality (if device supports it) +#define USBD_HS_ENABLE 0 +#if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE)) +#define USBD_BOS_ENABLE 1 +#else +#define USBD_BOS_ENABLE 0 +#endif +// Device Settings +// These settings affect Device Descriptor +// Power +// Default Power Setting +// <0=> Bus-powered +// <1=> Self-powered +// Max Endpoint 0 Packet Size +// Maximum packet size for endpoint zero (bMaxPacketSize0) +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes +// Vendor ID <0x0000-0xFFFF> +// Vendor ID assigned by the USB-IF (idVendor) +// Product ID <0x0000-0xFFFF> +// Product ID assigned by the manufacturer (idProduct) +// Device Release Number <0x0000-0xFFFF> +// Device release number in binary-coded decimal (bcdDevice) +// +#define USBD_POWER 0 +#define USBD_MAX_PACKET0 64 +#define USBD_DEVDESC_IDVENDOR 0x0D28 +#define USBD_DEVDESC_IDPRODUCT 0x0204 +#define USBD_DEVDESC_BCDDEVICE 0x1000 //was 0x0100 + +// Configuration Settings +// These settings affect Configuration Descriptor +// Remote Wakeup +// Configuration support for remote wakeup (D5: of bmAttributes) +// Maximum Power Consumption (in mA) <0-510><#/2> +// Maximum power consumption of the USB device +// from the bus in this specific configuration +// when the device is fully operational (bMaxPower) +// +#define USBD_CFGDESC_BMATTRIBUTES 0x80 +#define USBD_CFGDESC_BMAXPOWER 0xFA + +// String Settings +// These settings affect String Descriptor +// Language ID <0x0000-0xFCFF> +// English (United States) = 0x0409 +// Manufacturer String +// String descriptor describing manufacturer +// Product String +// String descriptor describing product +// Serial Number +// Enable serial number string +// If disabled serial number string will not be assigned to the USB Device +// Serial Number String +// String descriptor describing device's serial number +// +// +#define USBD_STRDESC_LANGID 0x0409 +#define USBD_STRDESC_MAN L"ARM" +#ifndef USB_PROD_STR +#define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" +#else +#define _TOWIDE(x) L ## #x +#define TOWIDE(x) _TOWIDE(x) +#define USBD_STRDESC_PROD TOWIDE(USB_PROD_STR) +#endif +#define USBD_STRDESC_SER_ENABLE 1 +#define USBD_STRDESC_SER L"0001A0000000" + +// Class Support +// Enables USB Device Class specific Requests +#define USBD_CLASS_ENABLE 1 + +// Human Interface Device (HID) +// Enable class support for Human Interface Device (HID) +// Interrupt Endpoint Settings +// Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Interrupt Out Endpoint Number <0=> Not used <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// If interrupt out endpoint is not used select "Not used" +// Endpoint Settings +// Maximum Endpoint Packet Size (in bytes) <0-64> +// Endpoint polling Interval (in ms) <1-255> +// High-speed +// If high-speed is enabled set endpoint settings for it +// Maximum Endpoint Packet Size (in bytes) <0-1024> +// Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// +// +// +// Human Interface Device Settings +// Device specific settings +// HID Interface String +// Number of Input Reports <1-32> +// Number of Output Reports <1-32> +// Maximum Input Report Size (in bytes) <1-65535> +// Maximum Output Report Size (in bytes) <1-65535> +// Maximum Feature Report Size (in bytes) <1-65535> +// +// +#ifndef HID_ENDPOINT +#define HID_ENDPOINT 0 +#else +#define HID_ENDPOINT 1 +#endif + +#ifndef WEBUSB_INTERFACE +#define WEBUSB_INTERFACE 0 +#else +#define WEBUSB_INTERFACE 1 +#endif + +#define USBD_HID_ENABLE HID_ENDPOINT +#define USBD_HID_EP_INTIN 1 +#define USBD_HID_EP_INTOUT 1 + +#define USBD_HID_EP_INTIN_STACK 0 +#define USBD_HID_WMAXPACKETSIZE 64 +#define USBD_HID_BINTERVAL 1 +#define USBD_HID_HS_ENABLE 0 +#define USBD_HID_HS_WMAXPACKETSIZE 64 +#define USBD_HID_HS_BINTERVAL 6 +#define USBD_HID_STRDESC L"CMSIS-DAP" +#define USBD_WEBUSB_STRDESC L"WebUSB: CMSIS-DAP" +#define USBD_HID_INREPORT_NUM 1 +#define USBD_HID_OUTREPORT_NUM 1 +#define USBD_HID_INREPORT_MAX_SZ 64 +#define USBD_HID_OUTREPORT_MAX_SZ 64 +#define USBD_HID_FEATREPORT_MAX_SZ 1 + +// Mass Storage Device (MSC) +// Enable class support for Mass Storage Device (MSC) +// Bulk Endpoint Settings +// Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Endpoint Settings +// Maximum Packet Size <1-1024> +// High-speed +// If high-speed is enabled set endpoint settings for it +// Maximum Packet Size <1-1024> +// Maximum NAK Rate <0-255> +// +// +// +// Mass Storage Device Settings +// Device specific settings +// MSC Interface String +// Inquiry Data +// Vendor Identification +// Product Identification +// Product Revision Level +// +// +// +#ifndef MSC_ENDPOINT +#define MSC_ENDPOINT 0 +#else +#define MSC_ENDPOINT 1 +#endif +#define USBD_MSC_ENABLE MSC_ENDPOINT +#define USBD_MSC_EP_BULKIN 2 +#define USBD_MSC_EP_BULKOUT 2 +#define USBD_MSC_EP_BULKIN_STACK 0 +#define USBD_MSC_WMAXPACKETSIZE 64 +#define USBD_MSC_HS_ENABLE 0 +#define USBD_MSC_HS_WMAXPACKETSIZE 512 +#define USBD_MSC_HS_BINTERVAL 0 +#define USBD_MSC_STRDESC L"USB_MSC" +// Make sure changes to USBD_MSC_INQUIRY_DATA are coordinated with mbed-ls +// since this is used to detect DAPLink drives +#define USBD_MSC_INQUIRY_DATA "MBED " \ + "VFS " \ + "0.1" + +// Audio Device (ADC) +// Enable class support for Audio Device (ADC) +// Isochronous Endpoint Settings +// Isochronous Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Endpoint Settings +// Maximum Endpoint Packet Size (in bytes) <0-1024> +// Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// High-speed +// If high-speed is enabled set endpoint settings for it +// Maximum Endpoint Packet Size (in bytes) <0-1024> +// Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// +// +// +// Audio Device Settings +// Device specific settings +// Audio Control Interface String +// Audio Streaming (Zero Bandwidth) Interface String +// Audio Streaming (Operational) Interface String +// Audio Subframe Size (in bytes) <0-255> +// Sample Resolution (in bits) <0-255> +// Sample Frequency (in Hz) <0-16777215> +// Packet Size (in bytes) <1-256> +// Packet Count <1-16> +// +// +#define USBD_ADC_ENABLE 0 +#define USBD_ADC_EP_ISOOUT 3 +#define USBD_ADC_WMAXPACKETSIZE 64 +#define USBD_ADC_BINTERVAL 1 +#define USBD_ADC_HS_ENABLE 0 +#define USBD_ADC_HS_WMAXPACKETSIZE 64 +#define USBD_ADC_CIF_STRDESC L"USB_ADC" +#define USBD_ADC_SIF1_STRDESC L"USB_ADC1" +#define USBD_ADC_SIF2_STRDESC L"USB_ADC2" +#define USBD_ADC_BSUBFRAMESIZE 2 +#define USBD_ADC_BBITRESOLUTION 16 +#define USBD_ADC_TSAMFREQ 32000 +#define USBD_ADC_CFG_P_S 32 +#define USBD_ADC_CFG_P_C 1 + +// Communication Device (CDC) - Abstract Control Model (ACM) +// Enable class support for Communication Device (CDC) - Abstract Control Model (ACM) +// Interrupt Endpoint Settings +// Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Endpoint Settings +// Maximum Endpoint Packet Size (in bytes) <0-1024> +// Endpoint polling Interval (in ms) <0-255> +// High-speed +// If high-speed is enabled set endpoint settings for it +// Maximum Endpoint Packet Size (in bytes) <0-1024> +// Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// +// +// +// Bulk Endpoint Settings +// Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Endpoint Settings +// Maximum Packet Size <1-1024> +// High-speed +// If high-speed is enabled set endpoint settings for it +// Maximum Packet Size <1-1024> +// Maximum NAK Rate <0-255> +// +// +// +// Communication Device Settings +// Device specific settings +// Communication Class Interface String +// Data Class Interface String +// Maximum Communication Device Send Buffer Size +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// Maximum Communication Device Receive Buffer Size +// Minimum size must be as big as maximum packet size for Bulk Out Endpoint +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// +// + +#ifndef CDC_ENDPOINT +#define CDC_ENDPOINT 0 +#else +#define CDC_ENDPOINT 1 +#endif +#define USBD_CDC_ACM_ENABLE CDC_ENDPOINT +#define USBD_CDC_ACM_EP_INTIN 3 +#define USBD_CDC_ACM_EP_INTIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_BINTERVAL 32 +#define USBD_CDC_ACM_HS_ENABLE 0 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_HS_BINTERVAL 2 +#define USBD_CDC_ACM_EP_BULKIN 4 +#define USBD_CDC_ACM_EP_BULKOUT 4 +#define USBD_CDC_ACM_EP_BULKIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_ENABLE1 0 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_BINTERVAL1 0 +#define USBD_CDC_ACM_CIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_DIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_SENDBUF_SIZE 64 +#define USBD_CDC_ACM_RECEIVEBUF_SIZE 64 +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Send Buffer size must be larger or equal to Bulk In maximum packet size!" +#endif +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Receive Buffer size must be larger or equal to Bulk Out maximum packet size!" +#endif + +// Custom Class Device +// Enables USB Custom Class Requests +// Class IDs: +// 0x00 - Class Reserved ID +// 0x01 - Class Audio ID +// 0x02 - Class Communications ID +// 0x03 - Class Human Interface ID +// 0x04 - Class Monitor ID +// 0x05 - Class Physical Interface ID +// 0x06 - Class Power ID +// 0x07 - Class Printer ID +// 0x08 - Class Storage ID +// 0x09 - Class HUB ID +// 0xEF - Class Miscellaneous ID +// 0xFF - Class Vendor Specific ID +// +#define USBD_CLS_ENABLE 0 + +// WebUSB support +#define USBD_WEBUSB_ENABLE WEBUSB_INTERFACE +#define USBD_WEBUSB_VENDOR_CODE 0x21 +#define USBD_WEBUSB_LANDING_URL "os.mbed.com/webusb/landing-page/?bid=" +#define USBD_WEBUSB_ORIGIN_URL "os.mbed.com/" + +// Microsoft OS Descriptors 2.0 (WinUSB) support +#define USBD_WINUSB_ENABLE WINUSB_INTERFACE +#define USBD_WINUSB_VENDOR_CODE 0x20 +#define USBD_WINUSB_IF_NUM USBD_WEBUSB_IF_NUM +// +// + + +/* USB Device Calculations ---------------------------------------------------*/ + +#define USBD_IF_NUM_MAX (USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) +#define USBD_MULTI_IF (USBD_CDC_ACM_ENABLE*(USBD_HID_ENABLE|USBD_MSC_ENABLE|USBD_ADC_ENABLE|USBD_CLS_ENABLE|USBD_WEBUSB_ENABLE)) +#define MAX(x, y) (((x) < (y)) ? (y) : (x)) +#define USBD_EP_NUM_CALC0 MAX((USBD_HID_ENABLE *(USBD_HID_EP_INTIN )), (USBD_HID_ENABLE *(USBD_HID_EP_INTOUT!=0)*(USBD_HID_EP_INTOUT))) +#define USBD_EP_NUM_CALC1 MAX((USBD_MSC_ENABLE *(USBD_MSC_EP_BULKIN )), (USBD_MSC_ENABLE *(USBD_MSC_EP_BULKOUT))) +#define USBD_EP_NUM_CALC2 MAX((USBD_ADC_ENABLE *(USBD_ADC_EP_ISOOUT )), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_INTIN))) +#define USBD_EP_NUM_CALC3 MAX((USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKIN)), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKOUT))) +#define USBD_EP_NUM_CALC4 MAX(USBD_EP_NUM_CALC0, USBD_EP_NUM_CALC1) +#define USBD_EP_NUM_CALC5 MAX(USBD_EP_NUM_CALC2, USBD_EP_NUM_CALC3) +#define USBD_EP_NUM_CALC6 MAX(USBD_EP_NUM_CALC4, USBD_EP_NUM_CALC5) +#define USBD_EP_NUM (USBD_EP_NUM_CALC6) + +#if (USBD_HID_ENABLE) +#if (USBD_MSC_ENABLE) +#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKOUT))) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKOUT))) +#error "HID and Mass Storage Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_ADC_ENABLE) +#if ((USBD_HID_EP_INTIN == USBD_ADC_EP_ISOOUT) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_ADC_EP_ISOOUT))) +#error "HID and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (((USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKOUT))|| \ + ((USBD_HID_EP_INTOUT != 0) && \ + ((USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKOUT)))) +#error "HID and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_MSC_ENABLE) +#if (USBD_ADC_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_ADC_EP_ISOOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_ADC_EP_ISOOUT)) +#error "Mass Storage Device and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Mass Storage Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_ADC_ENABLE) +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Audio Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#define USBD_ADC_CIF_NUM (0) +#define USBD_ADC_SIF1_NUM (1) +#define USBD_ADC_SIF2_NUM (2) +#define USBD_MSC_IF_NUM (USBD_ADC_ENABLE*2+0) +#define USBD_CDC_ACM_CIF_NUM (USBD_ADC_ENABLE*2+USBD_MSC_ENABLE*1+0) +#define USBD_CDC_ACM_DIF_NUM (USBD_ADC_ENABLE*2+USBD_MSC_ENABLE*1+1) +#define USBD_HID_IF_NUM (USBD_ADC_ENABLE*2+USBD_MSC_ENABLE*1+USBD_CDC_ACM_ENABLE*2+0) +#define USBD_WEBUSB_IF_NUM (USBD_ADC_ENABLE*2+USBD_MSC_ENABLE*1+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) + +#define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) +#define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) +#define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) +#define USBD_CDC_ACM_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+0) +#define USBD_CDC_ACM_DIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+1) +#define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) +#define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) +#define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) + +#if (USBD_HID_ENABLE) +#if (USBD_HID_HS_ENABLE) +#define USBD_HID_MAX_PACKET ((USBD_HID_HS_WMAXPACKETSIZE > USBD_HID_WMAXPACKETSIZE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) +#else +#define USBD_HID_MAX_PACKET (USBD_HID_WMAXPACKETSIZE) +#endif +#else +#define USBD_HID_MAX_PACKET (0) +#endif +#if (USBD_MSC_ENABLE) +#if (USBD_MSC_HS_ENABLE) +#define USBD_MSC_MAX_PACKET ((USBD_MSC_HS_WMAXPACKETSIZE > USBD_MSC_WMAXPACKETSIZE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) +#else +#define USBD_MSC_MAX_PACKET (USBD_MSC_WMAXPACKETSIZE) +#endif +#else +#define USBD_MSC_MAX_PACKET (0) +#endif +#if (USBD_ADC_ENABLE) +#if (USBD_ADC_HS_ENABLE) +#define USBD_ADC_MAX_PACKET ((USBD_ADC_HS_WMAXPACKETSIZE > USBD_ADC_WMAXPACKETSIZE) ? USBD_ADC_HS_WMAXPACKETSIZE : USBD_ADC_WMAXPACKETSIZE) +#else +#define USBD_ADC_MAX_PACKET (USBD_ADC_WMAXPACKETSIZE) +#endif +#else +#define USBD_ADC_MAX_PACKET (0) +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (USBD_CDC_ACM_HS_ENABLE) +#define USBD_CDC_ACM_MAX_PACKET ((USBD_CDC_ACM_HS_WMAXPACKETSIZE > USBD_CDC_ACM_WMAXPACKETSIZE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE : USBD_CDC_ACM_WMAXPACKETSIZE) +#else +#define USBD_CDC_ACM_MAX_PACKET (USBD_CDC_ACM_WMAXPACKETSIZE) +#endif +#if (USBD_CDC_ACM_HS_ENABLE1) +#define USBD_CDC_ACM_MAX_PACKET1 ((USBD_CDC_ACM_HS_WMAXPACKETSIZE1 > USBD_CDC_ACM_WMAXPACKETSIZE1) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) +#else +#define USBD_CDC_ACM_MAX_PACKET1 (USBD_CDC_ACM_WMAXPACKETSIZE1) +#endif +#else +#define USBD_CDC_ACM_MAX_PACKET (0) +#define USBD_CDC_ACM_MAX_PACKET1 (0) +#endif +#define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) +#define USBD_MAX_PACKET ((USBD_MAX_PACKET_CALC2 > USBD_CDC_ACM_MAX_PACKET1 ) ? (USBD_MAX_PACKET_CALC2) : (USBD_CDC_ACM_MAX_PACKET1 )) + + +/*------------------------------------------------------------------------------ + * USB Config Functions + *----------------------------------------------------------------------------*/ + +#ifndef __USB_CONFIG___ +#define __USB_CONFIG__ + +#ifndef __NO_USB_LIB_C +#include "usb_lib.c" +#endif + +#endif /* __USB_CONFIG__ */ diff --git a/source/hic_hal/cypress/psoc5lp/usbd_PSoC5LP.c b/source/hic_hal/cypress/psoc5lp/usbd_PSoC5LP.c new file mode 100644 index 0000000000..0189f824fd --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/usbd_PSoC5LP.c @@ -0,0 +1,573 @@ +/******************************************************************************* +* @file usbd_PSoC5LP.c +* @brief PSoC5LP usbd API implementation +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ + +#include "RTL.h" +#include "usb_def.h" +#include "usb_msc.h" +#include "usbd_core.h" +#include "usbd_hw.h" +#include "usbd_msc.h" +#include "usbd_event.h" +#include "usbd_hid.h" +#include "USBFS.h" +#include "USBFS_pvt.h" +#include "usbd_PSoC5LP.h" +#include "info.h" +#include "usbd_cdc_acm.h" +#include "UART_Bridge.h" +#include "Clock_UART.h" +#include "Pin_UART_Tx.h" +#include "rl_usb.h" + +#define USBD_MSC_EP_BULKOUT (0x02u) +#define USBD_MSC_EP_BULKIN (0x82u) +#define USBD_CDC_ACM_EP_INTIN (0x03u) +#define USBD_CDC_ACM_EP_BULKOUT (0x04u) +#define USBD_CDC_ACM_EP_BULKIN (0x84u) +#define USBD_HID_EP_INTOUT (0x01u) +#define USBD_HID_EP_INTIN (0x81u) + +#define EP_NOT_FOUND (0xFFFFFFFFu) + +volatile uint8 USBFS_EP_Mask[USBFS_MAX_EP]; +volatile uint8 USBFS_BUS_RESET = __FALSE; +volatile uint8 USBFS_CDCClassRqst = __FALSE; +volatile uint16_t break_value; +volatile uint8_t break_req = 0; + +void IncEPReq(uint8 epNumber) +{ + if (USBFS_EP_Mask[epNumber] < 0xFFu) + { + USBFS_EP_Mask[epNumber]++; + } +} + +void DecEPReq(uint8 epNumber) +{ + if ((epNumber == USBFS_EP6) || (epNumber == USBFS_EP7)) + { + USBFS_EP_Mask[epNumber] = 0; + } + else + { + if (USBFS_EP_Mask[epNumber] > 0) + { + USBFS_EP_Mask[epNumber]--; + } + } +} + +U32 FwEPToHwEP(U32 FwEP) +{ + U32 HwEP; + switch (FwEP) + { + case USBD_MSC_EP_BULKIN: + HwEP = USBFS_EP1; + break; + case USBD_MSC_EP_BULKOUT: + HwEP = USBFS_EP2; + break; + case USBD_CDC_ACM_EP_INTIN: + HwEP = USBFS_EP3; + break; + case USBD_CDC_ACM_EP_BULKOUT: + HwEP = USBFS_EP4; + break; + case USBD_CDC_ACM_EP_BULKIN: + HwEP = USBFS_EP5; + break; + case USBD_HID_EP_INTIN: + HwEP = USBFS_EP6; + break; + case USBD_HID_EP_INTOUT: + HwEP = USBFS_EP7; + break; + default: + HwEP = EP_NOT_FOUND; + } + return HwEP; +} + +void USBFS_CDCClassRqst_Callback(void) +{ + USBFS_CDCClassRqst = __TRUE; + USBD_SignalHandler(); +} + +void USBFS_BUS_RESET_ISR_ExitCallback(void) +{ + USBFS_BUS_RESET = __TRUE; + USBD_SignalHandler(); +} + +void USBFS_EP_1_ISR_ExitCallback(void) +{ + IncEPReq(USBFS_EP1); + USBD_SignalHandler(); +} + +void USBFS_EP_2_ISR_ExitCallback(void) +{ + IncEPReq(USBFS_EP2); + USBD_SignalHandler(); +} + +void USBFS_EP_3_ISR_ExitCallback(void) +{ + IncEPReq(USBFS_EP3); + USBD_SignalHandler(); +} + +void USBFS_EP_4_ISR_ExitCallback(void) +{ + IncEPReq(USBFS_EP4); + USBD_SignalHandler(); +} + +void USBFS_EP_5_ISR_ExitCallback(void) +{ + IncEPReq(USBFS_EP5); + USBD_SignalHandler(); +} + +void USBFS_EP_6_ISR_ExitCallback(void) +{ + IncEPReq(USBFS_EP6); + USBD_SignalHandler(); +} + +void USBFS_EP_7_ISR_ExitCallback(void) +{ + IncEPReq(USBFS_EP7); + USBD_SignalHandler(); +} + +/******************************************************************************* +* CheckLine +******************************************************************************** +* Checks if CDC line was changed and if it was - adjusts UART speed +* +*******************************************************************************/ +void CheckLine(void) +{ + uint32_t dDTERate; + uint16_t wDivider; + + if (USBFS_IsLineChanged()) + { + /* Get Baud Rate */ + dDTERate = USBFS_GetDTERate(); + + /* Check for Baud Rate Upper Limit */ + if (dDTERate > 4000000) + { + dDTERate = 4000000; + } + + /* Check for Baud Rate Lower Limit */ + if (dDTERate < 1200) + { + dDTERate = 1200; + } + + /* Sets the required Clock divider for UART */ + switch (dDTERate) + { + case 4000000: + wDivider = DIVIDER4000000; + break; + case 3000000: + wDivider = DIVIDER3000000; + break; + case 2000000: + wDivider = DIVIDER2000000; + break; + case 1000000: + wDivider = DIVIDER1000000; + break; + case 921600: + wDivider = DIVIDER1000000; + break; + case 460800: + wDivider = DIVIDER500000; + break; + case 230400: + wDivider = DIVIDER250000; + break; + case 115200: + wDivider = DIVIDER115200; + break; + case 57600: + wDivider = DIVIDER57600; + break; + case 38400: + wDivider = DIVIDER38400; + break; + case 19200: + wDivider = DIVIDER19200; + break; + case 9600: + wDivider = DIVIDER9600; + break; + case 4800: + wDivider = DIVIDER4800; + break; + case 2400: + wDivider = DIVIDER2400; + break; + case 1200: + wDivider = DIVIDER1200; + break; + default: + wDivider = DIVIDER115200; + break; + } + + if ((Clock_UART_GetDividerRegister() + 1u) != wDivider) + { + /* Stop UART for new Clock */ + UART_Bridge_Stop(); + /* Select clock source (PLL) */ + if (wDivider != DIVIDER3000000) + { + if (Clock_UART_GetSourceRegister() != CYCLK_SRC_SEL_PLL) + { + Clock_UART_Stop(); + Clock_UART_SetSourceRegister(CYCLK_SRC_SEL_PLL); + Clock_UART_Start(); + } + } + else /* For 3 000 000 bps select a different clock source (IMO), it shall improve + * baud rate accuracy */ + { + if (Clock_UART_GetSourceRegister() != CYCLK_SRC_SEL_IMO) + { + Clock_UART_Stop(); + Clock_UART_SetSourceRegister(CYCLK_SRC_SEL_IMO); + Clock_UART_Start(); + } + } + + /* Set new Clock Frequency divider */ + Clock_UART_SetDivider(wDivider - 1u); + + /* Restart UART */ + + UART_Bridge_ClearRxBuffer(); + UART_Bridge_ClearTxBuffer(); + + USBD_CDC_ACM_Reset(); + + UART_Bridge_Start(); + + Pin_UART_Tx_SetDriveMode(Pin_UART_Tx_DM_STRONG); + } + } +} + +void USBD_Handler(void) +{ + bool rep; + + if (USBFS_BUS_RESET) + { + USBFS_BUS_RESET = __FALSE; + for (uint8 epNumber = 0u; epNumber < USBFS_MAX_EP; epNumber++) + { + USBFS_EP_Mask[epNumber] = 0; + } + /* Ensure USB device is fully enumerated prior to running code */ + while (!USBFS_GetConfiguration()) + ; + + USBD_DeviceStatus = USBFS_deviceStatus; + USBD_DeviceAddress = USBFS_deviceAddress; + USBD_Configuration = USBFS_configuration; + + USBFS_EnableOutEP(USBFS_EP2); +#if defined(DAPLINK_IF) + USBFS_EnableOutEP(USBFS_EP4); + USBFS_EnableOutEP(USBFS_EP7); +#endif + return; + } + if (USBFS_CDCClassRqst) + { + USBFS_CDCClassRqst = __FALSE; + if (break_req != 0) + { + USBD_CDC_ACM_SendBreak(break_value); + break_req = 0; + USBD_CDC_ACM_Reset(); + } + + CheckLine(); + + } + + do + { + rep = false; + for (uint8 epNumber = 1u; epNumber < USBFS_MAX_EP; epNumber++) + { + + // check for lost ISR + if (((USBFS_EP[epNumber].addr & USBFS_DIR_IN) == 0) + && (USBFS_EP_Mask[epNumber] == 0) + && (USBFS_EP[epNumber].apiEpState != USBFS_OUT_BUFFER_EMPTY)) + { + // ISR was lost + IncEPReq(epNumber); + } + if (USBFS_EP_Mask[epNumber] > 0) + { + switch (epNumber) + { + case USBFS_EP1: + USBD_MSC_EP_BULK_Event(USBD_EVT_IN); + break; + case USBFS_EP2: + USBD_MSC_EP_BULK_Event(USBD_EVT_OUT); + break; + case USBFS_EP3: + // todo + break; + case USBFS_EP4: + USBD_CDC_ACM_EP_BULK_Event(USBD_EVT_OUT); + break; + case USBFS_EP5: + USBD_CDC_ACM_EP_BULK_Event(USBD_EVT_IN); + break; + case USBFS_EP6: + USBD_HID_EP_INT_Event(USBD_EVT_IN); + break; + case USBFS_EP7: + USBD_HID_EP_INT_Event(USBD_EVT_OUT); + break; + } + DecEPReq(epNumber); + if (USBFS_EP_Mask[epNumber] > 0) + { + rep = true; + } + } + } + } while (rep); +} + +void USBD_ClrStallEP(U32 EPNum) +{ + U32 HwEP = FwEPToHwEP(EPNum); + if (HwEP == EP_NOT_FOUND) + { + return; + } + else + { + /* Clear the endpoint Halt */ + USBFS_EP[HwEP].hwEpState &= (uint8) ~USBFS_ENDPOINT_STATUS_HALT; + + /* Clear the data toggle */ + USBFS_EP[HwEP].epToggle = 0u; + + /* Clear toggle bit for already armed packet */ + USBFS_SIE_EP_BASE.sieEp[HwEP].epCnt0 &= + (uint8) ~(uint8) USBFS_EPX_CNT_DATA_TOGGLE; + + /* Return API State as it was defined before */ + USBFS_EP[HwEP].apiEpState &= (uint8) ~USBFS_NO_EVENT_ALLOWED; + + if ((USBFS_EP[HwEP].addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + if (USBFS_EP[HwEP].apiEpState == USBFS_IN_BUFFER_EMPTY) + { + /* Wait for next packet from application */ + USBFS_SIE_EP_BASE.sieEp[HwEP].epCr0 = USBFS_MODE_NAK_IN; + } + else /* Continue armed transfer */ + { + USBFS_SIE_EP_BASE.sieEp[HwEP].epCr0 = USBFS_MODE_ACK_IN; + } + } + else + { + /* OUT Endpoint */ + if (USBFS_EP[HwEP].apiEpState == USBFS_OUT_BUFFER_FULL) + { + /* Allow application to read full buffer */ + USBFS_SIE_EP_BASE.sieEp[HwEP].epCr0 = USBFS_MODE_NAK_OUT; + } + else /* Mark endpoint as empty, so it will be reloaded */ + { + USBFS_SIE_EP_BASE.sieEp[HwEP].epCr0 = USBFS_MODE_ACK_OUT; + } + } + } +} + +void USBD_ConfigEP(USB_ENDPOINT_DESCRIPTOR *pEPD) +{ + // not used +} + +void USBD_Configure(BOOL cfg) +{ + // not used +} + +void USBD_Connect(BOOL con) +{ + if (con) + { + /* Start USBFS Component based on power settings in DWR (5V in this case) */ + USBFS_Start(0, USBFS_DWR_VDDD_OPERATION); + /* Wait until device address is assigned */ + while (USBFS_deviceAddress == 0) + ; + /* Ensure USB device is fully enumerated prior to running code */ + while (USBFS_GetConfiguration() == 0) + ; + USBD_DeviceStatus = USBFS_deviceStatus; + USBD_DeviceAddress = USBFS_deviceAddress; + USBD_Configuration = USBFS_configuration; + + USBFS_EnableOutEP(USBFS_EP2); +#if defined(DAPLINK_IF) + USBFS_EnableOutEP(USBFS_EP4); + USBFS_EnableOutEP(USBFS_EP7); +#endif + } + else + { + USBFS_Stop(); + USBD_DeviceStatus = 0; + USBD_DeviceAddress = 0; + USBD_Configuration = 0; + USBD_EndPointMask = 0x00010001; + USBD_EndPointHalt = 0x00000000; + USBD_EndPointStall = 0x00000000; + //USBD_SignalHandler(); + } +} + +void USBD_DirCtrlEP(U32 dir) +{ + // not used +} + +void USBD_DisableEP(U32 EPNum) +{ + // not used +} + +void USBD_EnableEP(U32 EPNum) +{ + // not used +} + +void USBD_Init(void) +{ + USBFS_SerialNumString((uint8 *) info_get_unique_id_string_descriptor()); + USBFS_Init(); +} + +U32 USBD_ReadEP(U32 EPNum, U8 *pData, U32 cnt) +{ + U32 HwEP = FwEPToHwEP(EPNum); + if (HwEP == EP_NOT_FOUND) + { + return 0; + } + else + { + U32 res = USBFS_ReadOutEP(HwEP, pData, cnt); + // Reenable EP + USBFS_EnableOutEP(HwEP); + return res; + + } +} + +void USBD_ResetEP(U32 EPNum) +{ + // not used +} + +void USBD_SetAddress(U32 adr, U32 setup) +{ + // not used +} + +void USBD_SetStallEP(U32 EPNum) +{ + U32 HwEP = FwEPToHwEP(EPNum); + if (HwEP == EP_NOT_FOUND) + { + return; + } + else + { + /* Set the endpoint Halt */ + USBFS_EP[HwEP].hwEpState |= (USBFS_ENDPOINT_STATUS_HALT); + + /* Clear the data toggle */ + USBFS_EP[HwEP].epToggle = 0u; + USBFS_EP[HwEP].apiEpState |= USBFS_NO_EVENT_ALLOWED; + + if ((USBFS_EP[HwEP].addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + USBFS_SIE_EP_BASE.sieEp[HwEP].epCr0 = (USBFS_MODE_STALL_DATA_EP + | USBFS_MODE_ACK_IN); + } + else + { + /* OUT Endpoint */ + USBFS_SIE_EP_BASE.sieEp[HwEP].epCr0 = (USBFS_MODE_STALL_DATA_EP + | USBFS_MODE_ACK_OUT); + } + } +} + +void USBD_WakeUpCfg(BOOL cfg) +{ + // not used +} + +U32 USBD_WriteEP(U32 EPNum, U8 *pData, U32 cnt) +{ + U32 HwEP = FwEPToHwEP(EPNum); + if (HwEP == EP_NOT_FOUND) + { + return 0; + } + else + { + while (USBFS_GetEPState(HwEP) != USBFS_IN_BUFFER_EMPTY) + ; + USBFS_LoadInEP(HwEP, pData, cnt); + return cnt; + } +} + diff --git a/source/hic_hal/cypress/psoc5lp/usbd_PSoC5LP.h b/source/hic_hal/cypress/psoc5lp/usbd_PSoC5LP.h new file mode 100644 index 0000000000..2cba684401 --- /dev/null +++ b/source/hic_hal/cypress/psoc5lp/usbd_PSoC5LP.h @@ -0,0 +1,89 @@ +/******************************************************************************* +* @file usbd_PSoC5LP.h +* @brief This file contains the function prototypes and constants used in +* the usbd_PSoC5LP.c +* +******************************************************************************** +* Copyright (2019) Cypress Semiconductor Corporation +* or a subsidiary of Cypress Semiconductor Corporation. +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*****************************************************************************/ +#ifndef _USBD_PSOC5LP_H_ +#define _USBD_PSOC5LP_H_ /**< Symbol preventing repeated inclusion */ + +#include "cytypes.h" +#include "USBFS.h" +#include "main.h" + +#define USBFS_EP_1_ISR_EXIT_CALLBACK +#define USBFS_EP_2_ISR_EXIT_CALLBACK +#define USBFS_EP_3_ISR_EXIT_CALLBACK +#define USBFS_EP_4_ISR_EXIT_CALLBACK +#define USBFS_EP_5_ISR_EXIT_CALLBACK +#define USBFS_EP_6_ISR_EXIT_CALLBACK +#define USBFS_EP_7_ISR_EXIT_CALLBACK +#define USBFS_BUS_RESET_ISR_EXIT_CALLBACK + +#define USBFS_EP1_Mask (1u << 0) +#define USBFS_EP2_Mask (1u << 1) +#define USBFS_EP3_Mask (1u << 2) +#define USBFS_EP4_Mask (1u << 3) +#define USBFS_EP5_Mask (1u << 4) +#define USBFS_EP6_Mask (1u << 5) +#define USBFS_EP7_Mask (1u << 6) + +void USBFS_EP_1_ISR_ExitCallback(void); +void USBFS_EP_2_ISR_ExitCallback(void); +void USBFS_EP_3_ISR_ExitCallback(void); +void USBFS_EP_4_ISR_ExitCallback(void); +void USBFS_EP_5_ISR_ExitCallback(void); +void USBFS_EP_6_ISR_ExitCallback(void); +void USBFS_EP_7_ISR_ExitCallback(void); +void USBFS_BUS_RESET_ISR_ExitCallback(void); +void USBFS_CDCClassRqst_Callback(void); + +extern volatile uint16_t break_value; /* break handling variables */ +extern volatile uint8_t break_req; + +extern uint8_t *ptr_data_received; /*!< Pointer to the receive intermediate buffer to the received unread data */ +extern uint8_t *ptr_data_read; /*!< Pointer to the receive intermediate buffer to the received read data */ +extern int32_t data_to_send_wr; /*!< Number of bytes written to the send intermediate buffer */ +extern int32_t data_to_send_rd; /*!< Number of bytes read from the send intermediate buffer */ +extern int32_t data_send_active; /*!< Flag active while data is being sent */ +// Global state of usb +extern main_usb_connect_t usb_state; + +extern volatile bool SetLineCodingReq; + +/* UART Source Clock Frequency */ +#define SOURCECLK (64000000u) +#define SOURCECLK_IMO (24000000u) +/* Dividers for Baud Rates */ +#define DIVIDER4000000 SOURCECLK/(UART_Bridge_OVER_SAMPLE_COUNT * 4000000) +#define DIVIDER3000000 SOURCECLK_IMO/(UART_Bridge_OVER_SAMPLE_COUNT * 3000000) +#define DIVIDER2000000 SOURCECLK/(UART_Bridge_OVER_SAMPLE_COUNT * 2000000) +#define DIVIDER1000000 SOURCECLK/(UART_Bridge_OVER_SAMPLE_COUNT * 1000000) +#define DIVIDER500000 SOURCECLK/(UART_Bridge_OVER_SAMPLE_COUNT * 500000) +#define DIVIDER250000 SOURCECLK/(UART_Bridge_OVER_SAMPLE_COUNT * 250000) +#define DIVIDER115200 SOURCECLK/(UART_Bridge_OVER_SAMPLE_COUNT * 115200) +#define DIVIDER57600 SOURCECLK/(UART_Bridge_OVER_SAMPLE_COUNT * 57600) +#define DIVIDER38400 SOURCECLK/(UART_Bridge_OVER_SAMPLE_COUNT * 38400) +#define DIVIDER19200 SOURCECLK/(UART_Bridge_OVER_SAMPLE_COUNT * 19200) +#define DIVIDER9600 SOURCECLK/(UART_Bridge_OVER_SAMPLE_COUNT * 9600) +#define DIVIDER4800 SOURCECLK/(UART_Bridge_OVER_SAMPLE_COUNT * 4800) +#define DIVIDER2400 SOURCECLK/(UART_Bridge_OVER_SAMPLE_COUNT * 2400) +#define DIVIDER1200 SOURCECLK/(UART_Bridge_OVER_SAMPLE_COUNT * 1200) + + +#endif diff --git a/source/hic_hal/flash_blob.h b/source/hic_hal/flash_blob.h index 69ab8d9843..b21bb8f258 100644 --- a/source/hic_hal/flash_blob.h +++ b/source/hic_hal/flash_blob.h @@ -28,6 +28,12 @@ extern "C" { #endif +// Flags for program_target +enum { + kAlgoVerifyReturnsAddress = 1u, /*!< Verify function returns address if bit set */ + kAlgoSingleInitType = 1u << 1u, /*!< The init function ignores the function code. */ +}; + typedef struct { uint32_t breakpoint; uint32_t static_base; @@ -47,6 +53,7 @@ typedef struct { const uint32_t algo_size; const uint32_t *algo_blob; const uint32_t program_buffer_size; + const uint32_t algo_flags; /*!< Combination of kAlgoVerifyReturnsAddress and kAlgoSingleInitType */ } program_target_t; typedef struct { diff --git a/source/hic_hal/target_config.h b/source/hic_hal/target_config.h index 972ff9afa7..1180ba497e 100644 --- a/source/hic_hal/target_config.h +++ b/source/hic_hal/target_config.h @@ -18,7 +18,6 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - #ifndef TARGET_CONFIG_H #define TARGET_CONFIG_H @@ -41,7 +40,7 @@ extern "C" { #define TARGET_AUTO_INCREMENT_PAGE_SIZE (1024) //Additional flash and ram regions -#define MAX_EXTRA_FLASH_REGION 3 +#define MAX_EXTRA_FLASH_REGION 7 #define MAX_EXTRA_RAM_REGION 3 typedef struct flash_region_info { diff --git a/source/target/target_family.h b/source/target/target_family.h index 5932e79e50..101799b26b 100644 --- a/source/target/target_family.h +++ b/source/target/target_family.h @@ -37,6 +37,7 @@ enum _vendor_ids { kStub_VendorID = 0, kNXP_VendorID = 11, kTI_VendorID = 16, + kCypress_VendorID = 19, kNordic_VendorID = 54, kToshiba_VendorID = 92, kRenesas_VendorID = 117, @@ -60,6 +61,8 @@ typedef enum _family_id { kToshiba_Tz_FamilyID = VENDOR_TO_FAMILY(kToshiba_VendorID, 1), kWiznet_W7500_FamilyID = VENDOR_TO_FAMILY(kWiznet_VendorID, 1), kRenesas_FamilyID = VENDOR_TO_FAMILY(kRenesas_VendorID, 1), + kCypress_psoc6_FamilyID = VENDOR_TO_FAMILY(kCypress_VendorID, 1), + kCypress_psoc6s_FamilyID = VENDOR_TO_FAMILY(kCypress_VendorID, 2), } family_id_t; typedef struct target_family_descriptor { diff --git a/tools/build_release.bat b/tools/build_release.bat index 03b981f5d0..63b589e513 100644 --- a/tools/build_release.bat +++ b/tools/build_release.bat @@ -84,10 +84,14 @@ if not [%requirements_file%]==[] pip install -r %requirements_file% progen generate -t uvision -b -p kl26z_bl progen generate -t uvision -b -p k20dx_bl progen generate -t uvision -b -p sam3u2c_bl + rem progen generate -t uvision -p psoc5lp_cy8ckit_if + rem python tools/make_customapp.py projectfiles/uvision/psoc5lp_cy8ckit_if/build/psoc5lp_cy8ckit_if_crc.hex daplink.hex daplink.cyacd @REM build but continue if there are errors progen generate -t uvision -b @if !errorlevel! neq 0 exit /B !errorlevel! python tools/copy_release_files.py --project-tool uvision + rem move daplink.cyacd uvision_release\daplink.cyacd + rem move daplink.hex uvision_release\daplink.hex exit /B !errorlevel! ) diff --git a/tools/make_customapp.py b/tools/make_customapp.py new file mode 100644 index 0000000000..659b826bb9 --- /dev/null +++ b/tools/make_customapp.py @@ -0,0 +1,117 @@ +#!/usr/bin/python + +header_row = "2E1270690000" + +from intelhex import IntelHex + +import argparse + + +def main(input_file, output_hex_file, output_cyacd_file): + empty_row = {} + for i in range(0,256): + empty_row[i] = 0 + cyacd_row = {} + for i in range(0,294): + cyacd_row[i] = 0 + + daplink = IntelHex() + daplink.fromfile(input_file,format='hex') + daplink.start_addr = None + pydict = daplink.todict() + cy_meta_dict = {} + max_addr = max([ k for k in pydict.keys() if k <0x3FE00 ]) + image_start_addr = 0x00021800 + image_len = max_addr - image_start_addr + 1 + last_bl_row = 0x0217 + + for i in range(0x3FEC0, 0x3FF00): + cy_meta_dict[i] = 0 + + csum = 0 + for i in range(image_start_addr, image_start_addr+image_len): + csum += pydict[i] + if csum > 255: + csum %= 0x100 + + csum = (0x100-csum) % 0x100 + + cy_meta_dict[0x3FEC0] = csum + cy_meta_dict[0x3FEC1] = pydict[image_start_addr+4] + cy_meta_dict[0x3FEC2] = pydict[image_start_addr+5] + cy_meta_dict[0x3FEC3] = pydict[image_start_addr+6] + cy_meta_dict[0x3FEC4] = pydict[image_start_addr+7] + cy_meta_dict[0x3FEC5] = last_bl_row % 0x100 + cy_meta_dict[0x3FEC6] = last_bl_row // 0x100 + cy_meta_dict[0x3FEC9] = image_len % 0x100 + cy_meta_dict[0x3FECA] = (image_len // 0x100 ) % 0x100 + cy_meta_dict[0x3FECB] = (image_len // 0x10000 ) % 0x100 + cy_meta_dict[0x3FECC] = (image_len // 0x1000000 ) % 0x100 + + cy_meta = IntelHex() + cy_meta.fromdict(cy_meta_dict) + + daplink.merge(cy_meta, overlap='replace') + daplink.start_addr = None + +# save custom app hex + daplink.write_hex_file(output_hex_file) + +# make custom app cyacd + rows = {} + for i in range(0, 4): + rows[i] = {} + + for i in daplink.todict(): + if (not isinstance(i, int)) or (i < 0) or (i >= 0x40000): + continue + bank = i // 0x10000 + row = (i % 0x10000) // 0x100 + offset = i % 0x100 + if bank == 0 and row < 0x32: + continue + if row not in rows[bank]: + rows[bank][row] = empty_row.copy() + rows[bank][row][offset] = daplink[i] + + cyacd_file = open("daplink.cyacd", "w") + cyacd_file.write(header_row + '\n') + + for bank in rows: + for row in rows[bank]: + cyacd_row[0] = bank + cyacd_row[1] = row // 0x100 + cyacd_row[2] = row % 0x100 + cyacd_row[3] = 0x01 + cyacd_row[4] = 0x20 + for i in range(0, 0x100): + cyacd_row[i+5] = rows[bank][row][i] + csum = 0 + for i in range(0,293): + csum += cyacd_row[i] + if csum > 0xFF: + csum %= 0x100 + csum = 0x100-csum + if csum > 0xFF: + csum %= 0x100 + cyacd_row[293] = csum + + cyacd_str = ":" + + for i in range(0,294): + cyacd_str += format(cyacd_row[i], '02X') + cyacd_file.write(cyacd_str + '\n') + + + cyacd_file.close() + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description='HEX to second Custom app HEX and CYACD converter tool') + parser.add_argument("input", type=str, help="HEX source file.") + parser.add_argument("output_hex", type=str, help="Output base file name for HEX Custom app.") + parser.add_argument("output_cyacd", type=str, help="Output base file name for CYACD Custom app.") + + args = parser.parse_args() + + main(args.input, args.output_hex, args.output_cyacd) + \ No newline at end of file